From f44daa284a054ffa02603c13c7cea1659f85c4ba Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sun, 10 Jul 2022 00:34:42 +0200 Subject: [PATCH] legacy files deleted --- gbe2_ecp3/feeder.vhd | 620 -- gbe2_ecp3/ip_configurator.vhd | 342 - gbe2_ecp3/ipcores/debug_fifo_2kx16.vhd | 1965 ----- gbe2_ecp3/ipcores/fifo_16kx8.vhd | 2711 ------- gbe2_ecp3/ipcores/fifo_2048x8.lpc | 47 - gbe2_ecp3/ipcores/fifo_2048x8.srp | 42 - gbe2_ecp3/ipcores/fifo_2048x8.vhd | 1415 ---- gbe2_ecp3/ipcores/fifo_2048x8_generate.log | 46 - gbe2_ecp3/ipcores/fifo_2048x8_tmpl.vhd | 18 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb.jhd | 949 --- gbe2_ecp3/ipcores/fifo_32kx16x8_mb.lpc | 47 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb.naf | 98 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb.srp | 44 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb.sym | Bin 716 -> 0 bytes gbe2_ecp3/ipcores/fifo_32kx16x8_mb.vhd | 3997 ---------- gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.lpc | 47 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.srp | 44 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.vhd | 5224 ------------- .../ipcores/fifo_32kx16x8_mb2_generate.log | 48 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb2_tmpl.vhd | 26 - .../ipcores/fifo_32kx16x8_mb_generate.log | 46 - gbe2_ecp3/ipcores/fifo_32kx16x8_mb_tmpl.vhd | 26 - gbe2_ecp3/ipcores/fifo_4096x32.jhd | 479 -- gbe2_ecp3/ipcores/fifo_4096x32.lpc | 47 - gbe2_ecp3/ipcores/fifo_4096x32.naf | 72 - gbe2_ecp3/ipcores/fifo_4096x32.srp | 42 - gbe2_ecp3/ipcores/fifo_4096x32.sym | Bin 436 -> 0 bytes gbe2_ecp3/ipcores/fifo_4096x32.vhd | 1803 ----- gbe2_ecp3/ipcores/fifo_4096x32_generate.log | 46 - gbe2_ecp3/ipcores/fifo_4096x32_tmpl.vhd | 18 - gbe2_ecp3/ipcores/fifo_4096x9.jhd | 487 -- gbe2_ecp3/ipcores/fifo_4096x9.lpc | 47 - gbe2_ecp3/ipcores/fifo_4096x9.naf | 26 - gbe2_ecp3/ipcores/fifo_4096x9.srp | 43 - gbe2_ecp3/ipcores/fifo_4096x9.sym | Bin 432 -> 0 bytes gbe2_ecp3/ipcores/fifo_4096x9.vhd | 1624 ---- gbe2_ecp3/ipcores/fifo_4096x9_generate.log | 46 - gbe2_ecp3/ipcores/fifo_4096x9_tmpl.vhd | 18 - gbe2_ecp3/ipcores/fifo_512x32.lpc | 47 - gbe2_ecp3/ipcores/fifo_512x32.vhd | 1604 ---- gbe2_ecp3/ipcores/fifo_512x64.jhd | 359 - gbe2_ecp3/ipcores/fifo_512x64.lpc | 47 - gbe2_ecp3/ipcores/fifo_512x64.naf | 152 - gbe2_ecp3/ipcores/fifo_512x64.srp | 42 - gbe2_ecp3/ipcores/fifo_512x64.sym | Bin 434 -> 0 bytes gbe2_ecp3/ipcores/fifo_512x64.vhd | 1651 ---- gbe2_ecp3/ipcores/fifo_512x64_generate.log | 46 - gbe2_ecp3/ipcores/fifo_512x64_tmpl.vhd | 18 - gbe2_ecp3/ipcores/fifo_512x72.jhd | 359 - gbe2_ecp3/ipcores/fifo_512x72.lpc | 47 - gbe2_ecp3/ipcores/fifo_512x72.naf | 152 - gbe2_ecp3/ipcores/fifo_512x72.srp | 42 - gbe2_ecp3/ipcores/fifo_512x72.sym | Bin 434 -> 0 bytes gbe2_ecp3/ipcores/fifo_512x72.vhd | 1651 ---- gbe2_ecp3/ipcores/fifo_512x72_generate.log | 46 - gbe2_ecp3/ipcores/fifo_512x72_tmpl.vhd | 18 - gbe2_ecp3/ipcores/fifo_64kx8.jhd | 711 -- gbe2_ecp3/ipcores/fifo_64kx8.lpc | 47 - gbe2_ecp3/ipcores/fifo_64kx8.naf | 24 - gbe2_ecp3/ipcores/fifo_64kx8.srp | 43 - gbe2_ecp3/ipcores/fifo_64kx8.sym | Bin 432 -> 0 bytes gbe2_ecp3/ipcores/fifo_64kx8.vhd | 3355 -------- gbe2_ecp3/ipcores/fifo_64kx8_generate.log | 46 - gbe2_ecp3/ipcores/fifo_64kx8_tmpl.vhd | 18 - gbe2_ecp3/ipcores/fifo_64kx9.lpc | 47 - gbe2_ecp3/ipcores/fifo_64kx9.srp | 43 - gbe2_ecp3/ipcores/fifo_64kx9.vhd | 4582 ----------- gbe2_ecp3/ipcores/fifo_64kx9_generate.log | 48 - gbe2_ecp3/ipcores/fifo_64kx9_tmpl.vhd | 18 - gbe2_ecp3/ipcores/ip_mem.jhd | 9 - gbe2_ecp3/ipcores/ip_mem.lpc | 60 - gbe2_ecp3/ipcores/ip_mem.mem | 277 - gbe2_ecp3/ipcores/ip_mem.mem.bak | 277 - gbe2_ecp3/ipcores/ip_mem.naf | 152 - gbe2_ecp3/ipcores/ip_mem.srp | 29 - gbe2_ecp3/ipcores/ip_mem.vhd | 379 - gbe2_ecp3/ipcores/ip_mem_generate.log | 45 - gbe2_ecp3/ipcores/ip_mem_tmpl.vhd | 23 - gbe2_ecp3/ipcores/macInitDataInvWithMac.mem | 59 - gbe2_ecp3/ipcores/mac_init_mem.lpc | 48 - gbe2_ecp3/ipcores/mac_init_mem.srp | 29 - gbe2_ecp3/ipcores/mac_init_mem.vhd | 262 - gbe2_ecp3/ipcores/mac_init_mem_generate.log | 45 - gbe2_ecp3/ipcores/mac_init_mem_tmpl.vhd | 15 - gbe2_ecp3/ipcores/msg_file.log | 33 - gbe2_ecp3/ipcores/tb_fifo_2048x8_tmpl.vhd | 102 - .../ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd | 115 - gbe2_ecp3/ipcores/tb_fifo_32kx16x8_tmpl.vhd | 106 - gbe2_ecp3/ipcores/tb_fifo_4096x32_tmpl.vhd | 102 - gbe2_ecp3/ipcores/tb_fifo_4096x9_tmpl.vhd | 102 - gbe2_ecp3/ipcores/tb_fifo_512x64_tmpl.vhd | 102 - gbe2_ecp3/ipcores/tb_fifo_512x72_tmpl.vhd | 102 - gbe2_ecp3/ipcores/tb_fifo_64kx8_tmpl.vhd | 102 - gbe2_ecp3/ipcores/tb_ip_mem_tmpl.vhd | 174 - gbe2_ecp3/ipcores/tb_mac_init_mem_tmpl.vhd | 64 - gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd | 1965 ----- gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.jhd | 413 - gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.naf | 35 - gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.srp | 42 - gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.sym | Bin 438 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.vhd | 1366 ---- .../ipcores_ecp3/fifo_1024x16x8_generate.log | 48 - .../ipcores_ecp3/fifo_1024x16x8_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd | 2711 ------- gbe2_ecp3/ipcores_ecp3/fifo_2048x8.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8.jhd | 429 -- gbe2_ecp3/ipcores_ecp3/fifo_2048x8.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8.naf | 24 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8.srp | 42 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8.sym | Bin 432 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd | 1415 ---- .../ipcores_ecp3/fifo_2048x8_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.jhd | 413 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.naf | 35 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.srp | 42 - gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.sym | Bin 436 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd | 1367 ---- .../ipcores_ecp3/fifo_2048x8x16_generate.log | 48 - .../ipcores_ecp3/fifo_2048x8x16_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.jhd | 949 --- gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.naf | 98 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.srp | 44 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.sym | Bin 716 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd | 3997 ---------- gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.jhd | 1233 --- gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.naf | 101 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.srp | 44 - gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.sym | Bin 716 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd | 5224 ------------- .../fifo_32kx16x8_mb2_generate.log | 48 - .../ipcores_ecp3/fifo_32kx16x8_mb2_tmpl.vhd | 26 - .../fifo_32kx16x8_mb_generate.log | 48 - .../ipcores_ecp3/fifo_32kx16x8_mb_tmpl.vhd | 26 - gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd | 3400 -------- gbe2_ecp3/ipcores_ecp3/fifo_4096x32.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_4096x32.jhd | 479 -- gbe2_ecp3/ipcores_ecp3/fifo_4096x32.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_4096x32.naf | 72 - gbe2_ecp3/ipcores_ecp3/fifo_4096x32.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_4096x32.srp | 42 - gbe2_ecp3/ipcores_ecp3/fifo_4096x32.sym | Bin 436 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd | 1803 ----- .../ipcores_ecp3/fifo_4096x32_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_4096x32_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_4096x9.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_4096x9.jhd | 487 -- gbe2_ecp3/ipcores_ecp3/fifo_4096x9.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_4096x9.naf | 26 - gbe2_ecp3/ipcores_ecp3/fifo_4096x9.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_4096x9.srp | 43 - gbe2_ecp3/ipcores_ecp3/fifo_4096x9.sym | Bin 432 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd | 1624 ---- .../ipcores_ecp3/fifo_4096x9_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_4096x9_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd | 1573 ---- gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd | 1559 ---- gbe2_ecp3/ipcores_ecp3/fifo_512x32.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_512x32.jhd | 357 - gbe2_ecp3/ipcores_ecp3/fifo_512x32.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_512x32.naf | 72 - gbe2_ecp3/ipcores_ecp3/fifo_512x32.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_512x32.srp | 42 - gbe2_ecp3/ipcores_ecp3/fifo_512x32.sym | Bin 434 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd | 1193 --- .../ipcores_ecp3/fifo_512x32_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_512x32_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd | 1298 ---- gbe2_ecp3/ipcores_ecp3/fifo_512x64.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_512x64.jhd | 359 - gbe2_ecp3/ipcores_ecp3/fifo_512x64.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_512x64.naf | 152 - gbe2_ecp3/ipcores_ecp3/fifo_512x64.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_512x64.srp | 42 - gbe2_ecp3/ipcores_ecp3/fifo_512x64.sym | Bin 434 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_512x64.vhd | 1231 --- .../ipcores_ecp3/fifo_512x64_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_512x64_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_512x72.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_512x72.jhd | 359 - gbe2_ecp3/ipcores_ecp3/fifo_512x72.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_512x72.naf | 152 - gbe2_ecp3/ipcores_ecp3/fifo_512x72.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_512x72.srp | 42 - gbe2_ecp3/ipcores_ecp3/fifo_512x72.sym | Bin 434 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd | 1231 --- .../ipcores_ecp3/fifo_512x72_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_512x72_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_64kx8.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_64kx8.jhd | 711 -- gbe2_ecp3/ipcores_ecp3/fifo_64kx8.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_64kx8.naf | 24 - gbe2_ecp3/ipcores_ecp3/fifo_64kx8.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_64kx8.srp | 43 - gbe2_ecp3/ipcores_ecp3/fifo_64kx8.sym | Bin 432 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd | 3355 -------- .../ipcores_ecp3/fifo_64kx8_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_64kx8_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_64kx9.ipx | 9 - gbe2_ecp3/ipcores_ecp3/fifo_64kx9.jhd | 995 --- gbe2_ecp3/ipcores_ecp3/fifo_64kx9.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_64kx9.naf | 26 - gbe2_ecp3/ipcores_ecp3/fifo_64kx9.sort | 1 - gbe2_ecp3/ipcores_ecp3/fifo_64kx9.srp | 43 - gbe2_ecp3/ipcores_ecp3/fifo_64kx9.sym | Bin 432 -> 0 bytes gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd | 4582 ----------- .../ipcores_ecp3/fifo_64kx9_generate.log | 48 - gbe2_ecp3/ipcores_ecp3/fifo_64kx9_tmpl.vhd | 18 - gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.lpc | 47 - gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd | 4493 ----------- gbe2_ecp3/ipcores_ecp3/ip_mem.ipx | 10 - gbe2_ecp3/ipcores_ecp3/ip_mem.jhd | 9 - gbe2_ecp3/ipcores_ecp3/ip_mem.lpc | 60 - gbe2_ecp3/ipcores_ecp3/ip_mem.mem | 277 - gbe2_ecp3/ipcores_ecp3/ip_mem.mem.bak | 277 - gbe2_ecp3/ipcores_ecp3/ip_mem.naf | 152 - gbe2_ecp3/ipcores_ecp3/ip_mem.sort | 1 - gbe2_ecp3/ipcores_ecp3/ip_mem.srp | 29 - gbe2_ecp3/ipcores_ecp3/ip_mem.sym | Bin 588 -> 0 bytes gbe2_ecp3/ipcores_ecp3/ip_mem.vhd | 379 - gbe2_ecp3/ipcores_ecp3/ip_mem_generate.log | 47 - gbe2_ecp3/ipcores_ecp3/ip_mem_tmpl.vhd | 23 - .../ipcores_ecp3/macInitDataInvWithMac.mem | 59 - gbe2_ecp3/ipcores_ecp3/mac_init_mem.ipx | 10 - gbe2_ecp3/ipcores_ecp3/mac_init_mem.jhd | 7 - gbe2_ecp3/ipcores_ecp3/mac_init_mem.lpc | 48 - gbe2_ecp3/ipcores_ecp3/mac_init_mem.naf | 17 - gbe2_ecp3/ipcores_ecp3/mac_init_mem.sort | 1 - gbe2_ecp3/ipcores_ecp3/mac_init_mem.srp | 29 - gbe2_ecp3/ipcores_ecp3/mac_init_mem.sym | Bin 266 -> 0 bytes gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd | 262 - .../ipcores_ecp3/mac_init_mem_generate.log | 47 - gbe2_ecp3/ipcores_ecp3/mac_init_mem_tmpl.vhd | 15 - gbe2_ecp3/ipcores_ecp3/msg_file.log | 33 - gbe2_ecp3/ipcores_ecp3/serdes/msg_file.log | 13 - .../serdes/serdes_gbe_0_extclock_8b.jhd | 5 - .../serdes/serdes_gbe_0_extclock_8b.lpc | 140 - .../serdes/serdes_gbe_0_extclock_8b.naf | 49 - .../serdes/serdes_gbe_0_extclock_8b.pp | 95 - .../serdes/serdes_gbe_0_extclock_8b.readme | 141 - .../serdes/serdes_gbe_0_extclock_8b.sym | Bin 1626 -> 0 bytes .../serdes/serdes_gbe_0_extclock_8b.tft | 98 - .../serdes/serdes_gbe_0_extclock_8b.txt | 49 - .../serdes/serdes_gbe_0_extclock_8b.vhd | 2182 ------ .../serdes_gbe_0_extclock_8b_generate.log | 26 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.ipx | 11 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.jhd | 7 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.lpc | 258 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.naf | 48 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.pp | 191 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.readme | 141 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.sort | 1 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.sym | Bin 1580 -> 0 bytes gbe2_ecp3/ipcores_ecp3/serdes_ch4.tft | 100 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt | 59 - gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd | 2689 ------- .../ipcores_ecp3/serdes_ch4_generate.log | 29 - .../serdes_gbe_0ch/dummy_sym.sort | 1 - .../ipcores_ecp3/serdes_gbe_0ch/msg_file.log | 14 - .../serdes_gbe_0ch/serdes_gbe_0ch.ipx | 11 - .../serdes_gbe_0ch/serdes_gbe_0ch.jhd | 7 - .../serdes_gbe_0ch/serdes_gbe_0ch.lpc | 258 - .../serdes_gbe_0ch/serdes_gbe_0ch.naf | 48 - .../serdes_gbe_0ch/serdes_gbe_0ch.pp | 195 - .../serdes_gbe_0ch/serdes_gbe_0ch.readme | 141 - .../serdes_gbe_0ch/serdes_gbe_0ch.sort | 1 - .../serdes_gbe_0ch/serdes_gbe_0ch.sym | Bin 1584 -> 0 bytes .../serdes_gbe_0ch/serdes_gbe_0ch.tft | 100 - .../serdes_gbe_0ch/serdes_gbe_0ch.txt | 59 - .../serdes_gbe_0ch/serdes_gbe_0ch.vhd | 2689 ------- .../serdes_gbe_0ch_generate.log | 29 - .../ipcores_ecp3/serdes_intclk/dummy_sym.sort | 1 - .../ipcores_ecp3/serdes_intclk/msg_file.log | 14 - .../serdes_intclk/rx_reset_sm.naf | 7 - .../serdes_gbe_0_intclock_8b.ipx | 11 - .../serdes_gbe_0_intclock_8b.jhd | 7 - .../serdes_gbe_0_intclock_8b.lpc | 258 - .../serdes_gbe_0_intclock_8b.naf | 48 - .../serdes_intclk/serdes_gbe_0_intclock_8b.pp | 195 - .../serdes_gbe_0_intclock_8b.readme | 141 - .../serdes_gbe_0_intclock_8b.sort | 1 - .../serdes_gbe_0_intclock_8b.sym | Bin 1594 -> 0 bytes .../serdes_gbe_0_intclock_8b.tft | 100 - .../serdes_gbe_0_intclock_8b.txt | 59 - .../serdes_gbe_0_intclock_8b.vhd | 2689 ------- .../serdes_gbe_0_intclock_8b_ecp3.ipx | 11 - .../serdes_gbe_0_intclock_8b_ecp3.jhd | 13 - .../serdes_gbe_0_intclock_8b_ecp3.lpc | 258 - .../serdes_gbe_0_intclock_8b_ecp3.naf | 46 - .../serdes_gbe_0_intclock_8b_ecp3.pp | 195 - .../serdes_gbe_0_intclock_8b_ecp3.readme | 137 - .../serdes_gbe_0_intclock_8b_ecp3.sort | 1 - .../serdes_gbe_0_intclock_8b_ecp3.sym | Bin 1506 -> 0 bytes .../serdes_gbe_0_intclock_8b_ecp3.tft | 100 - .../serdes_gbe_0_intclock_8b_ecp3.txt | 59 - .../serdes_gbe_0_intclock_8b_ecp3.vhd | 3117 -------- .../serdes_gbe_0_intclock_8b_ecp3.vhd~ | 3113 -------- ...serdes_gbe_0_intclock_8b_ecp3_generate.log | 29 - .../serdes_gbe_0_intclock_8b_generate.log | 29 - .../serdes_intclk/tx_reset_sm.naf | 5 - .../serdes_intclk_ecp2m50/msg_file.log | 14 - .../serdes_gbe_0_intclock_8b.jhd | 5 - .../serdes_gbe_0_intclock_8b.lpc | 145 - .../serdes_gbe_0_intclock_8b.naf | 48 - .../serdes_gbe_0_intclock_8b.pp | 119 - .../serdes_gbe_0_intclock_8b.readme | 139 - .../serdes_gbe_0_intclock_8b.tft | 98 - .../serdes_gbe_0_intclock_8b.txt | 49 - .../serdes_gbe_0_intclock_8b.vhd | 2202 ------ .../serdes_gbe_0_intclock_8b_generate.log | 27 - .../ipcores_ecp3/sgmii33/rate_resolution.v | 66 - .../sgmii33/register_interface_hb.v | 918 --- .../sgmii33/reset_controller_cdr.v | 219 - .../sgmii33/reset_controller_pcs.v | 226 - .../ipcores_ecp3/sgmii33/sgmii_channel_smi.v | 237 - .../ipcores_ecp3/sgmii_gbe_pcs32/dummy.sty | 1 - .../sgmii_gbe_pcs32/generate_core.tcl | 39 - .../pmi_fifo_dcLEan71301616161010.ngo | Bin 35501 -> 0 bytes .../sgmii_gbe_pcs32/sgmii_gbe_pcs32.cmd | 14 - .../sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc | 26 - .../sgmii_gbe_pcs32/sgmii_gbe_pcs32.ngo | Bin 377069 -> 0 bytes .../sgmii_gbe_pcs32/sgmii_gbe_pcs32_bb.v | 127 - .../sgmii_gbe_pcs32/sgmii_gbe_pcs32_beh.v | 5165 ------------- .../sgmii_gbe_pcs32/sgmii_gbe_pcs32_gen.log | 4 - .../sgmii_gbe_pcs32_generate.log | 10 - .../sgmii_gbe_pcs32/sgmii_gbe_pcs32_inst.v | 69 - .../sgmii_gbe_pcs32/sgmii_gbe_pcs32_wrapper.v | 233 - .../sgmii_gbe_pcs32/sgmii_pcs_eval.tar | Bin 1116188 -> 0 bytes .../ipcores_ecp3/sgmii_gbe_pcs32/stdout.log | 42 - .../sgmii_gbe_pcs34/generate_core.tcl | 43 - .../sgmii_gbe_pcs34/sgmii_gbe_pcs34.ipx | 10 - .../sgmii_gbe_pcs34/sgmii_gbe_pcs34.lpc | 26 - .../sgmii_gbe_pcs34/sgmii_gbe_pcs34.ngo | Bin 389472 -> 0 bytes .../sgmii_gbe_pcs34/sgmii_gbe_pcs34_bb.v | 143 - .../sgmii_gbe_pcs34/sgmii_gbe_pcs34_beh.v | 5440 ------------- .../sgmii_gbe_pcs34_filelist.log | 52 - .../sgmii_gbe_pcs34/sgmii_gbe_pcs34_gen.log | 10 - .../sgmii_gbe_pcs34_generate.log | 76 - .../sgmii_gbe_pcs34/sgmii_gbe_pcs34_inst.v | 79 - .../sgmii_gbe_pcs35/generate_core.tcl | 43 - .../sgmii_gbe_pcs35/sgmii_gbe_pcs35.ipx | 10 - .../sgmii_gbe_pcs35/sgmii_gbe_pcs35.lpc | 26 - .../sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo | Bin 389045 -> 0 bytes .../sgmii_gbe_pcs35/sgmii_gbe_pcs35_bb.v | 143 - .../sgmii_gbe_pcs35/sgmii_gbe_pcs35_beh.v | 3372 -------- .../sgmii_gbe_pcs35_filelist.log | 52 - .../sgmii_gbe_pcs35/sgmii_gbe_pcs35_gen.log | 10 - .../sgmii_gbe_pcs35_generate.log | 76 - .../sgmii_gbe_pcs35/sgmii_gbe_pcs35_inst.v | 79 - gbe2_ecp3/ipcores_ecp3/statts_mem.ipx | 10 - gbe2_ecp3/ipcores_ecp3/statts_mem.jhd | 7 - gbe2_ecp3/ipcores_ecp3/statts_mem.lpc | 53 - gbe2_ecp3/ipcores_ecp3/statts_mem.naf | 64 - gbe2_ecp3/ipcores_ecp3/statts_mem.sort | 1 - gbe2_ecp3/ipcores_ecp3/statts_mem.srp | 28 - gbe2_ecp3/ipcores_ecp3/statts_mem.sym | Bin 442 -> 0 bytes gbe2_ecp3/ipcores_ecp3/statts_mem.vhd | 159 - .../ipcores_ecp3/statts_mem_generate.log | 46 - gbe2_ecp3/ipcores_ecp3/statts_mem_tmpl.vhd | 19 - .../ipcores_ecp3/tb_fifo_1024x16x8_tmpl.vhd | 102 - .../ipcores_ecp3/tb_fifo_2048x8_tmpl.vhd | 102 - .../ipcores_ecp3/tb_fifo_2048x8x16_tmpl.vhd | 102 - .../tb_fifo_32kx16x8_mb2_tmpl.vhd | 115 - .../ipcores_ecp3/tb_fifo_32kx16x8_mb_tmpl.vhd | 115 - .../ipcores_ecp3/tb_fifo_32kx16x8_tmpl.vhd | 106 - .../ipcores_ecp3/tb_fifo_4096x32_tmpl.vhd | 102 - .../ipcores_ecp3/tb_fifo_4096x9_tmpl.vhd | 102 - .../ipcores_ecp3/tb_fifo_512x32_tmpl.vhd | 102 - .../ipcores_ecp3/tb_fifo_512x64_tmpl.vhd | 102 - .../ipcores_ecp3/tb_fifo_512x72_tmpl.vhd | 102 - gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx8_tmpl.vhd | 102 - gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx9_tmpl.vhd | 102 - gbe2_ecp3/ipcores_ecp3/tb_ip_mem_tmpl.vhd | 174 - .../ipcores_ecp3/tb_mac_init_mem_tmpl.vhd | 64 - gbe2_ecp3/ipcores_ecp3/tb_statts_mem_tmpl.vhd | 124 - .../ipcores_ecp3/tsmac3/generate_core.tcl | 39 - gbe2_ecp3/ipcores_ecp3/tsmac3/orcapp_head | 4 - .../pmi_ram_dpEbnonessdn208256208256.ngo | Bin 11279 -> 0 bytes .../tsmac3/pmi_ram_dpEbnonessdn96649664.ngo | Bin 8760 -> 0 bytes gbe2_ecp3/ipcores_ecp3/tsmac3/ts_mac_eval.tar | Bin 368640 -> 0 bytes gbe2_ecp3/ipcores_ecp3/tsmac3/tsmac3.lpc | 38 - gbe2_ecp3/ipcores_ecp3/tsmac3/tsmac3.ngo | Bin 866982 -> 0 bytes gbe2_ecp3/ipcores_ecp3/tsmac3/tsmac3.v | 211 - gbe2_ecp3/ipcores_ecp3/tsmac3/tsmac3_bb.v | 145 - gbe2_ecp3/ipcores_ecp3/tsmac3/tsmac3_beh.v | 5840 -------------- gbe2_ecp3/ipcores_ecp3/tsmac3/tsmac3_gen.log | 8 - .../ipcores_ecp3/tsmac3/tsmac3_generate.log | 10 - gbe2_ecp3/ipcores_ecp3/tsmac3/tsmac3_inst.v | 77 - .../ipcores_ecp3/tsmac34/generate_core.tcl | 43 - .../pmi_ram_dpEbnonessdn208256208256.ngo | Bin 11243 -> 0 bytes .../tsmac34/pmi_ram_dpEbnonessdn96649664.ngo | Bin 8808 -> 0 bytes gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34.ipx | 12 - gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34.lpc | 38 - gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34.ngo | Bin 814689 -> 0 bytes gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34.v | 211 - gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_bb.v | 145 - gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_beh.v | 5840 -------------- .../ipcores_ecp3/tsmac34/tsmac34_filelist.log | 46 - .../ipcores_ecp3/tsmac34/tsmac34_gen.log | 10 - .../ipcores_ecp3/tsmac34/tsmac34_generate.log | 126 - gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_inst.v | 77 - .../ipcores_ecp3/tsmac35/generate_core.tcl | 43 - .../pmi_ram_dpEbnonessdn208256208256.ngo | Bin 11243 -> 0 bytes .../tsmac35/pmi_ram_dpEbnonessdn96649664.ngo | Bin 8808 -> 0 bytes gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.ipx | 12 - gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.lpc | 38 - gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.ngo | Bin 818583 -> 0 bytes gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.v | 211 - gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35_bb.v | 145 - gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35_beh.v | 5845 -------------- .../ipcores_ecp3/tsmac35/tsmac35_filelist.log | 46 - .../ipcores_ecp3/tsmac35/tsmac35_gen.log | 10 - .../ipcores_ecp3/tsmac35/tsmac35_generate.log | 126 - gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35_inst.v | 77 - gbe2_ecp3/mb_mac_sim.vhd | 331 - gbe2_ecp3/slv_mac_memory.vhd | 178 - gbe2_ecp3/slv_register.vhd | 177 - gbe2_ecp3/tb_feeder.vhd | 300 - gbe2_ecp3/tb_frame_receiver.vhd | 2686 ------- gbe2_ecp3/tb_gbe_buf.vhd | 946 --- gbe2_ecp3/tb_ip_configurator.vhd | 145 - gbe2_ecp3/tb_ipu2gbe.vhd | 428 - gbe2_ecp3/tb_ipu2gbe_NEW.vhd | 428 - gbe2_ecp3/tb_ipu2gbe_OLD.vhd | 428 - gbe2_ecp3/tb_lsm.vhd | 113 - gbe2_ecp3/tb_pc.vhd | 310 - gbe2_ecp3/tb_slv_mac_memory.vhd | 114 - gbe2_ecp3/trb_net16_gbe_buf.vhd | 1617 ---- gbe2_ecp3/trb_net16_gbe_event_constr.vhd | 701 -- gbe2_ecp3/trb_net16_gbe_frame_constr.vhd | 630 -- gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd | 756 -- gbe2_ecp3/trb_net16_gbe_frame_trans.vhd | 226 - .../trb_net16_gbe_ipu2gbe_simple_sender.vhd | 1508 ---- gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd | 878 --- gbe2_ecp3/trb_net16_gbe_mac_control.vhd | 223 - gbe2_ecp3/trb_net16_gbe_main_control.vhd | 957 --- gbe2_ecp3/trb_net16_gbe_packet_constr.vhd | 1088 --- .../trb_net16_gbe_packet_constr_20101006.vhd | 958 --- .../trb_net16_gbe_packet_constr_nologic.vhd | 1099 --- ..._net16_gbe_packet_constr_simple_sender.vhd | 1182 --- .../trb_net16_gbe_protocol_prioritizer.vhd | 87 - gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd | 690 -- gbe2_ecp3/trb_net16_gbe_receive_control.vhd | 256 - ...trb_net16_gbe_response_constructor_ARP.vhd | 418 - ...rb_net16_gbe_response_constructor_DHCP.vhd | 818 -- ...net16_gbe_response_constructor_Forward.vhd | 235 - ...rb_net16_gbe_response_constructor_Ping.vhd | 424 - ...b_net16_gbe_response_constructor_SCTRL.vhd | 820 -- ...rb_net16_gbe_response_constructor_Stat.vhd | 336 - ...rb_net16_gbe_response_constructor_Test.vhd | 235 - ...b_net16_gbe_response_constructor_Test1.vhd | 160 - ...b_net16_gbe_response_constructor_Trash.vhd | 163 - ...16_gbe_response_constructor_TrbNetData.vhd | 600 -- gbe2_ecp3/trb_net16_gbe_setup.vhd | 403 - gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd | 597 -- gbe2_ecp3/trb_net16_gbe_transmit_control.vhd | 135 - gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd | 311 - gbe2_ecp3/trb_net16_gbe_type_validator.vhd | 141 - gbe2_ecp3/trb_net16_ipu2gbe.vhd | 1430 ---- gbe2_ecp3/trb_net16_ipu2gbe_20101006.vhd | 1316 ---- gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd | 1403 ---- gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd | 236 - gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd | 890 --- gbe2_ecp3/trb_net_gbe_components.vhd | 1360 ---- gbe2_ecp3/trb_net_gbe_protocols.vhd | 627 -- gbe_ecp2m/feeder.vhd | 620 -- gbe_ecp2m/ip_configurator.vhd | 342 - gbe_ecp2m/ipcores/.cvsignore | 6 - gbe_ecp2m/ipcores/debug_fifo_2kx16.vhd | 1965 ----- gbe_ecp2m/ipcores/fifo_1024x16x8.lpc | 47 - gbe_ecp2m/ipcores/fifo_1024x16x8.vhd | 1366 ---- gbe_ecp2m/ipcores/fifo_1024x16x8_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_16kx8.vhd | 2711 ------- gbe_ecp2m/ipcores/fifo_2048x8.lpc | 47 - gbe_ecp2m/ipcores/fifo_2048x8.vhd | 1913 ----- gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_2048x8x16.lpc | 47 - gbe_ecp2m/ipcores/fifo_2048x8x16.vhd | 1367 ---- gbe_ecp2m/ipcores/fifo_2048x8x16_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc | 47 - gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd | 5245 ------------- gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.ipx | 9 - gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc | 50 - gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp | 44 - gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd | 6859 ----------------- .../ipcores/fifo_32kx16x8_mb2_generate.log | 48 - gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd | 26 - gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd | 26 - gbe_ecp2m/ipcores/fifo_4096x32.lpc | 47 - gbe_ecp2m/ipcores/fifo_4096x32.vhd | 2415 ------ gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_4096x9.lpc | 47 - gbe_ecp2m/ipcores/fifo_4096x9.vhd | 2171 ------ gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_512x32.lpc | 47 - gbe_ecp2m/ipcores/fifo_512x32.vhd | 1193 --- gbe_ecp2m/ipcores/fifo_512x32_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_512x64.lpc | 47 - gbe_ecp2m/ipcores/fifo_512x64.vhd | 1231 --- gbe_ecp2m/ipcores/fifo_512x64_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_512x72.lpc | 47 - gbe_ecp2m/ipcores/fifo_512x72.vhd | 1231 --- gbe_ecp2m/ipcores/fifo_512x72_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_64kx8.lpc | 47 - gbe_ecp2m/ipcores/fifo_64kx8.vhd | 4435 ----------- gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd | 18 - gbe_ecp2m/ipcores/fifo_64kx9.ipx | 9 - gbe_ecp2m/ipcores/fifo_64kx9.lpc | 50 - gbe_ecp2m/ipcores/fifo_64kx9.srp | 43 - gbe_ecp2m/ipcores/fifo_64kx9.vhd | 6025 --------------- gbe_ecp2m/ipcores/fifo_64kx9_generate.log | 48 - gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd | 18 - gbe_ecp2m/ipcores/ip_mem.lpc | 57 - gbe_ecp2m/ipcores/ip_mem.mem | 277 - gbe_ecp2m/ipcores/ip_mem.vhd | 606 -- gbe_ecp2m/ipcores/ip_mem_tmpl.vhd | 23 - gbe_ecp2m/ipcores/macInitDataInvWithMac.mem | 59 - gbe_ecp2m/ipcores/mac_init_mem.lpc | 45 - gbe_ecp2m/ipcores/mac_init_mem.vhd | 413 - gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd | 15 - gbe_ecp2m/ipcores/serdes/.cvsignore | 9 - .../serdes/serdes_gbe_0_extclock_8b.lpc | 140 - .../serdes/serdes_gbe_0_extclock_8b.txt | 49 - .../serdes/serdes_gbe_0_extclock_8b.vhd | 2182 ------ gbe_ecp2m/ipcores/serdes_ch4.ipx | 11 - gbe_ecp2m/ipcores/serdes_ch4.jhd | 7 - gbe_ecp2m/ipcores/serdes_ch4.lpc | 258 - gbe_ecp2m/ipcores/serdes_ch4.naf | 48 - gbe_ecp2m/ipcores/serdes_ch4.pp | 191 - gbe_ecp2m/ipcores/serdes_ch4.readme | 141 - gbe_ecp2m/ipcores/serdes_ch4.sort | 1 - gbe_ecp2m/ipcores/serdes_ch4.sym | Bin 1580 -> 0 bytes gbe_ecp2m/ipcores/serdes_ch4.tft | 100 - gbe_ecp2m/ipcores/serdes_ch4.txt | 59 - gbe_ecp2m/ipcores/serdes_ch4.vhd | 2689 ------- gbe_ecp2m/ipcores/serdes_ch4_generate.log | 29 - .../serdes_gbe_0_intclock_8b.lpc | 140 - .../serdes_gbe_0_intclock_8b.txt | 49 - .../serdes_gbe_0_intclock_8b.vhd | 2183 ------ .../serdes_gbe_0_intclock_8b.lpc | 145 - .../serdes_gbe_0_intclock_8b.txt | 49 - .../serdes_gbe_0_intclock_8b.vhd | 2202 ------ gbe_ecp2m/ipcores/sgmii_gbe_pcs32/.cvsignore | 11 - .../pmi_fifo_dcLEan71301616161010.ngo | Bin 35501 -> 0 bytes .../sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc | 26 - .../sgmii_gbe_pcs32/sgmii_gbe_pcs32.ngo | Bin 377069 -> 0 bytes .../sgmii_gbe_pcs32/sgmii_pcs_eval.tar | Bin 1116160 -> 0 bytes gbe_ecp2m/ipcores/statts_mem.lpc | 53 - gbe_ecp2m/ipcores/statts_mem.vhd | 159 - gbe_ecp2m/ipcores/statts_mem_tmpl.vhd | 19 - gbe_ecp2m/ipcores/tb_fifo_1024x16x8_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_2048x8x16_tmpl.vhd | 102 - .../ipcores/tb_fifo_32kx16x8_mb2_tmpl.vhd | 119 - .../ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd | 115 - gbe_ecp2m/ipcores/tb_fifo_32kx16x8_tmpl.vhd | 106 - gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_512x32_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_512x64_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_512x72_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd | 102 - gbe_ecp2m/ipcores/tb_fifo_64kx9_tmpl.vhd | 106 - gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd | 174 - gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd | 64 - gbe_ecp2m/ipcores/tb_statts_mem_tmpl.vhd | 124 - gbe_ecp2m/ipcores/tsmac3/.cvsignore | 9 - .../pmi_ram_dpEbnonessdn208256208256.ngo | Bin 11279 -> 0 bytes .../tsmac3/pmi_ram_dpEbnonessdn96649664.ngo | Bin 8760 -> 0 bytes gbe_ecp2m/ipcores/tsmac3/ts_mac_eval.tar | Bin 368640 -> 0 bytes gbe_ecp2m/ipcores/tsmac3/tsmac3.lpc | 38 - gbe_ecp2m/ipcores/tsmac3/tsmac3.ngo | Bin 866982 -> 0 bytes gbe_ecp2m/mb_mac_sim.vhd | 331 - gbe_ecp2m/slv_mac_memory.vhd | 178 - gbe_ecp2m/slv_register.vhd | 177 - gbe_ecp2m/tb_feeder.vhd | 300 - gbe_ecp2m/tb_gbe_buf.vhd | 561 -- gbe_ecp2m/tb_ip_configurator.vhd | 145 - gbe_ecp2m/tb_ipu2gbe.vhd | 428 - gbe_ecp2m/tb_lsm.vhd | 113 - gbe_ecp2m/tb_pc.vhd | 310 - gbe_ecp2m/tb_slv_mac_memory.vhd | 114 - gbe_ecp2m/trb_net16_gbe_buf.vhd | 1281 --- gbe_ecp2m/trb_net16_gbe_frame_constr.vhd | 562 -- gbe_ecp2m/trb_net16_gbe_frame_trans.vhd | 588 -- gbe_ecp2m/trb_net16_gbe_packet_constr.vhd | 1045 --- gbe_ecp2m/trb_net16_gbe_setup.vhd | 445 -- gbe_ecp2m/trb_net16_ipu2gbe.vhd | 1435 ---- gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd | 236 - gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd | 457 -- gbe_ecp2m/trb_net_gbe_components.vhd | 309 - gbe_trb/base/trb_net16_gbe_mac_control.vhd | 10 +- gbe_trb_ecp3/base/forwarder.vhd | 82 - gbe_trb_ecp3/base/gather_ports.vhd | 176 - gbe_trb_ecp3/base/gbe_lsm.vhd | 137 - gbe_trb_ecp3/base/gbe_med_fifo.vhd | 39 +- gbe_trb_ecp3/base/gbe_med_raw.vhd | 8 +- gbe_trb_ecp3/base/rx_rb.vhd | 289 - gbe_trb_ecp3/base/scatter_ports.vhd | 97 - gbe_trb_ecp3/base/tx_fifo.vhd | 155 - oldfiles/L12TrigBusInterface.vhd | 213 - oldfiles/bus_handler.vhd | 293 - oldfiles/bus_handler_oepb.vhd | 264 - oldfiles/etrax_interface.vhd | 274 - oldfiles/rom_16x8.vhd | 47 - oldfiles/serdes_sync_0/serdes_sync_0.vhd | 435 -- .../serdes_sync_0/serdes_sync_0_softlogic.v | 2003 ----- oldfiles/serdes_test/ecp2m_link_fifo.vhd | 1992 ----- oldfiles/serdes_test/etrax_interfacev2.vhd | 490 -- oldfiles/serdes_test/f_divider.vhd | 174 - .../serdes_test/flexi_PCS_channel_synch.vhd | 539 -- oldfiles/serdes_test/flexi_PCS_fifo_EBR.vhd | 180 - oldfiles/serdes_test/flexi_PCS_synch.vhd | 90 - oldfiles/serdes_test/hub.vhd | 1076 --- oldfiles/serdes_test/link_test.vhd | 326 - oldfiles/serdes_test/pcs_for_ecp2m.txt | 49 - oldfiles/serdes_test/pcs_for_ecp2m.vhd | 2185 ------ oldfiles/serdes_test/rich.vhd | 350 - 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optical_link/trbv2_tlk_api_fifo.ngc delete mode 100644 optical_link/trbv2_tlk_api_fifo.vhd diff --git a/gbe2_ecp3/feeder.vhd b/gbe2_ecp3/feeder.vhd deleted file mode 100755 index 57fb2c2..0000000 --- a/gbe2_ecp3/feeder.vhd +++ /dev/null @@ -1,620 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity feeder is -port( CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- PacketConstructor interface - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - -- Debug - BSM_SAVE_OUT : out std_logic_vector(3 downto 0); - BSM_LOAD_OUT : out std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : out std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : out std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : out std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : out std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : out std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : out std_logic; - DBG_SF_WR_EN_OUT : out std_logic; - DBG_SF_EMPTY_OUT : out std_logic; - DBG_SF_FULL_OUT : out std_logic; - DBG_SF_AFULL_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end entity; - -architecture feeder of feeder is - -component fifo_32kx16x8_mb -port( Data : in std_logic_vector(15 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic - ); -end component; - -type saveStates is (SIDLE, WAIT_FOR_DATA, SAVE_DATA, TERMINATE, SCLOSE); -signal saveCurrentState, saveNextState : saveStates; -signal state : std_logic_vector(3 downto 0); -signal data_req_comb : std_logic; -signal data_req : std_logic; -- request data signal, will be used for fee_read generation -signal rst_saved_ctr_comb : std_logic; -signal rst_saved_ctr : std_logic; - -signal fee_read_comb : std_logic; -signal fee_read : std_logic; -- fee_read signal -signal saved_ctr : std_logic_vector(16 downto 0); -signal ce_saved_ctr : std_logic; - --- header data -signal cts_rnd : std_logic_vector(15 downto 0); -signal cts_rnd_saved : std_logic; -signal cts_trg : std_logic_vector(15 downto 0); -signal cts_trg_saved : std_logic; -signal cts_len : std_logic_vector(16 downto 0); -signal cts_len_saved : std_logic; - --- CTS interface -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal cts_length : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_data : std_logic_vector(31 downto 0); - --- Split FIFO signals -signal sf_data : std_logic_vector(15 downto 0); -signal sf_wr_en_comb : std_logic; -signal sf_wr_en : std_logic; -- write signal for FIFO -signal sf_rd_en : std_logic; -signal sf_wcnt : std_logic_vector(15 downto 0); -signal sf_rcnt : std_logic_vector(16 downto 0); -signal sf_empty : std_logic; -signal sf_full : std_logic; -signal sf_afull : std_logic; - -------------------------------------------------------------------- -type loadStates is (LIDLE, INIT, REMOVE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, WAIT_PC, CLOSE); -signal loadCurrentState, loadNextState : loadStates; -signal state2 : std_logic_vector(3 downto 0); - -signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data -signal rst_rem_ctr_comb : std_logic; -signal rst_rem_ctr : std_logic; -signal rst_regs_comb : std_logic; -signal rst_regs : std_logic; -signal ce_rem_ctr_comb : std_logic; -signal ce_rem_ctr : std_logic; -signal remove_done_comb : std_logic; -signal remove_done : std_logic; -- end of header stripping process -signal load_done_comb : std_logic; -signal load_done : std_logic; -- end of data transfer into PC -signal calc_pad_comb : std_logic; -signal calc_pad : std_logic; -- add padding bytes, if needed -signal read_data_comb : std_logic; -signal read_data : std_logic; -- fetch data from split fifo -signal data_phase_comb : std_logic; -signal data_phase : std_logic; -- data transport phase from split fifo to PC -signal pc_sos_comb : std_logic; -signal pc_sos : std_logic; -- start of data signal -signal pc_eod_comb : std_logic; -signal pc_eod : std_logic; -- end of data signal -signal pad_data_comb : std_logic; -signal pad_data : std_logic; -- insert padding bytes - -signal pc_data : std_logic_vector(7 downto 0); -signal pc_data_q : std_logic_vector(7 downto 0); -signal pc_trig_nr : std_logic_vector(15 downto 0); -signal pc_sub_size : std_logic_vector(17 downto 0); -signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo -signal padding_needed : std_logic; -signal pc_wr_en_q : std_logic; -signal pc_wr_en_qq : std_logic; -signal pc_eod_q : std_logic; - -signal debug : std_logic_vector(31 downto 0); - -begin - --- CTS interface signals -cts_error_pattern <= (others => '0'); -- FAKE -cts_dataready <= '1'; -- FAKE - -cts_length <= x"0000"; -- length of data payload is always 0 -cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' - -cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; - - --- Sync all critical pathes -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - sf_data <= FEE_DATA_IN; - sf_wr_en <= sf_wr_en_comb; - fee_read <= fee_read_comb; - load_done <= load_done_comb; - pc_eod_q <= pc_eod; - pc_wr_en_qq <= pc_wr_en_q; - pc_wr_en_q <= data_phase; - end if; -end process THE_SYNC_PROC; - --- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY -fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) - else '0'; - --- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY -sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) - else '0'; - --- Counter for header word storage -THE_CTS_SAVED_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - saved_ctr <= (others => '0'); - elsif( ce_saved_ctr = '1' ) then - saved_ctr <= saved_ctr + 1; - end if; - end if; -end process THE_CTS_SAVED_CTR; - -ce_saved_ctr <= sf_wr_en; - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -saveMachineProc: process( CLK ) -begin - if rising_edge(CLK) then - if RESET = '1' then - saveCurrentState <= SIDLE; - data_req <= '0'; - rst_saved_ctr <= '0'; - else - saveCurrentState <= saveNextState; - data_req <= data_req_comb; - rst_saved_ctr <= rst_saved_ctr_comb; - end if; - end if; -end process saveMachineProc; - -saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN ) -begin - saveNextState <= SIDLE; - data_req_comb <= '0'; - rst_saved_ctr_comb <= '0'; - case saveCurrentState is - when SIDLE => - state <= x"0"; - if (CTS_START_READOUT_IN = '1') then - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - rst_saved_ctr_comb <= '1'; - else - saveNextState <= SIDLE; - end if; - when WAIT_FOR_DATA => - state <= x"1"; - if (FEE_BUSY_IN = '1') then - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - else - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - end if; - when SAVE_DATA => - state <= x"2"; - if (FEE_BUSY_IN = '0') then - saveNextState <= TERMINATE; - else - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - end if; - when TERMINATE => - state <= x"3"; - if (CTS_READ_IN = '1') then - saveNextState <= SCLOSE; - else - saveNextState <= TERMINATE; - end if; - when SCLOSE => - state <= x"4"; - if (CTS_START_READOUT_IN = '0') then - saveNextState <= SIDLE; - else - saveNextState <= SCLOSE; - end if; - when others => - state <= x"f"; - saveNextState <= SIDLE; - end case; -end process saveMachine; - --- save triggerRnd from incoming data for cts response -CTS_RND_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_rnd <= (others => '0'); - cts_rnd_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then - cts_rnd <= sf_data; - cts_rnd_saved <= '1'; - end if; - end if; -end process CTS_RND_PROC; - --- save triggerNr from incoming data for cts response -CTS_TRG_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_trg <= (others => '0'); - cts_trg_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then - cts_trg <= sf_data; - cts_trg_saved <= '1'; - end if; - end if; -end process CTS_TRG_PROC; - --- save size from incoming data for cts response (future) and to get rid of padding -CTS_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_len <= (others => '0'); - cts_len_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then - cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words - elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then - cts_len <= cts_len + x"4"; - cts_len_saved <= '1'; - end if; - end if; -end process CTS_SIZE_PROC; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Split FIFO -THE_SPLIT_FIFO: fifo_32kx16x8_mb -port map( Data => sf_data, - WrClock => CLK, - RdClock => CLK, - WrEn => sf_wr_en, - RdEn => sf_rd_en, - Reset => RESET, - RPReset => RESET, - AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 - Q => pc_data, --open, - WCNT => sf_wcnt, - RCNT => sf_rcnt, - Empty => sf_empty, - Full => sf_full, - AlmostFull => sf_afull - ); - -sf_rd_en <= read_data; ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- FIFO data delay process (also forces padding bytes to known value) -THE_DATA_DELAY_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( pad_data = '1' ) then - pc_data_q <= x"ee"; - else - pc_data_q <= pc_data; - end if; - end if; -end process THE_DATA_DELAY_PROC; - --- Statemachine for reading the data payload from the SPLIT_FIFO and feeding --- it into the packet constructor -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if RESET = '1' then - loadCurrentState <= LIDLE; - rst_regs <= '0'; - rst_rem_ctr <= '0'; - ce_rem_ctr <= '0'; - calc_pad <= '0'; - read_data <= '0'; - data_phase <= '0'; - pc_sos <= '0'; - pc_eod <= '0'; - pad_data <= '0'; - else - loadCurrentState <= loadNextState; - rst_regs <= rst_regs_comb; - rst_rem_ctr <= rst_rem_ctr_comb; - ce_rem_ctr <= ce_rem_ctr_comb; - calc_pad <= calc_pad_comb; - read_data <= read_data_comb; - data_phase <= data_phase_comb; - pc_sos <= pc_sos_comb; - pc_eod <= pc_eod_comb; - pad_data <= pad_data_comb; - end if; - end if; -end process loadMachineProc; - -loadMachine : process( loadCurrentState, sf_empty, remove_done, load_done, padding_needed, PC_READY_IN ) -begin - loadNextState <= LIDLE; - rst_regs_comb <= '0'; - rst_rem_ctr_comb <= '0'; - ce_rem_ctr_comb <= '0'; - calc_pad_comb <= '0'; - read_data_comb <= '0'; - data_phase_comb <= '0'; - pc_sos_comb <= '0'; - pc_eod_comb <= '0'; - pad_data_comb <= '0'; - case loadCurrentState is - when LIDLE => - state2 <= x"0"; - if( (sf_empty = '0') and (PC_READY_IN = '1') ) then - loadNextState <= INIT; - rst_regs_comb <= '1'; - rst_rem_ctr_comb <= '1'; - else - loadNextState <= LIDLE; - end if; - when INIT => - state2 <= x"1"; - loadNextState <= REMOVE; - ce_rem_ctr_comb <= '1'; - read_data_comb <= '1'; - when REMOVE => - state2 <= x"2"; - if( remove_done = '1' ) then - loadNextState <= CALCA; - calc_pad_comb <= '1'; - else - loadNextState <= REMOVE; - ce_rem_ctr_comb <= '1'; - read_data_comb <= '1'; - end if; - when CALCA => - state2 <= x"3"; - loadNextState <= CALCB; - when CALCB => - -- we need a branch in case of length "0"!!!! - state2 <= x"4"; - loadNextState <= LOAD; - read_data_comb <= '1'; - data_phase_comb <= '1'; - pc_sos_comb <= '1'; - when LOAD => - state2 <= x"5"; - if ( (load_done = '1') and (padding_needed = '0') ) then - loadNextState <= CLOSE; - elsif( (load_done = '1') and (padding_needed = '1') ) then - loadNextState <= PAD0; - data_phase_comb <= '1'; - else - loadNextState <= LOAD; - read_data_comb <= '1'; - data_phase_comb <= '1'; - end if; - when PAD0 => - state2 <= x"5"; - loadNextState <= PAD1; - data_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD1 => - state2 <= x"6"; - loadNextState <= PAD2; - data_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD2 => - state2 <= x"7"; - loadNextState <= PAD3; - data_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD3 => - state2 <= x"8"; - loadNextState <= CLOSE; - pad_data_comb <= '1'; - when CLOSE => - state2 <= x"9"; - loadNextState <= WAIT_PC; - pc_eod_comb <= '1'; - when WAIT_PC => - state2 <= x"a"; - if( PC_READY_IN = '1' ) then - loadNextState <= LIDLE; - rst_rem_ctr_comb <= '1'; - rst_regs_comb <= '1'; - else - loadNextState <= WAIT_PC; - end if; - when others => - state2 <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- Counter for stripping the unneeded parts of the data stream, and saving the important parts -THE_REMOVE_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - rem_ctr <= (others => '0'); - elsif( ce_rem_ctr = '1' ) then - rem_ctr <= rem_ctr + 1; - end if; - end if; -end process THE_REMOVE_CTR; - -remove_done_comb <= '1' when ( rem_ctr = x"6" ) else '0'; - -THE_REM_DONE_SYNC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - remove_done <= '0'; - else - remove_done <= remove_done_comb; - end if; - end if; -end process THE_REM_DONE_SYNC; - --- extract the trigger number from splitfifo data -THE_TRG_NR_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_trig_nr <= (others => '0'); - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"3") ) then - pc_trig_nr(7 downto 0) <= pc_data; - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"4") ) then - pc_trig_nr(15 downto 8) <= pc_data; - end if; - end if; -end process THE_TRG_NR_PROC; - --- check for padding -THE_PADDING_NEEDED_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - padding_needed <= '0'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then - padding_needed <= '1'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then - padding_needed <= '0'; - end if; - end if; -end process THE_PADDING_NEEDED_PROC; - --- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, --- and in case of padding needed increase it accordingly -THE_SUB_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_sub_size <= (others => '0'); - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then - pc_sub_size(9 downto 2) <= pc_data; - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then - pc_sub_size(17 downto 10) <= pc_data; - elsif( (calc_pad = '1') and (padding_needed = '1') ) then - pc_sub_size <= pc_sub_size + 4; - end if; - end if; -end process THE_SUB_SIZE_PROC; - --- number of bytes to read from split fifo -THE_READ_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - read_size <= (others => '0'); - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then - read_size(9 downto 2) <= pc_data; - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then - read_size(17 downto 10) <= pc_data; - elsif( ((calc_pad = '1') and (load_done = '0')) ) then - read_size <= read_size - 2; - elsif( ((read_data = '1') and (data_phase = '1')) ) then - read_size <= read_size - 1; - end if; - end if; -end process THE_READ_SIZE_PROC; - -load_done_comb <= '1' when (read_size = 0) else '0'; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Debug signals -debug(31) <= remove_done; -debug(30) <= load_done; -debug(29) <= ce_rem_ctr; -debug(28) <= rst_rem_ctr; -debug(27) <= rst_regs; -debug(26) <= data_phase; -debug(25) <= read_data; -debug(24) <= pad_data; -debug(23 downto 18) <= (others => '0'); -debug(17 downto 0) <= read_size; - --- Outputs -FEE_READ_OUT <= fee_read; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; -CTS_DATA_OUT <= cts_data; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_LENGTH_OUT <= cts_length; - -PC_SOS_OUT <= pc_sos; -PC_EOD_OUT <= pc_eod_q; -PC_DATA_OUT <= pc_data_q; -PC_WR_EN_OUT <= pc_wr_en_qq; -PC_TRIG_NR_OUT <= x"0000" & pc_trig_nr; -PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; -PC_PADDING_OUT <= padding_needed; - -BSM_SAVE_OUT <= state; -BSM_LOAD_OUT <= state2; -DBG_CTS_CTR_OUT <= saved_ctr(2 downto 0); -DBG_REM_CTR_OUT <= rem_ctr; -DBG_SF_DATA_OUT <= sf_data; -DBG_SF_WCNT_OUT <= sf_wcnt; -DBG_SF_RCNT_OUT <= sf_rcnt; -DBG_SF_RD_EN_OUT <= sf_rd_en; -DBG_SF_WR_EN_OUT <= sf_wr_en; -DBG_SF_EMPTY_OUT <= sf_empty; -DBG_SF_FULL_OUT <= sf_full; -DBG_SF_AFULL_OUT <= sf_afull; - -DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/ip_configurator.vhd b/gbe2_ecp3/ip_configurator.vhd deleted file mode 100755 index d6b0778..0000000 --- a/gbe2_ecp3/ip_configurator.vhd +++ /dev/null @@ -1,342 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity ip_configurator is -port( - CLK : in std_logic; - RESET : in std_logic; - -- configuration interface - START_CONFIG_IN : in std_logic; -- start configuration run - BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank - CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used - MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for - MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory - MEM_CLK_OUT : out std_logic; -- clock for BlockRAM - -- information for IP cores - DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address - DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address - DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port - SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address - SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address - SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port - MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) - -- Debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end entity; - -architecture ip_configurator of ip_configurator is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of ip_configurator : architecture is "GBE_conf_group"; - -type STATES is (IDLE, LOAD_REG, DELAY0, DELAY1, DELAY2, LOAD_DONE); -signal CURRENT_STATE, NEXT_STATE : STATES; -signal bsm : std_logic_vector(3 downto 0); -signal ce_ctr_comb : std_logic; -signal ce_ctr : std_logic; -signal rst_ctr_comb : std_logic; -signal rst_ctr : std_logic; -signal cfg_done_comb : std_logic; -signal cfg_done : std_logic; - -signal ctr_done_comb : std_logic; -signal ctr_done : std_logic; - -signal wr_select_comb : std_logic_vector(15 downto 0); -signal wr_select : std_logic_vector(15 downto 0); -signal wr_select_q : std_logic_vector(15 downto 0); - -signal addr_ctr : std_logic_vector(3 downto 0); -signal dest_mac : std_logic_vector(47 downto 0); -signal dest_ip : std_logic_vector(31 downto 0); -signal dest_udp : std_logic_vector(15 downto 0); -signal src_mac : std_logic_vector(47 downto 0); -signal src_ip : std_logic_vector(31 downto 0); -signal src_udp : std_logic_vector(15 downto 0); -signal mtu : std_logic_vector(15 downto 0); - -signal debug : std_logic_vector(31 downto 0); - -begin - - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -STATE_MACHINE_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if RESET = '1' then - CURRENT_STATE <= IDLE; - ce_ctr <= '0'; - rst_ctr <= '0'; - cfg_done <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - ce_ctr <= ce_ctr_comb; - rst_ctr <= rst_ctr_comb; - cfg_done <= cfg_done_comb; - end if; - end if; -end process STATE_MACHINE_PROC; - -STATE_MACHINE_TRANS: process( CURRENT_STATE, START_CONFIG_IN, ctr_done ) -begin - NEXT_STATE <= IDLE; - ce_ctr_comb <= '0'; - rst_ctr_comb <= '0'; - cfg_done_comb <= '0'; - case CURRENT_STATE is - when IDLE => - bsm <= x"0"; - if( START_CONFIG_IN = '1' ) then - NEXT_STATE <= LOAD_REG; - ce_ctr_comb <= '1'; - else - NEXT_STATE <= IDLE; - end if; - when LOAD_REG => - bsm <= x"1"; - if( ctr_done = '1' ) then - NEXT_STATE <= DELAY0; - rst_ctr_comb <= '1'; - else - NEXT_STATE <= LOAD_REG; - ce_ctr_comb <= '1'; - end if; - when DELAY0 => - bsm <= x"2"; - NEXT_STATE <= DELAY1; - when DELAY1 => - bsm <= x"3"; - NEXT_STATE <= DELAY2; - when DELAY2 => - bsm <= x"4"; - NEXT_STATE <= LOAD_DONE; - cfg_done_comb <= '1'; - when LOAD_DONE => - bsm <= x"2"; - if( START_CONFIG_IN = '0' ) then - NEXT_STATE <= IDLE; - else - NEXT_STATE <= LOAD_DONE; - cfg_done_comb <= '1'; - end if; - when others => - bsm <= x"f"; - NEXT_STATE <= IDLE; - end case; -end process STATE_MACHINE_TRANS; - --- address counter -THE_ADDR_CTR_PROC: process( CLK ) -begin - if ( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_ctr = '1') ) then - addr_ctr <= (others => '0'); - elsif( ce_ctr = '1' ) then - addr_ctr <= addr_ctr + 1; - end if; - end if; -end process THE_ADDR_CTR_PROC; - -ctr_done_comb <= '1' when (addr_ctr = x"e") else '0'; - -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - ctr_done <= ctr_done_comb; - wr_select_q <= wr_select; - wr_select <= wr_select_comb; - end if; -end process THE_SYNC_PROC; - --- generate combinatorial write select signals, register and delay the (output registers in EBR!) -wr_select_comb(0) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"0") ) else '0'; -- dest MAC low -wr_select_comb(1) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"1") ) else '0'; -- dest MAC high -wr_select_comb(2) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"2") ) else '0'; -- dest IP -wr_select_comb(3) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"3") ) else '0'; -- dest port -wr_select_comb(4) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"4") ) else '0'; -- src MAC low -wr_select_comb(5) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"5") ) else '0'; -- src MAC high -wr_select_comb(6) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"6") ) else '0'; -- src IP -wr_select_comb(7) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"7") ) else '0'; -- src port -wr_select_comb(8) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"8") ) else '0'; -- MTU -wr_select_comb(9) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"9") ) else '0'; -wr_select_comb(10) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"a") ) else '0'; -wr_select_comb(11) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"b") ) else '0'; -wr_select_comb(12) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"c") ) else '0'; -wr_select_comb(13) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"d") ) else '0'; -wr_select_comb(14) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"e") ) else '0'; -wr_select_comb(15) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"f") ) else '0'; - --- destination MAC low register -THE_D_MAC_LOW_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_mac(31 downto 0) <= (others => '0'); - elsif( wr_select_q(0) = '1') then - dest_mac(31 downto 0) <= mem_data_in; - end if; - end if; -end process THE_D_MAC_LOW_PROC; - --- destination MAC high register -THE_D_MAC_HIGH_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_mac(47 downto 32) <= (others => '0'); - elsif( wr_select_q(1) = '1') then - dest_mac(47 downto 32) <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_D_MAC_HIGH_PROC; - --- destination IP register -THE_D_IP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_ip <= (others => '0'); - elsif( wr_select_q(2) = '1') then - dest_ip <= mem_data_in; - end if; - end if; -end process THE_D_IP_PROC; - --- destination PORT register -THE_D_PORT_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_udp <= (others => '0'); - elsif( wr_select_q(3) = '1') then - dest_udp <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_D_PORT_PROC; - --- source MAC low register -THE_S_MAC_LOW_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_mac(31 downto 0) <= (others => '0'); - elsif( wr_select_q(4) = '1') then - src_mac(31 downto 0) <= mem_data_in; - end if; - end if; -end process THE_S_MAC_LOW_PROC; - --- source MAC high register -THE_S_MAC_HIGH_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_mac(47 downto 32) <= (others => '0'); - elsif( wr_select_q(5) = '1') then - src_mac(47 downto 32) <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_S_MAC_HIGH_PROC; - --- source IP register -THE_S_IP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_ip <= (others => '0'); - elsif( wr_select_q(6) = '1') then - src_ip <= mem_data_in; - end if; - end if; -end process THE_S_IP_PROC; - --- source PORT register -THE_S_PORT_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_udp <= (others => '0'); - elsif( wr_select_q(7) = '1') then - src_udp <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_S_PORT_PROC; - --- MTU size register -THE_MTU_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - mtu <= (others => '0'); - elsif( wr_select_q(8) = '1') then - mtu <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_MTU_PROC; - - --- Debug signals -debug(31 downto 12) <= (others => '0'); -debug(11 downto 8) <= addr_ctr; -debug(7) <= '0'; -debug(6) <= ctr_done; -debug(5) <= ce_ctr; -debug(4) <= rst_ctr; -debug(3 downto 0) <= bsm; --- Outputs -MEM_ADDR_OUT(7 downto 4) <= BANK_SELECT_IN; -MEM_ADDR_OUT(3 downto 0) <= addr_ctr; -MEM_CLK_OUT <= CLK; -CONFIG_DONE_OUT <= cfg_done; - --- destination MAC address - swap for user convinience -DEST_MAC_OUT(47 downto 40) <= dest_mac(7 downto 0); -DEST_MAC_OUT(39 downto 32) <= dest_mac(15 downto 8); -DEST_MAC_OUT(31 downto 24) <= dest_mac(23 downto 16); -DEST_MAC_OUT(23 downto 16) <= dest_mac(31 downto 24); -DEST_MAC_OUT(15 downto 8) <= dest_mac(39 downto 32); -DEST_MAC_OUT(7 downto 0) <= dest_mac(47 downto 40); - --- destination IP address - swap for user convinience -DEST_IP_OUT(31 downto 24) <= dest_ip(7 downto 0); -DEST_IP_OUT(23 downto 16) <= dest_ip(15 downto 8); -DEST_IP_OUT(15 downto 8) <= dest_ip(23 downto 16); -DEST_IP_OUT(7 downto 0) <= dest_ip(31 downto 24); - --- destination port address - swap for user convinience -DEST_UDP_OUT(15 downto 8) <= dest_udp(7 downto 0); -DEST_UDP_OUT(7 downto 0) <= dest_udp(15 downto 8); - --- source MAC address - swap for user convinience -SRC_MAC_OUT(47 downto 40) <= src_mac(7 downto 0); -SRC_MAC_OUT(39 downto 32) <= src_mac(15 downto 8); -SRC_MAC_OUT(31 downto 24) <= src_mac(23 downto 16); -SRC_MAC_OUT(23 downto 16) <= src_mac(31 downto 24); -SRC_MAC_OUT(15 downto 8) <= src_mac(39 downto 32); -SRC_MAC_OUT(7 downto 0) <= src_mac(47 downto 40); - --- source IP address - swap for user convinience -SRC_IP_OUT(31 downto 24) <= src_ip(7 downto 0); -SRC_IP_OUT(23 downto 16) <= src_ip(15 downto 8); -SRC_IP_OUT(15 downto 8) <= src_ip(23 downto 16); -SRC_IP_OUT(7 downto 0) <= src_ip(31 downto 24); - --- source port address - swap for user convinience -SRC_UDP_OUT(15 downto 8) <= src_udp(7 downto 0); -SRC_UDP_OUT(7 downto 0) <= src_udp(15 downto 8); - --- DO NOT SWAP! -MTU_OUT <= mtu; - -DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/ipcores/debug_fifo_2kx16.vhd b/gbe2_ecp3/ipcores/debug_fifo_2kx16.vhd deleted file mode 100644 index e10ee86..0000000 --- a/gbe2_ecp3/ipcores/debug_fifo_2kx16.vhd +++ /dev/null @@ -1,1965 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 16 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e - --- Wed Jul 21 14:35:10 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity debug_fifo_2kx16 is - port ( - Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(15 downto 0); - Empty: out std_logic; - Full: out std_logic); -end debug_fifo_2kx16; - -architecture Structure of debug_fifo_2kx16 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "debug_fifo_2kx16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "debug_fifo_2kx16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_1_0 : label is "9"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t24: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t23: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t22: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t21: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t20: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t19: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t18: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t17: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t16: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t15: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t14: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t13: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t12: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t11: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), - DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_1_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), - DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), - DIA6=>Data(15), DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, - ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, - ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, - ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, - CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9), - DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13), - DOB5=>Q(14), DOB6=>Q(15), DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_121: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of debug_fifo_2kx16 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_16kx8.vhd b/gbe2_ecp3/ipcores/fifo_16kx8.vhd deleted file mode 100644 index 12a3160..0000000 --- a/gbe2_ecp3/ipcores/fifo_16kx8.vhd +++ /dev/null @@ -1,2711 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.4 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 8 -depth 16384 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Mon Dec 6 19:08:10 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_16kx8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_16kx8; - -architecture Structure of fifo_16kx8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal co7: std_logic; - signal wcount_14: std_logic; - signal co6: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal co7_1: std_logic; - signal rcount_14: std_logic; - signal co6_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal wcount_r13: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal rcount_w13: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "1"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t30: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t29: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t28: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t27: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t26: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t25: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t24: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t23: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t22: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t21: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t20: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t19: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t18: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t17: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t16: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t15: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t14: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t13: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t12: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t11: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t10: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t9: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t8: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t7: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t6: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t5: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t4: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t3: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t2: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t1: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t0: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>w_gcount_r214, - DO0=>w_g2b_xor_cluster_0); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>w_gcount_r210, - DO0=>w_g2b_xor_cluster_1); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, - DO0=>w_g2b_xor_cluster_2); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_1); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r0); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>r_gcount_w214, - DO0=>r_g2b_xor_cluster_0); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>r_gcount_w210, - DO0=>r_g2b_xor_cluster_1); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_2); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w13); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_151: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_135: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_134: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_133: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_132: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_106: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7, - NC0=>iwcount_14, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1, - NC0=>ircount_14, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>w_g2b_xor_cluster_0, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>wcount_r13, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co6_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>rcount_w13, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co6_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_16kx8 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_2048x8.lpc b/gbe2_ecp3/ipcores/fifo_2048x8.lpc deleted file mode 100755 index 7c0b6de..0000000 --- a/gbe2_ecp3/ipcores/fifo_2048x8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_2048x8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:58 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=2048 -Width=8 -RDepth=2048 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_2048x8.srp b/gbe2_ecp3/ipcores/fifo_2048x8.srp deleted file mode 100755 index 4cbac58..0000000 --- a/gbe2_ecp3/ipcores/fifo_2048x8.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version ispLever_v72_SP2_Build (23) -Sat Dec 26 00:12:59 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_2048x8 - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_2048x8.vhd - VHDL template : fifo_2048x8_tmpl.vhd - VHDL testbench : tb_fifo_2048x8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_2048x8.srp - Element Usage : - AGEB2 : 12 - AND2 : 2 - CU2 : 12 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 70 - FD1S3BX : 1 - FD1S3DX : 49 - INV : 2 - OR2 : 1 - ROM16X1 : 32 - XOR2 : 22 - DP16KB : 1 - Estimated Resource Usage: - LUT : 117 - EBR : 1 - Reg : 122 diff --git a/gbe2_ecp3/ipcores/fifo_2048x8.vhd b/gbe2_ecp3/ipcores/fifo_2048x8.vhd deleted file mode 100755 index 82dac9a..0000000 --- a/gbe2_ecp3/ipcores/fifo_2048x8.vhd +++ /dev/null @@ -1,1415 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:23:58 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_2048x8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_2048x8; - -architecture Structure of fifo_2048x8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t24: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t23: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t22: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t21: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t20: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t19: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t18: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t17: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t16: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t15: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t14: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t13: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t12: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t11: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), - DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_121: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_120: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_119: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_118: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_117: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_116: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_115: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_114: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_113: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_112: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_111: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_110: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_108: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_107: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_106: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_105: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_104: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_103: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_102: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_101: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_100: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_99: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_98: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_96: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_95: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_94: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_93: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_92: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_91: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_89: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_88: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_87: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_86: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_84: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_83: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_82: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_81: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_80: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_79: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_78: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_77: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_76: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_75: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_74: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_73: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_72: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_71: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_70: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_69: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_68: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_67: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_66: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_65: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_64: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_63: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_62: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_61: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_60: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_59: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_58: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_57: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_56: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_55: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_54: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_53: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_51: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_50: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_49: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_48: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_47: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_46: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_45: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_44: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_43: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_42: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_41: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_40: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_39: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_38: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_37: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_36: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_35: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_34: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_33: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_32: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_31: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_30: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_29: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_28: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_27: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_26: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_25: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_15: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_14: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_13: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_2048x8 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_2048x8_generate.log b/gbe2_ecp3/ipcores/fifo_2048x8_generate.log deleted file mode 100755 index a00a11d..0000000 --- a/gbe2_ecp3/ipcores/fifo_2048x8_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v72_SP2_Build (23) -Sat Dec 26 00:12:59 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_2048x8 - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_2048x8.vhd - VHDL template : fifo_2048x8_tmpl.vhd - VHDL testbench : tb_fifo_2048x8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_2048x8.srp - Estimated Resource Usage: - LUT : 117 - EBR : 1 - Reg : 122 - -END SCUBA Module Synthesis - -File: fifo_2048x8.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_2048x8_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_2048x8_tmpl.vhd deleted file mode 100755 index 1a3333f..0000000 --- a/gbe2_ecp3/ipcores/fifo_2048x8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:58 2011 - --- parameterized module component declaration -component fifo_2048x8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_2048x8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.jhd b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.jhd deleted file mode 100755 index 4503e3e..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.jhd +++ /dev/null @@ -1,949 +0,0 @@ -MODULE fifo_32kx16x8_mb DEFIN fifo_32kx16x8_mb.vhd - SUBMODULE FADD2B - INSTANCE a3 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE af_d_cmp_7 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_6 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_5 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_4 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_3 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_2 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_1 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_0 - SUBMODULE FADD2B - INSTANCE af_d_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a2 - SUBMODULE AGEB2 - INSTANCE ae_cmp_8 - SUBMODULE AGEB2 - INSTANCE ae_cmp_7 - SUBMODULE AGEB2 - INSTANCE ae_cmp_6 - SUBMODULE AGEB2 - INSTANCE ae_cmp_5 - SUBMODULE AGEB2 - INSTANCE ae_cmp_4 - SUBMODULE AGEB2 - INSTANCE ae_cmp_3 - SUBMODULE AGEB2 - INSTANCE ae_cmp_2 - SUBMODULE AGEB2 - INSTANCE ae_cmp_1 - SUBMODULE AGEB2 - INSTANCE ae_cmp_0 - SUBMODULE FADD2B - INSTANCE ae_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE AGEB2 - INSTANCE full_cmp_7 - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_8 - SUBMODULE AGEB2 - INSTANCE empty_cmp_7 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE FADD2B - INSTANCE rfilld - SUBMODULE FSUB2B - INSTANCE rfill_8 - SUBMODULE FSUB2B - INSTANCE rfill_7 - SUBMODULE FSUB2B - INSTANCE rfill_6 - SUBMODULE FSUB2B - INSTANCE rfill_5 - SUBMODULE FSUB2B - INSTANCE rfill_4 - SUBMODULE FSUB2B - INSTANCE rfill_3 - SUBMODULE FSUB2B - INSTANCE rfill_2 - SUBMODULE FSUB2B - INSTANCE rfill_1 - SUBMODULE FSUB2B - INSTANCE rfill_0 - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE FSUB2B - INSTANCE wfill_8 - SUBMODULE FSUB2B - INSTANCE wfill_7 - SUBMODULE FSUB2B - INSTANCE wfill_6 - SUBMODULE FSUB2B - INSTANCE wfill_5 - SUBMODULE FSUB2B - INSTANCE wfill_4 - SUBMODULE FSUB2B - INSTANCE wfill_3 - SUBMODULE FSUB2B - INSTANCE wfill_2 - SUBMODULE FSUB2B - INSTANCE wfill_1 - SUBMODULE FSUB2B - INSTANCE wfill_0 - SUBMODULE FADD2B - INSTANCE rcntd - SUBMODULE FSUB2B - INSTANCE rcnt_8 - SUBMODULE FSUB2B - INSTANCE rcnt_7 - SUBMODULE FSUB2B - INSTANCE rcnt_6 - SUBMODULE FSUB2B - INSTANCE rcnt_5 - SUBMODULE FSUB2B - INSTANCE rcnt_4 - SUBMODULE FSUB2B - INSTANCE rcnt_3 - SUBMODULE FSUB2B - INSTANCE rcnt_2 - SUBMODULE FSUB2B - INSTANCE rcnt_1 - SUBMODULE FSUB2B - INSTANCE rcnt_0 - SUBMODULE FSUB2B - INSTANCE wcnt_8 - SUBMODULE FSUB2B - INSTANCE wcnt_7 - SUBMODULE FSUB2B - INSTANCE wcnt_6 - SUBMODULE FSUB2B - INSTANCE wcnt_5 - SUBMODULE FSUB2B - INSTANCE wcnt_4 - SUBMODULE FSUB2B - INSTANCE wcnt_3 - SUBMODULE FSUB2B - INSTANCE wcnt_2 - SUBMODULE FSUB2B - INSTANCE wcnt_1 - SUBMODULE FSUB2B - INSTANCE wcnt_0 - SUBMODULE MUX41 - INSTANCE mux_0 - SUBMODULE MUX41 - INSTANCE mux_1 - SUBMODULE MUX41 - INSTANCE mux_2 - SUBMODULE MUX41 - INSTANCE mux_3 - SUBMODULE MUX41 - INSTANCE mux_4 - SUBMODULE MUX41 - INSTANCE mux_5 - SUBMODULE MUX41 - INSTANCE mux_6 - SUBMODULE MUX41 - INSTANCE mux_7 - SUBMODULE CU2 - INSTANCE r_gctr_8 - SUBMODULE CU2 - INSTANCE r_gctr_7 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE CU2 - INSTANCE w_gctr_7 - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3BX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1S3DX - INSTANCE FF_54 - SUBMODULE FD1S3DX - INSTANCE FF_55 - SUBMODULE FD1S3DX - INSTANCE FF_56 - SUBMODULE FD1S3DX - INSTANCE FF_57 - SUBMODULE FD1S3DX - INSTANCE FF_58 - SUBMODULE FD1S3DX - INSTANCE FF_59 - SUBMODULE FD1S3DX - INSTANCE FF_60 - SUBMODULE FD1S3DX - INSTANCE FF_61 - SUBMODULE FD1S3DX - INSTANCE FF_62 - SUBMODULE FD1S3DX - INSTANCE FF_63 - SUBMODULE FD1S3DX - INSTANCE FF_64 - SUBMODULE FD1S3DX - INSTANCE FF_65 - SUBMODULE FD1S3DX - INSTANCE FF_66 - SUBMODULE FD1S3DX - INSTANCE FF_67 - SUBMODULE FD1S3DX - INSTANCE FF_68 - SUBMODULE FD1S3DX - INSTANCE FF_69 - SUBMODULE FD1S3DX - INSTANCE FF_70 - SUBMODULE FD1S3DX - INSTANCE FF_71 - SUBMODULE FD1S3DX - INSTANCE FF_72 - SUBMODULE FD1S3DX - INSTANCE FF_73 - SUBMODULE FD1S3DX - INSTANCE FF_74 - SUBMODULE FD1S3DX - INSTANCE FF_75 - SUBMODULE FD1S3DX - INSTANCE FF_76 - SUBMODULE FD1S3DX - INSTANCE FF_77 - SUBMODULE FD1S3DX - INSTANCE FF_78 - SUBMODULE FD1S3DX - INSTANCE FF_79 - SUBMODULE FD1S3DX - INSTANCE FF_80 - SUBMODULE FD1S3DX - INSTANCE FF_81 - SUBMODULE FD1S3DX - INSTANCE FF_82 - SUBMODULE FD1S3DX - INSTANCE FF_83 - SUBMODULE FD1S3DX - INSTANCE FF_84 - SUBMODULE FD1S3DX - INSTANCE FF_85 - SUBMODULE FD1S3DX - INSTANCE FF_86 - SUBMODULE FD1S3DX - INSTANCE FF_87 - SUBMODULE FD1S3DX - INSTANCE FF_88 - SUBMODULE FD1S3DX - INSTANCE FF_89 - SUBMODULE FD1S3DX - INSTANCE FF_90 - SUBMODULE FD1S3DX - INSTANCE FF_91 - SUBMODULE FD1S3DX - INSTANCE FF_92 - SUBMODULE FD1S3DX - INSTANCE FF_93 - SUBMODULE FD1S3DX - INSTANCE FF_94 - SUBMODULE FD1S3DX - INSTANCE FF_95 - SUBMODULE FD1S3DX - INSTANCE FF_96 - SUBMODULE FD1S3DX - INSTANCE FF_97 - SUBMODULE FD1S3DX - INSTANCE FF_98 - SUBMODULE FD1S3DX - INSTANCE FF_99 - SUBMODULE FD1S3DX - INSTANCE FF_100 - SUBMODULE FD1S3DX - INSTANCE FF_101 - SUBMODULE FD1S3DX - INSTANCE FF_102 - SUBMODULE FD1S3DX - INSTANCE FF_103 - SUBMODULE FD1S3DX - INSTANCE FF_104 - SUBMODULE FD1S3DX - INSTANCE FF_105 - SUBMODULE FD1S3DX - INSTANCE FF_106 - SUBMODULE FD1S3DX - INSTANCE FF_107 - SUBMODULE FD1S3DX - INSTANCE FF_108 - SUBMODULE FD1S3DX - INSTANCE FF_109 - SUBMODULE FD1S3DX - INSTANCE FF_110 - SUBMODULE FD1S3DX - INSTANCE FF_111 - SUBMODULE FD1S3DX - INSTANCE FF_112 - SUBMODULE FD1S3DX - INSTANCE FF_113 - SUBMODULE FD1S3DX - INSTANCE FF_114 - SUBMODULE FD1S3DX - INSTANCE FF_115 - SUBMODULE FD1S3DX - INSTANCE FF_116 - SUBMODULE FD1S3DX - INSTANCE FF_117 - SUBMODULE FD1S3DX - INSTANCE FF_118 - SUBMODULE FD1S3DX - INSTANCE FF_119 - SUBMODULE FD1S3DX - INSTANCE FF_120 - SUBMODULE FD1S3DX - INSTANCE FF_121 - SUBMODULE FD1S3DX - INSTANCE FF_122 - SUBMODULE FD1S3DX - INSTANCE FF_123 - SUBMODULE FD1S3DX - INSTANCE FF_124 - SUBMODULE FD1S3DX - INSTANCE FF_125 - SUBMODULE FD1S3DX - INSTANCE FF_126 - SUBMODULE FD1S3DX - INSTANCE FF_127 - SUBMODULE FD1S3DX - INSTANCE FF_128 - SUBMODULE FD1S3DX - INSTANCE FF_129 - SUBMODULE FD1S3DX - INSTANCE FF_130 - SUBMODULE FD1S3DX - INSTANCE FF_131 - SUBMODULE FD1S3DX - INSTANCE FF_132 - SUBMODULE FD1S3DX - INSTANCE FF_133 - SUBMODULE FD1S3DX - INSTANCE FF_134 - SUBMODULE FD1S3DX - INSTANCE FF_135 - SUBMODULE FD1P3DX - INSTANCE FF_136 - SUBMODULE FD1P3DX - INSTANCE FF_137 - SUBMODULE FD1P3DX - INSTANCE FF_138 - SUBMODULE FD1P3DX - INSTANCE FF_139 - SUBMODULE FD1P3DX - INSTANCE FF_140 - SUBMODULE FD1P3DX - INSTANCE FF_141 - SUBMODULE FD1P3DX - INSTANCE FF_142 - SUBMODULE FD1P3DX - INSTANCE FF_143 - SUBMODULE FD1P3DX - INSTANCE FF_144 - SUBMODULE FD1P3DX - INSTANCE FF_145 - SUBMODULE FD1P3DX - INSTANCE FF_146 - SUBMODULE FD1P3DX - INSTANCE FF_147 - SUBMODULE FD1P3DX - INSTANCE FF_148 - SUBMODULE FD1P3DX - INSTANCE FF_149 - SUBMODULE FD1P3DX - INSTANCE FF_150 - SUBMODULE FD1P3DX - INSTANCE FF_151 - SUBMODULE FD1P3DX - INSTANCE FF_152 - SUBMODULE FD1P3DX - INSTANCE FF_153 - SUBMODULE FD1P3DX - INSTANCE FF_154 - SUBMODULE FD1P3DX - INSTANCE FF_155 - SUBMODULE FD1P3DX - INSTANCE FF_156 - SUBMODULE FD1P3DX - INSTANCE FF_157 - SUBMODULE FD1P3DX - INSTANCE FF_158 - SUBMODULE FD1P3DX - INSTANCE FF_159 - SUBMODULE FD1P3DX - INSTANCE FF_160 - SUBMODULE FD1P3DX - INSTANCE FF_161 - SUBMODULE FD1P3DX - INSTANCE FF_162 - SUBMODULE FD1P3DX - INSTANCE FF_163 - SUBMODULE FD1P3DX - INSTANCE FF_164 - SUBMODULE FD1P3DX - INSTANCE FF_165 - SUBMODULE FD1P3DX - INSTANCE FF_166 - SUBMODULE FD1P3DX - INSTANCE FF_167 - SUBMODULE FD1P3DX - INSTANCE FF_168 - SUBMODULE FD1P3DX - INSTANCE FF_169 - SUBMODULE FD1P3DX - INSTANCE FF_170 - SUBMODULE FD1P3DX - INSTANCE FF_171 - SUBMODULE FD1P3DX - INSTANCE FF_172 - SUBMODULE FD1P3DX - INSTANCE FF_173 - SUBMODULE FD1P3DX - INSTANCE FF_174 - SUBMODULE FD1P3DX - INSTANCE FF_175 - SUBMODULE FD1P3DX - INSTANCE FF_176 - SUBMODULE FD1P3DX - INSTANCE FF_177 - SUBMODULE FD1P3DX - INSTANCE FF_178 - SUBMODULE FD1P3DX - INSTANCE FF_179 - SUBMODULE FD1P3DX - INSTANCE FF_180 - SUBMODULE FD1P3DX - INSTANCE FF_181 - SUBMODULE FD1P3DX - INSTANCE FF_182 - SUBMODULE FD1P3DX - INSTANCE FF_183 - SUBMODULE FD1P3DX - INSTANCE FF_184 - SUBMODULE FD1P3DX - INSTANCE FF_185 - SUBMODULE FD1P3DX - INSTANCE FF_186 - SUBMODULE FD1P3DX - INSTANCE FF_187 - SUBMODULE FD1P3BX - INSTANCE FF_188 - SUBMODULE FD1P3DX - INSTANCE FF_189 - SUBMODULE FD1P3DX - INSTANCE FF_190 - SUBMODULE FD1P3DX - INSTANCE FF_191 - SUBMODULE FD1P3DX - INSTANCE FF_192 - SUBMODULE FD1P3DX - INSTANCE FF_193 - SUBMODULE FD1P3DX - INSTANCE FF_194 - SUBMODULE FD1P3DX - INSTANCE FF_195 - SUBMODULE FD1P3DX - INSTANCE FF_196 - SUBMODULE FD1P3DX - INSTANCE FF_197 - SUBMODULE FD1P3DX - INSTANCE FF_198 - SUBMODULE FD1P3DX - INSTANCE FF_199 - SUBMODULE FD1P3DX - INSTANCE FF_200 - SUBMODULE FD1P3DX - INSTANCE FF_201 - SUBMODULE FD1P3DX - INSTANCE FF_202 - SUBMODULE FD1P3DX - INSTANCE FF_203 - SUBMODULE FD1P3DX - INSTANCE FF_204 - SUBMODULE FD1P3DX - INSTANCE FF_205 - SUBMODULE FD1P3DX - INSTANCE FF_206 - SUBMODULE FD1P3DX - INSTANCE FF_207 - SUBMODULE FD1P3DX - INSTANCE FF_208 - SUBMODULE FD1P3DX - INSTANCE FF_209 - SUBMODULE FD1P3DX - INSTANCE FF_210 - SUBMODULE FD1P3DX - INSTANCE FF_211 - SUBMODULE FD1P3DX - INSTANCE FF_212 - SUBMODULE FD1P3DX - INSTANCE FF_213 - SUBMODULE FD1P3DX - INSTANCE FF_214 - SUBMODULE FD1P3DX - INSTANCE FF_215 - SUBMODULE FD1P3DX - INSTANCE FF_216 - SUBMODULE FD1P3DX - INSTANCE FF_217 - SUBMODULE FD1P3DX - INSTANCE FF_218 - SUBMODULE FD1P3DX - INSTANCE FF_219 - SUBMODULE FD1P3DX - INSTANCE FF_220 - SUBMODULE FD1P3DX - INSTANCE FF_221 - SUBMODULE FD1P3DX - INSTANCE FF_222 - SUBMODULE FD1P3DX - INSTANCE FF_223 - SUBMODULE FD1P3DX - INSTANCE FF_224 - SUBMODULE FD1P3DX - INSTANCE FF_225 - SUBMODULE FD1P3DX - INSTANCE FF_226 - SUBMODULE FD1P3DX - INSTANCE FF_227 - SUBMODULE FD1P3DX - INSTANCE FF_228 - SUBMODULE FD1P3DX - INSTANCE FF_229 - SUBMODULE FD1P3DX - INSTANCE FF_230 - SUBMODULE FD1P3DX - INSTANCE FF_231 - SUBMODULE FD1P3DX - INSTANCE FF_232 - SUBMODULE FD1P3DX - INSTANCE FF_233 - SUBMODULE FD1P3DX - INSTANCE FF_234 - SUBMODULE FD1P3DX - INSTANCE FF_235 - SUBMODULE FD1P3BX - INSTANCE FF_236 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_7_0 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_6_1 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_5_2 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_4_3 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_3_4 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_2_5 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_1_6 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_0_7 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_7_8 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_6_9 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_5_10 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_4_11 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_3_12 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_2_13 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_1_14 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_0_15 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_7_16 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_6_17 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_5_18 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_4_19 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_3_20 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_2_21 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_1_22 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_0_23 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_7_24 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_6_25 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_5_26 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_4_27 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_3_28 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_2_29 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_1_30 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_0_31 - SUBMODULE AND2 - INSTANCE AND2_t0 - SUBMODULE AND2 - INSTANCE AND2_t1 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE ROM16X1 - INSTANCE LUT4_0 - SUBMODULE ROM16X1 - INSTANCE LUT4_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_2 - SUBMODULE ROM16X1 - INSTANCE LUT4_3 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE ROM16X1 - INSTANCE LUT4_4 - SUBMODULE ROM16X1 - INSTANCE LUT4_5 - SUBMODULE ROM16X1 - INSTANCE LUT4_6 - SUBMODULE ROM16X1 - INSTANCE LUT4_7 - SUBMODULE ROM16X1 - INSTANCE LUT4_8 - SUBMODULE ROM16X1 - INSTANCE LUT4_9 - SUBMODULE ROM16X1 - INSTANCE LUT4_10 - SUBMODULE ROM16X1 - INSTANCE LUT4_11 - SUBMODULE ROM16X1 - INSTANCE LUT4_12 - SUBMODULE ROM16X1 - INSTANCE LUT4_13 - SUBMODULE ROM16X1 - INSTANCE LUT4_14 - SUBMODULE ROM16X1 - INSTANCE LUT4_15 - SUBMODULE ROM16X1 - INSTANCE LUT4_16 - SUBMODULE ROM16X1 - INSTANCE LUT4_17 - SUBMODULE ROM16X1 - INSTANCE LUT4_18 - SUBMODULE ROM16X1 - INSTANCE LUT4_19 - SUBMODULE ROM16X1 - INSTANCE LUT4_20 - SUBMODULE ROM16X1 - INSTANCE LUT4_21 - SUBMODULE ROM16X1 - INSTANCE LUT4_22 - SUBMODULE ROM16X1 - INSTANCE LUT4_23 - SUBMODULE ROM16X1 - INSTANCE LUT4_24 - SUBMODULE ROM16X1 - INSTANCE LUT4_25 - SUBMODULE ROM16X1 - INSTANCE LUT4_26 - SUBMODULE ROM16X1 - INSTANCE LUT4_27 - SUBMODULE ROM16X1 - INSTANCE LUT4_28 - SUBMODULE ROM16X1 - INSTANCE LUT4_29 - SUBMODULE ROM16X1 - INSTANCE LUT4_30 - SUBMODULE ROM16X1 - INSTANCE LUT4_31 - SUBMODULE ROM16X1 - INSTANCE LUT4_32 - SUBMODULE ROM16X1 - INSTANCE LUT4_33 - SUBMODULE ROM16X1 - INSTANCE LUT4_34 - SUBMODULE ROM16X1 - INSTANCE LUT4_35 - SUBMODULE ROM16X1 - INSTANCE LUT4_36 - SUBMODULE ROM16X1 - INSTANCE LUT4_37 - SUBMODULE ROM16X1 - INSTANCE LUT4_38 - SUBMODULE ROM16X1 - INSTANCE LUT4_39 - SUBMODULE ROM16X1 - INSTANCE LUT4_40 - SUBMODULE ROM16X1 - INSTANCE LUT4_41 - SUBMODULE ROM16X1 - INSTANCE LUT4_42 - SUBMODULE ROM16X1 - INSTANCE LUT4_43 - SUBMODULE ROM16X1 - INSTANCE LUT4_44 - SUBMODULE ROM16X1 - INSTANCE LUT4_45 - SUBMODULE ROM16X1 - INSTANCE LUT4_46 - SUBMODULE ROM16X1 - INSTANCE LUT4_47 - SUBMODULE ROM16X1 - INSTANCE LUT4_48 - SUBMODULE ROM16X1 - INSTANCE LUT4_49 - SUBMODULE ROM16X1 - INSTANCE LUT4_50 - SUBMODULE ROM16X1 - INSTANCE LUT4_51 - SUBMODULE ROM16X1 - INSTANCE LUT4_52 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE XOR2 - INSTANCE XOR2_t24 - SUBMODULE XOR2 - INSTANCE XOR2_t25 - SUBMODULE XOR2 - INSTANCE XOR2_t26 - SUBMODULE XOR2 - INSTANCE XOR2_t27 - SUBMODULE XOR2 - INSTANCE XOR2_t28 - SUBMODULE XOR2 - INSTANCE XOR2_t29 - SUBMODULE XOR2 - INSTANCE XOR2_t30 - SUBMODULE XOR2 - INSTANCE XOR2_t31 - SUBMODULE XOR2 - INSTANCE XOR2_t32 - SUBMODULE XOR2 - INSTANCE XOR2_t33 - SUBMODULE XOR2 - INSTANCE XOR2_t34 - SUBMODULE XOR2 - INSTANCE XOR2_t35 - SUBMODULE XOR2 - INSTANCE XOR2_t36 - SUBMODULE OR2 - INSTANCE OR2_t37 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t38 - SUBMODULE INV - INSTANCE INV_2 - SUBMODULE AND2 - INSTANCE AND2_t39 diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.lpc b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.lpc deleted file mode 100755 index aa233bb..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_32kx16x8_mb -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:22:35 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=16 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=16 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=32752 -PfDeassert=506 -RDataCount=1 -WDataCount=1 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.naf b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.naf deleted file mode 100755 index e20b82d..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.naf +++ /dev/null @@ -1,98 +0,0 @@ -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -AmEmptyThresh[15] i -AmEmptyThresh[14] i -AmEmptyThresh[13] i -AmEmptyThresh[12] i -AmEmptyThresh[11] i -AmEmptyThresh[10] i -AmEmptyThresh[9] i -AmEmptyThresh[8] i -AmEmptyThresh[7] i -AmEmptyThresh[6] i -AmEmptyThresh[5] i -AmEmptyThresh[4] i -AmEmptyThresh[3] i -AmEmptyThresh[2] i -AmEmptyThresh[1] i -AmEmptyThresh[0] i -AmFullThresh[14] i -AmFullThresh[13] i -AmFullThresh[12] i -AmFullThresh[11] i -AmFullThresh[10] i -AmFullThresh[9] i -AmFullThresh[8] i -AmFullThresh[7] i -AmFullThresh[6] i -AmFullThresh[5] i -AmFullThresh[4] i -AmFullThresh[3] i -AmFullThresh[2] i -AmFullThresh[1] i -AmFullThresh[0] i -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -WCNT[15] o -WCNT[14] o -WCNT[13] o -WCNT[12] o -WCNT[11] o -WCNT[10] o -WCNT[9] o -WCNT[8] o -WCNT[7] o -WCNT[6] o -WCNT[5] o -WCNT[4] o -WCNT[3] o -WCNT[2] o -WCNT[1] o -WCNT[0] o -RCNT[16] o -RCNT[15] o -RCNT[14] o -RCNT[13] o -RCNT[12] o -RCNT[11] o -RCNT[10] o -RCNT[9] o -RCNT[8] o -RCNT[7] o -RCNT[6] o -RCNT[5] o -RCNT[4] o -RCNT[3] o -RCNT[2] o -RCNT[1] o -RCNT[0] o -Empty o -Full o -AlmostEmpty o -AlmostFull o diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.srp b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.srp deleted file mode 100755 index f08c3a0..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.srp +++ /dev/null @@ -1,44 +0,0 @@ -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Fri Feb 05 16:48:12 2010 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb - Module type : ebfifo - Module Version : 5.3 - Ports : - Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb.vhd - VHDL template : fifo_32kx16x8_mb_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb.srp - Element Usage : - AGEB2 : 34 - AND2 : 4 - CU2 : 17 - FADD2B : 12 - FSUB2B : 36 - FD1P3BX : 2 - FD1P3DX : 99 - FD1S3BX : 2 - FD1S3DX : 134 - INV : 3 - MUX41 : 8 - OR2 : 1 - ROM16X1 : 53 - XOR2 : 35 - DP16KB : 32 - Estimated Resource Usage: - LUT : 299 - EBR : 32 - Reg : 237 diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.sym b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.sym deleted file mode 100755 index 62ba01e11303a90f050cc8a31d719391101c79b9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 716 zcmY+CKS&#K9L3-FE~c0|99D``$&jHqUHZpLaY(8Wky6uek|Bz*O@hTcb0jImr35L( zNiv92DH$C)9OBTSL+H@SAvj8hjGanwa_G=^zh6?w!QFj$@BQ9=e|PsaAN}-a+5~WE zM0n+4b|sF1zyPl01%;H%A+b!jm-aHA-#Bn~YvuZGA^G&Vy@e8umb}!7>9n`<-gQTT zCt&~|!Vc`~L~MDdu`^tX6FO}iY3EL^wB%Ob?%|AT4_~wz$(1tuz;|i`oNH|&SFV>E zxT0ps&(Z3vR)16V@oT8&Yr69<)c`lc&U`KGd>}Bh5|zZteZk$d>s9LwwLfOXT;FiG zbC|w7WMV-O(}{3@3=9*SOjxqUgd><3U)`iWj0rB}ouy<W$MQ=`^z zbo=Pg4fx#L(krKsoF7YY0JDQ1Ok6RMR|)kw{!a$XSe18`>h|MDd(Gs0b79+i1KdhW z0?9Dd5(^obG6a2t^KqZEinHXbBoy0ZTWrM^*^)(LlKDQL-p8uqj+(?#TqGA!B!~TR zp045)IVDZ@gkLPq^P}Pc_@|+*xJT~cv*Lgp;7oCw+{T4spX{TnJIN{b#drs2>dHTi CNQVLd diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.vhd b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.vhd deleted file mode 100755 index a24a3e6..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb.vhd +++ /dev/null @@ -1,3997 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e - --- Thu Sep 22 11:22:35 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_32kx16x8_mb is - port ( - Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(7 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end fifo_32kx16x8_mb; - -architecture Structure of fifo_32kx16x8_mb is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal rcount_w0: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal rcnt_reg_15_inv: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal wptr_15: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_16: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal rcnt_reg_16: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co7: std_logic; - signal wcount_15: std_logic; - signal co6: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal wcnt_sub_0: std_logic; - signal wcnt_sub_1: std_logic; - signal wcnt_sub_2: std_logic; - signal co0_2: std_logic; - signal wcnt_sub_3: std_logic; - signal wcnt_sub_4: std_logic; - signal co1_2: std_logic; - signal wcnt_sub_5: std_logic; - signal wcnt_sub_6: std_logic; - signal co2_2: std_logic; - signal wcnt_sub_7: std_logic; - signal wcnt_sub_8: std_logic; - signal co3_2: std_logic; - signal wcnt_sub_9: std_logic; - signal wcnt_sub_10: std_logic; - signal co4_2: std_logic; - signal wcnt_sub_11: std_logic; - signal wcnt_sub_12: std_logic; - signal co5_2: std_logic; - signal wcnt_sub_13: std_logic; - signal wcnt_sub_14: std_logic; - signal co6_2: std_logic; - signal wcnt_sub_15: std_logic; - signal co7_2: std_logic; - signal wcnt_sub_msb: std_logic; - signal rcnt_sub_0: std_logic; - signal rcnt_sub_1: std_logic; - signal rcnt_sub_2: std_logic; - signal co0_3: std_logic; - signal rcnt_sub_3: std_logic; - signal rcnt_sub_4: std_logic; - signal co1_3: std_logic; - signal rcnt_sub_5: std_logic; - signal rcnt_sub_6: std_logic; - signal co2_3: std_logic; - signal rcnt_sub_7: std_logic; - signal rcnt_sub_8: std_logic; - signal co3_3: std_logic; - signal rcnt_sub_9: std_logic; - signal rcnt_sub_10: std_logic; - signal co4_3: std_logic; - signal rcnt_sub_11: std_logic; - signal rcnt_sub_12: std_logic; - signal co5_3: std_logic; - signal rcnt_sub_13: std_logic; - signal rcnt_sub_14: std_logic; - signal co6_3: std_logic; - signal rcnt_sub_15: std_logic; - signal rcnt_sub_16: std_logic; - signal co7_3: std_logic; - signal rcnt_sub_msb: std_logic; - signal co8_1d: std_logic; - signal co8_1: std_logic; - signal wfill_sub_0: std_logic; - signal wptr_0: std_logic; - signal wfill_sub_1: std_logic; - signal wfill_sub_2: std_logic; - signal co0_4: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wfill_sub_3: std_logic; - signal wfill_sub_4: std_logic; - signal co1_4: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wfill_sub_5: std_logic; - signal wfill_sub_6: std_logic; - signal co2_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wfill_sub_7: std_logic; - signal wfill_sub_8: std_logic; - signal co3_4: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wfill_sub_9: std_logic; - signal wfill_sub_10: std_logic; - signal co4_4: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wfill_sub_11: std_logic; - signal wfill_sub_12: std_logic; - signal co5_4: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wfill_sub_13: std_logic; - signal wfill_sub_14: std_logic; - signal co6_4: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wfill_sub_15: std_logic; - signal co7_4: std_logic; - signal wfill_sub_msb: std_logic; - signal rfill_sub_0: std_logic; - signal rptr_0: std_logic; - signal scuba_vhi: std_logic; - signal rfill_sub_1: std_logic; - signal rfill_sub_2: std_logic; - signal co0_5: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rfill_sub_3: std_logic; - signal rfill_sub_4: std_logic; - signal co1_5: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rfill_sub_5: std_logic; - signal rfill_sub_6: std_logic; - signal co2_5: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rfill_sub_7: std_logic; - signal rfill_sub_8: std_logic; - signal co3_5: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rfill_sub_9: std_logic; - signal rfill_sub_10: std_logic; - signal co4_5: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rfill_sub_11: std_logic; - signal rfill_sub_12: std_logic; - signal co5_5: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rfill_sub_13: std_logic; - signal rfill_sub_14: std_logic; - signal co6_5: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rfill_sub_15: std_logic; - signal rfill_sub_16: std_logic; - signal co7_5: std_logic; - signal rptr_15: std_logic; - signal rfill_sub_msb: std_logic; - signal co8_2d: std_logic; - signal co8_2: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_6: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_6: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_6: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_6: std_logic; - signal wcount_r7: std_logic; - signal wcount_r8: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_6: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_6: std_logic; - signal wcount_r11: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_6: std_logic; - signal wcount_r13: std_logic; - signal wcount_r14: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_6: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_7: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_7: std_logic; - signal rcount_w7: std_logic; - signal rcount_w8: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_7: std_logic; - signal rcount_w9: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_7: std_logic; - signal rcount_w11: std_logic; - signal rcount_w12: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w14: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_7: std_logic; - signal rcount_w15: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_14: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; - signal co0_8: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; - signal co1_8: std_logic; - signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; - signal co2_8: std_logic; - signal rcnt_reg_6: std_logic; - signal rcnt_reg_7: std_logic; - signal co3_8: std_logic; - signal rcnt_reg_8: std_logic; - signal rcnt_reg_9: std_logic; - signal co4_8: std_logic; - signal rcnt_reg_10: std_logic; - signal rcnt_reg_11: std_logic; - signal co5_8: std_logic; - signal rcnt_reg_12: std_logic; - signal rcnt_reg_13: std_logic; - signal co6_8: std_logic; - signal rcnt_reg_14: std_logic; - signal rcnt_reg_15: std_logic; - signal co7_7: std_logic; - signal ae_clrsig: std_logic; - signal ae_setsig: std_logic; - signal ae_d: std_logic; - signal ae_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_3: std_logic; - signal wcnt_reg_0: std_logic; - signal wcnt_reg_1: std_logic; - signal co0_9: std_logic; - signal wcnt_reg_2: std_logic; - signal wcnt_reg_3: std_logic; - signal co1_9: std_logic; - signal wcnt_reg_4: std_logic; - signal wcnt_reg_5: std_logic; - signal co2_9: std_logic; - signal wcnt_reg_6: std_logic; - signal wcnt_reg_7: std_logic; - signal co3_9: std_logic; - signal wcnt_reg_8: std_logic; - signal wcnt_reg_9: std_logic; - signal co4_9: std_logic; - signal wcnt_reg_10: std_logic; - signal wcnt_reg_11: std_logic; - signal co5_9: std_logic; - signal wcnt_reg_12: std_logic; - signal wcnt_reg_13: std_logic; - signal co6_9: std_logic; - signal wcnt_reg_14: std_logic; - signal wcnt_reg_15: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX41 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; SD1: in std_logic; SD2: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; - attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; - attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; - attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; - attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; - attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; - attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; - attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; - attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; - attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; - attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; - attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; - attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; - attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; - attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; - attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; - attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; - attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; - attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; - attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; - attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; - attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; - attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; - attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; - attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; - attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; - attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; - attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; - attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; - attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; - attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; - attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC"; - attribute GSR of FF_236 : label is "ENABLED"; - attribute GSR of FF_235 : label is "ENABLED"; - attribute GSR of FF_234 : label is "ENABLED"; - attribute GSR of FF_233 : label is "ENABLED"; - attribute GSR of FF_232 : label is "ENABLED"; - attribute GSR of FF_231 : label is "ENABLED"; - attribute GSR of FF_230 : label is "ENABLED"; - attribute GSR of FF_229 : label is "ENABLED"; - attribute GSR of FF_228 : label is "ENABLED"; - attribute GSR of FF_227 : label is "ENABLED"; - attribute GSR of FF_226 : label is "ENABLED"; - attribute GSR of FF_225 : label is "ENABLED"; - attribute GSR of FF_224 : label is "ENABLED"; - attribute GSR of FF_223 : label is "ENABLED"; - attribute GSR of FF_222 : label is "ENABLED"; - attribute GSR of FF_221 : label is "ENABLED"; - attribute GSR of FF_220 : label is "ENABLED"; - attribute GSR of FF_219 : label is "ENABLED"; - attribute GSR of FF_218 : label is "ENABLED"; - attribute GSR of FF_217 : label is "ENABLED"; - attribute GSR of FF_216 : label is "ENABLED"; - attribute GSR of FF_215 : label is "ENABLED"; - attribute GSR of FF_214 : label is "ENABLED"; - attribute GSR of FF_213 : label is "ENABLED"; - attribute GSR of FF_212 : label is "ENABLED"; - attribute GSR of FF_211 : label is "ENABLED"; - attribute GSR of FF_210 : label is "ENABLED"; - attribute GSR of FF_209 : label is "ENABLED"; - attribute GSR of FF_208 : label is "ENABLED"; - attribute GSR of FF_207 : label is "ENABLED"; - attribute GSR of FF_206 : label is "ENABLED"; - attribute GSR of FF_205 : label is "ENABLED"; - attribute GSR of FF_204 : label is "ENABLED"; - attribute GSR of FF_203 : label is "ENABLED"; - attribute GSR of FF_202 : label is "ENABLED"; - attribute GSR of FF_201 : label is "ENABLED"; - attribute GSR of FF_200 : label is "ENABLED"; - attribute GSR of FF_199 : label is "ENABLED"; - attribute GSR of FF_198 : label is "ENABLED"; - attribute GSR of FF_197 : label is "ENABLED"; - attribute GSR of FF_196 : label is "ENABLED"; - attribute GSR of FF_195 : label is "ENABLED"; - attribute GSR of FF_194 : label is "ENABLED"; - attribute GSR of FF_193 : label is "ENABLED"; - attribute GSR of FF_192 : label is "ENABLED"; - attribute GSR of FF_191 : label is "ENABLED"; - attribute GSR of FF_190 : label is "ENABLED"; - attribute GSR of FF_189 : label is "ENABLED"; - attribute GSR of FF_188 : label is "ENABLED"; - attribute GSR of FF_187 : label is "ENABLED"; - attribute GSR of FF_186 : label is "ENABLED"; - attribute GSR of FF_185 : label is "ENABLED"; - attribute GSR of FF_184 : label is "ENABLED"; - attribute GSR of FF_183 : label is "ENABLED"; - attribute GSR of FF_182 : label is "ENABLED"; - attribute GSR of FF_181 : label is "ENABLED"; - attribute GSR of FF_180 : label is "ENABLED"; - attribute GSR of FF_179 : label is "ENABLED"; - attribute GSR of FF_178 : label is "ENABLED"; - attribute GSR of FF_177 : label is "ENABLED"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t39: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_2: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t38: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_1: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t37: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t36: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t35: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t34: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t33: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t32: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t31: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t30: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t29: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t28: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t27: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t26: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t25: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t24: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t23: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t22: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t21: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t20: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t19: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t18: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t17: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t16: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t15: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t14: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t13: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t12: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t11: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t9: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t8: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t7: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t6: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - XOR2_t5: XOR2 - port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); - - XOR2_t4: XOR2 - port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); - - XOR2_t3: XOR2 - port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - INV_0: INV - port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_1_30: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_2_29: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_3_28: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_4_27: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_5_26: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_6_25: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_7_24: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_1_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_2_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_3_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_4_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_5_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_6_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_7_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_15: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_1_14: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_2_13: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_3_12: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_4_11: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_5_10: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_6_9: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_7_8: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_7: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_1_6: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_2_5: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_3_4: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_4_3: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_5_2: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_6_1: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_7_0: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_236: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_235: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_234: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_233: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_232: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_231: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_230: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_229: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_228: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_227: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_226: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_225: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_224: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_223: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_222: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_221: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_220: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_219: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_218: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_217: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_216: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_215: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_214: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_213: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_212: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_211: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_210: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_209: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_208: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_207: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_206: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_205: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_204: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_203: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_202: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_201: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_200: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_199: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_198: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_197: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_196: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_195: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_194: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_193: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_192: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_191: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_190: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_189: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_188: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_187: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_186: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_185: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_184: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_183: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_182: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_181: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_180: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_179: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_178: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_177: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_176: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_175: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_174: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_173: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_172: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_171: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_170: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_169: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_168: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_167: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_166: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_165: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_164: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_163: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_162: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_161: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_160: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_159: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_158: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_157: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_156: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_155: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_154: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_153: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_152: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_151: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_150: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_149: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_148: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_147: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_146: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_145: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_144: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_143: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_142: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_141: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_140: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_139: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_138: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_137: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_136: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_135: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_134: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_133: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_132: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_131: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_130: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_129: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_128: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_127: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_126: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_125: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_124: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_123: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_122: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_121: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_120: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_119: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_118: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_117: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_116: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_115: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_114: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_113: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_112: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_111: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_110: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_109: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_108: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_107: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_106: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_105: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_104: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_103: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_102: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_101: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_100: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_99: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_98: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_97: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_96: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_95: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_94: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_93: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_92: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_91: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_90: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_89: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_88: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_87: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_86: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_85: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_84: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_83: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_82: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_81: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_80: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_79: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_78: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_77: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_76: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_75: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_74: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_73: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_72: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_71: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_70: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_69: FD1S3DX - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); - - FF_68: FD1S3DX - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); - - FF_67: FD1S3DX - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); - - FF_66: FD1S3DX - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); - - FF_65: FD1S3DX - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); - - FF_64: FD1S3DX - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); - - FF_63: FD1S3DX - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); - - FF_62: FD1S3DX - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); - - FF_61: FD1S3DX - port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); - - FF_60: FD1S3DX - port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); - - FF_59: FD1S3DX - port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); - - FF_58: FD1S3DX - port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); - - FF_57: FD1S3DX - port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); - - FF_56: FD1S3DX - port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); - - FF_55: FD1S3DX - port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); - - FF_54: FD1S3DX - port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); - - FF_53: FD1S3DX - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_52: FD1S3DX - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_51: FD1S3DX - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_50: FD1S3DX - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_49: FD1S3DX - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_48: FD1S3DX - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_47: FD1S3DX - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); - - FF_46: FD1S3DX - port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); - - FF_45: FD1S3DX - port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); - - FF_44: FD1S3DX - port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); - - FF_43: FD1S3DX - port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); - - FF_42: FD1S3DX - port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); - - FF_41: FD1S3DX - port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); - - FF_40: FD1S3DX - port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); - - FF_39: FD1S3DX - port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); - - FF_38: FD1S3DX - port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); - - FF_37: FD1S3DX - port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); - - FF_36: FD1S3DX - port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); - - FF_35: FD1S3DX - port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); - - FF_34: FD1S3DX - port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); - - FF_33: FD1S3DX - port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); - - FF_32: FD1S3DX - port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); - - FF_31: FD1S3DX - port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); - - FF_30: FD1S3DX - port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); - - FF_29: FD1S3DX - port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); - - FF_28: FD1S3DX - port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); - - FF_27: FD1S3DX - port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); - - FF_26: FD1S3DX - port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); - - FF_25: FD1S3DX - port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); - - FF_24: FD1S3DX - port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); - - FF_23: FD1S3DX - port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); - - FF_22: FD1S3DX - port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); - - FF_21: FD1S3DX - port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); - - FF_20: FD1S3DX - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); - - FF_19: FD1S3DX - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); - - FF_18: FD1S3DX - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); - - FF_17: FD1S3DX - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); - - FF_16: FD1S3DX - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); - - FF_15: FD1S3DX - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); - - FF_14: FD1S3DX - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); - - FF_13: FD1S3DX - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); - - FF_12: FD1S3DX - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); - - FF_11: FD1S3DX - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); - - FF_10: FD1S3DX - port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); - - FF_9: FD1S3DX - port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); - - FF_8: FD1S3DX - port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); - - FF_7: FD1S3DX - port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); - - FF_6: FD1S3DX - port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); - - FF_5: FD1S3DX - port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); - - FF_4: FD1S3DX - port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); - - FF_3: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_2: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_1: FD1S3BX - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_0: FD1S3DX - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>ircount_16, NC1=>open); - - mux_7: MUX41 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); - - mux_6: MUX41 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); - - mux_5: MUX41 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); - - mux_4: MUX41 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); - - mux_3: MUX41 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); - - mux_2: MUX41 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); - - mux_1: MUX41 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); - - mux_0: MUX41 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); - - wcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, - S1=>wcnt_sub_0); - - wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, - B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, - S1=>wcnt_sub_2); - - wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, - B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, - S1=>wcnt_sub_4); - - wcnt_3: FSUB2B - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, - B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, - S1=>wcnt_sub_6); - - wcnt_4: FSUB2B - port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, - B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, - S1=>wcnt_sub_8); - - wcnt_5: FSUB2B - port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, - S1=>wcnt_sub_10); - - wcnt_6: FSUB2B - port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, - S0=>wcnt_sub_11, S1=>wcnt_sub_12); - - wcnt_7: FSUB2B - port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, - S1=>wcnt_sub_14); - - wcnt_8: FSUB2B - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, - S1=>open); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, - B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, - B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, - B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcnt_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, - B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, - S1=>rcnt_sub_8); - - rcnt_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, - B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, - S1=>rcnt_sub_10); - - rcnt_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, - B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, - S1=>rcnt_sub_12); - - rcnt_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, - B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, - S1=>rcnt_sub_14); - - rcnt_8: FSUB2B - port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, - B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, - S1=>rcnt_sub_16); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); - - wfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, - S1=>wfill_sub_0); - - wfill_1: FSUB2B - port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, - BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); - - wfill_2: FSUB2B - port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, - BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); - - wfill_3: FSUB2B - port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, - BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); - - wfill_4: FSUB2B - port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, - BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); - - wfill_5: FSUB2B - port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, - S1=>wfill_sub_10); - - wfill_6: FSUB2B - port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, - S0=>wfill_sub_11, S1=>wfill_sub_12); - - wfill_7: FSUB2B - port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, - S1=>wfill_sub_14); - - wfill_8: FSUB2B - port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, - S1=>rfill_sub_0); - - rfill_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, - BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); - - rfill_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, - BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); - - rfill_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, - BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); - - rfill_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, - BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); - - rfill_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, - BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); - - rfill_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, - B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, - S1=>rfill_sub_12); - - rfill_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, - B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, - S1=>rfill_sub_14); - - rfill_8: FSUB2B - port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, - B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, - S1=>rfill_sub_16); - - rfilld: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_6, GE=>co1_6); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_6, GE=>co2_6); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_6, GE=>co3_6); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>wcount_r8, CI=>co3_6, GE=>co4_6); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_6, GE=>co5_6); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, - B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, - B1=>wcount_r14, CI=>co6_6, GE=>co7_6); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_7, GE=>co1_7); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_7, GE=>co2_7); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_7, GE=>co3_7); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_7, GE=>co4_7); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, - B1=>rcount_w12, CI=>co4_7, GE=>co5_7); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w14, CI=>co5_7, GE=>co6_7); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, - B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); - - ae_cmp_3: AGEB2 - port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), - B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); - - ae_cmp_4: AGEB2 - port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), - B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); - - ae_cmp_5: AGEB2 - port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), - B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); - - ae_cmp_6: AGEB2 - port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), - B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); - - ae_cmp_7: AGEB2 - port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), - B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); - - ae_cmp_8: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - - af_d_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_d_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); - - af_d_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); - - af_d_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); - - af_d_cmp_3: AGEB2 - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); - - af_d_cmp_4: AGEB2 - port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), - B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); - - af_d_cmp_5: AGEB2 - port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), - B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); - - af_d_cmp_6: AGEB2 - port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), - B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); - - af_d_cmp_7: AGEB2 - port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), - B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_32kx16x8_mb is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX41 use entity ecp3.MUX41(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.lpc b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.lpc deleted file mode 100644 index 4ac80c1..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_32kx16x8_mb2 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:22:54 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=18 -RDepth=65536 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=16 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=32752 -PfDeassert=506 -RDataCount=1 -WDataCount=1 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.srp b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.srp deleted file mode 100644 index 2b6645f..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.srp +++ /dev/null @@ -1,44 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:22:54 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb2 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb2.vhd - VHDL template : fifo_32kx16x8_mb2_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb2.srp - Element Usage : - AGEB2 : 34 - AND2 : 4 - CU2 : 17 - FADD2B : 12 - FSUB2B : 36 - FD1P3BX : 2 - FD1P3DX : 102 - FD1S3BX : 2 - FD1S3DX : 134 - INV : 13 - MUX321 : 9 - OR2 : 1 - ROM16X1A : 181 - XOR2 : 35 - DP16KC : 32 - Estimated Resource Usage: - LUT : 491 - EBR : 32 - Reg : 240 diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.vhd b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.vhd deleted file mode 100644 index fef0b67..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2.vhd +++ /dev/null @@ -1,5224 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e - --- Thu Sep 22 11:22:54 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_32kx16x8_mb2 is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(8 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end fifo_32kx16x8_mb2; - -architecture Structure of fifo_32kx16x8_mb2 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal func_and_inet: std_logic; - signal func_and_inet_1: std_logic; - signal func_and_inet_2: std_logic; - signal func_and_inet_3: std_logic; - signal func_and_inet_4: std_logic; - signal func_and_inet_5: std_logic; - signal func_and_inet_6: std_logic; - signal func_and_inet_7: std_logic; - signal func_and_inet_8: std_logic; - signal func_and_inet_9: std_logic; - signal func_and_inet_10: std_logic; - signal func_and_inet_11: std_logic; - signal func_and_inet_12: std_logic; - signal func_and_inet_13: std_logic; - signal func_and_inet_14: std_logic; - signal func_and_inet_15: std_logic; - signal func_and_inet_16: std_logic; - signal func_and_inet_17: std_logic; - signal func_and_inet_18: std_logic; - signal func_and_inet_19: std_logic; - signal func_and_inet_20: std_logic; - signal func_and_inet_21: std_logic; - signal func_and_inet_22: std_logic; - signal func_and_inet_23: std_logic; - signal func_and_inet_24: std_logic; - signal func_and_inet_25: std_logic; - signal func_and_inet_26: std_logic; - signal func_and_inet_27: std_logic; - signal func_and_inet_28: std_logic; - signal func_and_inet_29: std_logic; - signal wptr_14_inv: std_logic; - signal func_and_inet_30: std_logic; - signal rptr_15_inv: std_logic; - signal func_and_inet_31: std_logic; - signal func_and_inet_32: std_logic; - signal func_and_inet_33: std_logic; - signal func_and_inet_34: std_logic; - signal func_and_inet_35: std_logic; - signal func_and_inet_36: std_logic; - signal func_and_inet_37: std_logic; - signal func_and_inet_38: std_logic; - signal func_and_inet_39: std_logic; - signal func_and_inet_40: std_logic; - signal func_and_inet_41: std_logic; - signal func_and_inet_42: std_logic; - signal func_and_inet_43: std_logic; - signal func_and_inet_44: std_logic; - signal func_and_inet_45: std_logic; - signal wptr_13_inv: std_logic; - signal func_and_inet_46: std_logic; - signal rptr_14_inv: std_logic; - signal func_and_inet_47: std_logic; - signal func_and_inet_48: std_logic; - signal func_and_inet_49: std_logic; - signal func_and_inet_50: std_logic; - signal func_and_inet_51: std_logic; - signal func_and_inet_52: std_logic; - signal func_and_inet_53: std_logic; - signal wptr_12_inv: std_logic; - signal func_and_inet_54: std_logic; - signal rptr_13_inv: std_logic; - signal func_and_inet_55: std_logic; - signal func_and_inet_56: std_logic; - signal func_and_inet_57: std_logic; - signal wptr_11_inv: std_logic; - signal func_and_inet_58: std_logic; - signal rptr_12_inv: std_logic; - signal func_and_inet_59: std_logic; - signal wptr_10_inv: std_logic; - signal func_and_inet_60: std_logic; - signal rptr_11_inv: std_logic; - signal func_and_inet_61: std_logic; - signal func_and_inet_62: std_logic; - signal func_and_inet_63: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal rcount_w0: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal rcnt_reg_15_inv: std_logic; - signal dec1_r10: std_logic; - signal dec0_p00: std_logic; - signal dec3_r11: std_logic; - signal dec2_p01: std_logic; - signal dec5_r12: std_logic; - signal dec4_p02: std_logic; - signal dec7_r13: std_logic; - signal dec6_p03: std_logic; - signal dec9_r14: std_logic; - signal dec8_p04: std_logic; - signal dec11_r15: std_logic; - signal dec10_p05: std_logic; - signal dec13_r16: std_logic; - signal dec12_p06: std_logic; - signal dec15_r17: std_logic; - signal dec14_p07: std_logic; - signal dec17_r18: std_logic; - signal dec16_p08: std_logic; - signal dec19_r19: std_logic; - signal dec18_p09: std_logic; - signal dec21_r110: std_logic; - signal dec20_p010: std_logic; - signal dec23_r111: std_logic; - signal dec22_p011: std_logic; - signal dec25_r112: std_logic; - signal dec24_p012: std_logic; - signal dec27_r113: std_logic; - signal dec26_p013: std_logic; - signal dec29_r114: std_logic; - signal dec28_p014: std_logic; - signal dec31_r115: std_logic; - signal dec30_p015: std_logic; - signal dec33_r116: std_logic; - signal dec32_p016: std_logic; - signal dec35_r117: std_logic; - signal dec34_p017: std_logic; - signal dec37_r118: std_logic; - signal dec36_p018: std_logic; - signal dec39_r119: std_logic; - signal dec38_p019: std_logic; - signal dec41_r120: std_logic; - signal dec40_p020: std_logic; - signal dec43_r121: std_logic; - signal dec42_p021: std_logic; - signal dec45_r122: std_logic; - signal dec44_p022: std_logic; - signal dec47_r123: std_logic; - signal dec46_p023: std_logic; - signal dec49_r124: std_logic; - signal dec48_p024: std_logic; - signal dec51_r125: std_logic; - signal dec50_p025: std_logic; - signal dec53_r126: std_logic; - signal dec52_p026: std_logic; - signal dec55_r127: std_logic; - signal dec54_p027: std_logic; - signal dec57_r128: std_logic; - signal dec56_p028: std_logic; - signal dec59_r129: std_logic; - signal dec58_p029: std_logic; - signal dec61_r130: std_logic; - signal dec60_p030: std_logic; - signal dec63_r131: std_logic; - signal dec62_p031: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal wptr_15: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_16: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal rcnt_reg_16: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co7: std_logic; - signal wcount_15: std_logic; - signal co6: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_31_0: std_logic; - signal mdout1_30_0: std_logic; - signal mdout1_29_0: std_logic; - signal mdout1_28_0: std_logic; - signal mdout1_27_0: std_logic; - signal mdout1_26_0: std_logic; - signal mdout1_25_0: std_logic; - signal mdout1_24_0: std_logic; - signal mdout1_23_0: std_logic; - signal mdout1_22_0: std_logic; - signal mdout1_21_0: std_logic; - signal mdout1_20_0: std_logic; - signal mdout1_19_0: std_logic; - signal mdout1_18_0: std_logic; - signal mdout1_17_0: std_logic; - signal mdout1_16_0: std_logic; - signal mdout1_15_0: std_logic; - signal mdout1_14_0: std_logic; - signal mdout1_13_0: std_logic; - signal mdout1_12_0: std_logic; - signal mdout1_11_0: std_logic; - signal mdout1_10_0: std_logic; - signal mdout1_9_0: std_logic; - signal mdout1_8_0: std_logic; - signal mdout1_7_0: std_logic; - signal mdout1_6_0: std_logic; - signal mdout1_5_0: std_logic; - signal mdout1_4_0: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_31_1: std_logic; - signal mdout1_30_1: std_logic; - signal mdout1_29_1: std_logic; - signal mdout1_28_1: std_logic; - signal mdout1_27_1: std_logic; - signal mdout1_26_1: std_logic; - signal mdout1_25_1: std_logic; - signal mdout1_24_1: std_logic; - signal mdout1_23_1: std_logic; - signal mdout1_22_1: std_logic; - signal mdout1_21_1: std_logic; - signal mdout1_20_1: std_logic; - signal mdout1_19_1: std_logic; - signal mdout1_18_1: std_logic; - signal mdout1_17_1: std_logic; - signal mdout1_16_1: std_logic; - signal mdout1_15_1: std_logic; - signal mdout1_14_1: std_logic; - signal mdout1_13_1: std_logic; - signal mdout1_12_1: std_logic; - signal mdout1_11_1: std_logic; - signal mdout1_10_1: std_logic; - signal mdout1_9_1: std_logic; - signal mdout1_8_1: std_logic; - signal mdout1_7_1: std_logic; - signal mdout1_6_1: std_logic; - signal mdout1_5_1: std_logic; - signal mdout1_4_1: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_31_2: std_logic; - signal mdout1_30_2: std_logic; - signal mdout1_29_2: std_logic; - signal mdout1_28_2: std_logic; - signal mdout1_27_2: std_logic; - signal mdout1_26_2: std_logic; - signal mdout1_25_2: std_logic; - signal mdout1_24_2: std_logic; - signal mdout1_23_2: std_logic; - signal mdout1_22_2: std_logic; - signal mdout1_21_2: std_logic; - signal mdout1_20_2: std_logic; - signal mdout1_19_2: std_logic; - signal mdout1_18_2: std_logic; - signal mdout1_17_2: std_logic; - signal mdout1_16_2: std_logic; - signal mdout1_15_2: std_logic; - signal mdout1_14_2: std_logic; - signal mdout1_13_2: std_logic; - signal mdout1_12_2: std_logic; - signal mdout1_11_2: std_logic; - signal mdout1_10_2: std_logic; - signal mdout1_9_2: std_logic; - signal mdout1_8_2: std_logic; - signal mdout1_7_2: std_logic; - signal mdout1_6_2: std_logic; - signal mdout1_5_2: std_logic; - signal mdout1_4_2: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_31_3: std_logic; - signal mdout1_30_3: std_logic; - signal mdout1_29_3: std_logic; - signal mdout1_28_3: std_logic; - signal mdout1_27_3: std_logic; - signal mdout1_26_3: std_logic; - signal mdout1_25_3: std_logic; - signal mdout1_24_3: std_logic; - signal mdout1_23_3: std_logic; - signal mdout1_22_3: std_logic; - signal mdout1_21_3: std_logic; - signal mdout1_20_3: std_logic; - signal mdout1_19_3: std_logic; - signal mdout1_18_3: std_logic; - signal mdout1_17_3: std_logic; - signal mdout1_16_3: std_logic; - signal mdout1_15_3: std_logic; - signal mdout1_14_3: std_logic; - signal mdout1_13_3: std_logic; - signal mdout1_12_3: std_logic; - signal mdout1_11_3: std_logic; - signal mdout1_10_3: std_logic; - signal mdout1_9_3: std_logic; - signal mdout1_8_3: std_logic; - signal mdout1_7_3: std_logic; - signal mdout1_6_3: std_logic; - signal mdout1_5_3: std_logic; - signal mdout1_4_3: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_31_4: std_logic; - signal mdout1_30_4: std_logic; - signal mdout1_29_4: std_logic; - signal mdout1_28_4: std_logic; - signal mdout1_27_4: std_logic; - signal mdout1_26_4: std_logic; - signal mdout1_25_4: std_logic; - signal mdout1_24_4: std_logic; - signal mdout1_23_4: std_logic; - signal mdout1_22_4: std_logic; - signal mdout1_21_4: std_logic; - signal mdout1_20_4: std_logic; - signal mdout1_19_4: std_logic; - signal mdout1_18_4: std_logic; - signal mdout1_17_4: std_logic; - signal mdout1_16_4: std_logic; - signal mdout1_15_4: std_logic; - signal mdout1_14_4: std_logic; - signal mdout1_13_4: std_logic; - signal mdout1_12_4: std_logic; - signal mdout1_11_4: std_logic; - signal mdout1_10_4: std_logic; - signal mdout1_9_4: std_logic; - signal mdout1_8_4: std_logic; - signal mdout1_7_4: std_logic; - signal mdout1_6_4: std_logic; - signal mdout1_5_4: std_logic; - signal mdout1_4_4: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_31_5: std_logic; - signal mdout1_30_5: std_logic; - signal mdout1_29_5: std_logic; - signal mdout1_28_5: std_logic; - signal mdout1_27_5: std_logic; - signal mdout1_26_5: std_logic; - signal mdout1_25_5: std_logic; - signal mdout1_24_5: std_logic; - signal mdout1_23_5: std_logic; - signal mdout1_22_5: std_logic; - signal mdout1_21_5: std_logic; - signal mdout1_20_5: std_logic; - signal mdout1_19_5: std_logic; - signal mdout1_18_5: std_logic; - signal mdout1_17_5: std_logic; - signal mdout1_16_5: std_logic; - signal mdout1_15_5: std_logic; - signal mdout1_14_5: std_logic; - signal mdout1_13_5: std_logic; - signal mdout1_12_5: std_logic; - signal mdout1_11_5: std_logic; - signal mdout1_10_5: std_logic; - signal mdout1_9_5: std_logic; - signal mdout1_8_5: std_logic; - signal mdout1_7_5: std_logic; - signal mdout1_6_5: std_logic; - signal mdout1_5_5: std_logic; - signal mdout1_4_5: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_31_6: std_logic; - signal mdout1_30_6: std_logic; - signal mdout1_29_6: std_logic; - signal mdout1_28_6: std_logic; - signal mdout1_27_6: std_logic; - signal mdout1_26_6: std_logic; - signal mdout1_25_6: std_logic; - signal mdout1_24_6: std_logic; - signal mdout1_23_6: std_logic; - signal mdout1_22_6: std_logic; - signal mdout1_21_6: std_logic; - signal mdout1_20_6: std_logic; - signal mdout1_19_6: std_logic; - signal mdout1_18_6: std_logic; - signal mdout1_17_6: std_logic; - signal mdout1_16_6: std_logic; - signal mdout1_15_6: std_logic; - signal mdout1_14_6: std_logic; - signal mdout1_13_6: std_logic; - signal mdout1_12_6: std_logic; - signal mdout1_11_6: std_logic; - signal mdout1_10_6: std_logic; - signal mdout1_9_6: std_logic; - signal mdout1_8_6: std_logic; - signal mdout1_7_6: std_logic; - signal mdout1_6_6: std_logic; - signal mdout1_5_6: std_logic; - signal mdout1_4_6: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_31_7: std_logic; - signal mdout1_30_7: std_logic; - signal mdout1_29_7: std_logic; - signal mdout1_28_7: std_logic; - signal mdout1_27_7: std_logic; - signal mdout1_26_7: std_logic; - signal mdout1_25_7: std_logic; - signal mdout1_24_7: std_logic; - signal mdout1_23_7: std_logic; - signal mdout1_22_7: std_logic; - signal mdout1_21_7: std_logic; - signal mdout1_20_7: std_logic; - signal mdout1_19_7: std_logic; - signal mdout1_18_7: std_logic; - signal mdout1_17_7: std_logic; - signal mdout1_16_7: std_logic; - signal mdout1_15_7: std_logic; - signal mdout1_14_7: std_logic; - signal mdout1_13_7: std_logic; - signal mdout1_12_7: std_logic; - signal mdout1_11_7: std_logic; - signal mdout1_10_7: std_logic; - signal mdout1_9_7: std_logic; - signal mdout1_8_7: std_logic; - signal mdout1_7_7: std_logic; - signal mdout1_6_7: std_logic; - signal mdout1_5_7: std_logic; - signal mdout1_4_7: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal rptr_13_ff: std_logic; - signal rptr_12_ff: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_31_8: std_logic; - signal mdout1_30_8: std_logic; - signal mdout1_29_8: std_logic; - signal mdout1_28_8: std_logic; - signal mdout1_27_8: std_logic; - signal mdout1_26_8: std_logic; - signal mdout1_25_8: std_logic; - signal mdout1_24_8: std_logic; - signal mdout1_23_8: std_logic; - signal mdout1_22_8: std_logic; - signal mdout1_21_8: std_logic; - signal mdout1_20_8: std_logic; - signal mdout1_19_8: std_logic; - signal mdout1_18_8: std_logic; - signal mdout1_17_8: std_logic; - signal mdout1_16_8: std_logic; - signal mdout1_15_8: std_logic; - signal mdout1_14_8: std_logic; - signal mdout1_13_8: std_logic; - signal mdout1_12_8: std_logic; - signal mdout1_11_8: std_logic; - signal mdout1_10_8: std_logic; - signal mdout1_9_8: std_logic; - signal mdout1_8_8: std_logic; - signal mdout1_7_8: std_logic; - signal mdout1_6_8: std_logic; - signal mdout1_5_8: std_logic; - signal mdout1_4_8: std_logic; - signal mdout1_3_8: std_logic; - signal mdout1_2_8: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal wcnt_sub_0: std_logic; - signal wcnt_sub_1: std_logic; - signal wcnt_sub_2: std_logic; - signal co0_2: std_logic; - signal wcnt_sub_3: std_logic; - signal wcnt_sub_4: std_logic; - signal co1_2: std_logic; - signal wcnt_sub_5: std_logic; - signal wcnt_sub_6: std_logic; - signal co2_2: std_logic; - signal wcnt_sub_7: std_logic; - signal wcnt_sub_8: std_logic; - signal co3_2: std_logic; - signal wcnt_sub_9: std_logic; - signal wcnt_sub_10: std_logic; - signal co4_2: std_logic; - signal wcnt_sub_11: std_logic; - signal wcnt_sub_12: std_logic; - signal co5_2: std_logic; - signal wcnt_sub_13: std_logic; - signal wcnt_sub_14: std_logic; - signal co6_2: std_logic; - signal wcnt_sub_15: std_logic; - signal co7_2: std_logic; - signal wcnt_sub_msb: std_logic; - signal rcnt_sub_0: std_logic; - signal rcnt_sub_1: std_logic; - signal rcnt_sub_2: std_logic; - signal co0_3: std_logic; - signal rcnt_sub_3: std_logic; - signal rcnt_sub_4: std_logic; - signal co1_3: std_logic; - signal rcnt_sub_5: std_logic; - signal rcnt_sub_6: std_logic; - signal co2_3: std_logic; - signal rcnt_sub_7: std_logic; - signal rcnt_sub_8: std_logic; - signal co3_3: std_logic; - signal rcnt_sub_9: std_logic; - signal rcnt_sub_10: std_logic; - signal co4_3: std_logic; - signal rcnt_sub_11: std_logic; - signal rcnt_sub_12: std_logic; - signal co5_3: std_logic; - signal rcnt_sub_13: std_logic; - signal rcnt_sub_14: std_logic; - signal co6_3: std_logic; - signal rcnt_sub_15: std_logic; - signal rcnt_sub_16: std_logic; - signal co7_3: std_logic; - signal rcnt_sub_msb: std_logic; - signal co8_1d: std_logic; - signal co8_1: std_logic; - signal wfill_sub_0: std_logic; - signal wptr_0: std_logic; - signal wfill_sub_1: std_logic; - signal wfill_sub_2: std_logic; - signal co0_4: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wfill_sub_3: std_logic; - signal wfill_sub_4: std_logic; - signal co1_4: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wfill_sub_5: std_logic; - signal wfill_sub_6: std_logic; - signal co2_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wfill_sub_7: std_logic; - signal wfill_sub_8: std_logic; - signal co3_4: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wfill_sub_9: std_logic; - signal wfill_sub_10: std_logic; - signal co4_4: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wfill_sub_11: std_logic; - signal wfill_sub_12: std_logic; - signal co5_4: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wfill_sub_13: std_logic; - signal wfill_sub_14: std_logic; - signal co6_4: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wfill_sub_15: std_logic; - signal co7_4: std_logic; - signal wfill_sub_msb: std_logic; - signal rfill_sub_0: std_logic; - signal rptr_0: std_logic; - signal scuba_vhi: std_logic; - signal rfill_sub_1: std_logic; - signal rfill_sub_2: std_logic; - signal co0_5: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rfill_sub_3: std_logic; - signal rfill_sub_4: std_logic; - signal co1_5: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rfill_sub_5: std_logic; - signal rfill_sub_6: std_logic; - signal co2_5: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rfill_sub_7: std_logic; - signal rfill_sub_8: std_logic; - signal co3_5: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rfill_sub_9: std_logic; - signal rfill_sub_10: std_logic; - signal co4_5: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rfill_sub_11: std_logic; - signal rfill_sub_12: std_logic; - signal co5_5: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rfill_sub_13: std_logic; - signal rfill_sub_14: std_logic; - signal co6_5: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rfill_sub_15: std_logic; - signal rfill_sub_16: std_logic; - signal co7_5: std_logic; - signal rptr_15: std_logic; - signal rfill_sub_msb: std_logic; - signal co8_2d: std_logic; - signal co8_2: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_6: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_6: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_6: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_6: std_logic; - signal wcount_r7: std_logic; - signal wcount_r8: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_6: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_6: std_logic; - signal wcount_r11: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_6: std_logic; - signal wcount_r13: std_logic; - signal wcount_r14: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_6: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_7: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_7: std_logic; - signal rcount_w7: std_logic; - signal rcount_w8: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_7: std_logic; - signal rcount_w9: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_7: std_logic; - signal rcount_w11: std_logic; - signal rcount_w12: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w14: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_7: std_logic; - signal rcount_w15: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_14: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; - signal co0_8: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; - signal co1_8: std_logic; - signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; - signal co2_8: std_logic; - signal rcnt_reg_6: std_logic; - signal rcnt_reg_7: std_logic; - signal co3_8: std_logic; - signal rcnt_reg_8: std_logic; - signal rcnt_reg_9: std_logic; - signal co4_8: std_logic; - signal rcnt_reg_10: std_logic; - signal rcnt_reg_11: std_logic; - signal co5_8: std_logic; - signal rcnt_reg_12: std_logic; - signal rcnt_reg_13: std_logic; - signal co6_8: std_logic; - signal rcnt_reg_14: std_logic; - signal rcnt_reg_15: std_logic; - signal co7_7: std_logic; - signal ae_clrsig: std_logic; - signal ae_setsig: std_logic; - signal ae_d: std_logic; - signal ae_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_3: std_logic; - signal wcnt_reg_0: std_logic; - signal wcnt_reg_1: std_logic; - signal co0_9: std_logic; - signal wcnt_reg_2: std_logic; - signal wcnt_reg_3: std_logic; - signal co1_9: std_logic; - signal wcnt_reg_4: std_logic; - signal wcnt_reg_5: std_logic; - signal co2_9: std_logic; - signal wcnt_reg_6: std_logic; - signal wcnt_reg_7: std_logic; - signal co3_9: std_logic; - signal wcnt_reg_8: std_logic; - signal wcnt_reg_9: std_logic; - signal co4_9: std_logic; - signal wcnt_reg_10: std_logic; - signal wcnt_reg_11: std_logic; - signal co5_9: std_logic; - signal wcnt_reg_12: std_logic; - signal wcnt_reg_13: std_logic; - signal co6_9: std_logic; - signal wcnt_reg_14: std_logic; - signal wcnt_reg_15: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX321 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; D4: in std_logic; D5: in std_logic; - D6: in std_logic; D7: in std_logic; D8: in std_logic; - D9: in std_logic; D10: in std_logic; D11: in std_logic; - D12: in std_logic; D13: in std_logic; D14: in std_logic; - D15: in std_logic; D16: in std_logic; D17: in std_logic; - D18: in std_logic; D19: in std_logic; D20: in std_logic; - D21: in std_logic; D22: in std_logic; D23: in std_logic; - D24: in std_logic; D25: in std_logic; D26: in std_logic; - D27: in std_logic; D28: in std_logic; D29: in std_logic; - D30: in std_logic; D31: in std_logic; SD1: in std_logic; - SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; - SD5: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; - attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; - attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; - attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; - attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; - attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; - attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; - attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; - attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; - attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; - attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; - attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; - attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; - attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; - attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; - attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; - attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; - attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; - attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; - attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; - attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; - attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; - attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; - attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; - attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; - attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; - attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; - attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; - attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; - attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; - attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; - attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; - attribute GSR of FF_239 : label is "ENABLED"; - attribute GSR of FF_238 : label is "ENABLED"; - attribute GSR of FF_237 : label is "ENABLED"; - attribute GSR of FF_236 : label is "ENABLED"; - attribute GSR of FF_235 : label is "ENABLED"; - attribute GSR of FF_234 : label is "ENABLED"; - attribute GSR of FF_233 : label is "ENABLED"; - attribute GSR of FF_232 : label is "ENABLED"; - attribute GSR of FF_231 : label is "ENABLED"; - attribute GSR of FF_230 : label is "ENABLED"; - attribute GSR of FF_229 : label is "ENABLED"; - attribute GSR of FF_228 : label is "ENABLED"; - attribute GSR of FF_227 : label is "ENABLED"; - attribute GSR of FF_226 : label is "ENABLED"; - attribute GSR of FF_225 : label is "ENABLED"; - attribute GSR of FF_224 : label is "ENABLED"; - attribute GSR of FF_223 : label is "ENABLED"; - attribute GSR of FF_222 : label is "ENABLED"; - attribute GSR of FF_221 : label is "ENABLED"; - attribute GSR of FF_220 : label is "ENABLED"; - attribute GSR of FF_219 : label is "ENABLED"; - attribute GSR of FF_218 : label is "ENABLED"; - attribute GSR of FF_217 : label is "ENABLED"; - attribute GSR of FF_216 : label is "ENABLED"; - attribute GSR of FF_215 : label is "ENABLED"; - attribute GSR of FF_214 : label is "ENABLED"; - attribute GSR of FF_213 : label is "ENABLED"; - attribute GSR of FF_212 : label is "ENABLED"; - attribute GSR of FF_211 : label is "ENABLED"; - attribute GSR of FF_210 : label is "ENABLED"; - attribute GSR of FF_209 : label is "ENABLED"; - attribute GSR of FF_208 : label is "ENABLED"; - attribute GSR of FF_207 : label is "ENABLED"; - attribute GSR of FF_206 : label is "ENABLED"; - attribute GSR of FF_205 : label is "ENABLED"; - attribute GSR of FF_204 : label is "ENABLED"; - attribute GSR of FF_203 : label is "ENABLED"; - attribute GSR of FF_202 : label is "ENABLED"; - attribute GSR of FF_201 : label is "ENABLED"; - attribute GSR of FF_200 : label is "ENABLED"; - attribute GSR of FF_199 : label is "ENABLED"; - attribute GSR of FF_198 : label is "ENABLED"; - attribute GSR of FF_197 : label is "ENABLED"; - attribute GSR of FF_196 : label is "ENABLED"; - attribute GSR of FF_195 : label is "ENABLED"; - attribute GSR of FF_194 : label is "ENABLED"; - attribute GSR of FF_193 : label is "ENABLED"; - attribute GSR of FF_192 : label is "ENABLED"; - attribute GSR of FF_191 : label is "ENABLED"; - attribute GSR of FF_190 : label is "ENABLED"; - attribute GSR of FF_189 : label is "ENABLED"; - attribute GSR of FF_188 : label is "ENABLED"; - attribute GSR of FF_187 : label is "ENABLED"; - attribute GSR of FF_186 : label is "ENABLED"; - attribute GSR of FF_185 : label is "ENABLED"; - attribute GSR of FF_184 : label is "ENABLED"; - attribute GSR of FF_183 : label is "ENABLED"; - attribute GSR of FF_182 : label is "ENABLED"; - attribute GSR of FF_181 : label is "ENABLED"; - attribute GSR of FF_180 : label is "ENABLED"; - attribute GSR of FF_179 : label is "ENABLED"; - attribute GSR of FF_178 : label is "ENABLED"; - attribute GSR of FF_177 : label is "ENABLED"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t39: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_12: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t38: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_11: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t37: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t36: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t35: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t34: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t33: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t32: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t31: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t30: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t29: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t28: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t27: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t26: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t25: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t24: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t23: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t22: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t21: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t20: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t19: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t18: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t17: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t16: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t15: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t14: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t13: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t12: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t11: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t9: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t8: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t7: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t6: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - INV_10: INV - port map (A=>wptr_10, Z=>wptr_10_inv); - - INV_9: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_8: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_7: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_6: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - LUT4_180: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet); - - LUT4_179: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_p00); - - INV_5: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_4: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_3: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_2: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - INV_1: INV - port map (A=>rptr_15, Z=>rptr_15_inv); - - LUT4_178: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_1); - - LUT4_177: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec1_r10); - - LUT4_176: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_2); - - LUT4_175: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec2_p01); - - LUT4_174: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_3); - - LUT4_173: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec3_r11); - - LUT4_172: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_4); - - LUT4_171: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec4_p02); - - LUT4_170: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_5); - - LUT4_169: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec5_r12); - - LUT4_168: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_6); - - LUT4_167: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec6_p03); - - LUT4_166: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_7); - - LUT4_165: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec7_r13); - - LUT4_164: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_8); - - LUT4_163: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec8_p04); - - LUT4_162: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_9); - - LUT4_161: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec9_r14); - - LUT4_160: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_10); - - LUT4_159: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - - LUT4_158: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_11); - - LUT4_157: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - - LUT4_156: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_12); - - LUT4_155: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - - LUT4_154: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_13); - - LUT4_153: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - - LUT4_152: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_14); - - LUT4_151: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - - LUT4_150: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_15); - - LUT4_149: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - - LUT4_148: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_16); - - LUT4_147: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - - LUT4_146: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_17); - - LUT4_145: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - - LUT4_144: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_18); - - LUT4_143: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - - LUT4_142: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_19); - - LUT4_141: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - - LUT4_140: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_20); - - LUT4_139: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - - LUT4_138: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_21); - - LUT4_137: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - - LUT4_136: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_22); - - LUT4_135: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - - LUT4_134: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_23); - - LUT4_133: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - - LUT4_132: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_24); - - LUT4_131: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - - LUT4_130: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_25); - - LUT4_129: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - - LUT4_128: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_26); - - LUT4_127: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - - LUT4_126: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_27); - - LUT4_125: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - - LUT4_124: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_28); - - LUT4_123: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - - LUT4_122: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_29); - - LUT4_121: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - - LUT4_120: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_30); - - LUT4_119: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - - LUT4_118: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_31); - - LUT4_117: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - - LUT4_116: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_32); - - LUT4_115: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec32_p016); - - LUT4_114: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_33); - - LUT4_113: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec33_r116); - - LUT4_112: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_34); - - LUT4_111: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec34_p017); - - LUT4_110: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_35); - - LUT4_109: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec35_r117); - - LUT4_108: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_36); - - LUT4_107: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec36_p018); - - LUT4_106: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_37); - - LUT4_105: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec37_r118); - - LUT4_104: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_38); - - LUT4_103: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec38_p019); - - LUT4_102: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_39); - - LUT4_101: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec39_r119); - - LUT4_100: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_40); - - LUT4_99: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec40_p020); - - LUT4_98: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_41); - - LUT4_97: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec41_r120); - - LUT4_96: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_42); - - LUT4_95: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec42_p021); - - LUT4_94: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_43); - - LUT4_93: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec43_r121); - - LUT4_92: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_44); - - LUT4_91: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec44_p022); - - LUT4_90: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_45); - - LUT4_89: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec45_r122); - - LUT4_88: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_46); - - LUT4_87: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec46_p023); - - LUT4_86: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_47); - - LUT4_85: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec47_r123); - - LUT4_84: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_48); - - LUT4_83: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec48_p024); - - LUT4_82: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_49); - - LUT4_81: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec49_r124); - - LUT4_80: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_50); - - LUT4_79: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec50_p025); - - LUT4_78: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_51); - - LUT4_77: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec51_r125); - - LUT4_76: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_52); - - LUT4_75: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec52_p026); - - LUT4_74: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_53); - - LUT4_73: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec53_r126); - - LUT4_72: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_54); - - LUT4_71: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec54_p027); - - LUT4_70: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_55); - - LUT4_69: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec55_r127); - - LUT4_68: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_56); - - LUT4_67: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec56_p028); - - LUT4_66: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_57); - - LUT4_65: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec57_r128); - - LUT4_64: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_58); - - LUT4_63: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec58_p029); - - LUT4_62: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_59); - - LUT4_61: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec59_r129); - - LUT4_60: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_60); - - LUT4_59: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec60_p030); - - LUT4_58: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_61); - - LUT4_57: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec61_r130); - - LUT4_56: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_62); - - LUT4_55: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec62_p031); - - LUT4_54: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_63); - - LUT4_53: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec63_r131); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - XOR2_t5: XOR2 - port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); - - XOR2_t4: XOR2 - port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); - - XOR2_t3: XOR2 - port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - INV_0: INV - port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, - DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, - DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, - DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, - DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, - DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, - DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, - DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, - DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, - DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, - DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, - DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, - DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, - DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, - DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, - DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, - DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, - DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, - DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, - DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, - DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, - DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, - DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, - DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, - DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, - DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, - DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, - DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, - DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, - DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, - DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, - DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, - DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, - DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, - DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, - DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, - DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, - DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, - DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, - DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, - DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, - DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, - DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, - DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, - DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, - DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, - DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, - DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, - DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, - DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, - DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, - DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, - DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, - DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, - DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, - DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, - DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, - DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, - DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, - DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, - DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, - DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, - DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, - DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, - DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, - DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, - DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, - DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, - DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, - DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, - DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, - DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, - DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, - DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, - DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, - DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, - DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, - DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, - DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, - DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, - DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, - DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, - DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, - DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, - DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, - DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, - DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, - DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, - DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, - DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, - DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_239: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_238: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_237: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_236: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_235: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_234: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_233: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_232: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_231: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_230: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_229: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_228: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_227: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_226: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_225: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_224: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_223: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_222: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_221: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_220: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_219: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_218: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_217: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_216: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_215: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_214: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_213: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_212: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_211: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_210: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_209: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_208: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_207: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_206: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_205: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_204: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_203: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_202: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_201: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_200: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_199: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_198: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_197: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_196: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_195: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_194: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_193: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_192: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_191: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_190: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_189: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_188: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_187: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_186: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_185: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_184: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_183: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_182: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_181: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_180: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_179: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_178: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_177: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_176: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_175: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_174: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_173: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_172: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_171: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_170: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_169: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_168: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_167: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_166: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_165: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_164: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_163: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_162: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_161: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_160: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_159: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_158: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_157: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_156: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_155: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_154: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_153: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_152: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_151: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_150: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_149: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_148: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_147: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_146: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_145: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_144: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_143: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_142: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_141: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_140: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_139: FD1P3DX - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_138: FD1P3DX - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_137: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_136: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_135: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_134: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_133: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_132: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_131: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_130: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_129: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_128: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_127: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_126: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_125: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_124: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_123: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_122: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_121: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_120: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_119: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_118: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_117: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_116: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_115: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_114: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_113: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_112: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_111: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_110: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_109: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_108: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_107: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_106: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_105: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_104: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_103: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_102: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_101: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_100: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_99: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_98: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_97: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_96: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_95: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_94: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_93: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_92: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_91: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_90: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_89: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_88: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_87: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_86: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_85: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_84: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_83: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_82: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_81: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_80: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_79: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_78: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_77: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_76: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_75: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_74: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_73: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_72: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_71: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_70: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_69: FD1S3DX - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); - - FF_68: FD1S3DX - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); - - FF_67: FD1S3DX - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); - - FF_66: FD1S3DX - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); - - FF_65: FD1S3DX - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); - - FF_64: FD1S3DX - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); - - FF_63: FD1S3DX - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); - - FF_62: FD1S3DX - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); - - FF_61: FD1S3DX - port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); - - FF_60: FD1S3DX - port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); - - FF_59: FD1S3DX - port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); - - FF_58: FD1S3DX - port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); - - FF_57: FD1S3DX - port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); - - FF_56: FD1S3DX - port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); - - FF_55: FD1S3DX - port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); - - FF_54: FD1S3DX - port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); - - FF_53: FD1S3DX - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_52: FD1S3DX - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_51: FD1S3DX - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_50: FD1S3DX - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_49: FD1S3DX - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_48: FD1S3DX - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_47: FD1S3DX - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); - - FF_46: FD1S3DX - port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); - - FF_45: FD1S3DX - port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); - - FF_44: FD1S3DX - port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); - - FF_43: FD1S3DX - port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); - - FF_42: FD1S3DX - port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); - - FF_41: FD1S3DX - port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); - - FF_40: FD1S3DX - port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); - - FF_39: FD1S3DX - port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); - - FF_38: FD1S3DX - port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); - - FF_37: FD1S3DX - port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); - - FF_36: FD1S3DX - port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); - - FF_35: FD1S3DX - port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); - - FF_34: FD1S3DX - port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); - - FF_33: FD1S3DX - port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); - - FF_32: FD1S3DX - port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); - - FF_31: FD1S3DX - port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); - - FF_30: FD1S3DX - port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); - - FF_29: FD1S3DX - port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); - - FF_28: FD1S3DX - port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); - - FF_27: FD1S3DX - port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); - - FF_26: FD1S3DX - port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); - - FF_25: FD1S3DX - port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); - - FF_24: FD1S3DX - port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); - - FF_23: FD1S3DX - port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); - - FF_22: FD1S3DX - port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); - - FF_21: FD1S3DX - port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); - - FF_20: FD1S3DX - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); - - FF_19: FD1S3DX - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); - - FF_18: FD1S3DX - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); - - FF_17: FD1S3DX - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); - - FF_16: FD1S3DX - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); - - FF_15: FD1S3DX - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); - - FF_14: FD1S3DX - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); - - FF_13: FD1S3DX - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); - - FF_12: FD1S3DX - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); - - FF_11: FD1S3DX - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); - - FF_10: FD1S3DX - port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); - - FF_9: FD1S3DX - port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); - - FF_8: FD1S3DX - port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); - - FF_7: FD1S3DX - port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); - - FF_6: FD1S3DX - port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); - - FF_5: FD1S3DX - port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); - - FF_4: FD1S3DX - port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); - - FF_3: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_2: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_1: FD1S3BX - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_0: FD1S3DX - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>ircount_16, NC1=>open); - - mux_8: MUX321 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, - D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, - D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, - D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, - D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, - D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(0)); - - mux_7: MUX321 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, - D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, - D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, - D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, - D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, - D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(1)); - - mux_6: MUX321 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, - D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, - D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, - D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, - D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, - D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(2)); - - mux_5: MUX321 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, - D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, - D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, - D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, - D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, - D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(3)); - - mux_4: MUX321 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, - D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, - D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, - D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, - D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, - D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(4)); - - mux_3: MUX321 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, - D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, - D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, - D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, - D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, - D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(5)); - - mux_2: MUX321 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, - D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, - D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, - D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, - D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, - D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(6)); - - mux_1: MUX321 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, - D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, - D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, - D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, - D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, - D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(7)); - - mux_0: MUX321 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, - D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, - D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, - D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, - D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, - D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(8)); - - wcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, - S1=>wcnt_sub_0); - - wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, - B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, - S1=>wcnt_sub_2); - - wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, - B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, - S1=>wcnt_sub_4); - - wcnt_3: FSUB2B - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, - B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, - S1=>wcnt_sub_6); - - wcnt_4: FSUB2B - port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, - B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, - S1=>wcnt_sub_8); - - wcnt_5: FSUB2B - port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, - S1=>wcnt_sub_10); - - wcnt_6: FSUB2B - port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, - S0=>wcnt_sub_11, S1=>wcnt_sub_12); - - wcnt_7: FSUB2B - port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, - S1=>wcnt_sub_14); - - wcnt_8: FSUB2B - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, - S1=>open); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, - B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, - B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, - B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcnt_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, - B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, - S1=>rcnt_sub_8); - - rcnt_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, - B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, - S1=>rcnt_sub_10); - - rcnt_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, - B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, - S1=>rcnt_sub_12); - - rcnt_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, - B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, - S1=>rcnt_sub_14); - - rcnt_8: FSUB2B - port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, - B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, - S1=>rcnt_sub_16); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); - - wfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, - S1=>wfill_sub_0); - - wfill_1: FSUB2B - port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, - BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); - - wfill_2: FSUB2B - port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, - BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); - - wfill_3: FSUB2B - port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, - BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); - - wfill_4: FSUB2B - port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, - BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); - - wfill_5: FSUB2B - port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, - S1=>wfill_sub_10); - - wfill_6: FSUB2B - port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, - S0=>wfill_sub_11, S1=>wfill_sub_12); - - wfill_7: FSUB2B - port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, - S1=>wfill_sub_14); - - wfill_8: FSUB2B - port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, - S1=>rfill_sub_0); - - rfill_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, - BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); - - rfill_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, - BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); - - rfill_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, - BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); - - rfill_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, - BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); - - rfill_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, - BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); - - rfill_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, - B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, - S1=>rfill_sub_12); - - rfill_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, - B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, - S1=>rfill_sub_14); - - rfill_8: FSUB2B - port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, - B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, - S1=>rfill_sub_16); - - rfilld: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_6, GE=>co1_6); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_6, GE=>co2_6); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_6, GE=>co3_6); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>wcount_r8, CI=>co3_6, GE=>co4_6); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_6, GE=>co5_6); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, - B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, - B1=>wcount_r14, CI=>co6_6, GE=>co7_6); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_7, GE=>co1_7); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_7, GE=>co2_7); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_7, GE=>co3_7); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_7, GE=>co4_7); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, - B1=>rcount_w12, CI=>co4_7, GE=>co5_7); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w14, CI=>co5_7, GE=>co6_7); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, - B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); - - ae_cmp_3: AGEB2 - port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), - B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); - - ae_cmp_4: AGEB2 - port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), - B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); - - ae_cmp_5: AGEB2 - port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), - B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); - - ae_cmp_6: AGEB2 - port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), - B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); - - ae_cmp_7: AGEB2 - port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), - B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); - - ae_cmp_8: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - - af_d_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_d_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); - - af_d_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); - - af_d_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); - - af_d_cmp_3: AGEB2 - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); - - af_d_cmp_4: AGEB2 - port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), - B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); - - af_d_cmp_5: AGEB2 - port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), - B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); - - af_d_cmp_6: AGEB2 - port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), - B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); - - af_d_cmp_7: AGEB2 - port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), - B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_32kx16x8_mb2 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX321 use entity ecp3.MUX321(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2_generate.log b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2_generate.log deleted file mode 100644 index eceede3..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:22:54 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb2 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb2.vhd - VHDL template : fifo_32kx16x8_mb2_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb2.srp - Estimated Resource Usage: - LUT : 491 - EBR : 32 - Reg : 240 - -END SCUBA Module Synthesis - -File: fifo_32kx16x8_mb2.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2_tmpl.vhd deleted file mode 100644 index 041890c..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb2_tmpl.vhd +++ /dev/null @@ -1,26 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:22:54 2011 - --- parameterized module component declaration -component fifo_32kx16x8_mb2 - port (Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(8 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_32kx16x8_mb2 - port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__, - AmFullThresh(14 downto 0)=>__, Q(8 downto 0)=>__, WCNT(15 downto 0)=>__, - RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__, - AlmostFull=>__); diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb_generate.log b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb_generate.log deleted file mode 100755 index 4dfc957..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Fri Feb 05 16:48:12 2010 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb - Module type : ebfifo - Module Version : 5.3 - Ports : - Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb.vhd - VHDL template : fifo_32kx16x8_mb_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb.srp - Estimated Resource Usage: - LUT : 299 - EBR : 32 - Reg : 237 - -END SCUBA Module Synthesis - -File: .\ipexpress\fifo_32kx16x8_mb\fifo_32kx16x8_mb.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_32kx16x8_mb_tmpl.vhd deleted file mode 100755 index a84a110..0000000 --- a/gbe2_ecp3/ipcores/fifo_32kx16x8_mb_tmpl.vhd +++ /dev/null @@ -1,26 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:22:35 2011 - --- parameterized module component declaration -component fifo_32kx16x8_mb - port (Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(7 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_32kx16x8_mb - port map (Data(15 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__, - AmFullThresh(14 downto 0)=>__, Q(7 downto 0)=>__, WCNT(15 downto 0)=>__, - RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__, - AlmostFull=>__); diff --git a/gbe2_ecp3/ipcores/fifo_4096x32.jhd b/gbe2_ecp3/ipcores/fifo_4096x32.jhd deleted file mode 100755 index d87350d..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x32.jhd +++ /dev/null @@ -1,479 +0,0 @@ -MODULE fifo_4096x32 DEFIN fifo_4096x32.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3BX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3DX - INSTANCE FF_121 - SUBMODULE FD1P3DX - INSTANCE FF_122 - SUBMODULE FD1P3DX - INSTANCE FF_123 - SUBMODULE FD1P3DX - INSTANCE FF_124 - SUBMODULE FD1P3DX - INSTANCE FF_125 - SUBMODULE FD1P3DX - INSTANCE FF_126 - SUBMODULE FD1P3DX - INSTANCE FF_127 - SUBMODULE FD1P3DX - INSTANCE FF_128 - SUBMODULE FD1P3DX - INSTANCE FF_129 - SUBMODULE FD1P3DX - INSTANCE FF_130 - SUBMODULE FD1P3BX - INSTANCE FF_131 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_7_0 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_6_1 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_5_2 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_4_3 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_3_4 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_2_5 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_1_6 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_0_7 - SUBMODULE ROM16X1 - INSTANCE LUT4_0 - SUBMODULE ROM16X1 - INSTANCE LUT4_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_2 - SUBMODULE ROM16X1 - INSTANCE LUT4_3 - SUBMODULE ROM16X1 - INSTANCE LUT4_4 - SUBMODULE ROM16X1 - INSTANCE LUT4_5 - SUBMODULE ROM16X1 - INSTANCE LUT4_6 - SUBMODULE ROM16X1 - INSTANCE LUT4_7 - SUBMODULE ROM16X1 - INSTANCE LUT4_8 - SUBMODULE ROM16X1 - INSTANCE LUT4_9 - SUBMODULE ROM16X1 - INSTANCE LUT4_10 - SUBMODULE ROM16X1 - INSTANCE LUT4_11 - SUBMODULE ROM16X1 - INSTANCE LUT4_12 - SUBMODULE ROM16X1 - INSTANCE LUT4_13 - SUBMODULE ROM16X1 - INSTANCE LUT4_14 - SUBMODULE ROM16X1 - INSTANCE LUT4_15 - SUBMODULE ROM16X1 - INSTANCE LUT4_16 - SUBMODULE ROM16X1 - INSTANCE LUT4_17 - SUBMODULE ROM16X1 - INSTANCE LUT4_18 - SUBMODULE ROM16X1 - INSTANCE LUT4_19 - SUBMODULE ROM16X1 - INSTANCE LUT4_20 - SUBMODULE ROM16X1 - INSTANCE LUT4_21 - SUBMODULE ROM16X1 - INSTANCE LUT4_22 - SUBMODULE ROM16X1 - INSTANCE LUT4_23 - SUBMODULE ROM16X1 - INSTANCE LUT4_24 - SUBMODULE ROM16X1 - INSTANCE LUT4_25 - SUBMODULE ROM16X1 - INSTANCE LUT4_26 - SUBMODULE ROM16X1 - INSTANCE LUT4_27 - SUBMODULE ROM16X1 - INSTANCE LUT4_28 - SUBMODULE ROM16X1 - INSTANCE LUT4_29 - SUBMODULE ROM16X1 - INSTANCE LUT4_30 - SUBMODULE ROM16X1 - INSTANCE LUT4_31 - SUBMODULE ROM16X1 - INSTANCE LUT4_32 - SUBMODULE ROM16X1 - INSTANCE LUT4_33 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE OR2 - INSTANCE OR2_t24 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t25 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t26 diff --git a/gbe2_ecp3/ipcores/fifo_4096x32.lpc b/gbe2_ecp3/ipcores/fifo_4096x32.lpc deleted file mode 100755 index 39ae0d7..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x32.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_4096x32 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:15 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=32 -RDepth=4096 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_4096x32.naf b/gbe2_ecp3/ipcores/fifo_4096x32.naf deleted file mode 100755 index 7174bad..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x32.naf +++ /dev/null @@ -1,72 +0,0 @@ -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[31] o -Q[30] o -Q[29] o -Q[28] o -Q[27] o -Q[26] o -Q[25] o -Q[24] o -Q[23] o -Q[22] o -Q[21] o -Q[20] o -Q[19] o -Q[18] o -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores/fifo_4096x32.srp b/gbe2_ecp3/ipcores/fifo_4096x32.srp deleted file mode 100755 index 5b60728..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x32.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Fri Dec 18 03:02:30 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x32 - Module type : ebfifo - Module Version : 5.3 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x32.vhd - VHDL template : fifo_4096x32_tmpl.vhd - VHDL testbench : tb_fifo_4096x32_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x32.srp - Element Usage : - AGEB2 : 14 - AND2 : 2 - CU2 : 14 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 76 - FD1S3BX : 1 - FD1S3DX : 53 - INV : 2 - OR2 : 1 - ROM16X1 : 34 - XOR2 : 24 - DP16KB : 8 - Estimated Resource Usage: - LUT : 129 - EBR : 8 - Reg : 132 diff --git a/gbe2_ecp3/ipcores/fifo_4096x32.sym b/gbe2_ecp3/ipcores/fifo_4096x32.sym deleted file mode 100755 index aa8beace15d07f89e24426d73654238c0a890d76..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 436 zcmX|-u}i~17{%X5Q;Q;!!9O5F2XTs41dBt#q_`PFrJ#rw(}I|`p+=}%DbAA7!NI}7 zK_r8NZpGOlgR^vW?Cj*rrFFQw$M4;}@B8k#?&$6J9DrBRxC0}phyg=P0hXjpQo$;U z7R7?q2pdPGwX%5(I0O-_%qh6uj^91IfJd6(Fr%95*&U!yHbEz2dAE7l3~@`Q%W(GE z$><|#fV(NJ_p;14(ikt(%z7`){9>OmK2WTF0(rX~gx9~&?i{OFjX@y;-W7SDb z=E(;t{ggbN&fxNup1@#NeWerX1UE{@)G;EZBkBnEN(a;do|u{bzQM)M=Ly!R$R7qf BQi}ip diff --git a/gbe2_ecp3/ipcores/fifo_4096x32.vhd b/gbe2_ecp3/ipcores/fifo_4096x32.vhd deleted file mode 100755 index 2f52ee4..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x32.vhd +++ /dev/null @@ -1,1803 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:24:15 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_4096x32 is - port ( - Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4096x32; - -architecture Structure of fifo_4096x32 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; - attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; - attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; - attribute RESETMODE of pdp_ram_0_2_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; - attribute RESETMODE of pdp_ram_0_3_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; - attribute RESETMODE of pdp_ram_0_4_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; - attribute RESETMODE of pdp_ram_0_5_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; - attribute RESETMODE of pdp_ram_0_6_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; - attribute RESETMODE of pdp_ram_0_7_0 : label is "SYNC"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_7: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_1_6: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), - DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_2_5: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), - DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8), - DOB1=>Q(9), DOB2=>Q(10), DOB3=>Q(11), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_3_4: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), - DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(12), - DOB1=>Q(13), DOB2=>Q(14), DOB3=>Q(15), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_4_3: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), - DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(16), - DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_5_2: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), - DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(20), - DOB1=>Q(21), DOB2=>Q(22), DOB3=>Q(23), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_6_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), - DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(24), - DOB1=>Q(25), DOB2=>Q(26), DOB3=>Q(27), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_7_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), - DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(28), - DOB1=>Q(29), DOB2=>Q(30), DOB3=>Q(31), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_131: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_130: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_129: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_128: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_127: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_126: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_125: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_124: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_123: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_122: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_121: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_120: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_119: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_118: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_117: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_116: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_115: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_114: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_113: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_112: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_111: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_110: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_109: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_108: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_107: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_106: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_105: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_104: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_103: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_102: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_101: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_100: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_99: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_98: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_97: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_96: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_95: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_94: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_93: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_92: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_91: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_90: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_89: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_88: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_87: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_86: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_85: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_84: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_83: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_82: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_81: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_80: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_79: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_78: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_77: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_76: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_75: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_74: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_73: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_72: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_71: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_70: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_69: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_68: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_67: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_66: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_65: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_64: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_63: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_62: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_61: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_60: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_59: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_58: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_57: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_56: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_55: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_54: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_53: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_4096x32 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_4096x32_generate.log b/gbe2_ecp3/ipcores/fifo_4096x32_generate.log deleted file mode 100755 index ad8aeeb..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x32_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Fri Dec 18 03:02:30 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x32 - Module type : ebfifo - Module Version : 5.3 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x32.vhd - VHDL template : fifo_4096x32_tmpl.vhd - VHDL testbench : tb_fifo_4096x32_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x32.srp - Estimated Resource Usage: - LUT : 129 - EBR : 8 - Reg : 132 - -END SCUBA Module Synthesis - -File: fifo_4096x32.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_4096x32_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_4096x32_tmpl.vhd deleted file mode 100755 index f26714f..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x32_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:24:15 2011 - --- parameterized module component declaration -component fifo_4096x32 - port (Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x32 - port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores/fifo_4096x9.jhd b/gbe2_ecp3/ipcores/fifo_4096x9.jhd deleted file mode 100755 index f8c1e39..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x9.jhd +++ /dev/null @@ -1,487 +0,0 @@ -MODULE fifo_4096x9 DEFIN fifo_4096x9.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE MUX21 - INSTANCE mux_0 - SUBMODULE MUX21 - INSTANCE mux_1 - SUBMODULE MUX21 - INSTANCE mux_2 - SUBMODULE MUX21 - INSTANCE mux_3 - SUBMODULE MUX21 - INSTANCE mux_4 - SUBMODULE MUX21 - INSTANCE mux_5 - SUBMODULE MUX21 - INSTANCE mux_6 - SUBMODULE MUX21 - INSTANCE mux_7 - SUBMODULE MUX21 - INSTANCE mux_8 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3BX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3DX - INSTANCE FF_121 - SUBMODULE FD1P3DX - INSTANCE FF_122 - SUBMODULE FD1P3DX - INSTANCE FF_123 - SUBMODULE FD1P3DX - INSTANCE FF_124 - SUBMODULE FD1P3DX - INSTANCE FF_125 - SUBMODULE FD1P3DX - INSTANCE FF_126 - SUBMODULE FD1P3DX - INSTANCE FF_127 - SUBMODULE FD1P3DX - INSTANCE FF_128 - SUBMODULE FD1P3DX - INSTANCE FF_129 - SUBMODULE FD1P3DX - INSTANCE FF_130 - SUBMODULE FD1P3DX - INSTANCE FF_131 - SUBMODULE FD1P3BX - INSTANCE FF_132 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_0_0 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_0_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_0 - SUBMODULE ROM16X1 - INSTANCE LUT4_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_2 - SUBMODULE ROM16X1 - INSTANCE LUT4_3 - SUBMODULE ROM16X1 - INSTANCE LUT4_4 - SUBMODULE ROM16X1 - INSTANCE LUT4_5 - SUBMODULE ROM16X1 - INSTANCE LUT4_6 - SUBMODULE ROM16X1 - INSTANCE LUT4_7 - SUBMODULE ROM16X1 - INSTANCE LUT4_8 - SUBMODULE ROM16X1 - INSTANCE LUT4_9 - SUBMODULE ROM16X1 - INSTANCE LUT4_10 - SUBMODULE ROM16X1 - INSTANCE LUT4_11 - SUBMODULE ROM16X1 - INSTANCE LUT4_12 - SUBMODULE ROM16X1 - INSTANCE LUT4_13 - SUBMODULE ROM16X1 - INSTANCE LUT4_14 - SUBMODULE ROM16X1 - INSTANCE LUT4_15 - SUBMODULE ROM16X1 - INSTANCE LUT4_16 - SUBMODULE ROM16X1 - INSTANCE LUT4_17 - SUBMODULE ROM16X1 - INSTANCE LUT4_18 - SUBMODULE ROM16X1 - INSTANCE LUT4_19 - SUBMODULE ROM16X1 - INSTANCE LUT4_20 - SUBMODULE ROM16X1 - INSTANCE LUT4_21 - SUBMODULE ROM16X1 - INSTANCE LUT4_22 - SUBMODULE ROM16X1 - INSTANCE LUT4_23 - SUBMODULE ROM16X1 - INSTANCE LUT4_24 - SUBMODULE ROM16X1 - INSTANCE LUT4_25 - SUBMODULE ROM16X1 - INSTANCE LUT4_26 - SUBMODULE ROM16X1 - INSTANCE LUT4_27 - SUBMODULE ROM16X1 - INSTANCE LUT4_28 - SUBMODULE ROM16X1 - INSTANCE LUT4_29 - SUBMODULE ROM16X1 - INSTANCE LUT4_30 - SUBMODULE ROM16X1 - INSTANCE LUT4_31 - SUBMODULE ROM16X1 - INSTANCE LUT4_32 - SUBMODULE ROM16X1 - INSTANCE LUT4_33 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE OR2 - INSTANCE OR2_t24 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t25 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t26 diff --git a/gbe2_ecp3/ipcores/fifo_4096x9.lpc b/gbe2_ecp3/ipcores/fifo_4096x9.lpc deleted file mode 100755 index 6e382a8..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x9.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_4096x9 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:06 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=9 -RDepth=4096 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_4096x9.naf b/gbe2_ecp3/ipcores/fifo_4096x9.naf deleted file mode 100755 index cc69a7a..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x9.naf +++ /dev/null @@ -1,26 +0,0 @@ -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores/fifo_4096x9.srp b/gbe2_ecp3/ipcores/fifo_4096x9.srp deleted file mode 100755 index 932dbf1..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x9.srp +++ /dev/null @@ -1,43 +0,0 @@ -SCUBA, Version ispLever_v72_SP2_Build (23) -Tue Jan 5 23:44:15 2010 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x9 - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x9.vhd - VHDL template : fifo_4096x9_tmpl.vhd - VHDL testbench : tb_fifo_4096x9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x9.srp - Element Usage : - AGEB2 : 14 - AND2 : 2 - CU2 : 14 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 77 - FD1S3BX : 1 - FD1S3DX : 53 - INV : 2 - MUX21 : 9 - OR2 : 1 - ROM16X1 : 34 - XOR2 : 24 - DP16KB : 2 - Estimated Resource Usage: - LUT : 138 - EBR : 2 - Reg : 133 diff --git a/gbe2_ecp3/ipcores/fifo_4096x9.sym b/gbe2_ecp3/ipcores/fifo_4096x9.sym deleted file mode 100755 index 2c39ee8f834b81731bf9e0c4b59d764d2cb3b1c2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 432 zcmYk2Axy(S7=_=@I>-PqfkaeP5kv(c9jbwL62<~42@o>a76^qkqY!YlBokExNeFVH z1~eMgpwY;s63OeeB#3Lje(%4RyNg53$M580&?fX?HjL!O1y}X;bVKR%>_NOW=ksgI~C6yLZ(KF`}zW^tZcJ*k{@R z52f{nMdurBf^pgD4fD=Vo-)BZjOGVWbuWVOj#EL_Lyr`|kra)1|h=6_!20%rLJ_u29b-%?P> diff --git a/gbe2_ecp3/ipcores/fifo_4096x9.vhd b/gbe2_ecp3/ipcores/fifo_4096x9.vhd deleted file mode 100755 index 75ae6c9..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x9.vhd +++ /dev/null @@ -1,1624 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:24:06 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_4096x9 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4096x9; - -architecture Structure of fifo_4096x9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_12: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX21 - port (D0: in std_logic; D1: in std_logic; SD: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; - attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_132: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_131: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_130: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_129: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_128: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_127: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_126: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_125: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_124: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_123: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_122: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_121: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_120: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_119: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_118: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_117: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_116: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_115: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_114: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_113: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_112: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_111: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_110: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_109: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_108: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_107: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_106: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_105: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_104: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_103: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_102: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_101: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_100: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_99: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_98: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_97: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_96: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_95: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_94: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_93: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_92: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_91: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_90: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_89: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_88: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_87: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_86: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_85: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_84: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_83: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_82: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_81: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_80: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_79: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_78: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_77: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_76: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_75: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_74: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_73: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_72: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_71: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_70: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_69: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_68: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_67: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_66: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_65: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_64: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_63: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_62: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_61: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_60: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_59: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_58: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_57: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_56: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_55: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_54: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_53: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - mux_8: MUX21 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, - Z=>Q(0)); - - mux_7: MUX21 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, - Z=>Q(1)); - - mux_6: MUX21 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, - Z=>Q(2)); - - mux_5: MUX21 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, - Z=>Q(3)); - - mux_4: MUX21 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, - Z=>Q(4)); - - mux_3: MUX21 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, - Z=>Q(5)); - - mux_2: MUX21 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, - Z=>Q(6)); - - mux_1: MUX21 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, - Z=>Q(7)); - - mux_0: MUX21 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, - Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_4096x9 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX21 use entity ecp3.MUX21(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_4096x9_generate.log b/gbe2_ecp3/ipcores/fifo_4096x9_generate.log deleted file mode 100755 index 9df407a..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x9_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v72_SP2_Build (23) -Tue Jan 5 23:44:15 2010 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x9 - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x9.vhd - VHDL template : fifo_4096x9_tmpl.vhd - VHDL testbench : tb_fifo_4096x9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x9.srp - Estimated Resource Usage: - LUT : 138 - EBR : 2 - Reg : 133 - -END SCUBA Module Synthesis - -File: fifo_4096x9.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_4096x9_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_4096x9_tmpl.vhd deleted file mode 100755 index 8b69bd4..0000000 --- a/gbe2_ecp3/ipcores/fifo_4096x9_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:24:06 2011 - --- parameterized module component declaration -component fifo_4096x9 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x9 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores/fifo_512x32.lpc b/gbe2_ecp3/ipcores/fifo_512x32.lpc deleted file mode 100644 index 78c1782..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x32.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x32 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=05/26/2011 -Time=17:17:59 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=32 -RDepth=512 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_512x32.vhd b/gbe2_ecp3/ipcores/fifo_512x32.vhd deleted file mode 100644 index 583f135..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x32.vhd +++ /dev/null @@ -1,1604 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.1_Production (517) --- Module Version: 5.4 ---/opt/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - --- Thu May 26 17:17:59 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_512x32 is - port ( - Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_512x32; - -architecture Structure of fifo_512x32 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KB - -- synopsys translate_off - generic (CSDECODE_R : in std_logic_vector(2 downto 0); - CSDECODE_W : in std_logic_vector(2 downto 0); - GSR : in String; RESETMODE : in String; - REGMODE : in String; DATA_WIDTH_R : in Integer; - DATA_WIDTH_W : in Integer); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_R : string; - attribute CSDECODE_W : string; - attribute RESETMODE : string; - attribute REGMODE : string; - attribute DATA_WIDTH_R : string; - attribute DATA_WIDTH_W : string; - attribute GSR : string; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000"; - attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001"; - attribute GSR of pdp_ram_0_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; - attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG"; - attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36"; - attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t20: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: PDPW16KB - -- synopsys translate_off - generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, - DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, - DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, - ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open, - DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), - DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), - DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), - DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); - - FF_101: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_512x32 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_512x64.jhd b/gbe2_ecp3/ipcores/fifo_512x64.jhd deleted file mode 100644 index fbe81ea..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x64.jhd +++ /dev/null @@ -1,359 +0,0 @@ -MODULE fifo_512x64 DEFIN fifo_512x64.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1P3DX - INSTANCE FF_42 - SUBMODULE FD1P3DX - INSTANCE FF_43 - SUBMODULE FD1P3DX - INSTANCE FF_44 - SUBMODULE FD1P3DX - INSTANCE FF_45 - SUBMODULE FD1P3DX - INSTANCE FF_46 - SUBMODULE FD1P3DX - INSTANCE FF_47 - SUBMODULE FD1P3DX - INSTANCE FF_48 - SUBMODULE FD1P3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3BX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3BX - INSTANCE FF_101 - SUBMODULE PDPW16KB - INSTANCE pdp_ram_0_1_0 - SUBMODULE PDPW16KB - INSTANCE pdp_ram_0_0_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_0 - SUBMODULE ROM16X1 - INSTANCE LUT4_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_2 - SUBMODULE ROM16X1 - INSTANCE LUT4_3 - SUBMODULE ROM16X1 - INSTANCE LUT4_4 - SUBMODULE ROM16X1 - INSTANCE LUT4_5 - SUBMODULE ROM16X1 - INSTANCE LUT4_6 - SUBMODULE ROM16X1 - INSTANCE LUT4_7 - SUBMODULE ROM16X1 - INSTANCE LUT4_8 - SUBMODULE ROM16X1 - INSTANCE LUT4_9 - SUBMODULE ROM16X1 - INSTANCE LUT4_10 - SUBMODULE ROM16X1 - INSTANCE LUT4_11 - SUBMODULE ROM16X1 - INSTANCE LUT4_12 - SUBMODULE ROM16X1 - INSTANCE LUT4_13 - SUBMODULE ROM16X1 - INSTANCE LUT4_14 - SUBMODULE ROM16X1 - INSTANCE LUT4_15 - SUBMODULE ROM16X1 - INSTANCE LUT4_16 - SUBMODULE ROM16X1 - INSTANCE LUT4_17 - SUBMODULE ROM16X1 - INSTANCE LUT4_18 - SUBMODULE ROM16X1 - INSTANCE LUT4_19 - SUBMODULE ROM16X1 - INSTANCE LUT4_20 - SUBMODULE ROM16X1 - INSTANCE LUT4_21 - SUBMODULE ROM16X1 - INSTANCE LUT4_22 - SUBMODULE ROM16X1 - INSTANCE LUT4_23 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE OR2 - INSTANCE OR2_t18 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t19 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t20 diff --git a/gbe2_ecp3/ipcores/fifo_512x64.lpc b/gbe2_ecp3/ipcores/fifo_512x64.lpc deleted file mode 100644 index f7b5a40..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x64.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x64 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=06/01/2011 -Time=17:13:21 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=72 -RDepth=512 -RWidth=72 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_512x64.naf b/gbe2_ecp3/ipcores/fifo_512x64.naf deleted file mode 100644 index 8a50577..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x64.naf +++ /dev/null @@ -1,152 +0,0 @@ -Data[71] i -Data[70] i -Data[69] i -Data[68] i -Data[67] i -Data[66] i -Data[65] i -Data[64] i -Data[63] i -Data[62] i -Data[61] i -Data[60] i -Data[59] i -Data[58] i -Data[57] i -Data[56] i -Data[55] i -Data[54] i -Data[53] i -Data[52] i -Data[51] i -Data[50] i -Data[49] i -Data[48] i -Data[47] i -Data[46] i -Data[45] i -Data[44] i -Data[43] i -Data[42] i -Data[41] i -Data[40] i -Data[39] i -Data[38] i -Data[37] i -Data[36] i -Data[35] i -Data[34] i -Data[33] i -Data[32] i -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[71] o -Q[70] o -Q[69] o -Q[68] o -Q[67] o -Q[66] o -Q[65] o -Q[64] o -Q[63] o -Q[62] o -Q[61] o -Q[60] o -Q[59] o -Q[58] o -Q[57] o -Q[56] o -Q[55] o -Q[54] o -Q[53] o -Q[52] o -Q[51] o -Q[50] o -Q[49] o -Q[48] o -Q[47] o -Q[46] o -Q[45] o -Q[44] o -Q[43] o -Q[42] o -Q[41] o -Q[40] o -Q[39] o -Q[38] o -Q[37] o -Q[36] o -Q[35] o -Q[34] o -Q[33] o -Q[32] o -Q[31] o -Q[30] o -Q[29] o -Q[28] o -Q[27] o -Q[26] o -Q[25] o -Q[24] o -Q[23] o -Q[22] o -Q[21] o -Q[20] o -Q[19] o -Q[18] o -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores/fifo_512x64.srp b/gbe2_ecp3/ipcores/fifo_512x64.srp deleted file mode 100644 index 28cbb90..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x64.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version ispLever_v8.1_PROD_Build (20) -Wed Jun 1 17:13:21 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x64 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x64.vhd - VHDL template : fifo_512x64_tmpl.vhd - VHDL testbench : tb_fifo_512x64_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x64.srp - Element Usage : - AGEB2 : 10 - AND2 : 2 - CU2 : 10 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 58 - FD1S3BX : 1 - FD1S3DX : 41 - INV : 2 - OR2 : 1 - ROM16X1 : 24 - XOR2 : 18 - PDPW16KB : 2 - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 diff --git a/gbe2_ecp3/ipcores/fifo_512x64.sym b/gbe2_ecp3/ipcores/fifo_512x64.sym deleted file mode 100644 index acb66e1b6154b37fd474e194124f9abcdce27c55..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 434 zcmX|-ze~eV6ot>Ftwjat;4B%6gM+l<59m}d$!ZKrK~X8D1vR#zMrpUwKcHk3CkJs+ zBse)1XNL^V($US%PM*A^4)5jTyLso``<`o0y&o$B;8n8Rfss^2!;-8DupkwhDppX` z33GbguODueE2SgAq6nZTmAvh2yY15pIJ6NC5}UOhqXl&7CTJxtXE&}IK8AD!8B9-G ziG85;aGTm%C&_%H4e^p@);e+KC;JTXj-vSi*JTT89{z`I?R7{alU!hY@ckD*SeeQSe7wLV(|1B1sGBh!9BC%d{c3#`mkk| zzOS;6>Eqcnu5-l`Xzb}maYT+VP#ls&3>63D0C$Q#vWG`z#&552@#*;m@2JWj-WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: PDPW16KB - -- synopsys translate_off - generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, - DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), - DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, - ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, - ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), - DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), - DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), - DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), - DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), - DO35=>Q(17)); - - pdp_ram_0_1_0: PDPW16KB - -- synopsys translate_off - generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, - DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), - DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), - DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), - DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), - DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), - DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), - DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), - DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), - DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), - DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), - DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), - DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, - ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, - ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, - BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, - CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, - ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, - ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, - ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, - ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), - DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), - DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), - DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), - DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), - DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), - DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), - DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), - DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); - - FF_101: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_512x64 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_512x64_generate.log b/gbe2_ecp3/ipcores/fifo_512x64_generate.log deleted file mode 100644 index d5d2a1f..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x64_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v8.1_PROD_Build (20) -Wed Jun 1 17:13:21 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x64 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x64.vhd - VHDL template : fifo_512x64_tmpl.vhd - VHDL testbench : tb_fifo_512x64_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x64.srp - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 - -END SCUBA Module Synthesis - -File: fifo_512x64.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_512x64_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_512x64_tmpl.vhd deleted file mode 100644 index e0d6ffc..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x64_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.1_PROD_Build (20) --- Module Version: 5.4 --- Wed Jun 1 17:13:21 2011 - --- parameterized module component declaration -component fifo_512x64 - port (Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x64 - port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores/fifo_512x72.jhd b/gbe2_ecp3/ipcores/fifo_512x72.jhd deleted file mode 100644 index c02a40f..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x72.jhd +++ /dev/null @@ -1,359 +0,0 @@ -MODULE fifo_512x72 DEFIN fifo_512x72.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1P3DX - INSTANCE FF_42 - SUBMODULE FD1P3DX - INSTANCE FF_43 - SUBMODULE FD1P3DX - INSTANCE FF_44 - SUBMODULE FD1P3DX - INSTANCE FF_45 - SUBMODULE FD1P3DX - INSTANCE FF_46 - SUBMODULE FD1P3DX - INSTANCE FF_47 - SUBMODULE FD1P3DX - INSTANCE FF_48 - SUBMODULE FD1P3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3BX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3BX - INSTANCE FF_101 - SUBMODULE PDPW16KB - INSTANCE pdp_ram_0_1_0 - SUBMODULE PDPW16KB - INSTANCE pdp_ram_0_0_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_0 - SUBMODULE ROM16X1 - INSTANCE LUT4_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_2 - SUBMODULE ROM16X1 - INSTANCE LUT4_3 - SUBMODULE ROM16X1 - INSTANCE LUT4_4 - SUBMODULE ROM16X1 - INSTANCE LUT4_5 - SUBMODULE ROM16X1 - INSTANCE LUT4_6 - SUBMODULE ROM16X1 - INSTANCE LUT4_7 - SUBMODULE ROM16X1 - INSTANCE LUT4_8 - SUBMODULE ROM16X1 - INSTANCE LUT4_9 - SUBMODULE ROM16X1 - INSTANCE LUT4_10 - SUBMODULE ROM16X1 - INSTANCE LUT4_11 - SUBMODULE ROM16X1 - INSTANCE LUT4_12 - SUBMODULE ROM16X1 - INSTANCE LUT4_13 - SUBMODULE ROM16X1 - INSTANCE LUT4_14 - SUBMODULE ROM16X1 - INSTANCE LUT4_15 - SUBMODULE ROM16X1 - INSTANCE LUT4_16 - SUBMODULE ROM16X1 - INSTANCE LUT4_17 - SUBMODULE ROM16X1 - INSTANCE LUT4_18 - SUBMODULE ROM16X1 - INSTANCE LUT4_19 - SUBMODULE ROM16X1 - INSTANCE LUT4_20 - SUBMODULE ROM16X1 - INSTANCE LUT4_21 - SUBMODULE ROM16X1 - INSTANCE LUT4_22 - SUBMODULE ROM16X1 - INSTANCE LUT4_23 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE OR2 - INSTANCE OR2_t18 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t19 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t20 diff --git a/gbe2_ecp3/ipcores/fifo_512x72.lpc b/gbe2_ecp3/ipcores/fifo_512x72.lpc deleted file mode 100644 index 195818a..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x72.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x72 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=06/01/2011 -Time=17:14:00 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=72 -RDepth=512 -RWidth=72 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_512x72.naf b/gbe2_ecp3/ipcores/fifo_512x72.naf deleted file mode 100644 index 8a50577..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x72.naf +++ /dev/null @@ -1,152 +0,0 @@ -Data[71] i -Data[70] i -Data[69] i -Data[68] i -Data[67] i -Data[66] i -Data[65] i -Data[64] i -Data[63] i -Data[62] i -Data[61] i -Data[60] i -Data[59] i -Data[58] i -Data[57] i -Data[56] i -Data[55] i -Data[54] i -Data[53] i -Data[52] i -Data[51] i -Data[50] i -Data[49] i -Data[48] i -Data[47] i -Data[46] i -Data[45] i -Data[44] i -Data[43] i -Data[42] i -Data[41] i -Data[40] i -Data[39] i -Data[38] i -Data[37] i -Data[36] i -Data[35] i -Data[34] i -Data[33] i -Data[32] i -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[71] o -Q[70] o -Q[69] o -Q[68] o -Q[67] o -Q[66] o -Q[65] o -Q[64] o -Q[63] o -Q[62] o -Q[61] o -Q[60] o -Q[59] o -Q[58] o -Q[57] o -Q[56] o -Q[55] o -Q[54] o -Q[53] o -Q[52] o -Q[51] o -Q[50] o -Q[49] o -Q[48] o -Q[47] o -Q[46] o -Q[45] o -Q[44] o -Q[43] o -Q[42] o -Q[41] o -Q[40] o -Q[39] o -Q[38] o -Q[37] o -Q[36] o -Q[35] o -Q[34] o -Q[33] o -Q[32] o -Q[31] o -Q[30] o -Q[29] o -Q[28] o -Q[27] o -Q[26] o -Q[25] o -Q[24] o -Q[23] o -Q[22] o -Q[21] o -Q[20] o -Q[19] o -Q[18] o -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores/fifo_512x72.srp b/gbe2_ecp3/ipcores/fifo_512x72.srp deleted file mode 100644 index 17b4826..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x72.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version ispLever_v8.1_PROD_Build (20) -Wed Jun 1 17:14:00 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x72 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x72.vhd - VHDL template : fifo_512x72_tmpl.vhd - VHDL testbench : tb_fifo_512x72_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x72.srp - Element Usage : - AGEB2 : 10 - AND2 : 2 - CU2 : 10 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 58 - FD1S3BX : 1 - FD1S3DX : 41 - INV : 2 - OR2 : 1 - ROM16X1 : 24 - XOR2 : 18 - PDPW16KB : 2 - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 diff --git a/gbe2_ecp3/ipcores/fifo_512x72.sym b/gbe2_ecp3/ipcores/fifo_512x72.sym deleted file mode 100644 index 26a0ded4597432a0727a6c2ca2b8e04a6dd2a275..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 434 zcmX|-F-yZx6ot>Ftwjat;4B%6gM+jMDRc_hWHkmQpr{nnf?C^9qqJM;4=5drlY=;k z1SiMf?2y4(I=b1}$&;7V;k|r(H}AZA-?I}Aeyj|DSIKe*LeWLThHMM4CN&xzTPW5E zEA@uoIIfm!r4zuSn4q3i^0vF%?w()4rHycu*sSdu9iUG)M<;PPyLr>}F{UfXXmQ#~ z>?5s*X=_6=ms+jg6! zv=+}d#4l@0g8cqsnE&efYU`raJ=-Z)`qc_HWrmU%JUv4JhSWsx!0b5RR2-;2Y+0rs ys_awxcs7meQt=!bd%9B`kt2*02jl=_#S`)b_liBThbLynZ?AFj>G=ik(B%&Tf>SX7 diff --git a/gbe2_ecp3/ipcores/fifo_512x72.vhd b/gbe2_ecp3/ipcores/fifo_512x72.vhd deleted file mode 100644 index 0c53486..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x72.vhd +++ /dev/null @@ -1,1651 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20) --- Module Version: 5.4 ---/opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - --- Wed Jun 1 17:14:00 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_512x72 is - port ( - Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_512x72; - -architecture Structure of fifo_512x72 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KB - -- synopsys translate_off - generic (CSDECODE_R : in std_logic_vector(2 downto 0); - CSDECODE_W : in std_logic_vector(2 downto 0); - GSR : in String; RESETMODE : in String; - REGMODE : in String; DATA_WIDTH_R : in Integer; - DATA_WIDTH_W : in Integer); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_R : string; - attribute CSDECODE_W : string; - attribute RESETMODE : string; - attribute REGMODE : string; - attribute DATA_WIDTH_R : string; - attribute DATA_WIDTH_W : string; - attribute GSR : string; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute CSDECODE_R of pdp_ram_0_0_1 : label is "0b000"; - attribute CSDECODE_W of pdp_ram_0_0_1 : label is "0b001"; - attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; - attribute REGMODE of pdp_ram_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "36"; - attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "36"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute CSDECODE_R of pdp_ram_0_1_0 : label is "0b000"; - attribute CSDECODE_W of pdp_ram_0_1_0 : label is "0b001"; - attribute GSR of pdp_ram_0_1_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC"; - attribute REGMODE of pdp_ram_0_1_0 : label is "NOREG"; - attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "36"; - attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "36"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t20: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: PDPW16KB - -- synopsys translate_off - generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, - DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), - DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, - ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, - ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), - DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), - DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), - DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), - DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), - DO35=>Q(17)); - - pdp_ram_0_1_0: PDPW16KB - -- synopsys translate_off - generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, - DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), - DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), - DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), - DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), - DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), - DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), - DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), - DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), - DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), - DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), - DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), - DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, - ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, - ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, - BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, - CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, - ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, - ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, - ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, - ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), - DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), - DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), - DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), - DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), - DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), - DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), - DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), - DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); - - FF_101: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_512x72 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_512x72_generate.log b/gbe2_ecp3/ipcores/fifo_512x72_generate.log deleted file mode 100644 index c53ba2c..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x72_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v8.1_PROD_Build (20) -Wed Jun 1 17:14:00 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x72 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x72.vhd - VHDL template : fifo_512x72_tmpl.vhd - VHDL testbench : tb_fifo_512x72_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x72.srp - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 - -END SCUBA Module Synthesis - -File: fifo_512x72.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_512x72_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_512x72_tmpl.vhd deleted file mode 100644 index f77cba8..0000000 --- a/gbe2_ecp3/ipcores/fifo_512x72_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.1_PROD_Build (20) --- Module Version: 5.4 --- Wed Jun 1 17:14:00 2011 - --- parameterized module component declaration -component fifo_512x72 - port (Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x72 - port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores/fifo_64kx8.jhd b/gbe2_ecp3/ipcores/fifo_64kx8.jhd deleted file mode 100755 index 4128450..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx8.jhd +++ /dev/null @@ -1,711 +0,0 @@ -MODULE fifo_64kx8 DEFIN fifo_64kx8.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_8 - SUBMODULE AGEB2 - INSTANCE full_cmp_7 - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_8 - SUBMODULE AGEB2 - INSTANCE empty_cmp_7 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE MUX41 - INSTANCE mux_0 - SUBMODULE MUX41 - INSTANCE mux_1 - SUBMODULE MUX41 - INSTANCE mux_2 - SUBMODULE MUX41 - INSTANCE mux_3 - SUBMODULE MUX41 - INSTANCE mux_4 - SUBMODULE MUX41 - INSTANCE mux_5 - SUBMODULE MUX41 - INSTANCE mux_6 - SUBMODULE MUX41 - INSTANCE mux_7 - SUBMODULE CU2 - INSTANCE r_gctr_8 - SUBMODULE CU2 - INSTANCE r_gctr_7 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_8 - SUBMODULE CU2 - INSTANCE w_gctr_7 - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1S3DX - INSTANCE FF_54 - SUBMODULE FD1S3DX - INSTANCE FF_55 - SUBMODULE FD1S3DX - INSTANCE FF_56 - SUBMODULE FD1S3DX - INSTANCE FF_57 - SUBMODULE FD1S3DX - INSTANCE FF_58 - SUBMODULE FD1S3DX - INSTANCE FF_59 - SUBMODULE FD1S3DX - INSTANCE FF_60 - SUBMODULE FD1S3DX - INSTANCE FF_61 - SUBMODULE FD1S3DX - INSTANCE FF_62 - SUBMODULE FD1S3DX - INSTANCE FF_63 - SUBMODULE FD1S3DX - INSTANCE FF_64 - SUBMODULE FD1S3DX - INSTANCE FF_65 - SUBMODULE FD1S3DX - INSTANCE FF_66 - SUBMODULE FD1S3DX - INSTANCE FF_67 - SUBMODULE FD1S3DX - INSTANCE FF_68 - SUBMODULE FD1S3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3DX - INSTANCE FF_121 - SUBMODULE FD1P3BX - INSTANCE FF_122 - SUBMODULE FD1P3DX - INSTANCE FF_123 - SUBMODULE FD1P3DX - INSTANCE FF_124 - SUBMODULE FD1P3DX - INSTANCE FF_125 - SUBMODULE FD1P3DX - INSTANCE FF_126 - SUBMODULE FD1P3DX - INSTANCE FF_127 - SUBMODULE FD1P3DX - INSTANCE FF_128 - SUBMODULE FD1P3DX - INSTANCE FF_129 - SUBMODULE FD1P3DX - INSTANCE FF_130 - SUBMODULE FD1P3DX - INSTANCE FF_131 - SUBMODULE FD1P3DX - INSTANCE FF_132 - SUBMODULE FD1P3DX - INSTANCE FF_133 - SUBMODULE FD1P3DX - INSTANCE FF_134 - SUBMODULE FD1P3DX - INSTANCE FF_135 - SUBMODULE FD1P3DX - INSTANCE FF_136 - SUBMODULE FD1P3DX - INSTANCE FF_137 - SUBMODULE FD1P3DX - INSTANCE FF_138 - SUBMODULE FD1P3DX - INSTANCE FF_139 - SUBMODULE FD1P3DX - INSTANCE FF_140 - SUBMODULE FD1P3DX - INSTANCE FF_141 - SUBMODULE FD1P3DX - INSTANCE FF_142 - SUBMODULE FD1P3DX - INSTANCE FF_143 - SUBMODULE FD1P3DX - INSTANCE FF_144 - SUBMODULE FD1P3DX - INSTANCE FF_145 - SUBMODULE FD1P3DX - INSTANCE FF_146 - SUBMODULE FD1P3DX - INSTANCE FF_147 - SUBMODULE FD1P3DX - INSTANCE FF_148 - SUBMODULE FD1P3DX - INSTANCE FF_149 - SUBMODULE FD1P3DX - INSTANCE FF_150 - SUBMODULE FD1P3DX - INSTANCE FF_151 - SUBMODULE FD1P3DX - INSTANCE FF_152 - SUBMODULE FD1P3DX - INSTANCE FF_153 - SUBMODULE FD1P3DX - INSTANCE FF_154 - SUBMODULE FD1P3DX - INSTANCE FF_155 - SUBMODULE FD1P3DX - INSTANCE FF_156 - SUBMODULE FD1P3DX - INSTANCE FF_157 - SUBMODULE FD1P3DX - INSTANCE FF_158 - SUBMODULE FD1P3DX - INSTANCE FF_159 - SUBMODULE FD1P3DX - INSTANCE FF_160 - SUBMODULE FD1P3DX - INSTANCE FF_161 - SUBMODULE FD1P3DX - INSTANCE FF_162 - SUBMODULE FD1P3DX - INSTANCE FF_163 - SUBMODULE FD1P3DX - INSTANCE FF_164 - SUBMODULE FD1P3DX - INSTANCE FF_165 - SUBMODULE FD1P3DX - INSTANCE FF_166 - SUBMODULE FD1P3DX - INSTANCE FF_167 - SUBMODULE FD1P3DX - INSTANCE FF_168 - SUBMODULE FD1P3DX - INSTANCE FF_169 - SUBMODULE FD1P3DX - INSTANCE FF_170 - SUBMODULE FD1P3DX - INSTANCE FF_171 - SUBMODULE FD1P3DX - INSTANCE FF_172 - SUBMODULE FD1P3BX - INSTANCE FF_173 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_7_0 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_6_1 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_5_2 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_4_3 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_3_4 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_2_5 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_1_6 - SUBMODULE DP16KB - INSTANCE pdp_ram_3_0_7 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_7_8 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_6_9 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_5_10 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_4_11 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_3_12 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_2_13 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_1_14 - SUBMODULE DP16KB - INSTANCE pdp_ram_2_0_15 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_7_16 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_6_17 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_5_18 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_4_19 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_3_20 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_2_21 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_1_22 - SUBMODULE DP16KB - INSTANCE pdp_ram_1_0_23 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_7_24 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_6_25 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_5_26 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_4_27 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_3_28 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_2_29 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_1_30 - SUBMODULE DP16KB - INSTANCE pdp_ram_0_0_31 - SUBMODULE ROM16X1 - INSTANCE LUT4_0 - SUBMODULE ROM16X1 - INSTANCE LUT4_1 - SUBMODULE ROM16X1 - INSTANCE LUT4_2 - SUBMODULE ROM16X1 - INSTANCE LUT4_3 - SUBMODULE ROM16X1 - INSTANCE LUT4_4 - SUBMODULE ROM16X1 - INSTANCE LUT4_5 - SUBMODULE ROM16X1 - INSTANCE LUT4_6 - SUBMODULE ROM16X1 - INSTANCE LUT4_7 - SUBMODULE ROM16X1 - INSTANCE LUT4_8 - SUBMODULE ROM16X1 - INSTANCE LUT4_9 - SUBMODULE ROM16X1 - INSTANCE LUT4_10 - SUBMODULE ROM16X1 - INSTANCE LUT4_11 - SUBMODULE ROM16X1 - INSTANCE LUT4_12 - SUBMODULE ROM16X1 - INSTANCE LUT4_13 - SUBMODULE ROM16X1 - INSTANCE LUT4_14 - SUBMODULE ROM16X1 - INSTANCE LUT4_15 - SUBMODULE ROM16X1 - INSTANCE LUT4_16 - SUBMODULE ROM16X1 - INSTANCE LUT4_17 - SUBMODULE ROM16X1 - INSTANCE LUT4_18 - SUBMODULE ROM16X1 - INSTANCE LUT4_19 - SUBMODULE ROM16X1 - INSTANCE LUT4_20 - SUBMODULE ROM16X1 - INSTANCE LUT4_21 - SUBMODULE ROM16X1 - INSTANCE LUT4_22 - SUBMODULE ROM16X1 - INSTANCE LUT4_23 - SUBMODULE ROM16X1 - INSTANCE LUT4_24 - SUBMODULE ROM16X1 - INSTANCE LUT4_25 - SUBMODULE ROM16X1 - INSTANCE LUT4_26 - SUBMODULE ROM16X1 - INSTANCE LUT4_27 - SUBMODULE ROM16X1 - INSTANCE LUT4_28 - SUBMODULE ROM16X1 - INSTANCE LUT4_29 - SUBMODULE ROM16X1 - INSTANCE LUT4_30 - SUBMODULE ROM16X1 - INSTANCE LUT4_31 - SUBMODULE ROM16X1 - INSTANCE LUT4_32 - SUBMODULE ROM16X1 - INSTANCE LUT4_33 - SUBMODULE ROM16X1 - INSTANCE LUT4_34 - SUBMODULE ROM16X1 - INSTANCE LUT4_35 - SUBMODULE ROM16X1 - INSTANCE LUT4_36 - SUBMODULE ROM16X1 - INSTANCE LUT4_37 - SUBMODULE ROM16X1 - INSTANCE LUT4_38 - SUBMODULE ROM16X1 - INSTANCE LUT4_39 - SUBMODULE ROM16X1 - INSTANCE LUT4_40 - SUBMODULE ROM16X1 - INSTANCE LUT4_41 - SUBMODULE ROM16X1 - INSTANCE LUT4_42 - SUBMODULE ROM16X1 - INSTANCE LUT4_43 - SUBMODULE ROM16X1 - INSTANCE LUT4_44 - SUBMODULE ROM16X1 - INSTANCE LUT4_45 - SUBMODULE ROM16X1 - INSTANCE LUT4_46 - SUBMODULE ROM16X1 - INSTANCE LUT4_47 - SUBMODULE ROM16X1 - INSTANCE LUT4_48 - SUBMODULE ROM16X1 - INSTANCE LUT4_49 - SUBMODULE ROM16X1 - INSTANCE LUT4_50 - SUBMODULE ROM16X1 - INSTANCE LUT4_51 - SUBMODULE ROM16X1 - INSTANCE LUT4_52 - SUBMODULE ROM16X1 - INSTANCE LUT4_53 - SUBMODULE ROM16X1 - INSTANCE LUT4_54 - SUBMODULE ROM16X1 - INSTANCE LUT4_55 - SUBMODULE ROM16X1 - INSTANCE LUT4_56 - SUBMODULE ROM16X1 - INSTANCE LUT4_57 - SUBMODULE ROM16X1 - INSTANCE LUT4_58 - SUBMODULE ROM16X1 - INSTANCE LUT4_59 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE XOR2 - INSTANCE XOR2_t24 - SUBMODULE XOR2 - INSTANCE XOR2_t25 - SUBMODULE XOR2 - INSTANCE XOR2_t26 - SUBMODULE XOR2 - INSTANCE XOR2_t27 - SUBMODULE XOR2 - INSTANCE XOR2_t28 - SUBMODULE XOR2 - INSTANCE XOR2_t29 - SUBMODULE XOR2 - INSTANCE XOR2_t30 - SUBMODULE XOR2 - INSTANCE XOR2_t31 - SUBMODULE OR2 - INSTANCE OR2_t32 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t33 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t34 diff --git a/gbe2_ecp3/ipcores/fifo_64kx8.lpc b/gbe2_ecp3/ipcores/fifo_64kx8.lpc deleted file mode 100755 index badffb2..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_64kx8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:03 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=65536 -Width=8 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_64kx8.naf b/gbe2_ecp3/ipcores/fifo_64kx8.naf deleted file mode 100755 index 9da2be9..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx8.naf +++ /dev/null @@ -1,24 +0,0 @@ -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores/fifo_64kx8.srp b/gbe2_ecp3/ipcores/fifo_64kx8.srp deleted file mode 100755 index 56a2b66..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx8.srp +++ /dev/null @@ -1,43 +0,0 @@ -SCUBA, Version ispLever_v72_SP2_Build (23) -Sat Dec 26 00:12:05 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx8 - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx8.vhd - VHDL template : fifo_64kx8_tmpl.vhd - VHDL testbench : tb_fifo_64kx8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx8.srp - Element Usage : - AGEB2 : 18 - AND2 : 2 - CU2 : 18 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 102 - FD1S3BX : 1 - FD1S3DX : 69 - INV : 2 - MUX41 : 8 - OR2 : 1 - ROM16X1 : 60 - XOR2 : 32 - DP16KB : 32 - Estimated Resource Usage: - LUT : 187 - EBR : 32 - Reg : 174 diff --git a/gbe2_ecp3/ipcores/fifo_64kx8.sym b/gbe2_ecp3/ipcores/fifo_64kx8.sym deleted file mode 100755 index b2811a4caeb65eb7be00c6bcbdae9eba63ace513..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 432 zcmYk2F-XHe7=_DeBgQG)+OybZ%v^WJ#I%*9{1Qn^aMQOC5M$s*UV~0-SDB{@R zCP8p;b_&kUZc0W+UoH_GF8T7kyT|>R_&3jAFC_p<3_gK-vBkukEC?_o4H_HsupC0g zX-Dnd<(2wA*7-TcYVN1K&RQ@y>f?|$!A@=suj8HpmvkwD+?BoVc{jp{t|sx{=~iwZ zXhYl<)*t4bPqYe?qSGH{o$tJ*!Yi!i8&Gyn!|0m3q_nZUg>PmFKA3$1M)M*F7!_GI zU5p=QhG1$lALU;WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t33: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t32: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t31: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t30: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t29: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t28: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t27: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t26: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t25: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t24: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t23: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t22: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t21: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t20: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t19: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t18: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t17: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t16: XOR2 - port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - LUT4_59: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>w_gcount_r216, - DO0=>w_g2b_xor_cluster_0); - - LUT4_58: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_1); - - LUT4_57: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_2); - - LUT4_56: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_3); - - LUT4_55: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r15); - - LUT4_54: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, - AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_53: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, - DO0=>wcount_r10); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r3); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r2); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_10); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, - AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, - DO0=>func_xor_inet_11); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_1_30: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_2_29: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_3_28: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_4_27: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_5_26: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_6_25: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_7_24: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_1_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_2_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_3_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_4_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_5_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_6_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_7_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_15: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_1_14: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_2_13: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_3_12: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_4_11: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_5_10: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_6_9: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_7_8: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_7: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_1_6: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_2_5: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_3_4: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_4_3: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_5_2: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_6_1: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_7_0: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_173: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_172: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_171: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_170: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_169: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_168: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_167: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_166: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_165: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_164: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_163: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_162: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_161: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_160: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_159: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_158: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_157: FD1P3DX - port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_16); - - FF_156: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_155: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_154: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_153: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_152: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_151: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_150: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_149: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_148: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_147: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_146: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_145: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_144: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_143: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_142: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_141: FD1P3DX - port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_140: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_16); - - FF_139: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_138: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_137: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_136: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_135: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_134: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_133: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_132: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_131: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_130: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_129: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_128: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_127: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_126: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_125: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_124: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_123: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_16); - - FF_122: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_121: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_120: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_119: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_118: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_117: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_116: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_115: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_114: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_113: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_112: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_111: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_110: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_109: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_108: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_107: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_106: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_105: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_104: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_103: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_102: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_101: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_100: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_99: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_98: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_97: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_96: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_95: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_94: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_93: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_92: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_91: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_90: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_89: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_88: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_87: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_86: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_85: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_84: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_83: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_82: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_81: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_80: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_79: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_78: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_77: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_76: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_75: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_74: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_73: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_72: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_71: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_70: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_69: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_68: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_67: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_66: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_65: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_64: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_63: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_62: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_61: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_60: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_59: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_58: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_57: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_56: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_55: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_54: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_53: FD1S3DX - port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r16); - - FF_52: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_51: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_50: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_49: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_48: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_47: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_46: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_45: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_44: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_43: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_42: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_41: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_40: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_39: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_38: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_37: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_36: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_35: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_34: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_33: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_32: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_31: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_30: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_29: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_28: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_27: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_26: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_25: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_24: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_23: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_22: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_21: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_20: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_19: FD1S3DX - port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r216); - - FF_18: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - w_gctr_8: CU2 - port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>iwcount_16, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, - NC0=>ircount_16, NC1=>open); - - mux_7: MUX41 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); - - mux_6: MUX41 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); - - mux_5: MUX41 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); - - mux_4: MUX41 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); - - mux_3: MUX41 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); - - mux_2: MUX41 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); - - mux_1: MUX41 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); - - mux_0: MUX41 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, - B1=>wcount_r15, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, - B1=>rcount_w15, CI=>co6_3, GE=>co7_3); - - full_cmp_8: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_64kx8 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX41 use entity ecp3.MUX41(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_64kx8_generate.log b/gbe2_ecp3/ipcores/fifo_64kx8_generate.log deleted file mode 100755 index 87e2dad..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx8_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v72_SP2_Build (23) -Sat Dec 26 00:12:05 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx8 - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx8.vhd - VHDL template : fifo_64kx8_tmpl.vhd - VHDL testbench : tb_fifo_64kx8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx8.srp - Estimated Resource Usage: - LUT : 187 - EBR : 32 - Reg : 174 - -END SCUBA Module Synthesis - -File: fifo_64kx8.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_64kx8_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_64kx8_tmpl.vhd deleted file mode 100755 index 9aba2ac..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:03 2011 - --- parameterized module component declaration -component fifo_64kx8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_64kx8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores/fifo_64kx9.lpc b/gbe2_ecp3/ipcores/fifo_64kx9.lpc deleted file mode 100644 index a9ca96b..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx9.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_64kx9 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:21 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=65536 -Width=9 -RDepth=65536 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores/fifo_64kx9.srp b/gbe2_ecp3/ipcores/fifo_64kx9.srp deleted file mode 100644 index 3f23449..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx9.srp +++ /dev/null @@ -1,43 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:21 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx9 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx9.vhd - VHDL template : fifo_64kx9_tmpl.vhd - VHDL testbench : tb_fifo_64kx9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx9.srp - Element Usage : - AGEB2 : 18 - AND2 : 2 - CU2 : 18 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 105 - FD1S3BX : 1 - FD1S3DX : 69 - INV : 12 - MUX321 : 9 - OR2 : 1 - ROM16X1A : 188 - XOR2 : 32 - DP16KC : 32 - Estimated Resource Usage: - LUT : 379 - EBR : 32 - Reg : 177 diff --git a/gbe2_ecp3/ipcores/fifo_64kx9.vhd b/gbe2_ecp3/ipcores/fifo_64kx9.vhd deleted file mode 100644 index 9ad1f19..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx9.vhd +++ /dev/null @@ -1,4582 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:23:21 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_64kx9 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_64kx9; - -architecture Structure of fifo_64kx9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal func_and_inet: std_logic; - signal func_and_inet_1: std_logic; - signal func_and_inet_2: std_logic; - signal func_and_inet_3: std_logic; - signal func_and_inet_4: std_logic; - signal func_and_inet_5: std_logic; - signal func_and_inet_6: std_logic; - signal func_and_inet_7: std_logic; - signal func_and_inet_8: std_logic; - signal func_and_inet_9: std_logic; - signal func_and_inet_10: std_logic; - signal func_and_inet_11: std_logic; - signal func_and_inet_12: std_logic; - signal func_and_inet_13: std_logic; - signal func_and_inet_14: std_logic; - signal func_and_inet_15: std_logic; - signal func_and_inet_16: std_logic; - signal func_and_inet_17: std_logic; - signal func_and_inet_18: std_logic; - signal func_and_inet_19: std_logic; - signal func_and_inet_20: std_logic; - signal func_and_inet_21: std_logic; - signal func_and_inet_22: std_logic; - signal func_and_inet_23: std_logic; - signal func_and_inet_24: std_logic; - signal func_and_inet_25: std_logic; - signal func_and_inet_26: std_logic; - signal func_and_inet_27: std_logic; - signal func_and_inet_28: std_logic; - signal func_and_inet_29: std_logic; - signal wptr_15_inv: std_logic; - signal func_and_inet_30: std_logic; - signal rptr_15_inv: std_logic; - signal func_and_inet_31: std_logic; - signal func_and_inet_32: std_logic; - signal func_and_inet_33: std_logic; - signal func_and_inet_34: std_logic; - signal func_and_inet_35: std_logic; - signal func_and_inet_36: std_logic; - signal func_and_inet_37: std_logic; - signal func_and_inet_38: std_logic; - signal func_and_inet_39: std_logic; - signal func_and_inet_40: std_logic; - signal func_and_inet_41: std_logic; - signal func_and_inet_42: std_logic; - signal func_and_inet_43: std_logic; - signal func_and_inet_44: std_logic; - signal func_and_inet_45: std_logic; - signal wptr_14_inv: std_logic; - signal func_and_inet_46: std_logic; - signal rptr_14_inv: std_logic; - signal func_and_inet_47: std_logic; - signal func_and_inet_48: std_logic; - signal func_and_inet_49: std_logic; - signal func_and_inet_50: std_logic; - signal func_and_inet_51: std_logic; - signal func_and_inet_52: std_logic; - signal func_and_inet_53: std_logic; - signal wptr_13_inv: std_logic; - signal func_and_inet_54: std_logic; - signal rptr_13_inv: std_logic; - signal func_and_inet_55: std_logic; - signal func_and_inet_56: std_logic; - signal func_and_inet_57: std_logic; - signal wptr_12_inv: std_logic; - signal func_and_inet_58: std_logic; - signal rptr_12_inv: std_logic; - signal func_and_inet_59: std_logic; - signal wptr_11_inv: std_logic; - signal func_and_inet_60: std_logic; - signal rptr_11_inv: std_logic; - signal func_and_inet_61: std_logic; - signal func_and_inet_62: std_logic; - signal func_and_inet_63: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_9: std_logic; - signal func_xor_inet_8: std_logic; - signal func_xor_inet_7: std_logic; - signal func_xor_inet_6: std_logic; - signal func_xor_inet_10: std_logic; - signal func_xor_inet_11: std_logic; - signal dec1_r10: std_logic; - signal dec0_p00: std_logic; - signal dec3_r11: std_logic; - signal dec2_p01: std_logic; - signal dec5_r12: std_logic; - signal dec4_p02: std_logic; - signal dec7_r13: std_logic; - signal dec6_p03: std_logic; - signal dec9_r14: std_logic; - signal dec8_p04: std_logic; - signal dec11_r15: std_logic; - signal dec10_p05: std_logic; - signal dec13_r16: std_logic; - signal dec12_p06: std_logic; - signal dec15_r17: std_logic; - signal dec14_p07: std_logic; - signal dec17_r18: std_logic; - signal dec16_p08: std_logic; - signal dec19_r19: std_logic; - signal dec18_p09: std_logic; - signal dec21_r110: std_logic; - signal dec20_p010: std_logic; - signal dec23_r111: std_logic; - signal dec22_p011: std_logic; - signal dec25_r112: std_logic; - signal dec24_p012: std_logic; - signal dec27_r113: std_logic; - signal dec26_p013: std_logic; - signal dec29_r114: std_logic; - signal dec28_p014: std_logic; - signal dec31_r115: std_logic; - signal dec30_p015: std_logic; - signal dec33_r116: std_logic; - signal dec32_p016: std_logic; - signal dec35_r117: std_logic; - signal dec34_p017: std_logic; - signal dec37_r118: std_logic; - signal dec36_p018: std_logic; - signal dec39_r119: std_logic; - signal dec38_p019: std_logic; - signal dec41_r120: std_logic; - signal dec40_p020: std_logic; - signal dec43_r121: std_logic; - signal dec42_p021: std_logic; - signal dec45_r122: std_logic; - signal dec44_p022: std_logic; - signal dec47_r123: std_logic; - signal dec46_p023: std_logic; - signal dec49_r124: std_logic; - signal dec48_p024: std_logic; - signal dec51_r125: std_logic; - signal dec50_p025: std_logic; - signal dec53_r126: std_logic; - signal dec52_p026: std_logic; - signal dec55_r127: std_logic; - signal dec54_p027: std_logic; - signal dec57_r128: std_logic; - signal dec56_p028: std_logic; - signal dec59_r129: std_logic; - signal dec58_p029: std_logic; - signal dec61_r130: std_logic; - signal dec60_p030: std_logic; - signal dec63_r131: std_logic; - signal dec62_p031: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal w_gdata_15: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wptr_15: std_logic; - signal wptr_16: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_16: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rptr_15: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal w_gcount_16: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal w_gcount_r216: std_logic; - signal w_gcount_r16: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co6: std_logic; - signal iwcount_16: std_logic; - signal co8: std_logic; - signal wcount_16: std_logic; - signal co7: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8_1: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_31_0: std_logic; - signal mdout1_30_0: std_logic; - signal mdout1_29_0: std_logic; - signal mdout1_28_0: std_logic; - signal mdout1_27_0: std_logic; - signal mdout1_26_0: std_logic; - signal mdout1_25_0: std_logic; - signal mdout1_24_0: std_logic; - signal mdout1_23_0: std_logic; - signal mdout1_22_0: std_logic; - signal mdout1_21_0: std_logic; - signal mdout1_20_0: std_logic; - signal mdout1_19_0: std_logic; - signal mdout1_18_0: std_logic; - signal mdout1_17_0: std_logic; - signal mdout1_16_0: std_logic; - signal mdout1_15_0: std_logic; - signal mdout1_14_0: std_logic; - signal mdout1_13_0: std_logic; - signal mdout1_12_0: std_logic; - signal mdout1_11_0: std_logic; - signal mdout1_10_0: std_logic; - signal mdout1_9_0: std_logic; - signal mdout1_8_0: std_logic; - signal mdout1_7_0: std_logic; - signal mdout1_6_0: std_logic; - signal mdout1_5_0: std_logic; - signal mdout1_4_0: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_31_1: std_logic; - signal mdout1_30_1: std_logic; - signal mdout1_29_1: std_logic; - signal mdout1_28_1: std_logic; - signal mdout1_27_1: std_logic; - signal mdout1_26_1: std_logic; - signal mdout1_25_1: std_logic; - signal mdout1_24_1: std_logic; - signal mdout1_23_1: std_logic; - signal mdout1_22_1: std_logic; - signal mdout1_21_1: std_logic; - signal mdout1_20_1: std_logic; - signal mdout1_19_1: std_logic; - signal mdout1_18_1: std_logic; - signal mdout1_17_1: std_logic; - signal mdout1_16_1: std_logic; - signal mdout1_15_1: std_logic; - signal mdout1_14_1: std_logic; - signal mdout1_13_1: std_logic; - signal mdout1_12_1: std_logic; - signal mdout1_11_1: std_logic; - signal mdout1_10_1: std_logic; - signal mdout1_9_1: std_logic; - signal mdout1_8_1: std_logic; - signal mdout1_7_1: std_logic; - signal mdout1_6_1: std_logic; - signal mdout1_5_1: std_logic; - signal mdout1_4_1: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_31_2: std_logic; - signal mdout1_30_2: std_logic; - signal mdout1_29_2: std_logic; - signal mdout1_28_2: std_logic; - signal mdout1_27_2: std_logic; - signal mdout1_26_2: std_logic; - signal mdout1_25_2: std_logic; - signal mdout1_24_2: std_logic; - signal mdout1_23_2: std_logic; - signal mdout1_22_2: std_logic; - signal mdout1_21_2: std_logic; - signal mdout1_20_2: std_logic; - signal mdout1_19_2: std_logic; - signal mdout1_18_2: std_logic; - signal mdout1_17_2: std_logic; - signal mdout1_16_2: std_logic; - signal mdout1_15_2: std_logic; - signal mdout1_14_2: std_logic; - signal mdout1_13_2: std_logic; - signal mdout1_12_2: std_logic; - signal mdout1_11_2: std_logic; - signal mdout1_10_2: std_logic; - signal mdout1_9_2: std_logic; - signal mdout1_8_2: std_logic; - signal mdout1_7_2: std_logic; - signal mdout1_6_2: std_logic; - signal mdout1_5_2: std_logic; - signal mdout1_4_2: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_31_3: std_logic; - signal mdout1_30_3: std_logic; - signal mdout1_29_3: std_logic; - signal mdout1_28_3: std_logic; - signal mdout1_27_3: std_logic; - signal mdout1_26_3: std_logic; - signal mdout1_25_3: std_logic; - signal mdout1_24_3: std_logic; - signal mdout1_23_3: std_logic; - signal mdout1_22_3: std_logic; - signal mdout1_21_3: std_logic; - signal mdout1_20_3: std_logic; - signal mdout1_19_3: std_logic; - signal mdout1_18_3: std_logic; - signal mdout1_17_3: std_logic; - signal mdout1_16_3: std_logic; - signal mdout1_15_3: std_logic; - signal mdout1_14_3: std_logic; - signal mdout1_13_3: std_logic; - signal mdout1_12_3: std_logic; - signal mdout1_11_3: std_logic; - signal mdout1_10_3: std_logic; - signal mdout1_9_3: std_logic; - signal mdout1_8_3: std_logic; - signal mdout1_7_3: std_logic; - signal mdout1_6_3: std_logic; - signal mdout1_5_3: std_logic; - signal mdout1_4_3: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_31_4: std_logic; - signal mdout1_30_4: std_logic; - signal mdout1_29_4: std_logic; - signal mdout1_28_4: std_logic; - signal mdout1_27_4: std_logic; - signal mdout1_26_4: std_logic; - signal mdout1_25_4: std_logic; - signal mdout1_24_4: std_logic; - signal mdout1_23_4: std_logic; - signal mdout1_22_4: std_logic; - signal mdout1_21_4: std_logic; - signal mdout1_20_4: std_logic; - signal mdout1_19_4: std_logic; - signal mdout1_18_4: std_logic; - signal mdout1_17_4: std_logic; - signal mdout1_16_4: std_logic; - signal mdout1_15_4: std_logic; - signal mdout1_14_4: std_logic; - signal mdout1_13_4: std_logic; - signal mdout1_12_4: std_logic; - signal mdout1_11_4: std_logic; - signal mdout1_10_4: std_logic; - signal mdout1_9_4: std_logic; - signal mdout1_8_4: std_logic; - signal mdout1_7_4: std_logic; - signal mdout1_6_4: std_logic; - signal mdout1_5_4: std_logic; - signal mdout1_4_4: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_31_5: std_logic; - signal mdout1_30_5: std_logic; - signal mdout1_29_5: std_logic; - signal mdout1_28_5: std_logic; - signal mdout1_27_5: std_logic; - signal mdout1_26_5: std_logic; - signal mdout1_25_5: std_logic; - signal mdout1_24_5: std_logic; - signal mdout1_23_5: std_logic; - signal mdout1_22_5: std_logic; - signal mdout1_21_5: std_logic; - signal mdout1_20_5: std_logic; - signal mdout1_19_5: std_logic; - signal mdout1_18_5: std_logic; - signal mdout1_17_5: std_logic; - signal mdout1_16_5: std_logic; - signal mdout1_15_5: std_logic; - signal mdout1_14_5: std_logic; - signal mdout1_13_5: std_logic; - signal mdout1_12_5: std_logic; - signal mdout1_11_5: std_logic; - signal mdout1_10_5: std_logic; - signal mdout1_9_5: std_logic; - signal mdout1_8_5: std_logic; - signal mdout1_7_5: std_logic; - signal mdout1_6_5: std_logic; - signal mdout1_5_5: std_logic; - signal mdout1_4_5: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_31_6: std_logic; - signal mdout1_30_6: std_logic; - signal mdout1_29_6: std_logic; - signal mdout1_28_6: std_logic; - signal mdout1_27_6: std_logic; - signal mdout1_26_6: std_logic; - signal mdout1_25_6: std_logic; - signal mdout1_24_6: std_logic; - signal mdout1_23_6: std_logic; - signal mdout1_22_6: std_logic; - signal mdout1_21_6: std_logic; - signal mdout1_20_6: std_logic; - signal mdout1_19_6: std_logic; - signal mdout1_18_6: std_logic; - signal mdout1_17_6: std_logic; - signal mdout1_16_6: std_logic; - signal mdout1_15_6: std_logic; - signal mdout1_14_6: std_logic; - signal mdout1_13_6: std_logic; - signal mdout1_12_6: std_logic; - signal mdout1_11_6: std_logic; - signal mdout1_10_6: std_logic; - signal mdout1_9_6: std_logic; - signal mdout1_8_6: std_logic; - signal mdout1_7_6: std_logic; - signal mdout1_6_6: std_logic; - signal mdout1_5_6: std_logic; - signal mdout1_4_6: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_31_7: std_logic; - signal mdout1_30_7: std_logic; - signal mdout1_29_7: std_logic; - signal mdout1_28_7: std_logic; - signal mdout1_27_7: std_logic; - signal mdout1_26_7: std_logic; - signal mdout1_25_7: std_logic; - signal mdout1_24_7: std_logic; - signal mdout1_23_7: std_logic; - signal mdout1_22_7: std_logic; - signal mdout1_21_7: std_logic; - signal mdout1_20_7: std_logic; - signal mdout1_19_7: std_logic; - signal mdout1_18_7: std_logic; - signal mdout1_17_7: std_logic; - signal mdout1_16_7: std_logic; - signal mdout1_15_7: std_logic; - signal mdout1_14_7: std_logic; - signal mdout1_13_7: std_logic; - signal mdout1_12_7: std_logic; - signal mdout1_11_7: std_logic; - signal mdout1_10_7: std_logic; - signal mdout1_9_7: std_logic; - signal mdout1_8_7: std_logic; - signal mdout1_7_7: std_logic; - signal mdout1_6_7: std_logic; - signal mdout1_5_7: std_logic; - signal mdout1_4_7: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal rptr_13_ff: std_logic; - signal rptr_12_ff: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_31_8: std_logic; - signal mdout1_30_8: std_logic; - signal mdout1_29_8: std_logic; - signal mdout1_28_8: std_logic; - signal mdout1_27_8: std_logic; - signal mdout1_26_8: std_logic; - signal mdout1_25_8: std_logic; - signal mdout1_24_8: std_logic; - signal mdout1_23_8: std_logic; - signal mdout1_22_8: std_logic; - signal mdout1_21_8: std_logic; - signal mdout1_20_8: std_logic; - signal mdout1_19_8: std_logic; - signal mdout1_18_8: std_logic; - signal mdout1_17_8: std_logic; - signal mdout1_16_8: std_logic; - signal mdout1_15_8: std_logic; - signal mdout1_14_8: std_logic; - signal mdout1_13_8: std_logic; - signal mdout1_12_8: std_logic; - signal mdout1_11_8: std_logic; - signal mdout1_10_8: std_logic; - signal mdout1_9_8: std_logic; - signal mdout1_8_8: std_logic; - signal mdout1_7_8: std_logic; - signal mdout1_6_8: std_logic; - signal mdout1_5_8: std_logic; - signal mdout1_4_8: std_logic; - signal mdout1_3_8: std_logic; - signal mdout1_2_8: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal wcount_r14: std_logic; - signal wcount_r15: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal rcount_w14: std_logic; - signal rcount_w15: std_logic; - signal wcount_14: std_logic; - signal wcount_15: std_logic; - signal co7_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX321 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; D4: in std_logic; D5: in std_logic; - D6: in std_logic; D7: in std_logic; D8: in std_logic; - D9: in std_logic; D10: in std_logic; D11: in std_logic; - D12: in std_logic; D13: in std_logic; D14: in std_logic; - D15: in std_logic; D16: in std_logic; D17: in std_logic; - D18: in std_logic; D19: in std_logic; D20: in std_logic; - D21: in std_logic; D22: in std_logic; D23: in std_logic; - D24: in std_logic; D25: in std_logic; D26: in std_logic; - D27: in std_logic; D28: in std_logic; D29: in std_logic; - D30: in std_logic; D31: in std_logic; SD1: in std_logic; - SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; - SD5: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; - attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; - attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; - attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; - attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; - attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; - attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; - attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; - attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; - attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; - attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; - attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; - attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; - attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; - attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; - attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; - attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; - attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; - attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; - attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; - attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; - attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; - attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; - attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; - attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; - attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; - attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; - attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; - attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; - attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; - attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; - attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t34: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_11: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t33: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_10: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t32: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t31: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t30: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t29: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t28: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t27: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t26: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t25: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t24: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t23: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t22: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t21: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t20: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t19: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t18: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t17: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t16: XOR2 - port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - INV_9: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_8: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_7: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_6: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - INV_5: INV - port map (A=>wptr_15, Z=>wptr_15_inv); - - LUT4_187: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet); - - LUT4_186: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_p00); - - INV_4: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_3: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_2: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_1: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - INV_0: INV - port map (A=>rptr_15, Z=>rptr_15_inv); - - LUT4_185: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_1); - - LUT4_184: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec1_r10); - - LUT4_183: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_2); - - LUT4_182: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec2_p01); - - LUT4_181: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_3); - - LUT4_180: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec3_r11); - - LUT4_179: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_4); - - LUT4_178: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec4_p02); - - LUT4_177: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_5); - - LUT4_176: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec5_r12); - - LUT4_175: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_6); - - LUT4_174: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec6_p03); - - LUT4_173: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_7); - - LUT4_172: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec7_r13); - - LUT4_171: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_8); - - LUT4_170: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec8_p04); - - LUT4_169: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_9); - - LUT4_168: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec9_r14); - - LUT4_167: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_10); - - LUT4_166: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - - LUT4_165: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_11); - - LUT4_164: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - - LUT4_163: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_12); - - LUT4_162: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - - LUT4_161: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_13); - - LUT4_160: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - - LUT4_159: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_14); - - LUT4_158: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - - LUT4_157: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_15); - - LUT4_156: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - - LUT4_155: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_16); - - LUT4_154: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - - LUT4_153: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_17); - - LUT4_152: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - - LUT4_151: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_18); - - LUT4_150: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - - LUT4_149: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_19); - - LUT4_148: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - - LUT4_147: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_20); - - LUT4_146: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - - LUT4_145: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_21); - - LUT4_144: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - - LUT4_143: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_22); - - LUT4_142: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - - LUT4_141: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_23); - - LUT4_140: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - - LUT4_139: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_24); - - LUT4_138: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - - LUT4_137: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_25); - - LUT4_136: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - - LUT4_135: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_26); - - LUT4_134: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - - LUT4_133: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_27); - - LUT4_132: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - - LUT4_131: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_28); - - LUT4_130: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - - LUT4_129: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_29); - - LUT4_128: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - - LUT4_127: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, - DO0=>func_and_inet_30); - - LUT4_126: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - - LUT4_125: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_31); - - LUT4_124: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - - LUT4_123: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_32); - - LUT4_122: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec32_p016); - - LUT4_121: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_33); - - LUT4_120: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec33_r116); - - LUT4_119: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_34); - - LUT4_118: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec34_p017); - - LUT4_117: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_35); - - LUT4_116: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec35_r117); - - LUT4_115: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_36); - - LUT4_114: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec36_p018); - - LUT4_113: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_37); - - LUT4_112: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec37_r118); - - LUT4_111: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_38); - - LUT4_110: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec38_p019); - - LUT4_109: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_39); - - LUT4_108: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec39_r119); - - LUT4_107: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_40); - - LUT4_106: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec40_p020); - - LUT4_105: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_41); - - LUT4_104: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec41_r120); - - LUT4_103: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_42); - - LUT4_102: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec42_p021); - - LUT4_101: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_43); - - LUT4_100: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec43_r121); - - LUT4_99: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_44); - - LUT4_98: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec44_p022); - - LUT4_97: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_45); - - LUT4_96: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec45_r122); - - LUT4_95: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_46); - - LUT4_94: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec46_p023); - - LUT4_93: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_47); - - LUT4_92: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec47_r123); - - LUT4_91: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_48); - - LUT4_90: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec48_p024); - - LUT4_89: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_49); - - LUT4_88: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec49_r124); - - LUT4_87: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_50); - - LUT4_86: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec50_p025); - - LUT4_85: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_51); - - LUT4_84: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec51_r125); - - LUT4_83: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_52); - - LUT4_82: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec52_p026); - - LUT4_81: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_53); - - LUT4_80: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec53_r126); - - LUT4_79: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_54); - - LUT4_78: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec54_p027); - - LUT4_77: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_55); - - LUT4_76: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec55_r127); - - LUT4_75: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_56); - - LUT4_74: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec56_p028); - - LUT4_73: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_57); - - LUT4_72: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec57_r128); - - LUT4_71: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_58); - - LUT4_70: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec58_p029); - - LUT4_69: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_59); - - LUT4_68: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec59_r129); - - LUT4_67: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_60); - - LUT4_66: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec60_p030); - - LUT4_65: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_61); - - LUT4_64: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec61_r130); - - LUT4_63: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, - DO0=>func_and_inet_62); - - LUT4_62: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec62_p031); - - LUT4_61: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_63); - - LUT4_60: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec63_r131); - - LUT4_59: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>w_gcount_r216, - DO0=>w_g2b_xor_cluster_0); - - LUT4_58: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_1); - - LUT4_57: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_2); - - LUT4_56: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_3); - - LUT4_55: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r15); - - LUT4_54: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, - AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_53: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, - DO0=>wcount_r10); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r3); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r2); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_10); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, - AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, - DO0=>func_xor_inet_11); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, - DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, - DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, - DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, - DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, - DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, - DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, - DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, - DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, - DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, - DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, - DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, - DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, - DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, - DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, - DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, - DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, - DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, - DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, - DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, - DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, - DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, - DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, - DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, - DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, - DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, - DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, - DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, - DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, - DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, - DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, - DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, - DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, - DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, - DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, - DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, - DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, - DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, - DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, - DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, - DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, - DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, - DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, - DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, - DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, - DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, - DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, - DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, - DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, - DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, - DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, - DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, - DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, - DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, - DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, - DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, - DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, - DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, - DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, - DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, - DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, - DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, - DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, - DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, - DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, - DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, - DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, - DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, - DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, - DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, - DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, - DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, - DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, - DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, - DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, - DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, - DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, - DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, - DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, - DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, - DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, - DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, - DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, - DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, - DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, - DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, - DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, - DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, - DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, - DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, - DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_176: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_175: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_174: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_173: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_172: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_171: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_170: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_169: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_168: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_167: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_166: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_165: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_164: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_163: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_162: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_161: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_160: FD1P3DX - port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_16); - - FF_159: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_158: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_157: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_156: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_155: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_154: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_153: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_152: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_151: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_150: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_149: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_148: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_147: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_146: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_145: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_144: FD1P3DX - port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_143: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_16); - - FF_142: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_141: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_140: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_139: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_138: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_137: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_136: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_135: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_134: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_133: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_132: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_131: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_130: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_129: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_128: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_127: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_126: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_16); - - FF_125: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_124: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_123: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_122: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_121: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_120: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_119: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_118: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_117: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_116: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_115: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_114: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_113: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_112: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_111: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_110: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_109: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_108: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_107: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_106: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_105: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_104: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_103: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_102: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_101: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_100: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_99: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_98: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_97: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_96: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_95: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_94: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_93: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_92: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_91: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_90: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_89: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_88: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_87: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_86: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_85: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_84: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_83: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_82: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_81: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_80: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_79: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_78: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_77: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_76: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_75: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_74: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_73: FD1P3DX - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_72: FD1P3DX - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_71: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_70: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_69: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_68: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_67: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_66: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_65: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_64: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_63: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_62: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_61: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_60: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_59: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_58: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_57: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_56: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_55: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_54: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_53: FD1S3DX - port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r16); - - FF_52: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_51: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_50: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_49: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_48: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_47: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_46: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_45: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_44: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_43: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_42: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_41: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_40: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_39: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_38: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_37: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_36: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_35: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_34: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_33: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_32: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_31: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_30: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_29: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_28: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_27: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_26: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_25: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_24: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_23: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_22: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_21: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_20: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_19: FD1S3DX - port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r216); - - FF_18: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - w_gctr_8: CU2 - port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>iwcount_16, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, - NC0=>ircount_16, NC1=>open); - - mux_8: MUX321 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, - D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, - D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, - D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, - D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, - D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(0)); - - mux_7: MUX321 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, - D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, - D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, - D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, - D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, - D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(1)); - - mux_6: MUX321 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, - D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, - D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, - D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, - D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, - D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(2)); - - mux_5: MUX321 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, - D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, - D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, - D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, - D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, - D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(3)); - - mux_4: MUX321 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, - D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, - D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, - D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, - D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, - D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(4)); - - mux_3: MUX321 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, - D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, - D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, - D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, - D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, - D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(5)); - - mux_2: MUX321 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, - D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, - D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, - D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, - D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, - D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(6)); - - mux_1: MUX321 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, - D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, - D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, - D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, - D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, - D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(7)); - - mux_0: MUX321 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, - D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, - D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, - D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, - D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, - D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, - B1=>wcount_r15, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, - B1=>rcount_w15, CI=>co6_3, GE=>co7_3); - - full_cmp_8: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_64kx9 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX321 use entity ecp3.MUX321(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/fifo_64kx9_generate.log b/gbe2_ecp3/ipcores/fifo_64kx9_generate.log deleted file mode 100644 index 6860ef8..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx9_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:21 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx9 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx9.vhd - VHDL template : fifo_64kx9_tmpl.vhd - VHDL testbench : tb_fifo_64kx9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx9.srp - Estimated Resource Usage: - LUT : 379 - EBR : 32 - Reg : 177 - -END SCUBA Module Synthesis - -File: fifo_64kx9.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/fifo_64kx9_tmpl.vhd b/gbe2_ecp3/ipcores/fifo_64kx9_tmpl.vhd deleted file mode 100644 index a9d000b..0000000 --- a/gbe2_ecp3/ipcores/fifo_64kx9_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:21 2011 - --- parameterized module component declaration -component fifo_64kx9 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_64kx9 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores/ip_mem.jhd b/gbe2_ecp3/ipcores/ip_mem.jhd deleted file mode 100755 index 3ba907d..0000000 --- a/gbe2_ecp3/ipcores/ip_mem.jhd +++ /dev/null @@ -1,9 +0,0 @@ -MODULE ip_mem DEFIN ip_mem.vhd - SUBMODULE DP16KB - INSTANCE ip_mem_0_1_0 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE DP16KB - INSTANCE ip_mem_0_0_1 diff --git a/gbe2_ecp3/ipcores/ip_mem.lpc b/gbe2_ecp3/ipcores/ip_mem.lpc deleted file mode 100755 index 4c9ab25..0000000 --- a/gbe2_ecp3/ipcores/ip_mem.lpc +++ /dev/null @@ -1,60 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=RAM_DP_TRUE -CoreRevision=7.1 -ModuleName=ip_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:37 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -AAddress=256 -BAddress=256 -AData=32 -BData=32 -enByte=0 -ByteSize=9 -AadPipeline=0 -BadPipeline=0 -AinPipeline=0 -BinPipeline=0 -AoutPipeline=0 -BoutPipeline=1 -AMOR=0 -BMOR=0 -AInData=Registered -BInData=Registered -AAdControl=Registered -BAdControl=Registered -MemFile=ip_mem.mem -MemFormat=orca -Reset=Sync -GSR=Enabled -WriteA=Normal -WriteB=Normal -Pad=0 -EnECC=0 -Optimization=Speed -Pipeline=0 - -[FilesGenerated] -ip_mem.mem=mem diff --git a/gbe2_ecp3/ipcores/ip_mem.mem b/gbe2_ecp3/ipcores/ip_mem.mem deleted file mode 100755 index 836ca91..0000000 --- a/gbe2_ecp3/ipcores/ip_mem.mem +++ /dev/null @@ -1,277 +0,0 @@ -#Format=Address-Hex -#Depth=256 -#DataWidth=32 -#AddrRadix=3 -#DataRadix=3 - -00: 214397e9 -01: 0000001b -02: c0a80002 -03: 0000c350 -04: 023bdc00 -05: 00000013 -06: c0a80005 -07: 0000c350 -08: 00000578 -09: 00000000 -0a: 00000000 -0b: 00000000 -0c: 00000000 -0d: 00000000 -0e: 00000000 -0f: 00000000 - -10: 214397e9 -11: 0000001b -12: c0a80002 -13: 0000c351 -14: 023bdc01 -15: 00000013 -16: c0a80006 -17: 0000c350 -18: 00000578 -19: 00000000 -1a: 00000000 -1b: 00000000 -1c: 00000000 -1d: 00000000 -1e: 00000000 -1f: 00000000 - -20: 214397e9 -21: 0000001b -22: c0a80002 -23: 0000c352 -24: 023bdc02 -25: 00000013 -26: c0a80007 -27: 0000c350 -28: 00000578 -29: 00000000 -2a: 00000000 -2b: 00000000 -2c: 00000000 -2d: 00000000 -2e: 00000000 -2f: 00000000 - -30: 214397e9 -31: 0000001b -32: c0a80002 -33: 0000c353 -34: 023bdc03 -35: 00000013 -36: c0a80008 -37: 0000c350 -38: 00000578 -39: 00000000 -3a: 00000000 -3b: 00000000 -3c: 00000000 -3d: 00000000 -3e: 00000000 -3f: 00000000 - -40: 00000000 -41: 00000000 -42: 00000000 -43: 00000000 -44: 00000000 -45: 00000000 -46: 00000000 -47: 00000000 -48: 00000578 -49: 00000000 -4a: 00000000 -4b: 00000000 -4c: 00000000 -4d: 00000000 -4e: 00000000 -4f: 00000000 - -50: 00000000 -51: 00000000 -52: 00000000 -53: 00000000 -54: 00000000 -55: 00000000 -56: 00000000 -57: 00000000 -58: 00000578 -59: 00000000 -5a: 00000000 -5b: 00000000 -5c: 00000000 -5d: 00000000 -5e: 00000000 -5f: 00000000 - -60: 00000000 -61: 00000000 -62: 00000000 -63: 00000000 -64: 00000000 -65: 00000000 -66: 00000000 -67: 00000000 -68: 00000578 -69: 00000000 -6a: 00000000 -6b: 00000000 -6c: 00000000 -6d: 00000000 -6e: 00000000 -6f: 00000000 - -70: 00000000 -71: 00000000 -72: 00000000 -73: 00000000 -74: 00000000 -75: 00000000 -76: 00000000 -77: 00000000 -78: 00000578 -79: 00000000 -7a: 00000000 -7b: 00000000 -7c: 00000000 -7d: 00000000 -7e: 00000000 -7f: 00000000 - -80: 00000000 -81: 00000000 -82: 00000000 -83: 00000000 -84: 00000000 -85: 00000000 -86: 00000000 -87: 00000000 -88: 00000578 -89: 00000000 -8a: 00000000 -8b: 00000000 -8c: 00000000 -8d: 00000000 -8e: 00000000 -8f: 00000000 - -90: 00000000 -91: 00000000 -92: 00000000 -93: 00000000 -94: 00000000 -95: 00000000 -96: 00000000 -97: 00000000 -98: 00000578 -99: 00000000 -9a: 00000000 -9b: 00000000 -9c: 00000000 -9d: 00000000 -9e: 00000000 -9f: 00000000 - -a0: 00000000 -a1: 00000000 -a2: 00000000 -a3: 00000000 -a4: 00000000 -a5: 00000000 -a6: 00000000 -a7: 00000000 -a8: 00000578 -a9: 00000000 -aa: 00000000 -ab: 00000000 -ac: 00000000 -ad: 00000000 -ae: 00000000 -af: 00000000 - -b0: 00000000 -b1: 00000000 -b2: 00000000 -b3: 00000000 -b4: 00000000 -b5: 00000000 -b6: 00000000 -b7: 00000000 -b8: 00000578 -b9: 00000000 -ba: 00000000 -bb: 00000000 -bc: 00000000 -bd: 00000000 -be: 00000000 -bf: 00000000 - -c0: 00000000 -c1: 00000000 -c2: 00000000 -c3: 00000000 -c4: 00000000 -c5: 00000000 -c6: 00000000 -c7: 00000000 -c8: 00000578 -c9: 00000000 -ca: 00000000 -cb: 00000000 -cc: 00000000 -cd: 00000000 -ce: 00000000 -cf: 00000000 - -d0: 00000000 -d1: 00000000 -d2: 00000000 -d3: 00000000 -d4: 00000000 -d5: 00000000 -d6: 00000000 -d7: 00000000 -d8: 00000578 -d9: 00000000 -da: 00000000 -db: 00000000 -dc: 00000000 -dd: 00000000 -de: 00000000 -df: 00000000 - -e0: 00000000 -e1: 00000000 -e2: 00000000 -e3: 00000000 -e4: 00000000 -e5: 00000000 -e6: 00000000 -e7: 00000000 -e8: 00000578 -e9: 00000000 -ea: 00000000 -eb: 00000000 -ec: 00000000 -ed: 00000000 -ee: 00000000 -ef: 00000000 - -f0: 00000000 -f1: 00000000 -f2: 00000000 -f3: 00000000 -f4: 00000000 -f5: 00000000 -f6: 00000000 -f7: 00000000 -f8: 00000578 -f9: 00000000 -fa: 00000000 -fb: 00000000 -fc: 00000000 -fd: 00000000 -fe: 00000000 -ff: 00000000 diff --git a/gbe2_ecp3/ipcores/ip_mem.mem.bak b/gbe2_ecp3/ipcores/ip_mem.mem.bak deleted file mode 100755 index 9810f31..0000000 --- a/gbe2_ecp3/ipcores/ip_mem.mem.bak +++ /dev/null @@ -1,277 +0,0 @@ -#Format=Address-Hex -#Depth=256 -#DataWidth=32 -#AddrRadix=3 -#DataRadix=3 - -00: 00006cf0 -01: 4902d745 -02: c0a80002 -03: 0000c350 -04: 0000eeee -05: eeeeeeee -06: c0a80005 -07: 0000c350 -08: 00000578 -09: 00000000 -0a: 00000000 -0b: 00000000 -0c: 00000000 -0d: 00000000 -0e: 00000000 -0f: 00000000 - -10: 00000000 -11: 00000000 -12: 00000000 -13: 00000000 -14: 00000000 -15: 00000000 -16: 00000000 -17: 00000000 -18: 00000578 -19: 00000000 -1a: 00000000 -1b: 00000000 -1c: 00000000 -1d: 00000000 -1e: 00000000 -1f: 00000000 - -20: 00000000 -21: 00000000 -22: 00000000 -23: 00000000 -24: 00000000 -25: 00000000 -26: 00000000 -27: 00000000 -28: 00000578 -29: 00000000 -2a: 00000000 -2b: 00000000 -2c: 00000000 -2d: 00000000 -2e: 00000000 -2f: 00000000 - -30: 00000000 -31: 00000000 -32: 00000000 -33: 00000000 -34: 00000000 -35: 00000000 -36: 00000000 -37: 00000000 -38: 00000578 -39: 00000000 -3a: 00000000 -3b: 00000000 -3c: 00000000 -3d: 00000000 -3e: 00000000 -3f: 00000000 - -40: 00000000 -41: 00000000 -42: 00000000 -43: 00000000 -44: 00000000 -45: 00000000 -46: 00000000 -47: 00000000 -48: 00000578 -49: 00000000 -4a: 00000000 -4b: 00000000 -4c: 00000000 -4d: 00000000 -4e: 00000000 -4f: 00000000 - -50: 00000000 -51: 00000000 -52: 00000000 -53: 00000000 -54: 00000000 -55: 00000000 -56: 00000000 -57: 00000000 -58: 00000578 -59: 00000000 -5a: 00000000 -5b: 00000000 -5c: 00000000 -5d: 00000000 -5e: 00000000 -5f: 00000000 - -60: 00000000 -61: 00000000 -62: 00000000 -63: 00000000 -64: 00000000 -65: 00000000 -66: 00000000 -67: 00000000 -68: 00000578 -69: 00000000 -6a: 00000000 -6b: 00000000 -6c: 00000000 -6d: 00000000 -6e: 00000000 -6f: 00000000 - -70: 00000000 -71: 00000000 -72: 00000000 -73: 00000000 -74: 00000000 -75: 00000000 -76: 00000000 -77: 00000000 -78: 00000578 -79: 00000000 -7a: 00000000 -7b: 00000000 -7c: 00000000 -7d: 00000000 -7e: 00000000 -7f: 00000000 - -80: 00000000 -81: 00000000 -82: 00000000 -83: 00000000 -84: 00000000 -85: 00000000 -86: 00000000 -87: 00000000 -88: 00000578 -89: 00000000 -8a: 00000000 -8b: 00000000 -8c: 00000000 -8d: 00000000 -8e: 00000000 -8f: 00000000 - -90: 00000000 -91: 00000000 -92: 00000000 -93: 00000000 -94: 00000000 -95: 00000000 -96: 00000000 -97: 00000000 -98: 00000578 -99: 00000000 -9a: 00000000 -9b: 00000000 -9c: 00000000 -9d: 00000000 -9e: 00000000 -9f: 00000000 - -a0: 00000000 -a1: 00000000 -a2: 00000000 -a3: 00000000 -a4: 00000000 -a5: 00000000 -a6: 00000000 -a7: 00000000 -a8: 00000578 -a9: 00000000 -aa: 00000000 -ab: 00000000 -ac: 00000000 -ad: 00000000 -ae: 00000000 -af: 00000000 - -b0: 00000000 -b1: 00000000 -b2: 00000000 -b3: 00000000 -b4: 00000000 -b5: 00000000 -b6: 00000000 -b7: 00000000 -b8: 00000578 -b9: 00000000 -ba: 00000000 -bb: 00000000 -bc: 00000000 -bd: 00000000 -be: 00000000 -bf: 00000000 - -c0: 00000000 -c1: 00000000 -c2: 00000000 -c3: 00000000 -c4: 00000000 -c5: 00000000 -c6: 00000000 -c7: 00000000 -c8: 00000578 -c9: 00000000 -ca: 00000000 -cb: 00000000 -cc: 00000000 -cd: 00000000 -ce: 00000000 -cf: 00000000 - -d0: 00000000 -d1: 00000000 -d2: 00000000 -d3: 00000000 -d4: 00000000 -d5: 00000000 -d6: 00000000 -d7: 00000000 -d8: 00000578 -d9: 00000000 -da: 00000000 -db: 00000000 -dc: 00000000 -dd: 00000000 -de: 00000000 -df: 00000000 - -e0: 00000000 -e1: 00000000 -e2: 00000000 -e3: 00000000 -e4: 00000000 -e5: 00000000 -e6: 00000000 -e7: 00000000 -e8: 00000578 -e9: 00000000 -ea: 00000000 -eb: 00000000 -ec: 00000000 -ed: 00000000 -ee: 00000000 -ef: 00000000 - -f0: 00000000 -f1: 00000000 -f2: 00000000 -f3: 00000000 -f4: 00000000 -f5: 00000000 -f6: 00000000 -f7: 00000000 -f8: 00000578 -f9: 00000000 -fa: 00000000 -fb: 00000000 -fc: 00000000 -fd: 00000000 -fe: 00000000 -ff: 00000000 diff --git a/gbe2_ecp3/ipcores/ip_mem.naf b/gbe2_ecp3/ipcores/ip_mem.naf deleted file mode 100755 index 11b52d7..0000000 --- a/gbe2_ecp3/ipcores/ip_mem.naf +++ /dev/null @@ -1,152 +0,0 @@ -DataInA[31] i -DataInA[30] i -DataInA[29] i -DataInA[28] i -DataInA[27] i -DataInA[26] i -DataInA[25] i -DataInA[24] i -DataInA[23] i -DataInA[22] i -DataInA[21] i -DataInA[20] i -DataInA[19] i -DataInA[18] i -DataInA[17] i -DataInA[16] i -DataInA[15] i -DataInA[14] i -DataInA[13] i -DataInA[12] i -DataInA[11] i -DataInA[10] i -DataInA[9] i -DataInA[8] i -DataInA[7] i -DataInA[6] i -DataInA[5] i -DataInA[4] i -DataInA[3] i -DataInA[2] i -DataInA[1] i -DataInA[0] i -DataInB[31] i -DataInB[30] i -DataInB[29] i -DataInB[28] i -DataInB[27] i -DataInB[26] i -DataInB[25] i -DataInB[24] i -DataInB[23] i -DataInB[22] i -DataInB[21] i -DataInB[20] i -DataInB[19] i -DataInB[18] i -DataInB[17] i -DataInB[16] i -DataInB[15] i -DataInB[14] i -DataInB[13] i -DataInB[12] i -DataInB[11] i -DataInB[10] i -DataInB[9] i -DataInB[8] i -DataInB[7] i -DataInB[6] i -DataInB[5] i -DataInB[4] i -DataInB[3] i -DataInB[2] i -DataInB[1] i -DataInB[0] i -AddressA[7] i -AddressA[6] i -AddressA[5] i -AddressA[4] i -AddressA[3] i -AddressA[2] i -AddressA[1] i -AddressA[0] i -AddressB[7] i -AddressB[6] i -AddressB[5] i -AddressB[4] i -AddressB[3] i -AddressB[2] i -AddressB[1] i -AddressB[0] i -ClockA i -ClockB i -ClockEnA i -ClockEnB i -WrA i -WrB i -ResetA i -ResetB i -QA[31] o -QA[30] o -QA[29] o -QA[28] o -QA[27] o -QA[26] o -QA[25] o -QA[24] o -QA[23] o -QA[22] o -QA[21] o -QA[20] o -QA[19] o -QA[18] o -QA[17] o -QA[16] o -QA[15] o -QA[14] o -QA[13] o -QA[12] o -QA[11] o -QA[10] o -QA[9] o -QA[8] o -QA[7] o -QA[6] o -QA[5] o -QA[4] o -QA[3] o -QA[2] o -QA[1] o -QA[0] o -QB[31] o -QB[30] o -QB[29] o -QB[28] o -QB[27] o -QB[26] o -QB[25] o -QB[24] o -QB[23] o -QB[22] o -QB[21] o -QB[20] o -QB[19] o -QB[18] o -QB[17] o -QB[16] o -QB[15] o -QB[14] o -QB[13] o -QB[12] o -QB[11] o -QB[10] o -QB[9] o -QB[8] o -QB[7] o -QB[6] o -QB[5] o -QB[4] o -QB[3] o -QB[2] o -QB[1] o -QB[0] o diff --git a/gbe2_ecp3/ipcores/ip_mem.srp b/gbe2_ecp3/ipcores/ip_mem.srp deleted file mode 100755 index e9b1af8..0000000 --- a/gbe2_ecp3/ipcores/ip_mem.srp +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version ispLever_v72_SP2_Build (23) -Mon Mar 29 21:52:49 2010 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e - Circuit name : ip_mem - Module type : RAM_DP_TRUE - Module Version : 7.1 - Ports : - Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB - Outputs : QA[31:0], QB[31:0] - I/O buffer : not inserted - Memory file : /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem - EDIF output : suppressed - VHDL output : ip_mem.vhd - VHDL template : ip_mem_tmpl.vhd - VHDL testbench : tb_ip_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : ip_mem.srp - Element Usage : - DP16KB : 2 - Estimated Resource Usage: - EBR : 2 diff --git a/gbe2_ecp3/ipcores/ip_mem.vhd b/gbe2_ecp3/ipcores/ip_mem.vhd deleted file mode 100755 index 5b2e06e..0000000 --- a/gbe2_ecp3/ipcores/ip_mem.vhd +++ /dev/null @@ -1,379 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 7.1 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e - --- Thu Sep 22 11:24:37 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity ip_mem is - port ( - DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(31 downto 0); - AddressA: in std_logic_vector(7 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(31 downto 0)); -end ip_mem; - -architecture Structure of ip_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP16KC - generic (INITVAL_3F : in String; INITVAL_3E : in String; - INITVAL_3D : in String; INITVAL_3C : in String; - INITVAL_3B : in String; INITVAL_3A : in String; - INITVAL_39 : in String; INITVAL_38 : in String; - INITVAL_37 : in String; INITVAL_36 : in String; - INITVAL_35 : in String; INITVAL_34 : in String; - INITVAL_33 : in String; INITVAL_32 : in String; - INITVAL_31 : in String; INITVAL_30 : in String; - INITVAL_2F : in String; INITVAL_2E : in String; - INITVAL_2D : in String; INITVAL_2C : in String; - INITVAL_2B : in String; INITVAL_2A : in String; - INITVAL_29 : in String; INITVAL_28 : in String; - INITVAL_27 : in String; INITVAL_26 : in String; - INITVAL_25 : in String; INITVAL_24 : in String; - INITVAL_23 : in String; INITVAL_22 : in String; - INITVAL_21 : in String; INITVAL_20 : in String; - INITVAL_1F : in String; INITVAL_1E : in String; - INITVAL_1D : in String; INITVAL_1C : in String; - INITVAL_1B : in String; INITVAL_1A : in String; - INITVAL_19 : in String; INITVAL_18 : in String; - INITVAL_17 : in String; INITVAL_16 : in String; - INITVAL_15 : in String; INITVAL_14 : in String; - INITVAL_13 : in String; INITVAL_12 : in String; - INITVAL_11 : in String; INITVAL_10 : in String; - INITVAL_0F : in String; INITVAL_0E : in String; - INITVAL_0D : in String; INITVAL_0C : in String; - INITVAL_0B : in String; INITVAL_0A : in String; - INITVAL_09 : in String; INITVAL_08 : in String; - INITVAL_07 : in String; INITVAL_06 : in String; - INITVAL_05 : in String; INITVAL_04 : in String; - INITVAL_03 : in String; INITVAL_02 : in String; - INITVAL_01 : in String; INITVAL_00 : in String; - GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; - attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; - attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; - attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; - attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC"; - -begin - -- component instantiation statements - ip_mem_0_0_1: DP16KC - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9", - INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", - INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", - INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", - CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", - REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) - port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), - DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), - DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), - DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11), - DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14), - DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17), - ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, - ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), - ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), - ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, - CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, - DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2), - DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5), - DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8), - DIB9=>DataInB(9), DIB10=>DataInB(10), DIB11=>DataInB(11), - DIB12=>DataInB(12), DIB13=>DataInB(13), DIB14=>DataInB(14), - DIB15=>DataInB(15), DIB16=>DataInB(16), DIB17=>DataInB(17), - ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1), - ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4), - ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7), - ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB, - CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0), - DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4), - DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8), - DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12), - DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16), - DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2), - DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6), - DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10), - DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14), - DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17)); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - ip_mem_0_1_0: DP16KC - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", - REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) - port map (DIA0=>DataInA(18), DIA1=>DataInA(19), - DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22), - DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25), - DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28), - DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31), - DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo, - DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0), - ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3), - ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6), - ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>ClockEnA, CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>ResetA, DIB0=>DataInB(18), DIB1=>DataInB(19), - DIB2=>DataInB(20), DIB3=>DataInB(21), DIB4=>DataInB(22), - DIB5=>DataInB(23), DIB6=>DataInB(24), DIB7=>DataInB(25), - DIB8=>DataInB(26), DIB9=>DataInB(27), DIB10=>DataInB(28), - DIB11=>DataInB(29), DIB12=>DataInB(30), DIB13=>DataInB(31), - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vhi, ADB1=>scuba_vhi, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>AddressB(0), - ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3), - ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6), - ADB11=>AddressB(7), ADB12=>scuba_vlo, ADB13=>scuba_vlo, - CEB=>ClockEnB, CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), DOA2=>QA(20), - DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), DOA6=>QA(24), - DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), DOA10=>QA(28), - DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>QB(18), - DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), DOB4=>QB(22), - DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), DOB8=>QB(26), - DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), DOB12=>QB(30), - DOB13=>QB(31), DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of ip_mem is - for Structure - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/ip_mem_generate.log b/gbe2_ecp3/ipcores/ip_mem_generate.log deleted file mode 100755 index 4a57089..0000000 --- a/gbe2_ecp3/ipcores/ip_mem_generate.log +++ /dev/null @@ -1,45 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v72_SP2_Build (23) -Mon Mar 29 21:52:49 2010 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e - Circuit name : ip_mem - Module type : RAM_DP_TRUE - Module Version : 7.1 - Ports : - Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB - Outputs : QA[31:0], QB[31:0] - I/O buffer : not inserted - Memory file : /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem - EDIF output : suppressed - VHDL output : ip_mem.vhd - VHDL template : ip_mem_tmpl.vhd - VHDL testbench : tb_ip_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : ip_mem.srp - Estimated Resource Usage: - EBR : 2 - -END SCUBA Module Synthesis - -File: ip_mem.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/ip_mem_tmpl.vhd b/gbe2_ecp3/ipcores/ip_mem_tmpl.vhd deleted file mode 100755 index d516b11..0000000 --- a/gbe2_ecp3/ipcores/ip_mem_tmpl.vhd +++ /dev/null @@ -1,23 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 7.1 --- Thu Sep 22 11:24:37 2011 - --- parameterized module component declaration -component ip_mem - port (DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(31 downto 0); - AddressA: in std_logic_vector(7 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; ClockB: in std_logic; - ClockEnA: in std_logic; ClockEnB: in std_logic; - WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic; - ResetB: in std_logic; QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(31 downto 0)); -end component; - --- parameterized module component instance -__ : ip_mem - port map (DataInA(31 downto 0)=>__, DataInB(31 downto 0)=>__, - AddressA(7 downto 0)=>__, AddressB(7 downto 0)=>__, ClockA=>__, - ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, - ResetB=>__, QA(31 downto 0)=>__, QB(31 downto 0)=>__); diff --git a/gbe2_ecp3/ipcores/macInitDataInvWithMac.mem b/gbe2_ecp3/ipcores/macInitDataInvWithMac.mem deleted file mode 100755 index c93b822..0000000 --- a/gbe2_ecp3/ipcores/macInitDataInvWithMac.mem +++ /dev/null @@ -1,59 +0,0 @@ -#Format=Bin -#Depth=54 -#Width=8 -#AddrRadix=3 -#DataRadix=3 -#Data -00001111 -00001111 -10011001 -00000001 -11101110 -00000101 -00000000 -00000000 -00001100 -00000000 -00110100 -00010010 -01111000 -01010110 -10111100 -10011010 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -10000000 diff --git a/gbe2_ecp3/ipcores/mac_init_mem.lpc b/gbe2_ecp3/ipcores/mac_init_mem.lpc deleted file mode 100755 index 42f57b0..0000000 --- a/gbe2_ecp3/ipcores/mac_init_mem.lpc +++ /dev/null @@ -1,48 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=ROM -CoreRevision=5.0 -ModuleName=mac_init_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:53 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Address=54 -Data=8 -adPipeline=0 -inPipeline=0 -outPipeline=1 -MOR=0 -InData=Registered -AdControl=Registered -MemFile=macInitDataInvWithMac.mem -MemFormat=bin -Reset=Sync -Pad=0 -GSR=Enabled -EnECC=0 -Optimization=Speed -Pipeline=0 - -[FilesGenerated] -macInitDataInvWithMac.mem=mem diff --git a/gbe2_ecp3/ipcores/mac_init_mem.srp b/gbe2_ecp3/ipcores/mac_init_mem.srp deleted file mode 100755 index 37bdeb7..0000000 --- a/gbe2_ecp3/ipcores/mac_init_mem.srp +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version ispLever_v72_SP2_Build (23) -Thu Aug 20 16:00:49 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type romblk -device LFE2M100E -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - Circuit name : mac_init_mem - Module type : EBR_ROM - Module Version : 5.0 - Ports : - Inputs : Address[5:0], OutClock, OutClockEn, Reset - Outputs : Q[7:0] - I/O buffer : not inserted - Memory file : /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem - EDIF output : suppressed - VHDL output : mac_init_mem.vhd - VHDL template : mac_init_mem_tmpl.vhd - VHDL testbench : tb_mac_init_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : mac_init_mem.srp - Element Usage : - DP16KB : 1 - Estimated Resource Usage: - EBR : 1 diff --git a/gbe2_ecp3/ipcores/mac_init_mem.vhd b/gbe2_ecp3/ipcores/mac_init_mem.vhd deleted file mode 100755 index 3934a61..0000000 --- a/gbe2_ecp3/ipcores/mac_init_mem.vhd +++ /dev/null @@ -1,262 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.0 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - --- Thu Sep 22 11:24:53 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity mac_init_mem is - port ( - Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; - OutClockEn: in std_logic; - Reset: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end mac_init_mem; - -architecture Structure of mac_init_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP16KC - generic (INITVAL_3F : in String; INITVAL_3E : in String; - INITVAL_3D : in String; INITVAL_3C : in String; - INITVAL_3B : in String; INITVAL_3A : in String; - INITVAL_39 : in String; INITVAL_38 : in String; - INITVAL_37 : in String; INITVAL_36 : in String; - INITVAL_35 : in String; INITVAL_34 : in String; - INITVAL_33 : in String; INITVAL_32 : in String; - INITVAL_31 : in String; INITVAL_30 : in String; - INITVAL_2F : in String; INITVAL_2E : in String; - INITVAL_2D : in String; INITVAL_2C : in String; - INITVAL_2B : in String; INITVAL_2A : in String; - INITVAL_29 : in String; INITVAL_28 : in String; - INITVAL_27 : in String; INITVAL_26 : in String; - INITVAL_25 : in String; INITVAL_24 : in String; - INITVAL_23 : in String; INITVAL_22 : in String; - INITVAL_21 : in String; INITVAL_20 : in String; - INITVAL_1F : in String; INITVAL_1E : in String; - INITVAL_1D : in String; INITVAL_1C : in String; - INITVAL_1B : in String; INITVAL_1A : in String; - INITVAL_19 : in String; INITVAL_18 : in String; - INITVAL_17 : in String; INITVAL_16 : in String; - INITVAL_15 : in String; INITVAL_14 : in String; - INITVAL_13 : in String; INITVAL_12 : in String; - INITVAL_11 : in String; INITVAL_10 : in String; - INITVAL_0F : in String; INITVAL_0E : in String; - INITVAL_0D : in String; INITVAL_0C : in String; - INITVAL_0B : in String; INITVAL_0A : in String; - INITVAL_09 : in String; INITVAL_08 : in String; - INITVAL_07 : in String; INITVAL_06 : in String; - INITVAL_05 : in String; INITVAL_04 : in String; - INITVAL_03 : in String; INITVAL_02 : in String; - INITVAL_01 : in String; INITVAL_00 : in String; - GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc"; - attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem"; - attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC"; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - mac_init_mem_0_0_0: DP16KC - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", - INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", - CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", - REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, - ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), - ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), - ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, - CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo, - ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, - ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, - ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, - CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi, - WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1), - DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), - DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open, - DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of mac_init_mem is - for Structure - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores/mac_init_mem_generate.log b/gbe2_ecp3/ipcores/mac_init_mem_generate.log deleted file mode 100755 index a58303d..0000000 --- a/gbe2_ecp3/ipcores/mac_init_mem_generate.log +++ /dev/null @@ -1,45 +0,0 @@ -Starting process: - -SCUBA, Version ispLever_v72_SP2_Build (23) -Thu Aug 20 16:00:49 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type romblk -device LFE2M100E -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - Circuit name : mac_init_mem - Module type : EBR_ROM - Module Version : 5.0 - Ports : - Inputs : Address[5:0], OutClock, OutClockEn, Reset - Outputs : Q[7:0] - I/O buffer : not inserted - Memory file : /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem - EDIF output : suppressed - VHDL output : mac_init_mem.vhd - VHDL template : mac_init_mem_tmpl.vhd - VHDL testbench : tb_mac_init_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : mac_init_mem.srp - Estimated Resource Usage: - EBR : 1 - -END SCUBA Module Synthesis - -File: mac_init_mem.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores/mac_init_mem_tmpl.vhd b/gbe2_ecp3/ipcores/mac_init_mem_tmpl.vhd deleted file mode 100755 index 853efd2..0000000 --- a/gbe2_ecp3/ipcores/mac_init_mem_tmpl.vhd +++ /dev/null @@ -1,15 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.0 --- Thu Sep 22 11:24:53 2011 - --- parameterized module component declaration -component mac_init_mem - port (Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q: out std_logic_vector(7 downto 0)); -end component; - --- parameterized module component instance -__ : mac_init_mem - port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__, - Reset=>__, Q(7 downto 0)=>__); diff --git a/gbe2_ecp3/ipcores/msg_file.log b/gbe2_ecp3/ipcores/msg_file.log deleted file mode 100755 index ecd2f32..0000000 --- a/gbe2_ecp3/ipcores/msg_file.log +++ /dev/null @@ -1,33 +0,0 @@ -SCUBA, Version ispLever_v8.1_PROD_Build (20) -Wed Jun 1 17:14:00 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x72 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x72.vhd - VHDL template : fifo_512x72_tmpl.vhd - VHDL testbench : tb_fifo_512x72_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x72.srp - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 - -END SCUBA Module Synthesis - diff --git a/gbe2_ecp3/ipcores/tb_fifo_2048x8_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_2048x8_tmpl.vhd deleted file mode 100755 index 343af71..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_2048x8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_2048x8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_2048x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 2051 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd deleted file mode 100755 index 1ad6e7d..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd +++ /dev/null @@ -1,115 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8_mb - port (Data : in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic - ); - end component; - - signal Data : std_logic_vector(15 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0'); - signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0'); - signal Q : std_logic_vector(7 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; - signal AlmostEmpty: std_logic; - signal AlmostFull: std_logic; -begin - u1 : fifo_32kx16x8_mb - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full, - AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_fifo_32kx16x8_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_32kx16x8_tmpl.vhd deleted file mode 100755 index 3bbafb6..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_32kx16x8_tmpl.vhd +++ /dev/null @@ -1,106 +0,0 @@ --- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8 - port (Data : in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(15 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_32kx16x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_fifo_4096x32_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_4096x32_tmpl.vhd deleted file mode 100755 index 0559dd7..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_4096x32_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x32 - port (Data : in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(31 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x32 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_fifo_4096x9_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_4096x9_tmpl.vhd deleted file mode 100755 index 9352be8..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_4096x9_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x9 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x9 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_fifo_512x64_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_512x64_tmpl.vhd deleted file mode 100644 index 7276404..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_512x64_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA ispLever_v8.1_PROD_Build (20) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x64 - port (Data : in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(71 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(71 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(71 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x64 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_fifo_512x72_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_512x72_tmpl.vhd deleted file mode 100644 index 0e16359..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_512x72_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA ispLever_v8.1_PROD_Build (20) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x72 - port (Data : in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(71 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(71 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(71 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x72 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_fifo_64kx8_tmpl.vhd b/gbe2_ecp3/ipcores/tb_fifo_64kx8_tmpl.vhd deleted file mode 100755 index 2096041..0000000 --- a/gbe2_ecp3/ipcores/tb_fifo_64kx8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_64kx8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_64kx8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 65539 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_ip_mem_tmpl.vhd b/gbe2_ecp3/ipcores/tb_ip_mem_tmpl.vhd deleted file mode 100755 index 862c84d..0000000 --- a/gbe2_ecp3/ipcores/tb_ip_mem_tmpl.vhd +++ /dev/null @@ -1,174 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component ip_mem - port (DataInA : in std_logic_vector(31 downto 0); - DataInB : in std_logic_vector(31 downto 0); - AddressA : in std_logic_vector(7 downto 0); - AddressB : in std_logic_vector(7 downto 0); ClockA: in std_logic; - ClockB: in std_logic; ClockEnA: in std_logic; - ClockEnB: in std_logic; WrA: in std_logic; WrB: in std_logic; - ResetA: in std_logic; ResetB: in std_logic; - QA : out std_logic_vector(31 downto 0); - QB : out std_logic_vector(31 downto 0) - ); - end component; - - signal DataInA : std_logic_vector(31 downto 0) := (others => '0'); - signal DataInB : std_logic_vector(31 downto 0) := (others => '0'); - signal AddressA : std_logic_vector(7 downto 0) := (others => '0'); - signal AddressB : std_logic_vector(7 downto 0) := (others => '0'); - signal ClockA: std_logic := '0'; - signal ClockB: std_logic := '0'; - signal ClockEnA: std_logic := '0'; - signal ClockEnB: std_logic := '0'; - signal WrA: std_logic := '0'; - signal WrB: std_logic := '0'; - signal ResetA: std_logic := '0'; - signal ResetB: std_logic := '0'; - signal QA : std_logic_vector(31 downto 0); - signal QB : std_logic_vector(31 downto 0); -begin - u1 : ip_mem - port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA, - AddressB => AddressB, ClockA => ClockA, ClockB => ClockB, - ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB, - ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB - ); - - process - - begin - DataInA <= (others => '0') ; - wait for 100 ns; - wait until ResetA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - DataInA <= DataInA + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - DataInB <= (others => '0') ; - wait for 100 ns; - wait until ResetB = '0'; - wait until WrB = '1'; - for i in 0 to 259 loop - wait until ClockB'event and ClockB = '1'; - DataInB <= DataInB + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - AddressA <= (others => '0') ; - wait for 100 ns; - wait until ResetA = '0'; - for i in 0 to 518 loop - wait until ClockA'event and ClockA = '1'; - AddressA <= AddressA + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - AddressB <= (others => '0') ; - wait for 100 ns; - wait until ResetB = '0'; - wait until WrB = '1'; - for i in 0 to 518 loop - wait until ClockB'event and ClockB = '1'; - AddressB <= AddressB + '1' after 1 ns; - end loop; - wait; - end process; - - ClockA <= not ClockA after 5.00 ns; - - ClockB <= not ClockB after 5.00 ns; - - process - - begin - ClockEnA <= '0' ; - wait for 100 ns; - wait until ResetA = '0'; - ClockEnA <= '1' ; - wait; - end process; - - process - - begin - ClockEnB <= '0' ; - wait for 100 ns; - wait until ResetB = '0'; - ClockEnB <= '1' ; - wait; - end process; - - process - - begin - WrA <= '0' ; - wait until ResetA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - WrA <= '1' after 1 ns; - end loop; - WrA <= '0' ; - wait; - end process; - - process - - begin - WrB <= '0' ; - wait until ResetB = '0'; - wait until WrA = '1'; - wait until WrA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - end loop; - for i in 0 to 259 loop - wait until ClockB'event and ClockB = '1'; - WrB <= '1' after 1 ns; - end loop; - WrB <= '0' ; - wait; - end process; - - process - - begin - ResetA <= '1' ; - wait for 100 ns; - ResetA <= '0' ; - wait; - end process; - - process - - begin - ResetB <= '1' ; - wait for 100 ns; - ResetB <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores/tb_mac_init_mem_tmpl.vhd b/gbe2_ecp3/ipcores/tb_mac_init_mem_tmpl.vhd deleted file mode 100755 index 701eaf3..0000000 --- a/gbe2_ecp3/ipcores/tb_mac_init_mem_tmpl.vhd +++ /dev/null @@ -1,64 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component mac_init_mem - port (Address : in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q : out std_logic_vector(7 downto 0) - ); - end component; - - signal Address : std_logic_vector(5 downto 0) := (others => '0'); - signal OutClock: std_logic := '0'; - signal OutClockEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); -begin - u1 : mac_init_mem - port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn, - Reset => Reset, Q => Q - ); - - process - - begin - Address <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 57 loop - wait until OutClock'event and OutClock = '1'; - Address <= Address + '1' after 1 ns; - end loop; - wait; - end process; - - OutClock <= not OutClock after 5.00 ns; - - process - - begin - OutClockEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - OutClockEn <= '1' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd b/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd deleted file mode 100644 index e10ee86..0000000 --- a/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd +++ /dev/null @@ -1,1965 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 16 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e - --- Wed Jul 21 14:35:10 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity debug_fifo_2kx16 is - port ( - Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(15 downto 0); - Empty: out std_logic; - Full: out std_logic); -end debug_fifo_2kx16; - -architecture Structure of debug_fifo_2kx16 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "debug_fifo_2kx16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "debug_fifo_2kx16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_1_0 : label is "9"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t24: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t23: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t22: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t21: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t20: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t19: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t18: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t17: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t16: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t15: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t14: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t13: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t12: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t11: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), - DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_1_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), - DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), - DIA6=>Data(15), DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, - ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, - ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, - ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, - CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9), - DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13), - DOB5=>Q(14), DOB6=>Q(15), DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_121: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of debug_fifo_2kx16 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.ipx deleted file mode 100644 index 1fb1491..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.jhd deleted file mode 100644 index 77bc2dd..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.jhd +++ /dev/null @@ -1,413 +0,0 @@ -MODULE fifo_1024x16x8 DEFIN fifo_1024x16x8.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1P3DX - INSTANCE FF_48 - SUBMODULE FD1P3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3BX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3BX - INSTANCE FF_116 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE OR2 - INSTANCE OR2_t21 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t22 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t23 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.lpc deleted file mode 100644 index 0bcc570..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_1024x16x8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/05/2011 -Time=18:27:25 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=1024 -Width=18 -RDepth=2048 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.naf b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.naf deleted file mode 100644 index 0e4fd42..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.naf +++ /dev/null @@ -1,35 +0,0 @@ -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.sort b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.sort deleted file mode 100644 index 30a8b78..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_1024x16x8.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.srp b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.srp deleted file mode 100644 index b624152..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Mon Dec 5 18:27:25 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_1024x16x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 10 -data_width 18 -num_words 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_1024x16x8 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_1024x16x8.vhd - VHDL template : fifo_1024x16x8_tmpl.vhd - VHDL testbench : tb_fifo_1024x16x8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_1024x16x8.srp - Element Usage : - AGEB2 : 12 - AND2 : 2 - CU2 : 12 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 67 - FD1S3BX : 1 - FD1S3DX : 47 - INV : 2 - OR2 : 1 - ROM16X1A : 30 - XOR2 : 21 - DP16KC : 1 - Estimated Resource Usage: - LUT : 114 - EBR : 1 - Reg : 117 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.sym b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8.sym deleted file mode 100644 index 55d306865949b8f98690c6b8212d4544764b5b1b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 438 zcmYL_F-yZx6ot>FX+?+9!5UhgmJSjy>EL25YQQ2=O$%adLyb_Kii4vBCns@m z5|K>eSezX)I7>&z&Q6}ZR1945@!jOSd*8DIJ{i`lXbEC0rs!CbiU4`3(U>TqXb~2y zcF=AatF`hz(4YumrJcE^yYBUmPTWrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t22: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t21: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t20: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t19: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t18: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t17: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t16: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t15: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t14: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t13: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t12: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t11: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>w_gcount_r210, - DO0=>w_g2b_xor_cluster_0); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, - DO0=>w_g2b_xor_cluster_1); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), - DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_116: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_115: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_114: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_113: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_112: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_111: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_110: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_109: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_108: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_107: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_106: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_105: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_104: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_103: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_102: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_101: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_100: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_99: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_98: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_97: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_96: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_95: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_94: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_93: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_92: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_91: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_90: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_89: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_88: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_87: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_86: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_85: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_84: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_83: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_82: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_81: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_80: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_79: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_78: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_77: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_76: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_75: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_74: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_73: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_72: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_71: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_70: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_69: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_68: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_67: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_66: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_65: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_64: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_63: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_62: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_60: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_59: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_58: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_57: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_56: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_55: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_54: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_53: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_52: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_51: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_50: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_49: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_48: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_47: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_46: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_45: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_44: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_43: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_42: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_41: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_40: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_39: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_38: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_37: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_36: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_35: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_34: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_33: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_32: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_31: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_30: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_29: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_28: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_27: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_26: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_25: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_24: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_23: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_22: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_21: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_20: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_19: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_18: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_17: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_16: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_15: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_14: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_13: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5, - NC0=>iwcount_10, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r8, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r9, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>r_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_1024x16x8 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8_generate.log deleted file mode 100644 index fa619dd..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Mon Dec 5 18:27:25 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_1024x16x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 10 -data_width 18 -num_words 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_1024x16x8 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_1024x16x8.vhd - VHDL template : fifo_1024x16x8_tmpl.vhd - VHDL testbench : tb_fifo_1024x16x8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_1024x16x8.srp - Estimated Resource Usage: - LUT : 114 - EBR : 1 - Reg : 117 - -END SCUBA Module Synthesis - -File: fifo_1024x16x8.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8_tmpl.vhd deleted file mode 100644 index d7608a4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_1024x16x8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Mon Dec 5 18:27:25 2011 - --- parameterized module component declaration -component fifo_1024x16x8 - port (Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_1024x16x8 - port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd deleted file mode 100644 index 12a3160..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd +++ /dev/null @@ -1,2711 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.4 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 8 -depth 16384 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Mon Dec 6 19:08:10 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_16kx8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_16kx8; - -architecture Structure of fifo_16kx8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal co7: std_logic; - signal wcount_14: std_logic; - signal co6: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal co7_1: std_logic; - signal rcount_14: std_logic; - signal co6_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal wcount_r13: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal rcount_w13: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "1"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t30: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t29: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t28: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t27: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t26: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t25: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t24: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t23: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t22: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t21: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t20: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t19: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t18: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t17: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t16: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t15: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t14: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t13: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t12: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t11: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t10: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t9: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t8: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t7: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t6: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t5: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t4: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t3: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t2: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t1: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t0: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>w_gcount_r214, - DO0=>w_g2b_xor_cluster_0); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>w_gcount_r210, - DO0=>w_g2b_xor_cluster_1); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, - DO0=>w_g2b_xor_cluster_2); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_1); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r0); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>r_gcount_w214, - DO0=>r_g2b_xor_cluster_0); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>r_gcount_w210, - DO0=>r_g2b_xor_cluster_1); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_2); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w13); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_151: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_135: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_134: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_133: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_132: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_106: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7, - NC0=>iwcount_14, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1, - NC0=>ircount_14, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>w_g2b_xor_cluster_0, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>wcount_r13, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co6_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>rcount_w13, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co6_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_16kx8 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.ipx deleted file mode 100644 index baa4545..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.jhd deleted file mode 100644 index 9cd0750..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.jhd +++ /dev/null @@ -1,429 +0,0 @@ -MODULE fifo_2048x8 DEFIN fifo_2048x8.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3BX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3BX - INSTANCE FF_121 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE ROM16X1A - INSTANCE LUT4_30 - SUBMODULE ROM16X1A - INSTANCE LUT4_31 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE OR2 - INSTANCE OR2_t22 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t23 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t24 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.lpc deleted file mode 100755 index 7c0b6de..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_2048x8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:58 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=2048 -Width=8 -RDepth=2048 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.naf b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.naf deleted file mode 100644 index 6378b4d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.naf +++ /dev/null @@ -1,24 +0,0 @@ -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.sort b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.sort deleted file mode 100644 index f965b2d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_2048x8.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.srp b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.srp deleted file mode 100755 index fb3f623..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:58 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_2048x8 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_2048x8.vhd - VHDL template : fifo_2048x8_tmpl.vhd - VHDL testbench : tb_fifo_2048x8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_2048x8.srp - Element Usage : - AGEB2 : 12 - AND2 : 2 - CU2 : 12 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 70 - FD1S3BX : 1 - FD1S3DX : 49 - INV : 2 - OR2 : 1 - ROM16X1A : 32 - XOR2 : 22 - DP16KC : 1 - Estimated Resource Usage: - LUT : 117 - EBR : 1 - Reg : 122 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.sym b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.sym deleted file mode 100644 index 20d963c4ef1d929c1cb93f3f73c368c370b15957..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 432 zcmYk2u}i~17{%X5Q>E(A!OnxXUC2pBh&#hC)1vD<+m?MSulyXk0AA@(2yDlXMQ( zH|%3<^E1O{>1TuPRx~)f#3^logVGv7*S`kt=%$EDR}XqOy#!;rrlfzn+ogS`jqy;~ za9DP}(&m^{o#9Y*e(;nz-e9%ffx3ScCnHWtZD)TE-^>bpGW!CI)@>9qsxo!E6hF)i z!OU)Xm4E5teE*_9I9avVoO=frdu;KU7ihv4M+7OI>i0C~`W$U((5Jflh+f^z}vOteVNmImVhZa)w9EF*(KyJJp{zxqvyo!F{g$0y3~pk^lez diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd deleted file mode 100755 index 82dac9a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd +++ /dev/null @@ -1,1415 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:23:58 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_2048x8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_2048x8; - -architecture Structure of fifo_2048x8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t24: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t23: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t22: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t21: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t20: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t19: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t18: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t17: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t16: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t15: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t14: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t13: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t12: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t11: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), - DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_121: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_120: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_119: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_118: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_117: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_116: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_115: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_114: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_113: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_112: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_111: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_110: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_108: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_107: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_106: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_105: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_104: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_103: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_102: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_101: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_100: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_99: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_98: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_96: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_95: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_94: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_93: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_92: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_91: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_89: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_88: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_87: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_86: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_84: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_83: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_82: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_81: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_80: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_79: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_78: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_77: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_76: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_75: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_74: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_73: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_72: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_71: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_70: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_69: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_68: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_67: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_66: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_65: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_64: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_63: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_62: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_61: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_60: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_59: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_58: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_57: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_56: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_55: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_54: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_53: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_51: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_50: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_49: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_48: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_47: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_46: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_45: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_44: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_43: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_42: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_41: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_40: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_39: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_38: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_37: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_36: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_35: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_34: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_33: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_32: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_31: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_30: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_29: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_28: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_27: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_26: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_25: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_15: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_14: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_13: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_2048x8 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8_generate.log deleted file mode 100755 index 27952a3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:58 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_2048x8 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_2048x8.vhd - VHDL template : fifo_2048x8_tmpl.vhd - VHDL testbench : tb_fifo_2048x8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_2048x8.srp - Estimated Resource Usage: - LUT : 117 - EBR : 1 - Reg : 122 - -END SCUBA Module Synthesis - -File: fifo_2048x8.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8_tmpl.vhd deleted file mode 100755 index 1a3333f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:58 2011 - --- parameterized module component declaration -component fifo_2048x8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_2048x8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.ipx deleted file mode 100644 index 263f9c7..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.jhd deleted file mode 100644 index a2a5854..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.jhd +++ /dev/null @@ -1,413 +0,0 @@ -MODULE fifo_2048x8x16 DEFIN fifo_2048x8x16.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1P3DX - INSTANCE FF_48 - SUBMODULE FD1P3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3BX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3BX - INSTANCE FF_116 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE OR2 - INSTANCE OR2_t21 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t22 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t23 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.lpc deleted file mode 100644 index 4f4da58..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_2048x8x16 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/05/2011 -Time=18:26:53 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=2048 -Width=9 -RDepth=1024 -RWidth=18 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.naf b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.naf deleted file mode 100644 index 30207e3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.naf +++ /dev/null @@ -1,35 +0,0 @@ -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.sort b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.sort deleted file mode 100644 index e1406db..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_2048x8x16.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.srp b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.srp deleted file mode 100644 index ee6e782..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Mon Dec 5 18:26:53 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 9 -num_words 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_2048x8x16 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[17:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_2048x8x16.vhd - VHDL template : fifo_2048x8x16_tmpl.vhd - VHDL testbench : tb_fifo_2048x8x16_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_2048x8x16.srp - Element Usage : - AGEB2 : 12 - AND2 : 2 - CU2 : 12 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 67 - FD1S3BX : 1 - FD1S3DX : 47 - INV : 2 - OR2 : 1 - ROM16X1A : 30 - XOR2 : 21 - DP16KC : 1 - Estimated Resource Usage: - LUT : 114 - EBR : 1 - Reg : 117 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.sym b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.sym deleted file mode 100644 index c0322467bc1d366b175acb1110bbb5f931d78c40..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 436 zcmYL_ze~eV6ot>FDWxLP!9O5F2XRV8G>Ajcra1W{R4NqFYFiMa4Yf+TWpH%JuM3@4k25yP34Wr@(p+TH-(?MqSw3Xjc`X-k?3#tZf2io z1Kj7fHOw+!X%kHH%+^q4e(;tF-cW7414Z{D7>&6~3OoBve6yG0lf5s%Xk7a~TX|1S z7vYCJLr~gl*H+am|K0hy{#k!;v}7&Yp&iy%fCXk*;&M%j3S3ziK}4s{*wUQnyELUt yAL;yKdNrTP@--cR2E diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd deleted file mode 100644 index 4486567..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd +++ /dev/null @@ -1,1367 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 9 -depth 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e - --- Mon Dec 5 18:26:53 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_2048x8x16 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_2048x8x16; - -architecture Structure of fifo_2048x8x16 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal wcount_r0: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal co5_1: std_logic; - signal rcount_10: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r7: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w8: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w9: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8x16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t23: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t22: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t21: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t20: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t19: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t18: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t17: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t16: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t15: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t14: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t13: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t12: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t11: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t10: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t9: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t8: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t7: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t6: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t5: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t4: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t3: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t2: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t1: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t0: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>r_gcount_w210, - DO0=>r_g2b_xor_cluster_0); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_1); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo, - ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, - ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, ADB11=>rptr_7, - ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), - DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), - DOB11=>Q(11), DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), - DOB15=>Q(15), DOB16=>Q(16), DOB17=>Q(17)); - - FF_116: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_115: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_114: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_113: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_112: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_111: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_110: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_109: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_108: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_107: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_106: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_105: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_104: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_103: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_102: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_101: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_100: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_99: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_98: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_97: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_96: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_95: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_94: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_93: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_92: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_91: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_90: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_89: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_88: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_87: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_86: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_85: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_84: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_83: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_82: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_81: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_80: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_79: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_78: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_77: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_76: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_75: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_74: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_73: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_72: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_71: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_70: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_69: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_68: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_67: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_66: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_65: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_64: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_63: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_62: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_61: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_60: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_59: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_58: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_57: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_56: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_55: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_54: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_53: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_52: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_51: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_50: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_49: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_48: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_47: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_46: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_45: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_44: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_43: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_42: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_41: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_40: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_39: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_38: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_37: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_36: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_35: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_34: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_33: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_32: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_31: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_30: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_29: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_28: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_27: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_26: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_25: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_24: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_23: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_22: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_21: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_20: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_19: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_18: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_17: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_16: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_15: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_14: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_13: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_12: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_11: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_10: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_9: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_8: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_7: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_6: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_5: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_4: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_3: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_2: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, - NC0=>ircount_10, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1, - B1=>wcount_r2, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3, - B1=>wcount_r4, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5, - B1=>wcount_r6, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7, - B1=>w_g2b_xor_cluster_0, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9, - B1=>wcount_r10, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, - B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1, - B1=>rcount_w2, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3, - B1=>rcount_w4, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5, - B1=>rcount_w6, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w8, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_2048x8x16 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16_generate.log deleted file mode 100644 index df4f889..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Mon Dec 5 18:26:53 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_2048x8x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 9 -num_words 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_2048x8x16 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[17:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_2048x8x16.vhd - VHDL template : fifo_2048x8x16_tmpl.vhd - VHDL testbench : tb_fifo_2048x8x16_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_2048x8x16.srp - Estimated Resource Usage: - LUT : 114 - EBR : 1 - Reg : 117 - -END SCUBA Module Synthesis - -File: fifo_2048x8x16.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16_tmpl.vhd deleted file mode 100644 index e3db862..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Mon Dec 5 18:26:53 2011 - --- parameterized module component declaration -component fifo_2048x8x16 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_2048x8x16 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.ipx deleted file mode 100644 index e457f75..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.jhd deleted file mode 100755 index 0f484db..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.jhd +++ /dev/null @@ -1,949 +0,0 @@ -MODULE fifo_32kx16x8_mb DEFIN fifo_32kx16x8_mb.vhd - SUBMODULE FADD2B - INSTANCE a3 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE af_d_cmp_7 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_6 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_5 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_4 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_3 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_2 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_1 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_0 - SUBMODULE FADD2B - INSTANCE af_d_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a2 - SUBMODULE AGEB2 - INSTANCE ae_cmp_8 - SUBMODULE AGEB2 - INSTANCE ae_cmp_7 - SUBMODULE AGEB2 - INSTANCE ae_cmp_6 - SUBMODULE AGEB2 - INSTANCE ae_cmp_5 - SUBMODULE AGEB2 - INSTANCE ae_cmp_4 - SUBMODULE AGEB2 - INSTANCE ae_cmp_3 - SUBMODULE AGEB2 - INSTANCE ae_cmp_2 - SUBMODULE AGEB2 - INSTANCE ae_cmp_1 - SUBMODULE AGEB2 - INSTANCE ae_cmp_0 - SUBMODULE FADD2B - INSTANCE ae_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE AGEB2 - INSTANCE full_cmp_7 - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_8 - SUBMODULE AGEB2 - INSTANCE empty_cmp_7 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE FADD2B - INSTANCE rfilld - SUBMODULE FSUB2B - INSTANCE rfill_8 - SUBMODULE FSUB2B - INSTANCE rfill_7 - SUBMODULE FSUB2B - INSTANCE rfill_6 - SUBMODULE FSUB2B - INSTANCE rfill_5 - SUBMODULE FSUB2B - INSTANCE rfill_4 - SUBMODULE FSUB2B - INSTANCE rfill_3 - SUBMODULE FSUB2B - INSTANCE rfill_2 - SUBMODULE FSUB2B - INSTANCE rfill_1 - SUBMODULE FSUB2B - INSTANCE rfill_0 - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE FSUB2B - INSTANCE wfill_8 - SUBMODULE FSUB2B - INSTANCE wfill_7 - SUBMODULE FSUB2B - INSTANCE wfill_6 - SUBMODULE FSUB2B - INSTANCE wfill_5 - SUBMODULE FSUB2B - INSTANCE wfill_4 - SUBMODULE FSUB2B - INSTANCE wfill_3 - SUBMODULE FSUB2B - INSTANCE wfill_2 - SUBMODULE FSUB2B - INSTANCE wfill_1 - SUBMODULE FSUB2B - INSTANCE wfill_0 - SUBMODULE FADD2B - INSTANCE rcntd - SUBMODULE FSUB2B - INSTANCE rcnt_8 - SUBMODULE FSUB2B - INSTANCE rcnt_7 - SUBMODULE FSUB2B - INSTANCE rcnt_6 - SUBMODULE FSUB2B - INSTANCE rcnt_5 - SUBMODULE FSUB2B - INSTANCE rcnt_4 - SUBMODULE FSUB2B - INSTANCE rcnt_3 - SUBMODULE FSUB2B - INSTANCE rcnt_2 - SUBMODULE FSUB2B - INSTANCE rcnt_1 - SUBMODULE FSUB2B - INSTANCE rcnt_0 - SUBMODULE FSUB2B - INSTANCE wcnt_8 - SUBMODULE FSUB2B - INSTANCE wcnt_7 - SUBMODULE FSUB2B - INSTANCE wcnt_6 - SUBMODULE FSUB2B - INSTANCE wcnt_5 - SUBMODULE FSUB2B - INSTANCE wcnt_4 - SUBMODULE FSUB2B - INSTANCE wcnt_3 - SUBMODULE FSUB2B - INSTANCE wcnt_2 - SUBMODULE FSUB2B - INSTANCE wcnt_1 - SUBMODULE FSUB2B - INSTANCE wcnt_0 - SUBMODULE MUX41 - INSTANCE mux_0 - SUBMODULE MUX41 - INSTANCE mux_1 - SUBMODULE MUX41 - INSTANCE mux_2 - SUBMODULE MUX41 - INSTANCE mux_3 - SUBMODULE MUX41 - INSTANCE mux_4 - SUBMODULE MUX41 - INSTANCE mux_5 - SUBMODULE MUX41 - INSTANCE mux_6 - SUBMODULE MUX41 - INSTANCE mux_7 - SUBMODULE CU2 - INSTANCE r_gctr_8 - SUBMODULE CU2 - INSTANCE r_gctr_7 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE CU2 - INSTANCE w_gctr_7 - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3BX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1S3DX - INSTANCE FF_54 - SUBMODULE FD1S3DX - INSTANCE FF_55 - SUBMODULE FD1S3DX - INSTANCE FF_56 - SUBMODULE FD1S3DX - INSTANCE FF_57 - SUBMODULE FD1S3DX - INSTANCE FF_58 - SUBMODULE FD1S3DX - INSTANCE FF_59 - SUBMODULE FD1S3DX - INSTANCE FF_60 - SUBMODULE FD1S3DX - INSTANCE FF_61 - SUBMODULE FD1S3DX - INSTANCE FF_62 - SUBMODULE FD1S3DX - INSTANCE FF_63 - SUBMODULE FD1S3DX - INSTANCE FF_64 - SUBMODULE FD1S3DX - INSTANCE FF_65 - SUBMODULE FD1S3DX - INSTANCE FF_66 - SUBMODULE FD1S3DX - INSTANCE FF_67 - SUBMODULE FD1S3DX - INSTANCE FF_68 - SUBMODULE FD1S3DX - INSTANCE FF_69 - SUBMODULE FD1S3DX - INSTANCE FF_70 - SUBMODULE FD1S3DX - INSTANCE FF_71 - SUBMODULE FD1S3DX - INSTANCE FF_72 - SUBMODULE FD1S3DX - INSTANCE FF_73 - SUBMODULE FD1S3DX - INSTANCE FF_74 - SUBMODULE FD1S3DX - INSTANCE FF_75 - SUBMODULE FD1S3DX - INSTANCE FF_76 - SUBMODULE FD1S3DX - INSTANCE FF_77 - SUBMODULE FD1S3DX - INSTANCE FF_78 - SUBMODULE FD1S3DX - INSTANCE FF_79 - SUBMODULE FD1S3DX - INSTANCE FF_80 - SUBMODULE FD1S3DX - INSTANCE FF_81 - SUBMODULE FD1S3DX - INSTANCE FF_82 - SUBMODULE FD1S3DX - INSTANCE FF_83 - SUBMODULE FD1S3DX - INSTANCE FF_84 - SUBMODULE FD1S3DX - INSTANCE FF_85 - SUBMODULE FD1S3DX - INSTANCE FF_86 - SUBMODULE FD1S3DX - INSTANCE FF_87 - SUBMODULE FD1S3DX - INSTANCE FF_88 - SUBMODULE FD1S3DX - INSTANCE FF_89 - SUBMODULE FD1S3DX - INSTANCE FF_90 - SUBMODULE FD1S3DX - INSTANCE FF_91 - SUBMODULE FD1S3DX - INSTANCE FF_92 - SUBMODULE FD1S3DX - INSTANCE FF_93 - SUBMODULE FD1S3DX - INSTANCE FF_94 - SUBMODULE FD1S3DX - INSTANCE FF_95 - SUBMODULE FD1S3DX - INSTANCE FF_96 - SUBMODULE FD1S3DX - INSTANCE FF_97 - SUBMODULE FD1S3DX - INSTANCE FF_98 - SUBMODULE FD1S3DX - INSTANCE FF_99 - SUBMODULE FD1S3DX - INSTANCE FF_100 - SUBMODULE FD1S3DX - INSTANCE FF_101 - SUBMODULE FD1S3DX - INSTANCE FF_102 - SUBMODULE FD1S3DX - INSTANCE FF_103 - SUBMODULE FD1S3DX - INSTANCE FF_104 - SUBMODULE FD1S3DX - INSTANCE FF_105 - SUBMODULE FD1S3DX - INSTANCE FF_106 - SUBMODULE FD1S3DX - INSTANCE FF_107 - SUBMODULE FD1S3DX - INSTANCE FF_108 - SUBMODULE FD1S3DX - INSTANCE FF_109 - SUBMODULE FD1S3DX - INSTANCE FF_110 - SUBMODULE FD1S3DX - INSTANCE FF_111 - SUBMODULE FD1S3DX - INSTANCE FF_112 - SUBMODULE FD1S3DX - INSTANCE FF_113 - SUBMODULE FD1S3DX - INSTANCE FF_114 - SUBMODULE FD1S3DX - INSTANCE FF_115 - SUBMODULE FD1S3DX - INSTANCE FF_116 - SUBMODULE FD1S3DX - INSTANCE FF_117 - SUBMODULE FD1S3DX - INSTANCE FF_118 - SUBMODULE FD1S3DX - INSTANCE FF_119 - SUBMODULE FD1S3DX - INSTANCE FF_120 - SUBMODULE FD1S3DX - INSTANCE FF_121 - SUBMODULE FD1S3DX - INSTANCE FF_122 - SUBMODULE FD1S3DX - INSTANCE FF_123 - SUBMODULE FD1S3DX - INSTANCE FF_124 - SUBMODULE FD1S3DX - INSTANCE FF_125 - SUBMODULE FD1S3DX - INSTANCE FF_126 - SUBMODULE FD1S3DX - INSTANCE FF_127 - SUBMODULE FD1S3DX - INSTANCE FF_128 - SUBMODULE FD1S3DX - INSTANCE FF_129 - SUBMODULE FD1S3DX - INSTANCE FF_130 - SUBMODULE FD1S3DX - INSTANCE FF_131 - SUBMODULE FD1S3DX - INSTANCE FF_132 - SUBMODULE FD1S3DX - INSTANCE FF_133 - SUBMODULE FD1S3DX - INSTANCE FF_134 - SUBMODULE FD1S3DX - INSTANCE FF_135 - SUBMODULE FD1P3DX - INSTANCE FF_136 - SUBMODULE FD1P3DX - INSTANCE FF_137 - SUBMODULE FD1P3DX - INSTANCE FF_138 - SUBMODULE FD1P3DX - INSTANCE FF_139 - SUBMODULE FD1P3DX - INSTANCE FF_140 - SUBMODULE FD1P3DX - INSTANCE FF_141 - SUBMODULE FD1P3DX - INSTANCE FF_142 - SUBMODULE FD1P3DX - INSTANCE FF_143 - SUBMODULE FD1P3DX - INSTANCE FF_144 - SUBMODULE FD1P3DX - INSTANCE FF_145 - SUBMODULE FD1P3DX - INSTANCE FF_146 - SUBMODULE FD1P3DX - INSTANCE FF_147 - SUBMODULE FD1P3DX - INSTANCE FF_148 - SUBMODULE FD1P3DX - INSTANCE FF_149 - SUBMODULE FD1P3DX - INSTANCE FF_150 - SUBMODULE FD1P3DX - INSTANCE FF_151 - SUBMODULE FD1P3DX - INSTANCE FF_152 - SUBMODULE FD1P3DX - INSTANCE FF_153 - SUBMODULE FD1P3DX - INSTANCE FF_154 - SUBMODULE FD1P3DX - INSTANCE FF_155 - SUBMODULE FD1P3DX - INSTANCE FF_156 - SUBMODULE FD1P3DX - INSTANCE FF_157 - SUBMODULE FD1P3DX - INSTANCE FF_158 - SUBMODULE FD1P3DX - INSTANCE FF_159 - SUBMODULE FD1P3DX - INSTANCE FF_160 - SUBMODULE FD1P3DX - INSTANCE FF_161 - SUBMODULE FD1P3DX - INSTANCE FF_162 - SUBMODULE FD1P3DX - INSTANCE FF_163 - SUBMODULE FD1P3DX - INSTANCE FF_164 - SUBMODULE FD1P3DX - INSTANCE FF_165 - SUBMODULE FD1P3DX - INSTANCE FF_166 - SUBMODULE FD1P3DX - INSTANCE FF_167 - SUBMODULE FD1P3DX - INSTANCE FF_168 - SUBMODULE FD1P3DX - INSTANCE FF_169 - SUBMODULE FD1P3DX - INSTANCE FF_170 - SUBMODULE FD1P3DX - INSTANCE FF_171 - SUBMODULE FD1P3DX - INSTANCE FF_172 - SUBMODULE FD1P3DX - INSTANCE FF_173 - SUBMODULE FD1P3DX - INSTANCE FF_174 - SUBMODULE FD1P3DX - INSTANCE FF_175 - SUBMODULE FD1P3DX - INSTANCE FF_176 - SUBMODULE FD1P3DX - INSTANCE FF_177 - SUBMODULE FD1P3DX - INSTANCE FF_178 - SUBMODULE FD1P3DX - INSTANCE FF_179 - SUBMODULE FD1P3DX - INSTANCE FF_180 - SUBMODULE FD1P3DX - INSTANCE FF_181 - SUBMODULE FD1P3DX - INSTANCE FF_182 - SUBMODULE FD1P3DX - INSTANCE FF_183 - SUBMODULE FD1P3DX - INSTANCE FF_184 - SUBMODULE FD1P3DX - INSTANCE FF_185 - SUBMODULE FD1P3DX - INSTANCE FF_186 - SUBMODULE FD1P3DX - INSTANCE FF_187 - SUBMODULE FD1P3BX - INSTANCE FF_188 - SUBMODULE FD1P3DX - INSTANCE FF_189 - SUBMODULE FD1P3DX - INSTANCE FF_190 - SUBMODULE FD1P3DX - INSTANCE FF_191 - SUBMODULE FD1P3DX - INSTANCE FF_192 - SUBMODULE FD1P3DX - INSTANCE FF_193 - SUBMODULE FD1P3DX - INSTANCE FF_194 - SUBMODULE FD1P3DX - INSTANCE FF_195 - SUBMODULE FD1P3DX - INSTANCE FF_196 - SUBMODULE FD1P3DX - INSTANCE FF_197 - SUBMODULE FD1P3DX - INSTANCE FF_198 - SUBMODULE FD1P3DX - INSTANCE FF_199 - SUBMODULE FD1P3DX - INSTANCE FF_200 - SUBMODULE FD1P3DX - INSTANCE FF_201 - SUBMODULE FD1P3DX - INSTANCE FF_202 - SUBMODULE FD1P3DX - INSTANCE FF_203 - SUBMODULE FD1P3DX - INSTANCE FF_204 - SUBMODULE FD1P3DX - INSTANCE FF_205 - SUBMODULE FD1P3DX - INSTANCE FF_206 - SUBMODULE FD1P3DX - INSTANCE FF_207 - SUBMODULE FD1P3DX - INSTANCE FF_208 - SUBMODULE FD1P3DX - INSTANCE FF_209 - SUBMODULE FD1P3DX - INSTANCE FF_210 - SUBMODULE FD1P3DX - INSTANCE FF_211 - SUBMODULE FD1P3DX - INSTANCE FF_212 - SUBMODULE FD1P3DX - INSTANCE FF_213 - SUBMODULE FD1P3DX - INSTANCE FF_214 - SUBMODULE FD1P3DX - INSTANCE FF_215 - SUBMODULE FD1P3DX - INSTANCE FF_216 - SUBMODULE FD1P3DX - INSTANCE FF_217 - SUBMODULE FD1P3DX - INSTANCE FF_218 - SUBMODULE FD1P3DX - INSTANCE FF_219 - SUBMODULE FD1P3DX - INSTANCE FF_220 - SUBMODULE FD1P3DX - INSTANCE FF_221 - SUBMODULE FD1P3DX - INSTANCE FF_222 - SUBMODULE FD1P3DX - INSTANCE FF_223 - SUBMODULE FD1P3DX - INSTANCE FF_224 - SUBMODULE FD1P3DX - INSTANCE FF_225 - SUBMODULE FD1P3DX - INSTANCE FF_226 - SUBMODULE FD1P3DX - INSTANCE FF_227 - SUBMODULE FD1P3DX - INSTANCE FF_228 - SUBMODULE FD1P3DX - INSTANCE FF_229 - SUBMODULE FD1P3DX - INSTANCE FF_230 - SUBMODULE FD1P3DX - INSTANCE FF_231 - SUBMODULE FD1P3DX - INSTANCE FF_232 - SUBMODULE FD1P3DX - INSTANCE FF_233 - SUBMODULE FD1P3DX - INSTANCE FF_234 - SUBMODULE FD1P3DX - INSTANCE FF_235 - SUBMODULE FD1P3BX - INSTANCE FF_236 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_7_0 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_6_1 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_5_2 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_4_3 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_3_4 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_2_5 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_1_6 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_0_7 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_7_8 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_6_9 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_5_10 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_4_11 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_3_12 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_2_13 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_1_14 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_0_15 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_7_16 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_6_17 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_5_18 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_4_19 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_3_20 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_2_21 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_1_22 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_0_23 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_7_24 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_6_25 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_5_26 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_4_27 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_3_28 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_2_29 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_1_30 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_31 - SUBMODULE AND2 - INSTANCE AND2_t0 - SUBMODULE AND2 - INSTANCE AND2_t1 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE ROM16X1A - INSTANCE LUT4_30 - SUBMODULE ROM16X1A - INSTANCE LUT4_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_32 - SUBMODULE ROM16X1A - INSTANCE LUT4_33 - SUBMODULE ROM16X1A - INSTANCE LUT4_34 - SUBMODULE ROM16X1A - INSTANCE LUT4_35 - SUBMODULE ROM16X1A - INSTANCE LUT4_36 - SUBMODULE ROM16X1A - INSTANCE LUT4_37 - SUBMODULE ROM16X1A - INSTANCE LUT4_38 - SUBMODULE ROM16X1A - INSTANCE LUT4_39 - SUBMODULE ROM16X1A - INSTANCE LUT4_40 - SUBMODULE ROM16X1A - INSTANCE LUT4_41 - SUBMODULE ROM16X1A - INSTANCE LUT4_42 - SUBMODULE ROM16X1A - INSTANCE LUT4_43 - SUBMODULE ROM16X1A - INSTANCE LUT4_44 - SUBMODULE ROM16X1A - INSTANCE LUT4_45 - SUBMODULE ROM16X1A - INSTANCE LUT4_46 - SUBMODULE ROM16X1A - INSTANCE LUT4_47 - SUBMODULE ROM16X1A - INSTANCE LUT4_48 - SUBMODULE ROM16X1A - INSTANCE LUT4_49 - SUBMODULE ROM16X1A - INSTANCE LUT4_50 - SUBMODULE ROM16X1A - INSTANCE LUT4_51 - SUBMODULE ROM16X1A - INSTANCE LUT4_52 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE XOR2 - INSTANCE XOR2_t24 - SUBMODULE XOR2 - INSTANCE XOR2_t25 - SUBMODULE XOR2 - INSTANCE XOR2_t26 - SUBMODULE XOR2 - INSTANCE XOR2_t27 - SUBMODULE XOR2 - INSTANCE XOR2_t28 - SUBMODULE XOR2 - INSTANCE XOR2_t29 - SUBMODULE XOR2 - INSTANCE XOR2_t30 - SUBMODULE XOR2 - INSTANCE XOR2_t31 - SUBMODULE XOR2 - INSTANCE XOR2_t32 - SUBMODULE XOR2 - INSTANCE XOR2_t33 - SUBMODULE XOR2 - INSTANCE XOR2_t34 - SUBMODULE XOR2 - INSTANCE XOR2_t35 - SUBMODULE XOR2 - INSTANCE XOR2_t36 - SUBMODULE OR2 - INSTANCE OR2_t37 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t38 - SUBMODULE INV - INSTANCE INV_2 - SUBMODULE AND2 - INSTANCE AND2_t39 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.lpc deleted file mode 100755 index aa233bb..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_32kx16x8_mb -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:22:35 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=16 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=16 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=32752 -PfDeassert=506 -RDataCount=1 -WDataCount=1 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.naf b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.naf deleted file mode 100755 index dc502f3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.naf +++ /dev/null @@ -1,98 +0,0 @@ -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -AmEmptyThresh[15] i -AmEmptyThresh[14] i -AmEmptyThresh[13] i -AmEmptyThresh[12] i -AmEmptyThresh[11] i -AmEmptyThresh[10] i -AmEmptyThresh[9] i -AmEmptyThresh[8] i -AmEmptyThresh[7] i -AmEmptyThresh[6] i -AmEmptyThresh[5] i -AmEmptyThresh[4] i -AmEmptyThresh[3] i -AmEmptyThresh[2] i -AmEmptyThresh[1] i -AmEmptyThresh[0] i -AmFullThresh[14] i -AmFullThresh[13] i -AmFullThresh[12] i -AmFullThresh[11] i -AmFullThresh[10] i -AmFullThresh[9] i -AmFullThresh[8] i -AmFullThresh[7] i -AmFullThresh[6] i -AmFullThresh[5] i -AmFullThresh[4] i -AmFullThresh[3] i -AmFullThresh[2] i -AmFullThresh[1] i -AmFullThresh[0] i -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -WCNT[15] o -WCNT[14] o -WCNT[13] o -WCNT[12] o -WCNT[11] o -WCNT[10] o -WCNT[9] o -WCNT[8] o -WCNT[7] o -WCNT[6] o -WCNT[5] o -WCNT[4] o -WCNT[3] o -WCNT[2] o -WCNT[1] o -WCNT[0] o -RCNT[16] o -RCNT[15] o -RCNT[14] o -RCNT[13] o -RCNT[12] o -RCNT[11] o -RCNT[10] o -RCNT[9] o -RCNT[8] o -RCNT[7] o -RCNT[6] o -RCNT[5] o -RCNT[4] o -RCNT[3] o -RCNT[2] o -RCNT[1] o -RCNT[0] o -Empty o -Full o -AlmostEmpty o -AlmostFull o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.sort b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.sort deleted file mode 100644 index db451c2..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_32kx16x8_mb.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.srp b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.srp deleted file mode 100755 index 1b81d02..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.srp +++ /dev/null @@ -1,44 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:22:35 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb.vhd - VHDL template : fifo_32kx16x8_mb_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb.srp - Element Usage : - AGEB2 : 34 - AND2 : 4 - CU2 : 17 - FADD2B : 12 - FSUB2B : 36 - FD1P3BX : 2 - FD1P3DX : 99 - FD1S3BX : 2 - FD1S3DX : 134 - INV : 3 - MUX41 : 8 - OR2 : 1 - ROM16X1A : 53 - XOR2 : 35 - DP16KC : 32 - Estimated Resource Usage: - LUT : 299 - EBR : 32 - Reg : 237 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.sym b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.sym deleted file mode 100644 index 0c68ec94b111666ce5a3ae8f74e9301a7c69834a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 716 zcmY+CKS&#K9L3-FE-H;3jL&fdSme3WcQ1BECj=obuA1-#BtAwNky3Pb|K)w@{?flD9hXDCMmmy6z~j5C(7@ zcHlrKqH8;io#9q|q0`1E?M!8ht8VqYigEU zj&^6X`j@JYKSMQF)1CjQ2Dlw|=4xT*Gl7|rNr|sN6-=jGuUc=Y^D!&t`wtFJ4%3(C zOe_ncIuV|afnj2k2}|BE;Rq(icQ@(TQl{q%BIEnM(ktME-eN_W&SQ<-k0JDP&Ca#&tsf2nR_mcrntnyyDx;;O)-%Knum$$uL;7(c+NSdjZ zSV+r5L(n%kAI~|XI77}zT(M2I#a3*QEqP@;V7|}0_wibBM@`}=E|3c-ki-5Mm#a8Q yPD+zK;Twx_ohlxHUmDtqd*mLzDGta1&J?%FZTwQ~lYMk`CppQ!DF4Bky7C`BEQNLe diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd deleted file mode 100755 index a24a3e6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd +++ /dev/null @@ -1,3997 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e - --- Thu Sep 22 11:22:35 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_32kx16x8_mb is - port ( - Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(7 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end fifo_32kx16x8_mb; - -architecture Structure of fifo_32kx16x8_mb is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal rcount_w0: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal rcnt_reg_15_inv: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal wptr_15: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_16: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal rcnt_reg_16: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co7: std_logic; - signal wcount_15: std_logic; - signal co6: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal wcnt_sub_0: std_logic; - signal wcnt_sub_1: std_logic; - signal wcnt_sub_2: std_logic; - signal co0_2: std_logic; - signal wcnt_sub_3: std_logic; - signal wcnt_sub_4: std_logic; - signal co1_2: std_logic; - signal wcnt_sub_5: std_logic; - signal wcnt_sub_6: std_logic; - signal co2_2: std_logic; - signal wcnt_sub_7: std_logic; - signal wcnt_sub_8: std_logic; - signal co3_2: std_logic; - signal wcnt_sub_9: std_logic; - signal wcnt_sub_10: std_logic; - signal co4_2: std_logic; - signal wcnt_sub_11: std_logic; - signal wcnt_sub_12: std_logic; - signal co5_2: std_logic; - signal wcnt_sub_13: std_logic; - signal wcnt_sub_14: std_logic; - signal co6_2: std_logic; - signal wcnt_sub_15: std_logic; - signal co7_2: std_logic; - signal wcnt_sub_msb: std_logic; - signal rcnt_sub_0: std_logic; - signal rcnt_sub_1: std_logic; - signal rcnt_sub_2: std_logic; - signal co0_3: std_logic; - signal rcnt_sub_3: std_logic; - signal rcnt_sub_4: std_logic; - signal co1_3: std_logic; - signal rcnt_sub_5: std_logic; - signal rcnt_sub_6: std_logic; - signal co2_3: std_logic; - signal rcnt_sub_7: std_logic; - signal rcnt_sub_8: std_logic; - signal co3_3: std_logic; - signal rcnt_sub_9: std_logic; - signal rcnt_sub_10: std_logic; - signal co4_3: std_logic; - signal rcnt_sub_11: std_logic; - signal rcnt_sub_12: std_logic; - signal co5_3: std_logic; - signal rcnt_sub_13: std_logic; - signal rcnt_sub_14: std_logic; - signal co6_3: std_logic; - signal rcnt_sub_15: std_logic; - signal rcnt_sub_16: std_logic; - signal co7_3: std_logic; - signal rcnt_sub_msb: std_logic; - signal co8_1d: std_logic; - signal co8_1: std_logic; - signal wfill_sub_0: std_logic; - signal wptr_0: std_logic; - signal wfill_sub_1: std_logic; - signal wfill_sub_2: std_logic; - signal co0_4: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wfill_sub_3: std_logic; - signal wfill_sub_4: std_logic; - signal co1_4: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wfill_sub_5: std_logic; - signal wfill_sub_6: std_logic; - signal co2_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wfill_sub_7: std_logic; - signal wfill_sub_8: std_logic; - signal co3_4: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wfill_sub_9: std_logic; - signal wfill_sub_10: std_logic; - signal co4_4: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wfill_sub_11: std_logic; - signal wfill_sub_12: std_logic; - signal co5_4: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wfill_sub_13: std_logic; - signal wfill_sub_14: std_logic; - signal co6_4: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wfill_sub_15: std_logic; - signal co7_4: std_logic; - signal wfill_sub_msb: std_logic; - signal rfill_sub_0: std_logic; - signal rptr_0: std_logic; - signal scuba_vhi: std_logic; - signal rfill_sub_1: std_logic; - signal rfill_sub_2: std_logic; - signal co0_5: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rfill_sub_3: std_logic; - signal rfill_sub_4: std_logic; - signal co1_5: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rfill_sub_5: std_logic; - signal rfill_sub_6: std_logic; - signal co2_5: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rfill_sub_7: std_logic; - signal rfill_sub_8: std_logic; - signal co3_5: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rfill_sub_9: std_logic; - signal rfill_sub_10: std_logic; - signal co4_5: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rfill_sub_11: std_logic; - signal rfill_sub_12: std_logic; - signal co5_5: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rfill_sub_13: std_logic; - signal rfill_sub_14: std_logic; - signal co6_5: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rfill_sub_15: std_logic; - signal rfill_sub_16: std_logic; - signal co7_5: std_logic; - signal rptr_15: std_logic; - signal rfill_sub_msb: std_logic; - signal co8_2d: std_logic; - signal co8_2: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_6: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_6: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_6: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_6: std_logic; - signal wcount_r7: std_logic; - signal wcount_r8: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_6: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_6: std_logic; - signal wcount_r11: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_6: std_logic; - signal wcount_r13: std_logic; - signal wcount_r14: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_6: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_7: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_7: std_logic; - signal rcount_w7: std_logic; - signal rcount_w8: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_7: std_logic; - signal rcount_w9: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_7: std_logic; - signal rcount_w11: std_logic; - signal rcount_w12: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w14: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_7: std_logic; - signal rcount_w15: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_14: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; - signal co0_8: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; - signal co1_8: std_logic; - signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; - signal co2_8: std_logic; - signal rcnt_reg_6: std_logic; - signal rcnt_reg_7: std_logic; - signal co3_8: std_logic; - signal rcnt_reg_8: std_logic; - signal rcnt_reg_9: std_logic; - signal co4_8: std_logic; - signal rcnt_reg_10: std_logic; - signal rcnt_reg_11: std_logic; - signal co5_8: std_logic; - signal rcnt_reg_12: std_logic; - signal rcnt_reg_13: std_logic; - signal co6_8: std_logic; - signal rcnt_reg_14: std_logic; - signal rcnt_reg_15: std_logic; - signal co7_7: std_logic; - signal ae_clrsig: std_logic; - signal ae_setsig: std_logic; - signal ae_d: std_logic; - signal ae_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_3: std_logic; - signal wcnt_reg_0: std_logic; - signal wcnt_reg_1: std_logic; - signal co0_9: std_logic; - signal wcnt_reg_2: std_logic; - signal wcnt_reg_3: std_logic; - signal co1_9: std_logic; - signal wcnt_reg_4: std_logic; - signal wcnt_reg_5: std_logic; - signal co2_9: std_logic; - signal wcnt_reg_6: std_logic; - signal wcnt_reg_7: std_logic; - signal co3_9: std_logic; - signal wcnt_reg_8: std_logic; - signal wcnt_reg_9: std_logic; - signal co4_9: std_logic; - signal wcnt_reg_10: std_logic; - signal wcnt_reg_11: std_logic; - signal co5_9: std_logic; - signal wcnt_reg_12: std_logic; - signal wcnt_reg_13: std_logic; - signal co6_9: std_logic; - signal wcnt_reg_14: std_logic; - signal wcnt_reg_15: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX41 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; SD1: in std_logic; SD2: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; - attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; - attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; - attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; - attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; - attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; - attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; - attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; - attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; - attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; - attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; - attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; - attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; - attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; - attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; - attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; - attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; - attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; - attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; - attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; - attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; - attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; - attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; - attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; - attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; - attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; - attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; - attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; - attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; - attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; - attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; - attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC"; - attribute GSR of FF_236 : label is "ENABLED"; - attribute GSR of FF_235 : label is "ENABLED"; - attribute GSR of FF_234 : label is "ENABLED"; - attribute GSR of FF_233 : label is "ENABLED"; - attribute GSR of FF_232 : label is "ENABLED"; - attribute GSR of FF_231 : label is "ENABLED"; - attribute GSR of FF_230 : label is "ENABLED"; - attribute GSR of FF_229 : label is "ENABLED"; - attribute GSR of FF_228 : label is "ENABLED"; - attribute GSR of FF_227 : label is "ENABLED"; - attribute GSR of FF_226 : label is "ENABLED"; - attribute GSR of FF_225 : label is "ENABLED"; - attribute GSR of FF_224 : label is "ENABLED"; - attribute GSR of FF_223 : label is "ENABLED"; - attribute GSR of FF_222 : label is "ENABLED"; - attribute GSR of FF_221 : label is "ENABLED"; - attribute GSR of FF_220 : label is "ENABLED"; - attribute GSR of FF_219 : label is "ENABLED"; - attribute GSR of FF_218 : label is "ENABLED"; - attribute GSR of FF_217 : label is "ENABLED"; - attribute GSR of FF_216 : label is "ENABLED"; - attribute GSR of FF_215 : label is "ENABLED"; - attribute GSR of FF_214 : label is "ENABLED"; - attribute GSR of FF_213 : label is "ENABLED"; - attribute GSR of FF_212 : label is "ENABLED"; - attribute GSR of FF_211 : label is "ENABLED"; - attribute GSR of FF_210 : label is "ENABLED"; - attribute GSR of FF_209 : label is "ENABLED"; - attribute GSR of FF_208 : label is "ENABLED"; - attribute GSR of FF_207 : label is "ENABLED"; - attribute GSR of FF_206 : label is "ENABLED"; - attribute GSR of FF_205 : label is "ENABLED"; - attribute GSR of FF_204 : label is "ENABLED"; - attribute GSR of FF_203 : label is "ENABLED"; - attribute GSR of FF_202 : label is "ENABLED"; - attribute GSR of FF_201 : label is "ENABLED"; - attribute GSR of FF_200 : label is "ENABLED"; - attribute GSR of FF_199 : label is "ENABLED"; - attribute GSR of FF_198 : label is "ENABLED"; - attribute GSR of FF_197 : label is "ENABLED"; - attribute GSR of FF_196 : label is "ENABLED"; - attribute GSR of FF_195 : label is "ENABLED"; - attribute GSR of FF_194 : label is "ENABLED"; - attribute GSR of FF_193 : label is "ENABLED"; - attribute GSR of FF_192 : label is "ENABLED"; - attribute GSR of FF_191 : label is "ENABLED"; - attribute GSR of FF_190 : label is "ENABLED"; - attribute GSR of FF_189 : label is "ENABLED"; - attribute GSR of FF_188 : label is "ENABLED"; - attribute GSR of FF_187 : label is "ENABLED"; - attribute GSR of FF_186 : label is "ENABLED"; - attribute GSR of FF_185 : label is "ENABLED"; - attribute GSR of FF_184 : label is "ENABLED"; - attribute GSR of FF_183 : label is "ENABLED"; - attribute GSR of FF_182 : label is "ENABLED"; - attribute GSR of FF_181 : label is "ENABLED"; - attribute GSR of FF_180 : label is "ENABLED"; - attribute GSR of FF_179 : label is "ENABLED"; - attribute GSR of FF_178 : label is "ENABLED"; - attribute GSR of FF_177 : label is "ENABLED"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t39: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_2: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t38: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_1: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t37: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t36: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t35: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t34: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t33: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t32: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t31: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t30: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t29: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t28: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t27: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t26: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t25: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t24: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t23: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t22: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t21: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t20: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t19: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t18: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t17: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t16: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t15: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t14: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t13: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t12: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t11: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t9: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t8: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t7: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t6: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - XOR2_t5: XOR2 - port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); - - XOR2_t4: XOR2 - port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); - - XOR2_t3: XOR2 - port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - INV_0: INV - port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_1_30: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_2_29: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_3_28: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_4_27: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_5_26: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_6_25: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_7_24: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_1_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_2_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_3_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_4_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_5_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_6_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_7_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_15: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_1_14: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_2_13: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_3_12: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_4_11: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_5_10: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_6_9: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_7_8: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_7: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_1_6: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_2_5: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_3_4: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_4_3: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_5_2: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_6_1: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_7_0: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_236: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_235: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_234: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_233: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_232: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_231: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_230: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_229: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_228: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_227: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_226: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_225: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_224: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_223: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_222: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_221: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_220: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_219: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_218: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_217: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_216: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_215: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_214: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_213: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_212: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_211: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_210: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_209: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_208: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_207: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_206: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_205: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_204: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_203: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_202: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_201: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_200: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_199: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_198: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_197: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_196: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_195: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_194: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_193: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_192: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_191: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_190: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_189: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_188: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_187: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_186: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_185: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_184: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_183: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_182: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_181: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_180: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_179: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_178: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_177: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_176: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_175: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_174: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_173: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_172: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_171: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_170: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_169: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_168: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_167: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_166: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_165: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_164: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_163: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_162: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_161: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_160: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_159: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_158: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_157: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_156: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_155: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_154: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_153: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_152: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_151: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_150: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_149: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_148: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_147: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_146: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_145: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_144: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_143: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_142: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_141: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_140: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_139: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_138: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_137: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_136: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_135: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_134: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_133: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_132: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_131: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_130: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_129: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_128: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_127: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_126: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_125: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_124: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_123: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_122: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_121: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_120: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_119: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_118: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_117: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_116: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_115: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_114: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_113: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_112: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_111: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_110: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_109: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_108: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_107: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_106: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_105: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_104: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_103: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_102: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_101: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_100: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_99: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_98: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_97: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_96: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_95: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_94: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_93: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_92: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_91: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_90: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_89: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_88: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_87: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_86: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_85: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_84: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_83: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_82: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_81: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_80: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_79: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_78: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_77: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_76: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_75: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_74: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_73: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_72: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_71: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_70: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_69: FD1S3DX - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); - - FF_68: FD1S3DX - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); - - FF_67: FD1S3DX - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); - - FF_66: FD1S3DX - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); - - FF_65: FD1S3DX - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); - - FF_64: FD1S3DX - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); - - FF_63: FD1S3DX - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); - - FF_62: FD1S3DX - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); - - FF_61: FD1S3DX - port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); - - FF_60: FD1S3DX - port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); - - FF_59: FD1S3DX - port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); - - FF_58: FD1S3DX - port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); - - FF_57: FD1S3DX - port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); - - FF_56: FD1S3DX - port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); - - FF_55: FD1S3DX - port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); - - FF_54: FD1S3DX - port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); - - FF_53: FD1S3DX - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_52: FD1S3DX - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_51: FD1S3DX - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_50: FD1S3DX - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_49: FD1S3DX - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_48: FD1S3DX - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_47: FD1S3DX - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); - - FF_46: FD1S3DX - port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); - - FF_45: FD1S3DX - port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); - - FF_44: FD1S3DX - port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); - - FF_43: FD1S3DX - port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); - - FF_42: FD1S3DX - port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); - - FF_41: FD1S3DX - port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); - - FF_40: FD1S3DX - port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); - - FF_39: FD1S3DX - port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); - - FF_38: FD1S3DX - port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); - - FF_37: FD1S3DX - port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); - - FF_36: FD1S3DX - port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); - - FF_35: FD1S3DX - port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); - - FF_34: FD1S3DX - port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); - - FF_33: FD1S3DX - port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); - - FF_32: FD1S3DX - port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); - - FF_31: FD1S3DX - port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); - - FF_30: FD1S3DX - port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); - - FF_29: FD1S3DX - port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); - - FF_28: FD1S3DX - port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); - - FF_27: FD1S3DX - port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); - - FF_26: FD1S3DX - port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); - - FF_25: FD1S3DX - port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); - - FF_24: FD1S3DX - port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); - - FF_23: FD1S3DX - port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); - - FF_22: FD1S3DX - port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); - - FF_21: FD1S3DX - port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); - - FF_20: FD1S3DX - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); - - FF_19: FD1S3DX - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); - - FF_18: FD1S3DX - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); - - FF_17: FD1S3DX - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); - - FF_16: FD1S3DX - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); - - FF_15: FD1S3DX - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); - - FF_14: FD1S3DX - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); - - FF_13: FD1S3DX - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); - - FF_12: FD1S3DX - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); - - FF_11: FD1S3DX - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); - - FF_10: FD1S3DX - port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); - - FF_9: FD1S3DX - port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); - - FF_8: FD1S3DX - port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); - - FF_7: FD1S3DX - port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); - - FF_6: FD1S3DX - port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); - - FF_5: FD1S3DX - port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); - - FF_4: FD1S3DX - port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); - - FF_3: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_2: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_1: FD1S3BX - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_0: FD1S3DX - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>ircount_16, NC1=>open); - - mux_7: MUX41 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); - - mux_6: MUX41 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); - - mux_5: MUX41 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); - - mux_4: MUX41 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); - - mux_3: MUX41 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); - - mux_2: MUX41 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); - - mux_1: MUX41 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); - - mux_0: MUX41 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); - - wcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, - S1=>wcnt_sub_0); - - wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, - B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, - S1=>wcnt_sub_2); - - wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, - B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, - S1=>wcnt_sub_4); - - wcnt_3: FSUB2B - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, - B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, - S1=>wcnt_sub_6); - - wcnt_4: FSUB2B - port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, - B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, - S1=>wcnt_sub_8); - - wcnt_5: FSUB2B - port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, - S1=>wcnt_sub_10); - - wcnt_6: FSUB2B - port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, - S0=>wcnt_sub_11, S1=>wcnt_sub_12); - - wcnt_7: FSUB2B - port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, - S1=>wcnt_sub_14); - - wcnt_8: FSUB2B - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, - S1=>open); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, - B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, - B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, - B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcnt_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, - B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, - S1=>rcnt_sub_8); - - rcnt_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, - B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, - S1=>rcnt_sub_10); - - rcnt_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, - B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, - S1=>rcnt_sub_12); - - rcnt_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, - B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, - S1=>rcnt_sub_14); - - rcnt_8: FSUB2B - port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, - B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, - S1=>rcnt_sub_16); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); - - wfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, - S1=>wfill_sub_0); - - wfill_1: FSUB2B - port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, - BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); - - wfill_2: FSUB2B - port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, - BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); - - wfill_3: FSUB2B - port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, - BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); - - wfill_4: FSUB2B - port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, - BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); - - wfill_5: FSUB2B - port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, - S1=>wfill_sub_10); - - wfill_6: FSUB2B - port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, - S0=>wfill_sub_11, S1=>wfill_sub_12); - - wfill_7: FSUB2B - port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, - S1=>wfill_sub_14); - - wfill_8: FSUB2B - port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, - S1=>rfill_sub_0); - - rfill_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, - BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); - - rfill_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, - BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); - - rfill_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, - BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); - - rfill_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, - BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); - - rfill_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, - BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); - - rfill_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, - B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, - S1=>rfill_sub_12); - - rfill_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, - B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, - S1=>rfill_sub_14); - - rfill_8: FSUB2B - port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, - B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, - S1=>rfill_sub_16); - - rfilld: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_6, GE=>co1_6); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_6, GE=>co2_6); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_6, GE=>co3_6); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>wcount_r8, CI=>co3_6, GE=>co4_6); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_6, GE=>co5_6); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, - B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, - B1=>wcount_r14, CI=>co6_6, GE=>co7_6); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_7, GE=>co1_7); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_7, GE=>co2_7); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_7, GE=>co3_7); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_7, GE=>co4_7); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, - B1=>rcount_w12, CI=>co4_7, GE=>co5_7); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w14, CI=>co5_7, GE=>co6_7); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, - B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); - - ae_cmp_3: AGEB2 - port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), - B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); - - ae_cmp_4: AGEB2 - port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), - B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); - - ae_cmp_5: AGEB2 - port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), - B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); - - ae_cmp_6: AGEB2 - port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), - B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); - - ae_cmp_7: AGEB2 - port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), - B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); - - ae_cmp_8: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - - af_d_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_d_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); - - af_d_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); - - af_d_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); - - af_d_cmp_3: AGEB2 - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); - - af_d_cmp_4: AGEB2 - port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), - B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); - - af_d_cmp_5: AGEB2 - port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), - B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); - - af_d_cmp_6: AGEB2 - port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), - B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); - - af_d_cmp_7: AGEB2 - port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), - B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_32kx16x8_mb is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX41 use entity ecp3.MUX41(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.ipx deleted file mode 100644 index ed7a28f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.jhd deleted file mode 100644 index 2528505..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.jhd +++ /dev/null @@ -1,1233 +0,0 @@ -MODULE fifo_32kx16x8_mb2 DEFIN fifo_32kx16x8_mb2.vhd - SUBMODULE FADD2B - INSTANCE a3 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE af_d_cmp_7 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_6 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_5 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_4 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_3 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_2 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_1 - SUBMODULE AGEB2 - INSTANCE af_d_cmp_0 - SUBMODULE FADD2B - INSTANCE af_d_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a2 - SUBMODULE AGEB2 - INSTANCE ae_cmp_8 - SUBMODULE AGEB2 - INSTANCE ae_cmp_7 - SUBMODULE AGEB2 - INSTANCE ae_cmp_6 - SUBMODULE AGEB2 - INSTANCE ae_cmp_5 - SUBMODULE AGEB2 - INSTANCE ae_cmp_4 - SUBMODULE AGEB2 - INSTANCE ae_cmp_3 - SUBMODULE AGEB2 - INSTANCE ae_cmp_2 - SUBMODULE AGEB2 - INSTANCE ae_cmp_1 - SUBMODULE AGEB2 - INSTANCE ae_cmp_0 - SUBMODULE FADD2B - INSTANCE ae_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE AGEB2 - INSTANCE full_cmp_7 - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_8 - SUBMODULE AGEB2 - INSTANCE empty_cmp_7 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE FADD2B - INSTANCE rfilld - SUBMODULE FSUB2B - INSTANCE rfill_8 - SUBMODULE FSUB2B - INSTANCE rfill_7 - SUBMODULE FSUB2B - INSTANCE rfill_6 - SUBMODULE FSUB2B - INSTANCE rfill_5 - SUBMODULE FSUB2B - INSTANCE rfill_4 - SUBMODULE FSUB2B - INSTANCE rfill_3 - SUBMODULE FSUB2B - INSTANCE rfill_2 - SUBMODULE FSUB2B - INSTANCE rfill_1 - SUBMODULE FSUB2B - INSTANCE rfill_0 - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE FSUB2B - INSTANCE wfill_8 - SUBMODULE FSUB2B - INSTANCE wfill_7 - SUBMODULE FSUB2B - INSTANCE wfill_6 - SUBMODULE FSUB2B - INSTANCE wfill_5 - SUBMODULE FSUB2B - INSTANCE wfill_4 - SUBMODULE FSUB2B - INSTANCE wfill_3 - SUBMODULE FSUB2B - INSTANCE wfill_2 - SUBMODULE FSUB2B - INSTANCE wfill_1 - SUBMODULE FSUB2B - INSTANCE wfill_0 - SUBMODULE FADD2B - INSTANCE rcntd - SUBMODULE FSUB2B - INSTANCE rcnt_8 - SUBMODULE FSUB2B - INSTANCE rcnt_7 - SUBMODULE FSUB2B - INSTANCE rcnt_6 - SUBMODULE FSUB2B - INSTANCE rcnt_5 - SUBMODULE FSUB2B - INSTANCE rcnt_4 - SUBMODULE FSUB2B - INSTANCE rcnt_3 - SUBMODULE FSUB2B - INSTANCE rcnt_2 - SUBMODULE FSUB2B - INSTANCE rcnt_1 - SUBMODULE FSUB2B - INSTANCE rcnt_0 - SUBMODULE FSUB2B - INSTANCE wcnt_8 - SUBMODULE FSUB2B - INSTANCE wcnt_7 - SUBMODULE FSUB2B - INSTANCE wcnt_6 - SUBMODULE FSUB2B - INSTANCE wcnt_5 - SUBMODULE FSUB2B - INSTANCE wcnt_4 - SUBMODULE FSUB2B - INSTANCE wcnt_3 - SUBMODULE FSUB2B - INSTANCE wcnt_2 - SUBMODULE FSUB2B - INSTANCE wcnt_1 - SUBMODULE FSUB2B - INSTANCE wcnt_0 - SUBMODULE MUX321 - INSTANCE mux_0 - SUBMODULE MUX321 - INSTANCE mux_1 - SUBMODULE MUX321 - INSTANCE mux_2 - SUBMODULE MUX321 - INSTANCE mux_3 - SUBMODULE MUX321 - INSTANCE mux_4 - SUBMODULE MUX321 - INSTANCE mux_5 - SUBMODULE MUX321 - INSTANCE mux_6 - SUBMODULE MUX321 - INSTANCE mux_7 - SUBMODULE MUX321 - INSTANCE mux_8 - SUBMODULE CU2 - INSTANCE r_gctr_8 - SUBMODULE CU2 - INSTANCE r_gctr_7 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE CU2 - INSTANCE w_gctr_7 - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3BX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1S3DX - INSTANCE FF_54 - SUBMODULE FD1S3DX - INSTANCE FF_55 - SUBMODULE FD1S3DX - INSTANCE FF_56 - SUBMODULE FD1S3DX - INSTANCE FF_57 - SUBMODULE FD1S3DX - INSTANCE FF_58 - SUBMODULE FD1S3DX - INSTANCE FF_59 - SUBMODULE FD1S3DX - INSTANCE FF_60 - SUBMODULE FD1S3DX - INSTANCE FF_61 - SUBMODULE FD1S3DX - INSTANCE FF_62 - SUBMODULE FD1S3DX - INSTANCE FF_63 - SUBMODULE FD1S3DX - INSTANCE FF_64 - SUBMODULE FD1S3DX - INSTANCE FF_65 - SUBMODULE FD1S3DX - INSTANCE FF_66 - SUBMODULE FD1S3DX - INSTANCE FF_67 - SUBMODULE FD1S3DX - INSTANCE FF_68 - SUBMODULE FD1S3DX - INSTANCE FF_69 - SUBMODULE FD1S3DX - INSTANCE FF_70 - SUBMODULE FD1S3DX - INSTANCE FF_71 - SUBMODULE FD1S3DX - INSTANCE FF_72 - SUBMODULE FD1S3DX - INSTANCE FF_73 - SUBMODULE FD1S3DX - INSTANCE FF_74 - SUBMODULE FD1S3DX - INSTANCE FF_75 - SUBMODULE FD1S3DX - INSTANCE FF_76 - SUBMODULE FD1S3DX - INSTANCE FF_77 - SUBMODULE FD1S3DX - INSTANCE FF_78 - SUBMODULE FD1S3DX - INSTANCE FF_79 - SUBMODULE FD1S3DX - INSTANCE FF_80 - SUBMODULE FD1S3DX - INSTANCE FF_81 - SUBMODULE FD1S3DX - INSTANCE FF_82 - SUBMODULE FD1S3DX - INSTANCE FF_83 - SUBMODULE FD1S3DX - INSTANCE FF_84 - SUBMODULE FD1S3DX - INSTANCE FF_85 - SUBMODULE FD1S3DX - INSTANCE FF_86 - SUBMODULE FD1S3DX - INSTANCE FF_87 - SUBMODULE FD1S3DX - INSTANCE FF_88 - SUBMODULE FD1S3DX - INSTANCE FF_89 - SUBMODULE FD1S3DX - INSTANCE FF_90 - SUBMODULE FD1S3DX - INSTANCE FF_91 - SUBMODULE FD1S3DX - INSTANCE FF_92 - SUBMODULE FD1S3DX - INSTANCE FF_93 - SUBMODULE FD1S3DX - INSTANCE FF_94 - SUBMODULE FD1S3DX - INSTANCE FF_95 - SUBMODULE FD1S3DX - INSTANCE FF_96 - SUBMODULE FD1S3DX - INSTANCE FF_97 - SUBMODULE FD1S3DX - INSTANCE FF_98 - SUBMODULE FD1S3DX - INSTANCE FF_99 - SUBMODULE FD1S3DX - INSTANCE FF_100 - SUBMODULE FD1S3DX - INSTANCE FF_101 - SUBMODULE FD1S3DX - INSTANCE FF_102 - SUBMODULE FD1S3DX - INSTANCE FF_103 - SUBMODULE FD1S3DX - INSTANCE FF_104 - SUBMODULE FD1S3DX - INSTANCE FF_105 - SUBMODULE FD1S3DX - INSTANCE FF_106 - SUBMODULE FD1S3DX - INSTANCE FF_107 - SUBMODULE FD1S3DX - INSTANCE FF_108 - SUBMODULE FD1S3DX - INSTANCE FF_109 - SUBMODULE FD1S3DX - INSTANCE FF_110 - SUBMODULE FD1S3DX - INSTANCE FF_111 - SUBMODULE FD1S3DX - INSTANCE FF_112 - SUBMODULE FD1S3DX - INSTANCE FF_113 - SUBMODULE FD1S3DX - INSTANCE FF_114 - SUBMODULE FD1S3DX - INSTANCE FF_115 - SUBMODULE FD1S3DX - INSTANCE FF_116 - SUBMODULE FD1S3DX - INSTANCE FF_117 - SUBMODULE FD1S3DX - INSTANCE FF_118 - SUBMODULE FD1S3DX - INSTANCE FF_119 - SUBMODULE FD1S3DX - INSTANCE FF_120 - SUBMODULE FD1S3DX - INSTANCE FF_121 - SUBMODULE FD1S3DX - INSTANCE FF_122 - SUBMODULE FD1S3DX - INSTANCE FF_123 - SUBMODULE FD1S3DX - INSTANCE FF_124 - SUBMODULE FD1S3DX - INSTANCE FF_125 - SUBMODULE FD1S3DX - INSTANCE FF_126 - SUBMODULE FD1S3DX - INSTANCE FF_127 - SUBMODULE FD1S3DX - INSTANCE FF_128 - SUBMODULE FD1S3DX - INSTANCE FF_129 - SUBMODULE FD1S3DX - INSTANCE FF_130 - SUBMODULE FD1S3DX - INSTANCE FF_131 - SUBMODULE FD1S3DX - INSTANCE FF_132 - SUBMODULE FD1S3DX - INSTANCE FF_133 - SUBMODULE FD1S3DX - INSTANCE FF_134 - SUBMODULE FD1S3DX - INSTANCE FF_135 - SUBMODULE FD1P3DX - INSTANCE FF_136 - SUBMODULE FD1P3DX - INSTANCE FF_137 - SUBMODULE FD1P3DX - INSTANCE FF_138 - SUBMODULE FD1P3DX - INSTANCE FF_139 - SUBMODULE FD1P3DX - INSTANCE FF_140 - SUBMODULE FD1P3DX - INSTANCE FF_141 - SUBMODULE FD1P3DX - INSTANCE FF_142 - SUBMODULE FD1P3DX - INSTANCE FF_143 - SUBMODULE FD1P3DX - INSTANCE FF_144 - SUBMODULE FD1P3DX - INSTANCE FF_145 - SUBMODULE FD1P3DX - INSTANCE FF_146 - SUBMODULE FD1P3DX - INSTANCE FF_147 - SUBMODULE FD1P3DX - INSTANCE FF_148 - SUBMODULE FD1P3DX - INSTANCE FF_149 - SUBMODULE FD1P3DX - INSTANCE FF_150 - SUBMODULE FD1P3DX - INSTANCE FF_151 - SUBMODULE FD1P3DX - INSTANCE FF_152 - SUBMODULE FD1P3DX - INSTANCE FF_153 - SUBMODULE FD1P3DX - INSTANCE FF_154 - SUBMODULE FD1P3DX - INSTANCE FF_155 - SUBMODULE FD1P3DX - INSTANCE FF_156 - SUBMODULE FD1P3DX - INSTANCE FF_157 - SUBMODULE FD1P3DX - INSTANCE FF_158 - SUBMODULE FD1P3DX - INSTANCE FF_159 - SUBMODULE FD1P3DX - INSTANCE FF_160 - SUBMODULE FD1P3DX - INSTANCE FF_161 - SUBMODULE FD1P3DX - INSTANCE FF_162 - SUBMODULE FD1P3DX - INSTANCE FF_163 - SUBMODULE FD1P3DX - INSTANCE FF_164 - SUBMODULE FD1P3DX - INSTANCE FF_165 - SUBMODULE FD1P3DX - INSTANCE FF_166 - SUBMODULE FD1P3DX - INSTANCE FF_167 - SUBMODULE FD1P3DX - INSTANCE FF_168 - SUBMODULE FD1P3DX - INSTANCE FF_169 - SUBMODULE FD1P3DX - INSTANCE FF_170 - SUBMODULE FD1P3DX - INSTANCE FF_171 - SUBMODULE FD1P3DX - INSTANCE FF_172 - SUBMODULE FD1P3DX - INSTANCE FF_173 - SUBMODULE FD1P3DX - INSTANCE FF_174 - SUBMODULE FD1P3DX - INSTANCE FF_175 - SUBMODULE FD1P3DX - INSTANCE FF_176 - SUBMODULE FD1P3DX - INSTANCE FF_177 - SUBMODULE FD1P3DX - INSTANCE FF_178 - SUBMODULE FD1P3DX - INSTANCE FF_179 - SUBMODULE FD1P3DX - INSTANCE FF_180 - SUBMODULE FD1P3DX - INSTANCE FF_181 - SUBMODULE FD1P3DX - INSTANCE FF_182 - SUBMODULE FD1P3DX - INSTANCE FF_183 - SUBMODULE FD1P3DX - INSTANCE FF_184 - SUBMODULE FD1P3DX - INSTANCE FF_185 - SUBMODULE FD1P3DX - INSTANCE FF_186 - SUBMODULE FD1P3DX - INSTANCE FF_187 - SUBMODULE FD1P3DX - INSTANCE FF_188 - SUBMODULE FD1P3DX - INSTANCE FF_189 - SUBMODULE FD1P3DX - INSTANCE FF_190 - SUBMODULE FD1P3BX - INSTANCE FF_191 - SUBMODULE FD1P3DX - INSTANCE FF_192 - SUBMODULE FD1P3DX - INSTANCE FF_193 - SUBMODULE FD1P3DX - INSTANCE FF_194 - SUBMODULE FD1P3DX - INSTANCE FF_195 - SUBMODULE FD1P3DX - INSTANCE FF_196 - SUBMODULE FD1P3DX - INSTANCE FF_197 - SUBMODULE FD1P3DX - INSTANCE FF_198 - SUBMODULE FD1P3DX - INSTANCE FF_199 - SUBMODULE FD1P3DX - INSTANCE FF_200 - SUBMODULE FD1P3DX - INSTANCE FF_201 - SUBMODULE FD1P3DX - INSTANCE FF_202 - SUBMODULE FD1P3DX - INSTANCE FF_203 - SUBMODULE FD1P3DX - INSTANCE FF_204 - SUBMODULE FD1P3DX - INSTANCE FF_205 - SUBMODULE FD1P3DX - INSTANCE FF_206 - SUBMODULE FD1P3DX - INSTANCE FF_207 - SUBMODULE FD1P3DX - INSTANCE FF_208 - SUBMODULE FD1P3DX - INSTANCE FF_209 - SUBMODULE FD1P3DX - INSTANCE FF_210 - SUBMODULE FD1P3DX - INSTANCE FF_211 - SUBMODULE FD1P3DX - INSTANCE FF_212 - SUBMODULE FD1P3DX - INSTANCE FF_213 - SUBMODULE FD1P3DX - INSTANCE FF_214 - SUBMODULE FD1P3DX - INSTANCE FF_215 - SUBMODULE FD1P3DX - INSTANCE FF_216 - SUBMODULE FD1P3DX - INSTANCE FF_217 - SUBMODULE FD1P3DX - INSTANCE FF_218 - SUBMODULE FD1P3DX - INSTANCE FF_219 - SUBMODULE FD1P3DX - INSTANCE FF_220 - SUBMODULE FD1P3DX - INSTANCE FF_221 - SUBMODULE FD1P3DX - INSTANCE FF_222 - SUBMODULE FD1P3DX - INSTANCE FF_223 - SUBMODULE FD1P3DX - INSTANCE FF_224 - SUBMODULE FD1P3DX - INSTANCE FF_225 - SUBMODULE FD1P3DX - INSTANCE FF_226 - SUBMODULE FD1P3DX - INSTANCE FF_227 - SUBMODULE FD1P3DX - INSTANCE FF_228 - SUBMODULE FD1P3DX - INSTANCE FF_229 - SUBMODULE FD1P3DX - INSTANCE FF_230 - SUBMODULE FD1P3DX - INSTANCE FF_231 - SUBMODULE FD1P3DX - INSTANCE FF_232 - SUBMODULE FD1P3DX - INSTANCE FF_233 - SUBMODULE FD1P3DX - INSTANCE FF_234 - SUBMODULE FD1P3DX - INSTANCE FF_235 - SUBMODULE FD1P3DX - INSTANCE FF_236 - SUBMODULE FD1P3DX - INSTANCE FF_237 - SUBMODULE FD1P3DX - INSTANCE FF_238 - SUBMODULE FD1P3BX - INSTANCE FF_239 - SUBMODULE DP16KC - INSTANCE pdp_ram_31_0_0 - SUBMODULE DP16KC - INSTANCE pdp_ram_30_0_1 - SUBMODULE DP16KC - INSTANCE pdp_ram_29_0_2 - SUBMODULE DP16KC - INSTANCE pdp_ram_28_0_3 - SUBMODULE DP16KC - INSTANCE pdp_ram_27_0_4 - SUBMODULE DP16KC - INSTANCE pdp_ram_26_0_5 - SUBMODULE DP16KC - INSTANCE pdp_ram_25_0_6 - SUBMODULE DP16KC - INSTANCE pdp_ram_24_0_7 - SUBMODULE DP16KC - INSTANCE pdp_ram_23_0_8 - SUBMODULE DP16KC - INSTANCE pdp_ram_22_0_9 - SUBMODULE DP16KC - INSTANCE pdp_ram_21_0_10 - SUBMODULE DP16KC - INSTANCE pdp_ram_20_0_11 - SUBMODULE DP16KC - INSTANCE pdp_ram_19_0_12 - SUBMODULE DP16KC - INSTANCE pdp_ram_18_0_13 - SUBMODULE DP16KC - INSTANCE pdp_ram_17_0_14 - SUBMODULE DP16KC - INSTANCE pdp_ram_16_0_15 - SUBMODULE DP16KC - INSTANCE pdp_ram_15_0_16 - SUBMODULE DP16KC - INSTANCE pdp_ram_14_0_17 - SUBMODULE DP16KC - INSTANCE pdp_ram_13_0_18 - SUBMODULE DP16KC - INSTANCE pdp_ram_12_0_19 - SUBMODULE DP16KC - INSTANCE pdp_ram_11_0_20 - SUBMODULE DP16KC - INSTANCE pdp_ram_10_0_21 - SUBMODULE DP16KC - INSTANCE pdp_ram_9_0_22 - SUBMODULE DP16KC - INSTANCE pdp_ram_8_0_23 - SUBMODULE DP16KC - INSTANCE pdp_ram_7_0_24 - SUBMODULE DP16KC - INSTANCE pdp_ram_6_0_25 - SUBMODULE DP16KC - INSTANCE pdp_ram_5_0_26 - SUBMODULE DP16KC - INSTANCE pdp_ram_4_0_27 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_0_28 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_0_29 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_0_30 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_31 - SUBMODULE AND2 - INSTANCE AND2_t0 - SUBMODULE AND2 - INSTANCE AND2_t1 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE ROM16X1A - INSTANCE LUT4_30 - SUBMODULE ROM16X1A - INSTANCE LUT4_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_32 - SUBMODULE ROM16X1A - INSTANCE LUT4_33 - SUBMODULE ROM16X1A - INSTANCE LUT4_34 - SUBMODULE ROM16X1A - INSTANCE LUT4_35 - SUBMODULE ROM16X1A - INSTANCE LUT4_36 - SUBMODULE ROM16X1A - INSTANCE LUT4_37 - SUBMODULE ROM16X1A - INSTANCE LUT4_38 - SUBMODULE ROM16X1A - INSTANCE LUT4_39 - SUBMODULE ROM16X1A - INSTANCE LUT4_40 - SUBMODULE ROM16X1A - INSTANCE LUT4_41 - SUBMODULE ROM16X1A - INSTANCE LUT4_42 - SUBMODULE ROM16X1A - INSTANCE LUT4_43 - SUBMODULE ROM16X1A - INSTANCE LUT4_44 - SUBMODULE ROM16X1A - INSTANCE LUT4_45 - SUBMODULE ROM16X1A - INSTANCE LUT4_46 - SUBMODULE ROM16X1A - INSTANCE LUT4_47 - SUBMODULE ROM16X1A - INSTANCE LUT4_48 - SUBMODULE ROM16X1A - INSTANCE LUT4_49 - SUBMODULE ROM16X1A - INSTANCE LUT4_50 - SUBMODULE ROM16X1A - INSTANCE LUT4_51 - SUBMODULE ROM16X1A - INSTANCE LUT4_52 - SUBMODULE ROM16X1A - INSTANCE LUT4_53 - SUBMODULE ROM16X1A - INSTANCE LUT4_54 - SUBMODULE ROM16X1A - INSTANCE LUT4_55 - SUBMODULE ROM16X1A - INSTANCE LUT4_56 - SUBMODULE ROM16X1A - INSTANCE LUT4_57 - SUBMODULE ROM16X1A - INSTANCE LUT4_58 - SUBMODULE ROM16X1A - INSTANCE LUT4_59 - SUBMODULE ROM16X1A - INSTANCE LUT4_60 - SUBMODULE ROM16X1A - INSTANCE LUT4_61 - SUBMODULE ROM16X1A - INSTANCE LUT4_62 - SUBMODULE ROM16X1A - INSTANCE LUT4_63 - SUBMODULE ROM16X1A - INSTANCE LUT4_64 - SUBMODULE ROM16X1A - INSTANCE LUT4_65 - SUBMODULE ROM16X1A - INSTANCE LUT4_66 - SUBMODULE ROM16X1A - INSTANCE LUT4_67 - SUBMODULE ROM16X1A - INSTANCE LUT4_68 - SUBMODULE ROM16X1A - INSTANCE LUT4_69 - SUBMODULE ROM16X1A - INSTANCE LUT4_70 - SUBMODULE ROM16X1A - INSTANCE LUT4_71 - SUBMODULE ROM16X1A - INSTANCE LUT4_72 - SUBMODULE ROM16X1A - INSTANCE LUT4_73 - SUBMODULE ROM16X1A - INSTANCE LUT4_74 - SUBMODULE ROM16X1A - INSTANCE LUT4_75 - SUBMODULE ROM16X1A - INSTANCE LUT4_76 - SUBMODULE ROM16X1A - INSTANCE LUT4_77 - SUBMODULE ROM16X1A - INSTANCE LUT4_78 - SUBMODULE ROM16X1A - INSTANCE LUT4_79 - SUBMODULE ROM16X1A - INSTANCE LUT4_80 - SUBMODULE ROM16X1A - INSTANCE LUT4_81 - SUBMODULE ROM16X1A - INSTANCE LUT4_82 - SUBMODULE ROM16X1A - INSTANCE LUT4_83 - SUBMODULE ROM16X1A - INSTANCE LUT4_84 - SUBMODULE ROM16X1A - INSTANCE LUT4_85 - SUBMODULE ROM16X1A - INSTANCE LUT4_86 - SUBMODULE ROM16X1A - INSTANCE LUT4_87 - SUBMODULE ROM16X1A - INSTANCE LUT4_88 - SUBMODULE ROM16X1A - INSTANCE LUT4_89 - SUBMODULE ROM16X1A - INSTANCE LUT4_90 - SUBMODULE ROM16X1A - INSTANCE LUT4_91 - SUBMODULE ROM16X1A - INSTANCE LUT4_92 - SUBMODULE ROM16X1A - INSTANCE LUT4_93 - SUBMODULE ROM16X1A - INSTANCE LUT4_94 - SUBMODULE ROM16X1A - INSTANCE LUT4_95 - SUBMODULE ROM16X1A - INSTANCE LUT4_96 - SUBMODULE ROM16X1A - INSTANCE LUT4_97 - SUBMODULE ROM16X1A - INSTANCE LUT4_98 - SUBMODULE ROM16X1A - INSTANCE LUT4_99 - SUBMODULE ROM16X1A - INSTANCE LUT4_100 - SUBMODULE ROM16X1A - INSTANCE LUT4_101 - SUBMODULE ROM16X1A - INSTANCE LUT4_102 - SUBMODULE ROM16X1A - INSTANCE LUT4_103 - SUBMODULE ROM16X1A - INSTANCE LUT4_104 - SUBMODULE ROM16X1A - INSTANCE LUT4_105 - SUBMODULE ROM16X1A - INSTANCE LUT4_106 - SUBMODULE ROM16X1A - INSTANCE LUT4_107 - SUBMODULE ROM16X1A - INSTANCE LUT4_108 - SUBMODULE ROM16X1A - INSTANCE LUT4_109 - SUBMODULE ROM16X1A - INSTANCE LUT4_110 - SUBMODULE ROM16X1A - INSTANCE LUT4_111 - SUBMODULE ROM16X1A - INSTANCE LUT4_112 - SUBMODULE ROM16X1A - INSTANCE LUT4_113 - SUBMODULE ROM16X1A - INSTANCE LUT4_114 - SUBMODULE ROM16X1A - INSTANCE LUT4_115 - SUBMODULE ROM16X1A - INSTANCE LUT4_116 - SUBMODULE ROM16X1A - INSTANCE LUT4_117 - SUBMODULE ROM16X1A - INSTANCE LUT4_118 - SUBMODULE ROM16X1A - INSTANCE LUT4_119 - SUBMODULE ROM16X1A - INSTANCE LUT4_120 - SUBMODULE ROM16X1A - INSTANCE LUT4_121 - SUBMODULE ROM16X1A - INSTANCE LUT4_122 - SUBMODULE ROM16X1A - INSTANCE LUT4_123 - SUBMODULE ROM16X1A - INSTANCE LUT4_124 - SUBMODULE ROM16X1A - INSTANCE LUT4_125 - SUBMODULE ROM16X1A - INSTANCE LUT4_126 - SUBMODULE ROM16X1A - INSTANCE LUT4_127 - SUBMODULE ROM16X1A - INSTANCE LUT4_128 - SUBMODULE ROM16X1A - INSTANCE LUT4_129 - SUBMODULE ROM16X1A - INSTANCE LUT4_130 - SUBMODULE ROM16X1A - INSTANCE LUT4_131 - SUBMODULE ROM16X1A - INSTANCE LUT4_132 - SUBMODULE ROM16X1A - INSTANCE LUT4_133 - SUBMODULE ROM16X1A - INSTANCE LUT4_134 - SUBMODULE ROM16X1A - INSTANCE LUT4_135 - SUBMODULE ROM16X1A - INSTANCE LUT4_136 - SUBMODULE ROM16X1A - INSTANCE LUT4_137 - SUBMODULE ROM16X1A - INSTANCE LUT4_138 - SUBMODULE ROM16X1A - INSTANCE LUT4_139 - SUBMODULE ROM16X1A - INSTANCE LUT4_140 - SUBMODULE ROM16X1A - INSTANCE LUT4_141 - SUBMODULE ROM16X1A - INSTANCE LUT4_142 - SUBMODULE ROM16X1A - INSTANCE LUT4_143 - SUBMODULE ROM16X1A - INSTANCE LUT4_144 - SUBMODULE ROM16X1A - INSTANCE LUT4_145 - SUBMODULE ROM16X1A - INSTANCE LUT4_146 - SUBMODULE ROM16X1A - INSTANCE LUT4_147 - SUBMODULE ROM16X1A - INSTANCE LUT4_148 - SUBMODULE ROM16X1A - INSTANCE LUT4_149 - SUBMODULE ROM16X1A - INSTANCE LUT4_150 - SUBMODULE ROM16X1A - INSTANCE LUT4_151 - SUBMODULE ROM16X1A - INSTANCE LUT4_152 - SUBMODULE ROM16X1A - INSTANCE LUT4_153 - SUBMODULE ROM16X1A - INSTANCE LUT4_154 - SUBMODULE ROM16X1A - INSTANCE LUT4_155 - SUBMODULE ROM16X1A - INSTANCE LUT4_156 - SUBMODULE ROM16X1A - INSTANCE LUT4_157 - SUBMODULE ROM16X1A - INSTANCE LUT4_158 - SUBMODULE ROM16X1A - INSTANCE LUT4_159 - SUBMODULE ROM16X1A - INSTANCE LUT4_160 - SUBMODULE ROM16X1A - INSTANCE LUT4_161 - SUBMODULE ROM16X1A - INSTANCE LUT4_162 - SUBMODULE ROM16X1A - INSTANCE LUT4_163 - SUBMODULE ROM16X1A - INSTANCE LUT4_164 - SUBMODULE ROM16X1A - INSTANCE LUT4_165 - SUBMODULE ROM16X1A - INSTANCE LUT4_166 - SUBMODULE ROM16X1A - INSTANCE LUT4_167 - SUBMODULE ROM16X1A - INSTANCE LUT4_168 - SUBMODULE ROM16X1A - INSTANCE LUT4_169 - SUBMODULE ROM16X1A - INSTANCE LUT4_170 - SUBMODULE ROM16X1A - INSTANCE LUT4_171 - SUBMODULE ROM16X1A - INSTANCE LUT4_172 - SUBMODULE ROM16X1A - INSTANCE LUT4_173 - SUBMODULE ROM16X1A - INSTANCE LUT4_174 - SUBMODULE ROM16X1A - INSTANCE LUT4_175 - SUBMODULE ROM16X1A - INSTANCE LUT4_176 - SUBMODULE ROM16X1A - INSTANCE LUT4_177 - SUBMODULE ROM16X1A - INSTANCE LUT4_178 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE INV - INSTANCE INV_2 - SUBMODULE INV - INSTANCE INV_3 - SUBMODULE INV - INSTANCE INV_4 - SUBMODULE INV - INSTANCE INV_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_179 - SUBMODULE ROM16X1A - INSTANCE LUT4_180 - SUBMODULE INV - INSTANCE INV_6 - SUBMODULE INV - INSTANCE INV_7 - SUBMODULE INV - INSTANCE INV_8 - SUBMODULE INV - INSTANCE INV_9 - SUBMODULE INV - INSTANCE INV_10 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE XOR2 - INSTANCE XOR2_t24 - SUBMODULE XOR2 - INSTANCE XOR2_t25 - SUBMODULE XOR2 - INSTANCE XOR2_t26 - SUBMODULE XOR2 - INSTANCE XOR2_t27 - SUBMODULE XOR2 - INSTANCE XOR2_t28 - SUBMODULE XOR2 - INSTANCE XOR2_t29 - SUBMODULE XOR2 - INSTANCE XOR2_t30 - SUBMODULE XOR2 - INSTANCE XOR2_t31 - SUBMODULE XOR2 - INSTANCE XOR2_t32 - SUBMODULE XOR2 - INSTANCE XOR2_t33 - SUBMODULE XOR2 - INSTANCE XOR2_t34 - SUBMODULE XOR2 - INSTANCE XOR2_t35 - SUBMODULE XOR2 - INSTANCE XOR2_t36 - SUBMODULE OR2 - INSTANCE OR2_t37 - SUBMODULE INV - INSTANCE INV_11 - SUBMODULE AND2 - INSTANCE AND2_t38 - SUBMODULE INV - INSTANCE INV_12 - SUBMODULE AND2 - INSTANCE AND2_t39 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.lpc deleted file mode 100644 index 4ac80c1..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_32kx16x8_mb2 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:22:54 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=18 -RDepth=65536 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=16 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=32752 -PfDeassert=506 -RDataCount=1 -WDataCount=1 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.naf b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.naf deleted file mode 100644 index 8de024d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.naf +++ /dev/null @@ -1,101 +0,0 @@ -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -AmEmptyThresh[15] i -AmEmptyThresh[14] i -AmEmptyThresh[13] i -AmEmptyThresh[12] i -AmEmptyThresh[11] i -AmEmptyThresh[10] i -AmEmptyThresh[9] i -AmEmptyThresh[8] i -AmEmptyThresh[7] i -AmEmptyThresh[6] i -AmEmptyThresh[5] i -AmEmptyThresh[4] i -AmEmptyThresh[3] i -AmEmptyThresh[2] i -AmEmptyThresh[1] i -AmEmptyThresh[0] i -AmFullThresh[14] i -AmFullThresh[13] i -AmFullThresh[12] i -AmFullThresh[11] i -AmFullThresh[10] i -AmFullThresh[9] i -AmFullThresh[8] i -AmFullThresh[7] i -AmFullThresh[6] i -AmFullThresh[5] i -AmFullThresh[4] i -AmFullThresh[3] i -AmFullThresh[2] i -AmFullThresh[1] i -AmFullThresh[0] i -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -WCNT[15] o -WCNT[14] o -WCNT[13] o -WCNT[12] o -WCNT[11] o -WCNT[10] o -WCNT[9] o -WCNT[8] o -WCNT[7] o -WCNT[6] o -WCNT[5] o -WCNT[4] o -WCNT[3] o -WCNT[2] o -WCNT[1] o -WCNT[0] o -RCNT[16] o -RCNT[15] o -RCNT[14] o -RCNT[13] o -RCNT[12] o -RCNT[11] o -RCNT[10] o -RCNT[9] o -RCNT[8] o -RCNT[7] o -RCNT[6] o -RCNT[5] o -RCNT[4] o -RCNT[3] o -RCNT[2] o -RCNT[1] o -RCNT[0] o -Empty o -Full o -AlmostEmpty o -AlmostFull o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.sort b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.sort deleted file mode 100644 index 52d8ef6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_32kx16x8_mb2.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.srp b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.srp deleted file mode 100644 index 2b6645f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.srp +++ /dev/null @@ -1,44 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:22:54 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb2 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb2.vhd - VHDL template : fifo_32kx16x8_mb2_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb2.srp - Element Usage : - AGEB2 : 34 - AND2 : 4 - CU2 : 17 - FADD2B : 12 - FSUB2B : 36 - FD1P3BX : 2 - FD1P3DX : 102 - FD1S3BX : 2 - FD1S3DX : 134 - INV : 13 - MUX321 : 9 - OR2 : 1 - ROM16X1A : 181 - XOR2 : 35 - DP16KC : 32 - Estimated Resource Usage: - LUT : 491 - EBR : 32 - Reg : 240 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.sym b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.sym deleted file mode 100644 index b538f5015a26437e48217190a6e5c43b1f6525f1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 716 zcmY+CKWGzi9L3-FF0B|H&OeBgWXK>+m#S?Lhr~8TL~INv8Pd{JlThhhb0iVsB0(IS zB!f7KWbEK@NCyXp;NavCI*LO^$Iz)mhrav%5+Q*f`P_T&_wM_n@Y1oj8Cu zaR>HIBDuEH*{Nh!)cHuKkN3toSE{Z0%@=z(pgO`Aqb5qV!aneW+63Q>wot0K>m3|X zbL7`-chRW-sD}7ERm&~Yc}g|H@wBttiaT!z?4m46di|QtfS*hpF;UipzK;Ks0aq_IUN)NBx0m+1ndNSFJ9xf?6X{7L z1*Ur9pdc45!Pw$_Jm+=gBDpAOWtZ%VtL%^+xo@3ke$2a%@lbi7lX%Kiauro_+@Ip| zm2>2rblDTXu@u)kWrEn, B=>invout_1, Z=>wren_i); - - INV_12: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t38: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_11: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t37: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t36: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t35: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t34: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t33: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t32: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t31: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t30: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t29: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t28: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t27: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t26: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t25: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t24: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t23: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t22: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t21: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t20: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t19: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t18: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t17: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t16: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t15: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t14: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t13: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t12: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t11: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t9: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t8: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t7: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t6: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - INV_10: INV - port map (A=>wptr_10, Z=>wptr_10_inv); - - INV_9: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_8: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_7: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_6: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - LUT4_180: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet); - - LUT4_179: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_p00); - - INV_5: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_4: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_3: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_2: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - INV_1: INV - port map (A=>rptr_15, Z=>rptr_15_inv); - - LUT4_178: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_1); - - LUT4_177: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec1_r10); - - LUT4_176: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_2); - - LUT4_175: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec2_p01); - - LUT4_174: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_3); - - LUT4_173: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec3_r11); - - LUT4_172: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_4); - - LUT4_171: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec4_p02); - - LUT4_170: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_5); - - LUT4_169: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec5_r12); - - LUT4_168: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_6); - - LUT4_167: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec6_p03); - - LUT4_166: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_7); - - LUT4_165: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec7_r13); - - LUT4_164: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_8); - - LUT4_163: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec8_p04); - - LUT4_162: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_9); - - LUT4_161: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec9_r14); - - LUT4_160: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_10); - - LUT4_159: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - - LUT4_158: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_11); - - LUT4_157: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - - LUT4_156: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_12); - - LUT4_155: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - - LUT4_154: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_13); - - LUT4_153: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - - LUT4_152: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_14); - - LUT4_151: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - - LUT4_150: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_15); - - LUT4_149: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - - LUT4_148: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_16); - - LUT4_147: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - - LUT4_146: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_17); - - LUT4_145: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - - LUT4_144: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_18); - - LUT4_143: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - - LUT4_142: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_19); - - LUT4_141: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - - LUT4_140: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_20); - - LUT4_139: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - - LUT4_138: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_21); - - LUT4_137: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - - LUT4_136: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_22); - - LUT4_135: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - - LUT4_134: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_23); - - LUT4_133: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - - LUT4_132: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_24); - - LUT4_131: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - - LUT4_130: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_25); - - LUT4_129: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - - LUT4_128: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_26); - - LUT4_127: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - - LUT4_126: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_27); - - LUT4_125: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - - LUT4_124: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_28); - - LUT4_123: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - - LUT4_122: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_29); - - LUT4_121: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - - LUT4_120: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_30); - - LUT4_119: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - - LUT4_118: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_31); - - LUT4_117: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - - LUT4_116: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_32); - - LUT4_115: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec32_p016); - - LUT4_114: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_33); - - LUT4_113: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec33_r116); - - LUT4_112: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_34); - - LUT4_111: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec34_p017); - - LUT4_110: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_35); - - LUT4_109: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec35_r117); - - LUT4_108: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_36); - - LUT4_107: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec36_p018); - - LUT4_106: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_37); - - LUT4_105: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec37_r118); - - LUT4_104: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_38); - - LUT4_103: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec38_p019); - - LUT4_102: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_39); - - LUT4_101: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec39_r119); - - LUT4_100: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_40); - - LUT4_99: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec40_p020); - - LUT4_98: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_41); - - LUT4_97: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec41_r120); - - LUT4_96: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_42); - - LUT4_95: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec42_p021); - - LUT4_94: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_43); - - LUT4_93: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec43_r121); - - LUT4_92: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_44); - - LUT4_91: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec44_p022); - - LUT4_90: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_45); - - LUT4_89: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec45_r122); - - LUT4_88: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_46); - - LUT4_87: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec46_p023); - - LUT4_86: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_47); - - LUT4_85: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec47_r123); - - LUT4_84: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_48); - - LUT4_83: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec48_p024); - - LUT4_82: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_49); - - LUT4_81: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec49_r124); - - LUT4_80: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_50); - - LUT4_79: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec50_p025); - - LUT4_78: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_51); - - LUT4_77: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec51_r125); - - LUT4_76: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_52); - - LUT4_75: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec52_p026); - - LUT4_74: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_53); - - LUT4_73: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec53_r126); - - LUT4_72: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_54); - - LUT4_71: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec54_p027); - - LUT4_70: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_55); - - LUT4_69: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec55_r127); - - LUT4_68: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_56); - - LUT4_67: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec56_p028); - - LUT4_66: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_57); - - LUT4_65: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec57_r128); - - LUT4_64: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_58); - - LUT4_63: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec58_p029); - - LUT4_62: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_59); - - LUT4_61: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec59_r129); - - LUT4_60: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_60); - - LUT4_59: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec60_p030); - - LUT4_58: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_61); - - LUT4_57: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec61_r130); - - LUT4_56: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_62); - - LUT4_55: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec62_p031); - - LUT4_54: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_63); - - LUT4_53: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec63_r131); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - XOR2_t5: XOR2 - port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); - - XOR2_t4: XOR2 - port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); - - XOR2_t3: XOR2 - port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - INV_0: INV - port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, - DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, - DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, - DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, - DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, - DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, - DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, - DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, - DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, - DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, - DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, - DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, - DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, - DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, - DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, - DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, - DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, - DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, - DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, - DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, - DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, - DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, - DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, - DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, - DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, - DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, - DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, - DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, - DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, - DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, - DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, - DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, - DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, - DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, - DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, - DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, - DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, - DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, - DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, - DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, - DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, - DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, - DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, - DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, - DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, - DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, - DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, - DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, - DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, - DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, - DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, - DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, - DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, - DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, - DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, - DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, - DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, - DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, - DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, - DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, - DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, - DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, - DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, - DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, - DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, - DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, - DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, - DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, - DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, - DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, - DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, - DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, - DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, - DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, - DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, - DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, - DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, - DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, - DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, - DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, - DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, - DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, - DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, - DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, - DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, - DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, - DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, - DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, - DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, - DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, - DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_239: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_238: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_237: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_236: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_235: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_234: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_233: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_232: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_231: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_230: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_229: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_228: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_227: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_226: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_225: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_224: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_223: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_222: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_221: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_220: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_219: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_218: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_217: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_216: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_215: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_214: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_213: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_212: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_211: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_210: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_209: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_208: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_207: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_206: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_205: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_204: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_203: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_202: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_201: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_200: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_199: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_198: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_197: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_196: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_195: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_194: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_193: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_192: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_191: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_190: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_189: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_188: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_187: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_186: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_185: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_184: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_183: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_182: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_181: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_180: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_179: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_178: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_177: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_176: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_175: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_174: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_173: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_172: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_171: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_170: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_169: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_168: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_167: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_166: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_165: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_164: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_163: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_162: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_161: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_160: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_159: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_158: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_157: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_156: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_155: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_154: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_153: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_152: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_151: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_150: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_149: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_148: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_147: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_146: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_145: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_144: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_143: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_142: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_141: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_140: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_139: FD1P3DX - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_138: FD1P3DX - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_137: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_136: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_135: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_134: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_133: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_132: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_131: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_130: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_129: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_128: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_127: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_126: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_125: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_124: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_123: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_122: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_121: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_120: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_119: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_118: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_117: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_116: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_115: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_114: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_113: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_112: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_111: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_110: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_109: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_108: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_107: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_106: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_105: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_104: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_103: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_102: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_101: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_100: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_99: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_98: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_97: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_96: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_95: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_94: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_93: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_92: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_91: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_90: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_89: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_88: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_87: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_86: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_85: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_84: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_83: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_82: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_81: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_80: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_79: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_78: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_77: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_76: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_75: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_74: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_73: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_72: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_71: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_70: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_69: FD1S3DX - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); - - FF_68: FD1S3DX - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); - - FF_67: FD1S3DX - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); - - FF_66: FD1S3DX - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); - - FF_65: FD1S3DX - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); - - FF_64: FD1S3DX - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); - - FF_63: FD1S3DX - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); - - FF_62: FD1S3DX - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); - - FF_61: FD1S3DX - port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); - - FF_60: FD1S3DX - port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); - - FF_59: FD1S3DX - port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); - - FF_58: FD1S3DX - port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); - - FF_57: FD1S3DX - port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); - - FF_56: FD1S3DX - port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); - - FF_55: FD1S3DX - port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); - - FF_54: FD1S3DX - port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); - - FF_53: FD1S3DX - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_52: FD1S3DX - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_51: FD1S3DX - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_50: FD1S3DX - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_49: FD1S3DX - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_48: FD1S3DX - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_47: FD1S3DX - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); - - FF_46: FD1S3DX - port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); - - FF_45: FD1S3DX - port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); - - FF_44: FD1S3DX - port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); - - FF_43: FD1S3DX - port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); - - FF_42: FD1S3DX - port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); - - FF_41: FD1S3DX - port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); - - FF_40: FD1S3DX - port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); - - FF_39: FD1S3DX - port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); - - FF_38: FD1S3DX - port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); - - FF_37: FD1S3DX - port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); - - FF_36: FD1S3DX - port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); - - FF_35: FD1S3DX - port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); - - FF_34: FD1S3DX - port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); - - FF_33: FD1S3DX - port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); - - FF_32: FD1S3DX - port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); - - FF_31: FD1S3DX - port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); - - FF_30: FD1S3DX - port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); - - FF_29: FD1S3DX - port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); - - FF_28: FD1S3DX - port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); - - FF_27: FD1S3DX - port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); - - FF_26: FD1S3DX - port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); - - FF_25: FD1S3DX - port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); - - FF_24: FD1S3DX - port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); - - FF_23: FD1S3DX - port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); - - FF_22: FD1S3DX - port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); - - FF_21: FD1S3DX - port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); - - FF_20: FD1S3DX - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); - - FF_19: FD1S3DX - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); - - FF_18: FD1S3DX - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); - - FF_17: FD1S3DX - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); - - FF_16: FD1S3DX - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); - - FF_15: FD1S3DX - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); - - FF_14: FD1S3DX - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); - - FF_13: FD1S3DX - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); - - FF_12: FD1S3DX - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); - - FF_11: FD1S3DX - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); - - FF_10: FD1S3DX - port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); - - FF_9: FD1S3DX - port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); - - FF_8: FD1S3DX - port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); - - FF_7: FD1S3DX - port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); - - FF_6: FD1S3DX - port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); - - FF_5: FD1S3DX - port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); - - FF_4: FD1S3DX - port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); - - FF_3: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_2: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_1: FD1S3BX - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_0: FD1S3DX - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>ircount_16, NC1=>open); - - mux_8: MUX321 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, - D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, - D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, - D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, - D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, - D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(0)); - - mux_7: MUX321 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, - D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, - D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, - D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, - D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, - D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(1)); - - mux_6: MUX321 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, - D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, - D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, - D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, - D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, - D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(2)); - - mux_5: MUX321 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, - D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, - D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, - D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, - D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, - D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(3)); - - mux_4: MUX321 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, - D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, - D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, - D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, - D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, - D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(4)); - - mux_3: MUX321 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, - D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, - D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, - D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, - D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, - D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(5)); - - mux_2: MUX321 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, - D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, - D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, - D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, - D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, - D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(6)); - - mux_1: MUX321 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, - D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, - D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, - D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, - D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, - D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(7)); - - mux_0: MUX321 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, - D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, - D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, - D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, - D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, - D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(8)); - - wcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, - S1=>wcnt_sub_0); - - wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, - B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, - S1=>wcnt_sub_2); - - wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, - B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, - S1=>wcnt_sub_4); - - wcnt_3: FSUB2B - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, - B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, - S1=>wcnt_sub_6); - - wcnt_4: FSUB2B - port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, - B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, - S1=>wcnt_sub_8); - - wcnt_5: FSUB2B - port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, - S1=>wcnt_sub_10); - - wcnt_6: FSUB2B - port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, - S0=>wcnt_sub_11, S1=>wcnt_sub_12); - - wcnt_7: FSUB2B - port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, - S1=>wcnt_sub_14); - - wcnt_8: FSUB2B - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, - S1=>open); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, - B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, - B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, - B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcnt_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, - B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, - S1=>rcnt_sub_8); - - rcnt_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, - B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, - S1=>rcnt_sub_10); - - rcnt_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, - B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, - S1=>rcnt_sub_12); - - rcnt_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, - B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, - S1=>rcnt_sub_14); - - rcnt_8: FSUB2B - port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, - B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, - S1=>rcnt_sub_16); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); - - wfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, - S1=>wfill_sub_0); - - wfill_1: FSUB2B - port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, - BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); - - wfill_2: FSUB2B - port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, - BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); - - wfill_3: FSUB2B - port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, - BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); - - wfill_4: FSUB2B - port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, - BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); - - wfill_5: FSUB2B - port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, - S1=>wfill_sub_10); - - wfill_6: FSUB2B - port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, - S0=>wfill_sub_11, S1=>wfill_sub_12); - - wfill_7: FSUB2B - port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, - S1=>wfill_sub_14); - - wfill_8: FSUB2B - port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, - S1=>rfill_sub_0); - - rfill_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, - BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); - - rfill_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, - BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); - - rfill_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, - BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); - - rfill_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, - BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); - - rfill_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, - BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); - - rfill_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, - B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, - S1=>rfill_sub_12); - - rfill_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, - B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, - S1=>rfill_sub_14); - - rfill_8: FSUB2B - port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, - B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, - S1=>rfill_sub_16); - - rfilld: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_6, GE=>co1_6); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_6, GE=>co2_6); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_6, GE=>co3_6); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>wcount_r8, CI=>co3_6, GE=>co4_6); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_6, GE=>co5_6); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, - B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, - B1=>wcount_r14, CI=>co6_6, GE=>co7_6); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_7, GE=>co1_7); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_7, GE=>co2_7); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_7, GE=>co3_7); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_7, GE=>co4_7); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, - B1=>rcount_w12, CI=>co4_7, GE=>co5_7); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w14, CI=>co5_7, GE=>co6_7); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, - B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); - - ae_cmp_3: AGEB2 - port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), - B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); - - ae_cmp_4: AGEB2 - port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), - B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); - - ae_cmp_5: AGEB2 - port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), - B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); - - ae_cmp_6: AGEB2 - port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), - B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); - - ae_cmp_7: AGEB2 - port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), - B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); - - ae_cmp_8: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - - af_d_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_d_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); - - af_d_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); - - af_d_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); - - af_d_cmp_3: AGEB2 - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); - - af_d_cmp_4: AGEB2 - port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), - B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); - - af_d_cmp_5: AGEB2 - port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), - B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); - - af_d_cmp_6: AGEB2 - port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), - B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); - - af_d_cmp_7: AGEB2 - port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), - B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_32kx16x8_mb2 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX321 use entity ecp3.MUX321(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2_generate.log deleted file mode 100644 index eceede3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:22:54 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb2 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb2.vhd - VHDL template : fifo_32kx16x8_mb2_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb2.srp - Estimated Resource Usage: - LUT : 491 - EBR : 32 - Reg : 240 - -END SCUBA Module Synthesis - -File: fifo_32kx16x8_mb2.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2_tmpl.vhd deleted file mode 100644 index 041890c..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2_tmpl.vhd +++ /dev/null @@ -1,26 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:22:54 2011 - --- parameterized module component declaration -component fifo_32kx16x8_mb2 - port (Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(8 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_32kx16x8_mb2 - port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__, - AmFullThresh(14 downto 0)=>__, Q(8 downto 0)=>__, WCNT(15 downto 0)=>__, - RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__, - AlmostFull=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb_generate.log deleted file mode 100755 index 232d7cc..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:22:35 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 16 -num_words 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e - Circuit name : fifo_32kx16x8_mb - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[15:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[7:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_32kx16x8_mb.vhd - VHDL template : fifo_32kx16x8_mb_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb.srp - Estimated Resource Usage: - LUT : 299 - EBR : 32 - Reg : 237 - -END SCUBA Module Synthesis - -File: fifo_32kx16x8_mb.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb_tmpl.vhd deleted file mode 100755 index a84a110..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb_tmpl.vhd +++ /dev/null @@ -1,26 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:22:35 2011 - --- parameterized module component declaration -component fifo_32kx16x8_mb - port (Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(7 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_32kx16x8_mb - port map (Data(15 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__, - AmFullThresh(14 downto 0)=>__, Q(7 downto 0)=>__, WCNT(15 downto 0)=>__, - RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__, - AlmostFull=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd deleted file mode 100644 index cdfbc7a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd +++ /dev/null @@ -1,3400 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) --- Module Version: 5.5 ---/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx9_flags -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 9 -depth 32768 -rdata_width 9 -no_enable -pe -1 -pf 30000 -pf2 29990 -e - --- Wed Nov 6 19:54:22 2013 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_32kx9_flags is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostFull: out std_logic); -end fifo_32kx9_flags; - -architecture Structure of fifo_32kx9_flags is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal wptr_14_inv: std_logic; - signal rptr_14_inv: std_logic; - signal wptr_13_inv: std_logic; - signal rptr_13_inv: std_logic; - signal wptr_12_inv: std_logic; - signal rptr_12_inv: std_logic; - signal wptr_11_inv: std_logic; - signal rptr_11_inv: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal dec1_r10: std_logic; - signal dec0_p00: std_logic; - signal dec3_r11: std_logic; - signal dec2_p01: std_logic; - signal dec5_r12: std_logic; - signal dec4_p02: std_logic; - signal dec7_r13: std_logic; - signal dec6_p03: std_logic; - signal dec9_r14: std_logic; - signal dec8_p04: std_logic; - signal dec11_r15: std_logic; - signal dec10_p05: std_logic; - signal dec13_r16: std_logic; - signal dec12_p06: std_logic; - signal dec15_r17: std_logic; - signal dec14_p07: std_logic; - signal dec17_r18: std_logic; - signal dec16_p08: std_logic; - signal dec19_r19: std_logic; - signal dec18_p09: std_logic; - signal dec21_r110: std_logic; - signal dec20_p010: std_logic; - signal dec23_r111: std_logic; - signal dec22_p011: std_logic; - signal dec25_r112: std_logic; - signal dec24_p012: std_logic; - signal dec27_r113: std_logic; - signal dec26_p013: std_logic; - signal dec29_r114: std_logic; - signal dec28_p014: std_logic; - signal dec31_r115: std_logic; - signal dec30_p015: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wptr_15: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_15: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal af: std_logic; - signal af_d: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co7: std_logic; - signal co6: std_logic; - signal wcount_15: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co7_1: std_logic; - signal co6_1: std_logic; - signal rcount_15: std_logic; - signal mdout1_15_0: std_logic; - signal mdout1_14_0: std_logic; - signal mdout1_13_0: std_logic; - signal mdout1_12_0: std_logic; - signal mdout1_11_0: std_logic; - signal mdout1_10_0: std_logic; - signal mdout1_9_0: std_logic; - signal mdout1_8_0: std_logic; - signal mdout1_7_0: std_logic; - signal mdout1_6_0: std_logic; - signal mdout1_5_0: std_logic; - signal mdout1_4_0: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_15_1: std_logic; - signal mdout1_14_1: std_logic; - signal mdout1_13_1: std_logic; - signal mdout1_12_1: std_logic; - signal mdout1_11_1: std_logic; - signal mdout1_10_1: std_logic; - signal mdout1_9_1: std_logic; - signal mdout1_8_1: std_logic; - signal mdout1_7_1: std_logic; - signal mdout1_6_1: std_logic; - signal mdout1_5_1: std_logic; - signal mdout1_4_1: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_15_2: std_logic; - signal mdout1_14_2: std_logic; - signal mdout1_13_2: std_logic; - signal mdout1_12_2: std_logic; - signal mdout1_11_2: std_logic; - signal mdout1_10_2: std_logic; - signal mdout1_9_2: std_logic; - signal mdout1_8_2: std_logic; - signal mdout1_7_2: std_logic; - signal mdout1_6_2: std_logic; - signal mdout1_5_2: std_logic; - signal mdout1_4_2: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_15_3: std_logic; - signal mdout1_14_3: std_logic; - signal mdout1_13_3: std_logic; - signal mdout1_12_3: std_logic; - signal mdout1_11_3: std_logic; - signal mdout1_10_3: std_logic; - signal mdout1_9_3: std_logic; - signal mdout1_8_3: std_logic; - signal mdout1_7_3: std_logic; - signal mdout1_6_3: std_logic; - signal mdout1_5_3: std_logic; - signal mdout1_4_3: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_15_4: std_logic; - signal mdout1_14_4: std_logic; - signal mdout1_13_4: std_logic; - signal mdout1_12_4: std_logic; - signal mdout1_11_4: std_logic; - signal mdout1_10_4: std_logic; - signal mdout1_9_4: std_logic; - signal mdout1_8_4: std_logic; - signal mdout1_7_4: std_logic; - signal mdout1_6_4: std_logic; - signal mdout1_5_4: std_logic; - signal mdout1_4_4: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_15_5: std_logic; - signal mdout1_14_5: std_logic; - signal mdout1_13_5: std_logic; - signal mdout1_12_5: std_logic; - signal mdout1_11_5: std_logic; - signal mdout1_10_5: std_logic; - signal mdout1_9_5: std_logic; - signal mdout1_8_5: std_logic; - signal mdout1_7_5: std_logic; - signal mdout1_6_5: std_logic; - signal mdout1_5_5: std_logic; - signal mdout1_4_5: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_15_6: std_logic; - signal mdout1_14_6: std_logic; - signal mdout1_13_6: std_logic; - signal mdout1_12_6: std_logic; - signal mdout1_11_6: std_logic; - signal mdout1_10_6: std_logic; - signal mdout1_9_6: std_logic; - signal mdout1_8_6: std_logic; - signal mdout1_7_6: std_logic; - signal mdout1_6_6: std_logic; - signal mdout1_5_6: std_logic; - signal mdout1_4_6: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_15_7: std_logic; - signal mdout1_14_7: std_logic; - signal mdout1_13_7: std_logic; - signal mdout1_12_7: std_logic; - signal mdout1_11_7: std_logic; - signal mdout1_10_7: std_logic; - signal mdout1_9_7: std_logic; - signal mdout1_8_7: std_logic; - signal mdout1_7_7: std_logic; - signal mdout1_6_7: std_logic; - signal mdout1_5_7: std_logic; - signal mdout1_4_7: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_14_ff: std_logic; - signal rptr_13_ff: std_logic; - signal rptr_12_ff: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_15_8: std_logic; - signal mdout1_14_8: std_logic; - signal mdout1_13_8: std_logic; - signal mdout1_12_8: std_logic; - signal mdout1_11_8: std_logic; - signal mdout1_10_8: std_logic; - signal mdout1_9_8: std_logic; - signal mdout1_8_8: std_logic; - signal mdout1_7_8: std_logic; - signal mdout1_6_8: std_logic; - signal mdout1_5_8: std_logic; - signal mdout1_4_8: std_logic; - signal mdout1_3_8: std_logic; - signal mdout1_2_8: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r13: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal wcount_r14: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_14: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal cmp_ci_1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_14: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal iaf_setcount_0: std_logic; - signal iaf_setcount_1: std_logic; - signal af_set_ctr_ci: std_logic; - signal iaf_setcount_2: std_logic; - signal iaf_setcount_3: std_logic; - signal co0_4: std_logic; - signal iaf_setcount_4: std_logic; - signal iaf_setcount_5: std_logic; - signal co1_4: std_logic; - signal iaf_setcount_6: std_logic; - signal iaf_setcount_7: std_logic; - signal co2_4: std_logic; - signal iaf_setcount_8: std_logic; - signal iaf_setcount_9: std_logic; - signal co3_4: std_logic; - signal iaf_setcount_10: std_logic; - signal iaf_setcount_11: std_logic; - signal co4_4: std_logic; - signal iaf_setcount_12: std_logic; - signal iaf_setcount_13: std_logic; - signal co5_4: std_logic; - signal iaf_setcount_14: std_logic; - signal iaf_setcount_15: std_logic; - signal co7_2: std_logic; - signal co6_4: std_logic; - signal af_setcount_15: std_logic; - signal cmp_ci_2: std_logic; - signal af_setcount_0: std_logic; - signal af_setcount_1: std_logic; - signal co0_5: std_logic; - signal af_setcount_2: std_logic; - signal af_setcount_3: std_logic; - signal co1_5: std_logic; - signal af_setcount_4: std_logic; - signal af_setcount_5: std_logic; - signal co2_5: std_logic; - signal af_setcount_6: std_logic; - signal af_setcount_7: std_logic; - signal co3_5: std_logic; - signal af_setcount_8: std_logic; - signal af_setcount_9: std_logic; - signal co4_5: std_logic; - signal af_setcount_10: std_logic; - signal af_setcount_11: std_logic; - signal co5_5: std_logic; - signal af_setcount_12: std_logic; - signal af_setcount_13: std_logic; - signal co6_5: std_logic; - signal af_set_cmp_clr: std_logic; - signal af_setcount_14: std_logic; - signal af_set_cmp_set: std_logic; - signal af_set: std_logic; - signal af_set_c: std_logic; - signal scuba_vhi: std_logic; - signal iaf_clrcount_0: std_logic; - signal iaf_clrcount_1: std_logic; - signal af_clr_ctr_ci: std_logic; - signal iaf_clrcount_2: std_logic; - signal iaf_clrcount_3: std_logic; - signal co0_6: std_logic; - signal iaf_clrcount_4: std_logic; - signal iaf_clrcount_5: std_logic; - signal co1_6: std_logic; - signal iaf_clrcount_6: std_logic; - signal iaf_clrcount_7: std_logic; - signal co2_6: std_logic; - signal iaf_clrcount_8: std_logic; - signal iaf_clrcount_9: std_logic; - signal co3_6: std_logic; - signal iaf_clrcount_10: std_logic; - signal iaf_clrcount_11: std_logic; - signal co4_6: std_logic; - signal iaf_clrcount_12: std_logic; - signal iaf_clrcount_13: std_logic; - signal co5_6: std_logic; - signal iaf_clrcount_14: std_logic; - signal iaf_clrcount_15: std_logic; - signal co7_3: std_logic; - signal co6_6: std_logic; - signal af_clrcount_15: std_logic; - signal wren_i: std_logic; - signal cmp_ci_3: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal af_clrcount_0: std_logic; - signal af_clrcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal af_clrcount_2: std_logic; - signal af_clrcount_3: std_logic; - signal co1_7: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal af_clrcount_4: std_logic; - signal af_clrcount_5: std_logic; - signal co2_7: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal af_clrcount_6: std_logic; - signal af_clrcount_7: std_logic; - signal co3_7: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal af_clrcount_8: std_logic; - signal af_clrcount_9: std_logic; - signal co4_7: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal af_clrcount_10: std_logic; - signal af_clrcount_11: std_logic; - signal co5_7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w13: std_logic; - signal af_clrcount_12: std_logic; - signal af_clrcount_13: std_logic; - signal co6_7: std_logic; - signal rcount_w14: std_logic; - signal af_clr_cmp_clr: std_logic; - signal af_clrcount_14: std_logic; - signal af_clr_cmp_set: std_logic; - signal af_clr: std_logic; - signal af_clr_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX161 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; D4: in std_logic; D5: in std_logic; - D6: in std_logic; D7: in std_logic; D8: in std_logic; - D9: in std_logic; D10: in std_logic; D11: in std_logic; - D12: in std_logic; D13: in std_logic; D14: in std_logic; - D15: in std_logic; SD1: in std_logic; SD2: in std_logic; - SD3: in std_logic; SD4: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is ""; - attribute RESETMODE of pdp_ram_0_0_15 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_14 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_14 : label is ""; - attribute RESETMODE of pdp_ram_1_0_14 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_0_13 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_13 : label is ""; - attribute RESETMODE of pdp_ram_2_0_13 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_0_12 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_12 : label is ""; - attribute RESETMODE of pdp_ram_3_0_12 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_4_0_11 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_4_0_11 : label is ""; - attribute RESETMODE of pdp_ram_4_0_11 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_5_0_10 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_5_0_10 : label is ""; - attribute RESETMODE of pdp_ram_5_0_10 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_6_0_9 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_6_0_9 : label is ""; - attribute RESETMODE of pdp_ram_6_0_9 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_7_0_8 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_7_0_8 : label is ""; - attribute RESETMODE of pdp_ram_7_0_8 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_8_0_7 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_8_0_7 : label is ""; - attribute RESETMODE of pdp_ram_8_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_9_0_6 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_9_0_6 : label is ""; - attribute RESETMODE of pdp_ram_9_0_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_10_0_5 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_10_0_5 : label is ""; - attribute RESETMODE of pdp_ram_10_0_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_11_0_4 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_11_0_4 : label is ""; - attribute RESETMODE of pdp_ram_11_0_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_12_0_3 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_12_0_3 : label is ""; - attribute RESETMODE of pdp_ram_12_0_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_13_0_2 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_13_0_2 : label is ""; - attribute RESETMODE of pdp_ram_13_0_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_14_0_1 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_14_0_1 : label is ""; - attribute RESETMODE of pdp_ram_14_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_15_0_0 : label is "fifo_32kx9_flags.lpc"; - attribute MEM_INIT_FILE of pdp_ram_15_0_0 : label is ""; - attribute RESETMODE of pdp_ram_15_0_0 : label is "SYNC"; - attribute GSR of FF_198 : label is "ENABLED"; - attribute GSR of FF_197 : label is "ENABLED"; - attribute GSR of FF_196 : label is "ENABLED"; - attribute GSR of FF_195 : label is "ENABLED"; - attribute GSR of FF_194 : label is "ENABLED"; - attribute GSR of FF_193 : label is "ENABLED"; - attribute GSR of FF_192 : label is "ENABLED"; - attribute GSR of FF_191 : label is "ENABLED"; - attribute GSR of FF_190 : label is "ENABLED"; - attribute GSR of FF_189 : label is "ENABLED"; - attribute GSR of FF_188 : label is "ENABLED"; - attribute GSR of FF_187 : label is "ENABLED"; - attribute GSR of FF_186 : label is "ENABLED"; - attribute GSR of FF_185 : label is "ENABLED"; - attribute GSR of FF_184 : label is "ENABLED"; - attribute GSR of FF_183 : label is "ENABLED"; - attribute GSR of FF_182 : label is "ENABLED"; - attribute GSR of FF_181 : label is "ENABLED"; - attribute GSR of FF_180 : label is "ENABLED"; - attribute GSR of FF_179 : label is "ENABLED"; - attribute GSR of FF_178 : label is "ENABLED"; - attribute GSR of FF_177 : label is "ENABLED"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t32: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_9: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t31: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_8: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t30: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t29: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t28: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t27: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t26: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t25: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t24: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t23: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t22: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t21: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t20: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t19: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t18: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t17: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t16: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t15: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t14: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t13: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t12: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t11: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t10: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t9: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t8: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t7: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t6: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t5: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t4: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t3: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t2: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t1: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t0: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - INV_7: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_6: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_5: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_4: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - LUT4_82: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>dec0_p00); - - INV_3: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_2: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_1: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_0: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - LUT4_81: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>dec1_r10); - - LUT4_80: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>dec2_p01); - - LUT4_79: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>dec3_r11); - - LUT4_78: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>dec4_p02); - - LUT4_77: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>dec5_r12); - - LUT4_76: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>dec6_p03); - - LUT4_75: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>dec7_r13); - - LUT4_74: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>dec8_p04); - - LUT4_73: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>dec9_r14); - - LUT4_72: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>dec10_p05); - - LUT4_71: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>dec11_r15); - - LUT4_70: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>dec12_p06); - - LUT4_69: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>dec13_r16); - - LUT4_68: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>dec14_p07); - - LUT4_67: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>dec15_r17); - - LUT4_66: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>dec16_p08); - - LUT4_65: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>dec17_r18); - - LUT4_64: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>dec18_p09); - - LUT4_63: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>dec19_r19); - - LUT4_62: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>dec20_p010); - - LUT4_61: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>dec21_r110); - - LUT4_60: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>dec22_p011); - - LUT4_59: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>dec23_r111); - - LUT4_58: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>dec24_p012); - - LUT4_57: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>dec25_r112); - - LUT4_56: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>dec26_p013); - - LUT4_55: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>dec27_r113); - - LUT4_54: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14, DO0=>dec28_p014); - - LUT4_53: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>dec29_r114); - - LUT4_52: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, - DO0=>dec30_p015); - - LUT4_51: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>dec31_r115); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, - DO0=>r_g2b_xor_cluster_0); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_1); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_2); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_3); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>scuba_vlo, DO0=>rcount_w13); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w9); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w23, DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w1); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w0); - - LUT4_8: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_7: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_15, AD2=>rcount_15, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_6: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_5: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w215, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - LUT4_4: ROM16X1A - generic map (initval=> X"4c32") - port map (AD3=>af_setcount_15, AD2=>wcount_15, - AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_set); - - LUT4_3: ROM16X1A - generic map (initval=> X"8001") - port map (AD3=>af_setcount_15, AD2=>wcount_15, - AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_set_cmp_clr); - - LUT4_2: ROM16X1A - generic map (initval=> X"4c32") - port map (AD3=>af_clrcount_15, AD2=>wcount_15, - AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_set); - - LUT4_1: ROM16X1A - generic map (initval=> X"8001") - port map (AD3=>af_clrcount_15, AD2=>wcount_15, - AD1=>r_gcount_w215, AD0=>wptr_15, DO0=>af_clr_cmp_clr); - - LUT4_0: ROM16X1A - generic map (initval=> X"4450") - port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo, - DO0=>af_d); - - pdp_ram_0_0_15: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_14: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_13: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, - DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, - DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, - DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_12: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, - DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, - DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, - DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_4_0_11: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, - DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, - DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, - DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_5_0_10: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, - DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, - DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, - DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_6_0_9: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, - DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, - DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, - DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_7_0_8: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, - DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, - DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, - DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_8_0_7: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, - DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, - DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, - DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_9_0_6: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, - DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, - DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, - DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_10_0_5: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, - DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, - DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, - DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_11_0_4: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, - DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, - DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, - DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_12_0_3: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, - DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, - DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, - DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_13_0_2: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, - DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, - DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, - DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_14_0_1: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, - DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, - DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, - DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_15_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, - DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, - DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, - DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_198: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_197: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_196: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_195: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_194: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_193: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_192: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_191: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_190: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_189: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_188: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_187: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_186: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_185: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_184: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_183: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_182: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_181: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_180: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_179: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_178: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_177: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_176: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_175: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_174: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_173: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_172: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_171: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_170: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_169: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_168: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_167: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_166: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_165: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_164: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_163: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_162: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_161: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_160: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_159: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_158: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_157: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_156: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_155: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_154: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_153: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_152: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_151: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_150: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_149: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_148: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_147: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_146: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_145: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_144: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_143: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_142: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_141: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_140: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_139: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_138: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_137: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_136: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_135: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_134: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_133: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_132: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_131: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_130: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_129: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_128: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_127: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_126: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_125: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_124: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_123: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_122: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_121: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_120: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_119: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_118: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_117: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_116: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_115: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_114: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_113: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_112: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_111: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_110: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_109: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_108: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_107: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_106: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_105: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_104: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_103: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_102: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_101: FD1P3DX - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_100: FD1P3DX - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_99: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_98: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_97: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_96: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_95: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_94: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_93: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_92: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_91: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_90: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_89: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_88: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_87: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_86: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_85: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_84: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_83: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_82: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_81: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_80: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_79: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_78: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_77: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_76: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_75: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_74: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_73: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_72: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_71: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_70: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_69: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_68: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_67: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_66: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_65: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_64: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_63: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_62: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_61: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_60: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_59: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_58: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_57: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_56: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_55: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_54: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_53: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_52: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_51: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_50: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_49: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_48: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_47: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_46: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_45: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_44: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_43: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_42: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_41: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_40: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_39: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_38: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_37: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_36: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_35: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_34: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_33: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_32: FD1P3BX - port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_0); - - FF_31: FD1P3DX - port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_1); - - FF_30: FD1P3DX - port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_2); - - FF_29: FD1P3DX - port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_3); - - FF_28: FD1P3BX - port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_4); - - FF_27: FD1P3DX - port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_5); - - FF_26: FD1P3BX - port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_6); - - FF_25: FD1P3BX - port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_7); - - FF_24: FD1P3DX - port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_8); - - FF_23: FD1P3BX - port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_9); - - FF_22: FD1P3DX - port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_10); - - FF_21: FD1P3BX - port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_11); - - FF_20: FD1P3DX - port map (D=>iaf_setcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_12); - - FF_19: FD1P3DX - port map (D=>iaf_setcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_13); - - FF_18: FD1P3DX - port map (D=>iaf_setcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_14); - - FF_17: FD1P3DX - port map (D=>iaf_setcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_15); - - FF_16: FD1P3BX - port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_0); - - FF_15: FD1P3BX - port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_1); - - FF_14: FD1P3DX - port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_2); - - FF_13: FD1P3BX - port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_3); - - FF_12: FD1P3BX - port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_4); - - FF_11: FD1P3DX - port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_5); - - FF_10: FD1P3BX - port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_6); - - FF_9: FD1P3BX - port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_7); - - FF_8: FD1P3DX - port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_8); - - FF_7: FD1P3BX - port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_9); - - FF_6: FD1P3DX - port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_10); - - FF_5: FD1P3BX - port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_clrcount_11); - - FF_4: FD1P3DX - port map (D=>iaf_clrcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_12); - - FF_3: FD1P3DX - port map (D=>iaf_clrcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_13); - - FF_2: FD1P3DX - port map (D=>iaf_clrcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_14); - - FF_1: FD1P3DX - port map (D=>iaf_clrcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_clrcount_15); - - FF_0: FD1S3DX - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - mux_8: MUX161 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(0)); - - mux_7: MUX161 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(1)); - - mux_6: MUX161 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(2)); - - mux_5: MUX161 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(3)); - - mux_4: MUX161 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(4)); - - mux_3: MUX161 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(5)); - - mux_2: MUX161 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(6)); - - mux_1: MUX161 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(7)); - - mux_0: MUX161 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, SD1=>rptr_11_ff, SD2=>rptr_12_ff, - SD3=>rptr_13_ff, SD4=>rptr_14_ff, Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r13, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>empty_cmp_set, B0=>wcount_r14, - B1=>empty_cmp_clr, CI=>co6_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w13, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w14, - B1=>full_cmp_clr, CI=>co6_3, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - af_set_ctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, - S1=>open); - - af_set_ctr_0: CU2 - port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, - PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, - NC1=>iaf_setcount_1); - - af_set_ctr_1: CU2 - port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, - CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); - - af_set_ctr_2: CU2 - port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, - CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); - - af_set_ctr_3: CU2 - port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7, - CO=>co3_4, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); - - af_set_ctr_4: CU2 - port map (CI=>co3_4, PC0=>af_setcount_8, PC1=>af_setcount_9, - CO=>co4_4, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9); - - af_set_ctr_5: CU2 - port map (CI=>co4_4, PC0=>af_setcount_10, PC1=>af_setcount_11, - CO=>co5_4, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11); - - af_set_ctr_6: CU2 - port map (CI=>co5_4, PC0=>af_setcount_12, PC1=>af_setcount_13, - CO=>co6_4, NC0=>iaf_setcount_12, NC1=>iaf_setcount_13); - - af_set_ctr_7: CU2 - port map (CI=>co6_4, PC0=>af_setcount_14, PC1=>af_setcount_15, - CO=>co7_2, NC0=>iaf_setcount_14, NC1=>iaf_setcount_15); - - af_set_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - af_set_cmp_0: AGEB2 - port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5); - - af_set_cmp_1: AGEB2 - port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_5, GE=>co1_5); - - af_set_cmp_2: AGEB2 - port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_5, GE=>co2_5); - - af_set_cmp_3: AGEB2 - port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_5, GE=>co3_5); - - af_set_cmp_4: AGEB2 - port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_5, GE=>co4_5); - - af_set_cmp_5: AGEB2 - port map (A0=>af_setcount_10, A1=>af_setcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_5, GE=>co5_5); - - af_set_cmp_6: AGEB2 - port map (A0=>af_setcount_12, A1=>af_setcount_13, - B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_5, - GE=>co6_5); - - af_set_cmp_7: AGEB2 - port map (A0=>af_setcount_14, A1=>af_set_cmp_set, B0=>rcount_w14, - B1=>af_set_cmp_clr, CI=>co6_5, GE=>af_set_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - af_clr_ctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open, - S1=>open); - - af_clr_ctr_0: CU2 - port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0, - PC1=>af_clrcount_1, CO=>co0_6, NC0=>iaf_clrcount_0, - NC1=>iaf_clrcount_1); - - af_clr_ctr_1: CU2 - port map (CI=>co0_6, PC0=>af_clrcount_2, PC1=>af_clrcount_3, - CO=>co1_6, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3); - - af_clr_ctr_2: CU2 - port map (CI=>co1_6, PC0=>af_clrcount_4, PC1=>af_clrcount_5, - CO=>co2_6, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5); - - af_clr_ctr_3: CU2 - port map (CI=>co2_6, PC0=>af_clrcount_6, PC1=>af_clrcount_7, - CO=>co3_6, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7); - - af_clr_ctr_4: CU2 - port map (CI=>co3_6, PC0=>af_clrcount_8, PC1=>af_clrcount_9, - CO=>co4_6, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9); - - af_clr_ctr_5: CU2 - port map (CI=>co4_6, PC0=>af_clrcount_10, PC1=>af_clrcount_11, - CO=>co5_6, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11); - - af_clr_ctr_6: CU2 - port map (CI=>co5_6, PC0=>af_clrcount_12, PC1=>af_clrcount_13, - CO=>co6_6, NC0=>iaf_clrcount_12, NC1=>iaf_clrcount_13); - - af_clr_ctr_7: CU2 - port map (CI=>co6_6, PC0=>af_clrcount_14, PC1=>af_clrcount_15, - CO=>co7_3, NC0=>iaf_clrcount_14, NC1=>iaf_clrcount_15); - - af_clr_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_clr_cmp_0: AGEB2 - port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7); - - af_clr_cmp_1: AGEB2 - port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_7, GE=>co1_7); - - af_clr_cmp_2: AGEB2 - port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_7, GE=>co2_7); - - af_clr_cmp_3: AGEB2 - port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_7, GE=>co3_7); - - af_clr_cmp_4: AGEB2 - port map (A0=>af_clrcount_8, A1=>af_clrcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_7, GE=>co4_7); - - af_clr_cmp_5: AGEB2 - port map (A0=>af_clrcount_10, A1=>af_clrcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_7, GE=>co5_7); - - af_clr_cmp_6: AGEB2 - port map (A0=>af_clrcount_12, A1=>af_clrcount_13, - B0=>r_g2b_xor_cluster_0, B1=>rcount_w13, CI=>co5_7, - GE=>co6_7); - - af_clr_cmp_7: AGEB2 - port map (A0=>af_clrcount_14, A1=>af_clr_cmp_set, B0=>rcount_w14, - B1=>af_clr_cmp_clr, CI=>co6_7, GE=>af_clr_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr, - S1=>open); - - Empty <= empty_i; - Full <= full_i; - AlmostFull <= af; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_32kx9_flags is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX161 use entity ecp3.MUX161(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.ipx deleted file mode 100644 index d91ae3d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.jhd deleted file mode 100755 index 5e39ddf..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.jhd +++ /dev/null @@ -1,479 +0,0 @@ -MODULE fifo_4096x32 DEFIN fifo_4096x32.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3BX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3DX - INSTANCE FF_121 - SUBMODULE FD1P3DX - INSTANCE FF_122 - SUBMODULE FD1P3DX - INSTANCE FF_123 - SUBMODULE FD1P3DX - INSTANCE FF_124 - SUBMODULE FD1P3DX - INSTANCE FF_125 - SUBMODULE FD1P3DX - INSTANCE FF_126 - SUBMODULE FD1P3DX - INSTANCE FF_127 - SUBMODULE FD1P3DX - INSTANCE FF_128 - SUBMODULE FD1P3DX - INSTANCE FF_129 - SUBMODULE FD1P3DX - INSTANCE FF_130 - SUBMODULE FD1P3BX - INSTANCE FF_131 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_7_0 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_6_1 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_5_2 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_4_3 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_3_4 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_2_5 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_1_6 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE ROM16X1A - INSTANCE LUT4_30 - SUBMODULE ROM16X1A - INSTANCE LUT4_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_32 - SUBMODULE ROM16X1A - INSTANCE LUT4_33 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE OR2 - INSTANCE OR2_t24 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t25 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t26 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.lpc deleted file mode 100755 index 39ae0d7..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_4096x32 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:15 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=32 -RDepth=4096 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.naf b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.naf deleted file mode 100755 index 4603fbd..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.naf +++ /dev/null @@ -1,72 +0,0 @@ -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[31] o -Q[30] o -Q[29] o -Q[28] o -Q[27] o -Q[26] o -Q[25] o -Q[24] o -Q[23] o -Q[22] o -Q[21] o -Q[20] o -Q[19] o -Q[18] o -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.sort b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.sort deleted file mode 100644 index 90a33fa..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_4096x32.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.srp b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.srp deleted file mode 100755 index a38af87..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:15 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x32 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x32.vhd - VHDL template : fifo_4096x32_tmpl.vhd - VHDL testbench : tb_fifo_4096x32_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x32.srp - Element Usage : - AGEB2 : 14 - AND2 : 2 - CU2 : 14 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 76 - FD1S3BX : 1 - FD1S3DX : 53 - INV : 2 - OR2 : 1 - ROM16X1A : 34 - XOR2 : 24 - DP16KC : 8 - Estimated Resource Usage: - LUT : 129 - EBR : 8 - Reg : 132 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.sym b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.sym deleted file mode 100644 index 31b96dcb1af8686907a1495fa2cb785268272793..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 436 zcmX|-F-yZx6ot>FsYMa#;19^qL7bu$!Qv1wDQ?zM2`Hk)v>?Vd)Ch4a#aS{sI5;>s zh-7eZEY1!YoTZ~_r4bg{0gi$(Nc-An4&`$Lx3fzk(gLT#iCfS z+ClrMx>hrefd)YYD|1RscgO3WUBD$xaF|i8>DoOYB%7j_v0}4x)d_G%R+iE1b|a%t zq(1I*>I|~XchVTId8RW+Gru@zj1N@mpFq*R^n)9olEU6Wi@nB@;G5nLpw+KEk5=xb z`wj6+Z%$C!pDpw6E-!Y^yZw_5V{0?4t^+GFfgv{UPf&&}+ah>mdfH)E=~zwDl6mr> yN+38&KL213Q~m&R_fZ7^ diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd deleted file mode 100755 index 2f52ee4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd +++ /dev/null @@ -1,1803 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:24:15 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_4096x32 is - port ( - Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4096x32; - -architecture Structure of fifo_4096x32 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; - attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; - attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; - attribute RESETMODE of pdp_ram_0_2_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; - attribute RESETMODE of pdp_ram_0_3_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; - attribute RESETMODE of pdp_ram_0_4_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; - attribute RESETMODE of pdp_ram_0_5_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; - attribute RESETMODE of pdp_ram_0_6_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; - attribute RESETMODE of pdp_ram_0_7_0 : label is "SYNC"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_7: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_1_6: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), - DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_2_5: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), - DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8), - DOB1=>Q(9), DOB2=>Q(10), DOB3=>Q(11), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_3_4: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), - DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(12), - DOB1=>Q(13), DOB2=>Q(14), DOB3=>Q(15), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_4_3: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), - DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(16), - DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_5_2: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), - DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(20), - DOB1=>Q(21), DOB2=>Q(22), DOB3=>Q(23), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_6_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), - DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(24), - DOB1=>Q(25), DOB2=>Q(26), DOB3=>Q(27), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_7_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), - DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(28), - DOB1=>Q(29), DOB2=>Q(30), DOB3=>Q(31), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_131: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_130: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_129: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_128: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_127: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_126: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_125: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_124: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_123: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_122: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_121: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_120: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_119: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_118: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_117: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_116: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_115: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_114: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_113: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_112: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_111: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_110: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_109: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_108: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_107: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_106: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_105: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_104: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_103: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_102: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_101: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_100: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_99: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_98: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_97: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_96: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_95: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_94: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_93: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_92: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_91: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_90: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_89: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_88: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_87: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_86: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_85: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_84: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_83: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_82: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_81: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_80: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_79: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_78: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_77: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_76: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_75: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_74: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_73: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_72: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_71: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_70: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_69: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_68: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_67: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_66: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_65: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_64: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_63: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_62: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_61: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_60: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_59: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_58: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_57: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_56: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_55: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_54: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_53: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_4096x32 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32_generate.log deleted file mode 100755 index dcf82f8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:15 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 32 -num_words 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x32 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x32.vhd - VHDL template : fifo_4096x32_tmpl.vhd - VHDL testbench : tb_fifo_4096x32_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x32.srp - Estimated Resource Usage: - LUT : 129 - EBR : 8 - Reg : 132 - -END SCUBA Module Synthesis - -File: fifo_4096x32.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_4096x32_tmpl.vhd deleted file mode 100755 index f26714f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x32_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:24:15 2011 - --- parameterized module component declaration -component fifo_4096x32 - port (Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x32 - port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.ipx deleted file mode 100644 index 259c42b..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.jhd deleted file mode 100755 index 0a3f358..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.jhd +++ /dev/null @@ -1,487 +0,0 @@ -MODULE fifo_4096x9 DEFIN fifo_4096x9.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE MUX21 - INSTANCE mux_0 - SUBMODULE MUX21 - INSTANCE mux_1 - SUBMODULE MUX21 - INSTANCE mux_2 - SUBMODULE MUX21 - INSTANCE mux_3 - SUBMODULE MUX21 - INSTANCE mux_4 - SUBMODULE MUX21 - INSTANCE mux_5 - SUBMODULE MUX21 - INSTANCE mux_6 - SUBMODULE MUX21 - INSTANCE mux_7 - SUBMODULE MUX21 - INSTANCE mux_8 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3BX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3DX - INSTANCE FF_121 - SUBMODULE FD1P3DX - INSTANCE FF_122 - SUBMODULE FD1P3DX - INSTANCE FF_123 - SUBMODULE FD1P3DX - INSTANCE FF_124 - SUBMODULE FD1P3DX - INSTANCE FF_125 - SUBMODULE FD1P3DX - INSTANCE FF_126 - SUBMODULE FD1P3DX - INSTANCE FF_127 - SUBMODULE FD1P3DX - INSTANCE FF_128 - SUBMODULE FD1P3DX - INSTANCE FF_129 - SUBMODULE FD1P3DX - INSTANCE FF_130 - SUBMODULE FD1P3DX - INSTANCE FF_131 - SUBMODULE FD1P3BX - INSTANCE FF_132 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_0_0 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE ROM16X1A - INSTANCE LUT4_30 - SUBMODULE ROM16X1A - INSTANCE LUT4_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_32 - SUBMODULE ROM16X1A - INSTANCE LUT4_33 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE OR2 - INSTANCE OR2_t24 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t25 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t26 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.lpc deleted file mode 100755 index 6e382a8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_4096x9 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:06 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=9 -RDepth=4096 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.naf b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.naf deleted file mode 100755 index 1410b2d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.naf +++ /dev/null @@ -1,26 +0,0 @@ -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.sort b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.sort deleted file mode 100644 index 2c0a9ba..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_4096x9.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.srp b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.srp deleted file mode 100755 index b0b7426..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.srp +++ /dev/null @@ -1,43 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:06 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x9 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x9.vhd - VHDL template : fifo_4096x9_tmpl.vhd - VHDL testbench : tb_fifo_4096x9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x9.srp - Element Usage : - AGEB2 : 14 - AND2 : 2 - CU2 : 14 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 77 - FD1S3BX : 1 - FD1S3DX : 53 - INV : 2 - MUX21 : 9 - OR2 : 1 - ROM16X1A : 34 - XOR2 : 24 - DP16KC : 2 - Estimated Resource Usage: - LUT : 138 - EBR : 2 - Reg : 133 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.sym b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.sym deleted file mode 100644 index 01c98e8167ed3ad613c19c466b51a0b4860b4cea..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 432 zcmYk2u}i~17{%X5Q>E(A!OnxXUC2pBh&#hC)1vD<+m?MSulyXk0AA@(2yDn{*GH zb^8cg{LHXX`Prbi84XV_a6(&Pzp_Tq^RIwgx)M?4>OudypI}Val=N?Rr?StqF&?Hi z995mKv^gfz&TynUKX}RbpGW!CI_DvKqnr7;DDSnt4 zf|;G_D*w{O`N8>Mc)V)2*6v!c*kg;&yg(DaI3h^tRKKS=*XQU+gFe;WhxF=hCfAwf o5++I{nhSElSv8ZBbBr}-WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_132: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_131: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_130: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_129: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_128: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_127: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_126: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_125: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_124: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_123: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_122: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_121: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_120: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_119: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_118: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_117: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_116: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_115: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_114: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_113: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_112: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_111: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_110: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_109: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_108: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_107: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_106: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_105: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_104: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_103: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_102: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_101: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_100: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_99: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_98: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_97: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_96: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_95: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_94: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_93: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_92: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_91: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_90: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_89: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_88: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_87: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_86: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_85: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_84: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_83: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_82: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_81: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_80: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_79: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_78: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_77: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_76: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_75: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_74: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_73: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_72: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_71: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_70: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_69: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_68: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_67: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_66: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_65: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_64: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_63: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_62: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_61: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_60: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_59: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_58: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_57: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_56: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_55: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_54: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_53: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - mux_8: MUX21 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, - Z=>Q(0)); - - mux_7: MUX21 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, - Z=>Q(1)); - - mux_6: MUX21 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, - Z=>Q(2)); - - mux_5: MUX21 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, - Z=>Q(3)); - - mux_4: MUX21 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, - Z=>Q(4)); - - mux_3: MUX21 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, - Z=>Q(5)); - - mux_2: MUX21 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, - Z=>Q(6)); - - mux_1: MUX21 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, - Z=>Q(7)); - - mux_0: MUX21 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, - Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_4096x9 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX21 use entity ecp3.MUX21(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9_generate.log deleted file mode 100755 index a6a71a3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:06 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_4096x9 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_4096x9.vhd - VHDL template : fifo_4096x9_tmpl.vhd - VHDL testbench : tb_fifo_4096x9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_4096x9.srp - Estimated Resource Usage: - LUT : 138 - EBR : 2 - Reg : 133 - -END SCUBA Module Synthesis - -File: fifo_4096x9.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_4096x9_tmpl.vhd deleted file mode 100755 index 8b69bd4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4096x9_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:24:06 2011 - --- parameterized module component declaration -component fifo_4096x9 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x9 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd deleted file mode 100644 index 73df06a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd +++ /dev/null @@ -1,1573 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) --- Module Version: 5.5 ---/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_4kx18x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 18 -depth 2048 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Wed Jun 26 14:33:30 2013 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_4kx18x9 is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4kx18x9; - -architecture Structure of fifo_4kx18x9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal rcount_w0: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_12: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal co4: std_logic; - signal wcount_11: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6: std_logic; - signal co5_1: std_logic; - signal rcount_12: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r7: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w7: std_logic; - signal rcount_w8: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w11: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX21 - port (D0: in std_logic; D1: in std_logic; SD: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4kx18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; - attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t25: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t24: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t23: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t22: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t21: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t20: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t19: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t18: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t17: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t16: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t15: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t14: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t13: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t12: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, - DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, - DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, - DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_1_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, - DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, - DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, - DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - FF_127: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_126: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_125: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_124: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_123: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_122: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_121: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_120: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_119: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_118: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_117: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_116: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_115: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_114: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_113: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_112: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_111: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_110: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_109: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_108: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_107: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_106: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_105: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_104: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_103: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_102: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_101: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_100: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_99: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_98: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_97: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_96: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_95: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_94: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_93: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_92: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_91: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_90: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_89: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_88: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_87: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_86: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_85: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_84: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_83: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_82: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_81: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_80: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_79: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_78: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_77: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_76: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_75: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_74: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_73: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_72: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_71: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_70: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_69: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_68: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_67: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_66: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_65: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_64: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_63: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_62: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_61: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_60: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_59: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_58: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_57: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_56: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_55: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_54: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_53: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_52: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_51: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_50: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_49: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_48: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_47: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_46: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_45: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_44: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_43: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_42: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_41: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_40: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_39: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_38: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_37: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_36: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_35: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_34: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_33: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_32: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_31: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_30: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_29: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_28: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_27: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_26: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_25: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_24: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_23: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_22: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_21: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_20: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_19: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_18: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_17: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_16: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_15: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_14: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>ircount_12, NC1=>open); - - mux_8: MUX21 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, - Z=>Q(0)); - - mux_7: MUX21 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, - Z=>Q(1)); - - mux_6: MUX21 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, - Z=>Q(2)); - - mux_5: MUX21 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, - Z=>Q(3)); - - mux_4: MUX21 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, - Z=>Q(4)); - - mux_3: MUX21 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, - Z=>Q(5)); - - mux_2: MUX21 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, - Z=>Q(6)); - - mux_1: MUX21 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, - Z=>Q(7)); - - mux_0: MUX21 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, - Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w10, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w11, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_4kx18x9 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX21 use entity ecp3.MUX21(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd deleted file mode 100644 index f282f7a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd +++ /dev/null @@ -1,1559 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.4 ---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 8 -depth 4096 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Tue Apr 23 14:34:09 2013 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_4kx8_ecp3 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4kx8_ecp3; - -architecture Structure of fifo_4kx8_ecp3 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx8_ecp3.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_4kx8_ecp3.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_1_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, - ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, - ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, - ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), - DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - FF_131: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_130: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_129: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_128: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_127: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_126: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_125: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_124: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_123: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_122: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_121: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_120: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_119: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_118: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_117: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_116: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_115: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_114: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_113: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_112: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_111: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_110: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_109: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_108: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_107: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_106: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_105: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_104: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_103: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_102: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_101: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_100: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_99: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_98: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_97: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_96: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_95: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_94: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_93: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_92: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_91: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_90: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_89: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_88: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_87: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_86: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_85: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_84: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_83: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_82: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_81: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_80: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_79: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_78: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_77: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_76: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_75: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_74: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_73: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_72: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_71: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_70: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_69: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_68: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_67: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_66: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_65: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_64: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_63: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_62: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_61: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_60: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_59: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_58: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_57: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_56: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_55: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_54: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_53: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_4kx8_ecp3 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_512x32.ipx deleted file mode 100644 index 7699dd1..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x32.jhd deleted file mode 100644 index 161e346..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.jhd +++ /dev/null @@ -1,357 +0,0 @@ -MODULE fifo_512x32 DEFIN fifo_512x32.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1P3DX - INSTANCE FF_42 - SUBMODULE FD1P3DX - INSTANCE FF_43 - SUBMODULE FD1P3DX - INSTANCE FF_44 - SUBMODULE FD1P3DX - INSTANCE FF_45 - SUBMODULE FD1P3DX - INSTANCE FF_46 - SUBMODULE FD1P3DX - INSTANCE FF_47 - SUBMODULE FD1P3DX - INSTANCE FF_48 - SUBMODULE FD1P3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3BX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3BX - INSTANCE FF_101 - SUBMODULE PDPW16KC - INSTANCE pdp_ram_0_0_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE OR2 - INSTANCE OR2_t18 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t19 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t20 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_512x32.lpc deleted file mode 100644 index 67057ca..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x32 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:13:43 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=32 -RDepth=512 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.naf b/gbe2_ecp3/ipcores_ecp3/fifo_512x32.naf deleted file mode 100644 index 4603fbd..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.naf +++ /dev/null @@ -1,72 +0,0 @@ -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[31] o -Q[30] o -Q[29] o -Q[28] o -Q[27] o -Q[26] o -Q[25] o -Q[24] o -Q[23] o -Q[22] o -Q[21] o -Q[20] o -Q[19] o -Q[18] o -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.sort b/gbe2_ecp3/ipcores_ecp3/fifo_512x32.sort deleted file mode 100644 index d348cb5..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_512x32.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.srp b/gbe2_ecp3/ipcores_ecp3/fifo_512x32.srp deleted file mode 100644 index 9c75e33..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:13:43 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 32 -num_words 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x32 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x32.vhd - VHDL template : fifo_512x32_tmpl.vhd - VHDL testbench : tb_fifo_512x32_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x32.srp - Element Usage : - AGEB2 : 10 - AND2 : 2 - CU2 : 10 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 58 - FD1S3BX : 1 - FD1S3DX : 41 - INV : 2 - OR2 : 1 - ROM16X1A : 24 - XOR2 : 18 - PDPW16KC : 1 - Estimated Resource Usage: - LUT : 97 - EBR : 1 - Reg : 102 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32.sym b/gbe2_ecp3/ipcores_ecp3/fifo_512x32.sym deleted file mode 100644 index b1ded1ee0887feea07fc38e1005da44b97a4beff..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 434 zcmX|-ze~eV6ot>FsYM0p;4B%6gM;)3E|~&0U9CY0C@RIYpvE@TDs?OU14_o??fLQKRK6C1KEz?xVzHnvcx5>~2> zUgNk@vWh1_ogzXt?c`j4H|U&S!KY1dlv=~}oi@;?o1vY$tlPY4_AsK$%W$!~p4unc z5aYS^x@qP+ZH(7>rq@-OUz{_>2MV=MAnRO*y?d^b%--Pv&zeYrZ}xrwqjnnvY|VS> zegpinwbB6oWrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, - DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, - ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open, - DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), - DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), - DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), - DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); - - FF_101: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_512x32 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_512x32_generate.log deleted file mode 100644 index 04d17af..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:13:43 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 32 -num_words 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x32 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x32.vhd - VHDL template : fifo_512x32_tmpl.vhd - VHDL testbench : tb_fifo_512x32_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x32.srp - Estimated Resource Usage: - LUT : 97 - EBR : 1 - Reg : 102 - -END SCUBA Module Synthesis - -File: fifo_512x32.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x32_tmpl.vhd deleted file mode 100644 index a461685..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:13:43 2011 - --- parameterized module component declaration -component fifo_512x32 - port (Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x32 - port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd deleted file mode 100644 index fef9988..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd +++ /dev/null @@ -1,1298 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.4 ---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Tue Jun 11 11:02:45 2013 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_512x32x8 is - port ( - Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_512x32x8; - -architecture Structure of fifo_512x32x8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal rcount_w1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal rcount_w0: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r8: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KC - generic (GSR : in String; CSDECODE_R : in String; - CSDECODE_W : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32x8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t22: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t21: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t20: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t19: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t18: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t17: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t16: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t15: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t14: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t13: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t12: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t11: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10), - DI12=>Data(11), DI13=>Data(12), DI14=>Data(13), - DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo, - DI18=>Data(16), DI19=>Data(17), DI20=>Data(18), - DI21=>Data(19), DI22=>Data(20), DI23=>Data(21), - DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo, - DI27=>Data(24), DI28=>Data(25), DI29=>Data(26), - DI30=>Data(27), DI31=>Data(28), DI32=>Data(29), - DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo, - ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, - ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1, - ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5, - ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9, - ADR13=>rptr_10, CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, - CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), - DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), - DO6=>Q(6), DO7=>Q(7), DO8=>open, DO9=>open, DO10=>open, - DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, - DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open, - DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open, - DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open, - DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open); - - FF_111: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_110: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_109: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_108: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_107: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_106: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_105: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_104: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_103: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_102: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_101: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_100: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_99: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_98: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_97: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_96: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_95: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_94: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_93: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_92: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_91: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_90: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_89: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_88: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_87: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_86: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_85: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_84: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_83: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_81: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_80: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_79: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_78: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_77: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_76: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_75: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_74: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_73: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_72: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_71: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_70: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_69: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_68: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_67: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_66: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_65: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_64: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_63: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_62: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_61: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_60: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_59: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_58: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_57: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_56: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_55: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_54: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_53: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_52: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_51: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_50: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_49: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_48: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_47: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_46: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_45: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_44: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_43: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_42: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_41: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_40: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_39: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_38: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_37: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_36: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_35: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_34: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_33: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_32: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_31: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_30: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_29: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_28: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_27: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_26: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_25: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_24: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_23: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_22: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_21: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_20: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_19: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_18: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_17: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_16: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_15: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_14: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_13: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r0, - B1=>wcount_r1, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r2, - B1=>wcount_r3, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r4, - B1=>wcount_r5, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w2, - B1=>rcount_w3, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w4, - B1=>rcount_w5, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w6, - B1=>rcount_w7, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_512x32x8 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_512x64.ipx deleted file mode 100644 index 590d980..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x64.jhd deleted file mode 100644 index e72c941..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.jhd +++ /dev/null @@ -1,359 +0,0 @@ -MODULE fifo_512x64 DEFIN fifo_512x64.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1P3DX - INSTANCE FF_42 - SUBMODULE FD1P3DX - INSTANCE FF_43 - SUBMODULE FD1P3DX - INSTANCE FF_44 - SUBMODULE FD1P3DX - INSTANCE FF_45 - SUBMODULE FD1P3DX - INSTANCE FF_46 - SUBMODULE FD1P3DX - INSTANCE FF_47 - SUBMODULE FD1P3DX - INSTANCE FF_48 - SUBMODULE FD1P3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3BX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3BX - INSTANCE FF_101 - SUBMODULE PDPW16KC - INSTANCE pdp_ram_0_1_0 - SUBMODULE PDPW16KC - INSTANCE pdp_ram_0_0_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE OR2 - INSTANCE OR2_t18 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t19 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t20 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_512x64.lpc deleted file mode 100644 index f17569e..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x64 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:40 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=72 -RDepth=512 -RWidth=72 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.naf b/gbe2_ecp3/ipcores_ecp3/fifo_512x64.naf deleted file mode 100644 index 8a50577..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.naf +++ /dev/null @@ -1,152 +0,0 @@ -Data[71] i -Data[70] i -Data[69] i -Data[68] i -Data[67] i -Data[66] i -Data[65] i -Data[64] i -Data[63] i -Data[62] i -Data[61] i -Data[60] i -Data[59] i -Data[58] i -Data[57] i -Data[56] i -Data[55] i -Data[54] i -Data[53] i -Data[52] i -Data[51] i -Data[50] i -Data[49] i -Data[48] i -Data[47] i -Data[46] i -Data[45] i -Data[44] i -Data[43] i -Data[42] i -Data[41] i -Data[40] i -Data[39] i -Data[38] i -Data[37] i -Data[36] i -Data[35] i -Data[34] i -Data[33] i -Data[32] i -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[71] o -Q[70] o -Q[69] o -Q[68] o -Q[67] o -Q[66] o -Q[65] o -Q[64] o -Q[63] o -Q[62] o -Q[61] o -Q[60] o -Q[59] o -Q[58] o -Q[57] o -Q[56] o -Q[55] o -Q[54] o -Q[53] o -Q[52] o -Q[51] o -Q[50] o -Q[49] o -Q[48] o -Q[47] o -Q[46] o -Q[45] o -Q[44] o -Q[43] o -Q[42] o -Q[41] o -Q[40] o -Q[39] o -Q[38] o -Q[37] o -Q[36] o -Q[35] o -Q[34] o -Q[33] o -Q[32] o -Q[31] o -Q[30] o -Q[29] o -Q[28] o -Q[27] o -Q[26] o -Q[25] o -Q[24] o -Q[23] o -Q[22] o -Q[21] o -Q[20] o -Q[19] o -Q[18] o -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.sort b/gbe2_ecp3/ipcores_ecp3/fifo_512x64.sort deleted file mode 100644 index f4f13d7..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_512x64.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.srp b/gbe2_ecp3/ipcores_ecp3/fifo_512x64.srp deleted file mode 100644 index 554669e..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:40 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x64 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x64.vhd - VHDL template : fifo_512x64_tmpl.vhd - VHDL testbench : tb_fifo_512x64_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x64.srp - Element Usage : - AGEB2 : 10 - AND2 : 2 - CU2 : 10 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 58 - FD1S3BX : 1 - FD1S3DX : 41 - INV : 2 - OR2 : 1 - ROM16X1A : 24 - XOR2 : 18 - PDPW16KC : 2 - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64.sym b/gbe2_ecp3/ipcores_ecp3/fifo_512x64.sym deleted file mode 100644 index ec3f7b8a4f68c4984a292ffef5a94ab69be002f8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 434 zcmX|-ze~eV6ot>Ftwjat;4B%6gM+l<59k!I$!ZNsKv5~C1+})JMrpUwKcHk3CkJs7 z2~Lj1*&&0obad?O5(mRl-8G z9@LL_%9YXyP@@P@O*(nU+ii8uui(+fI7)2R@vJt`qno0gxSZ3tX#^P26=XQuT}$i} zt&jWEy4@u6oi@U2n(1~`<`?IT@PVTJ3FNG6Kj?FnWcCgZc-B~Ae6#lhWbNBli>`rZ(>y@D2c`06BJ-cMFfw`R{6H(NYCNOJpDjt wpVF(l8LUgqQy84-PIF9-G1MH9BaAeMWrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), - DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, - ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, - ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), - DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), - DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), - DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), - DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), - DO35=>Q(17)); - - pdp_ram_0_1_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), - DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), - DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), - DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), - DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), - DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), - DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), - DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), - DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), - DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), - DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), - DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, - ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, - ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, - BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, - CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, - ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, - ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, - ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, - ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), - DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), - DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), - DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), - DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), - DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), - DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), - DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), - DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); - - FF_101: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_512x64 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_512x64_generate.log deleted file mode 100644 index 2d50c76..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:40 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x64 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x64.vhd - VHDL template : fifo_512x64_tmpl.vhd - VHDL testbench : tb_fifo_512x64_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x64.srp - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 - -END SCUBA Module Synthesis - -File: fifo_512x64.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x64_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x64_tmpl.vhd deleted file mode 100644 index 490c7e6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x64_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:40 2011 - --- parameterized module component declaration -component fifo_512x64 - port (Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x64 - port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.ipx deleted file mode 100644 index 089af2c..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.jhd deleted file mode 100644 index 5bbf360..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.jhd +++ /dev/null @@ -1,359 +0,0 @@ -MODULE fifo_512x72 DEFIN fifo_512x72.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1P3DX - INSTANCE FF_42 - SUBMODULE FD1P3DX - INSTANCE FF_43 - SUBMODULE FD1P3DX - INSTANCE FF_44 - SUBMODULE FD1P3DX - INSTANCE FF_45 - SUBMODULE FD1P3DX - INSTANCE FF_46 - SUBMODULE FD1P3DX - INSTANCE FF_47 - SUBMODULE FD1P3DX - INSTANCE FF_48 - SUBMODULE FD1P3DX - INSTANCE FF_49 - SUBMODULE FD1P3DX - INSTANCE FF_50 - SUBMODULE FD1P3DX - INSTANCE FF_51 - SUBMODULE FD1P3DX - INSTANCE FF_52 - SUBMODULE FD1P3DX - INSTANCE FF_53 - SUBMODULE FD1P3DX - INSTANCE FF_54 - SUBMODULE FD1P3DX - INSTANCE FF_55 - SUBMODULE FD1P3DX - INSTANCE FF_56 - SUBMODULE FD1P3DX - INSTANCE FF_57 - SUBMODULE FD1P3DX - INSTANCE FF_58 - SUBMODULE FD1P3DX - INSTANCE FF_59 - SUBMODULE FD1P3DX - INSTANCE FF_60 - SUBMODULE FD1P3DX - INSTANCE FF_61 - SUBMODULE FD1P3DX - INSTANCE FF_62 - SUBMODULE FD1P3DX - INSTANCE FF_63 - SUBMODULE FD1P3DX - INSTANCE FF_64 - SUBMODULE FD1P3DX - INSTANCE FF_65 - SUBMODULE FD1P3DX - INSTANCE FF_66 - SUBMODULE FD1P3DX - INSTANCE FF_67 - SUBMODULE FD1P3DX - INSTANCE FF_68 - SUBMODULE FD1P3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3BX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3BX - INSTANCE FF_101 - SUBMODULE PDPW16KC - INSTANCE pdp_ram_0_1_0 - SUBMODULE PDPW16KC - INSTANCE pdp_ram_0_0_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE OR2 - INSTANCE OR2_t18 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t19 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t20 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.lpc deleted file mode 100644 index 1467961..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x72 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:14:03 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=72 -RDepth=512 -RWidth=72 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.naf b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.naf deleted file mode 100644 index 8a50577..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.naf +++ /dev/null @@ -1,152 +0,0 @@ -Data[71] i -Data[70] i -Data[69] i -Data[68] i -Data[67] i -Data[66] i -Data[65] i -Data[64] i -Data[63] i -Data[62] i -Data[61] i -Data[60] i -Data[59] i -Data[58] i -Data[57] i -Data[56] i -Data[55] i -Data[54] i -Data[53] i -Data[52] i -Data[51] i -Data[50] i -Data[49] i -Data[48] i -Data[47] i -Data[46] i -Data[45] i -Data[44] i -Data[43] i -Data[42] i -Data[41] i -Data[40] i -Data[39] i -Data[38] i -Data[37] i -Data[36] i -Data[35] i -Data[34] i -Data[33] i -Data[32] i -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[71] o -Q[70] o -Q[69] o -Q[68] o -Q[67] o -Q[66] o -Q[65] o -Q[64] o -Q[63] o -Q[62] o -Q[61] o -Q[60] o -Q[59] o -Q[58] o -Q[57] o -Q[56] o -Q[55] o -Q[54] o -Q[53] o -Q[52] o -Q[51] o -Q[50] o -Q[49] o -Q[48] o -Q[47] o -Q[46] o -Q[45] o -Q[44] o -Q[43] o -Q[42] o -Q[41] o -Q[40] o -Q[39] o -Q[38] o -Q[37] o -Q[36] o -Q[35] o -Q[34] o -Q[33] o -Q[32] o -Q[31] o -Q[30] o -Q[29] o -Q[28] o -Q[27] o -Q[26] o -Q[25] o -Q[24] o -Q[23] o -Q[22] o -Q[21] o -Q[20] o -Q[19] o -Q[18] o -Q[17] o -Q[16] o -Q[15] o -Q[14] o -Q[13] o -Q[12] o -Q[11] o -Q[10] o -Q[9] o -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.sort b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.sort deleted file mode 100644 index d456886..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_512x72.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.srp b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.srp deleted file mode 100644 index 291d3c1..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.srp +++ /dev/null @@ -1,42 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:14:03 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x72 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x72.vhd - VHDL template : fifo_512x72_tmpl.vhd - VHDL testbench : tb_fifo_512x72_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x72.srp - Element Usage : - AGEB2 : 10 - AND2 : 2 - CU2 : 10 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 58 - FD1S3BX : 1 - FD1S3DX : 41 - INV : 2 - OR2 : 1 - ROM16X1A : 24 - XOR2 : 18 - PDPW16KC : 2 - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.sym b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.sym deleted file mode 100644 index 50e7297cf7497f21f7083cb87c9d755424d20078..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 434 zcmX|-u}i~16vn?tQ;Q1H!C5jC2M1{jQpi*=$!ZNsK~X8D1vR#zMyXrrA5c0LCkJs7 z2~Lj1*&&0obad?OX1%L2zc^=%4;0)_AnRO*(LGm5X7BKTXH6u*H+w&T;ob%TTl1c} zUmw5hEeUe_i_83X*H>E?tr(R!CTF_SoRAX?G{@u^L(L=d2oIV=a)@VUs<$^;e0u)DGph0j+Wt_v diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd deleted file mode 100644 index 4ffa914..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd +++ /dev/null @@ -1,1231 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:14:04 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_512x72 is - port ( - Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_512x72; - -architecture Structure of fifo_512x72 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KC - generic (GSR : in String; CSDECODE_R : in String; - CSDECODE_W : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t20: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), - DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, - ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, - ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), - DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), - DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), - DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), - DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), - DO35=>Q(17)); - - pdp_ram_0_1_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), - DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), - DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), - DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), - DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), - DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), - DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), - DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), - DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), - DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), - DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), - DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, - ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, - ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, - BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, - CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, - ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, - ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, - ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, - ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), - DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), - DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), - DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), - DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), - DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), - DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), - DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), - DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); - - FF_101: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_512x72 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_512x72_generate.log deleted file mode 100644 index 4caac4e..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:14:03 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_512x72 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 72 -num_words 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_512x72 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[71:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[71:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_512x72.vhd - VHDL template : fifo_512x72_tmpl.vhd - VHDL testbench : tb_fifo_512x72_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_512x72.srp - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 - -END SCUBA Module Synthesis - -File: fifo_512x72.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_512x72_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_512x72_tmpl.vhd deleted file mode 100644 index b52a2b9..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_512x72_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:14:04 2011 - --- parameterized module component declaration -component fifo_512x72 - port (Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x72 - port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.ipx deleted file mode 100644 index f0fb8ec..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.jhd deleted file mode 100755 index a23a4f0..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.jhd +++ /dev/null @@ -1,711 +0,0 @@ -MODULE fifo_64kx8 DEFIN fifo_64kx8.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_8 - SUBMODULE AGEB2 - INSTANCE full_cmp_7 - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_8 - SUBMODULE AGEB2 - INSTANCE empty_cmp_7 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE MUX41 - INSTANCE mux_0 - SUBMODULE MUX41 - INSTANCE mux_1 - SUBMODULE MUX41 - INSTANCE mux_2 - SUBMODULE MUX41 - INSTANCE mux_3 - SUBMODULE MUX41 - INSTANCE mux_4 - SUBMODULE MUX41 - INSTANCE mux_5 - SUBMODULE MUX41 - INSTANCE mux_6 - SUBMODULE MUX41 - INSTANCE mux_7 - SUBMODULE CU2 - INSTANCE r_gctr_8 - SUBMODULE CU2 - INSTANCE r_gctr_7 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_8 - SUBMODULE CU2 - INSTANCE w_gctr_7 - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1S3DX - INSTANCE FF_54 - SUBMODULE FD1S3DX - INSTANCE FF_55 - SUBMODULE FD1S3DX - INSTANCE FF_56 - SUBMODULE FD1S3DX - INSTANCE FF_57 - SUBMODULE FD1S3DX - INSTANCE FF_58 - SUBMODULE FD1S3DX - INSTANCE FF_59 - SUBMODULE FD1S3DX - INSTANCE FF_60 - SUBMODULE FD1S3DX - INSTANCE FF_61 - SUBMODULE FD1S3DX - INSTANCE FF_62 - SUBMODULE FD1S3DX - INSTANCE FF_63 - SUBMODULE FD1S3DX - INSTANCE FF_64 - SUBMODULE FD1S3DX - INSTANCE FF_65 - SUBMODULE FD1S3DX - INSTANCE FF_66 - SUBMODULE FD1S3DX - INSTANCE FF_67 - SUBMODULE FD1S3DX - INSTANCE FF_68 - SUBMODULE FD1S3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3DX - INSTANCE FF_121 - SUBMODULE FD1P3BX - INSTANCE FF_122 - SUBMODULE FD1P3DX - INSTANCE FF_123 - SUBMODULE FD1P3DX - INSTANCE FF_124 - SUBMODULE FD1P3DX - INSTANCE FF_125 - SUBMODULE FD1P3DX - INSTANCE FF_126 - SUBMODULE FD1P3DX - INSTANCE FF_127 - SUBMODULE FD1P3DX - INSTANCE FF_128 - SUBMODULE FD1P3DX - INSTANCE FF_129 - SUBMODULE FD1P3DX - INSTANCE FF_130 - SUBMODULE FD1P3DX - INSTANCE FF_131 - SUBMODULE FD1P3DX - INSTANCE FF_132 - SUBMODULE FD1P3DX - INSTANCE FF_133 - SUBMODULE FD1P3DX - INSTANCE FF_134 - SUBMODULE FD1P3DX - INSTANCE FF_135 - SUBMODULE FD1P3DX - INSTANCE FF_136 - SUBMODULE FD1P3DX - INSTANCE FF_137 - SUBMODULE FD1P3DX - INSTANCE FF_138 - SUBMODULE FD1P3DX - INSTANCE FF_139 - SUBMODULE FD1P3DX - INSTANCE FF_140 - SUBMODULE FD1P3DX - INSTANCE FF_141 - SUBMODULE FD1P3DX - INSTANCE FF_142 - SUBMODULE FD1P3DX - INSTANCE FF_143 - SUBMODULE FD1P3DX - INSTANCE FF_144 - SUBMODULE FD1P3DX - INSTANCE FF_145 - SUBMODULE FD1P3DX - INSTANCE FF_146 - SUBMODULE FD1P3DX - INSTANCE FF_147 - SUBMODULE FD1P3DX - INSTANCE FF_148 - SUBMODULE FD1P3DX - INSTANCE FF_149 - SUBMODULE FD1P3DX - INSTANCE FF_150 - SUBMODULE FD1P3DX - INSTANCE FF_151 - SUBMODULE FD1P3DX - INSTANCE FF_152 - SUBMODULE FD1P3DX - INSTANCE FF_153 - SUBMODULE FD1P3DX - INSTANCE FF_154 - SUBMODULE FD1P3DX - INSTANCE FF_155 - SUBMODULE FD1P3DX - INSTANCE FF_156 - SUBMODULE FD1P3DX - INSTANCE FF_157 - SUBMODULE FD1P3DX - INSTANCE FF_158 - SUBMODULE FD1P3DX - INSTANCE FF_159 - SUBMODULE FD1P3DX - INSTANCE FF_160 - SUBMODULE FD1P3DX - INSTANCE FF_161 - SUBMODULE FD1P3DX - INSTANCE FF_162 - SUBMODULE FD1P3DX - INSTANCE FF_163 - SUBMODULE FD1P3DX - INSTANCE FF_164 - SUBMODULE FD1P3DX - INSTANCE FF_165 - SUBMODULE FD1P3DX - INSTANCE FF_166 - SUBMODULE FD1P3DX - INSTANCE FF_167 - SUBMODULE FD1P3DX - INSTANCE FF_168 - SUBMODULE FD1P3DX - INSTANCE FF_169 - SUBMODULE FD1P3DX - INSTANCE FF_170 - SUBMODULE FD1P3DX - INSTANCE FF_171 - SUBMODULE FD1P3DX - INSTANCE FF_172 - SUBMODULE FD1P3BX - INSTANCE FF_173 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_7_0 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_6_1 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_5_2 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_4_3 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_3_4 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_2_5 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_1_6 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_0_7 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_7_8 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_6_9 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_5_10 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_4_11 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_3_12 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_2_13 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_1_14 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_0_15 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_7_16 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_6_17 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_5_18 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_4_19 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_3_20 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_2_21 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_1_22 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_0_23 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_7_24 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_6_25 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_5_26 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_4_27 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_3_28 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_2_29 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_1_30 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE ROM16X1A - INSTANCE LUT4_30 - SUBMODULE ROM16X1A - INSTANCE LUT4_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_32 - SUBMODULE ROM16X1A - INSTANCE LUT4_33 - SUBMODULE ROM16X1A - INSTANCE LUT4_34 - SUBMODULE ROM16X1A - INSTANCE LUT4_35 - SUBMODULE ROM16X1A - INSTANCE LUT4_36 - SUBMODULE ROM16X1A - INSTANCE LUT4_37 - SUBMODULE ROM16X1A - INSTANCE LUT4_38 - SUBMODULE ROM16X1A - INSTANCE LUT4_39 - SUBMODULE ROM16X1A - INSTANCE LUT4_40 - SUBMODULE ROM16X1A - INSTANCE LUT4_41 - SUBMODULE ROM16X1A - INSTANCE LUT4_42 - SUBMODULE ROM16X1A - INSTANCE LUT4_43 - SUBMODULE ROM16X1A - INSTANCE LUT4_44 - SUBMODULE ROM16X1A - INSTANCE LUT4_45 - SUBMODULE ROM16X1A - INSTANCE LUT4_46 - SUBMODULE ROM16X1A - INSTANCE LUT4_47 - SUBMODULE ROM16X1A - INSTANCE LUT4_48 - SUBMODULE ROM16X1A - INSTANCE LUT4_49 - SUBMODULE ROM16X1A - INSTANCE LUT4_50 - SUBMODULE ROM16X1A - INSTANCE LUT4_51 - SUBMODULE ROM16X1A - INSTANCE LUT4_52 - SUBMODULE ROM16X1A - INSTANCE LUT4_53 - SUBMODULE ROM16X1A - INSTANCE LUT4_54 - SUBMODULE ROM16X1A - INSTANCE LUT4_55 - SUBMODULE ROM16X1A - INSTANCE LUT4_56 - SUBMODULE ROM16X1A - INSTANCE LUT4_57 - SUBMODULE ROM16X1A - INSTANCE LUT4_58 - SUBMODULE ROM16X1A - INSTANCE LUT4_59 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE XOR2 - INSTANCE XOR2_t24 - SUBMODULE XOR2 - INSTANCE XOR2_t25 - SUBMODULE XOR2 - INSTANCE XOR2_t26 - SUBMODULE XOR2 - INSTANCE XOR2_t27 - SUBMODULE XOR2 - INSTANCE XOR2_t28 - SUBMODULE XOR2 - INSTANCE XOR2_t29 - SUBMODULE XOR2 - INSTANCE XOR2_t30 - SUBMODULE XOR2 - INSTANCE XOR2_t31 - SUBMODULE OR2 - INSTANCE OR2_t32 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE AND2 - INSTANCE AND2_t33 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE AND2 - INSTANCE AND2_t34 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.lpc deleted file mode 100755 index badffb2..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_64kx8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:03 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=65536 -Width=8 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.naf b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.naf deleted file mode 100755 index 6378b4d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.naf +++ /dev/null @@ -1,24 +0,0 @@ -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.sort b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.sort deleted file mode 100644 index e09daf4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_64kx8.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.srp b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.srp deleted file mode 100755 index 3b2bc69..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.srp +++ /dev/null @@ -1,43 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:03 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx8 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx8.vhd - VHDL template : fifo_64kx8_tmpl.vhd - VHDL testbench : tb_fifo_64kx8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx8.srp - Element Usage : - AGEB2 : 18 - AND2 : 2 - CU2 : 18 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 102 - FD1S3BX : 1 - FD1S3DX : 69 - INV : 2 - MUX41 : 8 - OR2 : 1 - ROM16X1A : 60 - XOR2 : 32 - DP16KC : 32 - Estimated Resource Usage: - LUT : 187 - EBR : 32 - Reg : 174 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.sym b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.sym deleted file mode 100644 index 39af0f868df1c53f9739c8728a48fa4d638c9a21..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 432 zcmYk2u}i~17{%X5Q>DeBgQG)+PU6r(v^WJ#I%*9{1Qn^aMQOC5M$s*QK!;4?DB{>5 zle4o^aCUZ-jE=s$i(uf$FTZ#9xG%E+d@5X-SPJnZj@Vd|6#*8cP2*r0O_xw}dvWh@ zeWP`ZZGNWMG=ARiZ-wKt5l(4y92jf)eeVjmr7I8`SM>+igBVk~h9rNdyT(4#MtCS~ zFfpC4v>9e)XE0HnAG~FTH#9r%K-Ig9;(P9r%Fg~CzM19tWcCGEotrRZRAy?r1V79y z!Q8GHWrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t33: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t32: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t31: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t30: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t29: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t28: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t27: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t26: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t25: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t24: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t23: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t22: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t21: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t20: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t19: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t18: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t17: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t16: XOR2 - port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - LUT4_59: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>w_gcount_r216, - DO0=>w_g2b_xor_cluster_0); - - LUT4_58: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_1); - - LUT4_57: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_2); - - LUT4_56: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_3); - - LUT4_55: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r15); - - LUT4_54: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, - AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_53: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, - DO0=>wcount_r10); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r3); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r2); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_10); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, - AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, - DO0=>func_xor_inet_11); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_1_30: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_2_29: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_3_28: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_4_27: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_5_26: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_6_25: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_7_24: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_1_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_2_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_3_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_4_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_5_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_6_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_7_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_15: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_1_14: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_2_13: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_3_12: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_4_11: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_5_10: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_6_9: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_7_8: DP16KC - generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_7: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_1_6: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_2_5: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_3_4: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_4_3: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_5_2: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_6_1: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_7_0: DP16KC - generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, - DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, - DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_173: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_172: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_171: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_170: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_169: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_168: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_167: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_166: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_165: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_164: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_163: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_162: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_161: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_160: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_159: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_158: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_157: FD1P3DX - port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_16); - - FF_156: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_155: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_154: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_153: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_152: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_151: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_150: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_149: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_148: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_147: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_146: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_145: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_144: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_143: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_142: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_141: FD1P3DX - port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_140: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_16); - - FF_139: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_138: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_137: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_136: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_135: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_134: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_133: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_132: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_131: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_130: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_129: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_128: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_127: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_126: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_125: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_124: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_123: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_16); - - FF_122: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_121: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_120: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_119: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_118: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_117: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_116: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_115: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_114: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_113: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_112: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_111: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_110: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_109: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_108: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_107: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_106: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_105: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_104: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_103: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_102: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_101: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_100: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_99: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_98: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_97: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_96: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_95: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_94: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_93: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_92: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_91: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_90: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_89: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_88: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_87: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_86: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_85: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_84: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_83: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_82: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_81: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_80: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_79: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_78: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_77: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_76: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_75: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_74: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_73: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_72: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_71: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_70: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_69: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_68: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_67: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_66: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_65: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_64: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_63: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_62: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_61: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_60: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_59: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_58: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_57: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_56: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_55: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_54: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_53: FD1S3DX - port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r16); - - FF_52: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_51: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_50: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_49: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_48: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_47: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_46: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_45: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_44: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_43: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_42: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_41: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_40: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_39: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_38: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_37: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_36: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_35: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_34: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_33: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_32: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_31: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_30: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_29: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_28: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_27: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_26: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_25: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_24: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_23: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_22: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_21: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_20: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_19: FD1S3DX - port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r216); - - FF_18: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - w_gctr_8: CU2 - port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>iwcount_16, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, - NC0=>ircount_16, NC1=>open); - - mux_7: MUX41 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); - - mux_6: MUX41 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); - - mux_5: MUX41 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); - - mux_4: MUX41 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); - - mux_3: MUX41 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); - - mux_2: MUX41 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); - - mux_1: MUX41 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); - - mux_0: MUX41 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, - B1=>wcount_r15, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, - B1=>rcount_w15, CI=>co6_3, GE=>co7_3); - - full_cmp_8: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_64kx8 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX41 use entity ecp3.MUX41(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8_generate.log deleted file mode 100755 index 1ec2186..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:03 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 8 -num_words 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx8 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[7:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx8.vhd - VHDL template : fifo_64kx8_tmpl.vhd - VHDL testbench : tb_fifo_64kx8_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx8.srp - Estimated Resource Usage: - LUT : 187 - EBR : 32 - Reg : 174 - -END SCUBA Module Synthesis - -File: fifo_64kx8.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_64kx8_tmpl.vhd deleted file mode 100755 index 9aba2ac..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:03 2011 - --- parameterized module component declaration -component fifo_64kx8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_64kx8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.ipx b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.ipx deleted file mode 100644 index 78ff181..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.jhd b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.jhd deleted file mode 100644 index 2be439b..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.jhd +++ /dev/null @@ -1,995 +0,0 @@ -MODULE fifo_64kx9 DEFIN fifo_64kx9.vhd - SUBMODULE FADD2B - INSTANCE a1 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE AGEB2 - INSTANCE full_cmp_8 - SUBMODULE AGEB2 - INSTANCE full_cmp_7 - SUBMODULE AGEB2 - INSTANCE full_cmp_6 - SUBMODULE AGEB2 - INSTANCE full_cmp_5 - SUBMODULE AGEB2 - INSTANCE full_cmp_4 - SUBMODULE AGEB2 - INSTANCE full_cmp_3 - SUBMODULE AGEB2 - INSTANCE full_cmp_2 - SUBMODULE AGEB2 - INSTANCE full_cmp_1 - SUBMODULE AGEB2 - INSTANCE full_cmp_0 - SUBMODULE FADD2B - INSTANCE full_cmp_ci_a - SUBMODULE FADD2B - INSTANCE a0 - SUBMODULE AGEB2 - INSTANCE empty_cmp_8 - SUBMODULE AGEB2 - INSTANCE empty_cmp_7 - SUBMODULE AGEB2 - INSTANCE empty_cmp_6 - SUBMODULE AGEB2 - INSTANCE empty_cmp_5 - SUBMODULE AGEB2 - INSTANCE empty_cmp_4 - SUBMODULE AGEB2 - INSTANCE empty_cmp_3 - SUBMODULE AGEB2 - INSTANCE empty_cmp_2 - SUBMODULE AGEB2 - INSTANCE empty_cmp_1 - SUBMODULE AGEB2 - INSTANCE empty_cmp_0 - SUBMODULE FADD2B - INSTANCE empty_cmp_ci_a - SUBMODULE MUX321 - INSTANCE mux_0 - SUBMODULE MUX321 - INSTANCE mux_1 - SUBMODULE MUX321 - INSTANCE mux_2 - SUBMODULE MUX321 - INSTANCE mux_3 - SUBMODULE MUX321 - INSTANCE mux_4 - SUBMODULE MUX321 - INSTANCE mux_5 - SUBMODULE MUX321 - INSTANCE mux_6 - SUBMODULE MUX321 - INSTANCE mux_7 - SUBMODULE MUX321 - INSTANCE mux_8 - SUBMODULE CU2 - INSTANCE r_gctr_8 - SUBMODULE CU2 - INSTANCE r_gctr_7 - SUBMODULE CU2 - INSTANCE r_gctr_6 - SUBMODULE CU2 - INSTANCE r_gctr_5 - SUBMODULE CU2 - INSTANCE r_gctr_4 - SUBMODULE CU2 - INSTANCE r_gctr_3 - SUBMODULE CU2 - INSTANCE r_gctr_2 - SUBMODULE CU2 - INSTANCE r_gctr_1 - SUBMODULE CU2 - INSTANCE r_gctr_0 - SUBMODULE FADD2B - INSTANCE r_gctr_cia - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE CU2 - INSTANCE w_gctr_8 - SUBMODULE CU2 - INSTANCE w_gctr_7 - SUBMODULE CU2 - INSTANCE w_gctr_6 - SUBMODULE CU2 - INSTANCE w_gctr_5 - SUBMODULE CU2 - INSTANCE w_gctr_4 - SUBMODULE CU2 - INSTANCE w_gctr_3 - SUBMODULE CU2 - INSTANCE w_gctr_2 - SUBMODULE CU2 - INSTANCE w_gctr_1 - SUBMODULE CU2 - INSTANCE w_gctr_0 - SUBMODULE FADD2B - INSTANCE w_gctr_cia - SUBMODULE FD1S3DX - INSTANCE FF_0 - SUBMODULE FD1S3BX - INSTANCE FF_1 - SUBMODULE FD1S3DX - INSTANCE FF_2 - SUBMODULE FD1S3DX - INSTANCE FF_3 - SUBMODULE FD1S3DX - INSTANCE FF_4 - SUBMODULE FD1S3DX - INSTANCE FF_5 - SUBMODULE FD1S3DX - INSTANCE FF_6 - SUBMODULE FD1S3DX - INSTANCE FF_7 - SUBMODULE FD1S3DX - INSTANCE FF_8 - SUBMODULE FD1S3DX - INSTANCE FF_9 - SUBMODULE FD1S3DX - INSTANCE FF_10 - SUBMODULE FD1S3DX - INSTANCE FF_11 - SUBMODULE FD1S3DX - INSTANCE FF_12 - SUBMODULE FD1S3DX - INSTANCE FF_13 - SUBMODULE FD1S3DX - INSTANCE FF_14 - SUBMODULE FD1S3DX - INSTANCE FF_15 - SUBMODULE FD1S3DX - INSTANCE FF_16 - SUBMODULE FD1S3DX - INSTANCE FF_17 - SUBMODULE FD1S3DX - INSTANCE FF_18 - SUBMODULE FD1S3DX - INSTANCE FF_19 - SUBMODULE FD1S3DX - INSTANCE FF_20 - SUBMODULE FD1S3DX - INSTANCE FF_21 - SUBMODULE FD1S3DX - INSTANCE FF_22 - SUBMODULE FD1S3DX - INSTANCE FF_23 - SUBMODULE FD1S3DX - INSTANCE FF_24 - SUBMODULE FD1S3DX - INSTANCE FF_25 - SUBMODULE FD1S3DX - INSTANCE FF_26 - SUBMODULE FD1S3DX - INSTANCE FF_27 - SUBMODULE FD1S3DX - INSTANCE FF_28 - SUBMODULE FD1S3DX - INSTANCE FF_29 - SUBMODULE FD1S3DX - INSTANCE FF_30 - SUBMODULE FD1S3DX - INSTANCE FF_31 - SUBMODULE FD1S3DX - INSTANCE FF_32 - SUBMODULE FD1S3DX - INSTANCE FF_33 - SUBMODULE FD1S3DX - INSTANCE FF_34 - SUBMODULE FD1S3DX - INSTANCE FF_35 - SUBMODULE FD1S3DX - INSTANCE FF_36 - SUBMODULE FD1S3DX - INSTANCE FF_37 - SUBMODULE FD1S3DX - INSTANCE FF_38 - SUBMODULE FD1S3DX - INSTANCE FF_39 - SUBMODULE FD1S3DX - INSTANCE FF_40 - SUBMODULE FD1S3DX - INSTANCE FF_41 - SUBMODULE FD1S3DX - INSTANCE FF_42 - SUBMODULE FD1S3DX - INSTANCE FF_43 - SUBMODULE FD1S3DX - INSTANCE FF_44 - SUBMODULE FD1S3DX - INSTANCE FF_45 - SUBMODULE FD1S3DX - INSTANCE FF_46 - SUBMODULE FD1S3DX - INSTANCE FF_47 - SUBMODULE FD1S3DX - INSTANCE FF_48 - SUBMODULE FD1S3DX - INSTANCE FF_49 - SUBMODULE FD1S3DX - INSTANCE FF_50 - SUBMODULE FD1S3DX - INSTANCE FF_51 - SUBMODULE FD1S3DX - INSTANCE FF_52 - SUBMODULE FD1S3DX - INSTANCE FF_53 - SUBMODULE FD1S3DX - INSTANCE FF_54 - SUBMODULE FD1S3DX - INSTANCE FF_55 - SUBMODULE FD1S3DX - INSTANCE FF_56 - SUBMODULE FD1S3DX - INSTANCE FF_57 - SUBMODULE FD1S3DX - INSTANCE FF_58 - SUBMODULE FD1S3DX - INSTANCE FF_59 - SUBMODULE FD1S3DX - INSTANCE FF_60 - SUBMODULE FD1S3DX - INSTANCE FF_61 - SUBMODULE FD1S3DX - INSTANCE FF_62 - SUBMODULE FD1S3DX - INSTANCE FF_63 - SUBMODULE FD1S3DX - INSTANCE FF_64 - SUBMODULE FD1S3DX - INSTANCE FF_65 - SUBMODULE FD1S3DX - INSTANCE FF_66 - SUBMODULE FD1S3DX - INSTANCE FF_67 - SUBMODULE FD1S3DX - INSTANCE FF_68 - SUBMODULE FD1S3DX - INSTANCE FF_69 - SUBMODULE FD1P3DX - INSTANCE FF_70 - SUBMODULE FD1P3DX - INSTANCE FF_71 - SUBMODULE FD1P3DX - INSTANCE FF_72 - SUBMODULE FD1P3DX - INSTANCE FF_73 - SUBMODULE FD1P3DX - INSTANCE FF_74 - SUBMODULE FD1P3DX - INSTANCE FF_75 - SUBMODULE FD1P3DX - INSTANCE FF_76 - SUBMODULE FD1P3DX - INSTANCE FF_77 - SUBMODULE FD1P3DX - INSTANCE FF_78 - SUBMODULE FD1P3DX - INSTANCE FF_79 - SUBMODULE FD1P3DX - INSTANCE FF_80 - SUBMODULE FD1P3DX - INSTANCE FF_81 - SUBMODULE FD1P3DX - INSTANCE FF_82 - SUBMODULE FD1P3DX - INSTANCE FF_83 - SUBMODULE FD1P3DX - INSTANCE FF_84 - SUBMODULE FD1P3DX - INSTANCE FF_85 - SUBMODULE FD1P3DX - INSTANCE FF_86 - SUBMODULE FD1P3DX - INSTANCE FF_87 - SUBMODULE FD1P3DX - INSTANCE FF_88 - SUBMODULE FD1P3DX - INSTANCE FF_89 - SUBMODULE FD1P3DX - INSTANCE FF_90 - SUBMODULE FD1P3DX - INSTANCE FF_91 - SUBMODULE FD1P3DX - INSTANCE FF_92 - SUBMODULE FD1P3DX - INSTANCE FF_93 - SUBMODULE FD1P3DX - INSTANCE FF_94 - SUBMODULE FD1P3DX - INSTANCE FF_95 - SUBMODULE FD1P3DX - INSTANCE FF_96 - SUBMODULE FD1P3DX - INSTANCE FF_97 - SUBMODULE FD1P3DX - INSTANCE FF_98 - SUBMODULE FD1P3DX - INSTANCE FF_99 - SUBMODULE FD1P3DX - INSTANCE FF_100 - SUBMODULE FD1P3DX - INSTANCE FF_101 - SUBMODULE FD1P3DX - INSTANCE FF_102 - SUBMODULE FD1P3DX - INSTANCE FF_103 - SUBMODULE FD1P3DX - INSTANCE FF_104 - SUBMODULE FD1P3DX - INSTANCE FF_105 - SUBMODULE FD1P3DX - INSTANCE FF_106 - SUBMODULE FD1P3DX - INSTANCE FF_107 - SUBMODULE FD1P3DX - INSTANCE FF_108 - SUBMODULE FD1P3DX - INSTANCE FF_109 - SUBMODULE FD1P3DX - INSTANCE FF_110 - SUBMODULE FD1P3DX - INSTANCE FF_111 - SUBMODULE FD1P3DX - INSTANCE FF_112 - SUBMODULE FD1P3DX - INSTANCE FF_113 - SUBMODULE FD1P3DX - INSTANCE FF_114 - SUBMODULE FD1P3DX - INSTANCE FF_115 - SUBMODULE FD1P3DX - INSTANCE FF_116 - SUBMODULE FD1P3DX - INSTANCE FF_117 - SUBMODULE FD1P3DX - INSTANCE FF_118 - SUBMODULE FD1P3DX - INSTANCE FF_119 - SUBMODULE FD1P3DX - INSTANCE FF_120 - SUBMODULE FD1P3DX - INSTANCE FF_121 - SUBMODULE FD1P3DX - INSTANCE FF_122 - SUBMODULE FD1P3DX - INSTANCE FF_123 - SUBMODULE FD1P3DX - INSTANCE FF_124 - SUBMODULE FD1P3BX - INSTANCE FF_125 - SUBMODULE FD1P3DX - INSTANCE FF_126 - SUBMODULE FD1P3DX - INSTANCE FF_127 - SUBMODULE FD1P3DX - INSTANCE FF_128 - SUBMODULE FD1P3DX - INSTANCE FF_129 - SUBMODULE FD1P3DX - INSTANCE FF_130 - SUBMODULE FD1P3DX - INSTANCE FF_131 - SUBMODULE FD1P3DX - INSTANCE FF_132 - SUBMODULE FD1P3DX - INSTANCE FF_133 - SUBMODULE FD1P3DX - INSTANCE FF_134 - SUBMODULE FD1P3DX - INSTANCE FF_135 - SUBMODULE FD1P3DX - INSTANCE FF_136 - SUBMODULE FD1P3DX - INSTANCE FF_137 - SUBMODULE FD1P3DX - INSTANCE FF_138 - SUBMODULE FD1P3DX - INSTANCE FF_139 - SUBMODULE FD1P3DX - INSTANCE FF_140 - SUBMODULE FD1P3DX - INSTANCE FF_141 - SUBMODULE FD1P3DX - INSTANCE FF_142 - SUBMODULE FD1P3DX - INSTANCE FF_143 - SUBMODULE FD1P3DX - INSTANCE FF_144 - SUBMODULE FD1P3DX - INSTANCE FF_145 - SUBMODULE FD1P3DX - INSTANCE FF_146 - SUBMODULE FD1P3DX - INSTANCE FF_147 - SUBMODULE FD1P3DX - INSTANCE FF_148 - SUBMODULE FD1P3DX - INSTANCE FF_149 - SUBMODULE FD1P3DX - INSTANCE FF_150 - SUBMODULE FD1P3DX - INSTANCE FF_151 - SUBMODULE FD1P3DX - INSTANCE FF_152 - SUBMODULE FD1P3DX - INSTANCE FF_153 - SUBMODULE FD1P3DX - INSTANCE FF_154 - SUBMODULE FD1P3DX - INSTANCE FF_155 - SUBMODULE FD1P3DX - INSTANCE FF_156 - SUBMODULE FD1P3DX - INSTANCE FF_157 - SUBMODULE FD1P3DX - INSTANCE FF_158 - SUBMODULE FD1P3DX - INSTANCE FF_159 - SUBMODULE FD1P3DX - INSTANCE FF_160 - SUBMODULE FD1P3DX - INSTANCE FF_161 - SUBMODULE FD1P3DX - INSTANCE FF_162 - SUBMODULE FD1P3DX - INSTANCE FF_163 - SUBMODULE FD1P3DX - INSTANCE FF_164 - SUBMODULE FD1P3DX - INSTANCE FF_165 - SUBMODULE FD1P3DX - INSTANCE FF_166 - SUBMODULE FD1P3DX - INSTANCE FF_167 - SUBMODULE FD1P3DX - INSTANCE FF_168 - SUBMODULE FD1P3DX - INSTANCE FF_169 - SUBMODULE FD1P3DX - INSTANCE FF_170 - SUBMODULE FD1P3DX - INSTANCE FF_171 - SUBMODULE FD1P3DX - INSTANCE FF_172 - SUBMODULE FD1P3DX - INSTANCE FF_173 - SUBMODULE FD1P3DX - INSTANCE FF_174 - SUBMODULE FD1P3DX - INSTANCE FF_175 - SUBMODULE FD1P3BX - INSTANCE FF_176 - SUBMODULE DP16KC - INSTANCE pdp_ram_31_0_0 - SUBMODULE DP16KC - INSTANCE pdp_ram_30_0_1 - SUBMODULE DP16KC - INSTANCE pdp_ram_29_0_2 - SUBMODULE DP16KC - INSTANCE pdp_ram_28_0_3 - SUBMODULE DP16KC - INSTANCE pdp_ram_27_0_4 - SUBMODULE DP16KC - INSTANCE pdp_ram_26_0_5 - SUBMODULE DP16KC - INSTANCE pdp_ram_25_0_6 - SUBMODULE DP16KC - INSTANCE pdp_ram_24_0_7 - SUBMODULE DP16KC - INSTANCE pdp_ram_23_0_8 - SUBMODULE DP16KC - INSTANCE pdp_ram_22_0_9 - SUBMODULE DP16KC - INSTANCE pdp_ram_21_0_10 - SUBMODULE DP16KC - INSTANCE pdp_ram_20_0_11 - SUBMODULE DP16KC - INSTANCE pdp_ram_19_0_12 - SUBMODULE DP16KC - INSTANCE pdp_ram_18_0_13 - SUBMODULE DP16KC - INSTANCE pdp_ram_17_0_14 - SUBMODULE DP16KC - INSTANCE pdp_ram_16_0_15 - SUBMODULE DP16KC - INSTANCE pdp_ram_15_0_16 - SUBMODULE DP16KC - INSTANCE pdp_ram_14_0_17 - SUBMODULE DP16KC - INSTANCE pdp_ram_13_0_18 - SUBMODULE DP16KC - INSTANCE pdp_ram_12_0_19 - SUBMODULE DP16KC - INSTANCE pdp_ram_11_0_20 - SUBMODULE DP16KC - INSTANCE pdp_ram_10_0_21 - SUBMODULE DP16KC - INSTANCE pdp_ram_9_0_22 - SUBMODULE DP16KC - INSTANCE pdp_ram_8_0_23 - SUBMODULE DP16KC - INSTANCE pdp_ram_7_0_24 - SUBMODULE DP16KC - INSTANCE pdp_ram_6_0_25 - SUBMODULE DP16KC - INSTANCE pdp_ram_5_0_26 - SUBMODULE DP16KC - INSTANCE pdp_ram_4_0_27 - SUBMODULE DP16KC - INSTANCE pdp_ram_3_0_28 - SUBMODULE DP16KC - INSTANCE pdp_ram_2_0_29 - SUBMODULE DP16KC - INSTANCE pdp_ram_1_0_30 - SUBMODULE DP16KC - INSTANCE pdp_ram_0_0_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_0 - SUBMODULE ROM16X1A - INSTANCE LUT4_1 - SUBMODULE ROM16X1A - INSTANCE LUT4_2 - SUBMODULE ROM16X1A - INSTANCE LUT4_3 - SUBMODULE ROM16X1A - INSTANCE LUT4_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_5 - SUBMODULE ROM16X1A - INSTANCE LUT4_6 - SUBMODULE ROM16X1A - INSTANCE LUT4_7 - SUBMODULE ROM16X1A - INSTANCE LUT4_8 - SUBMODULE ROM16X1A - INSTANCE LUT4_9 - SUBMODULE ROM16X1A - INSTANCE LUT4_10 - SUBMODULE ROM16X1A - INSTANCE LUT4_11 - SUBMODULE ROM16X1A - INSTANCE LUT4_12 - SUBMODULE ROM16X1A - INSTANCE LUT4_13 - SUBMODULE ROM16X1A - INSTANCE LUT4_14 - SUBMODULE ROM16X1A - INSTANCE LUT4_15 - SUBMODULE ROM16X1A - INSTANCE LUT4_16 - SUBMODULE ROM16X1A - INSTANCE LUT4_17 - SUBMODULE ROM16X1A - INSTANCE LUT4_18 - SUBMODULE ROM16X1A - INSTANCE LUT4_19 - SUBMODULE ROM16X1A - INSTANCE LUT4_20 - SUBMODULE ROM16X1A - INSTANCE LUT4_21 - SUBMODULE ROM16X1A - INSTANCE LUT4_22 - SUBMODULE ROM16X1A - INSTANCE LUT4_23 - SUBMODULE ROM16X1A - INSTANCE LUT4_24 - SUBMODULE ROM16X1A - INSTANCE LUT4_25 - SUBMODULE ROM16X1A - INSTANCE LUT4_26 - SUBMODULE ROM16X1A - INSTANCE LUT4_27 - SUBMODULE ROM16X1A - INSTANCE LUT4_28 - SUBMODULE ROM16X1A - INSTANCE LUT4_29 - SUBMODULE ROM16X1A - INSTANCE LUT4_30 - SUBMODULE ROM16X1A - INSTANCE LUT4_31 - SUBMODULE ROM16X1A - INSTANCE LUT4_32 - SUBMODULE ROM16X1A - INSTANCE LUT4_33 - SUBMODULE ROM16X1A - INSTANCE LUT4_34 - SUBMODULE ROM16X1A - INSTANCE LUT4_35 - SUBMODULE ROM16X1A - INSTANCE LUT4_36 - SUBMODULE ROM16X1A - INSTANCE LUT4_37 - SUBMODULE ROM16X1A - INSTANCE LUT4_38 - SUBMODULE ROM16X1A - INSTANCE LUT4_39 - SUBMODULE ROM16X1A - INSTANCE LUT4_40 - SUBMODULE ROM16X1A - INSTANCE LUT4_41 - SUBMODULE ROM16X1A - INSTANCE LUT4_42 - SUBMODULE ROM16X1A - INSTANCE LUT4_43 - SUBMODULE ROM16X1A - INSTANCE LUT4_44 - SUBMODULE ROM16X1A - INSTANCE LUT4_45 - SUBMODULE ROM16X1A - INSTANCE LUT4_46 - SUBMODULE ROM16X1A - INSTANCE LUT4_47 - SUBMODULE ROM16X1A - INSTANCE LUT4_48 - SUBMODULE ROM16X1A - INSTANCE LUT4_49 - SUBMODULE ROM16X1A - INSTANCE LUT4_50 - SUBMODULE ROM16X1A - INSTANCE LUT4_51 - SUBMODULE ROM16X1A - INSTANCE LUT4_52 - SUBMODULE ROM16X1A - INSTANCE LUT4_53 - SUBMODULE ROM16X1A - INSTANCE LUT4_54 - SUBMODULE ROM16X1A - INSTANCE LUT4_55 - SUBMODULE ROM16X1A - INSTANCE LUT4_56 - SUBMODULE ROM16X1A - INSTANCE LUT4_57 - SUBMODULE ROM16X1A - INSTANCE LUT4_58 - SUBMODULE ROM16X1A - INSTANCE LUT4_59 - SUBMODULE ROM16X1A - INSTANCE LUT4_60 - SUBMODULE ROM16X1A - INSTANCE LUT4_61 - SUBMODULE ROM16X1A - INSTANCE LUT4_62 - SUBMODULE ROM16X1A - INSTANCE LUT4_63 - SUBMODULE ROM16X1A - INSTANCE LUT4_64 - SUBMODULE ROM16X1A - INSTANCE LUT4_65 - SUBMODULE ROM16X1A - INSTANCE LUT4_66 - SUBMODULE ROM16X1A - INSTANCE LUT4_67 - SUBMODULE ROM16X1A - INSTANCE LUT4_68 - SUBMODULE ROM16X1A - INSTANCE LUT4_69 - SUBMODULE ROM16X1A - INSTANCE LUT4_70 - SUBMODULE ROM16X1A - INSTANCE LUT4_71 - SUBMODULE ROM16X1A - INSTANCE LUT4_72 - SUBMODULE ROM16X1A - INSTANCE LUT4_73 - SUBMODULE ROM16X1A - INSTANCE LUT4_74 - SUBMODULE ROM16X1A - INSTANCE LUT4_75 - SUBMODULE ROM16X1A - INSTANCE LUT4_76 - SUBMODULE ROM16X1A - INSTANCE LUT4_77 - SUBMODULE ROM16X1A - INSTANCE LUT4_78 - SUBMODULE ROM16X1A - INSTANCE LUT4_79 - SUBMODULE ROM16X1A - INSTANCE LUT4_80 - SUBMODULE ROM16X1A - INSTANCE LUT4_81 - SUBMODULE ROM16X1A - INSTANCE LUT4_82 - SUBMODULE ROM16X1A - INSTANCE LUT4_83 - SUBMODULE ROM16X1A - INSTANCE LUT4_84 - SUBMODULE ROM16X1A - INSTANCE LUT4_85 - SUBMODULE ROM16X1A - INSTANCE LUT4_86 - SUBMODULE ROM16X1A - INSTANCE LUT4_87 - SUBMODULE ROM16X1A - INSTANCE LUT4_88 - SUBMODULE ROM16X1A - INSTANCE LUT4_89 - SUBMODULE ROM16X1A - INSTANCE LUT4_90 - SUBMODULE ROM16X1A - INSTANCE LUT4_91 - SUBMODULE ROM16X1A - INSTANCE LUT4_92 - SUBMODULE ROM16X1A - INSTANCE LUT4_93 - SUBMODULE ROM16X1A - INSTANCE LUT4_94 - SUBMODULE ROM16X1A - INSTANCE LUT4_95 - SUBMODULE ROM16X1A - INSTANCE LUT4_96 - SUBMODULE ROM16X1A - INSTANCE LUT4_97 - SUBMODULE ROM16X1A - INSTANCE LUT4_98 - SUBMODULE ROM16X1A - INSTANCE LUT4_99 - SUBMODULE ROM16X1A - INSTANCE LUT4_100 - SUBMODULE ROM16X1A - INSTANCE LUT4_101 - SUBMODULE ROM16X1A - INSTANCE LUT4_102 - SUBMODULE ROM16X1A - INSTANCE LUT4_103 - SUBMODULE ROM16X1A - INSTANCE LUT4_104 - SUBMODULE ROM16X1A - INSTANCE LUT4_105 - SUBMODULE ROM16X1A - INSTANCE LUT4_106 - SUBMODULE ROM16X1A - INSTANCE LUT4_107 - SUBMODULE ROM16X1A - INSTANCE LUT4_108 - SUBMODULE ROM16X1A - INSTANCE LUT4_109 - SUBMODULE ROM16X1A - INSTANCE LUT4_110 - SUBMODULE ROM16X1A - INSTANCE LUT4_111 - SUBMODULE ROM16X1A - INSTANCE LUT4_112 - SUBMODULE ROM16X1A - INSTANCE LUT4_113 - SUBMODULE ROM16X1A - INSTANCE LUT4_114 - SUBMODULE ROM16X1A - INSTANCE LUT4_115 - SUBMODULE ROM16X1A - INSTANCE LUT4_116 - SUBMODULE ROM16X1A - INSTANCE LUT4_117 - SUBMODULE ROM16X1A - INSTANCE LUT4_118 - SUBMODULE ROM16X1A - INSTANCE LUT4_119 - SUBMODULE ROM16X1A - INSTANCE LUT4_120 - SUBMODULE ROM16X1A - INSTANCE LUT4_121 - SUBMODULE ROM16X1A - INSTANCE LUT4_122 - SUBMODULE ROM16X1A - INSTANCE LUT4_123 - SUBMODULE ROM16X1A - INSTANCE LUT4_124 - SUBMODULE ROM16X1A - INSTANCE LUT4_125 - SUBMODULE ROM16X1A - INSTANCE LUT4_126 - SUBMODULE ROM16X1A - INSTANCE LUT4_127 - SUBMODULE ROM16X1A - INSTANCE LUT4_128 - SUBMODULE ROM16X1A - INSTANCE LUT4_129 - SUBMODULE ROM16X1A - INSTANCE LUT4_130 - SUBMODULE ROM16X1A - INSTANCE LUT4_131 - SUBMODULE ROM16X1A - INSTANCE LUT4_132 - SUBMODULE ROM16X1A - INSTANCE LUT4_133 - SUBMODULE ROM16X1A - INSTANCE LUT4_134 - SUBMODULE ROM16X1A - INSTANCE LUT4_135 - SUBMODULE ROM16X1A - INSTANCE LUT4_136 - SUBMODULE ROM16X1A - INSTANCE LUT4_137 - SUBMODULE ROM16X1A - INSTANCE LUT4_138 - SUBMODULE ROM16X1A - INSTANCE LUT4_139 - SUBMODULE ROM16X1A - INSTANCE LUT4_140 - SUBMODULE ROM16X1A - INSTANCE LUT4_141 - SUBMODULE ROM16X1A - INSTANCE LUT4_142 - SUBMODULE ROM16X1A - INSTANCE LUT4_143 - SUBMODULE ROM16X1A - INSTANCE LUT4_144 - SUBMODULE ROM16X1A - INSTANCE LUT4_145 - SUBMODULE ROM16X1A - INSTANCE LUT4_146 - SUBMODULE ROM16X1A - INSTANCE LUT4_147 - SUBMODULE ROM16X1A - INSTANCE LUT4_148 - SUBMODULE ROM16X1A - INSTANCE LUT4_149 - SUBMODULE ROM16X1A - INSTANCE LUT4_150 - SUBMODULE ROM16X1A - INSTANCE LUT4_151 - SUBMODULE ROM16X1A - INSTANCE LUT4_152 - SUBMODULE ROM16X1A - INSTANCE LUT4_153 - SUBMODULE ROM16X1A - INSTANCE LUT4_154 - SUBMODULE ROM16X1A - INSTANCE LUT4_155 - SUBMODULE ROM16X1A - INSTANCE LUT4_156 - SUBMODULE ROM16X1A - INSTANCE LUT4_157 - SUBMODULE ROM16X1A - INSTANCE LUT4_158 - SUBMODULE ROM16X1A - INSTANCE LUT4_159 - SUBMODULE ROM16X1A - INSTANCE LUT4_160 - SUBMODULE ROM16X1A - INSTANCE LUT4_161 - SUBMODULE ROM16X1A - INSTANCE LUT4_162 - SUBMODULE ROM16X1A - INSTANCE LUT4_163 - SUBMODULE ROM16X1A - INSTANCE LUT4_164 - SUBMODULE ROM16X1A - INSTANCE LUT4_165 - SUBMODULE ROM16X1A - INSTANCE LUT4_166 - SUBMODULE ROM16X1A - INSTANCE LUT4_167 - SUBMODULE ROM16X1A - INSTANCE LUT4_168 - SUBMODULE ROM16X1A - INSTANCE LUT4_169 - SUBMODULE ROM16X1A - INSTANCE LUT4_170 - SUBMODULE ROM16X1A - INSTANCE LUT4_171 - SUBMODULE ROM16X1A - INSTANCE LUT4_172 - SUBMODULE ROM16X1A - INSTANCE LUT4_173 - SUBMODULE ROM16X1A - INSTANCE LUT4_174 - SUBMODULE ROM16X1A - INSTANCE LUT4_175 - SUBMODULE ROM16X1A - INSTANCE LUT4_176 - SUBMODULE ROM16X1A - INSTANCE LUT4_177 - SUBMODULE ROM16X1A - INSTANCE LUT4_178 - SUBMODULE ROM16X1A - INSTANCE LUT4_179 - SUBMODULE ROM16X1A - INSTANCE LUT4_180 - SUBMODULE ROM16X1A - INSTANCE LUT4_181 - SUBMODULE ROM16X1A - INSTANCE LUT4_182 - SUBMODULE ROM16X1A - INSTANCE LUT4_183 - SUBMODULE ROM16X1A - INSTANCE LUT4_184 - SUBMODULE ROM16X1A - INSTANCE LUT4_185 - SUBMODULE INV - INSTANCE INV_0 - SUBMODULE INV - INSTANCE INV_1 - SUBMODULE INV - INSTANCE INV_2 - SUBMODULE INV - INSTANCE INV_3 - SUBMODULE INV - INSTANCE INV_4 - SUBMODULE ROM16X1A - INSTANCE LUT4_186 - SUBMODULE ROM16X1A - INSTANCE LUT4_187 - SUBMODULE INV - INSTANCE INV_5 - SUBMODULE INV - INSTANCE INV_6 - SUBMODULE INV - INSTANCE INV_7 - SUBMODULE INV - INSTANCE INV_8 - SUBMODULE INV - INSTANCE INV_9 - SUBMODULE XOR2 - INSTANCE XOR2_t0 - SUBMODULE XOR2 - INSTANCE XOR2_t1 - SUBMODULE XOR2 - INSTANCE XOR2_t2 - SUBMODULE XOR2 - INSTANCE XOR2_t3 - SUBMODULE XOR2 - INSTANCE XOR2_t4 - SUBMODULE XOR2 - INSTANCE XOR2_t5 - SUBMODULE XOR2 - INSTANCE XOR2_t6 - SUBMODULE XOR2 - INSTANCE XOR2_t7 - SUBMODULE XOR2 - INSTANCE XOR2_t8 - SUBMODULE XOR2 - INSTANCE XOR2_t9 - SUBMODULE XOR2 - INSTANCE XOR2_t10 - SUBMODULE XOR2 - INSTANCE XOR2_t11 - SUBMODULE XOR2 - INSTANCE XOR2_t12 - SUBMODULE XOR2 - INSTANCE XOR2_t13 - SUBMODULE XOR2 - INSTANCE XOR2_t14 - SUBMODULE XOR2 - INSTANCE XOR2_t15 - SUBMODULE XOR2 - INSTANCE XOR2_t16 - SUBMODULE XOR2 - INSTANCE XOR2_t17 - SUBMODULE XOR2 - INSTANCE XOR2_t18 - SUBMODULE XOR2 - INSTANCE XOR2_t19 - SUBMODULE XOR2 - INSTANCE XOR2_t20 - SUBMODULE XOR2 - INSTANCE XOR2_t21 - SUBMODULE XOR2 - INSTANCE XOR2_t22 - SUBMODULE XOR2 - INSTANCE XOR2_t23 - SUBMODULE XOR2 - INSTANCE XOR2_t24 - SUBMODULE XOR2 - INSTANCE XOR2_t25 - SUBMODULE XOR2 - INSTANCE XOR2_t26 - SUBMODULE XOR2 - INSTANCE XOR2_t27 - SUBMODULE XOR2 - INSTANCE XOR2_t28 - SUBMODULE XOR2 - INSTANCE XOR2_t29 - SUBMODULE XOR2 - INSTANCE XOR2_t30 - SUBMODULE XOR2 - INSTANCE XOR2_t31 - SUBMODULE OR2 - INSTANCE OR2_t32 - SUBMODULE INV - INSTANCE INV_10 - SUBMODULE AND2 - INSTANCE AND2_t33 - SUBMODULE INV - INSTANCE INV_11 - SUBMODULE AND2 - INSTANCE AND2_t34 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.lpc deleted file mode 100644 index a9ca96b..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_64kx9 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:21 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=65536 -Width=9 -RDepth=65536 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.naf b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.naf deleted file mode 100644 index 1410b2d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.naf +++ /dev/null @@ -1,26 +0,0 @@ -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WrClock i -RdClock i -WrEn i -RdEn i -Reset i -RPReset i -Q[8] o -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o -Empty o -Full o diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.sort b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.sort deleted file mode 100644 index 55eb217..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.sort +++ /dev/null @@ -1 +0,0 @@ -fifo_64kx9.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.srp b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.srp deleted file mode 100644 index 3f23449..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.srp +++ /dev/null @@ -1,43 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:21 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx9 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx9.vhd - VHDL template : fifo_64kx9_tmpl.vhd - VHDL testbench : tb_fifo_64kx9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx9.srp - Element Usage : - AGEB2 : 18 - AND2 : 2 - CU2 : 18 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 105 - FD1S3BX : 1 - FD1S3DX : 69 - INV : 12 - MUX321 : 9 - OR2 : 1 - ROM16X1A : 188 - XOR2 : 32 - DP16KC : 32 - Estimated Resource Usage: - LUT : 379 - EBR : 32 - Reg : 177 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.sym b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.sym deleted file mode 100644 index 056da05d3ad64e3cdda928e58bceb25b549136c4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 432 zcmYk2u}i~17{%X5Q>DeBgQG)+OybZ%Bsv96I%*9{1Qn^aMQOC5M$s*QK!;4?DB{>5 zle4o^aCUZ-jE=s$L@;pVm*4yDahF*DJ~ggP425_SM@%fqiU12@(>Pd$F53aRyaNz;gmMVL1_)Y?_B}6bOplF)&0TsAjXugCCT6JZfT!sBRo_# zn3SEbv>9eqXE0HnA3SA-H&~r_pzd8p@ja)cwzI#7Z)Q0@nSB99=OzppRhhb7f*)pv zU~ad(%D;56IlLH-Pu5mPck6(~p0;?*bF|=zErNtj^}CugeU7d)=o8(2M6d2(r~30I7trJz+~>$IIrvVS diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd deleted file mode 100644 index 9ad1f19..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd +++ /dev/null @@ -1,4582 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:23:21 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_64kx9 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_64kx9; - -architecture Structure of fifo_64kx9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal func_and_inet: std_logic; - signal func_and_inet_1: std_logic; - signal func_and_inet_2: std_logic; - signal func_and_inet_3: std_logic; - signal func_and_inet_4: std_logic; - signal func_and_inet_5: std_logic; - signal func_and_inet_6: std_logic; - signal func_and_inet_7: std_logic; - signal func_and_inet_8: std_logic; - signal func_and_inet_9: std_logic; - signal func_and_inet_10: std_logic; - signal func_and_inet_11: std_logic; - signal func_and_inet_12: std_logic; - signal func_and_inet_13: std_logic; - signal func_and_inet_14: std_logic; - signal func_and_inet_15: std_logic; - signal func_and_inet_16: std_logic; - signal func_and_inet_17: std_logic; - signal func_and_inet_18: std_logic; - signal func_and_inet_19: std_logic; - signal func_and_inet_20: std_logic; - signal func_and_inet_21: std_logic; - signal func_and_inet_22: std_logic; - signal func_and_inet_23: std_logic; - signal func_and_inet_24: std_logic; - signal func_and_inet_25: std_logic; - signal func_and_inet_26: std_logic; - signal func_and_inet_27: std_logic; - signal func_and_inet_28: std_logic; - signal func_and_inet_29: std_logic; - signal wptr_15_inv: std_logic; - signal func_and_inet_30: std_logic; - signal rptr_15_inv: std_logic; - signal func_and_inet_31: std_logic; - signal func_and_inet_32: std_logic; - signal func_and_inet_33: std_logic; - signal func_and_inet_34: std_logic; - signal func_and_inet_35: std_logic; - signal func_and_inet_36: std_logic; - signal func_and_inet_37: std_logic; - signal func_and_inet_38: std_logic; - signal func_and_inet_39: std_logic; - signal func_and_inet_40: std_logic; - signal func_and_inet_41: std_logic; - signal func_and_inet_42: std_logic; - signal func_and_inet_43: std_logic; - signal func_and_inet_44: std_logic; - signal func_and_inet_45: std_logic; - signal wptr_14_inv: std_logic; - signal func_and_inet_46: std_logic; - signal rptr_14_inv: std_logic; - signal func_and_inet_47: std_logic; - signal func_and_inet_48: std_logic; - signal func_and_inet_49: std_logic; - signal func_and_inet_50: std_logic; - signal func_and_inet_51: std_logic; - signal func_and_inet_52: std_logic; - signal func_and_inet_53: std_logic; - signal wptr_13_inv: std_logic; - signal func_and_inet_54: std_logic; - signal rptr_13_inv: std_logic; - signal func_and_inet_55: std_logic; - signal func_and_inet_56: std_logic; - signal func_and_inet_57: std_logic; - signal wptr_12_inv: std_logic; - signal func_and_inet_58: std_logic; - signal rptr_12_inv: std_logic; - signal func_and_inet_59: std_logic; - signal wptr_11_inv: std_logic; - signal func_and_inet_60: std_logic; - signal rptr_11_inv: std_logic; - signal func_and_inet_61: std_logic; - signal func_and_inet_62: std_logic; - signal func_and_inet_63: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_9: std_logic; - signal func_xor_inet_8: std_logic; - signal func_xor_inet_7: std_logic; - signal func_xor_inet_6: std_logic; - signal func_xor_inet_10: std_logic; - signal func_xor_inet_11: std_logic; - signal dec1_r10: std_logic; - signal dec0_p00: std_logic; - signal dec3_r11: std_logic; - signal dec2_p01: std_logic; - signal dec5_r12: std_logic; - signal dec4_p02: std_logic; - signal dec7_r13: std_logic; - signal dec6_p03: std_logic; - signal dec9_r14: std_logic; - signal dec8_p04: std_logic; - signal dec11_r15: std_logic; - signal dec10_p05: std_logic; - signal dec13_r16: std_logic; - signal dec12_p06: std_logic; - signal dec15_r17: std_logic; - signal dec14_p07: std_logic; - signal dec17_r18: std_logic; - signal dec16_p08: std_logic; - signal dec19_r19: std_logic; - signal dec18_p09: std_logic; - signal dec21_r110: std_logic; - signal dec20_p010: std_logic; - signal dec23_r111: std_logic; - signal dec22_p011: std_logic; - signal dec25_r112: std_logic; - signal dec24_p012: std_logic; - signal dec27_r113: std_logic; - signal dec26_p013: std_logic; - signal dec29_r114: std_logic; - signal dec28_p014: std_logic; - signal dec31_r115: std_logic; - signal dec30_p015: std_logic; - signal dec33_r116: std_logic; - signal dec32_p016: std_logic; - signal dec35_r117: std_logic; - signal dec34_p017: std_logic; - signal dec37_r118: std_logic; - signal dec36_p018: std_logic; - signal dec39_r119: std_logic; - signal dec38_p019: std_logic; - signal dec41_r120: std_logic; - signal dec40_p020: std_logic; - signal dec43_r121: std_logic; - signal dec42_p021: std_logic; - signal dec45_r122: std_logic; - signal dec44_p022: std_logic; - signal dec47_r123: std_logic; - signal dec46_p023: std_logic; - signal dec49_r124: std_logic; - signal dec48_p024: std_logic; - signal dec51_r125: std_logic; - signal dec50_p025: std_logic; - signal dec53_r126: std_logic; - signal dec52_p026: std_logic; - signal dec55_r127: std_logic; - signal dec54_p027: std_logic; - signal dec57_r128: std_logic; - signal dec56_p028: std_logic; - signal dec59_r129: std_logic; - signal dec58_p029: std_logic; - signal dec61_r130: std_logic; - signal dec60_p030: std_logic; - signal dec63_r131: std_logic; - signal dec62_p031: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal w_gdata_15: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wptr_15: std_logic; - signal wptr_16: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_16: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rptr_15: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal w_gcount_16: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal w_gcount_r216: std_logic; - signal w_gcount_r16: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co6: std_logic; - signal iwcount_16: std_logic; - signal co8: std_logic; - signal wcount_16: std_logic; - signal co7: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8_1: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_31_0: std_logic; - signal mdout1_30_0: std_logic; - signal mdout1_29_0: std_logic; - signal mdout1_28_0: std_logic; - signal mdout1_27_0: std_logic; - signal mdout1_26_0: std_logic; - signal mdout1_25_0: std_logic; - signal mdout1_24_0: std_logic; - signal mdout1_23_0: std_logic; - signal mdout1_22_0: std_logic; - signal mdout1_21_0: std_logic; - signal mdout1_20_0: std_logic; - signal mdout1_19_0: std_logic; - signal mdout1_18_0: std_logic; - signal mdout1_17_0: std_logic; - signal mdout1_16_0: std_logic; - signal mdout1_15_0: std_logic; - signal mdout1_14_0: std_logic; - signal mdout1_13_0: std_logic; - signal mdout1_12_0: std_logic; - signal mdout1_11_0: std_logic; - signal mdout1_10_0: std_logic; - signal mdout1_9_0: std_logic; - signal mdout1_8_0: std_logic; - signal mdout1_7_0: std_logic; - signal mdout1_6_0: std_logic; - signal mdout1_5_0: std_logic; - signal mdout1_4_0: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_31_1: std_logic; - signal mdout1_30_1: std_logic; - signal mdout1_29_1: std_logic; - signal mdout1_28_1: std_logic; - signal mdout1_27_1: std_logic; - signal mdout1_26_1: std_logic; - signal mdout1_25_1: std_logic; - signal mdout1_24_1: std_logic; - signal mdout1_23_1: std_logic; - signal mdout1_22_1: std_logic; - signal mdout1_21_1: std_logic; - signal mdout1_20_1: std_logic; - signal mdout1_19_1: std_logic; - signal mdout1_18_1: std_logic; - signal mdout1_17_1: std_logic; - signal mdout1_16_1: std_logic; - signal mdout1_15_1: std_logic; - signal mdout1_14_1: std_logic; - signal mdout1_13_1: std_logic; - signal mdout1_12_1: std_logic; - signal mdout1_11_1: std_logic; - signal mdout1_10_1: std_logic; - signal mdout1_9_1: std_logic; - signal mdout1_8_1: std_logic; - signal mdout1_7_1: std_logic; - signal mdout1_6_1: std_logic; - signal mdout1_5_1: std_logic; - signal mdout1_4_1: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_31_2: std_logic; - signal mdout1_30_2: std_logic; - signal mdout1_29_2: std_logic; - signal mdout1_28_2: std_logic; - signal mdout1_27_2: std_logic; - signal mdout1_26_2: std_logic; - signal mdout1_25_2: std_logic; - signal mdout1_24_2: std_logic; - signal mdout1_23_2: std_logic; - signal mdout1_22_2: std_logic; - signal mdout1_21_2: std_logic; - signal mdout1_20_2: std_logic; - signal mdout1_19_2: std_logic; - signal mdout1_18_2: std_logic; - signal mdout1_17_2: std_logic; - signal mdout1_16_2: std_logic; - signal mdout1_15_2: std_logic; - signal mdout1_14_2: std_logic; - signal mdout1_13_2: std_logic; - signal mdout1_12_2: std_logic; - signal mdout1_11_2: std_logic; - signal mdout1_10_2: std_logic; - signal mdout1_9_2: std_logic; - signal mdout1_8_2: std_logic; - signal mdout1_7_2: std_logic; - signal mdout1_6_2: std_logic; - signal mdout1_5_2: std_logic; - signal mdout1_4_2: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_31_3: std_logic; - signal mdout1_30_3: std_logic; - signal mdout1_29_3: std_logic; - signal mdout1_28_3: std_logic; - signal mdout1_27_3: std_logic; - signal mdout1_26_3: std_logic; - signal mdout1_25_3: std_logic; - signal mdout1_24_3: std_logic; - signal mdout1_23_3: std_logic; - signal mdout1_22_3: std_logic; - signal mdout1_21_3: std_logic; - signal mdout1_20_3: std_logic; - signal mdout1_19_3: std_logic; - signal mdout1_18_3: std_logic; - signal mdout1_17_3: std_logic; - signal mdout1_16_3: std_logic; - signal mdout1_15_3: std_logic; - signal mdout1_14_3: std_logic; - signal mdout1_13_3: std_logic; - signal mdout1_12_3: std_logic; - signal mdout1_11_3: std_logic; - signal mdout1_10_3: std_logic; - signal mdout1_9_3: std_logic; - signal mdout1_8_3: std_logic; - signal mdout1_7_3: std_logic; - signal mdout1_6_3: std_logic; - signal mdout1_5_3: std_logic; - signal mdout1_4_3: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_31_4: std_logic; - signal mdout1_30_4: std_logic; - signal mdout1_29_4: std_logic; - signal mdout1_28_4: std_logic; - signal mdout1_27_4: std_logic; - signal mdout1_26_4: std_logic; - signal mdout1_25_4: std_logic; - signal mdout1_24_4: std_logic; - signal mdout1_23_4: std_logic; - signal mdout1_22_4: std_logic; - signal mdout1_21_4: std_logic; - signal mdout1_20_4: std_logic; - signal mdout1_19_4: std_logic; - signal mdout1_18_4: std_logic; - signal mdout1_17_4: std_logic; - signal mdout1_16_4: std_logic; - signal mdout1_15_4: std_logic; - signal mdout1_14_4: std_logic; - signal mdout1_13_4: std_logic; - signal mdout1_12_4: std_logic; - signal mdout1_11_4: std_logic; - signal mdout1_10_4: std_logic; - signal mdout1_9_4: std_logic; - signal mdout1_8_4: std_logic; - signal mdout1_7_4: std_logic; - signal mdout1_6_4: std_logic; - signal mdout1_5_4: std_logic; - signal mdout1_4_4: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_31_5: std_logic; - signal mdout1_30_5: std_logic; - signal mdout1_29_5: std_logic; - signal mdout1_28_5: std_logic; - signal mdout1_27_5: std_logic; - signal mdout1_26_5: std_logic; - signal mdout1_25_5: std_logic; - signal mdout1_24_5: std_logic; - signal mdout1_23_5: std_logic; - signal mdout1_22_5: std_logic; - signal mdout1_21_5: std_logic; - signal mdout1_20_5: std_logic; - signal mdout1_19_5: std_logic; - signal mdout1_18_5: std_logic; - signal mdout1_17_5: std_logic; - signal mdout1_16_5: std_logic; - signal mdout1_15_5: std_logic; - signal mdout1_14_5: std_logic; - signal mdout1_13_5: std_logic; - signal mdout1_12_5: std_logic; - signal mdout1_11_5: std_logic; - signal mdout1_10_5: std_logic; - signal mdout1_9_5: std_logic; - signal mdout1_8_5: std_logic; - signal mdout1_7_5: std_logic; - signal mdout1_6_5: std_logic; - signal mdout1_5_5: std_logic; - signal mdout1_4_5: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_31_6: std_logic; - signal mdout1_30_6: std_logic; - signal mdout1_29_6: std_logic; - signal mdout1_28_6: std_logic; - signal mdout1_27_6: std_logic; - signal mdout1_26_6: std_logic; - signal mdout1_25_6: std_logic; - signal mdout1_24_6: std_logic; - signal mdout1_23_6: std_logic; - signal mdout1_22_6: std_logic; - signal mdout1_21_6: std_logic; - signal mdout1_20_6: std_logic; - signal mdout1_19_6: std_logic; - signal mdout1_18_6: std_logic; - signal mdout1_17_6: std_logic; - signal mdout1_16_6: std_logic; - signal mdout1_15_6: std_logic; - signal mdout1_14_6: std_logic; - signal mdout1_13_6: std_logic; - signal mdout1_12_6: std_logic; - signal mdout1_11_6: std_logic; - signal mdout1_10_6: std_logic; - signal mdout1_9_6: std_logic; - signal mdout1_8_6: std_logic; - signal mdout1_7_6: std_logic; - signal mdout1_6_6: std_logic; - signal mdout1_5_6: std_logic; - signal mdout1_4_6: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_31_7: std_logic; - signal mdout1_30_7: std_logic; - signal mdout1_29_7: std_logic; - signal mdout1_28_7: std_logic; - signal mdout1_27_7: std_logic; - signal mdout1_26_7: std_logic; - signal mdout1_25_7: std_logic; - signal mdout1_24_7: std_logic; - signal mdout1_23_7: std_logic; - signal mdout1_22_7: std_logic; - signal mdout1_21_7: std_logic; - signal mdout1_20_7: std_logic; - signal mdout1_19_7: std_logic; - signal mdout1_18_7: std_logic; - signal mdout1_17_7: std_logic; - signal mdout1_16_7: std_logic; - signal mdout1_15_7: std_logic; - signal mdout1_14_7: std_logic; - signal mdout1_13_7: std_logic; - signal mdout1_12_7: std_logic; - signal mdout1_11_7: std_logic; - signal mdout1_10_7: std_logic; - signal mdout1_9_7: std_logic; - signal mdout1_8_7: std_logic; - signal mdout1_7_7: std_logic; - signal mdout1_6_7: std_logic; - signal mdout1_5_7: std_logic; - signal mdout1_4_7: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal rptr_13_ff: std_logic; - signal rptr_12_ff: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_31_8: std_logic; - signal mdout1_30_8: std_logic; - signal mdout1_29_8: std_logic; - signal mdout1_28_8: std_logic; - signal mdout1_27_8: std_logic; - signal mdout1_26_8: std_logic; - signal mdout1_25_8: std_logic; - signal mdout1_24_8: std_logic; - signal mdout1_23_8: std_logic; - signal mdout1_22_8: std_logic; - signal mdout1_21_8: std_logic; - signal mdout1_20_8: std_logic; - signal mdout1_19_8: std_logic; - signal mdout1_18_8: std_logic; - signal mdout1_17_8: std_logic; - signal mdout1_16_8: std_logic; - signal mdout1_15_8: std_logic; - signal mdout1_14_8: std_logic; - signal mdout1_13_8: std_logic; - signal mdout1_12_8: std_logic; - signal mdout1_11_8: std_logic; - signal mdout1_10_8: std_logic; - signal mdout1_9_8: std_logic; - signal mdout1_8_8: std_logic; - signal mdout1_7_8: std_logic; - signal mdout1_6_8: std_logic; - signal mdout1_5_8: std_logic; - signal mdout1_4_8: std_logic; - signal mdout1_3_8: std_logic; - signal mdout1_2_8: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal wcount_r14: std_logic; - signal wcount_r15: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal rcount_w14: std_logic; - signal rcount_w15: std_logic; - signal wcount_14: std_logic; - signal wcount_15: std_logic; - signal co7_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX321 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; D4: in std_logic; D5: in std_logic; - D6: in std_logic; D7: in std_logic; D8: in std_logic; - D9: in std_logic; D10: in std_logic; D11: in std_logic; - D12: in std_logic; D13: in std_logic; D14: in std_logic; - D15: in std_logic; D16: in std_logic; D17: in std_logic; - D18: in std_logic; D19: in std_logic; D20: in std_logic; - D21: in std_logic; D22: in std_logic; D23: in std_logic; - D24: in std_logic; D25: in std_logic; D26: in std_logic; - D27: in std_logic; D28: in std_logic; D29: in std_logic; - D30: in std_logic; D31: in std_logic; SD1: in std_logic; - SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; - SD5: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; - attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; - attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; - attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; - attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; - attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; - attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; - attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; - attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; - attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; - attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; - attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; - attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; - attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; - attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; - attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; - attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; - attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; - attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; - attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; - attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; - attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; - attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; - attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; - attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; - attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; - attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; - attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; - attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; - attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; - attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; - attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t34: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_11: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t33: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_10: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t32: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t31: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t30: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t29: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t28: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t27: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t26: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t25: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t24: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t23: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t22: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t21: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t20: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t19: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t18: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t17: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t16: XOR2 - port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - INV_9: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_8: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_7: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_6: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - INV_5: INV - port map (A=>wptr_15, Z=>wptr_15_inv); - - LUT4_187: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet); - - LUT4_186: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_p00); - - INV_4: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_3: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_2: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_1: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - INV_0: INV - port map (A=>rptr_15, Z=>rptr_15_inv); - - LUT4_185: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_1); - - LUT4_184: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec1_r10); - - LUT4_183: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_2); - - LUT4_182: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec2_p01); - - LUT4_181: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_3); - - LUT4_180: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec3_r11); - - LUT4_179: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_4); - - LUT4_178: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec4_p02); - - LUT4_177: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_5); - - LUT4_176: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec5_r12); - - LUT4_175: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_6); - - LUT4_174: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec6_p03); - - LUT4_173: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_7); - - LUT4_172: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec7_r13); - - LUT4_171: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_8); - - LUT4_170: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec8_p04); - - LUT4_169: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_9); - - LUT4_168: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec9_r14); - - LUT4_167: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_10); - - LUT4_166: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - - LUT4_165: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_11); - - LUT4_164: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - - LUT4_163: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_12); - - LUT4_162: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - - LUT4_161: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_13); - - LUT4_160: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - - LUT4_159: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_14); - - LUT4_158: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - - LUT4_157: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_15); - - LUT4_156: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - - LUT4_155: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_16); - - LUT4_154: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - - LUT4_153: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_17); - - LUT4_152: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - - LUT4_151: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_18); - - LUT4_150: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - - LUT4_149: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_19); - - LUT4_148: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - - LUT4_147: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_20); - - LUT4_146: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - - LUT4_145: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_21); - - LUT4_144: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - - LUT4_143: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_22); - - LUT4_142: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - - LUT4_141: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_23); - - LUT4_140: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - - LUT4_139: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_24); - - LUT4_138: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - - LUT4_137: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_25); - - LUT4_136: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - - LUT4_135: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_26); - - LUT4_134: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - - LUT4_133: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_27); - - LUT4_132: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - - LUT4_131: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_28); - - LUT4_130: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - - LUT4_129: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_29); - - LUT4_128: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - - LUT4_127: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, - DO0=>func_and_inet_30); - - LUT4_126: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - - LUT4_125: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_31); - - LUT4_124: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - - LUT4_123: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_32); - - LUT4_122: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec32_p016); - - LUT4_121: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_33); - - LUT4_120: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec33_r116); - - LUT4_119: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_34); - - LUT4_118: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec34_p017); - - LUT4_117: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_35); - - LUT4_116: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec35_r117); - - LUT4_115: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_36); - - LUT4_114: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec36_p018); - - LUT4_113: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_37); - - LUT4_112: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec37_r118); - - LUT4_111: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_38); - - LUT4_110: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec38_p019); - - LUT4_109: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_39); - - LUT4_108: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec39_r119); - - LUT4_107: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_40); - - LUT4_106: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec40_p020); - - LUT4_105: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_41); - - LUT4_104: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec41_r120); - - LUT4_103: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_42); - - LUT4_102: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec42_p021); - - LUT4_101: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_43); - - LUT4_100: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec43_r121); - - LUT4_99: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_44); - - LUT4_98: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec44_p022); - - LUT4_97: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_45); - - LUT4_96: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec45_r122); - - LUT4_95: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_46); - - LUT4_94: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec46_p023); - - LUT4_93: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_47); - - LUT4_92: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec47_r123); - - LUT4_91: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_48); - - LUT4_90: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec48_p024); - - LUT4_89: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_49); - - LUT4_88: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec49_r124); - - LUT4_87: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_50); - - LUT4_86: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec50_p025); - - LUT4_85: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_51); - - LUT4_84: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec51_r125); - - LUT4_83: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_52); - - LUT4_82: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec52_p026); - - LUT4_81: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_53); - - LUT4_80: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec53_r126); - - LUT4_79: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_54); - - LUT4_78: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec54_p027); - - LUT4_77: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_55); - - LUT4_76: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec55_r127); - - LUT4_75: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_56); - - LUT4_74: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec56_p028); - - LUT4_73: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_57); - - LUT4_72: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec57_r128); - - LUT4_71: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_58); - - LUT4_70: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec58_p029); - - LUT4_69: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_59); - - LUT4_68: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec59_r129); - - LUT4_67: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_60); - - LUT4_66: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec60_p030); - - LUT4_65: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_61); - - LUT4_64: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec61_r130); - - LUT4_63: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, - DO0=>func_and_inet_62); - - LUT4_62: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec62_p031); - - LUT4_61: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_63); - - LUT4_60: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec63_r131); - - LUT4_59: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>w_gcount_r216, - DO0=>w_g2b_xor_cluster_0); - - LUT4_58: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_1); - - LUT4_57: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_2); - - LUT4_56: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_3); - - LUT4_55: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r15); - - LUT4_54: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, - AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_53: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, - DO0=>wcount_r10); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r3); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r2); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_10); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, - AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, - DO0=>func_xor_inet_11); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, - DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, - DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, - DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, - DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, - DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, - DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, - DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, - DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, - DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, - DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, - DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, - DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, - DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, - DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, - DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, - DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, - DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, - DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, - DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, - DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, - DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, - DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, - DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, - DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, - DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, - DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, - DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, - DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, - DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, - DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, - DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, - DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, - DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, - DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, - DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, - DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, - DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, - DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, - DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, - DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, - DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, - DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, - DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, - DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, - DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, - DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, - DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, - DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, - DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, - DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, - DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, - DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, - DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, - DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, - DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, - DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, - DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, - DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, - DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, - DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, - DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, - DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, - DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, - DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, - DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, - DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, - DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, - DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, - DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, - DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, - DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, - DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, - DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, - DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, - DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, - DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, - DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, - DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, - DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, - DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, - DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, - DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, - DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, - DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, - DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, - DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, - DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, - ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, - ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, - ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, - WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, - DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, - DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, - DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, - DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, - DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_176: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_175: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_174: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_173: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_172: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_171: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_170: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_169: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_168: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_167: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_166: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_165: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_164: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_163: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_162: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_161: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_160: FD1P3DX - port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_16); - - FF_159: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_158: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_157: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_156: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_155: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_154: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_153: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_152: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_151: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_150: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_149: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_148: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_147: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_146: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_145: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_144: FD1P3DX - port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_143: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_16); - - FF_142: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_141: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_140: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_139: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_138: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_137: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_136: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_135: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_134: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_133: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_132: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_131: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_130: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_129: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_128: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_127: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_126: FD1P3DX - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_16); - - FF_125: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_124: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_123: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_122: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_121: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_120: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_119: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_118: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_117: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_116: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_115: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_114: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_113: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_112: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_111: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_110: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_109: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_108: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_107: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_106: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_105: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_104: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_103: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_102: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_101: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_100: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_99: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_98: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_97: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_96: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_95: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_94: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_93: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_92: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_91: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_90: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_89: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_88: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_87: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_86: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_85: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_84: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_83: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_82: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_81: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_80: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_79: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_78: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_77: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_76: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_75: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_74: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_73: FD1P3DX - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_72: FD1P3DX - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_71: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_70: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_69: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_68: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_67: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_66: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_65: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_64: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_63: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_62: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_61: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_60: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_59: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_58: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_57: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_56: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_55: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_54: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_53: FD1S3DX - port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r16); - - FF_52: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_51: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_50: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_49: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_48: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_47: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_46: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_45: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_44: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_43: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_42: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_41: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_40: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_39: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_38: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_37: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_36: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_35: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_34: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_33: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_32: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_31: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_30: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_29: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_28: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_27: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_26: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_25: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_24: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_23: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_22: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_21: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_20: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_19: FD1S3DX - port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r216); - - FF_18: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - w_gctr_8: CU2 - port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>iwcount_16, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, - NC0=>ircount_16, NC1=>open); - - mux_8: MUX321 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, - D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, - D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, - D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, - D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, - D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(0)); - - mux_7: MUX321 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, - D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, - D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, - D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, - D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, - D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(1)); - - mux_6: MUX321 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, - D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, - D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, - D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, - D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, - D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(2)); - - mux_5: MUX321 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, - D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, - D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, - D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, - D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, - D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(3)); - - mux_4: MUX321 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, - D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, - D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, - D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, - D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, - D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(4)); - - mux_3: MUX321 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, - D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, - D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, - D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, - D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, - D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(5)); - - mux_2: MUX321 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, - D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, - D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, - D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, - D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, - D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(6)); - - mux_1: MUX321 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, - D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, - D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, - D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, - D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, - D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(7)); - - mux_0: MUX321 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, - D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, - D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, - D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, - D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, - D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, - B1=>wcount_r15, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, - B1=>rcount_w15, CI=>co6_3, GE=>co7_3); - - full_cmp_8: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_64kx9 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX321 use entity ecp3.MUX321(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9_generate.log b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9_generate.log deleted file mode 100644 index 6860ef8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:23:21 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_64kx9 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_64kx9.vhd - VHDL template : fifo_64kx9_tmpl.vhd - VHDL testbench : tb_fifo_64kx9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx9.srp - Estimated Resource Usage: - LUT : 379 - EBR : 32 - Reg : 177 - -END SCUBA Module Synthesis - -File: fifo_64kx9.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_64kx9_tmpl.vhd deleted file mode 100644 index a9d000b..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_64kx9_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:21 2011 - --- parameterized module component declaration -component fifo_64kx9 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_64kx9 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.lpc b/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.lpc deleted file mode 100644 index fc672fb..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_65536x18x9 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=05/19/2012 -Time=15:06:37 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=18 -RDepth=65536 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd b/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd deleted file mode 100644 index 9360064..0000000 --- a/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd +++ /dev/null @@ -1,4493 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) --- Module Version: 5.4 ---/opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Sat May 19 15:06:38 2012 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_65536x18x9 is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_65536x18x9; - -architecture Structure of fifo_65536x18x9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal func_and_inet: std_logic; - signal func_and_inet_1: std_logic; - signal func_and_inet_2: std_logic; - signal func_and_inet_3: std_logic; - signal func_and_inet_4: std_logic; - signal func_and_inet_5: std_logic; - signal func_and_inet_6: std_logic; - signal func_and_inet_7: std_logic; - signal func_and_inet_8: std_logic; - signal func_and_inet_9: std_logic; - signal func_and_inet_10: std_logic; - signal func_and_inet_11: std_logic; - signal func_and_inet_12: std_logic; - signal func_and_inet_13: std_logic; - signal func_and_inet_14: std_logic; - signal func_and_inet_15: std_logic; - signal func_and_inet_16: std_logic; - signal func_and_inet_17: std_logic; - signal func_and_inet_18: std_logic; - signal func_and_inet_19: std_logic; - signal func_and_inet_20: std_logic; - signal func_and_inet_21: std_logic; - signal func_and_inet_22: std_logic; - signal func_and_inet_23: std_logic; - signal func_and_inet_24: std_logic; - signal func_and_inet_25: std_logic; - signal func_and_inet_26: std_logic; - signal func_and_inet_27: std_logic; - signal func_and_inet_28: std_logic; - signal func_and_inet_29: std_logic; - signal wptr_14_inv: std_logic; - signal func_and_inet_30: std_logic; - signal rptr_15_inv: std_logic; - signal func_and_inet_31: std_logic; - signal func_and_inet_32: std_logic; - signal func_and_inet_33: std_logic; - signal func_and_inet_34: std_logic; - signal func_and_inet_35: std_logic; - signal func_and_inet_36: std_logic; - signal func_and_inet_37: std_logic; - signal func_and_inet_38: std_logic; - signal func_and_inet_39: std_logic; - signal func_and_inet_40: std_logic; - signal func_and_inet_41: std_logic; - signal func_and_inet_42: std_logic; - signal func_and_inet_43: std_logic; - signal func_and_inet_44: std_logic; - signal func_and_inet_45: std_logic; - signal wptr_13_inv: std_logic; - signal func_and_inet_46: std_logic; - signal rptr_14_inv: std_logic; - signal func_and_inet_47: std_logic; - signal func_and_inet_48: std_logic; - signal func_and_inet_49: std_logic; - signal func_and_inet_50: std_logic; - signal func_and_inet_51: std_logic; - signal func_and_inet_52: std_logic; - signal func_and_inet_53: std_logic; - signal wptr_12_inv: std_logic; - signal func_and_inet_54: std_logic; - signal rptr_13_inv: std_logic; - signal func_and_inet_55: std_logic; - signal func_and_inet_56: std_logic; - signal func_and_inet_57: std_logic; - signal wptr_11_inv: std_logic; - signal func_and_inet_58: std_logic; - signal rptr_12_inv: std_logic; - signal func_and_inet_59: std_logic; - signal wptr_10_inv: std_logic; - signal func_and_inet_60: std_logic; - signal rptr_11_inv: std_logic; - signal func_and_inet_61: std_logic; - signal func_and_inet_62: std_logic; - signal func_and_inet_63: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal rcount_w0: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal dec1_r10: std_logic; - signal dec0_p00: std_logic; - signal dec3_r11: std_logic; - signal dec2_p01: std_logic; - signal dec5_r12: std_logic; - signal dec4_p02: std_logic; - signal dec7_r13: std_logic; - signal dec6_p03: std_logic; - signal dec9_r14: std_logic; - signal dec8_p04: std_logic; - signal dec11_r15: std_logic; - signal dec10_p05: std_logic; - signal dec13_r16: std_logic; - signal dec12_p06: std_logic; - signal dec15_r17: std_logic; - signal dec14_p07: std_logic; - signal dec17_r18: std_logic; - signal dec16_p08: std_logic; - signal dec19_r19: std_logic; - signal dec18_p09: std_logic; - signal dec21_r110: std_logic; - signal dec20_p010: std_logic; - signal dec23_r111: std_logic; - signal dec22_p011: std_logic; - signal dec25_r112: std_logic; - signal dec24_p012: std_logic; - signal dec27_r113: std_logic; - signal dec26_p013: std_logic; - signal dec29_r114: std_logic; - signal dec28_p014: std_logic; - signal dec31_r115: std_logic; - signal dec30_p015: std_logic; - signal dec33_r116: std_logic; - signal dec32_p016: std_logic; - signal dec35_r117: std_logic; - signal dec34_p017: std_logic; - signal dec37_r118: std_logic; - signal dec36_p018: std_logic; - signal dec39_r119: std_logic; - signal dec38_p019: std_logic; - signal dec41_r120: std_logic; - signal dec40_p020: std_logic; - signal dec43_r121: std_logic; - signal dec42_p021: std_logic; - signal dec45_r122: std_logic; - signal dec44_p022: std_logic; - signal dec47_r123: std_logic; - signal dec46_p023: std_logic; - signal dec49_r124: std_logic; - signal dec48_p024: std_logic; - signal dec51_r125: std_logic; - signal dec50_p025: std_logic; - signal dec53_r126: std_logic; - signal dec52_p026: std_logic; - signal dec55_r127: std_logic; - signal dec54_p027: std_logic; - signal dec57_r128: std_logic; - signal dec56_p028: std_logic; - signal dec59_r129: std_logic; - signal dec58_p029: std_logic; - signal dec61_r130: std_logic; - signal dec60_p030: std_logic; - signal dec63_r131: std_logic; - signal dec62_p031: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wptr_15: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_16: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rptr_15: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co7: std_logic; - signal wcount_15: std_logic; - signal co6: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_31_0: std_logic; - signal mdout1_30_0: std_logic; - signal mdout1_29_0: std_logic; - signal mdout1_28_0: std_logic; - signal mdout1_27_0: std_logic; - signal mdout1_26_0: std_logic; - signal mdout1_25_0: std_logic; - signal mdout1_24_0: std_logic; - signal mdout1_23_0: std_logic; - signal mdout1_22_0: std_logic; - signal mdout1_21_0: std_logic; - signal mdout1_20_0: std_logic; - signal mdout1_19_0: std_logic; - signal mdout1_18_0: std_logic; - signal mdout1_17_0: std_logic; - signal mdout1_16_0: std_logic; - signal mdout1_15_0: std_logic; - signal mdout1_14_0: std_logic; - signal mdout1_13_0: std_logic; - signal mdout1_12_0: std_logic; - signal mdout1_11_0: std_logic; - signal mdout1_10_0: std_logic; - signal mdout1_9_0: std_logic; - signal mdout1_8_0: std_logic; - signal mdout1_7_0: std_logic; - signal mdout1_6_0: std_logic; - signal mdout1_5_0: std_logic; - signal mdout1_4_0: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_31_1: std_logic; - signal mdout1_30_1: std_logic; - signal mdout1_29_1: std_logic; - signal mdout1_28_1: std_logic; - signal mdout1_27_1: std_logic; - signal mdout1_26_1: std_logic; - signal mdout1_25_1: std_logic; - signal mdout1_24_1: std_logic; - signal mdout1_23_1: std_logic; - signal mdout1_22_1: std_logic; - signal mdout1_21_1: std_logic; - signal mdout1_20_1: std_logic; - signal mdout1_19_1: std_logic; - signal mdout1_18_1: std_logic; - signal mdout1_17_1: std_logic; - signal mdout1_16_1: std_logic; - signal mdout1_15_1: std_logic; - signal mdout1_14_1: std_logic; - signal mdout1_13_1: std_logic; - signal mdout1_12_1: std_logic; - signal mdout1_11_1: std_logic; - signal mdout1_10_1: std_logic; - signal mdout1_9_1: std_logic; - signal mdout1_8_1: std_logic; - signal mdout1_7_1: std_logic; - signal mdout1_6_1: std_logic; - signal mdout1_5_1: std_logic; - signal mdout1_4_1: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_31_2: std_logic; - signal mdout1_30_2: std_logic; - signal mdout1_29_2: std_logic; - signal mdout1_28_2: std_logic; - signal mdout1_27_2: std_logic; - signal mdout1_26_2: std_logic; - signal mdout1_25_2: std_logic; - signal mdout1_24_2: std_logic; - signal mdout1_23_2: std_logic; - signal mdout1_22_2: std_logic; - signal mdout1_21_2: std_logic; - signal mdout1_20_2: std_logic; - signal mdout1_19_2: std_logic; - signal mdout1_18_2: std_logic; - signal mdout1_17_2: std_logic; - signal mdout1_16_2: std_logic; - signal mdout1_15_2: std_logic; - signal mdout1_14_2: std_logic; - signal mdout1_13_2: std_logic; - signal mdout1_12_2: std_logic; - signal mdout1_11_2: std_logic; - signal mdout1_10_2: std_logic; - signal mdout1_9_2: std_logic; - signal mdout1_8_2: std_logic; - signal mdout1_7_2: std_logic; - signal mdout1_6_2: std_logic; - signal mdout1_5_2: std_logic; - signal mdout1_4_2: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_31_3: std_logic; - signal mdout1_30_3: std_logic; - signal mdout1_29_3: std_logic; - signal mdout1_28_3: std_logic; - signal mdout1_27_3: std_logic; - signal mdout1_26_3: std_logic; - signal mdout1_25_3: std_logic; - signal mdout1_24_3: std_logic; - signal mdout1_23_3: std_logic; - signal mdout1_22_3: std_logic; - signal mdout1_21_3: std_logic; - signal mdout1_20_3: std_logic; - signal mdout1_19_3: std_logic; - signal mdout1_18_3: std_logic; - signal mdout1_17_3: std_logic; - signal mdout1_16_3: std_logic; - signal mdout1_15_3: std_logic; - signal mdout1_14_3: std_logic; - signal mdout1_13_3: std_logic; - signal mdout1_12_3: std_logic; - signal mdout1_11_3: std_logic; - signal mdout1_10_3: std_logic; - signal mdout1_9_3: std_logic; - signal mdout1_8_3: std_logic; - signal mdout1_7_3: std_logic; - signal mdout1_6_3: std_logic; - signal mdout1_5_3: std_logic; - signal mdout1_4_3: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_31_4: std_logic; - signal mdout1_30_4: std_logic; - signal mdout1_29_4: std_logic; - signal mdout1_28_4: std_logic; - signal mdout1_27_4: std_logic; - signal mdout1_26_4: std_logic; - signal mdout1_25_4: std_logic; - signal mdout1_24_4: std_logic; - signal mdout1_23_4: std_logic; - signal mdout1_22_4: std_logic; - signal mdout1_21_4: std_logic; - signal mdout1_20_4: std_logic; - signal mdout1_19_4: std_logic; - signal mdout1_18_4: std_logic; - signal mdout1_17_4: std_logic; - signal mdout1_16_4: std_logic; - signal mdout1_15_4: std_logic; - signal mdout1_14_4: std_logic; - signal mdout1_13_4: std_logic; - signal mdout1_12_4: std_logic; - signal mdout1_11_4: std_logic; - signal mdout1_10_4: std_logic; - signal mdout1_9_4: std_logic; - signal mdout1_8_4: std_logic; - signal mdout1_7_4: std_logic; - signal mdout1_6_4: std_logic; - signal mdout1_5_4: std_logic; - signal mdout1_4_4: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_31_5: std_logic; - signal mdout1_30_5: std_logic; - signal mdout1_29_5: std_logic; - signal mdout1_28_5: std_logic; - signal mdout1_27_5: std_logic; - signal mdout1_26_5: std_logic; - signal mdout1_25_5: std_logic; - signal mdout1_24_5: std_logic; - signal mdout1_23_5: std_logic; - signal mdout1_22_5: std_logic; - signal mdout1_21_5: std_logic; - signal mdout1_20_5: std_logic; - signal mdout1_19_5: std_logic; - signal mdout1_18_5: std_logic; - signal mdout1_17_5: std_logic; - signal mdout1_16_5: std_logic; - signal mdout1_15_5: std_logic; - signal mdout1_14_5: std_logic; - signal mdout1_13_5: std_logic; - signal mdout1_12_5: std_logic; - signal mdout1_11_5: std_logic; - signal mdout1_10_5: std_logic; - signal mdout1_9_5: std_logic; - signal mdout1_8_5: std_logic; - signal mdout1_7_5: std_logic; - signal mdout1_6_5: std_logic; - signal mdout1_5_5: std_logic; - signal mdout1_4_5: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_31_6: std_logic; - signal mdout1_30_6: std_logic; - signal mdout1_29_6: std_logic; - signal mdout1_28_6: std_logic; - signal mdout1_27_6: std_logic; - signal mdout1_26_6: std_logic; - signal mdout1_25_6: std_logic; - signal mdout1_24_6: std_logic; - signal mdout1_23_6: std_logic; - signal mdout1_22_6: std_logic; - signal mdout1_21_6: std_logic; - signal mdout1_20_6: std_logic; - signal mdout1_19_6: std_logic; - signal mdout1_18_6: std_logic; - signal mdout1_17_6: std_logic; - signal mdout1_16_6: std_logic; - signal mdout1_15_6: std_logic; - signal mdout1_14_6: std_logic; - signal mdout1_13_6: std_logic; - signal mdout1_12_6: std_logic; - signal mdout1_11_6: std_logic; - signal mdout1_10_6: std_logic; - signal mdout1_9_6: std_logic; - signal mdout1_8_6: std_logic; - signal mdout1_7_6: std_logic; - signal mdout1_6_6: std_logic; - signal mdout1_5_6: std_logic; - signal mdout1_4_6: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_31_7: std_logic; - signal mdout1_30_7: std_logic; - signal mdout1_29_7: std_logic; - signal mdout1_28_7: std_logic; - signal mdout1_27_7: std_logic; - signal mdout1_26_7: std_logic; - signal mdout1_25_7: std_logic; - signal mdout1_24_7: std_logic; - signal mdout1_23_7: std_logic; - signal mdout1_22_7: std_logic; - signal mdout1_21_7: std_logic; - signal mdout1_20_7: std_logic; - signal mdout1_19_7: std_logic; - signal mdout1_18_7: std_logic; - signal mdout1_17_7: std_logic; - signal mdout1_16_7: std_logic; - signal mdout1_15_7: std_logic; - signal mdout1_14_7: std_logic; - signal mdout1_13_7: std_logic; - signal mdout1_12_7: std_logic; - signal mdout1_11_7: std_logic; - signal mdout1_10_7: std_logic; - signal mdout1_9_7: std_logic; - signal mdout1_8_7: std_logic; - signal mdout1_7_7: std_logic; - signal mdout1_6_7: std_logic; - signal mdout1_5_7: std_logic; - signal mdout1_4_7: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal rptr_13_ff: std_logic; - signal rptr_12_ff: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_31_8: std_logic; - signal mdout1_30_8: std_logic; - signal mdout1_29_8: std_logic; - signal mdout1_28_8: std_logic; - signal mdout1_27_8: std_logic; - signal mdout1_26_8: std_logic; - signal mdout1_25_8: std_logic; - signal mdout1_24_8: std_logic; - signal mdout1_23_8: std_logic; - signal mdout1_22_8: std_logic; - signal mdout1_21_8: std_logic; - signal mdout1_20_8: std_logic; - signal mdout1_19_8: std_logic; - signal mdout1_18_8: std_logic; - signal mdout1_17_8: std_logic; - signal mdout1_16_8: std_logic; - signal mdout1_15_8: std_logic; - signal mdout1_14_8: std_logic; - signal mdout1_13_8: std_logic; - signal mdout1_12_8: std_logic; - signal mdout1_11_8: std_logic; - signal mdout1_10_8: std_logic; - signal mdout1_9_8: std_logic; - signal mdout1_8_8: std_logic; - signal mdout1_7_8: std_logic; - signal mdout1_6_8: std_logic; - signal mdout1_5_8: std_logic; - signal mdout1_4_8: std_logic; - signal mdout1_3_8: std_logic; - signal mdout1_2_8: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r7: std_logic; - signal wcount_r8: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r11: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal wcount_r13: std_logic; - signal wcount_r14: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w7: std_logic; - signal rcount_w8: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w9: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w11: std_logic; - signal rcount_w12: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w14: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal rcount_w15: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_14: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX321 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; D4: in std_logic; D5: in std_logic; - D6: in std_logic; D7: in std_logic; D8: in std_logic; - D9: in std_logic; D10: in std_logic; D11: in std_logic; - D12: in std_logic; D13: in std_logic; D14: in std_logic; - D15: in std_logic; D16: in std_logic; D17: in std_logic; - D18: in std_logic; D19: in std_logic; D20: in std_logic; - D21: in std_logic; D22: in std_logic; D23: in std_logic; - D24: in std_logic; D25: in std_logic; D26: in std_logic; - D27: in std_logic; D28: in std_logic; D29: in std_logic; - D30: in std_logic; D31: in std_logic; SD1: in std_logic; - SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; - SD5: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; - attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; - attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; - attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; - attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; - attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; - attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; - attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; - attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; - attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; - attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; - attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; - attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; - attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; - attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; - attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; - attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; - attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; - attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; - attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; - attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; - attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; - attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; - attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; - attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; - attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; - attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; - attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; - attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; - attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; - attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_65536x18x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; - attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t33: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_11: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t32: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_10: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t31: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t30: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t29: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t28: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t27: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t26: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t25: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t24: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t23: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t22: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t21: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t20: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t19: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t18: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t17: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t16: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - INV_9: INV - port map (A=>wptr_10, Z=>wptr_10_inv); - - INV_8: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_7: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_6: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_5: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - LUT4_180: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet); - - LUT4_179: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_p00); - - INV_4: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_3: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_2: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_1: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - INV_0: INV - port map (A=>rptr_15, Z=>rptr_15_inv); - - LUT4_178: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_1); - - LUT4_177: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec1_r10); - - LUT4_176: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_2); - - LUT4_175: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec2_p01); - - LUT4_174: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_3); - - LUT4_173: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec3_r11); - - LUT4_172: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_4); - - LUT4_171: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec4_p02); - - LUT4_170: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_5); - - LUT4_169: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec5_r12); - - LUT4_168: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_6); - - LUT4_167: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec6_p03); - - LUT4_166: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_7); - - LUT4_165: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec7_r13); - - LUT4_164: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_8); - - LUT4_163: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec8_p04); - - LUT4_162: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_9); - - LUT4_161: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec9_r14); - - LUT4_160: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_10); - - LUT4_159: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - - LUT4_158: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_11); - - LUT4_157: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - - LUT4_156: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_12); - - LUT4_155: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - - LUT4_154: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_13); - - LUT4_153: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - - LUT4_152: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_14); - - LUT4_151: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - - LUT4_150: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_15); - - LUT4_149: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - - LUT4_148: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_16); - - LUT4_147: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - - LUT4_146: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_17); - - LUT4_145: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - - LUT4_144: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_18); - - LUT4_143: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - - LUT4_142: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_19); - - LUT4_141: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - - LUT4_140: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_20); - - LUT4_139: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - - LUT4_138: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_21); - - LUT4_137: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - - LUT4_136: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_22); - - LUT4_135: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - - LUT4_134: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_23); - - LUT4_133: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - - LUT4_132: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_24); - - LUT4_131: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - - LUT4_130: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_25); - - LUT4_129: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - - LUT4_128: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_26); - - LUT4_127: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - - LUT4_126: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_27); - - LUT4_125: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - - LUT4_124: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_28); - - LUT4_123: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - - LUT4_122: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_29); - - LUT4_121: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - - LUT4_120: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_30); - - LUT4_119: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - - LUT4_118: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_31); - - LUT4_117: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - - LUT4_116: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_32); - - LUT4_115: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec32_p016); - - LUT4_114: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_33); - - LUT4_113: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec33_r116); - - LUT4_112: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_34); - - LUT4_111: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec34_p017); - - LUT4_110: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_35); - - LUT4_109: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec35_r117); - - LUT4_108: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_36); - - LUT4_107: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec36_p018); - - LUT4_106: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_37); - - LUT4_105: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec37_r118); - - LUT4_104: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_38); - - LUT4_103: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec38_p019); - - LUT4_102: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_39); - - LUT4_101: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec39_r119); - - LUT4_100: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_40); - - LUT4_99: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec40_p020); - - LUT4_98: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_41); - - LUT4_97: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec41_r120); - - LUT4_96: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_42); - - LUT4_95: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec42_p021); - - LUT4_94: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_43); - - LUT4_93: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec43_r121); - - LUT4_92: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_44); - - LUT4_91: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec44_p022); - - LUT4_90: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_45); - - LUT4_89: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec45_r122); - - LUT4_88: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_46); - - LUT4_87: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec46_p023); - - LUT4_86: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_47); - - LUT4_85: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec47_r123); - - LUT4_84: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_48); - - LUT4_83: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec48_p024); - - LUT4_82: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_49); - - LUT4_81: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec49_r124); - - LUT4_80: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_50); - - LUT4_79: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec50_p025); - - LUT4_78: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_51); - - LUT4_77: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec51_r125); - - LUT4_76: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_52); - - LUT4_75: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec52_p026); - - LUT4_74: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_53); - - LUT4_73: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec53_r126); - - LUT4_72: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_54); - - LUT4_71: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec54_p027); - - LUT4_70: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_55); - - LUT4_69: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec55_r127); - - LUT4_68: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_56); - - LUT4_67: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec56_p028); - - LUT4_66: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_57); - - LUT4_65: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec57_r128); - - LUT4_64: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_58); - - LUT4_63: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec58_p029); - - LUT4_62: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_59); - - LUT4_61: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec59_r129); - - LUT4_60: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_60); - - LUT4_59: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec60_p030); - - LUT4_58: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_61); - - LUT4_57: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec61_r130); - - LUT4_56: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_62); - - LUT4_55: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec62_p031); - - LUT4_54: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_63); - - LUT4_53: ROM16X1A - generic map (initval=> X"8000") - port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec63_r131); - - LUT4_52: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_51: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_50: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_49: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_48: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_47: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_46: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_45: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_44: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_43: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_42: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_41: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_40: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_39: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_38: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_37: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_36: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_35: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_34: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_33: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_32: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_31: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, - DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, - DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, - DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, - DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, - DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, - DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, - DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, - DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, - DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, - DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, - DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, - DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, - DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, - DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, - DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, - DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, - DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, - DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, - DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, - DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, - DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, - DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, - DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, - DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, - DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, - DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, - DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, - DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, - DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, - DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, - DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, - DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, - DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, - DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, - DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, - DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, - DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, - DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, - DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, - DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, - DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, - DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, - DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, - DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, - DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, - DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, - DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, - DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, - DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, - DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, - DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, - DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, - DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, - DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, - DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, - DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, - DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, - DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, - DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, - DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, - DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, - DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, - DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, - DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, - DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, - DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, - DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, - DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, - DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, - DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, - DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, - DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, - DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, - DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, - DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, - DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, - DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, - DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, - DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, - DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, - DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, - DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, - DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, - DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, - DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, - DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, - DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, - DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, - DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, - DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, - DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, - DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, - DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KC - generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, - DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, - DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, - DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_171: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_170: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_169: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_168: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_167: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_166: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_165: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_164: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_163: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_162: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_161: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_160: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_159: FD1P3DX - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_158: FD1P3DX - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_157: FD1P3DX - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_156: FD1P3DX - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_155: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_154: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_153: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_152: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_151: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_150: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_149: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_148: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_147: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_146: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_145: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_144: FD1P3DX - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_143: FD1P3DX - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_142: FD1P3DX - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_141: FD1P3DX - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_140: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_139: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_138: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_137: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_136: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_135: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_134: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_133: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_132: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_131: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_130: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_129: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_128: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_127: FD1P3DX - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_126: FD1P3DX - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_125: FD1P3DX - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_124: FD1P3DX - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_123: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_122: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_121: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_120: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_119: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_118: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_117: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_116: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_115: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_114: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_113: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_112: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_111: FD1P3DX - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_110: FD1P3DX - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_109: FD1P3DX - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_108: FD1P3DX - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_107: FD1P3DX - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_106: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_105: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_104: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_103: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_102: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_101: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_100: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_99: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_98: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_97: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_96: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_95: FD1P3DX - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_94: FD1P3DX - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_93: FD1P3DX - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_92: FD1P3DX - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_91: FD1P3DX - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_90: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_89: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_88: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_87: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_86: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_85: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_84: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_83: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_82: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_81: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_80: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_79: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_78: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_77: FD1P3DX - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_76: FD1P3DX - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_75: FD1P3DX - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_74: FD1P3DX - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_73: FD1P3DX - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_72: FD1P3DX - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_71: FD1P3DX - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_70: FD1P3DX - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_69: FD1P3DX - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_68: FD1P3DX - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_67: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_66: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_65: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_64: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_63: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_62: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_61: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_60: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_59: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_58: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_57: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_56: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_55: FD1S3DX - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_54: FD1S3DX - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_53: FD1S3DX - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_52: FD1S3DX - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_51: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_50: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_49: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_48: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_47: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_46: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_45: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_44: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_43: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_42: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_41: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_40: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_39: FD1S3DX - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_38: FD1S3DX - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_37: FD1S3DX - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_36: FD1S3DX - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_35: FD1S3DX - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_34: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_33: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_32: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_31: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_30: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_29: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_28: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_27: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_26: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_25: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_24: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_23: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_22: FD1S3DX - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_21: FD1S3DX - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_20: FD1S3DX - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_19: FD1S3DX - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_18: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>ircount_16, NC1=>open); - - mux_8: MUX321 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, - D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, - D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, - D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, - D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, - D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(0)); - - mux_7: MUX321 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, - D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, - D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, - D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, - D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, - D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(1)); - - mux_6: MUX321 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, - D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, - D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, - D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, - D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, - D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(2)); - - mux_5: MUX321 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, - D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, - D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, - D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, - D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, - D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(3)); - - mux_4: MUX321 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, - D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, - D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, - D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, - D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, - D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(4)); - - mux_3: MUX321 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, - D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, - D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, - D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, - D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, - D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(5)); - - mux_2: MUX321 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, - D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, - D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, - D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, - D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, - D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(6)); - - mux_1: MUX321 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, - D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, - D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, - D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, - D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, - D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(7)); - - mux_0: MUX321 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, - D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, - D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, - D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, - D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, - D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>wcount_r8, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, - B1=>wcount_r14, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, - B1=>rcount_w12, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w14, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, - B1=>full_cmp_clr, CI=>co6_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_65536x18x9 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:MUX321 use entity ecp3.MUX321(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.ipx b/gbe2_ecp3/ipcores_ecp3/ip_mem.ipx deleted file mode 100644 index 27e3da4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.ipx +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.jhd b/gbe2_ecp3/ipcores_ecp3/ip_mem.jhd deleted file mode 100755 index e666bec..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.jhd +++ /dev/null @@ -1,9 +0,0 @@ -MODULE ip_mem DEFIN ip_mem.vhd - SUBMODULE DP16KC - INSTANCE ip_mem_0_1_0 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE VHI - INSTANCE scuba_vhi_inst - SUBMODULE DP16KC - INSTANCE ip_mem_0_0_1 diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.lpc b/gbe2_ecp3/ipcores_ecp3/ip_mem.lpc deleted file mode 100755 index 4c9ab25..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.lpc +++ /dev/null @@ -1,60 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=RAM_DP_TRUE -CoreRevision=7.1 -ModuleName=ip_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:37 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -AAddress=256 -BAddress=256 -AData=32 -BData=32 -enByte=0 -ByteSize=9 -AadPipeline=0 -BadPipeline=0 -AinPipeline=0 -BinPipeline=0 -AoutPipeline=0 -BoutPipeline=1 -AMOR=0 -BMOR=0 -AInData=Registered -BInData=Registered -AAdControl=Registered -BAdControl=Registered -MemFile=ip_mem.mem -MemFormat=orca -Reset=Sync -GSR=Enabled -WriteA=Normal -WriteB=Normal -Pad=0 -EnECC=0 -Optimization=Speed -Pipeline=0 - -[FilesGenerated] -ip_mem.mem=mem diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.mem b/gbe2_ecp3/ipcores_ecp3/ip_mem.mem deleted file mode 100755 index 836ca91..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.mem +++ /dev/null @@ -1,277 +0,0 @@ -#Format=Address-Hex -#Depth=256 -#DataWidth=32 -#AddrRadix=3 -#DataRadix=3 - -00: 214397e9 -01: 0000001b -02: c0a80002 -03: 0000c350 -04: 023bdc00 -05: 00000013 -06: c0a80005 -07: 0000c350 -08: 00000578 -09: 00000000 -0a: 00000000 -0b: 00000000 -0c: 00000000 -0d: 00000000 -0e: 00000000 -0f: 00000000 - -10: 214397e9 -11: 0000001b -12: c0a80002 -13: 0000c351 -14: 023bdc01 -15: 00000013 -16: c0a80006 -17: 0000c350 -18: 00000578 -19: 00000000 -1a: 00000000 -1b: 00000000 -1c: 00000000 -1d: 00000000 -1e: 00000000 -1f: 00000000 - -20: 214397e9 -21: 0000001b -22: c0a80002 -23: 0000c352 -24: 023bdc02 -25: 00000013 -26: c0a80007 -27: 0000c350 -28: 00000578 -29: 00000000 -2a: 00000000 -2b: 00000000 -2c: 00000000 -2d: 00000000 -2e: 00000000 -2f: 00000000 - -30: 214397e9 -31: 0000001b -32: c0a80002 -33: 0000c353 -34: 023bdc03 -35: 00000013 -36: c0a80008 -37: 0000c350 -38: 00000578 -39: 00000000 -3a: 00000000 -3b: 00000000 -3c: 00000000 -3d: 00000000 -3e: 00000000 -3f: 00000000 - -40: 00000000 -41: 00000000 -42: 00000000 -43: 00000000 -44: 00000000 -45: 00000000 -46: 00000000 -47: 00000000 -48: 00000578 -49: 00000000 -4a: 00000000 -4b: 00000000 -4c: 00000000 -4d: 00000000 -4e: 00000000 -4f: 00000000 - -50: 00000000 -51: 00000000 -52: 00000000 -53: 00000000 -54: 00000000 -55: 00000000 -56: 00000000 -57: 00000000 -58: 00000578 -59: 00000000 -5a: 00000000 -5b: 00000000 -5c: 00000000 -5d: 00000000 -5e: 00000000 -5f: 00000000 - -60: 00000000 -61: 00000000 -62: 00000000 -63: 00000000 -64: 00000000 -65: 00000000 -66: 00000000 -67: 00000000 -68: 00000578 -69: 00000000 -6a: 00000000 -6b: 00000000 -6c: 00000000 -6d: 00000000 -6e: 00000000 -6f: 00000000 - -70: 00000000 -71: 00000000 -72: 00000000 -73: 00000000 -74: 00000000 -75: 00000000 -76: 00000000 -77: 00000000 -78: 00000578 -79: 00000000 -7a: 00000000 -7b: 00000000 -7c: 00000000 -7d: 00000000 -7e: 00000000 -7f: 00000000 - -80: 00000000 -81: 00000000 -82: 00000000 -83: 00000000 -84: 00000000 -85: 00000000 -86: 00000000 -87: 00000000 -88: 00000578 -89: 00000000 -8a: 00000000 -8b: 00000000 -8c: 00000000 -8d: 00000000 -8e: 00000000 -8f: 00000000 - -90: 00000000 -91: 00000000 -92: 00000000 -93: 00000000 -94: 00000000 -95: 00000000 -96: 00000000 -97: 00000000 -98: 00000578 -99: 00000000 -9a: 00000000 -9b: 00000000 -9c: 00000000 -9d: 00000000 -9e: 00000000 -9f: 00000000 - -a0: 00000000 -a1: 00000000 -a2: 00000000 -a3: 00000000 -a4: 00000000 -a5: 00000000 -a6: 00000000 -a7: 00000000 -a8: 00000578 -a9: 00000000 -aa: 00000000 -ab: 00000000 -ac: 00000000 -ad: 00000000 -ae: 00000000 -af: 00000000 - -b0: 00000000 -b1: 00000000 -b2: 00000000 -b3: 00000000 -b4: 00000000 -b5: 00000000 -b6: 00000000 -b7: 00000000 -b8: 00000578 -b9: 00000000 -ba: 00000000 -bb: 00000000 -bc: 00000000 -bd: 00000000 -be: 00000000 -bf: 00000000 - -c0: 00000000 -c1: 00000000 -c2: 00000000 -c3: 00000000 -c4: 00000000 -c5: 00000000 -c6: 00000000 -c7: 00000000 -c8: 00000578 -c9: 00000000 -ca: 00000000 -cb: 00000000 -cc: 00000000 -cd: 00000000 -ce: 00000000 -cf: 00000000 - -d0: 00000000 -d1: 00000000 -d2: 00000000 -d3: 00000000 -d4: 00000000 -d5: 00000000 -d6: 00000000 -d7: 00000000 -d8: 00000578 -d9: 00000000 -da: 00000000 -db: 00000000 -dc: 00000000 -dd: 00000000 -de: 00000000 -df: 00000000 - -e0: 00000000 -e1: 00000000 -e2: 00000000 -e3: 00000000 -e4: 00000000 -e5: 00000000 -e6: 00000000 -e7: 00000000 -e8: 00000578 -e9: 00000000 -ea: 00000000 -eb: 00000000 -ec: 00000000 -ed: 00000000 -ee: 00000000 -ef: 00000000 - -f0: 00000000 -f1: 00000000 -f2: 00000000 -f3: 00000000 -f4: 00000000 -f5: 00000000 -f6: 00000000 -f7: 00000000 -f8: 00000578 -f9: 00000000 -fa: 00000000 -fb: 00000000 -fc: 00000000 -fd: 00000000 -fe: 00000000 -ff: 00000000 diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.mem.bak b/gbe2_ecp3/ipcores_ecp3/ip_mem.mem.bak deleted file mode 100755 index 9810f31..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.mem.bak +++ /dev/null @@ -1,277 +0,0 @@ -#Format=Address-Hex -#Depth=256 -#DataWidth=32 -#AddrRadix=3 -#DataRadix=3 - -00: 00006cf0 -01: 4902d745 -02: c0a80002 -03: 0000c350 -04: 0000eeee -05: eeeeeeee -06: c0a80005 -07: 0000c350 -08: 00000578 -09: 00000000 -0a: 00000000 -0b: 00000000 -0c: 00000000 -0d: 00000000 -0e: 00000000 -0f: 00000000 - -10: 00000000 -11: 00000000 -12: 00000000 -13: 00000000 -14: 00000000 -15: 00000000 -16: 00000000 -17: 00000000 -18: 00000578 -19: 00000000 -1a: 00000000 -1b: 00000000 -1c: 00000000 -1d: 00000000 -1e: 00000000 -1f: 00000000 - -20: 00000000 -21: 00000000 -22: 00000000 -23: 00000000 -24: 00000000 -25: 00000000 -26: 00000000 -27: 00000000 -28: 00000578 -29: 00000000 -2a: 00000000 -2b: 00000000 -2c: 00000000 -2d: 00000000 -2e: 00000000 -2f: 00000000 - -30: 00000000 -31: 00000000 -32: 00000000 -33: 00000000 -34: 00000000 -35: 00000000 -36: 00000000 -37: 00000000 -38: 00000578 -39: 00000000 -3a: 00000000 -3b: 00000000 -3c: 00000000 -3d: 00000000 -3e: 00000000 -3f: 00000000 - -40: 00000000 -41: 00000000 -42: 00000000 -43: 00000000 -44: 00000000 -45: 00000000 -46: 00000000 -47: 00000000 -48: 00000578 -49: 00000000 -4a: 00000000 -4b: 00000000 -4c: 00000000 -4d: 00000000 -4e: 00000000 -4f: 00000000 - -50: 00000000 -51: 00000000 -52: 00000000 -53: 00000000 -54: 00000000 -55: 00000000 -56: 00000000 -57: 00000000 -58: 00000578 -59: 00000000 -5a: 00000000 -5b: 00000000 -5c: 00000000 -5d: 00000000 -5e: 00000000 -5f: 00000000 - -60: 00000000 -61: 00000000 -62: 00000000 -63: 00000000 -64: 00000000 -65: 00000000 -66: 00000000 -67: 00000000 -68: 00000578 -69: 00000000 -6a: 00000000 -6b: 00000000 -6c: 00000000 -6d: 00000000 -6e: 00000000 -6f: 00000000 - -70: 00000000 -71: 00000000 -72: 00000000 -73: 00000000 -74: 00000000 -75: 00000000 -76: 00000000 -77: 00000000 -78: 00000578 -79: 00000000 -7a: 00000000 -7b: 00000000 -7c: 00000000 -7d: 00000000 -7e: 00000000 -7f: 00000000 - -80: 00000000 -81: 00000000 -82: 00000000 -83: 00000000 -84: 00000000 -85: 00000000 -86: 00000000 -87: 00000000 -88: 00000578 -89: 00000000 -8a: 00000000 -8b: 00000000 -8c: 00000000 -8d: 00000000 -8e: 00000000 -8f: 00000000 - -90: 00000000 -91: 00000000 -92: 00000000 -93: 00000000 -94: 00000000 -95: 00000000 -96: 00000000 -97: 00000000 -98: 00000578 -99: 00000000 -9a: 00000000 -9b: 00000000 -9c: 00000000 -9d: 00000000 -9e: 00000000 -9f: 00000000 - -a0: 00000000 -a1: 00000000 -a2: 00000000 -a3: 00000000 -a4: 00000000 -a5: 00000000 -a6: 00000000 -a7: 00000000 -a8: 00000578 -a9: 00000000 -aa: 00000000 -ab: 00000000 -ac: 00000000 -ad: 00000000 -ae: 00000000 -af: 00000000 - -b0: 00000000 -b1: 00000000 -b2: 00000000 -b3: 00000000 -b4: 00000000 -b5: 00000000 -b6: 00000000 -b7: 00000000 -b8: 00000578 -b9: 00000000 -ba: 00000000 -bb: 00000000 -bc: 00000000 -bd: 00000000 -be: 00000000 -bf: 00000000 - -c0: 00000000 -c1: 00000000 -c2: 00000000 -c3: 00000000 -c4: 00000000 -c5: 00000000 -c6: 00000000 -c7: 00000000 -c8: 00000578 -c9: 00000000 -ca: 00000000 -cb: 00000000 -cc: 00000000 -cd: 00000000 -ce: 00000000 -cf: 00000000 - -d0: 00000000 -d1: 00000000 -d2: 00000000 -d3: 00000000 -d4: 00000000 -d5: 00000000 -d6: 00000000 -d7: 00000000 -d8: 00000578 -d9: 00000000 -da: 00000000 -db: 00000000 -dc: 00000000 -dd: 00000000 -de: 00000000 -df: 00000000 - -e0: 00000000 -e1: 00000000 -e2: 00000000 -e3: 00000000 -e4: 00000000 -e5: 00000000 -e6: 00000000 -e7: 00000000 -e8: 00000578 -e9: 00000000 -ea: 00000000 -eb: 00000000 -ec: 00000000 -ed: 00000000 -ee: 00000000 -ef: 00000000 - -f0: 00000000 -f1: 00000000 -f2: 00000000 -f3: 00000000 -f4: 00000000 -f5: 00000000 -f6: 00000000 -f7: 00000000 -f8: 00000578 -f9: 00000000 -fa: 00000000 -fb: 00000000 -fc: 00000000 -fd: 00000000 -fe: 00000000 -ff: 00000000 diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.naf b/gbe2_ecp3/ipcores_ecp3/ip_mem.naf deleted file mode 100755 index 11b52d7..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.naf +++ /dev/null @@ -1,152 +0,0 @@ -DataInA[31] i -DataInA[30] i -DataInA[29] i -DataInA[28] i -DataInA[27] i -DataInA[26] i -DataInA[25] i -DataInA[24] i -DataInA[23] i -DataInA[22] i -DataInA[21] i -DataInA[20] i -DataInA[19] i -DataInA[18] i -DataInA[17] i -DataInA[16] i -DataInA[15] i -DataInA[14] i -DataInA[13] i -DataInA[12] i -DataInA[11] i -DataInA[10] i -DataInA[9] i -DataInA[8] i -DataInA[7] i -DataInA[6] i -DataInA[5] i -DataInA[4] i -DataInA[3] i -DataInA[2] i -DataInA[1] i -DataInA[0] i -DataInB[31] i -DataInB[30] i -DataInB[29] i -DataInB[28] i -DataInB[27] i -DataInB[26] i -DataInB[25] i -DataInB[24] i -DataInB[23] i -DataInB[22] i -DataInB[21] i -DataInB[20] i -DataInB[19] i -DataInB[18] i -DataInB[17] i -DataInB[16] i -DataInB[15] i -DataInB[14] i -DataInB[13] i -DataInB[12] i -DataInB[11] i -DataInB[10] i -DataInB[9] i -DataInB[8] i -DataInB[7] i -DataInB[6] i -DataInB[5] i -DataInB[4] i -DataInB[3] i -DataInB[2] i -DataInB[1] i -DataInB[0] i -AddressA[7] i -AddressA[6] i -AddressA[5] i -AddressA[4] i -AddressA[3] i -AddressA[2] i -AddressA[1] i -AddressA[0] i -AddressB[7] i -AddressB[6] i -AddressB[5] i -AddressB[4] i -AddressB[3] i -AddressB[2] i -AddressB[1] i -AddressB[0] i -ClockA i -ClockB i -ClockEnA i -ClockEnB i -WrA i -WrB i -ResetA i -ResetB i -QA[31] o -QA[30] o -QA[29] o -QA[28] o -QA[27] o -QA[26] o -QA[25] o -QA[24] o -QA[23] o -QA[22] o -QA[21] o -QA[20] o -QA[19] o -QA[18] o -QA[17] o -QA[16] o -QA[15] o -QA[14] o -QA[13] o -QA[12] o -QA[11] o -QA[10] o -QA[9] o -QA[8] o -QA[7] o -QA[6] o -QA[5] o -QA[4] o -QA[3] o -QA[2] o -QA[1] o -QA[0] o -QB[31] o -QB[30] o -QB[29] o -QB[28] o -QB[27] o -QB[26] o -QB[25] o -QB[24] o -QB[23] o -QB[22] o -QB[21] o -QB[20] o -QB[19] o -QB[18] o -QB[17] o -QB[16] o -QB[15] o -QB[14] o -QB[13] o -QB[12] o -QB[11] o -QB[10] o -QB[9] o -QB[8] o -QB[7] o -QB[6] o -QB[5] o -QB[4] o -QB[3] o -QB[2] o -QB[1] o -QB[0] o diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.sort b/gbe2_ecp3/ipcores_ecp3/ip_mem.sort deleted file mode 100644 index d965f9c..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.sort +++ /dev/null @@ -1 +0,0 @@ -ip_mem.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.srp b/gbe2_ecp3/ipcores_ecp3/ip_mem.srp deleted file mode 100755 index edd5574..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.srp +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:37 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ramdp -device LFE3-150EA -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e - Circuit name : ip_mem - Module type : RAM_DP_TRUE - Module Version : 7.1 - Ports : - Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB - Outputs : QA[31:0], QB[31:0] - I/O buffer : not inserted - Memory file : ip_mem.mem - EDIF output : suppressed - VHDL output : ip_mem.vhd - VHDL template : ip_mem_tmpl.vhd - VHDL testbench : tb_ip_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : ip_mem.srp - Element Usage : - DP16KC : 2 - Estimated Resource Usage: - EBR : 2 diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.sym b/gbe2_ecp3/ipcores_ecp3/ip_mem.sym deleted file mode 100644 index 2ef039abfce77024479453feee2ddeaf61914ea5..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 588 zcmY+Cze~eV6ov13Eu|F;9UMA11nD51A{GScki@ni2>zf_p^8)+L9{ir9UL4wI5&sB%TbxmoG5EEGI11TiM8{K<1<_2nsy79|E(i(PwU|} zvPoTAZnOHCet^em&-#GglGn(mOO0M*y=~W*m%^S#%=+>%l{vqe;zVP7MOk9U?Ycdl zlBLb4S?CEP%QNz{J{BSyt95KC(gY~{8AtYED$b8wr3y)IPg-CHh;8mxx$`b@!n_ye zlQ#b4bBR;$u;sSGIkS9QnOPPYDdPbtc4g67@HLA*?FDRuiNW=zc?^S7y=xB00X{YR zWFI5V1M&dhnmw|Icz7B776w;Fvq?5FuTu0v7A$HWiorjipt(=(i>28jTOu;UJ?zL* EKQOyppa1{> diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd b/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd deleted file mode 100755 index 5b2e06e..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd +++ /dev/null @@ -1,379 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 7.1 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e - --- Thu Sep 22 11:24:37 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity ip_mem is - port ( - DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(31 downto 0); - AddressA: in std_logic_vector(7 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(31 downto 0)); -end ip_mem; - -architecture Structure of ip_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP16KC - generic (INITVAL_3F : in String; INITVAL_3E : in String; - INITVAL_3D : in String; INITVAL_3C : in String; - INITVAL_3B : in String; INITVAL_3A : in String; - INITVAL_39 : in String; INITVAL_38 : in String; - INITVAL_37 : in String; INITVAL_36 : in String; - INITVAL_35 : in String; INITVAL_34 : in String; - INITVAL_33 : in String; INITVAL_32 : in String; - INITVAL_31 : in String; INITVAL_30 : in String; - INITVAL_2F : in String; INITVAL_2E : in String; - INITVAL_2D : in String; INITVAL_2C : in String; - INITVAL_2B : in String; INITVAL_2A : in String; - INITVAL_29 : in String; INITVAL_28 : in String; - INITVAL_27 : in String; INITVAL_26 : in String; - INITVAL_25 : in String; INITVAL_24 : in String; - INITVAL_23 : in String; INITVAL_22 : in String; - INITVAL_21 : in String; INITVAL_20 : in String; - INITVAL_1F : in String; INITVAL_1E : in String; - INITVAL_1D : in String; INITVAL_1C : in String; - INITVAL_1B : in String; INITVAL_1A : in String; - INITVAL_19 : in String; INITVAL_18 : in String; - INITVAL_17 : in String; INITVAL_16 : in String; - INITVAL_15 : in String; INITVAL_14 : in String; - INITVAL_13 : in String; INITVAL_12 : in String; - INITVAL_11 : in String; INITVAL_10 : in String; - INITVAL_0F : in String; INITVAL_0E : in String; - INITVAL_0D : in String; INITVAL_0C : in String; - INITVAL_0B : in String; INITVAL_0A : in String; - INITVAL_09 : in String; INITVAL_08 : in String; - INITVAL_07 : in String; INITVAL_06 : in String; - INITVAL_05 : in String; INITVAL_04 : in String; - INITVAL_03 : in String; INITVAL_02 : in String; - INITVAL_01 : in String; INITVAL_00 : in String; - GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; - attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; - attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; - attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; - attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC"; - -begin - -- component instantiation statements - ip_mem_0_0_1: DP16KC - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9", - INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", - INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", - INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", - CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", - REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) - port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), - DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), - DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), - DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11), - DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14), - DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17), - ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, - ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), - ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), - ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, - CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, - DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2), - DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5), - DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8), - DIB9=>DataInB(9), DIB10=>DataInB(10), DIB11=>DataInB(11), - DIB12=>DataInB(12), DIB13=>DataInB(13), DIB14=>DataInB(14), - DIB15=>DataInB(15), DIB16=>DataInB(16), DIB17=>DataInB(17), - ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1), - ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4), - ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7), - ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB, - CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0), - DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4), - DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8), - DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12), - DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16), - DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2), - DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6), - DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10), - DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14), - DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17)); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - ip_mem_0_1_0: DP16KC - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", - REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) - port map (DIA0=>DataInA(18), DIA1=>DataInA(19), - DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22), - DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25), - DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28), - DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31), - DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo, - DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0), - ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3), - ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6), - ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>ClockEnA, CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>ResetA, DIB0=>DataInB(18), DIB1=>DataInB(19), - DIB2=>DataInB(20), DIB3=>DataInB(21), DIB4=>DataInB(22), - DIB5=>DataInB(23), DIB6=>DataInB(24), DIB7=>DataInB(25), - DIB8=>DataInB(26), DIB9=>DataInB(27), DIB10=>DataInB(28), - DIB11=>DataInB(29), DIB12=>DataInB(30), DIB13=>DataInB(31), - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vhi, ADB1=>scuba_vhi, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>AddressB(0), - ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3), - ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6), - ADB11=>AddressB(7), ADB12=>scuba_vlo, ADB13=>scuba_vlo, - CEB=>ClockEnB, CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), DOA2=>QA(20), - DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), DOA6=>QA(24), - DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), DOA10=>QA(28), - DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>QB(18), - DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), DOB4=>QB(22), - DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), DOB8=>QB(26), - DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), DOB12=>QB(30), - DOB13=>QB(31), DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of ip_mem is - for Structure - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem_generate.log b/gbe2_ecp3/ipcores_ecp3/ip_mem_generate.log deleted file mode 100755 index 36881d4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem_generate.log +++ /dev/null @@ -1,47 +0,0 @@ -Starting process: Module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:37 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ramdp -device LFE3-150EA -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e - Circuit name : ip_mem - Module type : RAM_DP_TRUE - Module Version : 7.1 - Ports : - Inputs : DataInA[31:0], DataInB[31:0], AddressA[7:0], AddressB[7:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB - Outputs : QA[31:0], QB[31:0] - I/O buffer : not inserted - Memory file : ip_mem.mem - EDIF output : suppressed - VHDL output : ip_mem.vhd - VHDL template : ip_mem_tmpl.vhd - VHDL testbench : tb_ip_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : ip_mem.srp - Estimated Resource Usage: - EBR : 2 - -END SCUBA Module Synthesis - -File: ip_mem.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/ip_mem_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/ip_mem_tmpl.vhd deleted file mode 100755 index d516b11..0000000 --- a/gbe2_ecp3/ipcores_ecp3/ip_mem_tmpl.vhd +++ /dev/null @@ -1,23 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 7.1 --- Thu Sep 22 11:24:37 2011 - --- parameterized module component declaration -component ip_mem - port (DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(31 downto 0); - AddressA: in std_logic_vector(7 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; ClockB: in std_logic; - ClockEnA: in std_logic; ClockEnB: in std_logic; - WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic; - ResetB: in std_logic; QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(31 downto 0)); -end component; - --- parameterized module component instance -__ : ip_mem - port map (DataInA(31 downto 0)=>__, DataInB(31 downto 0)=>__, - AddressA(7 downto 0)=>__, AddressB(7 downto 0)=>__, ClockA=>__, - ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, - ResetB=>__, QA(31 downto 0)=>__, QB(31 downto 0)=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/macInitDataInvWithMac.mem b/gbe2_ecp3/ipcores_ecp3/macInitDataInvWithMac.mem deleted file mode 100755 index c93b822..0000000 --- a/gbe2_ecp3/ipcores_ecp3/macInitDataInvWithMac.mem +++ /dev/null @@ -1,59 +0,0 @@ -#Format=Bin -#Depth=54 -#Width=8 -#AddrRadix=3 -#DataRadix=3 -#Data -00001111 -00001111 -10011001 -00000001 -11101110 -00000101 -00000000 -00000000 -00001100 -00000000 -00110100 -00010010 -01111000 -01010110 -10111100 -10011010 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -10000000 diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.ipx b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.ipx deleted file mode 100644 index f73d4c2..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.ipx +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.jhd b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.jhd deleted file mode 100644 index 792bd48..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.jhd +++ /dev/null @@ -1,7 +0,0 @@ -MODULE mac_init_mem DEFIN mac_init_mem.vhd - SUBMODULE DP16KC - INSTANCE mac_init_mem_0_0_0 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE VHI - INSTANCE scuba_vhi_inst diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.lpc b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.lpc deleted file mode 100755 index 42f57b0..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.lpc +++ /dev/null @@ -1,48 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=ROM -CoreRevision=5.0 -ModuleName=mac_init_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:53 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Address=54 -Data=8 -adPipeline=0 -inPipeline=0 -outPipeline=1 -MOR=0 -InData=Registered -AdControl=Registered -MemFile=macInitDataInvWithMac.mem -MemFormat=bin -Reset=Sync -Pad=0 -GSR=Enabled -EnECC=0 -Optimization=Speed -Pipeline=0 - -[FilesGenerated] -macInitDataInvWithMac.mem=mem diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.naf b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.naf deleted file mode 100644 index c78cc61..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.naf +++ /dev/null @@ -1,17 +0,0 @@ -Address[5] i -Address[4] i -Address[3] i -Address[2] i -Address[1] i -Address[0] i -OutClock i -OutClockEn i -Reset i -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.sort b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.sort deleted file mode 100644 index 09863c5..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.sort +++ /dev/null @@ -1 +0,0 @@ -mac_init_mem.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.srp b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.srp deleted file mode 100755 index 0152dbc..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.srp +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:53 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type romblk -device LFE3-150EA -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - Circuit name : mac_init_mem - Module type : EBR_ROM - Module Version : 5.0 - Ports : - Inputs : Address[5:0], OutClock, OutClockEn, Reset - Outputs : Q[7:0] - I/O buffer : not inserted - Memory file : macInitDataInvWithMac.mem - EDIF output : suppressed - VHDL output : mac_init_mem.vhd - VHDL template : mac_init_mem_tmpl.vhd - VHDL testbench : tb_mac_init_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : mac_init_mem.srp - Element Usage : - DP16KC : 1 - Estimated Resource Usage: - EBR : 1 diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.sym b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.sym deleted file mode 100644 index 1d18ea4ad1ed04ad2803f6be2eb2c39e3ea617df..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 266 zcmZ1z&Hx0=K+MI+0%9@91qwF-Wi~KWKx9~hQj1edfFc4+ z1q?k5DsD3v7}x@%&B10fFfcOvhk|Sn;mJ)*j?c`?EQ!xe&1GQN#lXRMfx#6h!@(%P z;L3Q8fs^3_V*%KdTMUd~8x(-HJOi^Q0R1w7;S-o$0Av?1`~#{7`AGqYfxZUP3_$%4 F7y#!LFqQxS diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd b/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd deleted file mode 100755 index 3934a61..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd +++ /dev/null @@ -1,262 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.0 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - --- Thu Sep 22 11:24:53 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity mac_init_mem is - port ( - Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; - OutClockEn: in std_logic; - Reset: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end mac_init_mem; - -architecture Structure of mac_init_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP16KC - generic (INITVAL_3F : in String; INITVAL_3E : in String; - INITVAL_3D : in String; INITVAL_3C : in String; - INITVAL_3B : in String; INITVAL_3A : in String; - INITVAL_39 : in String; INITVAL_38 : in String; - INITVAL_37 : in String; INITVAL_36 : in String; - INITVAL_35 : in String; INITVAL_34 : in String; - INITVAL_33 : in String; INITVAL_32 : in String; - INITVAL_31 : in String; INITVAL_30 : in String; - INITVAL_2F : in String; INITVAL_2E : in String; - INITVAL_2D : in String; INITVAL_2C : in String; - INITVAL_2B : in String; INITVAL_2A : in String; - INITVAL_29 : in String; INITVAL_28 : in String; - INITVAL_27 : in String; INITVAL_26 : in String; - INITVAL_25 : in String; INITVAL_24 : in String; - INITVAL_23 : in String; INITVAL_22 : in String; - INITVAL_21 : in String; INITVAL_20 : in String; - INITVAL_1F : in String; INITVAL_1E : in String; - INITVAL_1D : in String; INITVAL_1C : in String; - INITVAL_1B : in String; INITVAL_1A : in String; - INITVAL_19 : in String; INITVAL_18 : in String; - INITVAL_17 : in String; INITVAL_16 : in String; - INITVAL_15 : in String; INITVAL_14 : in String; - INITVAL_13 : in String; INITVAL_12 : in String; - INITVAL_11 : in String; INITVAL_10 : in String; - INITVAL_0F : in String; INITVAL_0E : in String; - INITVAL_0D : in String; INITVAL_0C : in String; - INITVAL_0B : in String; INITVAL_0A : in String; - INITVAL_09 : in String; INITVAL_08 : in String; - INITVAL_07 : in String; INITVAL_06 : in String; - INITVAL_05 : in String; INITVAL_04 : in String; - INITVAL_03 : in String; INITVAL_02 : in String; - INITVAL_01 : in String; INITVAL_00 : in String; - GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc"; - attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem"; - attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC"; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - mac_init_mem_0_0_0: DP16KC - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", - INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", - CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", - REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, - ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), - ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), - ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, - CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo, - ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, - ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, - ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, - CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi, - WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1), - DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), - DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, - DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, - DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open, - DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of mac_init_mem is - for Structure - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem_generate.log b/gbe2_ecp3/ipcores_ecp3/mac_init_mem_generate.log deleted file mode 100755 index 8c200b2..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem_generate.log +++ /dev/null @@ -1,47 +0,0 @@ -Starting process: Module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Thu Sep 22 11:24:53 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n mac_init_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type romblk -device LFE3-150EA -addr_width 6 -data_width 8 -num_words 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - Circuit name : mac_init_mem - Module type : EBR_ROM - Module Version : 5.0 - Ports : - Inputs : Address[5:0], OutClock, OutClockEn, Reset - Outputs : Q[7:0] - I/O buffer : not inserted - Memory file : macInitDataInvWithMac.mem - EDIF output : suppressed - VHDL output : mac_init_mem.vhd - VHDL template : mac_init_mem_tmpl.vhd - VHDL testbench : tb_mac_init_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : mac_init_mem.srp - Estimated Resource Usage: - EBR : 1 - -END SCUBA Module Synthesis - -File: mac_init_mem.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/mac_init_mem_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/mac_init_mem_tmpl.vhd deleted file mode 100755 index 853efd2..0000000 --- a/gbe2_ecp3/ipcores_ecp3/mac_init_mem_tmpl.vhd +++ /dev/null @@ -1,15 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.0 --- Thu Sep 22 11:24:53 2011 - --- parameterized module component declaration -component mac_init_mem - port (Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q: out std_logic_vector(7 downto 0)); -end component; - --- parameterized module component instance -__ : mac_init_mem - port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__, - Reset=>__, Q(7 downto 0)=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/msg_file.log b/gbe2_ecp3/ipcores_ecp3/msg_file.log deleted file mode 100755 index 0fba5db..0000000 --- a/gbe2_ecp3/ipcores_ecp3/msg_file.log +++ /dev/null @@ -1,33 +0,0 @@ -SCUBA, Version Diamond_1.4_Production (87) -Sat May 19 15:06:38 2012 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -n fifo_65536x18x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - Circuit name : fifo_65536x18x9 - Module type : ebfifo - Module Version : 5.4 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : fifo_65536x18x9.vhd - VHDL template : fifo_65536x18x9_tmpl.vhd - VHDL testbench : tb_fifo_65536x18x9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_65536x18x9.srp - Estimated Resource Usage: - LUT : 367 - EBR : 32 - Reg : 172 - -END SCUBA Module Synthesis - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/msg_file.log b/gbe2_ecp3/ipcores_ecp3/serdes/msg_file.log deleted file mode 100755 index 0bdfb30..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/msg_file.log +++ /dev/null @@ -1,13 +0,0 @@ - Module Name: serdes_gbe_0_extclock_8b - Core Name: PCS - LPC file : serdes_gbe_0_extclock_8b.lpc - Parameter File : serdes_gbe_0_extclock_8b.pp - Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_extclock_8b.pp - Return Value: - - - Module PCS has been generated in /home/greg/NewHub2/hub2/ipexpress/serdes successfully! - -/home/greg/.isplever_lin1/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_extclock_8b -ext readme -out serdes_gbe_0_extclock_8b -tpl serdes_gbe_0_extclock_8b.tft serdes_gbe_0_extclock_8b.vhd - -Done successfully! diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.jhd b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.jhd deleted file mode 100755 index 0142dfe..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.jhd +++ /dev/null @@ -1,5 +0,0 @@ -MODULE serdes_gbe_0_extclock_8b DEFIN serdes_gbe_0_extclock_8b.vhd - SUBMODULE PCSC - INSTANCE PCSC_INST - SUBMODULE VLO - INSTANCE vlo_inst diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.lpc b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.lpc deleted file mode 100755 index 4efe9cf..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.lpc +++ /dev/null @@ -1,140 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-6F900C -SpeedGrade=-6 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=7.0 -ModuleName=serdes_gbe_0_extclock_8b -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=08/20/2009 -Time=11:50:53 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Protocol=Quad -mode=Gigabit Ethernet -Channel0=SINGLE -Channel1=DISABLE -Channel2=DISABLE -Channel3=DISABLE -Rate0=None -Rate1=None -Rate2=None -Rate3=None -TxRefClk=REFCLK -RxRefClk=REFCLK -ClkRate=1.25 -ClkMult=10X -CalClkRate=125.0 -DataWidth=8 -FPGAClkRate=125.0 -TxRefClkCM=REFCLK -RxRefClk0CM=REFCLK -RxRefClk1CM=REFCLK -RxRefClk2CM=REFCLK -RxRefClk3CM=REFCLK -ClkRateH=0.625 -ClkMultH=10XH -CalClkRateH=125.0 -DataWidthH=8 -FPGAClkRateH=62.5 -VCh0=0 -VCh1=0 -VCh2=0 -VCh3=0 -PreCh0=DISABLE -PreCh1=DISABLE -PreCh2=DISABLE -PreCh3=DISABLE -TxCh0=50 -TxCh1=50 -TxCh2=50 -TxCh3=50 -EqCh0=DISABLE -EqCh1=DISABLE -EqCh2=DISABLE -EqCh3=DISABLE -RxTermCh0=50 -RxTermCh1=50 -RxTermCh2=50 -RxTermCh3=50 -RxCoupCh0=AC -RxCoupCh1=AC -RxCoupCh2=AC -RxCoupCh3=AC -Loss=0 -CDRLoss=0 -TxTerm=50 -TxCoup=AC -TxPllLoss=0 -TxInvCh0=NORMAL -TxInvCh1=NORMAL -TxInvCh2=NORMAL -TxInvCh3=NORMAL -RxInvCh0=NORMAL -RxInvCh1=NORMAL -RxInvCh2=NORMAL -RxInvCh3=NORMAL -RxModeCh0=NORMAL -RxModeCh1=NORMAL -RxModeCh2=NORMAL -RxModeCh3=NORMAL -Plus=1100000101 -Minus=0011111010 -Mask=1111111111 -Align=AUTO -CTCCh0=NORMAL -CTCCh1=NORMAL -CTCCh2=NORMAL -CTCCh3=NORMAL -CC_MATCH1=0000000000 -CC_MATCH2=0000000000 -CC_MATCH3=0110111100 -CC_MATCH4=0001010000 -MinIPG=3 -High=9 -Low=7 -CC_MATCH_MODE=MATCH_3_4 -RxDataCh0=FALSE -RxDataCh1=FALSE -RxDataCh2=FALSE -RxDataCh3=FALSE -AlignerCh0=FALSE -AlignerCh1=FALSE -AlignerCh2=FALSE -AlignerCh3=FALSE -DetectCh0=FALSE -DetectCh1=FALSE -DetectCh2=FALSE -DetectCh3=FALSE -ELSMCh0=FALSE -ELSMCh1=FALSE -ELSMCh2=FALSE -ELSMCh3=FALSE -_teidleCh0=FALSE -_teidleCh1=FALSE -_teidleCh2=FALSE -_teidleCh3=FALSE -Ports0=FALSE -rdoPorts0=Serial Loopback -Ports1=FALSE -Ports2=TRUE -Ports3=FALSE -Ports3_1=FALSE -Ports4=FALSE diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.naf b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.naf deleted file mode 100755 index e0d6b71..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.naf +++ /dev/null @@ -1,49 +0,0 @@ -refclkp i -refclkn i -hdinp0 i -hdinn0 i -hdoutp0 o -hdoutn0 o -ff_rxiclk_ch0 i -ff_txiclk_ch0 i -ff_ebrd_clk_0 i -ff_txdata_ch0[7] i -ff_txdata_ch0[6] i -ff_txdata_ch0[5] i -ff_txdata_ch0[4] i -ff_txdata_ch0[3] i -ff_txdata_ch0[2] i -ff_txdata_ch0[1] i -ff_txdata_ch0[0] i -ff_rxdata_ch0[7] o -ff_rxdata_ch0[6] o -ff_rxdata_ch0[5] o -ff_rxdata_ch0[4] o -ff_rxdata_ch0[3] o -ff_rxdata_ch0[2] o -ff_rxdata_ch0[1] o -ff_rxdata_ch0[0] o -ff_tx_k_cntrl_ch0 i -ff_rx_k_cntrl_ch0 o -ff_rxfullclk_ch0 o -ff_xmit_ch0 i -ff_correct_disp_ch0 i -ff_disp_err_ch0 o -ff_cv_ch0 o -ff_rx_even_ch0 o -ffc_rrst_ch0 i -ffc_lane_tx_rst_ch0 i -ffc_lane_rx_rst_ch0 i -ffc_txpwdnb_ch0 i -ffc_rxpwdnb_ch0 i -ffs_rlos_lo_ch0 o -ffs_ls_sync_status_ch0 o -ffs_rlol_ch0 o -oob_out_ch0 o -ffc_macro_rst i -ffc_quad_rst i -ffc_trst i -ff_txfullclk o -ff_txhalfclk o -refck2core o -ffs_plol o diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.pp b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.pp deleted file mode 100755 index 49e4332..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.pp +++ /dev/null @@ -1,95 +0,0 @@ -#define _device_name "LFE2M100E" -#define _protocol_mode "Quad Based Protocol Mode" -#define _protocol "GIGE" -#define _ch0_mode "SINGLE" -#define _ch1_mode "DISABLE" -#define _ch2_mode "DISABLE" -#define _ch3_mode "DISABLE" -#define _pll_txsrc "REFCLK" -#define _pll_rxsrc "REFCLK" -#define _datarange "MED" -#define _refclk_mult "10X" -#define _refclk_rate 125.0 -#define _data_width "8" -#define _fpgaintclk_rate 125.0 -#define _ch0_tdrv_amp "0" -#define _ch1_tdrv_amp "0" -#define _ch2_tdrv_amp "0" -#define _ch3_tdrv_amp "0" -#define _ch0_tx_pre "DISABLE" -#define _ch1_tx_pre "DISABLE" -#define _ch2_tx_pre "DISABLE" -#define _ch3_tx_pre "DISABLE" -#define _ch0_rterm_tx "50" -#define _ch1_rterm_tx "50" -#define _ch2_rterm_tx "50" -#define _ch3_rterm_tx "50" -#define _ch0_rx_eq "DISABLE" -#define _ch1_rx_eq "DISABLE" -#define _ch2_rx_eq "DISABLE" -#define _ch3_rx_eq "DISABLE" -#define _ch0_rterm_rx "50" -#define _ch1_rterm_rx "50" -#define _ch2_rterm_rx "50" -#define _ch3_rterm_rx "50" -#define _ch0_rx_dcc "AC" -#define _ch1_rx_dcc "AC" -#define _ch2_rx_dcc "AC" -#define _ch3_rx_dcc "AC" -#define _los_threshold "0" -#define _pll_term "50" -#define _pll_dcc "AC" -#define _pll_lol_set "0" -#define _ch0_tx_sb "NORMAL" -#define _ch1_tx_sb "NORMAL" -#define _ch2_tx_sb "NORMAL" -#define _ch3_tx_sb "NORMAL" -#define _ch0_rx_sb "NORMAL" -#define _ch1_rx_sb "NORMAL" -#define _ch2_rx_sb "NORMAL" -#define _ch3_rx_sb "NORMAL" -#define _ch0_8b10b "NORMAL" -#define _ch1_8b10b "NORMAL" -#define _ch2_8b10b "NORMAL" -#define _ch3_8b10b "NORMAL" -#define _comma_a "1100000101" -#define _comma_b "0011111010" -#define _comma_m "1111111111" -#define _comma_align "AUTO" -#define _ch0_ctc_byp "NORMAL" -#define _ch1_ctc_byp "NORMAL" -#define _ch2_ctc_byp "NORMAL" -#define _ch3_ctc_byp "NORMAL" -#define _cc_match1 "0000000000" -#define _cc_match2 "0000000000" -#define _cc_match3 "0110111100" -#define _cc_match4 "0001010000" -#define _cc_match_mode "MATCH_3_4" -#define _cc_min_ipg "3" -#define _cchmark "9" -#define _cclmark "7" -#define _ch0_ird "FALSE" -#define _ch1_ird "FALSE" -#define _ch2_ird "FALSE" -#define _ch3_ird "FALSE" -#define _ch0_elsm "FALSE" -#define _ch1_elsm "FALSE" -#define _ch2_elsm "FALSE" -#define _ch3_elsm "FALSE" -#define _ch0_teidle "FALSE" -#define _ch1_teidle "FALSE" -#define _ch2_teidle "FALSE" -#define _ch3_teidle "FALSE" -#define _loopback "FALSE" -#define _lbtype "Serial Loopback" -#define _refck2core "TRUE" -#define _pllqclkports "FALSE" -#define _sci_ports "FALSE" -#define _sci_int_port "FALSE" -#define _errsports "FALSE" - -#define _circuit_name serdes_gbe_0_extclock_8b -#define _lang vhdl - -#include -#include diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.readme b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.readme deleted file mode 100755 index e231789..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.readme +++ /dev/null @@ -1,141 +0,0 @@ - - TOOL: orcapp - DATE: 19-MAR-2008 13:11:51 - TITLE: Lattice Semiconductor Corporation - MODULE: serdes_gbe_0_extclock_8b - DESIGN: serdes_gbe_0_extclock_8b - FILENAME: serdes_gbe_0_extclock_8b.readme - PROJECT: Unknown - VERSION: 2.0 - This file is auto generated by the ispLEVER - - -NOTE: This readme file has been provided to instantiate the interface -netlist. Since this template contains synthesis attributes for precision that -are crucial to the design flow, we recommend that you use this -template in your FPGA design. -entity chip is -port ( - --- Add your FPGA design top level I/Os here - - --- ASIC side pins for PCSA. These pins must exist for the --- PCS core. - refclkp : in std_logic; - refclkn : in std_logic; - hdinp0 : in std_logic; - hdinn0 : in std_logic; - hdinp1 : in std_logic; - hdinn1 : in std_logic; - hdinp2 : in std_logic; - hdinn2 : in std_logic; - hdinp3 : in std_logic; - hdinn3 : in std_logic; - - hdoutp0 : out std_logic; - hdoutn0 : out std_logic; - hdoutp1 : out std_logic; - hdoutn1 : out std_logic; - hdoutp2 : out std_logic; - hdoutn2 : out std_logic; - hdoutp3 : out std_logic; - hdoutn3 : out std_logic; - - -); -end chip; - -architecture chip_arch of chip is - --- This defines all the high-speed ports. You may have to remove --- some of them depending on your design. -attribute nopad : string; -attribute nopad of - refclkp, refclkn, - hdinp0, hdinn0, hdinp1, hdinn1, - hdinp2, hdinn2, hdinp3, hdinn3, - hdoutp0, hdoutn0, hdoutp1, hdoutn1, - hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true"; - - COMPONENT serdes_gbe_0_extclock_8b - PORT( - refclkp : IN std_logic; - refclkn : IN std_logic; - hdinp0 : IN std_logic; - hdinn0 : IN std_logic; - ff_rxiclk_ch0 : IN std_logic; - ff_txiclk_ch0 : IN std_logic; - ff_ebrd_clk_0 : IN std_logic; - ff_txdata_ch0 : IN std_logic_vector(7 downto 0); - ff_tx_k_cntrl_ch0 : IN std_logic; - ff_xmit_ch0 : IN std_logic; - ff_correct_disp_ch0 : IN std_logic; - ffc_rrst_ch0 : IN std_logic; - ffc_lane_tx_rst_ch0 : IN std_logic; - ffc_lane_rx_rst_ch0 : IN std_logic; - ffc_txpwdnb_ch0 : IN std_logic; - ffc_rxpwdnb_ch0 : IN std_logic; - ffc_macro_rst : IN std_logic; - ffc_quad_rst : IN std_logic; - ffc_trst : IN std_logic; - hdoutp0 : OUT std_logic; - hdoutn0 : OUT std_logic; - ff_rxdata_ch0 : OUT std_logic_vector(7 downto 0); - ff_rx_k_cntrl_ch0 : OUT std_logic; - ff_rxfullclk_ch0 : OUT std_logic; - ff_disp_err_ch0 : OUT std_logic; - ff_cv_ch0 : OUT std_logic; - ff_rx_even_ch0 : OUT std_logic; - ffs_rlos_lo_ch0 : OUT std_logic; - ffs_ls_sync_status_ch0 : OUT std_logic; - ffs_rlol_ch0 : OUT std_logic; - oob_out_ch0 : OUT std_logic; - ff_txfullclk : OUT std_logic; - ff_txhalfclk : OUT std_logic; - refck2core : OUT std_logic; - ffs_plol : OUT std_logic - ); - END COMPONENT; - - - - uut: serdes_gbe_0_extclock_8b PORT MAP( - refclkp => refclkp, - refclkn => refclkn, - hdinp0 => hdinp0, - hdinn0 => hdinn0, - hdoutp0 => hdoutp0, - hdoutn0 => hdoutn0, - ff_rxiclk_ch0 => ff_rxiclk_ch0, - ff_txiclk_ch0 => ff_txiclk_ch0, - ff_ebrd_clk_0 => ff_ebrd_clk_0, - ff_txdata_ch0 => ff_txdata_ch0, - ff_rxdata_ch0 => ff_rxdata_ch0, - ff_tx_k_cntrl_ch0 => ff_tx_k_cntrl_ch0, - ff_rx_k_cntrl_ch0 => ff_rx_k_cntrl_ch0, - ff_rxfullclk_ch0 => ff_rxfullclk_ch0, - ff_xmit_ch0 => ff_xmit_ch0, - ff_correct_disp_ch0 => ff_correct_disp_ch0, - ff_disp_err_ch0 => ff_disp_err_ch0, - ff_cv_ch0 => ff_cv_ch0, - ff_rx_even_ch0 => ff_rx_even_ch0, - ffc_rrst_ch0 => ffc_rrst_ch0, - ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst_ch0, - ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst_ch0, - ffc_txpwdnb_ch0 => ffc_txpwdnb_ch0, - ffc_rxpwdnb_ch0 => ffc_rxpwdnb_ch0, - ffs_rlos_lo_ch0 => ffs_rlos_lo_ch0, - ffs_ls_sync_status_ch0 => ffs_ls_sync_status_ch0, - ffs_rlol_ch0 => ffs_rlol_ch0, - oob_out_ch0 => oob_out_ch0, - ffc_macro_rst => ffc_macro_rst, - ffc_quad_rst => ffc_quad_rst, - ffc_trst => ffc_trst, - ff_txfullclk => ff_txfullclk, - ff_txhalfclk => ff_txhalfclk, - refck2core => refck2core, - ffs_plol => ffs_plol - ); - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.sym b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.sym deleted file mode 100755 index 738404a543f19a6fdb45fdcf16c46ffb4b5a94eb..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1626 zcmZ9MPly{;9LImZH`CN^)y8!xB2oqk9`+zZ59`uXSnM7|)?x7vw6!nE%*3oaI~iwY z*I0T8A|85>Af6TvOA(RML)e4#P$cx=VGkt-DdIsw58^?}QuZWe@%w(0kd22)K6&5I z`^|fAewn);U0vI{VG+@ll8sNI#2P4vcI`X(dDC9ONRJn(@;2b*W>fp^G!6Y+2OC+U z{gzAD5ggLHh4BK6u#pDZk2bYSH<0zIHOd6Rv%T@NIpTgdv{ zIgzE4lJpZYSAADx=ghpclYAb;4O#U7X;1AJ>2oH{&CTdfjF;8HiCOuHSx06T{avJ` zR*Okmri9m!ez3G@Y?-!>aMuuyz%_2n)|3+zI2cG_G|3YeaWpJy2x& z1lGwuncVXTUY~x0_m3jeFKOq0{W39Mvl5H=80LaSWigxEQ8Z~xbWX90s`1ntR%LbB zB0NcS=-7iYb^F=X%=wFh+qP%U|5Y0nmF&vu zyiKQDL3=wl?J?fjGSV7Vkh+u9w8=QVf^@_yNY`yT+io{BX3tbNZ<4ACVB|K5 zh?hq=-3igcD_NKZVWvN6gxb|%C-D5rUS3bco*EIPlapX8ts71f7rqGrEmgH)HlK&*i*a0F4$E+ z3YWoUwJ&_g4&Ge92oJ$SJ`nDM`}|0_2k!A>;RKxU6JZbR@xNH7d8<0ON+q+NLqbiO p7aoF#bV0Ze?$e@h58R_A;RKw}im(UvXieA!yQnvZZ^Bs&)PGO+XvF{k diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.tft b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.tft deleted file mode 100755 index 8a55292..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.tft +++ /dev/null @@ -1,98 +0,0 @@ -@set suppresnewline=on@ - -@comment --------------------------------------------------------------------- @ -@comment Template-drive TFI generator @ -@comment Template for TFI generation. @ -@comment --------------------------------------------------------------------- @ - -@set suppresnewline=off@ - TOOL: orcapp - DATE: 19-MAR-2008 13:11:51 - TITLE: %title% - MODULE: %module% - DESIGN: %module% - FILENAME: %filename% - PROJECT: %project% - VERSION: %ver% - This file is auto generated by the ispLEVER -@set suppresnewline=on@ - -@cr@ -@cr@ - -@set sigdelim=@ - -NOTE: This readme file has been provided to instantiate the interface@cr@ -netlist. Since this template contains synthesis attributes for precision that@cr@ -are crucial to the design flow, we recommend that you use this@cr@ -template in your FPGA design.@cr@ -entity chip is@cr@ -port (@cr@ -@cr@ --- Add your FPGA design top level I/Os here@cr@ -@cr@ -@cr@ --- ASIC side pins for PCSA. These pins must exist for the@cr@ --- PCS core.@cr@ - refclkp : in std_logic;@cr@ - refclkn : in std_logic;@cr@ - hdinp0 : in std_logic;@cr@ - hdinn0 : in std_logic;@cr@ - hdinp1 : in std_logic;@cr@ - hdinn1 : in std_logic;@cr@ - hdinp2 : in std_logic;@cr@ - hdinn2 : in std_logic;@cr@ - hdinp3 : in std_logic;@cr@ - hdinn3 : in std_logic;@cr@ -@cr@ - hdoutp0 : out std_logic;@cr@ - hdoutn0 : out std_logic;@cr@ - hdoutp1 : out std_logic;@cr@ - hdoutn1 : out std_logic;@cr@ - hdoutp2 : out std_logic;@cr@ - hdoutn2 : out std_logic;@cr@ - hdoutp3 : out std_logic;@cr@ - hdoutn3 : out std_logic;@cr@ -@cr@ -@cr@ -);@cr@ -end chip;@cr@ -@cr@ -architecture chip_arch of chip is@cr@ -@cr@ --- This defines all the high-speed ports. You may have to remove@cr@ --- some of them depending on your design.@cr@ -attribute nopad : string;@cr@ -attribute nopad of@cr@ - refclkp, refclkn,@cr@ - hdinp0, hdinn0, hdinp1, hdinn1,@cr@ - hdinp2, hdinn2, hdinp3, hdinn3,@cr@ - hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@ - hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@ - -@cr@ -@tab@COMPONENT %module% -@set sigdelim=@ -@cr@@tab@PORT( -@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ -@ifhas oport=*@ @comment if the design has any output ports... @ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ - @set sigdelim=;@ - @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ -@endif@ -@ifnhas oport=*@ @comment we need an "else in this language! @ - @set sigdelim=;@ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ -@endif@ -@cr@@tab@@tab@);@cr@ -@tab@END COMPONENT;@cr@@cr@ -@comment Now do a signal declaration for each port @ - -@cr@@cr@ -@comment do the component instantiation @ -@set sigdelim=,@ -@tab@uut: %module% PORT MAP( -@iterate@%port% -@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ -@cr@@tab@);@cr@@cr@ -@set suppresnewline=off@ diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.txt b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.txt deleted file mode 100755 index 860001f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.txt +++ /dev/null @@ -1,49 +0,0 @@ - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSC quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSC quad to the final design requirements. - -DEVICE_NAME "LFE2M100E" -PROTOCOL "GIGE" -CH0_MODE "SINGLE" -CH1_MODE "DISABLE" -CH2_MODE "DISABLE" -CH3_MODE "DISABLE" -PLL_SRC "REFCLK" -DATARANGE "MED" -CH0_CDR_SRC "REFCLK" -CH0_DATA_WIDTH "8" -CH0_REFCK_MULT "10X" -#REFCLK_RATE 125.0 -#FPGAINTCLK_RATE 125.0 -CH0_TDRV_AMP "0" -CH0_TX_PRE "DISABLE" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLE" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -LOS_THRESHOLD "0" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "NORMAL" -CH0_RX_SB "NORMAL" -CH0_8B10B "NORMAL" -COMMA_A "1100000101" -COMMA_B "0011111010" -COMMA_M "1111111111" -CH0_COMMA_ALIGN "AUTO" -CH0_CTC_BYP "BYPASS" -CC_MATCH1 "0000000000" -CC_MATCH2 "0000000000" -CC_MATCH3 "0110111100" -CC_MATCH4 "0001010000" -CC_MATCH_MODE "MATCH_3_4" -CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -OS_REFCK2CORE "1" -OS_PLLQCLKPORTS "0" -OS_INT_ALL "0" - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.vhd b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.vhd deleted file mode 100755 index c3d0eda..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b.vhd +++ /dev/null @@ -1,2182 +0,0 @@ - - ---synopsys translate_off - -library pcsc_work; -use pcsc_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSC is -GENERIC( - CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); - -end PCSC; - -architecture PCSC_arch of PCSC is - -component PCSC_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - -begin - -PCSC_sim_inst : PCSC_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, - FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, - FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, - FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, - FF_TX_F_CLK => FF_TX_F_CLK, - FF_TX_H_CLK => FF_TX_H_CLK, - FF_TX_Q_CLK => FF_TX_Q_CLK, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - OOB_OUT_0 => OOB_OUT_0, - OOB_OUT_1 => OOB_OUT_1, - OOB_OUT_2 => OOB_OUT_2, - OOB_OUT_3 => OOB_OUT_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7 - ); - -end PCSC_arch; - ---synopsys translate_on - ---synopsys translate_off -library ECP2; -use ECP2.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_extclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"); - port ( - refclkp, refclkn : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - refck2core : out std_logic; - ffs_plol : out std_logic); - -end serdes_gbe_0_extclock_8b; - -architecture serdes_gbe_0_extclock_8b_arch of serdes_gbe_0_extclock_8b is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; -component PCSC ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal fpsc_vlo : std_logic := '0'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSC_INST : PCSC ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - FFC_CK_CORE_TX => fpsc_vlo, - FFC_CK_CORE_RX => fpsc_vlo, - REFCLKP => refclkp, - REFCLKN => refclkn, - HDINP0 => hdinp0, - HDINN0 => hdinn0, - HDOUTP0 => hdoutp0, - HDOUTN0 => hdoutn0, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => ff_rxiclk_ch0, - FF_TXI_CLK_0 => ff_txiclk_ch0, - FF_EBRD_CLK_0 => ff_ebrd_clk_0, - FF_RX_F_CLK_0 => ff_rxfullclk_ch0, - FF_RX_H_CLK_0 => open, - FF_RX_Q_CLK_0 => open, - FF_TX_D_0_0 => ff_txdata_ch0(0), - FF_TX_D_0_1 => ff_txdata_ch0(1), - FF_TX_D_0_2 => ff_txdata_ch0(2), - FF_TX_D_0_3 => ff_txdata_ch0(3), - FF_TX_D_0_4 => ff_txdata_ch0(4), - FF_TX_D_0_5 => ff_txdata_ch0(5), - FF_TX_D_0_6 => ff_txdata_ch0(6), - FF_TX_D_0_7 => ff_txdata_ch0(7), - FF_TX_D_0_8 => ff_tx_k_cntrl_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => ff_xmit_ch0, - FF_TX_D_0_11 => ff_correct_disp_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => ff_rxdata_ch0(0), - FF_RX_D_0_1 => ff_rxdata_ch0(1), - FF_RX_D_0_2 => ff_rxdata_ch0(2), - FF_RX_D_0_3 => ff_rxdata_ch0(3), - FF_RX_D_0_4 => ff_rxdata_ch0(4), - FF_RX_D_0_5 => ff_rxdata_ch0(5), - FF_RX_D_0_6 => ff_rxdata_ch0(6), - FF_RX_D_0_7 => ff_rxdata_ch0(7), - FF_RX_D_0_8 => ff_rx_k_cntrl_ch0, - FF_RX_D_0_9 => ff_disp_err_ch0, - FF_RX_D_0_10 => ff_cv_ch0, - FF_RX_D_0_11 => ff_rx_even_ch0, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - FFC_RRST_0 => ffc_rrst_ch0, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFS_PCIE_DONE_0 => open, - FFS_PCIE_CON_0 => open, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, - FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, - FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, - FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, - FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, - FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, - FFS_CC_UNDERRUN_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - FFS_RLOL_0 => ffs_rlol_ch0, - OOB_OUT_0 => oob_out_ch0, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - HDOUTP1 => open, - HDOUTN1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_RX_Q_CLK_1 => open, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_PCIE_CON_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - OOB_OUT_1 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - HDOUTP2 => open, - HDOUTN2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_RX_Q_CLK_2 => open, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_PCIE_CON_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - OOB_OUT_2 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - HDOUTP3 => open, - HDOUTN3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_RX_Q_CLK_3 => open, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_PCIE_CON_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - OOB_OUT_3 => open, - SCIWDATA0 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA7 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIRDATA0 => open, - SCIRDATA1 => open, - SCIRDATA2 => open, - SCIRDATA3 => open, - SCIRDATA4 => open, - SCIRDATA5 => open, - SCIRDATA6 => open, - SCIRDATA7 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_MACRO_RST => ffc_macro_rst, - FFC_QUAD_RST => ffc_quad_rst, - FFC_TRST => ffc_trst, - FF_TX_F_CLK => ff_txfullclk, - FF_TX_H_CLK => ff_txhalfclk, - FF_TX_Q_CLK => open, - REFCK2CORE => refck2core, - CIN0 => cin(0), - CIN1 => cin(1), - CIN2 => cin(2), - CIN3 => cin(3), - CIN4 => cin(4), - CIN5 => cin(5), - CIN6 => cin(6), - CIN7 => cin(7), - CIN8 => cin(8), - CIN9 => cin(9), - CIN10 => cin(10), - CIN11 => cin(11), - COUT0 => cout(0), - COUT1 => cout(1), - COUT2 => cout(2), - COUT3 => cout(3), - COUT4 => cout(4), - COUT5 => cout(5), - COUT6 => cout(6), - COUT7 => cout(7), - COUT8 => cout(8), - COUT9 => cout(9), - COUT10 => cout(10), - COUT11 => cout(11), - COUT12 => cout(12), - COUT13 => cout(13), - COUT14 => cout(14), - COUT15 => cout(15), - COUT16 => cout(16), - COUT17 => cout(17), - COUT18 => cout(18), - COUT19 => cout(19), - FFS_PLOL => ffs_plol); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end serdes_gbe_0_extclock_8b_arch ; diff --git a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b_generate.log b/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b_generate.log deleted file mode 100755 index 8e108c6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes/serdes_gbe_0_extclock_8b_generate.log +++ /dev/null @@ -1,26 +0,0 @@ -Starting process: - - Module Name: serdes_gbe_0_extclock_8b - Core Name: PCS - LPC file : serdes_gbe_0_extclock_8b.lpc - Parameter File : serdes_gbe_0_extclock_8b.pp - Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_extclock_8b.pp - Return Value: - - - Module PCS has been generated in /home/greg/NewHub2/hub2/ipexpress/serdes successfully! - -/home/greg/.isplever_lin1/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_extclock_8b -ext readme -out serdes_gbe_0_extclock_8b -tpl serdes_gbe_0_extclock_8b.tft serdes_gbe_0_extclock_8b.vhd - -Done successfully! -File: serdes_gbe_0_extclock_8b.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.ipx b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.ipx deleted file mode 100644 index 82a5965..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.jhd b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.jhd deleted file mode 100644 index 0338a8f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.jhd +++ /dev/null @@ -1,7 +0,0 @@ -MODULE serdes_ch4 DEFIN serdes_ch4.vhd - SUBMODULE PCSD - INSTANCE PCSD_INST - SUBMODULE VHI - INSTANCE vhi_inst - SUBMODULE VLO - INSTANCE vlo_inst diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.lpc b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.lpc deleted file mode 100644 index daf6272..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_ch4 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/04/2012 -Time=20:33:49 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=DISABLED -_mode1=DISABLED -_mode2=DISABLED -_mode3=RXTX -_protocol0=G8B10B -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=GIGE -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=1.25 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=125.0 -_tx_protocol0=DISABLED -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=GIGE -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=125.0 -_tx_ficlk_rate1=125.0 -_tx_ficlk_rate2=125.0 -_tx_ficlk_rate3=125.0 -_pll_rxsrc0=EXTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=INTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=2.5 -_rx_datarange1=2.5 -_rx_datarange2=2.5 -_rx_datarange3=1.25 -_rx_protocol0=DISABLED -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=GIGE -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=250.0 -_rxrefclk_rate1=250.0 -_rxrefclk_rate2=250.0 -_rxrefclk_rate3=125.0 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=ENABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=ENABLED -_rx_ficlk_rate0=250.0 -_rx_ficlk_rate1=250.0 -_rx_ficlk_rate2=250.0 -_rx_ficlk_rate3=125.0 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=AC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=AC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P157 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P5 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111100 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111111 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=1 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=2 -_k00=00 -_k01=00 -_k02=00 -_k03=01 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=01 -_k31=01 -_k32=01 -_k33=00 -_byten00=00000000 -_byten01=00000000 -_byten02=00000000 -_byten03=10111100 -_byten10=00000000 -_byten11=00000000 -_byten12=00000000 -_byten13=01010000 -_byten20=00011100 -_byten21=00011100 -_byten22=00011100 -_byten23=10111100 -_byten30=00011100 -_byten31=00011100 -_byten32=00011100 -_byten33=01010000 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=DISABLED -_sci_int_port=DISABLED -_refck2core=DISABLED -Regen=auto -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_ch4.pp=pp -serdes_ch4.tft=tft -serdes_ch4.txt=pcs_module -serdes_ch4.sym=sym diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.naf b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.naf deleted file mode 100644 index 22645f6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.naf +++ /dev/null @@ -1,48 +0,0 @@ -hdinp_ch3 i -hdinn_ch3 i -hdoutp_ch3 o -hdoutn_ch3 o -rxiclk_ch3 i -txiclk_ch3 i -rx_full_clk_ch3 o -rx_half_clk_ch3 o -tx_full_clk_ch3 o -tx_half_clk_ch3 o -fpga_rxrefclk_ch3 i -txdata_ch3[7] i -txdata_ch3[6] i -txdata_ch3[5] i -txdata_ch3[4] i -txdata_ch3[3] i -txdata_ch3[2] i -txdata_ch3[1] i -txdata_ch3[0] i -tx_k_ch3 i -xmit_ch3 i -tx_disp_correct_ch3 i -rxdata_ch3[7] o -rxdata_ch3[6] o -rxdata_ch3[5] o -rxdata_ch3[4] o -rxdata_ch3[3] o -rxdata_ch3[2] o -rxdata_ch3[1] o -rxdata_ch3[0] o -rx_k_ch3 o -rx_disp_err_ch3 o -rx_cv_err_ch3 o -rx_serdes_rst_ch3_c i -sb_felb_ch3_c i -sb_felb_rst_ch3_c i -tx_pcs_rst_ch3_c i -tx_pwrup_ch3_c i -rx_pcs_rst_ch3_c i -rx_pwrup_ch3_c i -rx_los_low_ch3_s o -lsm_status_ch3_s o -rx_cdr_lol_ch3_s o -fpga_txrefclk i -tx_serdes_rst_c i -tx_pll_lol_qd_s o -rst_qd_c i -serdes_rst_qd_c i diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.pp b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.pp deleted file mode 100644 index 76f371d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.pp +++ /dev/null @@ -1,191 +0,0 @@ -#define _device_name "LFE3-150EA" -#define _ch0_pll_rxsrc "REFCLK_EXT" -#define _ch0_mode "DISABLED" -#define _ch0_protocol "G8B10B" -#define _ch0_ldr "DISABLED" -#define _ch0_tx_data_rate "FULL" -#define _ch0_tx_data_width "8" -#define _ch0_tx_fifo "ENABLED" -#define _ch0_tx_ficlk_rate 125.0 -#define _ch0_rx_datarange "MEDHIGH" -#define _ch0_rx_data_rate "FULL" -#define _ch0_rxrefclk_rate "250.0" -#define _ch0_rx_data_width "8" -#define _ch0_rx_fifo "ENABLED" -#define _ch0_rx_ficlk_rate 250.0 -#define _ch0_tdrv "0" -#define _ch0_tx_pre "DISABLED" -#define _ch0_rterm_tx "50" -#define _ch0_rx_eq "DISABLED" -#define _ch0_rterm_rx "50" -#define _ch0_rx_dcc "AC" -#define _los_threshold_lo0 "2" -#define _ch0_tx_sb "DISABLED" -#define _ch0_tx_8b10b "ENABLED" -#define _ch0_rx_sb "DISABLED" -#define _ch0_ird "DISABLED" -#define _ch0_rx_8b10b "ENABLED" -#define _ch0_rxwa "ENABLED" -#define _ch0_ilsm "ENABLED" -#define _ch0_scomma "K28P157" -#define _ch0_comma_a "1100000101" -#define _ch0_comma_b "0011111010" -#define _ch0_comma_m "1111111100" -#define _ch0_ctc "DISABLED" -#define _ch0_cc_match_mode "1" -#define _ch0_byten "0000000000" -#define _ch0_byten1 "0000000000" -#define _ch0_byten2 "0100011100" -#define _ch0_byten3 "0100011100" -#define _ch0_cc_min_ipg "3" -#define _ch0_lbtype "DISABLED" -#define _ch0_teidle "DISABLED" -#define _ch0_rx_lol_port "INTERNAL" - -#define _ch1_pll_rxsrc "REFCLK_EXT" -#define _ch1_mode "DISABLED" -#define _ch1_protocol "G8B10B" -#define _ch1_ldr "DISABLED" -#define _ch1_tx_data_rate "FULL" -#define _ch1_tx_data_width "8" -#define _ch1_tx_fifo "ENABLED" -#define _ch1_tx_ficlk_rate 125.0 -#define _ch1_rx_datarange "MEDHIGH" -#define _ch1_rx_data_rate "FULL" -#define _ch1_rxrefclk_rate "250.0" -#define _ch1_rx_data_width "8" -#define _ch1_rx_fifo "ENABLED" -#define _ch1_rx_ficlk_rate 250.0 -#define _ch1_tdrv "0" -#define _ch1_tx_pre "DISABLED" -#define _ch1_rterm_tx "50" -#define _ch1_rx_eq "DISABLED" -#define _ch1_rterm_rx "50" -#define _ch1_rx_dcc "AC" -#define _los_threshold_lo1 "2" -#define _ch1_tx_sb "DISABLED" -#define _ch1_tx_8b10b "ENABLED" -#define _ch1_rx_sb "DISABLED" -#define _ch1_ird "DISABLED" -#define _ch1_rx_8b10b "ENABLED" -#define _ch1_rxwa "ENABLED" -#define _ch1_ilsm "ENABLED" -#define _ch1_scomma "K28P157" -#define _ch1_comma_a "1100000101" -#define _ch1_comma_b "0011111010" -#define _ch1_comma_m "1111111100" -#define _ch1_ctc "DISABLED" -#define _ch1_cc_match_mode "1" -#define _ch1_byten "0000000000" -#define _ch1_byten1 "0000000000" -#define _ch1_byten2 "0100011100" -#define _ch1_byten3 "0100011100" -#define _ch1_cc_min_ipg "3" -#define _ch1_lbtype "DISABLED" -#define _ch1_teidle "DISABLED" -#define _ch1_rx_lol_port "INTERNAL" - -#define _ch2_pll_rxsrc "REFCLK_EXT" -#define _ch2_mode "DISABLED" -#define _ch2_protocol "G8B10B" -#define _ch2_ldr "DISABLED" -#define _ch2_tx_data_rate "FULL" -#define _ch2_tx_data_width "8" -#define _ch2_tx_fifo "ENABLED" -#define _ch2_tx_ficlk_rate 125.0 -#define _ch2_rx_datarange "MEDHIGH" -#define _ch2_rx_data_rate "FULL" -#define _ch2_rxrefclk_rate "250.0" -#define _ch2_rx_data_width "8" -#define _ch2_rx_fifo "ENABLED" -#define _ch2_rx_ficlk_rate 250.0 -#define _ch2_tdrv "0" -#define _ch2_tx_pre "DISABLED" -#define _ch2_rterm_tx "50" -#define _ch2_rx_eq "DISABLED" -#define _ch2_rterm_rx "50" -#define _ch2_rx_dcc "AC" -#define _los_threshold_lo2 "2" -#define _ch2_tx_sb "DISABLED" -#define _ch2_tx_8b10b "ENABLED" -#define _ch2_rx_sb "DISABLED" -#define _ch2_ird "DISABLED" -#define _ch2_rx_8b10b "ENABLED" -#define _ch2_rxwa "ENABLED" -#define _ch2_ilsm "ENABLED" -#define _ch2_scomma "K28P157" -#define _ch2_comma_a "1100000101" -#define _ch2_comma_b "0011111010" -#define _ch2_comma_m "1111111100" -#define _ch2_ctc "DISABLED" -#define _ch2_cc_match_mode "1" -#define _ch2_byten "0000000000" -#define _ch2_byten1 "0000000000" -#define _ch2_byten2 "0100011100" -#define _ch2_byten3 "0100011100" -#define _ch2_cc_min_ipg "3" -#define _ch2_lbtype "DISABLED" -#define _ch2_teidle "DISABLED" -#define _ch2_rx_lol_port "INTERNAL" - -#define _ch3_pll_rxsrc "REFCLK_CORE" -#define _ch3_mode "RXTX" -#define _ch3_protocol "GIGE" -#define _ch3_ldr "DISABLED" -#define _ch3_tx_data_rate "FULL" -#define _ch3_tx_data_width "8" -#define _ch3_tx_fifo "ENABLED" -#define _ch3_tx_ficlk_rate 125.0 -#define _ch3_rx_datarange "MED" -#define _ch3_rx_data_rate "FULL" -#define _ch3_rxrefclk_rate "125.0" -#define _ch3_rx_data_width "8" -#define _ch3_rx_fifo "ENABLED" -#define _ch3_rx_ficlk_rate 125.0 -#define _ch3_tdrv "0" -#define _ch3_tx_pre "DISABLED" -#define _ch3_rterm_tx "50" -#define _ch3_rx_eq "DISABLED" -#define _ch3_rterm_rx "50" -#define _ch3_rx_dcc "AC" -#define _los_threshold_lo3 "2" -#define _ch3_tx_sb "DISABLED" -#define _ch3_tx_8b10b "ENABLED" -#define _ch3_rx_sb "DISABLED" -#define _ch3_ird "DISABLED" -#define _ch3_rx_8b10b "ENABLED" -#define _ch3_rxwa "ENABLED" -#define _ch3_ilsm "ENABLED" -#define _ch3_scomma "K28P5" -#define _ch3_comma_a "1100000101" -#define _ch3_comma_b "0011111010" -#define _ch3_comma_m "1111111111" -#define _ch3_ctc "DISABLED" -#define _ch3_cc_match_mode "2" -#define _ch3_byten "0110111100" -#define _ch3_byten1 "0001010000" -#define _ch3_byten2 "0110111100" -#define _ch3_byten3 "0001010000" -#define _ch3_cc_min_ipg "3" -#define _ch3_lbtype "DISABLED" -#define _ch3_teidle "DISABLED" -#define _ch3_rx_lol_port "INTERNAL" - -#define _datarange "MED" -#define _pll_txsrc "REFCLK_CORE" -#define _refclk_mult "10X" -#define _refclk_rate 125.0 -#define _pll_term "50" -#define _pll_dcc "AC" -#define _pll_lol_set "0" -#define _cchmark "9" -#define _cclmark "7" -#define _rst_gen "DISABLED" -#define _sci_ports "DISABLED" -#define _sci_int_port "DISABLED" -#define _refck2core "DISABLED" -#define _circuit_name serdes_ch4 -#define _lang vhdl - -#include -#include diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.readme b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.readme deleted file mode 100644 index 98e2a4b..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.readme +++ /dev/null @@ -1,141 +0,0 @@ - - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: Lattice Semiconductor Corporation - MODULE: serdes_ch4 - DESIGN: serdes_ch4 - FILENAME: serdes_ch4.readme - PROJECT: Unknown - VERSION: 2.0 - This file is auto generated by the ispLEVER - - -NOTE: This readme file has been provided to instantiate the interface -netlist. Since this template contains synthesis attributes for precision that -are crucial to the design flow, we recommend that you use this -template in your FPGA design. -entity chip is -port ( - --- Add your FPGA design top level I/Os here - - --- ASIC side pins for PCSD. These pins must exist for the --- PCS core. - refclkp : in std_logic; - refclkn : in std_logic; - hdinp_ch0 : in std_logic; - hdinn_ch0 : in std_logic; - hdinp_ch1 : in std_logic; - hdinn_ch1 : in std_logic; - hdinp_ch2 : in std_logic; - hdinn_ch2 : in std_logic; - hdinp_ch3 : in std_logic; - hdinn_ch3 : in std_logic; - - hdoutp_ch0 : out std_logic; - hdoutn_ch0 : out std_logic; - hdoutp_ch1 : out std_logic; - hdoutn_ch1 : out std_logic; - hdoutp_ch2 : out std_logic; - hdoutn_ch2 : out std_logic; - hdoutp_ch3 : out std_logic; - hdoutn_ch3 : out std_logic; - - -); -end chip; - -architecture chip_arch of chip is - --- This defines all the high-speed ports. You may have to remove --- some of them depending on your design. -attribute nopad : string; -attribute nopad of - refclkp, refclkn, - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1, - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3, - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1, - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true"; - - COMPONENT serdes_ch4 - PORT( - hdinp_ch3 : IN std_logic; - hdinn_ch3 : IN std_logic; - rxiclk_ch3 : IN std_logic; - txiclk_ch3 : IN std_logic; - fpga_rxrefclk_ch3 : IN std_logic; - txdata_ch3 : IN std_logic_vector(7 downto 0); - tx_k_ch3 : IN std_logic; - xmit_ch3 : IN std_logic; - tx_disp_correct_ch3 : IN std_logic; - rx_serdes_rst_ch3_c : IN std_logic; - sb_felb_ch3_c : IN std_logic; - sb_felb_rst_ch3_c : IN std_logic; - tx_pcs_rst_ch3_c : IN std_logic; - tx_pwrup_ch3_c : IN std_logic; - rx_pcs_rst_ch3_c : IN std_logic; - rx_pwrup_ch3_c : IN std_logic; - fpga_txrefclk : IN std_logic; - tx_serdes_rst_c : IN std_logic; - rst_qd_c : IN std_logic; - serdes_rst_qd_c : IN std_logic; - hdoutp_ch3 : OUT std_logic; - hdoutn_ch3 : OUT std_logic; - rx_full_clk_ch3 : OUT std_logic; - rx_half_clk_ch3 : OUT std_logic; - tx_full_clk_ch3 : OUT std_logic; - tx_half_clk_ch3 : OUT std_logic; - rxdata_ch3 : OUT std_logic_vector(7 downto 0); - rx_k_ch3 : OUT std_logic; - rx_disp_err_ch3 : OUT std_logic; - rx_cv_err_ch3 : OUT std_logic; - rx_los_low_ch3_s : OUT std_logic; - lsm_status_ch3_s : OUT std_logic; - rx_cdr_lol_ch3_s : OUT std_logic; - tx_pll_lol_qd_s : OUT std_logic - ); - END COMPONENT; - - - - uut: serdes_ch4 PORT MAP( - hdinp_ch3 => hdinp_ch3, - hdinn_ch3 => hdinn_ch3, - hdoutp_ch3 => hdoutp_ch3, - hdoutn_ch3 => hdoutn_ch3, - rxiclk_ch3 => rxiclk_ch3, - txiclk_ch3 => txiclk_ch3, - rx_full_clk_ch3 => rx_full_clk_ch3, - rx_half_clk_ch3 => rx_half_clk_ch3, - tx_full_clk_ch3 => tx_full_clk_ch3, - tx_half_clk_ch3 => tx_half_clk_ch3, - fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3, - txdata_ch3 => txdata_ch3, - tx_k_ch3 => tx_k_ch3, - xmit_ch3 => xmit_ch3, - tx_disp_correct_ch3 => tx_disp_correct_ch3, - rxdata_ch3 => rxdata_ch3, - rx_k_ch3 => rx_k_ch3, - rx_disp_err_ch3 => rx_disp_err_ch3, - rx_cv_err_ch3 => rx_cv_err_ch3, - rx_serdes_rst_ch3_c => rx_serdes_rst_ch3_c, - sb_felb_ch3_c => sb_felb_ch3_c, - sb_felb_rst_ch3_c => sb_felb_rst_ch3_c, - tx_pcs_rst_ch3_c => tx_pcs_rst_ch3_c, - tx_pwrup_ch3_c => tx_pwrup_ch3_c, - rx_pcs_rst_ch3_c => rx_pcs_rst_ch3_c, - rx_pwrup_ch3_c => rx_pwrup_ch3_c, - rx_los_low_ch3_s => rx_los_low_ch3_s, - lsm_status_ch3_s => lsm_status_ch3_s, - rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s, - fpga_txrefclk => fpga_txrefclk, - tx_serdes_rst_c => tx_serdes_rst_c, - tx_pll_lol_qd_s => tx_pll_lol_qd_s, - rst_qd_c => rst_qd_c, - serdes_rst_qd_c => serdes_rst_qd_c - ); - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.sort b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.sort deleted file mode 100644 index 9e836ba..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.sort +++ /dev/null @@ -1 +0,0 @@ -serdes_ch4.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.sym b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.sym deleted file mode 100644 index 9e4bc2056f3cc01409a4b03f74743dc4b3268e15..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1580 zcmZvbKZq1r5XP%sw=z4pvn{)bfgBSIavTN?io&vi$U2A!*TKqxciJ;Mf1JhEZM%E5 zBN@a%#GsMm0=Ynr4Gfl}5d(t@4lxipq>&3m3>GmE5g9}b#K7;>o6&LIfyex&zHjQi zs(Nqj7sAKF+OyTxh#%{!N~wJnKYR8;1akU`YV&~Y-SBkNkJ6~qZ3SoiR&Ou;hOnoO z8hujqWT;c3HR>8|qSszJcTWCu9dVZ~jm1NWuOgnQKTNz7#fg8u?YD>?AnvHYP27o6 zKWxRmmT>^BztH*AW20BJelc2+lv=f!DC9RrorW5BqIPFI!4KL&6_y&yQMxoLj%J}` z{G(AO<3+#Q2^NRjo`9C~ywSFgw6DiXwXWJmpBmd#in$Foz zC!n^QNmG~m>w#JKB-Np2wBM-ZWUNo8pt$TArIemsG9^%7k(E1%HCCV$r1bUGO_mq-|ev&B2p%)vDF^Su_QYOlPBOQD>q$TqlgH zyAoi#;ma7E>ndCW3gGG+SFag#zjNJ&E8`n*-Lj~J9f#8%WhrzPz61TCCDjGXF{-<` zvAPfNHTW5PZ)LY{CpgNs%SKO`>{@-sCVdMwJ^3NHT;2`WtZ{96ax~5I)G@dk#ucIo zy6?E>dOT*%L^I{#RcrP35%ujp7wRzdK09=nf5$UjR~}~QsawLX%yUiH0XyoRFzz=x z@j$o$7hDME;GCZeXW)!q*%Qdw05|x(#9c7f7QL4Pc6gic05uF~r*Hu-s3x3)b8>|< za7J@r!n>|w9TCpJnOYDI!J%phdtgrm!Y diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.tft b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.tft deleted file mode 100644 index b9db080..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.tft +++ /dev/null @@ -1,100 +0,0 @@ -@set suppresnewline=on@ - -@comment --------------------------------------------------------------------- @ -@comment Template-drive TFI generator @ -@comment Template for TFI generation. @ -@comment --------------------------------------------------------------------- @ - -@set suppresnewline=off@ - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: %title% - MODULE: %module% - DESIGN: %module% - FILENAME: %filename% - PROJECT: %project% - VERSION: %ver% - This file is auto generated by the ispLEVER -@set suppresnewline=on@ - -@cr@ -@cr@ - -@set sigdelim=@ - -NOTE: This readme file has been provided to instantiate the interface@cr@ -netlist. Since this template contains synthesis attributes for precision that@cr@ -are crucial to the design flow, we recommend that you use this@cr@ -template in your FPGA design.@cr@ -entity chip is@cr@ -port (@cr@ -@cr@ --- Add your FPGA design top level I/Os here@cr@ -@cr@ -@cr@ --- ASIC side pins for PCSD. These pins must exist for the@cr@ --- PCS core.@cr@ - refclkp : in std_logic;@cr@ - refclkn : in std_logic;@cr@ - hdinp_ch0 : in std_logic;@cr@ - hdinn_ch0 : in std_logic;@cr@ - hdinp_ch1 : in std_logic;@cr@ - hdinn_ch1 : in std_logic;@cr@ - hdinp_ch2 : in std_logic;@cr@ - hdinn_ch2 : in std_logic;@cr@ - hdinp_ch3 : in std_logic;@cr@ - hdinn_ch3 : in std_logic;@cr@ -@cr@ - hdoutp_ch0 : out std_logic;@cr@ - hdoutn_ch0 : out std_logic;@cr@ - hdoutp_ch1 : out std_logic;@cr@ - hdoutn_ch1 : out std_logic;@cr@ - hdoutp_ch2 : out std_logic;@cr@ - hdoutn_ch2 : out std_logic;@cr@ - hdoutp_ch3 : out std_logic;@cr@ - hdoutn_ch3 : out std_logic;@cr@ -@cr@ -@cr@ -);@cr@ -end chip;@cr@ -@cr@ -architecture chip_arch of chip is@cr@ -@cr@ --- This defines all the high-speed ports. You may have to remove@cr@ --- some of them depending on your design.@cr@ -attribute nopad : string;@cr@ -attribute nopad of@cr@ - refclkp, refclkn,@cr@ - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@ - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@ - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@ - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@ - -@cr@ -@tab@COMPONENT %module% -@set sigdelim=@ -@cr@@tab@PORT( -@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ -@ifhas oport=*@ @comment if the design has any output ports... @ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ - @set sigdelim=;@ - @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ -@endif@ -@ifnhas oport=*@ @comment we need an "else in this language! @ - @set sigdelim=;@ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ -@endif@ -@cr@@tab@@tab@);@cr@ -@tab@END COMPONENT;@cr@@cr@ -@comment Now do a signal declaration for each port @ - -@cr@@cr@ -@comment do the component instantiation @ -@set sigdelim=,@ -@tab@uut: %module% PORT MAP( -@iterate@%port% -@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ -@cr@@tab@);@cr@@cr@ -@set suppresnewline=off@ - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt deleted file mode 100644 index 6b3b65f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt +++ /dev/null @@ -1,59 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH3_PROTOCOL "GIGE" -CH0_MODE "DISABLED" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "RXTX" -CH3_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MED" -CH3_RX_DATARATE_RANGE "MED" -REFCK_MULT "10X" -#REFCLK_RATE 125.0 -CH3_RX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" -CH3_TX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" -CH3_TX_FIFO "ENABLED" -CH3_RX_FIFO "ENABLED" -CH3_TDRV "0" -#CH3_TX_FICLK_RATE 125.0 -#CH3_RXREFCLK_RATE "125.0" -#CH3_RX_FICLK_RATE 125.0 -CH3_TX_PRE "DISABLED" -CH3_RTERM_TX "50" -CH3_RX_EQ "DISABLED" -CH3_RTERM_RX "50" -CH3_RX_DCC "AC" -CH3_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH3_TX_SB "DISABLED" -CH3_RX_SB "DISABLED" -CH3_TX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" -CH3_COMMA_A "1100000101" -CH3_COMMA_B "0011111010" -CH3_COMMA_M "1111111111" -CH3_RXWA "ENABLED" -CH3_ILSM "ENABLED" -CH3_CTC "DISABLED" -CH3_CC_MATCH3 "0110111100" -CH3_CC_MATCH4 "0001010000" -CH3_CC_MATCH_MODE "2" -CH3_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH3_SSLB "DISABLED" -CH3_SPLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "DISABLED" - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd b/gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd deleted file mode 100644 index 9f3f819..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd +++ /dev/null @@ -1,2689 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_ch4.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_EXT"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_CORE"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - - - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_ch4 is - GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt"); - port ( ------------------- --- CH0 -- --- CH1 -- --- CH2 -- --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (7 downto 0); - tx_k_ch3 : in std_logic; - xmit_ch3 : in std_logic; - tx_disp_correct_ch3 : in std_logic; - rxdata_ch3 : out std_logic_vector (7 downto 0); - rx_k_ch3 : out std_logic; - rx_disp_err_ch3 : out std_logic; - rx_cv_err_ch3 : out std_logic; - rx_serdes_rst_ch3_c : in std_logic; - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pcs_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pcs_rst_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_ch4; - - -architecture serdes_ch4_arch of serdes_ch4 is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - - - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH3_CDR_SRC: string; - attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch3_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - - - - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - rx_los_low_ch3_s <= rx_los_low_ch3_sig; - rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch3 <= tx_full_clk_ch3_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH3_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => open, - HDOUTN0 => open, - HDINP0 => fpsc_vlo, - HDINN0 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => fpsc_vlo, - FF_TXI_CLK_0 => fpsc_vlo, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => open, - FF_RX_H_CLK_0 => open, - FF_TX_F_CLK_0 => open, - FF_TX_H_CLK_0 => open, - FFC_CK_CORE_RX_0 => fpsc_vlo, - FF_TX_D_0_0 => fpsc_vlo, - FF_TX_D_0_1 => fpsc_vlo, - FF_TX_D_0_2 => fpsc_vlo, - FF_TX_D_0_3 => fpsc_vlo, - FF_TX_D_0_4 => fpsc_vlo, - FF_TX_D_0_5 => fpsc_vlo, - FF_TX_D_0_6 => fpsc_vlo, - FF_TX_D_0_7 => fpsc_vlo, - FF_TX_D_0_8 => fpsc_vlo, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => fpsc_vlo, - FF_TX_D_0_11 => fpsc_vlo, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => open, - FF_RX_D_0_1 => open, - FF_RX_D_0_2 => open, - FF_RX_D_0_3 => open, - FF_RX_D_0_4 => open, - FF_RX_D_0_5 => open, - FF_RX_D_0_6 => open, - FF_RX_D_0_7 => open, - FF_RX_D_0_8 => open, - FF_RX_D_0_9 => open, - FF_RX_D_0_10 => open, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => fpsc_vlo, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => fpsc_vlo, - FFC_TXPWDNB_0 => fpsc_vlo, - FFC_LANE_RX_RST_0 => fpsc_vlo, - FFC_RXPWDNB_0 => fpsc_vlo, - FFS_RLOS_LO_0 => open, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => fpsc_vlo, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => fpsc_vlo, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => hdoutp_ch3, - HDOUTN3 => hdoutn_ch3, - HDINP3 => hdinp_ch3, - HDINN3 => hdinn_ch3, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => rxiclk_ch3, - FF_TXI_CLK_3 => txiclk_ch3, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => rx_full_clk_ch3, - FF_RX_H_CLK_3 => rx_half_clk_ch3, - FF_TX_F_CLK_3 => tx_full_clk_ch3_sig, - FF_TX_H_CLK_3 => tx_half_clk_ch3, - FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3, - FF_TX_D_3_0 => txdata_ch3(0), - FF_TX_D_3_1 => txdata_ch3(1), - FF_TX_D_3_2 => txdata_ch3(2), - FF_TX_D_3_3 => txdata_ch3(3), - FF_TX_D_3_4 => txdata_ch3(4), - FF_TX_D_3_5 => txdata_ch3(5), - FF_TX_D_3_6 => txdata_ch3(6), - FF_TX_D_3_7 => txdata_ch3(7), - FF_TX_D_3_8 => tx_k_ch3, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => xmit_ch3, - FF_TX_D_3_11 => tx_disp_correct_ch3, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => rxdata_ch3(0), - FF_RX_D_3_1 => rxdata_ch3(1), - FF_RX_D_3_2 => rxdata_ch3(2), - FF_RX_D_3_3 => rxdata_ch3(3), - FF_RX_D_3_4 => rxdata_ch3(4), - FF_RX_D_3_5 => rxdata_ch3(5), - FF_RX_D_3_6 => rxdata_ch3(6), - FF_RX_D_3_7 => rxdata_ch3(7), - FF_RX_D_3_8 => rx_k_ch3, - FF_RX_D_3_9 => rx_disp_err_ch3, - FF_RX_D_3_10 => rx_cv_err_ch3, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => rx_serdes_rst_ch3_c, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c, - FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c, - FFC_TXPWDNB_3 => tx_pwrup_ch3_c, - FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c, - FFC_RXPWDNB_3 => rx_pwrup_ch3_c, - FFS_RLOS_LO_3 => rx_los_low_ch3_sig, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => rx_cdr_lol_ch3_sig, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA0 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIRDATA7 => open, - SCIRDATA6 => open, - SCIRDATA5 => open, - SCIRDATA4 => open, - SCIRDATA3 => open, - SCIRDATA2 => open, - SCIRDATA1 => open, - SCIRDATA0 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - - - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_ch4_arch ; diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_ch4_generate.log b/gbe2_ecp3/ipcores_ecp3/serdes_ch4_generate.log deleted file mode 100644 index 26130c0..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_ch4_generate.log +++ /dev/null @@ -1,29 +0,0 @@ -Starting process: Module - -Starting process: - - Module Name: serdes_ch4 - Core Name: PCS - LPC file : serdes_ch4.lpc - Parameter File : serdes_ch4.pp - Command line: /opt/lattice/diamond/1.4/ispfpga/bin/lin/orcapp -Fmaco serdes_ch4.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/. successfully! - -/opt/lattice/diamond/1.4/bin/lin/hdl2jhd -tfi -mod serdes_ch4 -ext readme -out serdes_ch4 -tpl serdes_ch4.tft serdes_ch4.vhd - -Done successfully! -File: serdes_ch4.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/dummy_sym.sort b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/dummy_sym.sort deleted file mode 100644 index a1712c9..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/dummy_sym.sort +++ /dev/null @@ -1 +0,0 @@ -dummy_sym.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/msg_file.log b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/msg_file.log deleted file mode 100644 index ada5650..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/msg_file.log +++ /dev/null @@ -1,14 +0,0 @@ - Module Name: serdes_gbe_0ch - Core Name: PCS - LPC file : serdes_gbe_0ch.lpc - Parameter File : serdes_gbe_0ch.pp - Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0ch.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/simple_test/ipcores/serdes_gbe_0ch/. successfully! - -/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0ch -ext readme -out serdes_gbe_0ch -tpl serdes_gbe_0ch.tft serdes_gbe_0ch.vhd - -Done successfully! diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.ipx b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.ipx deleted file mode 100644 index 012c405..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.jhd b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.jhd deleted file mode 100644 index 9fdc304..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.jhd +++ /dev/null @@ -1,7 +0,0 @@ -MODULE serdes_gbe_0ch DEFIN serdes_gbe_0ch.vhd - SUBMODULE PCSD - INSTANCE PCSD_INST - SUBMODULE VHI - INSTANCE vhi_inst - SUBMODULE VLO - INSTANCE vlo_inst diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.lpc b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.lpc deleted file mode 100644 index 6db75a5..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-6FN1156C -SpeedGrade=6 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_gbe_0ch -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=11/30/2011 -Time=14:02:46 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=RXTX -_mode1=DISABLED -_mode2=DISABLED -_mode3=DISABLED -_protocol0=GIGE -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=1.25 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=125.0 -_tx_protocol0=GIGE -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=DISABLED -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=125.0 -_tx_ficlk_rate1=125.0 -_tx_ficlk_rate2=125.0 -_tx_ficlk_rate3=125.0 -_pll_rxsrc0=INTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=EXTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=1.25 -_rx_datarange1=2.5 -_rx_datarange2=2.5 -_rx_datarange3=2.5 -_rx_protocol0=GIGE -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=DISABLED -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=125.0 -_rxrefclk_rate1=250.0 -_rxrefclk_rate2=250.0 -_rxrefclk_rate3=250.0 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=ENABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=ENABLED -_rx_ficlk_rate0=125.0 -_rx_ficlk_rate1=250.0 -_rx_ficlk_rate2=250.0 -_rx_ficlk_rate3=250.0 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=AC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=AC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P5 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111111 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=2 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=01 -_k01=00 -_k02=00 -_k03=00 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=00 -_k31=01 -_k32=01 -_k33=01 -_byten00=10111100 -_byten01=00000000 -_byten02=00000000 -_byten03=00000000 -_byten10=01010000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=10111100 -_byten21=00011100 -_byten22=00011100 -_byten23=00011100 -_byten30=01010000 -_byten31=00011100 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=DISABLED -_sci_int_port=DISABLED -_refck2core=DISABLED -Regen=auto -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_gbe_0ch.pp=pp -serdes_gbe_0ch.tft=tft -serdes_gbe_0ch.txt=pcs_module -serdes_gbe_0ch.sym=sym diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.naf b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.naf deleted file mode 100644 index f56b8f4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.naf +++ /dev/null @@ -1,48 +0,0 @@ -hdinp_ch0 i -hdinn_ch0 i -hdoutp_ch0 o -hdoutn_ch0 o -rxiclk_ch0 i -txiclk_ch0 i -rx_full_clk_ch0 o -rx_half_clk_ch0 o -tx_full_clk_ch0 o -tx_half_clk_ch0 o -fpga_rxrefclk_ch0 i -txdata_ch0[7] i -txdata_ch0[6] i -txdata_ch0[5] i -txdata_ch0[4] i -txdata_ch0[3] i -txdata_ch0[2] i -txdata_ch0[1] i -txdata_ch0[0] i -tx_k_ch0 i -xmit_ch0 i -tx_disp_correct_ch0 i -rxdata_ch0[7] o -rxdata_ch0[6] o -rxdata_ch0[5] o -rxdata_ch0[4] o -rxdata_ch0[3] o -rxdata_ch0[2] o -rxdata_ch0[1] o -rxdata_ch0[0] o -rx_k_ch0 o -rx_disp_err_ch0 o -rx_cv_err_ch0 o -rx_serdes_rst_ch0_c i -sb_felb_ch0_c i -sb_felb_rst_ch0_c i -tx_pcs_rst_ch0_c i -tx_pwrup_ch0_c i -rx_pcs_rst_ch0_c i -rx_pwrup_ch0_c i -rx_los_low_ch0_s o -lsm_status_ch0_s o -rx_cdr_lol_ch0_s o -fpga_txrefclk i -tx_serdes_rst_c i -tx_pll_lol_qd_s o -rst_qd_c i -serdes_rst_qd_c i diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.pp b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.pp deleted file mode 100644 index 6a85bbd..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.pp +++ /dev/null @@ -1,195 +0,0 @@ -#define _device_name "LFE3-150EA" -#define _ch0_pll_rxsrc "REFCLK_CORE" -#define _ch0_mode "RXTX" -#define _ch0_protocol "GIGE" -#define _ch0_ldr "DISABLED" -#define _ch0_tx_data_rate "FULL" -#define _ch0_tx_data_width "8" -#define _ch0_tx_fifo "ENABLED" -#define _ch0_tx_ficlk_rate 125.0 -#define _ch0_rx_datarange "MED" -#define _ch0_rx_data_rate "FULL" -#define _ch0_rxrefclk_rate "125.0" -#define _ch0_rx_data_width "8" -#define _ch0_rx_fifo "ENABLED" -#define _ch0_rx_ficlk_rate 125.0 -#define _ch0_tdrv "0" -#define _ch0_tx_pre "DISABLED" -#define _ch0_rterm_tx "50" -#define _ch0_rx_eq "DISABLED" -#define _ch0_rterm_rx "50" -#define _ch0_rx_dcc "AC" -#define _los_threshold_mode0 "LOS_E" -#define _los_threshold_lo0 "2" -#define _ch0_tx_sb "DISABLED" -#define _ch0_tx_8b10b "ENABLED" -#define _ch0_rx_sb "DISABLED" -#define _ch0_ird "DISABLED" -#define _ch0_rx_8b10b "ENABLED" -#define _ch0_rxwa "ENABLED" -#define _ch0_ilsm "ENABLED" -#define _ch0_scomma "K28P5" -#define _ch0_comma_a "1100000101" -#define _ch0_comma_b "0011111010" -#define _ch0_comma_m "1111111111" -#define _ch0_ctc "DISABLED" -#define _ch0_cc_match_mode "2" -#define _ch0_byten "0110111100" -#define _ch0_byten1 "0001010000" -#define _ch0_byten2 "0110111100" -#define _ch0_byten3 "0001010000" -#define _ch0_cc_min_ipg "3" -#define _ch0_lbtype "DISABLED" -#define _ch0_teidle "DISABLED" -#define _ch0_rx_lol_port "INTERNAL" - -#define _ch1_pll_rxsrc "REFCLK_EXT" -#define _ch1_mode "DISABLED" -#define _ch1_protocol "G8B10B" -#define _ch1_ldr "DISABLED" -#define _ch1_tx_data_rate "FULL" -#define _ch1_tx_data_width "8" -#define _ch1_tx_fifo "ENABLED" -#define _ch1_tx_ficlk_rate 125.0 -#define _ch1_rx_datarange "MEDHIGH" -#define _ch1_rx_data_rate "FULL" -#define _ch1_rxrefclk_rate "250.0" -#define _ch1_rx_data_width "8" -#define _ch1_rx_fifo "ENABLED" -#define _ch1_rx_ficlk_rate 250.0 -#define _ch1_tdrv "0" -#define _ch1_tx_pre "DISABLED" -#define _ch1_rterm_tx "50" -#define _ch1_rx_eq "DISABLED" -#define _ch1_rterm_rx "50" -#define _ch1_rx_dcc "AC" -#define _los_threshold_mode1 "LOS_E" -#define _los_threshold_lo1 "2" -#define _ch1_tx_sb "DISABLED" -#define _ch1_tx_8b10b "ENABLED" -#define _ch1_rx_sb "DISABLED" -#define _ch1_ird "DISABLED" -#define _ch1_rx_8b10b "ENABLED" -#define _ch1_rxwa "ENABLED" -#define _ch1_ilsm "ENABLED" -#define _ch1_scomma "K28P157" -#define _ch1_comma_a "1100000101" -#define _ch1_comma_b "0011111010" -#define _ch1_comma_m "1111111100" -#define _ch1_ctc "DISABLED" -#define _ch1_cc_match_mode "1" -#define _ch1_byten "0000000000" -#define _ch1_byten1 "0000000000" -#define _ch1_byten2 "0100011100" -#define _ch1_byten3 "0100011100" -#define _ch1_cc_min_ipg "3" -#define _ch1_lbtype "DISABLED" -#define _ch1_teidle "DISABLED" -#define _ch1_rx_lol_port "INTERNAL" - -#define _ch2_pll_rxsrc "REFCLK_EXT" -#define _ch2_mode "DISABLED" -#define _ch2_protocol "G8B10B" -#define _ch2_ldr "DISABLED" -#define _ch2_tx_data_rate "FULL" -#define _ch2_tx_data_width "8" -#define _ch2_tx_fifo "ENABLED" -#define _ch2_tx_ficlk_rate 125.0 -#define _ch2_rx_datarange "MEDHIGH" -#define _ch2_rx_data_rate "FULL" -#define _ch2_rxrefclk_rate "250.0" -#define _ch2_rx_data_width "8" -#define _ch2_rx_fifo "ENABLED" -#define _ch2_rx_ficlk_rate 250.0 -#define _ch2_tdrv "0" -#define _ch2_tx_pre "DISABLED" -#define _ch2_rterm_tx "50" -#define _ch2_rx_eq "DISABLED" -#define _ch2_rterm_rx "50" -#define _ch2_rx_dcc "AC" -#define _los_threshold_mode2 "LOS_E" -#define _los_threshold_lo2 "2" -#define _ch2_tx_sb "DISABLED" -#define _ch2_tx_8b10b "ENABLED" -#define _ch2_rx_sb "DISABLED" -#define _ch2_ird "DISABLED" -#define _ch2_rx_8b10b "ENABLED" -#define _ch2_rxwa "ENABLED" -#define _ch2_ilsm "ENABLED" -#define _ch2_scomma "K28P157" -#define _ch2_comma_a "1100000101" -#define _ch2_comma_b "0011111010" -#define _ch2_comma_m "1111111100" -#define _ch2_ctc "DISABLED" -#define _ch2_cc_match_mode "1" -#define _ch2_byten "0000000000" -#define _ch2_byten1 "0000000000" -#define _ch2_byten2 "0100011100" -#define _ch2_byten3 "0100011100" -#define _ch2_cc_min_ipg "3" -#define _ch2_lbtype "DISABLED" -#define _ch2_teidle "DISABLED" -#define _ch2_rx_lol_port "INTERNAL" - -#define _ch3_pll_rxsrc "REFCLK_EXT" -#define _ch3_mode "DISABLED" -#define _ch3_protocol "G8B10B" -#define _ch3_ldr "DISABLED" -#define _ch3_tx_data_rate "FULL" -#define _ch3_tx_data_width "8" -#define _ch3_tx_fifo "ENABLED" -#define _ch3_tx_ficlk_rate 125.0 -#define _ch3_rx_datarange "MEDHIGH" -#define _ch3_rx_data_rate "FULL" -#define _ch3_rxrefclk_rate "250.0" -#define _ch3_rx_data_width "8" -#define _ch3_rx_fifo "ENABLED" -#define _ch3_rx_ficlk_rate 250.0 -#define _ch3_tdrv "0" -#define _ch3_tx_pre "DISABLED" -#define _ch3_rterm_tx "50" -#define _ch3_rx_eq "DISABLED" -#define _ch3_rterm_rx "50" -#define _ch3_rx_dcc "AC" -#define _los_threshold_mode3 "LOS_E" -#define _los_threshold_lo3 "2" -#define _ch3_tx_sb "DISABLED" -#define _ch3_tx_8b10b "ENABLED" -#define _ch3_rx_sb "DISABLED" -#define _ch3_ird "DISABLED" -#define _ch3_rx_8b10b "ENABLED" -#define _ch3_rxwa "ENABLED" -#define _ch3_ilsm "ENABLED" -#define _ch3_scomma "K28P157" -#define _ch3_comma_a "1100000101" -#define _ch3_comma_b "0011111010" -#define _ch3_comma_m "1111111100" -#define _ch3_ctc "DISABLED" -#define _ch3_cc_match_mode "1" -#define _ch3_byten "0000000000" -#define _ch3_byten1 "0000000000" -#define _ch3_byten2 "0100011100" -#define _ch3_byten3 "0100011100" -#define _ch3_cc_min_ipg "3" -#define _ch3_lbtype "DISABLED" -#define _ch3_teidle "DISABLED" -#define _ch3_rx_lol_port "INTERNAL" - -#define _datarange "MED" -#define _pll_txsrc "REFCLK_CORE" -#define _refclk_mult "10X" -#define _refclk_rate 125.0 -#define _pll_term "50" -#define _pll_dcc "AC" -#define _pll_lol_set "0" -#define _cchmark "9" -#define _cclmark "7" -#define _rst_gen "DISABLED" -#define _sci_ports "DISABLED" -#define _sci_int_port "DISABLED" -#define _refck2core "DISABLED" -#define _circuit_name serdes_gbe_0ch -#define _lang vhdl - -#include -#include diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.readme b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.readme deleted file mode 100644 index 90abab8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.readme +++ /dev/null @@ -1,141 +0,0 @@ - - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: Lattice Semiconductor Corporation - MODULE: serdes_gbe_0ch - DESIGN: serdes_gbe_0ch - FILENAME: serdes_gbe_0ch.readme - PROJECT: Unknown - VERSION: 2.0 - This file is auto generated by the ispLEVER - - -NOTE: This readme file has been provided to instantiate the interface -netlist. Since this template contains synthesis attributes for precision that -are crucial to the design flow, we recommend that you use this -template in your FPGA design. -entity chip is -port ( - --- Add your FPGA design top level I/Os here - - --- ASIC side pins for PCSD. These pins must exist for the --- PCS core. - refclkp : in std_logic; - refclkn : in std_logic; - hdinp_ch0 : in std_logic; - hdinn_ch0 : in std_logic; - hdinp_ch1 : in std_logic; - hdinn_ch1 : in std_logic; - hdinp_ch2 : in std_logic; - hdinn_ch2 : in std_logic; - hdinp_ch3 : in std_logic; - hdinn_ch3 : in std_logic; - - hdoutp_ch0 : out std_logic; - hdoutn_ch0 : out std_logic; - hdoutp_ch1 : out std_logic; - hdoutn_ch1 : out std_logic; - hdoutp_ch2 : out std_logic; - hdoutn_ch2 : out std_logic; - hdoutp_ch3 : out std_logic; - hdoutn_ch3 : out std_logic; - - -); -end chip; - -architecture chip_arch of chip is - --- This defines all the high-speed ports. You may have to remove --- some of them depending on your design. -attribute nopad : string; -attribute nopad of - refclkp, refclkn, - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1, - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3, - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1, - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true"; - - COMPONENT serdes_gbe_0ch - PORT( - hdinp_ch0 : IN std_logic; - hdinn_ch0 : IN std_logic; - rxiclk_ch0 : IN std_logic; - txiclk_ch0 : IN std_logic; - fpga_rxrefclk_ch0 : IN std_logic; - txdata_ch0 : IN std_logic_vector(7 downto 0); - tx_k_ch0 : IN std_logic; - xmit_ch0 : IN std_logic; - tx_disp_correct_ch0 : IN std_logic; - rx_serdes_rst_ch0_c : IN std_logic; - sb_felb_ch0_c : IN std_logic; - sb_felb_rst_ch0_c : IN std_logic; - tx_pcs_rst_ch0_c : IN std_logic; - tx_pwrup_ch0_c : IN std_logic; - rx_pcs_rst_ch0_c : IN std_logic; - rx_pwrup_ch0_c : IN std_logic; - fpga_txrefclk : IN std_logic; - tx_serdes_rst_c : IN std_logic; - rst_qd_c : IN std_logic; - serdes_rst_qd_c : IN std_logic; - hdoutp_ch0 : OUT std_logic; - hdoutn_ch0 : OUT std_logic; - rx_full_clk_ch0 : OUT std_logic; - rx_half_clk_ch0 : OUT std_logic; - tx_full_clk_ch0 : OUT std_logic; - tx_half_clk_ch0 : OUT std_logic; - rxdata_ch0 : OUT std_logic_vector(7 downto 0); - rx_k_ch0 : OUT std_logic; - rx_disp_err_ch0 : OUT std_logic; - rx_cv_err_ch0 : OUT std_logic; - rx_los_low_ch0_s : OUT std_logic; - lsm_status_ch0_s : OUT std_logic; - rx_cdr_lol_ch0_s : OUT std_logic; - tx_pll_lol_qd_s : OUT std_logic - ); - END COMPONENT; - - - - uut: serdes_gbe_0ch PORT MAP( - hdinp_ch0 => hdinp_ch0, - hdinn_ch0 => hdinn_ch0, - hdoutp_ch0 => hdoutp_ch0, - hdoutn_ch0 => hdoutn_ch0, - rxiclk_ch0 => rxiclk_ch0, - txiclk_ch0 => txiclk_ch0, - rx_full_clk_ch0 => rx_full_clk_ch0, - rx_half_clk_ch0 => rx_half_clk_ch0, - tx_full_clk_ch0 => tx_full_clk_ch0, - tx_half_clk_ch0 => tx_half_clk_ch0, - fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0, - txdata_ch0 => txdata_ch0, - tx_k_ch0 => tx_k_ch0, - xmit_ch0 => xmit_ch0, - tx_disp_correct_ch0 => tx_disp_correct_ch0, - rxdata_ch0 => rxdata_ch0, - rx_k_ch0 => rx_k_ch0, - rx_disp_err_ch0 => rx_disp_err_ch0, - rx_cv_err_ch0 => rx_cv_err_ch0, - rx_serdes_rst_ch0_c => rx_serdes_rst_ch0_c, - sb_felb_ch0_c => sb_felb_ch0_c, - sb_felb_rst_ch0_c => sb_felb_rst_ch0_c, - tx_pcs_rst_ch0_c => tx_pcs_rst_ch0_c, - tx_pwrup_ch0_c => tx_pwrup_ch0_c, - rx_pcs_rst_ch0_c => rx_pcs_rst_ch0_c, - rx_pwrup_ch0_c => rx_pwrup_ch0_c, - rx_los_low_ch0_s => rx_los_low_ch0_s, - lsm_status_ch0_s => lsm_status_ch0_s, - rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s, - fpga_txrefclk => fpga_txrefclk, - tx_serdes_rst_c => tx_serdes_rst_c, - tx_pll_lol_qd_s => tx_pll_lol_qd_s, - rst_qd_c => rst_qd_c, - serdes_rst_qd_c => serdes_rst_qd_c - ); - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.sort b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.sort deleted file mode 100644 index 5de7180..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.sort +++ /dev/null @@ -1 +0,0 @@ -serdes_gbe_0ch.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.sym b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.sym deleted file mode 100644 index 95861722d1291e4b3030f35121d554546185b571..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1584 zcmZvbKZw*&5XNU-qTC(cUPKWKku4Sxv3P|j92O$Fg$Sll6#wP+HoNX&^kS0JEkq8n z5U~g%B32?-SR4|pEUd&rEF_4PSS(f|B8!NKSopnpySkn(g#Bf{FZ15aytjOm@N@9! z)viIj^i-8DyEpOLarYol&^D^=1FUVwXBt7$OB>kvmiQ9lxw>QHV@a9?7s8-P^c-~B#4UCKp82!D; zr(RjTV)RSNf}}L6%S17Mvg$ghX)6g^qX{+}2US>VoJhKJ!{TTfO3quYGMUZ>?N&59 zSoS!yg7;Z%?NIx(t*+5kX!WU)MWv{FP<_5?)pc1n2-Mjv{g-&wt4^wDlq6lzsJtU3jCWMfU*4z))cm2?7X*vJ~D+!MQ| z^(m@D&1t7qC$f<~ora>>x5`-e+?*|e78N-KbyTh1RW#8F=NB@21TZmn4jnm658%k@ z1|0W>4tp4WJ6^)!sbx5xDe|K9T##msY$25~q_7P#eSuG_H}HLg4|8sYNf6CPD}5Ur za!URQU&WzGTn&muJ%HNcdw4d+ds`iwRIr?fzSj$WcVGr!7r@}bn=*A1-5?t~d z;R0N6PdEqX{K*|h&Kd9wf0wuhYj#(ewLGxLo^T&^^l6iD2`*`?Z~-o8hj0$gX%Coi zx2t##3g_Tl9TSehu?mHKu&-ia4c6+ium|?kb>Ti&abIr>m*A4`3m4#mmxXh1&QFA6 zaLmtzeX!4^um)>>C+vYe{;+DC%zdun`6}@OToA1``_I8Str3pFF>Ms~!9LZ5HCV$t Kfq!IDJ@pIb%UlEi diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.tft b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.tft deleted file mode 100644 index b9db080..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.tft +++ /dev/null @@ -1,100 +0,0 @@ -@set suppresnewline=on@ - -@comment --------------------------------------------------------------------- @ -@comment Template-drive TFI generator @ -@comment Template for TFI generation. @ -@comment --------------------------------------------------------------------- @ - -@set suppresnewline=off@ - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: %title% - MODULE: %module% - DESIGN: %module% - FILENAME: %filename% - PROJECT: %project% - VERSION: %ver% - This file is auto generated by the ispLEVER -@set suppresnewline=on@ - -@cr@ -@cr@ - -@set sigdelim=@ - -NOTE: This readme file has been provided to instantiate the interface@cr@ -netlist. Since this template contains synthesis attributes for precision that@cr@ -are crucial to the design flow, we recommend that you use this@cr@ -template in your FPGA design.@cr@ -entity chip is@cr@ -port (@cr@ -@cr@ --- Add your FPGA design top level I/Os here@cr@ -@cr@ -@cr@ --- ASIC side pins for PCSD. These pins must exist for the@cr@ --- PCS core.@cr@ - refclkp : in std_logic;@cr@ - refclkn : in std_logic;@cr@ - hdinp_ch0 : in std_logic;@cr@ - hdinn_ch0 : in std_logic;@cr@ - hdinp_ch1 : in std_logic;@cr@ - hdinn_ch1 : in std_logic;@cr@ - hdinp_ch2 : in std_logic;@cr@ - hdinn_ch2 : in std_logic;@cr@ - hdinp_ch3 : in std_logic;@cr@ - hdinn_ch3 : in std_logic;@cr@ -@cr@ - hdoutp_ch0 : out std_logic;@cr@ - hdoutn_ch0 : out std_logic;@cr@ - hdoutp_ch1 : out std_logic;@cr@ - hdoutn_ch1 : out std_logic;@cr@ - hdoutp_ch2 : out std_logic;@cr@ - hdoutn_ch2 : out std_logic;@cr@ - hdoutp_ch3 : out std_logic;@cr@ - hdoutn_ch3 : out std_logic;@cr@ -@cr@ -@cr@ -);@cr@ -end chip;@cr@ -@cr@ -architecture chip_arch of chip is@cr@ -@cr@ --- This defines all the high-speed ports. You may have to remove@cr@ --- some of them depending on your design.@cr@ -attribute nopad : string;@cr@ -attribute nopad of@cr@ - refclkp, refclkn,@cr@ - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@ - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@ - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@ - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@ - -@cr@ -@tab@COMPONENT %module% -@set sigdelim=@ -@cr@@tab@PORT( -@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ -@ifhas oport=*@ @comment if the design has any output ports... @ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ - @set sigdelim=;@ - @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ -@endif@ -@ifnhas oport=*@ @comment we need an "else in this language! @ - @set sigdelim=;@ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ -@endif@ -@cr@@tab@@tab@);@cr@ -@tab@END COMPONENT;@cr@@cr@ -@comment Now do a signal declaration for each port @ - -@cr@@cr@ -@comment do the component instantiation @ -@set sigdelim=,@ -@tab@uut: %module% PORT MAP( -@iterate@%port% -@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ -@cr@@tab@);@cr@@cr@ -@set suppresnewline=off@ - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt deleted file mode 100644 index 17ddaaf..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt +++ /dev/null @@ -1,59 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "GIGE" -CH0_MODE "RXTX" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "DISABLED" -CH0_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MED" -CH0_RX_DATARATE_RANGE "MED" -REFCK_MULT "10X" -#REFCLK_RATE 125.0 -CH0_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH0_TX_FIFO "ENABLED" -CH0_RX_FIFO "ENABLED" -CH0_TDRV "0" -#CH0_TX_FICLK_RATE 125.0 -#CH0_RXREFCLK_RATE "125.0" -#CH0_RX_FICLK_RATE 125.0 -CH0_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -CH0_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH0_COMMA_M "1111111111" -CH0_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH0_CC_MATCH3 "0110111100" -CH0_CC_MATCH4 "0001010000" -CH0_CC_MATCH_MODE "2" -CH0_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "DISABLED" - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd deleted file mode 100644 index ecb6a65..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd +++ /dev/null @@ -1,2689 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_gbe_0ch.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_CORE"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_EXT"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - - - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0ch is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0ch.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - xmit_ch0 : in std_logic; - tx_disp_correct_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_gbe_0ch; - - -architecture serdes_gbe_0ch_arch of serdes_gbe_0ch is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - - - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH0_CDR_SRC: string; - attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch0_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - - - - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - rx_los_low_ch0_s <= rx_los_low_ch0_sig; - rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch0 <= tx_full_clk_ch0_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH0_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => hdoutp_ch0, - HDOUTN0 => hdoutn_ch0, - HDINP0 => hdinp_ch0, - HDINN0 => hdinn_ch0, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => rxiclk_ch0, - FF_TXI_CLK_0 => txiclk_ch0, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => rx_full_clk_ch0, - FF_RX_H_CLK_0 => rx_half_clk_ch0, - FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, - FF_TX_H_CLK_0 => tx_half_clk_ch0, - FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, - FF_TX_D_0_0 => txdata_ch0(0), - FF_TX_D_0_1 => txdata_ch0(1), - FF_TX_D_0_2 => txdata_ch0(2), - FF_TX_D_0_3 => txdata_ch0(3), - FF_TX_D_0_4 => txdata_ch0(4), - FF_TX_D_0_5 => txdata_ch0(5), - FF_TX_D_0_6 => txdata_ch0(6), - FF_TX_D_0_7 => txdata_ch0(7), - FF_TX_D_0_8 => tx_k_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => xmit_ch0, - FF_TX_D_0_11 => tx_disp_correct_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => rxdata_ch0(0), - FF_RX_D_0_1 => rxdata_ch0(1), - FF_RX_D_0_2 => rxdata_ch0(2), - FF_RX_D_0_3 => rxdata_ch0(3), - FF_RX_D_0_4 => rxdata_ch0(4), - FF_RX_D_0_5 => rxdata_ch0(5), - FF_RX_D_0_6 => rxdata_ch0(6), - FF_RX_D_0_7 => rxdata_ch0(7), - FF_RX_D_0_8 => rx_k_ch0, - FF_RX_D_0_9 => rx_disp_err_ch0, - FF_RX_D_0_10 => rx_cv_err_ch0, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => rx_serdes_rst_ch0_c, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, - FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c, - FFC_TXPWDNB_0 => tx_pwrup_ch0_c, - FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, - FFC_RXPWDNB_0 => rx_pwrup_ch0_c, - FFS_RLOS_LO_0 => rx_los_low_ch0_sig, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => rx_cdr_lol_ch0_sig, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => fpsc_vlo, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => fpsc_vlo, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => open, - HDOUTN3 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_TX_F_CLK_3 => open, - FF_TX_H_CLK_3 => open, - FFC_CK_CORE_RX_3 => fpsc_vlo, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA0 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIRDATA7 => open, - SCIRDATA6 => open, - SCIRDATA5 => open, - SCIRDATA4 => open, - SCIRDATA3 => open, - SCIRDATA2 => open, - SCIRDATA1 => open, - SCIRDATA0 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - - - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_gbe_0ch_arch ; diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch_generate.log b/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch_generate.log deleted file mode 100644 index a3bb684..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch_generate.log +++ /dev/null @@ -1,29 +0,0 @@ -Starting process: Module - -Starting process: - - Module Name: serdes_gbe_0ch - Core Name: PCS - LPC file : serdes_gbe_0ch.lpc - Parameter File : serdes_gbe_0ch.pp - Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0ch.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/simple_test/ipcores/serdes_gbe_0ch/. successfully! - -/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0ch -ext readme -out serdes_gbe_0ch -tpl serdes_gbe_0ch.tft serdes_gbe_0ch.vhd - -Done successfully! -File: serdes_gbe_0ch.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/dummy_sym.sort b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/dummy_sym.sort deleted file mode 100644 index a1712c9..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/dummy_sym.sort +++ /dev/null @@ -1 +0,0 @@ -dummy_sym.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/msg_file.log b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/msg_file.log deleted file mode 100644 index d4f3cbe..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/msg_file.log +++ /dev/null @@ -1,14 +0,0 @@ - Module Name: serdes_gbe_0_intclock_8b_ecp3 - Core Name: PCS - LPC file : serdes_gbe_0_intclock_8b_ecp3.lpc - Parameter File : serdes_gbe_0_intclock_8b_ecp3.pp - Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b_ecp3.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/. successfully! - -/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b_ecp3 -ext readme -out serdes_gbe_0_intclock_8b_ecp3 -tpl serdes_gbe_0_intclock_8b_ecp3.tft serdes_gbe_0_intclock_8b_ecp3.vhd - -Done successfully! diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/rx_reset_sm.naf b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/rx_reset_sm.naf deleted file mode 100644 index 1ff93d7..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/rx_reset_sm.naf +++ /dev/null @@ -1,7 +0,0 @@ -rst_n i -refclkdiv2 i -tx_pll_lol_qd_s i -rx_serdes_rst_ch_c o -rx_cdr_lol_ch_s i -rx_los_low_ch_s i -rx_pcs_rst_ch_c o diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.ipx b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.ipx deleted file mode 100644 index cec288c..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.jhd b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.jhd deleted file mode 100644 index c00e48b..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.jhd +++ /dev/null @@ -1,7 +0,0 @@ -MODULE serdes_gbe_0_intclock_8b DEFIN serdes_gbe_0_intclock_8b.vhd - SUBMODULE PCSD - INSTANCE PCSD_INST - SUBMODULE VHI - INSTANCE vhi_inst - SUBMODULE VLO - INSTANCE vlo_inst diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.lpc b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.lpc deleted file mode 100644 index b301420..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_gbe_0_intclock_8b -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/25/2011 -Time=14:19:31 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=RXTX -_mode1=DISABLED -_mode2=DISABLED -_mode3=DISABLED -_protocol0=GIGE -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=1.25 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=125.0 -_tx_protocol0=GIGE -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=DISABLED -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=125.0 -_tx_ficlk_rate1=125.0 -_tx_ficlk_rate2=125.0 -_tx_ficlk_rate3=125.0 -_pll_rxsrc0=INTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=EXTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=1.25 -_rx_datarange1=1.25 -_rx_datarange2=1.25 -_rx_datarange3=1.25 -_rx_protocol0=GIGE -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=DISABLED -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=125.0 -_rxrefclk_rate1=125.0 -_rxrefclk_rate2=125.0 -_rxrefclk_rate3=125.0 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=ENABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=ENABLED -_rx_ficlk_rate0=125.0 -_rx_ficlk_rate1=125.0 -_rx_ficlk_rate2=125.0 -_rx_ficlk_rate3=125.0 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=AC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=AC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P5 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111111 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=2 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=01 -_k01=00 -_k02=00 -_k03=00 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=00 -_k31=01 -_k32=01 -_k33=01 -_byten00=10111100 -_byten01=00000000 -_byten02=00000000 -_byten03=00000000 -_byten10=01010000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=10111100 -_byten21=00011100 -_byten22=00011100 -_byten23=00011100 -_byten30=01010000 -_byten31=00011100 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=DISABLED -_sci_int_port=DISABLED -_refck2core=DISABLED -Regen=auto -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_gbe_0_intclock_8b.pp=pp -serdes_gbe_0_intclock_8b.tft=tft -serdes_gbe_0_intclock_8b.txt=pcs_module -serdes_gbe_0_intclock_8b.sym=sym diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.naf b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.naf deleted file mode 100644 index f56b8f4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.naf +++ /dev/null @@ -1,48 +0,0 @@ -hdinp_ch0 i -hdinn_ch0 i -hdoutp_ch0 o -hdoutn_ch0 o -rxiclk_ch0 i -txiclk_ch0 i -rx_full_clk_ch0 o -rx_half_clk_ch0 o -tx_full_clk_ch0 o -tx_half_clk_ch0 o -fpga_rxrefclk_ch0 i -txdata_ch0[7] i -txdata_ch0[6] i -txdata_ch0[5] i -txdata_ch0[4] i -txdata_ch0[3] i -txdata_ch0[2] i -txdata_ch0[1] i -txdata_ch0[0] i -tx_k_ch0 i -xmit_ch0 i -tx_disp_correct_ch0 i -rxdata_ch0[7] o -rxdata_ch0[6] o -rxdata_ch0[5] o -rxdata_ch0[4] o -rxdata_ch0[3] o -rxdata_ch0[2] o -rxdata_ch0[1] o -rxdata_ch0[0] o -rx_k_ch0 o -rx_disp_err_ch0 o -rx_cv_err_ch0 o -rx_serdes_rst_ch0_c i -sb_felb_ch0_c i -sb_felb_rst_ch0_c i -tx_pcs_rst_ch0_c i -tx_pwrup_ch0_c i -rx_pcs_rst_ch0_c i -rx_pwrup_ch0_c i -rx_los_low_ch0_s o -lsm_status_ch0_s o -rx_cdr_lol_ch0_s o -fpga_txrefclk i -tx_serdes_rst_c i -tx_pll_lol_qd_s o -rst_qd_c i -serdes_rst_qd_c i diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.pp b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.pp deleted file mode 100644 index 34d4da3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.pp +++ /dev/null @@ -1,195 +0,0 @@ -#define _device_name "LFE3-150EA" -#define _ch0_pll_rxsrc "REFCLK_CORE" -#define _ch0_mode "RXTX" -#define _ch0_protocol "GIGE" -#define _ch0_ldr "DISABLED" -#define _ch0_tx_data_rate "FULL" -#define _ch0_tx_data_width "8" -#define _ch0_tx_fifo "ENABLED" -#define _ch0_tx_ficlk_rate 125.0 -#define _ch0_rx_datarange "MED" -#define _ch0_rx_data_rate "FULL" -#define _ch0_rxrefclk_rate "125.0" -#define _ch0_rx_data_width "8" -#define _ch0_rx_fifo "ENABLED" -#define _ch0_rx_ficlk_rate 125.0 -#define _ch0_tdrv "0" -#define _ch0_tx_pre "DISABLED" -#define _ch0_rterm_tx "50" -#define _ch0_rx_eq "DISABLED" -#define _ch0_rterm_rx "50" -#define _ch0_rx_dcc "AC" -#define _los_threshold_mode0 "LOS_E" -#define _los_threshold_lo0 "2" -#define _ch0_tx_sb "DISABLED" -#define _ch0_tx_8b10b "ENABLED" -#define _ch0_rx_sb "DISABLED" -#define _ch0_ird "DISABLED" -#define _ch0_rx_8b10b "ENABLED" -#define _ch0_rxwa "ENABLED" -#define _ch0_ilsm "ENABLED" -#define _ch0_scomma "K28P5" -#define _ch0_comma_a "1100000101" -#define _ch0_comma_b "0011111010" -#define _ch0_comma_m "1111111111" -#define _ch0_ctc "DISABLED" -#define _ch0_cc_match_mode "2" -#define _ch0_byten "0110111100" -#define _ch0_byten1 "0001010000" -#define _ch0_byten2 "0110111100" -#define _ch0_byten3 "0001010000" -#define _ch0_cc_min_ipg "3" -#define _ch0_lbtype "DISABLED" -#define _ch0_teidle "DISABLED" -#define _ch0_rx_lol_port "INTERNAL" - -#define _ch1_pll_rxsrc "REFCLK_EXT" -#define _ch1_mode "DISABLED" -#define _ch1_protocol "G8B10B" -#define _ch1_ldr "DISABLED" -#define _ch1_tx_data_rate "FULL" -#define _ch1_tx_data_width "8" -#define _ch1_tx_fifo "ENABLED" -#define _ch1_tx_ficlk_rate 125.0 -#define _ch1_rx_datarange "MED" -#define _ch1_rx_data_rate "FULL" -#define _ch1_rxrefclk_rate "125.0" -#define _ch1_rx_data_width "8" -#define _ch1_rx_fifo "ENABLED" -#define _ch1_rx_ficlk_rate 125.0 -#define _ch1_tdrv "0" -#define _ch1_tx_pre "DISABLED" -#define _ch1_rterm_tx "50" -#define _ch1_rx_eq "DISABLED" -#define _ch1_rterm_rx "50" -#define _ch1_rx_dcc "AC" -#define _los_threshold_mode1 "LOS_E" -#define _los_threshold_lo1 "2" -#define _ch1_tx_sb "DISABLED" -#define _ch1_tx_8b10b "ENABLED" -#define _ch1_rx_sb "DISABLED" -#define _ch1_ird "DISABLED" -#define _ch1_rx_8b10b "ENABLED" -#define _ch1_rxwa "ENABLED" -#define _ch1_ilsm "ENABLED" -#define _ch1_scomma "K28P157" -#define _ch1_comma_a "1100000101" -#define _ch1_comma_b "0011111010" -#define _ch1_comma_m "1111111100" -#define _ch1_ctc "DISABLED" -#define _ch1_cc_match_mode "1" -#define _ch1_byten "0000000000" -#define _ch1_byten1 "0000000000" -#define _ch1_byten2 "0100011100" -#define _ch1_byten3 "0100011100" -#define _ch1_cc_min_ipg "3" -#define _ch1_lbtype "DISABLED" -#define _ch1_teidle "DISABLED" -#define _ch1_rx_lol_port "INTERNAL" - -#define _ch2_pll_rxsrc "REFCLK_EXT" -#define _ch2_mode "DISABLED" -#define _ch2_protocol "G8B10B" -#define _ch2_ldr "DISABLED" -#define _ch2_tx_data_rate "FULL" -#define _ch2_tx_data_width "8" -#define _ch2_tx_fifo "ENABLED" -#define _ch2_tx_ficlk_rate 125.0 -#define _ch2_rx_datarange "MED" -#define _ch2_rx_data_rate "FULL" -#define _ch2_rxrefclk_rate "125.0" -#define _ch2_rx_data_width "8" -#define _ch2_rx_fifo "ENABLED" -#define _ch2_rx_ficlk_rate 125.0 -#define _ch2_tdrv "0" -#define _ch2_tx_pre "DISABLED" -#define _ch2_rterm_tx "50" -#define _ch2_rx_eq "DISABLED" -#define _ch2_rterm_rx "50" -#define _ch2_rx_dcc "AC" -#define _los_threshold_mode2 "LOS_E" -#define _los_threshold_lo2 "2" -#define _ch2_tx_sb "DISABLED" -#define _ch2_tx_8b10b "ENABLED" -#define _ch2_rx_sb "DISABLED" -#define _ch2_ird "DISABLED" -#define _ch2_rx_8b10b "ENABLED" -#define _ch2_rxwa "ENABLED" -#define _ch2_ilsm "ENABLED" -#define _ch2_scomma "K28P157" -#define _ch2_comma_a "1100000101" -#define _ch2_comma_b "0011111010" -#define _ch2_comma_m "1111111100" -#define _ch2_ctc "DISABLED" -#define _ch2_cc_match_mode "1" -#define _ch2_byten "0000000000" -#define _ch2_byten1 "0000000000" -#define _ch2_byten2 "0100011100" -#define _ch2_byten3 "0100011100" -#define _ch2_cc_min_ipg "3" -#define _ch2_lbtype "DISABLED" -#define _ch2_teidle "DISABLED" -#define _ch2_rx_lol_port "INTERNAL" - -#define _ch3_pll_rxsrc "REFCLK_EXT" -#define _ch3_mode "DISABLED" -#define _ch3_protocol "G8B10B" -#define _ch3_ldr "DISABLED" -#define _ch3_tx_data_rate "FULL" -#define _ch3_tx_data_width "8" -#define _ch3_tx_fifo "ENABLED" -#define _ch3_tx_ficlk_rate 125.0 -#define _ch3_rx_datarange "MED" -#define _ch3_rx_data_rate "FULL" -#define _ch3_rxrefclk_rate "125.0" -#define _ch3_rx_data_width "8" -#define _ch3_rx_fifo "ENABLED" -#define _ch3_rx_ficlk_rate 125.0 -#define _ch3_tdrv "0" -#define _ch3_tx_pre "DISABLED" -#define _ch3_rterm_tx "50" -#define _ch3_rx_eq "DISABLED" -#define _ch3_rterm_rx "50" -#define _ch3_rx_dcc "AC" -#define _los_threshold_mode3 "LOS_E" -#define _los_threshold_lo3 "2" -#define _ch3_tx_sb "DISABLED" -#define _ch3_tx_8b10b "ENABLED" -#define _ch3_rx_sb "DISABLED" -#define _ch3_ird "DISABLED" -#define _ch3_rx_8b10b "ENABLED" -#define _ch3_rxwa "ENABLED" -#define _ch3_ilsm "ENABLED" -#define _ch3_scomma "K28P157" -#define _ch3_comma_a "1100000101" -#define _ch3_comma_b "0011111010" -#define _ch3_comma_m "1111111100" -#define _ch3_ctc "DISABLED" -#define _ch3_cc_match_mode "1" -#define _ch3_byten "0000000000" -#define _ch3_byten1 "0000000000" -#define _ch3_byten2 "0100011100" -#define _ch3_byten3 "0100011100" -#define _ch3_cc_min_ipg "3" -#define _ch3_lbtype "DISABLED" -#define _ch3_teidle "DISABLED" -#define _ch3_rx_lol_port "INTERNAL" - -#define _datarange "MED" -#define _pll_txsrc "REFCLK_CORE" -#define _refclk_mult "10X" -#define _refclk_rate 125.0 -#define _pll_term "50" -#define _pll_dcc "AC" -#define _pll_lol_set "0" -#define _cchmark "9" -#define _cclmark "7" -#define _rst_gen "DISABLED" -#define _sci_ports "DISABLED" -#define _sci_int_port "DISABLED" -#define _refck2core "DISABLED" -#define _circuit_name serdes_gbe_0_intclock_8b -#define _lang vhdl - -#include -#include diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.readme b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.readme deleted file mode 100644 index bc17e35..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.readme +++ /dev/null @@ -1,141 +0,0 @@ - - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: Lattice Semiconductor Corporation - MODULE: serdes_gbe_0_intclock_8b - DESIGN: serdes_gbe_0_intclock_8b - FILENAME: serdes_gbe_0_intclock_8b.readme - PROJECT: Unknown - VERSION: 2.0 - This file is auto generated by the ispLEVER - - -NOTE: This readme file has been provided to instantiate the interface -netlist. Since this template contains synthesis attributes for precision that -are crucial to the design flow, we recommend that you use this -template in your FPGA design. -entity chip is -port ( - --- Add your FPGA design top level I/Os here - - --- ASIC side pins for PCSD. These pins must exist for the --- PCS core. - refclkp : in std_logic; - refclkn : in std_logic; - hdinp_ch0 : in std_logic; - hdinn_ch0 : in std_logic; - hdinp_ch1 : in std_logic; - hdinn_ch1 : in std_logic; - hdinp_ch2 : in std_logic; - hdinn_ch2 : in std_logic; - hdinp_ch3 : in std_logic; - hdinn_ch3 : in std_logic; - - hdoutp_ch0 : out std_logic; - hdoutn_ch0 : out std_logic; - hdoutp_ch1 : out std_logic; - hdoutn_ch1 : out std_logic; - hdoutp_ch2 : out std_logic; - hdoutn_ch2 : out std_logic; - hdoutp_ch3 : out std_logic; - hdoutn_ch3 : out std_logic; - - -); -end chip; - -architecture chip_arch of chip is - --- This defines all the high-speed ports. You may have to remove --- some of them depending on your design. -attribute nopad : string; -attribute nopad of - refclkp, refclkn, - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1, - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3, - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1, - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true"; - - COMPONENT serdes_gbe_0_intclock_8b - PORT( - hdinp_ch0 : IN std_logic; - hdinn_ch0 : IN std_logic; - rxiclk_ch0 : IN std_logic; - txiclk_ch0 : IN std_logic; - fpga_rxrefclk_ch0 : IN std_logic; - txdata_ch0 : IN std_logic_vector(7 downto 0); - tx_k_ch0 : IN std_logic; - xmit_ch0 : IN std_logic; - tx_disp_correct_ch0 : IN std_logic; - rx_serdes_rst_ch0_c : IN std_logic; - sb_felb_ch0_c : IN std_logic; - sb_felb_rst_ch0_c : IN std_logic; - tx_pcs_rst_ch0_c : IN std_logic; - tx_pwrup_ch0_c : IN std_logic; - rx_pcs_rst_ch0_c : IN std_logic; - rx_pwrup_ch0_c : IN std_logic; - fpga_txrefclk : IN std_logic; - tx_serdes_rst_c : IN std_logic; - rst_qd_c : IN std_logic; - serdes_rst_qd_c : IN std_logic; - hdoutp_ch0 : OUT std_logic; - hdoutn_ch0 : OUT std_logic; - rx_full_clk_ch0 : OUT std_logic; - rx_half_clk_ch0 : OUT std_logic; - tx_full_clk_ch0 : OUT std_logic; - tx_half_clk_ch0 : OUT std_logic; - rxdata_ch0 : OUT std_logic_vector(7 downto 0); - rx_k_ch0 : OUT std_logic; - rx_disp_err_ch0 : OUT std_logic; - rx_cv_err_ch0 : OUT std_logic; - rx_los_low_ch0_s : OUT std_logic; - lsm_status_ch0_s : OUT std_logic; - rx_cdr_lol_ch0_s : OUT std_logic; - tx_pll_lol_qd_s : OUT std_logic - ); - END COMPONENT; - - - - uut: serdes_gbe_0_intclock_8b PORT MAP( - hdinp_ch0 => hdinp_ch0, - hdinn_ch0 => hdinn_ch0, - hdoutp_ch0 => hdoutp_ch0, - hdoutn_ch0 => hdoutn_ch0, - rxiclk_ch0 => rxiclk_ch0, - txiclk_ch0 => txiclk_ch0, - rx_full_clk_ch0 => rx_full_clk_ch0, - rx_half_clk_ch0 => rx_half_clk_ch0, - tx_full_clk_ch0 => tx_full_clk_ch0, - tx_half_clk_ch0 => tx_half_clk_ch0, - fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0, - txdata_ch0 => txdata_ch0, - tx_k_ch0 => tx_k_ch0, - xmit_ch0 => xmit_ch0, - tx_disp_correct_ch0 => tx_disp_correct_ch0, - rxdata_ch0 => rxdata_ch0, - rx_k_ch0 => rx_k_ch0, - rx_disp_err_ch0 => rx_disp_err_ch0, - rx_cv_err_ch0 => rx_cv_err_ch0, - rx_serdes_rst_ch0_c => rx_serdes_rst_ch0_c, - sb_felb_ch0_c => sb_felb_ch0_c, - sb_felb_rst_ch0_c => sb_felb_rst_ch0_c, - tx_pcs_rst_ch0_c => tx_pcs_rst_ch0_c, - tx_pwrup_ch0_c => tx_pwrup_ch0_c, - rx_pcs_rst_ch0_c => rx_pcs_rst_ch0_c, - rx_pwrup_ch0_c => rx_pwrup_ch0_c, - rx_los_low_ch0_s => rx_los_low_ch0_s, - lsm_status_ch0_s => lsm_status_ch0_s, - rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s, - fpga_txrefclk => fpga_txrefclk, - tx_serdes_rst_c => tx_serdes_rst_c, - tx_pll_lol_qd_s => tx_pll_lol_qd_s, - rst_qd_c => rst_qd_c, - serdes_rst_qd_c => serdes_rst_qd_c - ); - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.sort b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.sort deleted file mode 100644 index 62b2781..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.sort +++ /dev/null @@ -1 +0,0 @@ -serdes_gbe_0_intclock_8b.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.sym b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.sym deleted file mode 100644 index a3b53efd7843a2a7af5d6d1e51ad9315886e26ef..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1594 zcmZvbPiPc(6vyBD%_zx2HWL&Pk+Mh-DN=?awgeFo-GdZ52mgTDPIhN^vrES8I5W}3 zg9HyEB4zO4A%`L%2N99Mg9q^>rIa3Ike);&c<3RNvUtd$Nb&o7zumY^T^RN=@B5wi z`@Q#mzenc?KMT*yc3UG})>MUV+V}9EaZenH$(k4@Z( zdwvuozLv28t-sUx)Jvn6wSF~Tl$2VvnJD7FjJgAA(u^C;(F9*;2bEcBEXBRfusE85 zlJNnfOeA%`)eP%{WzR#)`GnD?hT5lX^|Y=UMxPv6REk=L>hTSu?nrxnqmy9E-8gOr zQW!mf!{Jrq7=yz!oL(Vb@N*M)5Z}^`KJ-4nF?w0+qunSg)T;h5>Lk>WjRkZN>Kg4< z(g~=IT3XZPUifCl{eh}bGdgV4QaaM7AECJH8D*?@sbfl@B}Gy!SIM%k!Tu0!^xnfOM4_Pz`k4$H)tFALq6|VEf z)mjX(+~8&m_jL=dK80{C8CSa&w*KdO09VF$;ks|p7*-ridzhurS@;R`-z=#v>?Wx0 z>elKu;G5;w@ck{T{da=HY!I9x98hik^TKD%=?&GOWDaLpQ5 zgeK^|b0`kjR|2)n_&|81SRo!VFp_@%H1_V~513wHTWVF&E+`)%W-Z*~RGzY@>E jIhD5S{b%5eb_qw|i1rD4V2{2McEK*ZCHy0kT2mhZGOA#2 diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.tft b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.tft deleted file mode 100644 index b9db080..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.tft +++ /dev/null @@ -1,100 +0,0 @@ -@set suppresnewline=on@ - -@comment --------------------------------------------------------------------- @ -@comment Template-drive TFI generator @ -@comment Template for TFI generation. @ -@comment --------------------------------------------------------------------- @ - -@set suppresnewline=off@ - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: %title% - MODULE: %module% - DESIGN: %module% - FILENAME: %filename% - PROJECT: %project% - VERSION: %ver% - This file is auto generated by the ispLEVER -@set suppresnewline=on@ - -@cr@ -@cr@ - -@set sigdelim=@ - -NOTE: This readme file has been provided to instantiate the interface@cr@ -netlist. Since this template contains synthesis attributes for precision that@cr@ -are crucial to the design flow, we recommend that you use this@cr@ -template in your FPGA design.@cr@ -entity chip is@cr@ -port (@cr@ -@cr@ --- Add your FPGA design top level I/Os here@cr@ -@cr@ -@cr@ --- ASIC side pins for PCSD. These pins must exist for the@cr@ --- PCS core.@cr@ - refclkp : in std_logic;@cr@ - refclkn : in std_logic;@cr@ - hdinp_ch0 : in std_logic;@cr@ - hdinn_ch0 : in std_logic;@cr@ - hdinp_ch1 : in std_logic;@cr@ - hdinn_ch1 : in std_logic;@cr@ - hdinp_ch2 : in std_logic;@cr@ - hdinn_ch2 : in std_logic;@cr@ - hdinp_ch3 : in std_logic;@cr@ - hdinn_ch3 : in std_logic;@cr@ -@cr@ - hdoutp_ch0 : out std_logic;@cr@ - hdoutn_ch0 : out std_logic;@cr@ - hdoutp_ch1 : out std_logic;@cr@ - hdoutn_ch1 : out std_logic;@cr@ - hdoutp_ch2 : out std_logic;@cr@ - hdoutn_ch2 : out std_logic;@cr@ - hdoutp_ch3 : out std_logic;@cr@ - hdoutn_ch3 : out std_logic;@cr@ -@cr@ -@cr@ -);@cr@ -end chip;@cr@ -@cr@ -architecture chip_arch of chip is@cr@ -@cr@ --- This defines all the high-speed ports. You may have to remove@cr@ --- some of them depending on your design.@cr@ -attribute nopad : string;@cr@ -attribute nopad of@cr@ - refclkp, refclkn,@cr@ - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@ - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@ - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@ - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@ - -@cr@ -@tab@COMPONENT %module% -@set sigdelim=@ -@cr@@tab@PORT( -@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ -@ifhas oport=*@ @comment if the design has any output ports... @ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ - @set sigdelim=;@ - @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ -@endif@ -@ifnhas oport=*@ @comment we need an "else in this language! @ - @set sigdelim=;@ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ -@endif@ -@cr@@tab@@tab@);@cr@ -@tab@END COMPONENT;@cr@@cr@ -@comment Now do a signal declaration for each port @ - -@cr@@cr@ -@comment do the component instantiation @ -@set sigdelim=,@ -@tab@uut: %module% PORT MAP( -@iterate@%port% -@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ -@cr@@tab@);@cr@@cr@ -@set suppresnewline=off@ - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.txt b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.txt deleted file mode 100644 index 17ddaaf..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.txt +++ /dev/null @@ -1,59 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "GIGE" -CH0_MODE "RXTX" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "DISABLED" -CH0_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MED" -CH0_RX_DATARATE_RANGE "MED" -REFCK_MULT "10X" -#REFCLK_RATE 125.0 -CH0_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH0_TX_FIFO "ENABLED" -CH0_RX_FIFO "ENABLED" -CH0_TDRV "0" -#CH0_TX_FICLK_RATE 125.0 -#CH0_RXREFCLK_RATE "125.0" -#CH0_RX_FICLK_RATE 125.0 -CH0_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -CH0_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH0_COMMA_M "1111111111" -CH0_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH0_CC_MATCH3 "0110111100" -CH0_CC_MATCH4 "0001010000" -CH0_CC_MATCH_MODE "2" -CH0_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "DISABLED" - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.vhd b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.vhd deleted file mode 100644 index e8038d8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b.vhd +++ /dev/null @@ -1,2689 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_CORE"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_EXT"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - - - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_intclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - xmit_ch0 : in std_logic; - tx_disp_correct_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_gbe_0_intclock_8b; - - -architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - - - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH0_CDR_SRC: string; - attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch0_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - - - - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - rx_los_low_ch0_s <= rx_los_low_ch0_sig; - rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch0 <= tx_full_clk_ch0_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH0_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => hdoutp_ch0, - HDOUTN0 => hdoutn_ch0, - HDINP0 => hdinp_ch0, - HDINN0 => hdinn_ch0, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => rxiclk_ch0, - FF_TXI_CLK_0 => txiclk_ch0, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => rx_full_clk_ch0, - FF_RX_H_CLK_0 => rx_half_clk_ch0, - FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, - FF_TX_H_CLK_0 => tx_half_clk_ch0, - FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, - FF_TX_D_0_0 => txdata_ch0(0), - FF_TX_D_0_1 => txdata_ch0(1), - FF_TX_D_0_2 => txdata_ch0(2), - FF_TX_D_0_3 => txdata_ch0(3), - FF_TX_D_0_4 => txdata_ch0(4), - FF_TX_D_0_5 => txdata_ch0(5), - FF_TX_D_0_6 => txdata_ch0(6), - FF_TX_D_0_7 => txdata_ch0(7), - FF_TX_D_0_8 => tx_k_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => xmit_ch0, - FF_TX_D_0_11 => tx_disp_correct_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => rxdata_ch0(0), - FF_RX_D_0_1 => rxdata_ch0(1), - FF_RX_D_0_2 => rxdata_ch0(2), - FF_RX_D_0_3 => rxdata_ch0(3), - FF_RX_D_0_4 => rxdata_ch0(4), - FF_RX_D_0_5 => rxdata_ch0(5), - FF_RX_D_0_6 => rxdata_ch0(6), - FF_RX_D_0_7 => rxdata_ch0(7), - FF_RX_D_0_8 => rx_k_ch0, - FF_RX_D_0_9 => rx_disp_err_ch0, - FF_RX_D_0_10 => rx_cv_err_ch0, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => rx_serdes_rst_ch0_c, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, - FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c, - FFC_TXPWDNB_0 => tx_pwrup_ch0_c, - FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, - FFC_RXPWDNB_0 => rx_pwrup_ch0_c, - FFS_RLOS_LO_0 => rx_los_low_ch0_sig, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => rx_cdr_lol_ch0_sig, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => fpsc_vlo, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => fpsc_vlo, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => open, - HDOUTN3 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_TX_F_CLK_3 => open, - FF_TX_H_CLK_3 => open, - FFC_CK_CORE_RX_3 => fpsc_vlo, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA0 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIRDATA7 => open, - SCIRDATA6 => open, - SCIRDATA5 => open, - SCIRDATA4 => open, - SCIRDATA3 => open, - SCIRDATA2 => open, - SCIRDATA1 => open, - SCIRDATA0 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - - - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_gbe_0_intclock_8b_arch ; diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.ipx b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.ipx deleted file mode 100644 index 07fc708..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.jhd b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.jhd deleted file mode 100644 index 5a78672..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.jhd +++ /dev/null @@ -1,13 +0,0 @@ -MODULE rx_reset_sm DEFIN serdes_gbe_0_intclock_8b_ecp3.vhd -MODULE tx_reset_sm DEFIN serdes_gbe_0_intclock_8b_ecp3.vhd -MODULE serdes_gbe_0_intclock_8b_ecp3 DEFIN serdes_gbe_0_intclock_8b_ecp3.vhd - SUBMODULE tx_reset_sm - INSTANCE tx_reset_sm_ch - SUBMODULE rx_reset_sm - INSTANCE rx_reset_sm_ch0 - SUBMODULE PCSD - INSTANCE PCSD_INST - SUBMODULE VHI - INSTANCE vhi_inst - SUBMODULE VLO - INSTANCE vlo_inst diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.lpc b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.lpc deleted file mode 100644 index 5da776a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_gbe_0_intclock_8b_ecp3 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=10/05/2011 -Time=15:38:09 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=RXTX -_mode1=DISABLED -_mode2=DISABLED -_mode3=DISABLED -_protocol0=GIGE -_protocol1=GIGE -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=1.25 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=125.0 -_tx_protocol0=GIGE -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=DISABLED -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=125.0 -_tx_ficlk_rate1=125.0 -_tx_ficlk_rate2=125.0 -_tx_ficlk_rate3=125.0 -_pll_rxsrc0=INTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=EXTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=1.25 -_rx_datarange1=1.25 -_rx_datarange2=1.25 -_rx_datarange3=1.25 -_rx_protocol0=GIGE -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=DISABLED -_rx_data_rate0=FULL -_rx_data_rate1=DIV2 -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=125.0 -_rxrefclk_rate1=125.0 -_rxrefclk_rate2=125.0 -_rxrefclk_rate3=125.0 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=ENABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=ENABLED -_rx_ficlk_rate0=125.0 -_rx_ficlk_rate1=62.5 -_rx_ficlk_rate2=125.0 -_rx_ficlk_rate3=125.0 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=AC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=AC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P5 -_scomma1=K28P5 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111111 -_comma_m1=1111111111 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=2 -_cc_match_mode1=2 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=01 -_k01=00 -_k02=01 -_k03=00 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=00 -_k31=00 -_k32=01 -_k33=01 -_byten00=10111100 -_byten01=00000000 -_byten02=00011100 -_byten03=00000000 -_byten10=01010000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=10111100 -_byten21=10111100 -_byten22=00011100 -_byten23=00011100 -_byten30=01010000 -_byten31=01010000 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=ENABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=DISABLED -_sci_int_port=DISABLED -_refck2core=ENABLED -Regen=auto -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_gbe_0_intclock_8b_ecp3.pp=pp -serdes_gbe_0_intclock_8b_ecp3.tft=tft -serdes_gbe_0_intclock_8b_ecp3.txt=pcs_module -serdes_gbe_0_intclock_8b_ecp3.sym=sym diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.naf b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.naf deleted file mode 100644 index 10e2252..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.naf +++ /dev/null @@ -1,46 +0,0 @@ -hdinp_ch0 i -hdinn_ch0 i -hdoutp_ch0 o -hdoutn_ch0 o -rxiclk_ch0 i -txiclk_ch0 i -rx_full_clk_ch0 o -rx_half_clk_ch0 o -tx_full_clk_ch0 o -tx_half_clk_ch0 o -fpga_rxrefclk_ch0 i -txdata_ch0[7] i -txdata_ch0[6] i -txdata_ch0[5] i -txdata_ch0[4] i -txdata_ch0[3] i -txdata_ch0[2] i -txdata_ch0[1] i -txdata_ch0[0] i -tx_k_ch0 i -xmit_ch0 i -tx_disp_correct_ch0 i -rxdata_ch0[7] o -rxdata_ch0[6] o -rxdata_ch0[5] o -rxdata_ch0[4] o -rxdata_ch0[3] o -rxdata_ch0[2] o -rxdata_ch0[1] o -rxdata_ch0[0] o -rx_k_ch0 o -rx_disp_err_ch0 o -rx_cv_err_ch0 o -sb_felb_ch0_c i -sb_felb_rst_ch0_c i -tx_pwrup_ch0_c i -rx_pwrup_ch0_c i -rx_los_low_ch0_s o -lsm_status_ch0_s o -rx_cdr_lol_ch0_s o -fpga_txrefclk i -tx_serdes_rst_c i -tx_pll_lol_qd_s o -refclk2fpga o -rst_n i -serdes_rst_qd_c i diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.pp b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.pp deleted file mode 100644 index 51384af..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.pp +++ /dev/null @@ -1,195 +0,0 @@ -#define _device_name "LFE3-150EA" -#define _ch0_pll_rxsrc "REFCLK_CORE" -#define _ch0_mode "RXTX" -#define _ch0_protocol "GIGE" -#define _ch0_ldr "DISABLED" -#define _ch0_tx_data_rate "FULL" -#define _ch0_tx_data_width "8" -#define _ch0_tx_fifo "ENABLED" -#define _ch0_tx_ficlk_rate 125.0 -#define _ch0_rx_datarange "MED" -#define _ch0_rx_data_rate "FULL" -#define _ch0_rxrefclk_rate "125.0" -#define _ch0_rx_data_width "8" -#define _ch0_rx_fifo "ENABLED" -#define _ch0_rx_ficlk_rate 125.0 -#define _ch0_tdrv "0" -#define _ch0_tx_pre "DISABLED" -#define _ch0_rterm_tx "50" -#define _ch0_rx_eq "DISABLED" -#define _ch0_rterm_rx "50" -#define _ch0_rx_dcc "AC" -#define _los_threshold_mode0 "LOS_E" -#define _los_threshold_lo0 "2" -#define _ch0_tx_sb "DISABLED" -#define _ch0_tx_8b10b "ENABLED" -#define _ch0_rx_sb "DISABLED" -#define _ch0_ird "DISABLED" -#define _ch0_rx_8b10b "ENABLED" -#define _ch0_rxwa "ENABLED" -#define _ch0_ilsm "ENABLED" -#define _ch0_scomma "K28P5" -#define _ch0_comma_a "1100000101" -#define _ch0_comma_b "0011111010" -#define _ch0_comma_m "1111111111" -#define _ch0_ctc "DISABLED" -#define _ch0_cc_match_mode "2" -#define _ch0_byten "0110111100" -#define _ch0_byten1 "0001010000" -#define _ch0_byten2 "0110111100" -#define _ch0_byten3 "0001010000" -#define _ch0_cc_min_ipg "3" -#define _ch0_lbtype "DISABLED" -#define _ch0_teidle "DISABLED" -#define _ch0_rx_lol_port "INTERNAL" - -#define _ch1_pll_rxsrc "REFCLK_EXT" -#define _ch1_mode "DISABLED" -#define _ch1_protocol "GIGE" -#define _ch1_ldr "DISABLED" -#define _ch1_tx_data_rate "FULL" -#define _ch1_tx_data_width "8" -#define _ch1_tx_fifo "ENABLED" -#define _ch1_tx_ficlk_rate 125.0 -#define _ch1_rx_datarange "MED" -#define _ch1_rx_data_rate "DIV2" -#define _ch1_rxrefclk_rate "125.0" -#define _ch1_rx_data_width "8" -#define _ch1_rx_fifo "ENABLED" -#define _ch1_rx_ficlk_rate 62.5 -#define _ch1_tdrv "0" -#define _ch1_tx_pre "DISABLED" -#define _ch1_rterm_tx "50" -#define _ch1_rx_eq "DISABLED" -#define _ch1_rterm_rx "50" -#define _ch1_rx_dcc "AC" -#define _los_threshold_mode1 "LOS_E" -#define _los_threshold_lo1 "2" -#define _ch1_tx_sb "DISABLED" -#define _ch1_tx_8b10b "ENABLED" -#define _ch1_rx_sb "DISABLED" -#define _ch1_ird "DISABLED" -#define _ch1_rx_8b10b "ENABLED" -#define _ch1_rxwa "ENABLED" -#define _ch1_ilsm "ENABLED" -#define _ch1_scomma "K28P5" -#define _ch1_comma_a "1100000101" -#define _ch1_comma_b "0011111010" -#define _ch1_comma_m "1111111111" -#define _ch1_ctc "DISABLED" -#define _ch1_cc_match_mode "2" -#define _ch1_byten "0000000000" -#define _ch1_byten1 "0000000000" -#define _ch1_byten2 "0110111100" -#define _ch1_byten3 "0001010000" -#define _ch1_cc_min_ipg "3" -#define _ch1_lbtype "DISABLED" -#define _ch1_teidle "DISABLED" -#define _ch1_rx_lol_port "INTERNAL" - -#define _ch2_pll_rxsrc "REFCLK_EXT" -#define _ch2_mode "DISABLED" -#define _ch2_protocol "G8B10B" -#define _ch2_ldr "DISABLED" -#define _ch2_tx_data_rate "FULL" -#define _ch2_tx_data_width "8" -#define _ch2_tx_fifo "ENABLED" -#define _ch2_tx_ficlk_rate 125.0 -#define _ch2_rx_datarange "MED" -#define _ch2_rx_data_rate "FULL" -#define _ch2_rxrefclk_rate "125.0" -#define _ch2_rx_data_width "8" -#define _ch2_rx_fifo "ENABLED" -#define _ch2_rx_ficlk_rate 125.0 -#define _ch2_tdrv "0" -#define _ch2_tx_pre "DISABLED" -#define _ch2_rterm_tx "50" -#define _ch2_rx_eq "DISABLED" -#define _ch2_rterm_rx "50" -#define _ch2_rx_dcc "AC" -#define _los_threshold_mode2 "LOS_E" -#define _los_threshold_lo2 "2" -#define _ch2_tx_sb "DISABLED" -#define _ch2_tx_8b10b "ENABLED" -#define _ch2_rx_sb "DISABLED" -#define _ch2_ird "DISABLED" -#define _ch2_rx_8b10b "ENABLED" -#define _ch2_rxwa "ENABLED" -#define _ch2_ilsm "ENABLED" -#define _ch2_scomma "K28P157" -#define _ch2_comma_a "1100000101" -#define _ch2_comma_b "0011111010" -#define _ch2_comma_m "1111111100" -#define _ch2_ctc "DISABLED" -#define _ch2_cc_match_mode "1" -#define _ch2_byten "0100011100" -#define _ch2_byten1 "0000000000" -#define _ch2_byten2 "0100011100" -#define _ch2_byten3 "0100011100" -#define _ch2_cc_min_ipg "3" -#define _ch2_lbtype "DISABLED" -#define _ch2_teidle "DISABLED" -#define _ch2_rx_lol_port "INTERNAL" - -#define _ch3_pll_rxsrc "REFCLK_EXT" -#define _ch3_mode "DISABLED" -#define _ch3_protocol "G8B10B" -#define _ch3_ldr "DISABLED" -#define _ch3_tx_data_rate "FULL" -#define _ch3_tx_data_width "8" -#define _ch3_tx_fifo "ENABLED" -#define _ch3_tx_ficlk_rate 125.0 -#define _ch3_rx_datarange "MED" -#define _ch3_rx_data_rate "FULL" -#define _ch3_rxrefclk_rate "125.0" -#define _ch3_rx_data_width "8" -#define _ch3_rx_fifo "ENABLED" -#define _ch3_rx_ficlk_rate 125.0 -#define _ch3_tdrv "0" -#define _ch3_tx_pre "DISABLED" -#define _ch3_rterm_tx "50" -#define _ch3_rx_eq "DISABLED" -#define _ch3_rterm_rx "50" -#define _ch3_rx_dcc "AC" -#define _los_threshold_mode3 "LOS_E" -#define _los_threshold_lo3 "2" -#define _ch3_tx_sb "DISABLED" -#define _ch3_tx_8b10b "ENABLED" -#define _ch3_rx_sb "DISABLED" -#define _ch3_ird "DISABLED" -#define _ch3_rx_8b10b "ENABLED" -#define _ch3_rxwa "ENABLED" -#define _ch3_ilsm "ENABLED" -#define _ch3_scomma "K28P157" -#define _ch3_comma_a "1100000101" -#define _ch3_comma_b "0011111010" -#define _ch3_comma_m "1111111100" -#define _ch3_ctc "DISABLED" -#define _ch3_cc_match_mode "1" -#define _ch3_byten "0000000000" -#define _ch3_byten1 "0000000000" -#define _ch3_byten2 "0100011100" -#define _ch3_byten3 "0100011100" -#define _ch3_cc_min_ipg "3" -#define _ch3_lbtype "DISABLED" -#define _ch3_teidle "DISABLED" -#define _ch3_rx_lol_port "INTERNAL" - -#define _datarange "MED" -#define _pll_txsrc "REFCLK_CORE" -#define _refclk_mult "10X" -#define _refclk_rate 125.0 -#define _pll_term "50" -#define _pll_dcc "AC" -#define _pll_lol_set "0" -#define _cchmark "9" -#define _cclmark "7" -#define _rst_gen "ENABLED" -#define _sci_ports "DISABLED" -#define _sci_int_port "DISABLED" -#define _refck2core "ENABLED" -#define _circuit_name serdes_gbe_0_intclock_8b_ecp3 -#define _lang vhdl - -#include -#include diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.readme b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.readme deleted file mode 100644 index a6c3168..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.readme +++ /dev/null @@ -1,137 +0,0 @@ - - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: Lattice Semiconductor Corporation - MODULE: serdes_gbe_0_intclock_8b_ecp3 - DESIGN: serdes_gbe_0_intclock_8b_ecp3 - FILENAME: serdes_gbe_0_intclock_8b_ecp3.readme - PROJECT: Unknown - VERSION: 2.0 - This file is auto generated by the ispLEVER - - -NOTE: This readme file has been provided to instantiate the interface -netlist. Since this template contains synthesis attributes for precision that -are crucial to the design flow, we recommend that you use this -template in your FPGA design. -entity chip is -port ( - --- Add your FPGA design top level I/Os here - - --- ASIC side pins for PCSD. These pins must exist for the --- PCS core. - refclkp : in std_logic; - refclkn : in std_logic; - hdinp_ch0 : in std_logic; - hdinn_ch0 : in std_logic; - hdinp_ch1 : in std_logic; - hdinn_ch1 : in std_logic; - hdinp_ch2 : in std_logic; - hdinn_ch2 : in std_logic; - hdinp_ch3 : in std_logic; - hdinn_ch3 : in std_logic; - - hdoutp_ch0 : out std_logic; - hdoutn_ch0 : out std_logic; - hdoutp_ch1 : out std_logic; - hdoutn_ch1 : out std_logic; - hdoutp_ch2 : out std_logic; - hdoutn_ch2 : out std_logic; - hdoutp_ch3 : out std_logic; - hdoutn_ch3 : out std_logic; - - -); -end chip; - -architecture chip_arch of chip is - --- This defines all the high-speed ports. You may have to remove --- some of them depending on your design. -attribute nopad : string; -attribute nopad of - refclkp, refclkn, - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1, - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3, - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1, - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true"; - - COMPONENT serdes_gbe_0_intclock_8b_ecp3 - PORT( - hdinp_ch0 : IN std_logic; - hdinn_ch0 : IN std_logic; - rxiclk_ch0 : IN std_logic; - txiclk_ch0 : IN std_logic; - fpga_rxrefclk_ch0 : IN std_logic; - txdata_ch0 : IN std_logic_vector(7 downto 0); - tx_k_ch0 : IN std_logic; - xmit_ch0 : IN std_logic; - tx_disp_correct_ch0 : IN std_logic; - sb_felb_ch0_c : IN std_logic; - sb_felb_rst_ch0_c : IN std_logic; - tx_pwrup_ch0_c : IN std_logic; - rx_pwrup_ch0_c : IN std_logic; - fpga_txrefclk : IN std_logic; - tx_serdes_rst_c : IN std_logic; - rst_n : IN std_logic; - serdes_rst_qd_c : IN std_logic; - hdoutp_ch0 : OUT std_logic; - hdoutn_ch0 : OUT std_logic; - rx_full_clk_ch0 : OUT std_logic; - rx_half_clk_ch0 : OUT std_logic; - tx_full_clk_ch0 : OUT std_logic; - tx_half_clk_ch0 : OUT std_logic; - rxdata_ch0 : OUT std_logic_vector(7 downto 0); - rx_k_ch0 : OUT std_logic; - rx_disp_err_ch0 : OUT std_logic; - rx_cv_err_ch0 : OUT std_logic; - rx_los_low_ch0_s : OUT std_logic; - lsm_status_ch0_s : OUT std_logic; - rx_cdr_lol_ch0_s : OUT std_logic; - tx_pll_lol_qd_s : OUT std_logic; - refclk2fpga : OUT std_logic - ); - END COMPONENT; - - - - uut: serdes_gbe_0_intclock_8b_ecp3 PORT MAP( - hdinp_ch0 => hdinp_ch0, - hdinn_ch0 => hdinn_ch0, - hdoutp_ch0 => hdoutp_ch0, - hdoutn_ch0 => hdoutn_ch0, - rxiclk_ch0 => rxiclk_ch0, - txiclk_ch0 => txiclk_ch0, - rx_full_clk_ch0 => rx_full_clk_ch0, - rx_half_clk_ch0 => rx_half_clk_ch0, - tx_full_clk_ch0 => tx_full_clk_ch0, - tx_half_clk_ch0 => tx_half_clk_ch0, - fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0, - txdata_ch0 => txdata_ch0, - tx_k_ch0 => tx_k_ch0, - xmit_ch0 => xmit_ch0, - tx_disp_correct_ch0 => tx_disp_correct_ch0, - rxdata_ch0 => rxdata_ch0, - rx_k_ch0 => rx_k_ch0, - rx_disp_err_ch0 => rx_disp_err_ch0, - rx_cv_err_ch0 => rx_cv_err_ch0, - sb_felb_ch0_c => sb_felb_ch0_c, - sb_felb_rst_ch0_c => sb_felb_rst_ch0_c, - tx_pwrup_ch0_c => tx_pwrup_ch0_c, - rx_pwrup_ch0_c => rx_pwrup_ch0_c, - rx_los_low_ch0_s => rx_los_low_ch0_s, - lsm_status_ch0_s => lsm_status_ch0_s, - rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s, - fpga_txrefclk => fpga_txrefclk, - tx_serdes_rst_c => tx_serdes_rst_c, - tx_pll_lol_qd_s => tx_pll_lol_qd_s, - refclk2fpga => refclk2fpga, - rst_n => rst_n, - serdes_rst_qd_c => serdes_rst_qd_c - ); - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.sort b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.sort deleted file mode 100644 index 072d9c8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.sort +++ /dev/null @@ -1 +0,0 @@ -serdes_gbe_0_intclock_8b_ecp3.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.sym b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.sym deleted file mode 100644 index 2a4c04ffb6b26f786b7810eb1eced7c1ec3d93be..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1506 zcmZvcKWG$b7>D2Yn++r@(eV@uQCW^H#6kuY6iIP~ZegLrp=V*vVRvTNtd6^%Gn2Sn zAwk4KLR5fZ;e!<6jVQD?vEt(JabCK4tT1 z$+J;T88V+bHk+D@y1kyfa~E}wZfvM)ssCx}>Y=SqBxx4(=oxAyFWK7GWDw}<$-L-6 zNc0A&rsp=TCWG#HTJ*^zylRu_v=wyPam$Q?*LE^d&TBT?KF-W|Ha~>iSNmAjye(}f zQ9BJxd@aJ;XHCj8Hr zXi}=)_(4&1F6z%`_HeLo?3_7wmS$l1REKe7Y}jL3HzF7%H(<;va^v)BkY>$nK9y}u zp^ZA-hUcjsyc>$P*voUsT$Od>35+4<6>SzX*uvAXMo^giCPAKMNP&f-ef^;G8cDYp~`8VIS=CO<@o0 z@jYP|?DFpuQ)Is9H9U``UVsZ)7S6#rJrmYoO)rFfuurdrJ+Ox!Rs2UMwWz)VYr;)Q diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.tft b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.tft deleted file mode 100644 index b9db080..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.tft +++ /dev/null @@ -1,100 +0,0 @@ -@set suppresnewline=on@ - -@comment --------------------------------------------------------------------- @ -@comment Template-drive TFI generator @ -@comment Template for TFI generation. @ -@comment --------------------------------------------------------------------- @ - -@set suppresnewline=off@ - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: %title% - MODULE: %module% - DESIGN: %module% - FILENAME: %filename% - PROJECT: %project% - VERSION: %ver% - This file is auto generated by the ispLEVER -@set suppresnewline=on@ - -@cr@ -@cr@ - -@set sigdelim=@ - -NOTE: This readme file has been provided to instantiate the interface@cr@ -netlist. Since this template contains synthesis attributes for precision that@cr@ -are crucial to the design flow, we recommend that you use this@cr@ -template in your FPGA design.@cr@ -entity chip is@cr@ -port (@cr@ -@cr@ --- Add your FPGA design top level I/Os here@cr@ -@cr@ -@cr@ --- ASIC side pins for PCSD. These pins must exist for the@cr@ --- PCS core.@cr@ - refclkp : in std_logic;@cr@ - refclkn : in std_logic;@cr@ - hdinp_ch0 : in std_logic;@cr@ - hdinn_ch0 : in std_logic;@cr@ - hdinp_ch1 : in std_logic;@cr@ - hdinn_ch1 : in std_logic;@cr@ - hdinp_ch2 : in std_logic;@cr@ - hdinn_ch2 : in std_logic;@cr@ - hdinp_ch3 : in std_logic;@cr@ - hdinn_ch3 : in std_logic;@cr@ -@cr@ - hdoutp_ch0 : out std_logic;@cr@ - hdoutn_ch0 : out std_logic;@cr@ - hdoutp_ch1 : out std_logic;@cr@ - hdoutn_ch1 : out std_logic;@cr@ - hdoutp_ch2 : out std_logic;@cr@ - hdoutn_ch2 : out std_logic;@cr@ - hdoutp_ch3 : out std_logic;@cr@ - hdoutn_ch3 : out std_logic;@cr@ -@cr@ -@cr@ -);@cr@ -end chip;@cr@ -@cr@ -architecture chip_arch of chip is@cr@ -@cr@ --- This defines all the high-speed ports. You may have to remove@cr@ --- some of them depending on your design.@cr@ -attribute nopad : string;@cr@ -attribute nopad of@cr@ - refclkp, refclkn,@cr@ - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@ - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@ - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@ - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@ - -@cr@ -@tab@COMPONENT %module% -@set sigdelim=@ -@cr@@tab@PORT( -@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ -@ifhas oport=*@ @comment if the design has any output ports... @ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ - @set sigdelim=;@ - @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ -@endif@ -@ifnhas oport=*@ @comment we need an "else in this language! @ - @set sigdelim=;@ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ -@endif@ -@cr@@tab@@tab@);@cr@ -@tab@END COMPONENT;@cr@@cr@ -@comment Now do a signal declaration for each port @ - -@cr@@cr@ -@comment do the component instantiation @ -@set sigdelim=,@ -@tab@uut: %module% PORT MAP( -@iterate@%port% -@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ -@cr@@tab@);@cr@@cr@ -@set suppresnewline=off@ - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.txt b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.txt deleted file mode 100644 index 257807f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.txt +++ /dev/null @@ -1,59 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "GIGE" -CH0_MODE "RXTX" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "DISABLED" -CH0_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MED" -CH0_RX_DATARATE_RANGE "MED" -REFCK_MULT "10X" -#REFCLK_RATE 125.0 -CH0_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH0_TX_FIFO "ENABLED" -CH0_RX_FIFO "ENABLED" -CH0_TDRV "0" -#CH0_TX_FICLK_RATE 125.0 -#CH0_RXREFCLK_RATE "125.0" -#CH0_RX_FICLK_RATE 125.0 -CH0_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -CH0_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH0_COMMA_M "1111111111" -CH0_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH0_CC_MATCH3 "0110111100" -CH0_CC_MATCH4 "0001010000" -CH0_CC_MATCH_MODE "2" -CH0_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "ENABLED" - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd deleted file mode 100644 index 9f273c8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd +++ /dev/null @@ -1,3117 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_CORE"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_EXT"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - ---THIS MODULE IS INSTANTIATED PER RX CHANNEL ---Reset Sequence Generator -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity rx_reset_sm is -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rx_serdes_rst_ch_c: out std_logic; - rx_cdr_lol_ch_s : in std_logic; - rx_los_low_ch_s : in std_logic; - rx_pcs_rst_ch_c : out std_logic -); -end rx_reset_sm ; - -architecture rx_reset_sm_arch of rx_reset_sm is - -type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL); - -signal cs: statetype; -- current state of lsm -signal ns: statetype; -- next state of lsm - -signal tx_pll_lol_qd_s_int: std_logic; -signal rx_los_low_int: std_logic; -signal plol_los_int: std_logic; -signal rx_lol_los : std_logic; -signal rx_lol_los_int: std_logic; -signal rx_lol_los_del: std_logic; -signal rx_pcs_rst_ch_c_int: std_logic; -signal rx_serdes_rst_ch_c_int: std_logic; - -signal reset_timer1: std_logic; -signal reset_timer2: std_logic; - -signal counter1: std_logic_vector(1 downto 0); -signal TIMER1: std_logic; - -signal counter2: std_logic_vector(18 downto 0); -signal TIMER2 : std_logic; - -begin - -rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ; - -process(refclkdiv2,rst_n) -begin - if rising_edge(refclkdiv2) then - if rst_n = '0' then - cs <= WAIT_FOR_PLOL; - rx_lol_los_int <= '1'; - rx_lol_los_del <= '1'; - tx_pll_lol_qd_s_int <= '1'; - rx_pcs_rst_ch_c <= '1'; - rx_serdes_rst_ch_c <= '0'; - rx_los_low_int <= '1'; - else - cs <= ns; - rx_lol_los_del <= rx_lol_los; - rx_lol_los_int <= rx_lol_los_del; - tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; - rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int; - rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int; - rx_los_low_int <= rx_los_low_ch_s; - end if; - end if; -end process; - ---TIMER1 = 3NS; ---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles ---A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1] - -process(refclkdiv2, reset_timer1) -begin - if rising_edge(refclkdiv2) then - if reset_timer1 = '1' then - counter1 <= "00"; - TIMER1 <= '0'; - else - if counter1(1) = '1' then - TIMER1 <='1'; - else - TIMER1 <='0'; - counter1 <= counter1 + 1 ; - end if; - end if; - end if; -end process; - ---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles ---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] - -process(refclkdiv2, reset_timer2) -begin - if rising_edge(refclkdiv2) then - if reset_timer2 = '1' then - counter2 <= "0000000000000000000"; - TIMER2 <= '0'; - else - if counter2(count_index) = '1' then - TIMER2 <='1'; - else - TIMER2 <='0'; - counter2 <= counter2 + 1 ; - end if; - end if; - end if; -end process; - - -process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2) -begin - reset_timer1 <= '0'; - reset_timer2 <= '0'; - - case cs is - when WAIT_FOR_PLOL => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal - ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next - else - ns <= RX_SERDES_RESET; - end if; - - when RX_SERDES_RESET => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '1'; - reset_timer1 <= '1'; - ns <= WAIT_FOR_TIMER1; - - - when WAIT_FOR_TIMER1 => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '1'; - if TIMER1 = '1' then - ns <= CHECK_LOL_LOS; - else - ns <= WAIT_FOR_TIMER1; - end if; - - when CHECK_LOL_LOS => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - reset_timer2 <= '1'; - ns <= WAIT_FOR_TIMER2; - - when WAIT_FOR_TIMER2 => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES - if TIMER2 = '1' then - if rx_lol_los_int = '1' then - ns <= WAIT_FOR_PLOL; - else - ns <= NORMAL; - end if; - else - ns <= WAIT_FOR_TIMER2; - end if; - else - ns <= CHECK_LOL_LOS; --RESET TIMER2 - end if; - - when NORMAL => - rx_pcs_rst_ch_c_int <= '0'; - rx_serdes_rst_ch_c_int <= '0'; - if rx_lol_los_int = '1' then - ns <= WAIT_FOR_PLOL; - else - ns <= NORMAL; - end if; - - when others => - ns <= WAIT_FOR_PLOL; - - end case; - -end process; - - -end rx_reset_sm_arch; - ---THIS MODULE IS INSTANTIATED PER TX QUAD ---TX Reset Sequence state machine-- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity tx_reset_sm is -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rst_qd_c : out std_logic; - tx_pcs_rst_ch_c : out std_logic - ); -end tx_reset_sm; - -architecture tx_reset_sm_arch of tx_reset_sm is - -type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); - -signal cs: statetype; -- current state of lsm -signal ns: statetype; -- next state of lsm - -signal tx_pll_lol_qd_s_int : std_logic; -signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0); -signal rst_qd_c_int : std_logic; - -signal reset_timer1: std_logic; -signal reset_timer2: std_logic; - -signal counter1: std_logic_vector(2 downto 0); -signal TIMER1: std_logic; - -signal counter2: std_logic_vector(18 downto 0); -signal TIMER2: std_logic; - -begin - -process (refclkdiv2, rst_n) -begin - if rst_n = '0' then - cs <= QUAD_RESET; - tx_pll_lol_qd_s_int <= '1'; - tx_pcs_rst_ch_c <= '1'; - rst_qd_c <= '1'; - else if rising_edge(refclkdiv2) then - cs <= ns; - tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; - tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0); - rst_qd_c <= rst_qd_c_int; - end if; - end if; -end process; ---TIMER1 = 20ns; ---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles --- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2] - - -process (refclkdiv2, reset_timer1) -begin - if rising_edge(refclkdiv2) then - if reset_timer1 = '1' then - counter1 <= "000"; - TIMER1 <= '0'; - else - if counter1(2) = '1' then - TIMER1 <= '1'; - else - TIMER1 <='0'; - counter1 <= counter1 + 1 ; - end if; - end if; - end if; -end process; - - ---TIMER2 = 1,400,000 UI; ---WORST CASE CYCLES is with smallest multipier factor. --- This would be with X8 clock multiplier in DIV2 mode --- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES --- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES --- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] - - -process(refclkdiv2, reset_timer2) -begin - if rising_edge(refclkdiv2) then - if reset_timer2 = '1' then - counter2 <= "0000000000000000000"; - TIMER2 <= '0'; - else - if counter2(count_index) = '1' then - TIMER2 <='1'; - else - TIMER2 <='0'; - counter2 <= counter2 + 1 ; - end if; - end if; - end if; -end process; - -process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int) -begin - - reset_timer1 <= '0'; - reset_timer2 <= '0'; - - case cs is - - when QUAD_RESET => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '1'; - reset_timer1 <= '1'; - ns <= WAIT_FOR_TIMER1; - - when WAIT_FOR_TIMER1 => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '1'; - if TIMER1 = '1' then - ns <= CHECK_PLOL; - else - ns <= WAIT_FOR_TIMER1; - end if; - - when CHECK_PLOL => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '0'; - reset_timer2 <= '1'; - ns <= WAIT_FOR_TIMER2; - - when WAIT_FOR_TIMER2 => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '0'; - if TIMER2 = '1' then - if tx_pll_lol_qd_s_int = '1' then - ns <= QUAD_RESET; - else - ns <= NORMAL; - end if; - else - ns <= WAIT_FOR_TIMER2; - end if; - - when NORMAL => - tx_pcs_rst_ch_c_int <= "0000"; - rst_qd_c_int <= '0'; - if tx_pll_lol_qd_s_int = '1' then - ns <= QUAD_RESET; - else - ns <= NORMAL; - end if; - - when others => - ns <= QUAD_RESET; - - end case; - -end process; - -end tx_reset_sm_arch; - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_intclock_8b_ecp3 is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - xmit_ch0 : in std_logic; - tx_disp_correct_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - refclk2fpga : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_gbe_0_intclock_8b_ecp3; - - -architecture serdes_gbe_0_intclock_8b_ecp3_arch of serdes_gbe_0_intclock_8b_ecp3 is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - -component rx_reset_sm -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rx_serdes_rst_ch_c: out std_logic; - rx_cdr_lol_ch_s : in std_logic; - rx_los_low_ch_s : in std_logic; - rx_pcs_rst_ch_c : out std_logic -); -end component ; - -component tx_reset_sm -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rst_qd_c : out std_logic; - tx_pcs_rst_ch_c : out std_logic - ); -end component; - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH0_CDR_SRC: string; - attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "31.2500"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_REFCK2CORE: string; - attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch0_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - -signal rx_serdes_rst_ch0_c : std_logic; -signal rx_pcs_rst_ch0_c : std_logic; - --- reset sequence for rx -signal refclkdiv2_rx_ch0 : std_logic; - -signal refclkdiv2_tx_ch : std_logic; -signal tx_pcs_rst_ch_c : std_logic; -signal rst_qd_c : std_logic; - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - refclk2fpga <= refclk2fpga_sig; - rx_los_low_ch0_s <= rx_los_low_ch0_sig; - rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch0 <= tx_full_clk_ch0_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH0_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => hdoutp_ch0, - HDOUTN0 => hdoutn_ch0, - HDINP0 => hdinp_ch0, - HDINN0 => hdinn_ch0, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => rxiclk_ch0, - FF_TXI_CLK_0 => txiclk_ch0, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => rx_full_clk_ch0, - FF_RX_H_CLK_0 => rx_half_clk_ch0, - FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, - FF_TX_H_CLK_0 => tx_half_clk_ch0, - FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, - FF_TX_D_0_0 => txdata_ch0(0), - FF_TX_D_0_1 => txdata_ch0(1), - FF_TX_D_0_2 => txdata_ch0(2), - FF_TX_D_0_3 => txdata_ch0(3), - FF_TX_D_0_4 => txdata_ch0(4), - FF_TX_D_0_5 => txdata_ch0(5), - FF_TX_D_0_6 => txdata_ch0(6), - FF_TX_D_0_7 => txdata_ch0(7), - FF_TX_D_0_8 => tx_k_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => xmit_ch0, - FF_TX_D_0_11 => tx_disp_correct_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => rxdata_ch0(0), - FF_RX_D_0_1 => rxdata_ch0(1), - FF_RX_D_0_2 => rxdata_ch0(2), - FF_RX_D_0_3 => rxdata_ch0(3), - FF_RX_D_0_4 => rxdata_ch0(4), - FF_RX_D_0_5 => rxdata_ch0(5), - FF_RX_D_0_6 => rxdata_ch0(6), - FF_RX_D_0_7 => rxdata_ch0(7), - FF_RX_D_0_8 => rx_k_ch0, - FF_RX_D_0_9 => rx_disp_err_ch0, - FF_RX_D_0_10 => rx_cv_err_ch0, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => rx_serdes_rst_ch0_c, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, - FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => tx_pcs_rst_ch_c, - FFC_TXPWDNB_0 => tx_pwrup_ch0_c, - FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, - FFC_RXPWDNB_0 => rx_pwrup_ch0_c, - FFS_RLOS_LO_0 => rx_los_low_ch0_sig, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => rx_cdr_lol_ch0_sig, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => fpsc_vlo, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => fpsc_vlo, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => open, - HDOUTN3 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_TX_F_CLK_3 => open, - FF_TX_H_CLK_3 => open, - FFC_CK_CORE_RX_3 => fpsc_vlo, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA0 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIRDATA7 => open, - SCIRDATA6 => open, - SCIRDATA5 => open, - SCIRDATA4 => open, - SCIRDATA3 => open, - SCIRDATA2 => open, - SCIRDATA1 => open, - SCIRDATA0 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - --- reset sequence for rx - - P1 : PROCESS(fpga_rxrefclk_ch0, rst_n) - BEGIN - IF (rst_n = '0') THEN - refclkdiv2_rx_ch0 <= '0'; - ELSIF (fpga_rxrefclk_ch0'event and fpga_rxrefclk_ch0 = '1') THEN - refclkdiv2_rx_ch0 <= not refclkdiv2_rx_ch0; - END IF; - END PROCESS; - -rx_reset_sm_ch0 : rx_reset_sm ---synopsys translate_off - generic map (count_index => 4) ---synopsys translate_on -port map ( - refclkdiv2 => refclkdiv2_rx_ch0, - rst_n => rst_n, - rx_cdr_lol_ch_s => rx_cdr_lol_ch0_sig, - rx_los_low_ch_s => rx_los_low_ch0_sig, - tx_pll_lol_qd_s => tx_pll_lol_qd_sig, - rx_pcs_rst_ch_c => rx_pcs_rst_ch0_c, - rx_serdes_rst_ch_c => rx_serdes_rst_ch0_c); - - - - - - P5 : PROCESS(fpga_txrefclk, rst_n) - BEGIN - IF (rst_n = '0') THEN - refclkdiv2_tx_ch <= '0'; - ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN - refclkdiv2_tx_ch <= not refclkdiv2_tx_ch; - END IF; - END PROCESS; - --- reset sequence for tx -tx_reset_sm_ch : tx_reset_sm ---synopsys translate_off - generic map (count_index => 4) ---synopsys translate_on -port map ( - rst_n => rst_n, - refclkdiv2 => refclkdiv2_tx_ch, - tx_pll_lol_qd_s => tx_pll_lol_qd_sig, - rst_qd_c => rst_qd_c, - tx_pcs_rst_ch_c => tx_pcs_rst_ch_c - ); - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_gbe_0_intclock_8b_ecp3_arch ; diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd~ b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd~ deleted file mode 100644 index 58a8008..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3.vhd~ +++ /dev/null @@ -1,3113 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_CORE"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_EXT"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - ---THIS MODULE IS INSTANTIATED PER RX CHANNEL ---Reset Sequence Generator -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity rx_reset_sm is -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rx_serdes_rst_ch_c: out std_logic; - rx_cdr_lol_ch_s : in std_logic; - rx_los_low_ch_s : in std_logic; - rx_pcs_rst_ch_c : out std_logic -); -end rx_reset_sm ; - -architecture rx_reset_sm_arch of rx_reset_sm is - -type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL); - -signal cs: statetype; -- current state of lsm -signal ns: statetype; -- next state of lsm - -signal tx_pll_lol_qd_s_int: std_logic; -signal rx_los_low_int: std_logic; -signal plol_los_int: std_logic; -signal rx_lol_los : std_logic; -signal rx_lol_los_int: std_logic; -signal rx_lol_los_del: std_logic; -signal rx_pcs_rst_ch_c_int: std_logic; -signal rx_serdes_rst_ch_c_int: std_logic; - -signal reset_timer1: std_logic; -signal reset_timer2: std_logic; - -signal counter1: std_logic_vector(1 downto 0); -signal TIMER1: std_logic; - -signal counter2: std_logic_vector(18 downto 0); -signal TIMER2 : std_logic; - -begin - -rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ; - -process(refclkdiv2,rst_n) -begin - if rising_edge(refclkdiv2) then - if rst_n = '0' then - cs <= WAIT_FOR_PLOL; - rx_lol_los_int <= '1'; - rx_lol_los_del <= '1'; - tx_pll_lol_qd_s_int <= '1'; - rx_pcs_rst_ch_c <= '1'; - rx_serdes_rst_ch_c <= '0'; - rx_los_low_int <= '1'; - else - cs <= ns; - rx_lol_los_del <= rx_lol_los; - rx_lol_los_int <= rx_lol_los_del; - tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; - rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int; - rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int; - rx_los_low_int <= rx_los_low_ch_s; - end if; - end if; -end process; - ---TIMER1 = 3NS; ---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles ---A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1] - -process(refclkdiv2, reset_timer1) -begin - if rising_edge(refclkdiv2) then - if reset_timer1 = '1' then - counter1 <= "00"; - TIMER1 <= '0'; - else - if counter1(1) = '1' then - TIMER1 <='1'; - else - TIMER1 <='0'; - counter1 <= counter1 + 1 ; - end if; - end if; - end if; -end process; - ---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles ---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] - -process(refclkdiv2, reset_timer2) -begin - if rising_edge(refclkdiv2) then - if reset_timer2 = '1' then - counter2 <= "0000000000000000000"; - TIMER2 <= '0'; - else - if counter2(count_index) = '1' then - TIMER2 <='1'; - else - TIMER2 <='0'; - counter2 <= counter2 + 1 ; - end if; - end if; - end if; -end process; - - -process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2) -begin - reset_timer1 <= '0'; - reset_timer2 <= '0'; - - case cs is - when WAIT_FOR_PLOL => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal - ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next - else - ns <= RX_SERDES_RESET; - end if; - - when RX_SERDES_RESET => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '1'; - reset_timer1 <= '1'; - ns <= WAIT_FOR_TIMER1; - - - when WAIT_FOR_TIMER1 => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '1'; - if TIMER1 = '1' then - ns <= CHECK_LOL_LOS; - else - ns <= WAIT_FOR_TIMER1; - end if; - - when CHECK_LOL_LOS => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - reset_timer2 <= '1'; - ns <= WAIT_FOR_TIMER2; - - when WAIT_FOR_TIMER2 => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES - if TIMER2 = '1' then - if rx_lol_los_int = '1' then - ns <= WAIT_FOR_PLOL; - else - ns <= NORMAL; - end if; - else - ns <= WAIT_FOR_TIMER2; - end if; - else - ns <= CHECK_LOL_LOS; --RESET TIMER2 - end if; - - when NORMAL => - rx_pcs_rst_ch_c_int <= '0'; - rx_serdes_rst_ch_c_int <= '0'; - if rx_lol_los_int = '1' then - ns <= WAIT_FOR_PLOL; - else - ns <= NORMAL; - end if; - - when others => - ns <= WAIT_FOR_PLOL; - - end case; - -end process; - - -end rx_reset_sm_arch; - ---THIS MODULE IS INSTANTIATED PER TX QUAD ---TX Reset Sequence state machine-- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity tx_reset_sm is -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rst_qd_c : out std_logic; - tx_pcs_rst_ch_c : out std_logic - ); -end tx_reset_sm; - -architecture tx_reset_sm_arch of tx_reset_sm is - -type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); - -signal cs: statetype; -- current state of lsm -signal ns: statetype; -- next state of lsm - -signal tx_pll_lol_qd_s_int : std_logic; -signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0); -signal rst_qd_c_int : std_logic; - -signal reset_timer1: std_logic; -signal reset_timer2: std_logic; - -signal counter1: std_logic_vector(2 downto 0); -signal TIMER1: std_logic; - -signal counter2: std_logic_vector(18 downto 0); -signal TIMER2: std_logic; - -begin - -process (refclkdiv2, rst_n) -begin - if rst_n = '0' then - cs <= QUAD_RESET; - tx_pll_lol_qd_s_int <= '1'; - tx_pcs_rst_ch_c <= '1'; - rst_qd_c <= '1'; - else if rising_edge(refclkdiv2) then - cs <= ns; - tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; - tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0); - rst_qd_c <= rst_qd_c_int; - end if; - end if; -end process; ---TIMER1 = 20ns; ---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles --- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2] - - -process (refclkdiv2, reset_timer1) -begin - if rising_edge(refclkdiv2) then - if reset_timer1 = '1' then - counter1 <= "000"; - TIMER1 <= '0'; - else - if counter1(2) = '1' then - TIMER1 <= '1'; - else - TIMER1 <='0'; - counter1 <= counter1 + 1 ; - end if; - end if; - end if; -end process; - - ---TIMER2 = 1,400,000 UI; ---WORST CASE CYCLES is with smallest multipier factor. --- This would be with X8 clock multiplier in DIV2 mode --- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES --- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES --- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] - - -process(refclkdiv2, reset_timer2) -begin - if rising_edge(refclkdiv2) then - if reset_timer2 = '1' then - counter2 <= "0000000000000000000"; - TIMER2 <= '0'; - else - if counter2(count_index) = '1' then - TIMER2 <='1'; - else - TIMER2 <='0'; - counter2 <= counter2 + 1 ; - end if; - end if; - end if; -end process; - -process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int) -begin - - reset_timer1 <= '0'; - reset_timer2 <= '0'; - - case cs is - - when QUAD_RESET => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '1'; - reset_timer1 <= '1'; - ns <= WAIT_FOR_TIMER1; - - when WAIT_FOR_TIMER1 => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '1'; - if TIMER1 = '1' then - ns <= CHECK_PLOL; - else - ns <= WAIT_FOR_TIMER1; - end if; - - when CHECK_PLOL => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '0'; - reset_timer2 <= '1'; - ns <= WAIT_FOR_TIMER2; - - when WAIT_FOR_TIMER2 => - tx_pcs_rst_ch_c_int <= "1111"; - rst_qd_c_int <= '0'; - if TIMER2 = '1' then - if tx_pll_lol_qd_s_int = '1' then - ns <= QUAD_RESET; - else - ns <= NORMAL; - end if; - else - ns <= WAIT_FOR_TIMER2; - end if; - - when NORMAL => - tx_pcs_rst_ch_c_int <= "0000"; - rst_qd_c_int <= '0'; - if tx_pll_lol_qd_s_int = '1' then - ns <= QUAD_RESET; - else - ns <= NORMAL; - end if; - - when others => - ns <= QUAD_RESET; - - end case; - -end process; - -end tx_reset_sm_arch; - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_intclock_8b_ecp3 is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - xmit_ch0 : in std_logic; - tx_disp_correct_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_n : in std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_gbe_0_intclock_8b_ecp3; - - -architecture serdes_gbe_0_intclock_8b_ecp3_arch of serdes_gbe_0_intclock_8b_ecp3 is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - -component rx_reset_sm -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rx_serdes_rst_ch_c: out std_logic; - rx_cdr_lol_ch_s : in std_logic; - rx_los_low_ch_s : in std_logic; - rx_pcs_rst_ch_c : out std_logic -); -end component ; - -component tx_reset_sm -generic (count_index: integer :=18); -port ( - rst_n : in std_logic; - refclkdiv2 : in std_logic; - tx_pll_lol_qd_s : in std_logic; - rst_qd_c : out std_logic; - tx_pcs_rst_ch_c : out std_logic - ); -end component; - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH0_CDR_SRC: string; - attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch0_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - -signal rx_serdes_rst_ch0_c : std_logic; -signal rx_pcs_rst_ch0_c : std_logic; - --- reset sequence for rx -signal refclkdiv2_rx_ch0 : std_logic; - -signal refclkdiv2_tx_ch : std_logic; -signal tx_pcs_rst_ch_c : std_logic; -signal rst_qd_c : std_logic; - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - rx_los_low_ch0_s <= rx_los_low_ch0_sig; - rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch0 <= tx_full_clk_ch0_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH0_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => hdoutp_ch0, - HDOUTN0 => hdoutn_ch0, - HDINP0 => hdinp_ch0, - HDINN0 => hdinn_ch0, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => rxiclk_ch0, - FF_TXI_CLK_0 => txiclk_ch0, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => rx_full_clk_ch0, - FF_RX_H_CLK_0 => rx_half_clk_ch0, - FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, - FF_TX_H_CLK_0 => tx_half_clk_ch0, - FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, - FF_TX_D_0_0 => txdata_ch0(0), - FF_TX_D_0_1 => txdata_ch0(1), - FF_TX_D_0_2 => txdata_ch0(2), - FF_TX_D_0_3 => txdata_ch0(3), - FF_TX_D_0_4 => txdata_ch0(4), - FF_TX_D_0_5 => txdata_ch0(5), - FF_TX_D_0_6 => txdata_ch0(6), - FF_TX_D_0_7 => txdata_ch0(7), - FF_TX_D_0_8 => tx_k_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => xmit_ch0, - FF_TX_D_0_11 => tx_disp_correct_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => rxdata_ch0(0), - FF_RX_D_0_1 => rxdata_ch0(1), - FF_RX_D_0_2 => rxdata_ch0(2), - FF_RX_D_0_3 => rxdata_ch0(3), - FF_RX_D_0_4 => rxdata_ch0(4), - FF_RX_D_0_5 => rxdata_ch0(5), - FF_RX_D_0_6 => rxdata_ch0(6), - FF_RX_D_0_7 => rxdata_ch0(7), - FF_RX_D_0_8 => rx_k_ch0, - FF_RX_D_0_9 => rx_disp_err_ch0, - FF_RX_D_0_10 => rx_cv_err_ch0, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => rx_serdes_rst_ch0_c, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, - FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => tx_pcs_rst_ch_c, - FFC_TXPWDNB_0 => tx_pwrup_ch0_c, - FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, - FFC_RXPWDNB_0 => rx_pwrup_ch0_c, - FFS_RLOS_LO_0 => rx_los_low_ch0_sig, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => rx_cdr_lol_ch0_sig, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => fpsc_vlo, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => fpsc_vlo, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => open, - HDOUTN3 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_TX_F_CLK_3 => open, - FF_TX_H_CLK_3 => open, - FFC_CK_CORE_RX_3 => fpsc_vlo, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA0 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIRDATA7 => open, - SCIRDATA6 => open, - SCIRDATA5 => open, - SCIRDATA4 => open, - SCIRDATA3 => open, - SCIRDATA2 => open, - SCIRDATA1 => open, - SCIRDATA0 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - --- reset sequence for rx - - P1 : PROCESS(fpga_rxrefclk_ch0, rst_n) - BEGIN - IF (rst_n = '0') THEN - refclkdiv2_rx_ch0 <= '0'; - ELSIF (fpga_rxrefclk_ch0'event and fpga_rxrefclk_ch0 = '1') THEN - refclkdiv2_rx_ch0 <= not refclkdiv2_rx_ch0; - END IF; - END PROCESS; - -rx_reset_sm_ch0 : rx_reset_sm ---synopsys translate_off - generic map (count_index => 4) ---synopsys translate_on -port map ( - refclkdiv2 => refclkdiv2_rx_ch0, - rst_n => rst_n, - rx_cdr_lol_ch_s => rx_cdr_lol_ch0_sig, - rx_los_low_ch_s => rx_los_low_ch0_sig, - tx_pll_lol_qd_s => tx_pll_lol_qd_sig, - rx_pcs_rst_ch_c => rx_pcs_rst_ch0_c, - rx_serdes_rst_ch_c => rx_serdes_rst_ch0_c); - - - - - - P5 : PROCESS(fpga_txrefclk, rst_n) - BEGIN - IF (rst_n = '0') THEN - refclkdiv2_tx_ch <= '0'; - ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN - refclkdiv2_tx_ch <= not refclkdiv2_tx_ch; - END IF; - END PROCESS; - --- reset sequence for tx -tx_reset_sm_ch : tx_reset_sm ---synopsys translate_off - generic map (count_index => 4) ---synopsys translate_on -port map ( - rst_n => rst_n, - refclkdiv2 => refclkdiv2_tx_ch, - tx_pll_lol_qd_s => tx_pll_lol_qd_sig, - rst_qd_c => rst_qd_c, - tx_pcs_rst_ch_c => tx_pcs_rst_ch_c - ); - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_gbe_0_intclock_8b_ecp3_arch ; diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3_generate.log b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3_generate.log deleted file mode 100644 index 3b3aef8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_ecp3_generate.log +++ /dev/null @@ -1,29 +0,0 @@ -Starting process: Module - -Starting process: - - Module Name: serdes_gbe_0_intclock_8b_ecp3 - Core Name: PCS - LPC file : serdes_gbe_0_intclock_8b_ecp3.lpc - Parameter File : serdes_gbe_0_intclock_8b_ecp3.pp - Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b_ecp3.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/serdes_intclk/. successfully! - -/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b_ecp3 -ext readme -out serdes_gbe_0_intclock_8b_ecp3 -tpl serdes_gbe_0_intclock_8b_ecp3.tft serdes_gbe_0_intclock_8b_ecp3.vhd - -Done successfully! -File: serdes_gbe_0_intclock_8b_ecp3.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_generate.log b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_generate.log deleted file mode 100644 index 919fdf4..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/serdes_gbe_0_intclock_8b_generate.log +++ /dev/null @@ -1,29 +0,0 @@ -Starting process: Module - -Starting process: - - Module Name: serdes_gbe_0_intclock_8b - Core Name: PCS - LPC file : serdes_gbe_0_intclock_8b.lpc - Parameter File : serdes_gbe_0_intclock_8b.pp - Command line: /opt/lattice/diamond/1.3/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trbnet/gbe2_ecp2m/ipcores_ecp3/serdes_intclk/. successfully! - -/opt/lattice/diamond/1.3/bin/lin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b -ext readme -out serdes_gbe_0_intclock_8b -tpl serdes_gbe_0_intclock_8b.tft serdes_gbe_0_intclock_8b.vhd - -Done successfully! -File: serdes_gbe_0_intclock_8b.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/tx_reset_sm.naf b/gbe2_ecp3/ipcores_ecp3/serdes_intclk/tx_reset_sm.naf deleted file mode 100644 index 88793a6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk/tx_reset_sm.naf +++ /dev/null @@ -1,5 +0,0 @@ -rst_n i -refclkdiv2 i -tx_pll_lol_qd_s i -rst_qd_c o -tx_pcs_rst_ch_c o diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/msg_file.log b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/msg_file.log deleted file mode 100644 index d0edc0a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/msg_file.log +++ /dev/null @@ -1,14 +0,0 @@ - Module Name: serdes_gbe_0_intclock_8b - Core Name: PCS - LPC file : serdes_gbe_0_intclock_8b.lpc - Parameter File : serdes_gbe_0_intclock_8b.pp - Command line: /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trbnet/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50 successfully! - -/home/greg/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b -ext readme -out serdes_gbe_0_intclock_8b -tpl serdes_gbe_0_intclock_8b.tft serdes_gbe_0_intclock_8b.vhd - -Done successfully! diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.jhd b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.jhd deleted file mode 100644 index 9408b9e..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.jhd +++ /dev/null @@ -1,5 +0,0 @@ -MODULE serdes_gbe_0_intclock_8b DEFIN serdes_gbe_0_intclock_8b.vhd - SUBMODULE PCSC - INSTANCE PCSC_INST - SUBMODULE VLO - INSTANCE vlo_inst diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.lpc b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.lpc deleted file mode 100644 index 2a5b9c7..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.lpc +++ /dev/null @@ -1,145 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M50E -PartName=LFE2M50E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_gbe_0_intclock_8b -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=07/31/2010 -Time=18:08:44 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Protocol=Quad -mode=Gigabit Ethernet -Channel0=SINGLE -Channel1=DISABLE -Channel2=DISABLE -Channel3=DISABLE -Rate0=None -Rate1=None -Rate2=None -Rate3=None -TxRefClk=CORE_TXREFCLK -RxRefClk=CORE_RXREFCLK -ClkRate=1.25 -ClkMult=10X -CalClkRate=125.0 -DataWidth=8 -FPGAClkRate=125.0 -TxRefClkCM=REFCLK -RxRefClk0CM=REFCLK -RxRefClk1CM=REFCLK -RxRefClk2CM=REFCLK -RxRefClk3CM=REFCLK -ClkRateH=0.625 -ClkMultH=10XH -CalClkRateH=125.0 -DataWidthH=8 -FPGAClkRateH=62.5 -VCh0=0 -VCh1=0 -VCh2=0 -VCh3=0 -PreCh0=DISABLE -PreCh1=DISABLE -PreCh2=DISABLE -PreCh3=DISABLE -TxCh0=50 -TxCh1=50 -TxCh2=50 -TxCh3=50 -EqCh0=DISABLE -EqCh1=DISABLE -EqCh2=DISABLE -EqCh3=DISABLE -RxTermCh0=50 -RxTermCh1=50 -RxTermCh2=50 -RxTermCh3=50 -RxCoupCh0=AC -RxCoupCh1=AC -RxCoupCh2=AC -RxCoupCh3=AC -Loss=0 -CDRLoss=0 -TxTerm=50 -TxCoup=AC -TxPllLoss=0 -TxInvCh0=NORMAL -TxInvCh1=NORMAL -TxInvCh2=NORMAL -TxInvCh3=NORMAL -RxInvCh0=NORMAL -RxInvCh1=NORMAL -RxInvCh2=NORMAL -RxInvCh3=NORMAL -RxModeCh0=NORMAL -RxModeCh1=NORMAL -RxModeCh2=NORMAL -RxModeCh3=NORMAL -Plus=1100000101 -Minus=0011111010 -Mask=1111111111 -Align=AUTO -CTCCh0=NORMAL -CTCCh1=NORMAL -CTCCh2=NORMAL -CTCCh3=NORMAL -CC_MATCH1=0000000000 -CC_MATCH2=0000000000 -CC_MATCH3=0110111100 -CC_MATCH4=0001010000 -MinIPG=3 -High=9 -Low=7 -CC_MATCH_MODE=MATCH_3_4 -RxDataCh0=FALSE -RxDataCh1=FALSE -RxDataCh2=FALSE -RxDataCh3=FALSE -AlignerCh0=FALSE -AlignerCh1=FALSE -AlignerCh2=FALSE -AlignerCh3=FALSE -DetectCh0=FALSE -DetectCh1=FALSE -DetectCh2=FALSE -DetectCh3=FALSE -ELSMCh0=FALSE -ELSMCh1=FALSE -ELSMCh2=FALSE -ELSMCh3=FALSE -_teidleCh0=FALSE -_teidleCh1=FALSE -_teidleCh2=FALSE -_teidleCh3=FALSE -Ports0=FALSE -rdoPorts0=Serial Loopback -Ports1=FALSE -Ports2=FALSE -Ports3=FALSE -Ports3_1=FALSE -Ports4=FALSE -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.naf b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.naf deleted file mode 100644 index 03daf07..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.naf +++ /dev/null @@ -1,48 +0,0 @@ -core_txrefclk i -core_rxrefclk i -hdinp0 i -hdinn0 i -hdoutp0 o -hdoutn0 o -ff_rxiclk_ch0 i -ff_txiclk_ch0 i -ff_ebrd_clk_0 i -ff_txdata_ch0[7] i -ff_txdata_ch0[6] i -ff_txdata_ch0[5] i -ff_txdata_ch0[4] i -ff_txdata_ch0[3] i -ff_txdata_ch0[2] i -ff_txdata_ch0[1] i -ff_txdata_ch0[0] i -ff_rxdata_ch0[7] o -ff_rxdata_ch0[6] o -ff_rxdata_ch0[5] o -ff_rxdata_ch0[4] o -ff_rxdata_ch0[3] o -ff_rxdata_ch0[2] o -ff_rxdata_ch0[1] o -ff_rxdata_ch0[0] o -ff_tx_k_cntrl_ch0 i -ff_rx_k_cntrl_ch0 o -ff_rxfullclk_ch0 o -ff_xmit_ch0 i -ff_correct_disp_ch0 i -ff_disp_err_ch0 o -ff_cv_ch0 o -ff_rx_even_ch0 o -ffc_rrst_ch0 i -ffc_lane_tx_rst_ch0 i -ffc_lane_rx_rst_ch0 i -ffc_txpwdnb_ch0 i -ffc_rxpwdnb_ch0 i -ffs_rlos_lo_ch0 o -ffs_ls_sync_status_ch0 o -ffs_rlol_ch0 o -oob_out_ch0 o -ffc_macro_rst i -ffc_quad_rst i -ffc_trst i -ff_txfullclk o -ff_txhalfclk o -ffs_plol o diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.pp b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.pp deleted file mode 100644 index 20ee73c..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.pp +++ /dev/null @@ -1,119 +0,0 @@ -#define _device_name "LFE2M50E" -#define _protocol_mode "Quad Based Protocol Mode" -#define _protocol "GIGE" -#define _ch0_mode "SINGLE" -#define _ch1_mode "DISABLE" -#define _ch2_mode "DISABLE" -#define _ch3_mode "DISABLE" -#define _pll_txsrc "CORE_TXREFCLK" -#define _pll_rxsrc "CORE_RXREFCLK" -#define _datarange "MED" -#define _refclk_mult "10X" -#define _refclk_rate 125.0 -#define _data_width "8" -#define _fpgaintclk_rate 125.0 -#define _ch0_tdrv_amp "0" -#define _ch1_tdrv_amp "0" -#define _ch2_tdrv_amp "0" -#define _ch3_tdrv_amp "0" -#define _ch0_tx_pre "DISABLE" -#define _ch1_tx_pre "DISABLE" -#define _ch2_tx_pre "DISABLE" -#define _ch3_tx_pre "DISABLE" -#define _ch0_rterm_tx "50" -#define _ch1_rterm_tx "50" -#define _ch2_rterm_tx "50" -#define _ch3_rterm_tx "50" -#define _ch0_rx_eq "DISABLE" -#define _ch1_rx_eq "DISABLE" -#define _ch2_rx_eq "DISABLE" -#define _ch3_rx_eq "DISABLE" -#define _ch0_rterm_rx "50" -#define _ch1_rterm_rx "50" -#define _ch2_rterm_rx "50" -#define _ch3_rterm_rx "50" -#define _ch0_rx_dcc "AC" -#define _ch1_rx_dcc "AC" -#define _ch2_rx_dcc "AC" -#define _ch3_rx_dcc "AC" -#define _los_threshold "0" -#define _pll_term "50" -#define _pll_dcc "AC" -#define _pll_lol_set "0" -#define _ch0_tx_sb "NORMAL" -#define _ch1_tx_sb "NORMAL" -#define _ch2_tx_sb "NORMAL" -#define _ch3_tx_sb "NORMAL" -#define _ch0_rx_sb "NORMAL" -#define _ch1_rx_sb "NORMAL" -#define _ch2_rx_sb "NORMAL" -#define _ch3_rx_sb "NORMAL" -#define _ch0_8b10b "NORMAL" -#define _ch1_8b10b "NORMAL" -#define _ch2_8b10b "NORMAL" -#define _ch3_8b10b "NORMAL" -#define _comma_a "1100000101" -#define _comma_b "0011111010" -#define _comma_m "1111111111" -#define _comma_align "AUTO" -#define _ch0_ctc_byp "NORMAL" -#define _ch1_ctc_byp "NORMAL" -#define _ch2_ctc_byp "NORMAL" -#define _ch3_ctc_byp "NORMAL" -#define _cc_match1 "0000000000" -#define _cc_match2 "0000000000" -#define _cc_match3 "0110111100" -#define _cc_match4 "0001010000" -#define _cc_match_mode "MATCH_3_4" -#define _cc_min_ipg "3" -#define _cchmark "9" -#define _cclmark "7" -#define _ch0_ird "FALSE" -#define _ch1_ird "FALSE" -#define _ch2_ird "FALSE" -#define _ch3_ird "FALSE" -#define _ch0_elsm "FALSE" -#define _ch1_elsm "FALSE" -#define _ch2_elsm "FALSE" -#define _ch3_elsm "FALSE" -#define _ch0_teidle "FALSE" -#define _ch1_teidle "FALSE" -#define _ch2_teidle "FALSE" -#define _ch3_teidle "FALSE" -#define _loopback "FALSE" -#define _lbtype "Serial Loopback" -#define _refck2core "FALSE" -#define _pllqclkports "FALSE" -#define _sci_ports "FALSE" -#define _sci_int_port "FALSE" -#define _errsports "FALSE" -#define _rst_gen "DISABLED" -#define _rx_los_port0 "Internal" -#define _rx_los_port1 "Internal" -#define _rx_los_port2 "Internal" -#define _rx_los_port3 "Internal" - -#define _ch0_rx_ficlk_rate 125.0 -#define _ch1_rx_ficlk_rate 125.0 -#define _ch2_rx_ficlk_rate 125.0 -#define _ch3_rx_ficlk_rate 125.0 - -#define _ch0_rx_hiclk_rate 62.5 -#define _ch1_rx_hiclk_rate 62.5 -#define _ch2_rx_hiclk_rate 62.5 -#define _ch3_rx_hiclk_rate 62.5 - -#define _ch0_rx_qiclk_rate 31.25 -#define _ch1_rx_qiclk_rate 31.25 -#define _ch2_rx_qiclk_rate 31.25 -#define _ch3_rx_qiclk_rate 31.25 - -#define _tx_ficlk_rate 125.0 -#define _tx_hiclk_rate 62.5 -#define _tx_qiclk_rate 31.25 - -#define _circuit_name serdes_gbe_0_intclock_8b -#define _lang vhdl - -#include -#include diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.readme b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.readme deleted file mode 100644 index b286cf3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.readme +++ /dev/null @@ -1,139 +0,0 @@ - - TOOL: orcapp - DATE: 19-MAR-2008 13:11:51 - TITLE: Lattice Semiconductor Corporation - MODULE: serdes_gbe_0_intclock_8b - DESIGN: serdes_gbe_0_intclock_8b - FILENAME: serdes_gbe_0_intclock_8b.readme - PROJECT: Unknown - VERSION: 2.0 - This file is auto generated by the ispLEVER - - -NOTE: This readme file has been provided to instantiate the interface -netlist. Since this template contains synthesis attributes for precision that -are crucial to the design flow, we recommend that you use this -template in your FPGA design. -entity chip is -port ( - --- Add your FPGA design top level I/Os here - - --- ASIC side pins for PCSA. These pins must exist for the --- PCS core. - refclkp : in std_logic; - refclkn : in std_logic; - hdinp0 : in std_logic; - hdinn0 : in std_logic; - hdinp1 : in std_logic; - hdinn1 : in std_logic; - hdinp2 : in std_logic; - hdinn2 : in std_logic; - hdinp3 : in std_logic; - hdinn3 : in std_logic; - - hdoutp0 : out std_logic; - hdoutn0 : out std_logic; - hdoutp1 : out std_logic; - hdoutn1 : out std_logic; - hdoutp2 : out std_logic; - hdoutn2 : out std_logic; - hdoutp3 : out std_logic; - hdoutn3 : out std_logic; - - -); -end chip; - -architecture chip_arch of chip is - --- This defines all the high-speed ports. You may have to remove --- some of them depending on your design. -attribute nopad : string; -attribute nopad of - refclkp, refclkn, - hdinp0, hdinn0, hdinp1, hdinn1, - hdinp2, hdinn2, hdinp3, hdinn3, - hdoutp0, hdoutn0, hdoutp1, hdoutn1, - hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true"; - - COMPONENT serdes_gbe_0_intclock_8b - PORT( - core_txrefclk : IN std_logic; - core_rxrefclk : IN std_logic; - hdinp0 : IN std_logic; - hdinn0 : IN std_logic; - ff_rxiclk_ch0 : IN std_logic; - ff_txiclk_ch0 : IN std_logic; - ff_ebrd_clk_0 : IN std_logic; - ff_txdata_ch0 : IN std_logic_vector(7 downto 0); - ff_tx_k_cntrl_ch0 : IN std_logic; - ff_xmit_ch0 : IN std_logic; - ff_correct_disp_ch0 : IN std_logic; - ffc_rrst_ch0 : IN std_logic; - ffc_lane_tx_rst_ch0 : IN std_logic; - ffc_lane_rx_rst_ch0 : IN std_logic; - ffc_txpwdnb_ch0 : IN std_logic; - ffc_rxpwdnb_ch0 : IN std_logic; - ffc_macro_rst : IN std_logic; - ffc_quad_rst : IN std_logic; - ffc_trst : IN std_logic; - hdoutp0 : OUT std_logic; - hdoutn0 : OUT std_logic; - ff_rxdata_ch0 : OUT std_logic_vector(7 downto 0); - ff_rx_k_cntrl_ch0 : OUT std_logic; - ff_rxfullclk_ch0 : OUT std_logic; - ff_disp_err_ch0 : OUT std_logic; - ff_cv_ch0 : OUT std_logic; - ff_rx_even_ch0 : OUT std_logic; - ffs_rlos_lo_ch0 : OUT std_logic; - ffs_ls_sync_status_ch0 : OUT std_logic; - ffs_rlol_ch0 : OUT std_logic; - oob_out_ch0 : OUT std_logic; - ff_txfullclk : OUT std_logic; - ff_txhalfclk : OUT std_logic; - ffs_plol : OUT std_logic - ); - END COMPONENT; - - - - uut: serdes_gbe_0_intclock_8b PORT MAP( - core_txrefclk => core_txrefclk, - core_rxrefclk => core_rxrefclk, - hdinp0 => hdinp0, - hdinn0 => hdinn0, - hdoutp0 => hdoutp0, - hdoutn0 => hdoutn0, - ff_rxiclk_ch0 => ff_rxiclk_ch0, - ff_txiclk_ch0 => ff_txiclk_ch0, - ff_ebrd_clk_0 => ff_ebrd_clk_0, - ff_txdata_ch0 => ff_txdata_ch0, - ff_rxdata_ch0 => ff_rxdata_ch0, - ff_tx_k_cntrl_ch0 => ff_tx_k_cntrl_ch0, - ff_rx_k_cntrl_ch0 => ff_rx_k_cntrl_ch0, - ff_rxfullclk_ch0 => ff_rxfullclk_ch0, - ff_xmit_ch0 => ff_xmit_ch0, - ff_correct_disp_ch0 => ff_correct_disp_ch0, - ff_disp_err_ch0 => ff_disp_err_ch0, - ff_cv_ch0 => ff_cv_ch0, - ff_rx_even_ch0 => ff_rx_even_ch0, - ffc_rrst_ch0 => ffc_rrst_ch0, - ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst_ch0, - ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst_ch0, - ffc_txpwdnb_ch0 => ffc_txpwdnb_ch0, - ffc_rxpwdnb_ch0 => ffc_rxpwdnb_ch0, - ffs_rlos_lo_ch0 => ffs_rlos_lo_ch0, - ffs_ls_sync_status_ch0 => ffs_ls_sync_status_ch0, - ffs_rlol_ch0 => ffs_rlol_ch0, - oob_out_ch0 => oob_out_ch0, - ffc_macro_rst => ffc_macro_rst, - ffc_quad_rst => ffc_quad_rst, - ffc_trst => ffc_trst, - ff_txfullclk => ff_txfullclk, - ff_txhalfclk => ff_txhalfclk, - ffs_plol => ffs_plol - ); - - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.tft b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.tft deleted file mode 100644 index 3f60410..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.tft +++ /dev/null @@ -1,98 +0,0 @@ -@set suppresnewline=on@ - -@comment --------------------------------------------------------------------- @ -@comment Template-drive TFI generator @ -@comment Template for TFI generation. @ -@comment --------------------------------------------------------------------- @ - -@set suppresnewline=off@ - TOOL: orcapp - DATE: 19-MAR-2008 13:11:51 - TITLE: %title% - MODULE: %module% - DESIGN: %module% - FILENAME: %filename% - PROJECT: %project% - VERSION: %ver% - This file is auto generated by the ispLEVER -@set suppresnewline=on@ - -@cr@ -@cr@ - -@set sigdelim=@ - -NOTE: This readme file has been provided to instantiate the interface@cr@ -netlist. Since this template contains synthesis attributes for precision that@cr@ -are crucial to the design flow, we recommend that you use this@cr@ -template in your FPGA design.@cr@ -entity chip is@cr@ -port (@cr@ -@cr@ --- Add your FPGA design top level I/Os here@cr@ -@cr@ -@cr@ --- ASIC side pins for PCSA. These pins must exist for the@cr@ --- PCS core.@cr@ - refclkp : in std_logic;@cr@ - refclkn : in std_logic;@cr@ - hdinp0 : in std_logic;@cr@ - hdinn0 : in std_logic;@cr@ - hdinp1 : in std_logic;@cr@ - hdinn1 : in std_logic;@cr@ - hdinp2 : in std_logic;@cr@ - hdinn2 : in std_logic;@cr@ - hdinp3 : in std_logic;@cr@ - hdinn3 : in std_logic;@cr@ -@cr@ - hdoutp0 : out std_logic;@cr@ - hdoutn0 : out std_logic;@cr@ - hdoutp1 : out std_logic;@cr@ - hdoutn1 : out std_logic;@cr@ - hdoutp2 : out std_logic;@cr@ - hdoutn2 : out std_logic;@cr@ - hdoutp3 : out std_logic;@cr@ - hdoutn3 : out std_logic;@cr@ -@cr@ -@cr@ -);@cr@ -end chip;@cr@ -@cr@ -architecture chip_arch of chip is@cr@ -@cr@ --- This defines all the high-speed ports. You may have to remove@cr@ --- some of them depending on your design.@cr@ -attribute nopad : string;@cr@ -attribute nopad of@cr@ - refclkp, refclkn,@cr@ - hdinp0, hdinn0, hdinp1, hdinn1,@cr@ - hdinp2, hdinn2, hdinp3, hdinn3,@cr@ - hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@ - hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@ - -@cr@ -@tab@COMPONENT %module% -@set sigdelim=@ -@cr@@tab@PORT( -@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ -@ifhas oport=*@ @comment if the design has any output ports... @ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ - @set sigdelim=;@ - @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ -@endif@ -@ifnhas oport=*@ @comment we need an "else in this language! @ - @set sigdelim=;@ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ -@endif@ -@cr@@tab@@tab@);@cr@ -@tab@END COMPONENT;@cr@@cr@ -@comment Now do a signal declaration for each port @ - -@cr@@cr@ -@comment do the component instantiation @ -@set sigdelim=,@ -@tab@uut: %module% PORT MAP( -@iterate@%port% -@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ -@cr@@tab@);@cr@@cr@ -@set suppresnewline=off@ diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.txt b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.txt deleted file mode 100644 index 4ac16e9..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.txt +++ /dev/null @@ -1,49 +0,0 @@ - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSC quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSC quad to the final design requirements. - -DEVICE_NAME "LFE2M50E" -PROTOCOL "GIGE" -CH0_MODE "SINGLE" -CH1_MODE "DISABLE" -CH2_MODE "DISABLE" -CH3_MODE "DISABLE" -PLL_SRC "CORE_TXREFCLK" -DATARANGE "MED" -CH0_CDR_SRC "CORE_RXREFCLK" -CH0_DATA_WIDTH "8" -CH0_REFCK_MULT "10X" -#REFCLK_RATE 125.0 -#FPGAINTCLK_RATE 125.0 -CH0_TDRV_AMP "0" -CH0_TX_PRE "DISABLE" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLE" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -LOS_THRESHOLD "0" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "NORMAL" -CH0_RX_SB "NORMAL" -CH0_8B10B "NORMAL" -COMMA_A "1100000101" -COMMA_B "0011111010" -COMMA_M "1111111111" -CH0_COMMA_ALIGN "AUTO" -CH0_CTC_BYP "BYPASS" -CC_MATCH1 "0000000000" -CC_MATCH2 "0000000000" -CC_MATCH3 "0110111100" -CC_MATCH4 "0001010000" -CC_MATCH_MODE "MATCH_3_4" -CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -OS_REFCK2CORE "0" -OS_PLLQCLKPORTS "0" -OS_INT_ALL "0" - diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.vhd b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.vhd deleted file mode 100644 index b57bb59..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.vhd +++ /dev/null @@ -1,2202 +0,0 @@ - - ---synopsys translate_off - -library pcsc_work; -use pcsc_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSC is -GENERIC( - CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); - -end PCSC; - -architecture PCSC_arch of PCSC is - -component PCSC_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - -begin - -PCSC_sim_inst : PCSC_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, - FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, - FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, - FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, - FF_TX_F_CLK => FF_TX_F_CLK, - FF_TX_H_CLK => FF_TX_H_CLK, - FF_TX_Q_CLK => FF_TX_Q_CLK, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - OOB_OUT_0 => OOB_OUT_0, - OOB_OUT_1 => OOB_OUT_1, - OOB_OUT_2 => OOB_OUT_2, - OOB_OUT_3 => OOB_OUT_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7 - ); - -end PCSC_arch; - ---synopsys translate_on - ---synopsys translate_off -library ECP2; -use ECP2.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_intclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); - port ( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - ffs_plol : out std_logic); - -end serdes_gbe_0_intclock_8b; - -architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; -component PCSC ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_TX_F_CLK: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_TX_H_CLK: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK of PCSC_INST : label is "62.5"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal fpsc_vlo : std_logic := '0'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSC_INST : PCSC ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - FFC_CK_CORE_TX => core_txrefclk, - FFC_CK_CORE_RX => core_rxrefclk, - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - HDINP0 => hdinp0, - HDINN0 => hdinn0, - HDOUTP0 => hdoutp0, - HDOUTN0 => hdoutn0, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => ff_rxiclk_ch0, - FF_TXI_CLK_0 => ff_txiclk_ch0, - FF_EBRD_CLK_0 => ff_ebrd_clk_0, - FF_RX_F_CLK_0 => ff_rxfullclk_ch0, - FF_RX_H_CLK_0 => open, - FF_RX_Q_CLK_0 => open, - FF_TX_D_0_0 => ff_txdata_ch0(0), - FF_TX_D_0_1 => ff_txdata_ch0(1), - FF_TX_D_0_2 => ff_txdata_ch0(2), - FF_TX_D_0_3 => ff_txdata_ch0(3), - FF_TX_D_0_4 => ff_txdata_ch0(4), - FF_TX_D_0_5 => ff_txdata_ch0(5), - FF_TX_D_0_6 => ff_txdata_ch0(6), - FF_TX_D_0_7 => ff_txdata_ch0(7), - FF_TX_D_0_8 => ff_tx_k_cntrl_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => ff_xmit_ch0, - FF_TX_D_0_11 => ff_correct_disp_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => ff_rxdata_ch0(0), - FF_RX_D_0_1 => ff_rxdata_ch0(1), - FF_RX_D_0_2 => ff_rxdata_ch0(2), - FF_RX_D_0_3 => ff_rxdata_ch0(3), - FF_RX_D_0_4 => ff_rxdata_ch0(4), - FF_RX_D_0_5 => ff_rxdata_ch0(5), - FF_RX_D_0_6 => ff_rxdata_ch0(6), - FF_RX_D_0_7 => ff_rxdata_ch0(7), - FF_RX_D_0_8 => ff_rx_k_cntrl_ch0, - FF_RX_D_0_9 => ff_disp_err_ch0, - FF_RX_D_0_10 => ff_cv_ch0, - FF_RX_D_0_11 => ff_rx_even_ch0, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - FFC_RRST_0 => ffc_rrst_ch0, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFS_PCIE_DONE_0 => open, - FFS_PCIE_CON_0 => open, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, - FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, - FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, - FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, - FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, - FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, - FFS_CC_UNDERRUN_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - FFS_RLOL_0 => ffs_rlol_ch0, - OOB_OUT_0 => oob_out_ch0, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - HDOUTP1 => open, - HDOUTN1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_RX_Q_CLK_1 => open, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_PCIE_CON_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - OOB_OUT_1 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - HDOUTP2 => open, - HDOUTN2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_RX_Q_CLK_2 => open, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_PCIE_CON_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - OOB_OUT_2 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - HDOUTP3 => open, - HDOUTN3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_RX_Q_CLK_3 => open, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_PCIE_CON_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - OOB_OUT_3 => open, - SCIWDATA0 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA7 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIRDATA0 => open, - SCIRDATA1 => open, - SCIRDATA2 => open, - SCIRDATA3 => open, - SCIRDATA4 => open, - SCIRDATA5 => open, - SCIRDATA6 => open, - SCIRDATA7 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_MACRO_RST => ffc_macro_rst, - FFC_QUAD_RST => ffc_quad_rst, - FFC_TRST => ffc_trst, - FF_TX_F_CLK => ff_txfullclk, - FF_TX_H_CLK => ff_txhalfclk, - FF_TX_Q_CLK => open, - REFCK2CORE => open, - CIN0 => cin(0), - CIN1 => cin(1), - CIN2 => cin(2), - CIN3 => cin(3), - CIN4 => cin(4), - CIN5 => cin(5), - CIN6 => cin(6), - CIN7 => cin(7), - CIN8 => cin(8), - CIN9 => cin(9), - CIN10 => cin(10), - CIN11 => cin(11), - COUT0 => cout(0), - COUT1 => cout(1), - COUT2 => cout(2), - COUT3 => cout(3), - COUT4 => cout(4), - COUT5 => cout(5), - COUT6 => cout(6), - COUT7 => cout(7), - COUT8 => cout(8), - COUT9 => cout(9), - COUT10 => cout(10), - COUT11 => cout(11), - COUT12 => cout(12), - COUT13 => cout(13), - COUT14 => cout(14), - COUT15 => cout(15), - COUT16 => cout(16), - COUT17 => cout(17), - COUT18 => cout(18), - COUT19 => cout(19), - FFS_PLOL => ffs_plol); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end serdes_gbe_0_intclock_8b_arch ; diff --git a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b_generate.log b/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b_generate.log deleted file mode 100644 index ce2cdde..0000000 --- a/gbe2_ecp3/ipcores_ecp3/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b_generate.log +++ /dev/null @@ -1,27 +0,0 @@ -Starting process: - - Module Name: serdes_gbe_0_intclock_8b - Core Name: PCS - LPC file : serdes_gbe_0_intclock_8b.lpc - Parameter File : serdes_gbe_0_intclock_8b.pp - Command line: /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_gbe_0_intclock_8b.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trbnet/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50 successfully! - -/home/greg/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_gbe_0_intclock_8b -ext readme -out serdes_gbe_0_intclock_8b -tpl serdes_gbe_0_intclock_8b.tft serdes_gbe_0_intclock_8b.vhd - -Done successfully! -File: serdes_gbe_0_intclock_8b.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v b/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v deleted file mode 100755 index b9edbef..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v +++ /dev/null @@ -1,66 +0,0 @@ -//************************************************************************** -// ************************************************************************* -// * LATTICE SEMICONDUCTOR CONFIDENTIAL * -// * PROPRIETARY NOTE * -// * * -// * This software contains information confidential and proprietary * -// * to Lattice Semiconductor Corporation. It shall not be reproduced * -// * in whole or in part, or transferred to other documents, or disclosed * -// * to third parties, or used for any purpose other than that for which * -// * it was obtained, without the prior written consent of Lattice * -// * Semiconductor Corporation. All rights reserved. * -// * * -// ************************************************************************* -//************************************************************************** - -`timescale 1ns/100ps - -module rate_resolution ( - gbe_mode, - sgmii_mode, - an_enable, - advertised_rate, - link_partner_rate, - non_an_rate, - - operational_rate -); - -input gbe_mode; -input sgmii_mode; -input an_enable; -input [1:0] advertised_rate; // 00=10Mbps 01=100Mbps 10=1Gbps -input [1:0] link_partner_rate; -input [1:0] non_an_rate; - -output [1:0] operational_rate; -reg [1:0] operational_rate; - - - -always @(gbe_mode or sgmii_mode or an_enable or advertised_rate or link_partner_rate or non_an_rate) begin - if (gbe_mode) begin - operational_rate <= 2'b10; // 1Gbps - end - else begin - if (an_enable) begin - if (sgmii_mode) begin - // PHY Mode - operational_rate <= advertised_rate; - end - else begin - // MAC Mode - operational_rate <= link_partner_rate; - end - end - else begin - // If auto-negotiation disabled, then this becomes active rate - operational_rate <= non_an_rate; - end - end -end - - - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v b/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v deleted file mode 100755 index 73e0b86..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v +++ /dev/null @@ -1,918 +0,0 @@ -//************************************************************************** -// ************************************************************************* -// * LATTICE SEMICONDUCTOR CONFIDENTIAL * -// * PROPRIETARY NOTE * -// * * -// * This software contains information confidential and proprietary * -// * to Lattice Semiconductor Corporation. It shall not be reproduced * -// * in whole or in part, or transferred to other documents, or disclosed * -// * to third parties, or used for any purpose other than that for which * -// * it was obtained, without the prior written consent of Lattice * -// * Semiconductor Corporation. All rights reserved. * -// * * -// ************************************************************************* -//************************************************************************** - -`timescale 1ns/100ps - -module register_interface_hb ( - - // Control Signals - rst_n, - hclk, - gbe_mode, - sgmii_mode, - - // Host Bus - hcs_n, - hwrite_n, - haddr, - hdatain, - - hdataout, - hready_n, - - // Register Inputs - mr_an_enable, - mr_restart_an, - mr_adv_ability, - - // Register Outputs - mr_main_reset, - mr_an_complete, - mr_page_rx, - mr_lp_adv_ability - ); - - -input rst_n ; -input hclk ; -input gbe_mode ; -input sgmii_mode ; - -input hcs_n; -input hwrite_n; -input [3:0] haddr; -input [7:0] hdatain; - -output [7:0] hdataout; -output hready_n; - -input mr_an_complete; -input mr_page_rx; -input [15:0] mr_lp_adv_ability; - -output mr_an_enable; -output mr_restart_an; -output [15:0] mr_adv_ability; -output mr_main_reset; - -regs_hb regs ( - .rst_n (rst_n), - .hclk (hclk), - - .gbe_mode (gbe_mode), - .sgmii_mode (sgmii_mode), - - .hcs_n (hcs_n), - .hwrite_n (hwrite_n), - .haddr (haddr), - .hdatain (hdatain), - - .hdataout (hdataout), - .hready_n (hready_n), - - .mr_an_complete (mr_an_complete), - .mr_page_rx (mr_page_rx), - .mr_lp_adv_ability (mr_lp_adv_ability), - - .mr_main_reset (mr_main_reset), - .mr_an_enable (mr_an_enable), - .mr_restart_an (mr_restart_an), - .mr_adv_ability (mr_adv_ability) -); -endmodule - - - - - - -module register_0_hb ( - rst_n, - clk, - cs_0, - cs_1, - write, - ready, - data_in, - - data_out, - mr_main_reset, - mr_an_enable, - mr_restart_an -); - -input rst_n; -input clk; -input cs_0; -input cs_1; -input write; -input ready; -input [15:0] data_in; - -output [15:0] data_out; -output mr_main_reset; // bit D15 // R/W // Self Clearing -output mr_an_enable; // bit D12 // R/W -output mr_restart_an; // bit D09 // R/W // Self Clearing - -reg [15:0] data_out; -reg mr_main_reset; -reg mr_an_enable; -reg mr_restart_an; -reg m_m_r; -reg m_r_a; - - -// Write Operations - - // Low Portion of Register[D7:D0] has no - // implemented bits. Therefore, no write - // operations here. - - // High Portion of Register[D15:D8] - always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - mr_main_reset <= 0; // default value - mr_an_enable <= 1; // default value - mr_restart_an <= 0; // default value - m_m_r <= 0; - m_r_a <= 0; - end - else begin - - // Do the Writes - if (cs_1 && ready && write) begin - mr_main_reset <= data_in[15]; - mr_an_enable <= data_in[12]; - mr_restart_an <= data_in[9]; - end - - // Delay the Self Clearing Register Bits - m_m_r <= mr_main_reset; - m_r_a <= mr_restart_an; - - // Do the Self Clearing - if (m_m_r) - mr_main_reset <= 0; - - if (m_r_a) - mr_restart_an <= 0; - end - end - - - - - -// Read Operations - always @(*) begin - data_out[7:0] = 8'b00000000; - data_out[15] = mr_main_reset; - data_out[14] = 0; - data_out[13] = 0; - data_out[12] = mr_an_enable; - data_out[11] = 0; - data_out[10] = 0; - data_out[9] = mr_restart_an; - data_out[8] = 0; - end -endmodule - -module register_1_hb ( - rst_n, - cs_0, - cs_1, - mr_an_complete, - - data_out -); - -input rst_n; -input cs_0; -input cs_1; -input mr_an_complete; // bit D5 // Read-Only - -output [15:0] data_out; - -reg [15:0] data_out; - - -// Read Operations - - always @(*) begin - data_out[7] <= 0; - data_out[6] <= 0; - data_out[5] <= mr_an_complete; - data_out[4] <= 0; - data_out[3] <= 0; - data_out[2] <= 0; - data_out[1] <= 0; - data_out[0] <= 0; - data_out[15:8] <= 8'b00000000; - end -endmodule - -module register_4_hb ( - rst_n, - clk, - gbe_mode, - sgmii_mode, - cs_0, - cs_1, - write, - ready, - data_in, - - data_out, - mr_adv_ability -); - -parameter [15:0] initval_gbe = 16'h0020; -parameter [15:0] initval_phy = 16'hd801; -parameter [15:0] initval_mac = 16'h4001; - -input rst_n; -input clk; -input gbe_mode; -input sgmii_mode; -input cs_0; -input cs_1; -input write; -input ready; -input [15:0] data_in; - -output [15:0] data_out; -output [15:0] mr_adv_ability; // When sgmii_mode == 1 == PHY - // all bits D15-D0 are R/W, - /////////////////////////////////// - // D15 = Link Status (1=up, 0=down) - // D14 = Can be written but has no effect - // on autonegotiation. Instead - // the autonegotiation state machine - // controls the utilization of this bit. - // D12 = Duplex Mode (1=full, 0=half) - // D11:10 = Speed (11=reserved) - // (10=1000Mbps) - // (01=100 Mbps) - // (00=10 Mbps) - // D0 = 1 - // all other bits = 0 - /////////////////////////////////// - //When sgmii_mode == 0 = MAC - // all bits D15-D0 are R/W, - // D14 = Can be written but has no effect - // on autonegotiation. Instead - // the autonegotiation state machine - // controls the utilization of this bit. - // D0 = 1 - // all other bits = 0 - /////////////////////////////////// - - -reg [15:0] data_out; -reg [15:0] mr_adv_ability; -reg rst_d1; -reg rst_d2; -reg rst_d3; -reg rst_d4; -reg rst_d5; -reg rst_d6; -reg rst_d7; -reg rst_d8; -reg sync_reset; -reg sgmii_mode_d1; -reg sgmii_mode_d2; -reg sgmii_mode_d3; -reg sgmii_mode_d4; -reg sgmii_mode_change; -reg gbe_mode_d1; -reg gbe_mode_d2; -reg gbe_mode_d3; -reg gbe_mode_d4; -reg gbe_mode_change; - -// generate a synchronous reset signal -// note: this method is used so that -// an initval can be applied during -// device run-time, instead of at compile time -always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - rst_d1 <= 0; - rst_d2 <= 0; - rst_d3 <= 0; - rst_d4 <= 0; - rst_d5 <= 0; - rst_d6 <= 0; - rst_d7 <= 0; - rst_d8 <= 0; - sync_reset <= 0; - end - else begin - rst_d1 <= 1; - rst_d2 <= rst_d1; - rst_d3 <= rst_d2; - rst_d4 <= rst_d3; - rst_d5 <= rst_d4; - rst_d6 <= rst_d5; - rst_d7 <= rst_d6; - rst_d8 <= rst_d7; - - // asserts on rising edge of rst_d8 - sync_reset <= !rst_d8 & rst_d7; - end -end - - -// Detect change in sgmii_mode -always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - sgmii_mode_d1 <= 0; - sgmii_mode_d2 <= 0; - sgmii_mode_d3 <= 0; - sgmii_mode_d4 <= 0; - sgmii_mode_change <= 0; - end - else begin - - // deboggle - sgmii_mode_d1 <= sgmii_mode; - sgmii_mode_d2 <= sgmii_mode_d1; - - // delay - sgmii_mode_d3 <= sgmii_mode_d2; - sgmii_mode_d4 <= sgmii_mode_d3; - - // detect change - if (sgmii_mode_d3 != sgmii_mode_d4) - sgmii_mode_change <= 1; - else - sgmii_mode_change <= 0; - end -end - - -// Detect change in gbe_mode -always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - gbe_mode_d1 <= 0; - gbe_mode_d2 <= 0; - gbe_mode_d3 <= 0; - gbe_mode_d4 <= 0; - gbe_mode_change <= 0; - end - else begin - - // deboggle - gbe_mode_d1 <= gbe_mode; - gbe_mode_d2 <= gbe_mode_d1; - - // delay - gbe_mode_d3 <= gbe_mode_d2; - gbe_mode_d4 <= gbe_mode_d3; - - // detect change - if (gbe_mode_d3 != gbe_mode_d4) - gbe_mode_change <= 1; - else - gbe_mode_change <= 0; - end -end - - -// Write Operations - // Low Portion of Register[D7:D0] - always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - mr_adv_ability[7:0] <= 8'h01; - end - else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin - if (gbe_mode_d4) - mr_adv_ability[7:0] <= initval_gbe[7:0]; - else if (sgmii_mode) - mr_adv_ability[7:0] <= initval_phy[7:0]; - else - mr_adv_ability[7:0] <= initval_mac[7:0]; - end - else begin - if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin - mr_adv_ability[7:0] <= data_in[7:0]; - end - end - end - - - // High Portion of Register[D15:D8] - always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - mr_adv_ability[15:8] <= 8'h40; // default - end - else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin - if (gbe_mode_d4) - mr_adv_ability[15:8] <= initval_gbe[15:8]; - else if (sgmii_mode) - mr_adv_ability[15:8] <= initval_phy[15:8]; - else - mr_adv_ability[15:8] <= initval_mac[15:8]; - end - else begin - if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin - mr_adv_ability[15:8] <= data_in[15:8]; - end - end - end - - - - - - - - - -// Read Operations - - always @(*) begin - data_out[7:0] <= mr_adv_ability[7:0]; - data_out[15:8] <= mr_adv_ability[15:8]; - end - -endmodule - - - - - - -module register_5_hb ( - rst_n, - mr_lp_adv_ability, - cs_0, - cs_1, - ready, - - data_out -); - -input rst_n; -input cs_0; -input cs_1; -input ready; -input [15:0] mr_lp_adv_ability; - // This entire register is read-only - /////////////////////////////////// - // When sgmii_mode == 0 == MAC - /////////////////////////////////// - // D15 = PHY Link Status (1=up, 0=down) - // D14 = PHY Autonegotiation Handshake - // D12 = PHY Duplex Mode (1=full, 0=half) - // D11:10 = PHY Speed (11=reserved) - // (10=1000Mbps) - // (01=100 Mbps) - // (00=10 Mbps) - // D0 = 1 - // all other bits = 0 - /////////////////////////////////// - //When sgmii_mode == 1 = PHY - // D14 = MAC Autonegotiation Handshake - // D0 = 1 - // all other bits = 0 - /////////////////////////////////// -output [15:0] data_out; - -reg [15:0] data_out; - -// Read Operations - - always @(*) begin - data_out[7:0] <= mr_lp_adv_ability[7:0]; - data_out[15:8] <= mr_lp_adv_ability[15:8]; - end -endmodule - -module register_6_hb ( - rst_n, - clk, - mr_page_rx, - cs_0, - cs_1, - write, - ready, - - data_out -); - -input rst_n; -input clk; -input cs_0; -input cs_1; -input write; -input ready; -input mr_page_rx; -output [15:0] data_out; - -reg [15:0] data_out; -reg mr_page_rx_latched; -reg clear_on_read; -reg read_detect; -reg rd_d1; -reg rd_d2; - -// generate clear-on-read signal - always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - clear_on_read <= 0; - read_detect <= 0; - rd_d1 <= 0; - rd_d2 <= 0; - end - else begin - if (!write && ready && cs_0) - read_detect <= 1; - else - read_detect <= 0; - - rd_d1 <= read_detect; - rd_d2 <= rd_d1; - - // assert on falling edge of rd_d2 - clear_on_read <= !rd_d1 & rd_d2; - end - end - - -// Latch and Clear - always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - mr_page_rx_latched <= 0; - end - else begin - if (clear_on_read) - mr_page_rx_latched <= 0; - else if (mr_page_rx) - mr_page_rx_latched <= 1; - end - end - - -// Read Operations - - always @(*) begin - data_out[15:2] <= 14'd0; - data_out[1] <= mr_page_rx_latched; - data_out[0] <= 0; - end -endmodule - - -module regs_hb ( - rst_n, - hclk, - gbe_mode, - sgmii_mode, - hcs_n, - hwrite_n, - haddr, - hdatain, - - hdataout, - hready_n, - - mr_an_complete, - mr_page_rx, - mr_lp_adv_ability, - - mr_main_reset, - mr_an_enable, - mr_restart_an, - mr_adv_ability -); - -input rst_n; -input hclk; -input gbe_mode; -input sgmii_mode; -input hcs_n; -input hwrite_n; -input [3:0] haddr; -input [7:0] hdatain; - -output [7:0] hdataout; -output hready_n; - -input mr_an_complete; -input mr_page_rx; -input [15:0] mr_lp_adv_ability; - -output mr_main_reset; -output mr_an_enable; -output mr_restart_an; -output [15:0] mr_adv_ability; - -/////////////////////////////////// - - - -reg [7:0] hdataout; -reg hr; -reg hready_n; - -reg hcs_n_delayed; - -wire reg0_cs_0; -wire reg0_cs_1; - -wire reg1_cs_0; -wire reg1_cs_1; - -wire reg4_cs_0; -wire reg4_cs_1; - -wire reg5_cs_0; -wire reg5_cs_1; - -wire reg6_cs_0; -wire reg6_cs_1; - -wire [15:0] data_out_reg_0; -wire [15:0] data_out_reg_1; -wire [15:0] data_out_reg_4; -wire [15:0] data_out_reg_5; -wire [15:0] data_out_reg_6; - - - -register_addr_decoder ad_dec ( - .rst_n(rst_n), - .addr(haddr), - .cs_in(~hcs_n), - - .reg0_cs_0 (reg0_cs_0), - .reg0_cs_1 (reg0_cs_1), - .reg1_cs_0 (reg1_cs_0), - .reg1_cs_1 (reg1_cs_1), - .reg4_cs_0 (reg4_cs_0), - .reg4_cs_1 (reg4_cs_1), - .reg5_cs_0 (reg5_cs_0), - .reg5_cs_1 (reg5_cs_1), - .reg6_cs_0 (reg6_cs_0), - .reg6_cs_1 (reg6_cs_1) -); - - -register_0_hb register_0 ( - .rst_n (rst_n), - .clk (hclk), - .cs_0 (reg0_cs_0), - .cs_1 (reg0_cs_1), - .write (~hwrite_n), - .ready (1'b1), - .data_in ({hdatain, hdatain}), - - .data_out (data_out_reg_0), - .mr_main_reset (mr_main_reset), - .mr_an_enable (mr_an_enable), - .mr_restart_an (mr_restart_an) -); - - -register_1_hb register_1 ( - .rst_n (rst_n), - .cs_0 (reg1_cs_0), - .cs_1 (reg1_cs_1), - .mr_an_complete (mr_an_complete), - - .data_out (data_out_reg_1) -); - - -register_4_hb register_4 ( - .rst_n (rst_n), - .clk (hclk), - .gbe_mode (gbe_mode), - .sgmii_mode (sgmii_mode), - .cs_0 (reg4_cs_0), - .cs_1 (reg4_cs_1), - .write (~hwrite_n), - .ready (1'b1), - .data_in ({hdatain, hdatain}), - - .data_out (data_out_reg_4), - .mr_adv_ability (mr_adv_ability) -); - - -register_5_hb register_5 ( - .rst_n (rst_n), - .mr_lp_adv_ability (mr_lp_adv_ability), - .cs_0 (reg5_cs_0), - .cs_1 (reg5_cs_1), - .ready (1'b1), - - .data_out (data_out_reg_5) -); - - -register_6_hb register_6 ( - .rst_n (rst_n), - .clk (hclk), - .mr_page_rx (mr_page_rx), - .cs_0 (reg6_cs_0), - .cs_1 (reg6_cs_1), - .write (~hwrite_n), - .ready (1'b1), - - .data_out (data_out_reg_6) -); - - - -// generate an ack -always @(posedge hclk or negedge rst_n) begin - if (rst_n == 1'b0) begin - hcs_n_delayed <= 1'b1; - hr <= 1'b1; - hready_n <= 1'b1; - end - else begin - hcs_n_delayed <= hcs_n; - - //assert on falling edge of delayed chip select - hr <= ~hcs_n & hcs_n_delayed; - hready_n <= ~hr; - end -end - - - -// Mux Register Read-Data Outputs -always @(posedge hclk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - hdataout <= 8'd0; - end - else begin - case (haddr[3:0]) - - 4'd0: - begin - hdataout <= data_out_reg_0[7:0]; - end - - - 4'd1: - begin - hdataout <= data_out_reg_0[15:8]; - end - - ///////////////////////////////////////////// - - 4'd2: - begin - hdataout <= data_out_reg_1[7:0]; - end - - - 4'd3: - begin - hdataout <= data_out_reg_1[15:8]; - end - - ///////////////////////////////////////////// - - 4'd8: - begin - hdataout <= data_out_reg_4[7:0]; - end - - - 4'd9: - begin - hdataout <= data_out_reg_4[15:8]; - end - - ///////////////////////////////////////////// - - 4'd10: - begin - hdataout <= data_out_reg_5[7:0]; - end - - - 4'd11: - begin - hdataout <= data_out_reg_5[15:8]; - end - - ///////////////////////////////////////////// - - 4'd12: - begin - hdataout <= data_out_reg_6[7:0]; - end - - - 4'd13: - begin - hdataout <= data_out_reg_6[15:8]; - end - - ///////////////////////////////////////////// - - default: - begin - hdataout <= 8'd0; - end - endcase - end -end - -endmodule - -module register_addr_decoder ( - rst_n, - addr, - cs_in, - - reg0_cs_0, - reg0_cs_1, - - reg1_cs_0, - reg1_cs_1, - - reg4_cs_0, - reg4_cs_1, - - reg5_cs_0, - reg5_cs_1, - - reg6_cs_0, - reg6_cs_1 -); - -input rst_n; -input cs_in; -input [3:0] addr; - -output reg0_cs_0; -output reg0_cs_1; - -output reg1_cs_0; -output reg1_cs_1; - -output reg4_cs_0; -output reg4_cs_1; - -output reg5_cs_0; -output reg5_cs_1; - -output reg6_cs_0; -output reg6_cs_1; - -////////////////////////// - -wire reg0_cs_0; -wire reg0_cs_1; - -wire reg1_cs_0; -wire reg1_cs_1; - -wire reg4_cs_0; -wire reg4_cs_1; - -wire reg5_cs_0; -wire reg5_cs_1; - -wire reg6_cs_0; -wire reg6_cs_1; - -////////////////////////// - -assign reg0_cs_0 = (addr == 4'h0) ? cs_in : 1'b0; -assign reg0_cs_1 = (addr == 4'h1) ? cs_in : 1'b0; - -assign reg1_cs_0 = (addr == 4'h2) ? cs_in : 1'b0; -assign reg1_cs_1 = (addr == 4'h3) ? cs_in : 1'b0; - -assign reg4_cs_0 = (addr == 4'h8) ? cs_in : 1'b0; -assign reg4_cs_1 = (addr == 4'h9) ? cs_in : 1'b0; - -assign reg5_cs_0 = (addr == 4'ha) ? cs_in : 1'b0; -assign reg5_cs_1 = (addr == 4'hb) ? cs_in : 1'b0; - -assign reg6_cs_0 = (addr == 4'hc) ? cs_in : 1'b0; -assign reg6_cs_1 = (addr == 4'hd) ? cs_in : 1'b0; - - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v b/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v deleted file mode 100755 index fa0a645..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v +++ /dev/null @@ -1,219 +0,0 @@ -//************************************************************************** -// ************************************************************************* -// * LATTICE SEMICONDUCTOR CONFIDENTIAL * -// * PROPRIETARY NOTE * -// * * -// * This software contains information confidential and proprietary * -// * to Lattice Semiconductor Corporation. It shall not be reproduced * -// * in whole or in part, or transferred to other documents, or disclosed * -// * to third parties, or used for any purpose other than that for which * -// * it was obtained, without the prior written consent of Lattice * -// * Semiconductor Corporation. All rights reserved. * -// * * -// ************************************************************************* -//************************************************************************** - -//////////////////////////////////////////////////////////////////////// -// This module forces a RESET to the SERDES CDR -// when the CDR either loses lock or loses signal -//////////////////////////////////////////////////////////////////////// - -`timescale 1ns/100ps - -module reset_controller_cdr ( - - rst_n, - clk, - - cdr_lol, - - cdr_rst_out - ); - -input rst_n; -input clk; // 125Mhz clock - -input cdr_lol; - -output cdr_rst_out; - - -/////////////////////////////////////// - -reg cdr_rst_out; - -reg cdr_lol_mstb_1; -reg cdr_lol_mstb_2; - - -reg sht_mx; -reg [5:0] sht_count; - -reg lng_mx; -reg [22:0] lng_count; - -reg cnt_rst; -parameter - ASSRT_RST = 3'd0, - WAIT_SHORT = 3'd1, - DSSRT_RST = 3'd2, - WAIT_LONG = 3'd3, - SEEK_CDR_ERR = 3'd4, - SEEK_SIGNAL_RESTORE = 3'd5; -reg[2:0] fsm; - -////////////////////////////////////// -// Mestastability Filter -////////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - cdr_lol_mstb_1 <= 1'b1; - cdr_lol_mstb_2 <= 1'b1; - - - end - else begin - cdr_lol_mstb_1 <= cdr_lol; - cdr_lol_mstb_2 <= cdr_lol_mstb_1; - - end -end - - - -/////////////////////////////////////// -// Operate Short Timer (256 nsec) -/////////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - sht_mx <= 1'b0; - sht_count <= 6'd0; - end - else begin - - // define max count - if (sht_count[5] && (!cnt_rst)) begin - sht_mx <= 1'b1; - end - else begin - sht_mx <= 1'b0; - end - - // operate counter - if (cnt_rst) begin - sht_count <= 6'd0; //clear - end - else if (sht_mx) begin - sht_count <= sht_count; //hold - end - else begin - sht_count <= sht_count + 1; //count - end - end -end - - -///////////////////////////////////// -// Operate Long Timer (33 msec) -///////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - lng_mx <= 1'b0; - lng_count <= 23'd0; - end - else begin - - // define max count - if (lng_count[22] && (!cnt_rst)) begin - lng_mx <= 1'b1; - end - else begin - lng_mx <= 1'b0; - end - - // operate counter - if (cnt_rst) begin - lng_count <= 6'd0; //clear - end - else if (lng_mx) begin - lng_count <= lng_count; //hold - end - else begin - lng_count <= lng_count + 1; //count - end - end -end - - -///////////////////////////////////// -// State Machine -///////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - cdr_rst_out <= 1'b1; - cnt_rst <= 1'b1; - fsm <= ASSRT_RST; - end - else begin - - // defaults - cnt_rst <= 1'b0; - - case (fsm) - ASSRT_RST: begin - cdr_rst_out <= 1'b1; // assert - cnt_rst <= 1'b1; - fsm <= WAIT_SHORT; - end - - WAIT_SHORT: begin - // wait for 256 nsec - if (sht_mx && (!cnt_rst)) begin - fsm <= DSSRT_RST; - end - end - - DSSRT_RST: begin - cdr_rst_out <= 1'b0; // de-assert - fsm <= WAIT_LONG; - end - - WAIT_LONG: begin - // wait for 33 msec - if (lng_mx && (!cnt_rst)) begin - fsm <= SEEK_CDR_ERR; - end - end - - SEEK_CDR_ERR: begin - - cnt_rst <= 1'b1; - - - // Wait for CDR to fail - if (cdr_lol_mstb_2) begin - fsm <= ASSRT_RST; - end - else begin - fsm <= SEEK_CDR_ERR; - end - end - - - - default: begin - fsm <= ASSRT_RST; - end - endcase - - end -end - - - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v b/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v deleted file mode 100755 index 9d2e584..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v +++ /dev/null @@ -1,226 +0,0 @@ -//************************************************************************** -// ************************************************************************* -// * LATTICE SEMICONDUCTOR CONFIDENTIAL * -// * PROPRIETARY NOTE * -// * * -// * This software contains information confidential and proprietary * -// * to Lattice Semiconductor Corporation. It shall not be reproduced * -// * in whole or in part, or transferred to other documents, or disclosed * -// * to third parties, or used for any purpose other than that for which * -// * it was obtained, without the prior written consent of Lattice * -// * Semiconductor Corporation. All rights reserved. * -// * * -// ************************************************************************* -//************************************************************************** - -//////////////////////////////////////////////////////////////////////// -// This module implements the SERDES/PCS reset sequence as specified -// in Figure 47 of Lattice Technical Note TN1176 -//////////////////////////////////////////////////////////////////////// - -`timescale 1ns/100ps - -module reset_controller_pcs ( - - rst_n, - clk, - - tx_plol, - rx_cdr_lol, - - quad_rst_out, - tx_pcs_rst_out, - rx_pcs_rst_out - ); - -input rst_n; -input clk; // 125Mhz clock - -input tx_plol; -input rx_cdr_lol; - -output quad_rst_out; -output tx_pcs_rst_out; -output rx_pcs_rst_out; - - -/////////////////////////////////////// - -reg quad_rst_out; -reg tx_pcs_rst_out; -reg rx_pcs_rst_out; - -reg q_mx; -reg [3:0] q_count; - -reg rx_cdr_lol_mstb_1; -reg rx_cdr_lol_mstb_2; - -reg wd_mx; -reg wd_mx_d1; -reg wd_mx_re; -reg [22:0] wd_count; -reg watchdog_flag; - -//////////////////////////////////////////////////////// -// Assert Quad RST For 8 Clocks After Device Hard Reset -//////////////////////////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - q_mx <= 1'b0; - q_count <= 4'd0; - quad_rst_out <= 1'b1; // assert - end - else begin - - // define max count - if (q_count[3]) begin - q_mx <= 1'b1; - end - else begin - q_mx <= 1'b0; - end - - // operate counter - if (q_mx) begin - q_count <= q_count; //hold - end - else begin - q_count <= q_count + 1; //count - end - - // operate quad reset - if (q_mx) begin - quad_rst_out <= 1'b0; //de-assert on max-count - end - else begin - quad_rst_out <= 1'b1; //assert otherwise - end - end -end - - -//////////////////////////////////////////////////////////////////// -// Watchdog Timer -- In Case PLLs Don't Acquire Lock Within 33msec -//////////////////////////////////////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - wd_mx <= 1'b0; - wd_mx_d1 <= 1'b0; - wd_mx_re <= 1'b0; - wd_count <= 23'd0; - watchdog_flag <= 1'b0; - end - else begin - - // define max count - if (wd_count[22]) begin - wd_mx <= 1'b1; - end - else begin - wd_mx <= 1'b0; - end - - // operate counter - if (quad_rst_out) begin - wd_count <= 23'd0; //clear - end - else if (wd_mx) begin - wd_count <= wd_count; //hold - end - else begin - wd_count <= wd_count + 1; //count - end - - // detect rising edge of max_count flag - wd_mx_d1 <= wd_mx; - - wd_mx_re <= wd_mx & (!wd_mx_d1); - - // generate watchdog flag - watchdog_flag <= wd_mx_re; - end -end - - - - -//////////////////////////////////////////////// -// De-Assert TX PCS After TX PLL Acquires Lock -//////////////////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - tx_pcs_rst_out <= 1'b1; // assert - end - else begin - - case (tx_pcs_rst_out) - 1'b1: begin - // if asserted, wait for PLL to acquire lock - if ((!quad_rst_out && (!tx_plol)) || watchdog_flag) begin - tx_pcs_rst_out <= 1'b0; // deassert - end - end - - 1'b0: begin - // if de-asserted, stay that way - tx_pcs_rst_out <= 1'b0; // deassert - end - - default: begin - tx_pcs_rst_out <= 1'b1; // assert - end - endcase - - end -end - - - - - -/////////////////////////////////////////////////////// -// De-Assert RX PCS-Chan-0 After RX CDR Acquires Lock -/////////////////////////////////////////////////////// -always @(posedge clk or negedge rst_n) -begin - if (rst_n == 1'b0) begin - rx_pcs_rst_out <= 1'b1; // assert - rx_cdr_lol_mstb_1 <= 1'b1; - rx_cdr_lol_mstb_2 <= 1'b1; - end - else begin - - // metastability - filter - rx_cdr_lol_mstb_1 <= rx_cdr_lol; - rx_cdr_lol_mstb_2 <= rx_cdr_lol_mstb_1; - - case (rx_pcs_rst_out) - 1'b1: begin - // if asserted, wait for CDR to acquire lock - if ((!quad_rst_out && (!rx_cdr_lol_mstb_2)) || watchdog_flag) begin - rx_pcs_rst_out <= 1'b0; // deassert - end - end - - 1'b0: begin - // if de-asserted, stay that way - rx_pcs_rst_out <= 1'b0; // deassert - end - - default: begin - rx_pcs_rst_out <= 1'b1; // assert - end - endcase - - end -end - - - - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v b/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v deleted file mode 100644 index a97ca4f..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v +++ /dev/null @@ -1,237 +0,0 @@ -//************************************************************************** -// ************************************************************************* -// * LATTICE SEMICONDUCTOR CONFIDENTIAL * -// * PROPRIETARY NOTE * -// * * -// * This software contains information confidential and proprietary * -// * to Lattice Semiconductor Corporation. It shall not be reproduced * -// * in whole or in part, or transferred to other documents, or disclosed * -// * to third parties, or used for any purpose other than that for which * -// * it was obtained, without the prior written consent of Lattice * -// * Semiconductor Corporation. All rights reserved. * -// * * -// ************************************************************************* -//************************************************************************** - -`timescale 1ns/100ps - -module sgmii_channel_smi ( - - // Control Interface - rst_n, - gbe_mode, - sgmii_mode, - signal_detect, - debug_link_timer_short, - rx_compensation_err, - non_an_rate, - - // G/MII Interface - in_clk_gmii, - in_clk_mii, - data_in_mii, - en_in_mii, - err_in_mii, - - out_clk_gmii, - out_clk_mii, - data_out_mii, - dv_out_mii, - err_out_mii, - col_out_mii, - crs_out_mii, - - // 8-bit Interface - data_out_8bi, - kcntl_out_8bi, - disparity_cntl_out_8bi, - - serdes_recovered_clk, - data_in_8bi, - kcntl_in_8bi, - even_in_8bi, - disp_err_in_8bi, - cv_err_in_8bi, - err_decode_mode_8bi, - - // MDIO Port - mdc, - mdio, - port_id - ); - - - -// I/O Declarations -input rst_n ; // System Reset, Active Low -input signal_detect ; -input gbe_mode ; // GBE Mode (0=SGMII 1=GBE) -input sgmii_mode ; // SGMII PCS Mode (0=MAC 1=PHY) -input debug_link_timer_short ; // (0=NORMAL 1=SHORT) -output rx_compensation_err; // Active high pulse indicating RX_CTC_FIFO either underflowed or overflowed -input [1:0] non_an_rate ; // MII Rate Used When Autonegotiation is Disabled (00=10Mbps; 01=100Mbps; 10=1Gbps) - -input in_clk_mii ; // G/MII Transmit clock 2.5Mhz/25Mhz/125Mhz -input [7:0] data_in_mii ; // G/MII Tx data -input en_in_mii ; // G/MII data valid -input err_in_mii ; // G/MII Tx error - -input out_clk_mii ; // G/MII Receice clock 2.5Mhz/25Mhz/125MHz -output [7:0] data_out_mii ; // G/MII Rx data -output dv_out_mii ; // G/MII Rx data valid -output err_out_mii ; // G/MII Rx error -output col_out_mii ; // G/MII collision detect -output crs_out_mii ; // G/MII carrier sense detect - -output [7:0] data_out_8bi ; // 8BI Tx Data -output kcntl_out_8bi ; // 8BI Tx Kcntl -output disparity_cntl_out_8bi ; // 8BI Tx Kcntl - -input serdes_recovered_clk ; -input [7:0] data_in_8bi ; // 8BI Rx Data -input kcntl_in_8bi ; // 8BI Rx Kcntl -input even_in_8bi ; // 8BI Rx Even -input disp_err_in_8bi ; // 8BI Rx Disparity Error -input cv_err_in_8bi ; // 8BI Rx Coding Violation Error -input err_decode_mode_8bi ; // 8BI Error Decode Mode (0=NORMAL, 1=DECODE_MODE) - -input in_clk_gmii ; // GMII Transmit clock 125Mhz -input out_clk_gmii ; // GMII Receive clock 125Mhz - -input mdc; -inout mdio; -input [4:0] port_id; - - -wire mdin; -wire mdout; -wire mdout_en; - -// Internal Signals - -wire mr_an_complete; -wire mr_page_rx; -wire [15:0] mr_lp_adv_ability; - -wire mr_main_reset; -wire mr_an_enable; -wire mr_restart_an; -wire [15:0] mr_adv_ability; - -wire [1:0] operational_rate; - - - - - - - - -// SGMII PCS -sgmii33 sgmii33_U ( - // Clock and Reset - .rst_n (rst_n ), - .signal_detect (signal_detect), - .gbe_mode (gbe_mode), - .sgmii_mode (sgmii_mode), - .debug_link_timer_short (debug_link_timer_short), - .operational_rate (operational_rate), - .rx_compensation_err (rx_compensation_err), - .tx_clk_125 (in_clk_gmii), - .serdes_recovered_clk (serdes_recovered_clk), - .rx_clk_125 (out_clk_gmii), - - // Control - - - // (G)MII TX Port - .tx_clk_mii (in_clk_mii), - .tx_d (data_in_mii), - .tx_en (err_in_mii), - .tx_er (en_in_mii), - - // (G)MII RX Port - .rx_clk_mii (out_clk_mii), - .rx_d (data_out_mii), - .rx_dv (dv_out_mii), - .rx_er (err_out_mii), - .col (col_out_mii), - .crs (crs_out_mii), - - // 8BI TX Port - .tx_data (data_out_8bi), - .tx_kcntl (kcntl_out_8bi), - .tx_disparity_cntl (disparity_cntl_out_8bi), - - // 8BI RX Port - .rx_data (data_in_8bi), - .rx_kcntl (kcntl_in_8bi), - .rx_even (even_in_8bi), - .rx_disp_err (disp_err_in_8bi), - .rx_cv_err (cv_err_in_8bi), - .rx_err_decode_mode (err_decode_mode_8bi), - - // Management Interface I/O - .mr_adv_ability (mr_adv_ability), - .mr_an_enable (mr_an_enable), - .mr_main_reset (mr_main_reset), - .mr_restart_an (mr_restart_an), - - .mr_an_complete (mr_an_complete), - .mr_lp_adv_ability (mr_lp_adv_ability), - .mr_page_rx (mr_page_rx) - ); - - - -// SMI Register Interface for SGMII IP Core -register_interface_smi ri ( - - // Control Signals - .rst_n (rst_n), - .gbe_mode (gbe_mode), - .sgmii_mode (sgmii_mode), - - // MDIO Port - .mdc (mdc), - .mdin (mdin), - .mdout (mdout), - .mdout_en (mdout_en), - .port_id (port_id), - - // Register Outputs - .mr_an_enable (mr_an_enable), - .mr_restart_an (mr_restart_an), - .mr_main_reset (mr_main_reset), - .mr_adv_ability (mr_adv_ability), - - // Register Inputs - .mr_an_complete (mr_an_complete), - .mr_page_rx (mr_page_rx), - .mr_lp_adv_ability (mr_lp_adv_ability) - ); - - - -// (G)MII Rate Resolution for SGMII IP Core -rate_resolution rate_resolution ( - .gbe_mode (gbe_mode), - .sgmii_mode (sgmii_mode), - .an_enable (mr_an_enable), - .advertised_rate (mr_adv_ability[11:10]), - .link_partner_rate (mr_lp_adv_ability[11:10]), - .non_an_rate (non_an_rate), - - .operational_rate (operational_rate) -); - - - - - -// Bidirectional Assignments -assign mdio = mdout_en ? mdout : 1'bz; // MDIO Output -assign mdin = mdio; // MDIO Input - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/dummy.sty b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/dummy.sty deleted file mode 100644 index 8b13789..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/dummy.sty +++ /dev/null @@ -1 +0,0 @@ - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/generate_core.tcl b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/generate_core.tcl deleted file mode 100755 index 1561878..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/generate_core.tcl +++ /dev/null @@ -1,39 +0,0 @@ - -#!/usr/local/bin/wish - -set Para(cmd) "" -if ![catch {set temp $argc} result] { - if {$argc > 0} { - for {set i 0} {$i < $argc} {incr i 2} { - set temp [lindex $argv $i] - set temp [string range $temp 1 end] - lappend argv_list $temp - lappend value_list [lindex $argv [expr $i+1]] - } - foreach argument $argv_list value $value_list { - switch $argument { - "cmd" {set Para(cmd) $value;} - } - } - } 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sgmii_gbe_pcs32 - - verilog_file_list: "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../../../../../cae_library/synthesis/verilog/ecp2m.v" "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32_wrapper.v" "/home/greg/sgmii_gbepcs_v3.4/lib/../sgmii_pcs_eval/username/src/ertl/ertl.v" - - suffix_name: edi - output_file_name: sgmii_gbe_pcs32 - write_prf: false - vlog_std_v2001: true - disable_io_insertion: true - STYFILENAME: dummy.sty - -force_gsr: false diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc deleted file mode 100755 index c91da93..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc +++ /dev/null @@ -1,26 +0,0 @@ -[Device] -Family=ep5m00 -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=IPCFG -CoreStatus=Demo -CoreName=SGMII/Gb Ethernet PCS -CoreRevision=3.2 -ModuleName=sgmii_gbe_pcs32 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=06/17/2011 -Time=11:34:20 - -[Parameters] -RX_CTC=2 -RX_CTC_LOW=16 -RX_CTC_HIGH=32 -EasyConnect=1 diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32.ngo b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32.ngo deleted file mode 100755 index 4bfd6e06e5be71df4f7969a47cabece5ca352283..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 377069 zcmb@vd3;=Dy+59$r3}atL_0HCXOb?{Bu&mtGU*gWCtVZh61rf3FV3WC+C`UY5f`Ee1{IBaRK%cgjjRKxM7iD@Wea8dz2BeboHOUloRj9hUO)aQ z`Rt$1`|~`{*`9M|Vk$Ko$qCoy@V_OVHHWA1|J>gF2Rl0x`}edby4!kdBRQTmO_Sue zcSjFuT8=0B3m?fXn>I$aMzoDNp3~0v2%~A;j)ol)~qT}@jz?%dU|wHba9Z&5DgTXyZ-xQKojYY`nV%1hOM-H?-W%7q^9Q{C{e=#sXs zz5|JU`*J+q=f>%>C$Yb+uO|`B@%ZYR!N}|DPwY+fv|hC4EbZb@-KrcDqv$qgxNop!GwAFPx5WdFn#)$G7}Z0t)sPT ze|w_+NPAa~C$Ns;b0z$aZQJR!OtP6nPiwbj;FQJs>1ILn_@Jw@cS($$xMEb_Qk;W$4n_))%;cPJ-V;= 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zl=0TVEBAD$hIg~{b)L2I)UwA0g!{?J8xel3f!QX6_qy<4Gs0Wq)O!dot){jhJV8dT zLGUBVwj%s|lvU?W`$9*{AMyz0^K9 zTlG?(!P%yl`rO^3m-@opo|pO(&eptCy}K^;~5_~ zHM-mCQoq32QkOdHZl_B*&r|Qtp?-6>(WQQOx6q}Wd!cvADCb@%Sx-6lLaUOLb1$^E zlydHc)<-GlUT9-8<=hK>oS>Y0q50*Mb1!trg$K^P&<+{d*}}HEf!PUnOI+%tyB#id z%H0Z=I_++QOa1F^flHlnx4)&%x?A76YURAsKxf}pDejiH%$z%=!!A6nQr)d?sWf++ zTPoe%;+D#Ax3{HQx?9^)aJRLkTDe==Qs=na*;41aTiH^r-EC~C^V}_LDd&!AR1@Vq zfxWYVa-P6GSwvmvZdpq?Phjtrk)0>78%vluPhkI2NjXnoAFiXEC$N9hDd!37-%BXx z3G5@%&Upg+sI+V6Zb!?i^DOo;X{Wf`&@#K+-GY{Kp3nZfm~x)a{wG1@xZBQBSHRhF zmbwzocC(c8r1oji)$TU4%zW+^vy|W6UY63_tz{|Q-By+|+%07()7?&%x(3cxvQ)0S ojVxus*+Q1G-R)zkfV*`pl?P|rSSsjl8B2xS?P94goULO258(kII{*Lx diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32_bb.v b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32_bb.v deleted file mode 100755 index 8930efc..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32_bb.v +++ /dev/null @@ -1,127 +0,0 @@ -//============================================================================= -// Verilog module generated by IPExpress 12/10/2009 15:57:55 -// Filename: sgmii_gbe_pcs32_bb.v -// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved. -//============================================================================= - -//--------------------------------------------------------------- -// sgmii_gbe_pcs32 synthesis black box definition -//--------------------------------------------------------------- - -/* WARNING - Changes to this file should be performed by re-running IPexpress -or modifying the .LPC file and regenerating the core. Other changes may lead -to inconsistent simulation and/or implemenation results */ - - - - - - -module sgmii_gbe_pcs32 ( - // Control Interface - rst_n, - signal_detect, - gbe_mode, - sgmii_mode, - operational_rate, - debug_link_timer_short, - rx_compensation_err, - - // G/MII Interface - tx_clock_enable_sink , - tx_clock_enable_source , - tx_clk_125, - tx_d, - tx_en, - tx_er, - - rx_clock_enable_sink , - rx_clock_enable_source , - rx_clk_125, - rx_d, - rx_dv, - rx_er, - col, - crs, - - // 8-bit Interface - tx_data, - tx_kcntl, - tx_disparity_cntl, - - serdes_recovered_clk, - rx_data, - rx_kcntl, - rx_even , - rx_disp_err , - rx_cv_err , - rx_err_decode_mode , - - // Managment Control Outputs - mr_an_complete, - mr_page_rx, - mr_lp_adv_ability, - - // Managment Control Inputs - mr_main_reset, - mr_an_enable, - mr_restart_an, - mr_adv_ability - ); - - - -// Control Interface -input rst_n ; -input signal_detect ; -input gbe_mode ; -input sgmii_mode ; -input [1:0] operational_rate ; -input debug_link_timer_short ; -output rx_compensation_err ; - -// G/MII Interface -input tx_clock_enable_sink; -output tx_clock_enable_source; -input tx_clk_125 ; -input [7:0] tx_d ; -input tx_en ; -input tx_er ; - -input rx_clock_enable_sink; -output rx_clock_enable_source; -input rx_clk_125 ; -output [7:0] rx_d ; -output rx_dv ; -output rx_er ; -output col ; -output crs ; - -// 8-bit Interface -output [7:0] tx_data ; -output tx_kcntl; -output tx_disparity_cntl; - -input serdes_recovered_clk ; -input [7:0] rx_data ; -input rx_even ; -input rx_kcntl; -input rx_disp_err ; -input rx_cv_err ; -input rx_err_decode_mode ; - -// Managment Control Outputs -output mr_an_complete; -output mr_page_rx; -output [15:0] mr_lp_adv_ability; - -// Managment Control Inputs -input mr_main_reset; -input mr_an_enable; -input mr_restart_an; -input [15:0] mr_adv_ability; - - - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32_beh.v b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32_beh.v deleted file mode 100755 index aa3390e..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/sgmii_gbe_pcs32_beh.v +++ /dev/null @@ -1,5165 +0,0 @@ -// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1 -// created on Wed Mar 11 09:41:50 CST 2009 -// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved -// obfuscator_exe version 1.mar0807 - -// top - - -`define SGMII_NO_ENC - -`define SGMII_YES_CTC_DYNAMIC - -`define SGMII_FIFO_FAMILY_ECP2M - -`define SGMII_YES_SINGLE_CLOCK - - - - -`timescale 1 ns / 100 ps -module xwfb762 (icdbb13, fndd899, dzec4ce, ww62677, nt133b8, je99dc6, - gocee32, ay77190, dob8c81, gbc640b, db3205d, cb902ef, fp8177d, - pubbee); -input [17:0] icdbb13; -input fndd899; -input dzec4ce; -input ww62677; -input nt133b8; -input je99dc6; -input gocee32; -input [9:0] ay77190; -input [9:0] dob8c81; -output [17:0] gbc640b; -output db3205d; -output cb902ef; -output fp8177d; -output pubbee; -reg [17 : 0] hqbd2d7; -reg jpe96ba; -reg uv4b5d7; -reg pf5aebd; -reg jpd75ef; -reg fpbaf7e; -reg thd7bf6; -reg [9 : 0] jebdfb7; -reg [9 : 0] ayefdbb; -reg [2047:0] bl7edd9; -wire [8:0] nrf6ece; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -localparam zmb7676 = 9,wlbb3b3 = 32'hfdfff40b; -localparam [31:0] czd9d9d = wlbb3b3; -localparam vi76760 = wlbb3b3 & 4'hf; -localparam [11:0] gq9d818 = 'h7ff; -wire [(1 << vi76760) -1:0] kd60607; -reg [zmb7676-1:0] yz181ef; -reg [vi76760-1:0] oh7beb [0:1]; -reg [vi76760-1:0] qgefae7; -reg ww7d739; -integer xweb9c8; -integer ay5ce43; - -AND2 ofe7218 (.A(ww62677), .B(fnc8624), .Z(su43126)); INV ux18931 (.A(qgc498c), .Z(fnc8624)); AND2 ir26308 (.A(nt133b8), .B(tw8c221), .Z(dz6110a)); INV ux8857 (.A(of442bd), .Z(tw8c221)); OR2 gqaf61 (.A(je99dc6), .B(gocee32), .Z(vvec21b)); XOR2 nr610df (.A(wl86ff), .B(yk437fc), .Z(pu1bfe1)); XOR2 hodff0b (.A(yk437fc), .B(jpfc2d8), .Z(xwe16c6)); XOR2 xyb633 (.A(jpfc2d8), .B(hbd8cdc), .Z(shc66e6)); XOR2 ux33735 (.A(hbd8cdc), .B(mrdcd6f), .Z(hbe6b7c)); XOR2 zm35be7 (.A(mrdcd6f), .B(ip6f9da), .Z(lq7ced5)); XOR2 she76ab (.A(ip6f9da), .B(nedaae1), .Z(rgd570b)); XOR2 uxab85b (.A(nedaae1), .B(hoe16e9), .Z(zmb74b)); XOR2 cz5ba5b (.A(hoe16e9), .B(nre96ef), .Z(al4b77f)); XOR2 kd5bbfd (.A(nre96ef), .B(ykeff6e), .Z(kd7fb71)); XOR2 gbfdb8c (.A(ykeff6e), .B(dz6e32c), .Z(vv71966)); XOR2 pu8cb37 (.A(al659bb), .B(sj2cddc), .Z(jc66ee4)); XOR2 rv37723 (.A(sj2cddc), .B(gbdc8fc), .Z(jce47e4)); XOR2 qv23f23 (.A(gbdc8fc), .B(hbfc8e9), .Z(lqe474f)); XOR2 gd23a7b (.A(hbfc8e9), .B(hbe9eed), .Z(bl4f76e)); XOR2 th7bb77 (.A(hbe9eed), .B(wjeddf6), .Z(rt6efb4)); XOR2 ea77da7 (.A(wjeddf6), .B(blf69c4), .Z(irb4e26)); XOR2 pua7135 (.A(blf69c4), .B(ayc4d57), .Z(gd26ab9)); XOR2 ri355cd (.A(ayc4d57), .B(dm57357), .Z(gqb9aba)); XOR2 fncd5d1 (.A(dm57357), .B(dm57475), .Z(jrba3aa)); XOR2 ayd1d57 (.A(dm57475), .B(qt755c6), .Z(zzaae34)); defparam rg571a7.initval = 16'h6996 ; ROM16X1 rg571a7 (.AD3(yxc69d3), .AD2(ks34e9c), .AD1(fca74e1), .AD0(fc3a70a), .DO0(wjd3853)) ; defparam hq9c29d.initval = 16'h6996 ; ROM16X1 hq9c29d (.AD3(gqa75b), .AD2(ea53ad9), .AD1(sw9d6c9), .AD0(faeb649), .DO0(kd5b24a)) ; defparam qtd9254.initval = 16'h6996 ; ROM16X1 qtd9254 (.AD3(fca74e1), .AD2(fc3a70a), .AD1(ip54b06), .AD0(ip54b06), .DO0(ux2c1a6)) ; defparam en60d35.initval = 16'h6996 ; ROM16X1 en60d35 (.AD3(ks34e9c), .AD2(fca74e1), .AD1(fc3a70a), .AD0(ip54b06), .DO0(fa66258)) ; defparam ec312c2.initval = 16'h6996 ; ROM16X1 ec312c2 (.AD3(faeb649), .AD2(yxc69d3), .AD1(ks34e9c), .AD0(ux2c1a6), .DO0(mg82af9)) ; defparam sw157c8.initval = 16'h6996 ; ROM16X1 sw157c8 (.AD3(sw9d6c9), .AD2(faeb649), .AD1(yxc69d3), .AD0(fa66258), .DO0(yzddb5)) ; defparam vv6edad.initval = 16'h6996 ; ROM16X1 vv6edad (.AD3(ea53ad9), .AD2(sw9d6c9), .AD1(faeb649), .AD0(wjd3853), .DO0(al7a1d4)) ; defparam hod0ea5.initval = 16'h6996 ; ROM16X1 hod0ea5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(ip54b06), .AD0(ip54b06), .DO0(en5143a)) ; defparam ux8a1d5.initval = 16'h6996 ; ROM16X1 ux8a1d5 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(tud5b8a), .AD0(ip54b06), .DO0(ld6e292)) ; defparam hb71496.initval = 16'h6996 ; ROM16X1 hb71496 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xy96d51), .AD0(tud5b8a), .DO0(jrb5458)) ; defparam vxaa2c6.initval = 16'h6996 ; ROM16X1 vxaa2c6 (.AD3(bn8b1b5), .AD2(xy96d51), .AD1(tud5b8a), .AD0(ip54b06), .DO0(xlb5ea4)) ; defparam hdaf527.initval = 16'h6996 ; ROM16X1 hdaf527 (.AD3(wjd3853), .AD2(kd5b24a), .AD1(xlb5ea4), .AD0(ip54b06), .DO0(byf4138)) ; defparam jra09c2.initval = 16'h6996 ; ROM16X1 jra09c2 (.AD3(rv270b3), .AD2(zz3859e), .AD1(xjc2cf6), .AD0(fp167b6), .DO0(wyb3db6)) ; defparam vx9edb0.initval = 16'h6996 ; ROM16X1 vx9edb0 (.AD3(mgb6c3e), .AD2(qib61f0), .AD1(dbb0f81), .AD0(aa87c0f), .DO0(aa3e078)) ; defparam gof03c1.initval = 16'h6996 ; ROM16X1 gof03c1 (.AD3(xjc2cf6), .AD2(fp167b6), .AD1(ip54b06), .AD0(ip54b06), .DO0(rg47205)) ; defparam mt3902b.initval = 16'h6996 ; ROM16X1 mt3902b (.AD3(zz3859e), .AD2(xjc2cf6), .AD1(fp167b6), .AD0(ip54b06), .DO0(pfe6e08)) ; defparam nt37047.initval = 16'h6996 ; ROM16X1 nt37047 (.AD3(aa87c0f), .AD2(rv270b3), .AD1(zz3859e), .AD0(rg47205), .DO0(cmfa153)) ; defparam xwd0a99.initval = 16'h6996 ; ROM16X1 xwd0a99 (.AD3(dbb0f81), .AD2(aa87c0f), .AD1(rv270b3), .AD0(pfe6e08), .DO0(sh5441a)) ; defparam baa20d5.initval = 16'h6996 ; ROM16X1 baa20d5 (.AD3(qib61f0), .AD2(dbb0f81), .AD1(aa87c0f), .AD0(wyb3db6), .DO0(mr5165e)) ; defparam hd8b2f5.initval = 16'h6996 ; ROM16X1 hd8b2f5 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ip54b06), .AD0(ip54b06), .DO0(fa7914e)) ; defparam thc8a72.initval = 16'h6996 ; ROM16X1 thc8a72 (.AD3(wyb3db6), .AD2(aa3e078), .AD1(ww72fa5), .AD0(ip54b06), .DO0(cbbe941)) ; defparam tuf4a0c.initval = 16'h6996 ; ROM16X1 tuf4a0c (.AD3(wyb3db6), .AD2(aa3e078), .AD1(phc7fd), .AD0(ww72fa5), .DO0(gq1ff73)) ; defparam meffb99.initval = 16'h6996 ; ROM16X1 meffb99 (.AD3(byee645), .AD2(phc7fd), .AD1(ww72fa5), .AD0(ip54b06), .DO0(th454df)) ; defparam xy2a6fe.initval = 16'h6996 ; ROM16X1 xy2a6fe (.AD3(wyb3db6), .AD2(aa3e078), .AD1(th454df), .AD0(ip54b06), .DO0(yz90edd)) ; XOR2 sw876ec (.A(dz6e32c), .B(fp167b6), .Z(xjdd849)); XOR2 rtec24e (.A(fc3a70a), .B(qt755c6), .Z(me49dfe)); defparam cz4eff1.initval = 16'h0410 ; ROM16X1 cz4eff1 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(en60cda)) ; defparam zz66d4.initval = 16'h1004 ; ROM16X1 zz66d4 (.AD3(fpbfc60), .AD2(qt755c6), .AD1(fc3a70a), .AD0(ip54b06), .DO0(db3dcc3)) ; defparam faee61f.initval = 16'h0140 ; ROM16X1 faee61f (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ipd3301)) ; defparam vk9980c.initval = 16'h4001 ; ROM16X1 vk9980c (.AD3(wy987d3), .AD2(dz6e32c), .AD1(fp167b6), .AD0(ip54b06), .DO0(ba14af1)) ; INV tja578a (.A(qi2bc57), .Z(yx5e2b9)); AND2 xwf15cc (.A(cb8ae62), .B(yx5e2b9), .Z(ukb98a2)); AND2 mrcc511 (.A(cb8ae62), .B(qi2bc57), .Z(doa230b)); defparam pu1185a.CSDECODE_R = 3'b000 ; defparam pu1185a.CSDECODE_W = 3'b000 ; defparam pu1185a.GSR = "ENABLED" ; defparam pu1185a.RESETMODE = "ASYNC" ; defparam pu1185a.REGMODE = "NOREG" ; defparam pu1185a.DATA_WIDTH_R = 18 ; defparam pu1185a.DATA_WIDTH_W = 18 ; PDP16KA pu1185a (.DI0(icdbb13[0]), .DI1(icdbb13[1]), .DI2(icdbb13[2]), .DI3(icdbb13[3]), .DI4(icdbb13[4]), .DI5(icdbb13[5]), .DI6(icdbb13[6]), .DI7(icdbb13[7]), .DI8(icdbb13[8]), .DI9(icdbb13[9]), .DI10(icdbb13[10]), .DI11(icdbb13[11]), .DI12(icdbb13[12]), .DI13(icdbb13[13]), .DI14(icdbb13[14]), .DI15(icdbb13[15]), .DI16(icdbb13[16]), .DI17(icdbb13[17]), .DI18(icdbb13[0]), .DI19(icdbb13[1]), .DI20(icdbb13[2]), .DI21(icdbb13[3]), .DI22(icdbb13[4]), .DI23(icdbb13[5]), .DI24(icdbb13[6]), .DI25(icdbb13[7]), .DI26(icdbb13[8]), .DI27(icdbb13[9]), .DI28(icdbb13[10]), .DI29(icdbb13[11]), .DI30(icdbb13[12]), .DI31(icdbb13[13]), .DI32(icdbb13[14]), .DI33(icdbb13[15]), .DI34(icdbb13[16]), .DI35(icdbb13[17]), .ADW0(vve93e5), .ADW1(vve93e5), .ADW2(ip54b06), .ADW3(ip54b06), .ADW4(uie5e73), .ADW5(vk2f398), .ADW6(ho79cc2), .ADW7(kqce613), .ADW8(lq73099), .ADW9(mg984cb), .ADW10(ldc2659), .ADW11(rv132cf), .ADW12(pu9967e), .ADW13(gocb3f3), .CEW(su43126), .CLKW(fndd899), .WE(vve93e5), .CSW0(ip54b06), .CSW1(ip54b06), .CSW2(ip54b06), .ADR0(ip54b06), .ADR1(ip54b06), .ADR2(ip54b06), .ADR3(ip54b06), .ADR4(icde57a), .ADR5(alf2bd0), .ADR6(an95e84), .ADR7(lfaf424), .ADR8(gb7a126), .ADR9(dmd0935), .ADR10(jr849aa), .ADR11(ym24d57), .ADR12(cb26ab8), .ADR13(ls355c5), .CER(dz6110a), .CLKR(dzec4ce), .CSR0(ip54b06), .CSR1(ip54b06), .CSR2(ip54b06), .RST(je99dc6), .DO0(gbc640b[0]), .DO1(gbc640b[1]), .DO2(gbc640b[2]), .DO3(gbc640b[3]), .DO4(gbc640b[4]), .DO5(gbc640b[5]), . -DO6(gbc640b[6]), .DO7(gbc640b[7]), .DO8(gbc640b[8]), .DO9(gbc640b[9]), .DO10(gbc640b[10]), .DO11(gbc640b[11]), .DO12(gbc640b[12]), .DO13(gbc640b[13]), .DO14(gbc640b[14]), .DO15(gbc640b[15]), .DO16(gbc640b[16]), .DO17(gbc640b[17]), .DO18(), .DO19(), .DO20(), .DO21(), .DO22(), .DO23(), .DO24(), .DO25(), .DO26(), .DO27(), .DO28(), .DO29(), .DO30(), .DO31(), .DO32(), .DO33(), .DO34(), .DO35()) ; defparam mt9f303.GSR = "ENABLED" ; FD1P3BX mt9f303 (.D(mrcc0e7), .SP(su43126), .CK(fndd899), .PD(je99dc6), .Q(wl86ff)) ; defparam kf3cbb5.GSR = "ENABLED" ; FD1P3DX kf3cbb5 (.D(co2ed68), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(yk437fc)) ; defparam of415d9.GSR = "ENABLED" ; FD1P3DX of415d9 (.D(rg57660), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jpfc2d8)) ; defparam ir2b25.GSR = "ENABLED" ; FD1P3DX ir2b25 (.D(aaac960), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbd8cdc)) ; defparam gqcad.GSR = "ENABLED" ; FD1P3DX gqcad (.D(fp32b4f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mrdcd6f)) ; defparam rt7e8d6.GSR = "ENABLED" ; FD1P3DX rt7e8d6 (.D(swa35b2), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ip6f9da)) ; defparam gd9034b.GSR = "ENABLED" ; FD1P3DX gd9034b (.D(qvd2ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nedaae1)) ; defparam ps7c711.GSR = "ENABLED" ; FD1P3DX ps7c711 (.D(jr1c457), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hoe16e9)) ; defparam vxbf8e3.GSR = "ENABLED" ; FD1P3DX vxbf8e3 (.D(lde38f6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(nre96ef)) ; defparam lsb7fde.GSR = "ENABLED" ; FD1P3DX lsb7fde (.D(meff796), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ykeff6e)) ; defparam kfb1422.GSR = "ENABLED" ; FD1P3DX kfb1422 (.D(bl508a5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(dz6e32c)) ; defparam aa2edd6.GSR = "ENABLED" ; FD1P3DX aa2edd6 (.D(pu1bfe1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(oh8a7a4)) ; defparam qg53d25.GSR = "ENABLED" ; FD1P3DX qg53d25 (.D(xwe16c6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ld4f71c)) ; defparam vv7b8e7.GSR = "ENABLED" ; FD1P3DX vv7b8e7 (.D(shc66e6), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uif5fa8)) ; defparam jrafd41.GSR = "ENABLED" ; FD1P3DX jrafd41 (.D(hbe6b7c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(jp7e0e8)) ; defparam ayf0747.GSR = "ENABLED" ; FD1P3DX ayf0747 (.D(lq7ced5), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(hbc2b1e)) ; defparam ec158f6.GSR = "ENABLED" ; FD1P3DX ec158f6 (.D(rgd570b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv816fe)) ; defparam hqb7f6.GSR = "ENABLED" ; FD1P3DX hqb7f6 (.D(zmb74b), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(co9d6b8)) ; defparam hoeb5c1.GSR = "ENABLED" ; FD1P3DX hoeb5c1 (.D(al4b77f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(xw57c80)) ; defparam qvbe403.GSR = "ENABLED" ; FD1P3DX qvbe403 (.D(kd7fb71), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gbedb34)) ; defparam qg6d9a4.GSR = "ENABLED" ; FD1P3DX qg6d9a4 (.D(vv71966), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ep266b)) ; defparam nt1335d.GSR = "ENABLED" ; FD1P3DX nt1335d (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ay72dd2)) ; defparam zm96e90.GSR = "ENABLED" ; FD1P3DX zm96e90 (.D(wl86ff), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(uie5e73)) ; defparam vidfd5b.GSR = "ENABLED" ; FD1P3DX vidfd5b (.D(yk437fc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(vk2f398)) ; defparam hod0902.GSR = "ENABLED" ; FD1P3DX hod0902 (.D(jpfc2d8), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ho79cc2)) ; defparam mgb9768.GSR = "ENABLED" ; FD1P3DX mgb9768 (.D(hbd8cdc), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(kqce613)) ; defparam mt2a70.GSR = "ENABLED" ; FD1P3DX mt2a70 (.D(mrdcd6f), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(lq73099)) ; defparam yz8b71.GSR = "ENABLED" ; FD1P3DX yz8b71 (.D(ip6f9da), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(mg984cb)) ; defparam fn7edcd.GSR = "ENABLED" ; FD1P3DX fn7edcd (.D(nedaae1), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(ldc2659)) ; defparam qib33fb.GSR = "ENABLED" ; FD1P3DX qib33fb (.D(hoe16e9), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(rv132cf)) ; defparam vi52aeb.GSR = "ENABLED" ; FD1P3DX vi52aeb (.D(nre96ef), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(pu9967e)) ; defparam czed6ae.GSR = "ENABLED" ; FD1P3DX czed6ae (.D(ykeff6e), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(gocb3f3)) ; defparam ea7756d.GSR = "ENABLED" ; FD1P3DX ea7756d (.D(dz6e32c), .SP(su43126), .CK(fndd899), .CD(je99dc6), .Q(wy987d3)) ; defparam ic72455.GSR = "ENABLED" ; FD1P3BX ic72455 (.D(tj91548), .SP(dz6110a), .CK(dzec4ce), .PD(vvec21b), .Q(al659bb)) ; defparam vi479cb.GSR = "ENABLED" ; FD1P3DX vi479cb (.D(qte72d5), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj2cddc)) ; defparam qiac87a.GSR = "ENABLED" ; FD1P3DX qiac87a (.D(gq21e87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gbdc8fc)) ; defparam jr38351.GSR = "ENABLED" ; FD1P3DX jr38351 (.D(and471), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbfc8e9)) ; defparam ba8c93f.GSR = "ENABLED" ; FD1P3DX ba8c93f (.D(mg24fde), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(hbe9eed)) ; defparam uif0ed0.GSR = "ENABLED" ; FD1P3DX uif0ed0 (.D(aa3b409), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(wjeddf6)) ; defparam ui494f6.GSR = "ENABLED" ; FD1P3DX ui494f6 (.D(su53d87), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(blf69c4)) ; defparam yz39ff9.GSR = "ENABLED" ; FD1P3DX yz39ff9 (.D(mr7fe6a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ayc4d57)) ; defparam al543f5.GSR = "ENABLED" ; FD1P3DX al543f5 (.D(ymfd6c), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57357)) ; defparam kd60c53.GSR = "ENABLED" ; FD1P3DX kd60c53 (.D(qi314e7), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dm57475)) ; defparam nt38a54.GSR = "ENABLED" ; FD1P3DX nt38a54 (.D(gd2953a), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(qt755c6)) ; defparam byd5d12.GSR = "ENABLED" ; FD1P3DX byd5d12 (.D(jc66ee4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(sj95ca1)) ; defparam yzae50c.GSR = "ENABLED" ; FD1P3DX yzae50c (.D(jce47e4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls20f3f)) ; defparam cb79fa.GSR = "ENABLED" ; FD1P3DX cb79fa (.D(lqe474f), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpa5ac0)) ; defparam hd2d606.GSR = "ENABLED" ; FD1P3DX hd2d606 (.D(bl4f76e), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(uxbe6f6)) ; defparam nrf37b5.GSR = "ENABLED" ; FD1P3DX nrf37b5 (.D(rt6efb4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ip7f3bf)) ; defparam vvf9dfd.GSR = "ENABLED" ; FD1P3DX vvf9dfd (.D(irb4e26), -.SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ww781a8)) ; defparam xwc0d40.GSR = "ENABLED" ; FD1P3DX xwc0d40 (.D(gd26ab9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ba1e4f6)) ; defparam wjf27b2.GSR = "ENABLED" ; FD1P3DX wjf27b2 (.D(gqb9aba), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gdabfd5)) ; defparam xj5fead.GSR = "ENABLED" ; FD1P3DX xj5fead (.D(jrba3aa), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ps79094)) ; defparam vvc84a2.GSR = "ENABLED" ; FD1P3DX vvc84a2 (.D(zzaae34), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqb3bde)) ; defparam uk9def0.GSR = "ENABLED" ; FD1P3DX uk9def0 (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gqc04)) ; defparam db6021.GSR = "ENABLED" ; FD1P3DX db6021 (.D(al659bb), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(icde57a)) ; defparam rgd540c.GSR = "ENABLED" ; FD1P3DX rgd540c (.D(sj2cddc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(alf2bd0)) ; defparam enf7f9b.GSR = "ENABLED" ; FD1P3DX enf7f9b (.D(gbdc8fc), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(an95e84)) ; defparam cb33fe6.GSR = "ENABLED" ; FD1P3DX cb33fe6 (.D(hbfc8e9), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(lfaf424)) ; defparam xl28fcf.GSR = "ENABLED" ; FD1P3DX xl28fcf (.D(hbe9eed), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(gb7a126)) ; defparam ls93ebd.GSR = "ENABLED" ; FD1P3DX ls93ebd (.D(wjeddf6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(dmd0935)) ; defparam wwe0e99.GSR = "ENABLED" ; FD1P3DX wwe0e99 (.D(blf69c4), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(jr849aa)) ; defparam uk2b8fe.GSR = "ENABLED" ; FD1P3DX uk2b8fe (.D(ayc4d57), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ym24d57)) ; defparam rt4f2d3.GSR = "ENABLED" ; FD1P3DX rt4f2d3 (.D(dm57357), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(cb26ab8)) ; defparam osd1d61.GSR = "ENABLED" ; FD1P3DX osd1d61 (.D(dm57475), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(ls355c5)) ; defparam ba353e8.GSR = "ENABLED" ; FD1P3DX ba353e8 (.D(qt755c6), .SP(dz6110a), .CK(dzec4ce), .CD(vvec21b), .Q(fpbfc60)) ; defparam xy86158.GSR = "ENABLED" ; FD1S3DX xy86158 (.D(oh8a7a4), .CK(dzec4ce), .CD(je99dc6), .Q(shc3703)) ; defparam tw1b81d.GSR = "ENABLED" ; FD1S3DX tw1b81d (.D(ld4f71c), .CK(dzec4ce), .CD(je99dc6), .Q(neeba75)) ; defparam zk5d3ab.GSR = "ENABLED" ; FD1S3DX zk5d3ab (.D(uif5fa8), .CK(dzec4ce), .CD(je99dc6), .Q(uv5bd24)) ; defparam uide925.GSR = "ENABLED" ; FD1S3DX uide925 (.D(jp7e0e8), .CK(dzec4ce), .CD(je99dc6), .Q(oh29703)) ; defparam ip4b81d.GSR = "ENABLED" ; FD1S3DX ip4b81d (.D(hbc2b1e), .CK(dzec4ce), .CD(je99dc6), .Q(nrec274)) ; defparam bl613a7.GSR = "ENABLED" ; FD1S3DX bl613a7 (.D(rv816fe), .CK(dzec4ce), .CD(je99dc6), .Q(pu3ff3b)) ; defparam suff9da.GSR = "ENABLED" ; FD1S3DX suff9da (.D(co9d6b8), .CK(dzec4ce), .CD(je99dc6), .Q(vid0f0a)) ; defparam uk87852.GSR = "ENABLED" ; FD1S3DX uk87852 (.D(xw57c80), .CK(dzec4ce), .CD(je99dc6), .Q(sj908ca)) ; defparam zz84654.GSR = "ENABLED" ; FD1S3DX zz84654 (.D(gbedb34), .CK(dzec4ce), .CD(je99dc6), .Q(yma69d4)) ; defparam ec34ea1.GSR = "ENABLED" ; FD1S3DX ec34ea1 (.D(ep266b), .CK(dzec4ce), .CD(je99dc6), .Q(tj948d)) ; defparam dz4a46e.GSR = "ENABLED" ; FD1S3DX dz4a46e (.D(ay72dd2), .CK(dzec4ce), .CD(je99dc6), .Q(kq7758f)) ; defparam hdbac79.GSR = "ENABLED" ; FD1S3DX hdbac79 (.D(sj95ca1), .CK(fndd899), .CD(vvec21b), .Q(cmce96b)) ; defparam xj74b58.GSR = "ENABLED" ; FD1S3DX xj74b58 (.D(ls20f3f), .CK(fndd899), .CD(vvec21b), .Q(ldc7df2)) ; defparam ks3ef96.GSR = "ENABLED" ; FD1S3DX ks3ef96 (.D(fpa5ac0), .CK(fndd899), .CD(vvec21b), .Q(bnb0962)) ; defparam nt84b17.GSR = "ENABLED" ; FD1S3DX nt84b17 (.D(uxbe6f6), .CK(fndd899), .CD(vvec21b), .Q(phbf54d)) ; defparam wwfaa6f.GSR = "ENABLED" ; FD1S3DX wwfaa6f (.D(ip7f3bf), .CK(fndd899), .CD(vvec21b), .Q(go7861c)) ; defparam alc30e0.GSR = "ENABLED" ; FD1S3DX alc30e0 (.D(ww781a8), .CK(fndd899), .CD(vvec21b), .Q(qi5b38)) ; defparam fp2d9c1.GSR = "ENABLED" ; FD1S3DX fp2d9c1 (.D(ba1e4f6), .CK(fndd899), .CD(vvec21b), .Q(hqe431)) ; defparam me7218b.GSR = "ENABLED" ; FD1S3DX me7218b (.D(gdabfd5), .CK(fndd899), .CD(vvec21b), .Q(os598c7)) ; defparam wjcc638.GSR = "ENABLED" ; FD1S3DX wjcc638 (.D(ps79094), .CK(fndd899), .CD(vvec21b), .Q(goc453f)) ; defparam zz229f8.GSR = "ENABLED" ; FD1S3DX zz229f8 (.D(gqb3bde), .CK(fndd899), .CD(vvec21b), .Q(thc74dd)) ; defparam ba3a6ef.GSR = "ENABLED" ; FD1S3DX ba3a6ef (.D(gqc04), .CK(fndd899), .CD(vvec21b), .Q(pf7b9f0)) ; defparam uvdcf86.GSR = "ENABLED" ; FD1S3DX uvdcf86 (.D(shc3703), .CK(dzec4ce), .CD(je99dc6), .Q(bn8b1b5)) ; defparam bna5251.GSR = "ENABLED" ; FD1S3DX bna5251 (.D(neeba75), .CK(dzec4ce), .CD(je99dc6), .Q(xy96d51)) ; defparam ww7d1e4.GSR = "ENABLED" ; FD1S3DX ww7d1e4 (.D(uv5bd24), .CK(dzec4ce), .CD(je99dc6), .Q(tud5b8a)) ; defparam ls455a.GSR = "ENABLED" ; FD1S3DX ls455a (.D(oh29703), .CK(dzec4ce), .CD(je99dc6), .Q(gqa75b)) ; defparam ec97337.GSR = "ENABLED" ; FD1S3DX ec97337 (.D(nrec274), .CK(dzec4ce), .CD(je99dc6), .Q(ea53ad9)) ; defparam mec1afa.GSR = "ENABLED" ; FD1S3DX mec1afa (.D(pu3ff3b), .CK(dzec4ce), .CD(je99dc6), .Q(sw9d6c9)) ; defparam pu8cf88.GSR = "ENABLED" ; FD1S3DX pu8cf88 (.D(vid0f0a), .CK(dzec4ce), .CD(je99dc6), .Q(faeb649)) ; defparam ph19281.GSR = "ENABLED" ; FD1S3DX ph19281 (.D(sj908ca), .CK(dzec4ce), .CD(je99dc6), .Q(yxc69d3)) ; defparam fa7cff8.GSR = "ENABLED" ; FD1S3DX fa7cff8 (.D(yma69d4), .CK(dzec4ce), .CD(je99dc6), .Q(ks34e9c)) ; defparam mt1d464.GSR = "ENABLED" ; FD1S3DX mt1d464 (.D(tj948d), .CK(dzec4ce), .CD(je99dc6), .Q(fca74e1)) ; defparam tj288f3.GSR = "ENABLED" ; FD1S3DX tj288f3 (.D(kq7758f), .CK(dzec4ce), .CD(je99dc6), .Q(fc3a70a)) ; defparam byf4ab7.GSR = "ENABLED" ; FD1S3DX byf4ab7 (.D(cmce96b), .CK(fndd899), .CD(vvec21b), .Q(byee645)) ; defparam hodf65c.GSR = "ENABLED" ; FD1S3DX hodf65c (.D(ldc7df2), .CK(fndd899), .CD(vvec21b), .Q(phc7fd)) ; defparam tj13a0c.GSR = "ENABLED" ; FD1S3DX tj13a0c (.D(bnb0962), .CK(fndd899), .CD(vvec21b), .Q(ww72fa5)) ; defparam oh39b78.GSR = "ENABLED" ; FD1S3DX oh39b78 (.D(phbf54d), .CK(fndd899), .CD(vvec21b), .Q(mgb6c3e)) ; defparam je2f10b.GSR = "ENABLED" ; FD1S3DX je2f10b (.D(go7861c), .CK(fndd899), .CD(vvec21b), .Q(qib61f0)) ; defparam cmd105e.GSR = "ENABLED" ; FD1S3DX cmd105e (.D(qi5b38), .CK(fndd899), .CD(vvec21b), .Q(dbb0f81)) ; defparam gq888a2.GSR = "ENABLED" ; FD1S3DX gq888a2 (.D(hqe431), .CK(fndd899), .CD(vvec21b), .Q(aa87c0f)) ; defparam pu8ced2.GSR = "ENABLED" ; FD1S3DX pu8ced2 (.D(os598c7), .CK(fndd899), .CD(vvec21b), .Q(rv270b3)) ; defparam wy982b2.GSR = "ENABLED" ; FD1S3DX wy982b2 (.D(goc453f), .CK(fndd899), .CD(vvec21b), .Q(zz3859e)) ; defparam aa8801f.GSR = "ENABLED" ; FD1S3DX aa8801f (.D(thc74dd), .CK(fndd899), . -CD(vvec21b), .Q(xjc2cf6)) ; defparam wjc6185.GSR = "ENABLED" ; FD1S3DX wjc6185 (.D(pf7b9f0), .CK(fndd899), .CD(vvec21b), .Q(fp167b6)) ; defparam vv6b6ef.GSR = "ENABLED" ; FD1S3BX vv6b6ef (.D(ykdbbf4), .CK(dzec4ce), .PD(vvec21b), .Q(of442bd)) ; defparam byf438e.GSR = "ENABLED" ; FD1S3DX byf438e (.D(doe394), .CK(fndd899), .CD(je99dc6), .Q(qgc498c)) ; defparam bn947f8.GSR = "ENABLED" ; FD1S3BX bn947f8 (.D(ym1fe39), .CK(dzec4ce), .PD(vvec21b), .Q(fp8177d)) ; defparam sj3926f.GSR = "ENABLED" ; FD1S3DX sj3926f (.D(su49be4), .CK(fndd899), .CD(je99dc6), .Q(pubbee)) ; CU2 nee42eb (.CI(vve93e5), .PC1(yk437fc), .PC0(wl86ff), .CO(tueb653), .NC1(co2ed68), .NC0(mrcc0e7)); CU2 hoca6a5 (.CI(tueb653), .PC1(hbd8cdc), .PC0(jpfc2d8), .CO(hda5628), .NC1(aaac960), .NC0(rg57660)); CU2 byc51c2 (.CI(hda5628), .PC1(ip6f9da), .PC0(mrdcd6f), .CO(rtc259e), .NC1(swa35b2), .NC0(fp32b4f)); CU2 wyb3dea (.CI(rtc259e), .PC1(hoe16e9), .PC0(nedaae1), .CO(qgea1e2), .NC1(jr1c457), .NC0(qvd2ef)); CU2 gd3c430 (.CI(qgea1e2), .PC1(ykeff6e), .PC0(nre96ef), .CO(je30903), .NC1(meff796), .NC0(lde38f6)); CU2 pu206f9 (.CI(je30903), .PC1(ip54b06), .PC0(dz6e32c), .CO(dzf97da), .NC1(), .NC0(bl508a5)); CU2 hb5f6b0 (.CI(vve93e5), .PC1(sj2cddc), .PC0(al659bb), .CO(zzb0cdc), .NC1(qte72d5), .NC0(tj91548)); CU2 tj9b9dd (.CI(zzb0cdc), .PC1(hbfc8e9), .PC0(gbdc8fc), .CO(hbddf20), .NC1(and471), .NC0(gq21e87)); CU2 jce418b (.CI(hbddf20), .PC1(wjeddf6), .PC0(hbe9eed), .CO(lf8b6b8), .NC1(aa3b409), .NC0(mg24fde)); CU2 zxd71e3 (.CI(lf8b6b8), .PC1(ayc4d57), .PC0(blf69c4), .CO(rte3cf4), .NC1(mr7fe6a), .NC0(su53d87)); CU2 db9e9d6 (.CI(rte3cf4), .PC1(dm57475), .PC0(dm57357), .CO(end6ed2), .NC1(qi314e7), .NC0(ymfd6c)); CU2 hoda55d (.CI(end6ed2), .PC1(ip54b06), .PC0(qt755c6), .CO(xw5d5ed), .NC1(), .NC0(gd2953a)); FSUB2 ne57b59 (.A1(yk437fc), .A0(wl86ff), .B1(gq1ff73), .B0(yz90edd), .BI(vve93e5), .BOUT1(of5bb89), .BOUT0(), .S1(blddc4d), .S0(viee26e)); FSUB2 jp71372 (.A1(hbd8cdc), .A0(jpfc2d8), .B1(fa7914e), .B0(cbbe941), .BI(of5bb89), .BOUT1(oub3782), .BOUT0(), .S1(nt9bc11), .S0(qgde08f)); FSUB2 kqf0478 (.A1(ip6f9da), .A0(mrdcd6f), .B1(sh5441a), .B0(mr5165e), .BI(oub3782), .BOUT1(hq1542), .BOUT0(), .S1(ecaa12), .S0(nr55090)); FSUB2 nga8487 (.A1(hoe16e9), .A0(nedaae1), .B1(wyb3db6), .B0(cmfa153), .BI(hq1542), .BOUT1(aydb909), .BOUT0(), .S1(shdc849), .S0(bye424c)); FSUB2 co21263 (.A1(ykeff6e), .A0(nre96ef), .B1(rg47205), .B0(pfe6e08), .BI(aydb909), .BOUT1(icce216), .BOUT0(), .S1(xj710b1), .S0(aa8858e)); FSUB2 fa42c70 (.A1(ip54b06), .A0(xjdd849), .B1(ip54b06), .B0(ip54b06), .BI(icce216), .BOUT1(), .BOUT0(), .S1(), .S0(fp16be0)); VHI dbb5f07 (.Z(vve93e5)); FSUB2 xw7c1ff (.A1(jrb5458), .A0(byf4138), .B1(sj2cddc), .B0(al659bb), .BI(vve93e5), .BOUT1(rgd0889), .BOUT0(), .S1(rv8444a), .S0(jr22256)); FSUB2 ls112b6 (.A1(en5143a), .A0(ld6e292), .B1(hbfc8e9), .B0(gbdc8fc), .BI(rgd0889), .BOUT1(yz9ac49), .BOUT0(), .S1(czd624d), .S0(anb126c)); FSUB2 zm89364 (.A1(yzddb5), .A0(al7a1d4), .B1(wjeddf6), .B0(hbe9eed), .BI(yz9ac49), .BOUT1(fc116be), .BOUT0(), .S1(db8b5f3), .S0(jp5af9f)); FSUB2 nrd7cff (.A1(wjd3853), .A0(mg82af9), .B1(ayc4d57), .B0(blf69c4), .BI(fc116be), .BOUT1(ipfdd40), .BOUT0(), .S1(tueea05), .S0(wj7502b)); FSUB2 twa815c (.A1(ux2c1a6), .A0(fa66258), .B1(dm57475), .B0(dm57357), .BI(ipfdd40), .BOUT1(ym1f04f), .BOUT0(), .S1(qi2bc57), .S0(mec13c4)); FSUB2 vx9e20 (.A1(ip54b06), .A0(me49dfe), .B1(ip54b06), .B0(ip54b06), .BI(ym1f04f), .BOUT1(), .BOUT0(), .S1(), .S0(cb8ae62)); AGEB2 zxf90a3 (.A1(sj2cddc), .A0(al659bb), .B1(jrb5458), .B0(byf4138), .CI(dz6110a), .GE(fnf64cb)); AGEB2 rib265f (.A1(hbfc8e9), .A0(gbdc8fc), .B1(en5143a), .B0(ld6e292), .CI(fnf64cb), .GE(fada633)); AGEB2 czd319a (.A1(wjeddf6), .A0(hbe9eed), .B1(yzddb5), .B0(al7a1d4), .CI(fada633), .GE(lfa0b69)); AGEB2 aa5b4e (.A1(ayc4d57), .A0(blf69c4), .B1(wjd3853), .B0(mg82af9), .CI(lfa0b69), .GE(zz8e2af)); AGEB2 dz7157f (.A1(dm57475), .A0(dm57357), .B1(ux2c1a6), .B0(fa66258), .CI(zz8e2af), .GE(vif4de2)); AGEB2 oua6f13 (.A1(ip54b06), .A0(en60cda), .B1(ip54b06), .B0(db3dcc3), .CI(vif4de2), .GE(goce132)); FADD2 gb70991 (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(goce132), .COUT1(), .COUT0(), .S1(), .S0(ykdbbf4)); AGEB2 tu7cf8d (.A1(yk437fc), .A0(wl86ff), .B1(gq1ff73), .B0(yz90edd), .CI(su43126), .GE(xw5d2c7)); AGEB2 vve963b (.A1(hbd8cdc), .A0(jpfc2d8), .B1(fa7914e), .B0(cbbe941), .CI(xw5d2c7), .GE(kdfd5c3)); AGEB2 eaeae1c (.A1(ip6f9da), .A0(mrdcd6f), .B1(sh5441a), .B0(mr5165e), .CI(kdfd5c3), .GE(oua53b)); AGEB2 rg529d9 (.A1(hoe16e9), .A0(nedaae1), .B1(wyb3db6), .B0(cmfa153), .CI(oua53b), .GE(gb5e468)); AGEB2 kdf2344 (.A1(ykeff6e), .A0(nre96ef), .B1(rg47205), .B0(pfe6e08), .CI(gb5e468), .GE(ou2e02a)); AGEB2 en70150 (.A1(ip54b06), .A0(ipd3301), .B1(ip54b06), .B0(ba14af1), .CI(ou2e02a), .GE(xy250b7)); FADD2 zz285bb (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(xy250b7), .COUT1(), .COUT0(), .S1(), .S0(doe394)); AGEB2 vvd7710 (.A1(ay77190[1]), .A0(ay77190[0]), .B1(rv8444a), .B0(jr22256), .CI(dz6110a), .GE(ou34b02)); AGEB2 nta5811 (.A1(ay77190[3]), .A0(ay77190[2]), .B1(czd624d), .B0(anb126c), .CI(ou34b02), .GE(sh75b56)); AGEB2 riadab5 (.A1(ay77190[5]), .A0(ay77190[4]), .B1(db8b5f3), .B0(jp5af9f), .CI(sh75b56), .GE(sh51a76)); AGEB2 wy8d3b4 (.A1(ay77190[7]), .A0(ay77190[6]), .B1(tueea05), .B0(wj7502b), .CI(sh51a76), .GE(ep28a7)); AGEB2 hq1453c (.A1(ay77190[9]), .A0(ay77190[8]), .B1(qi2bc57), .B0(mec13c4), .CI(ep28a7), .GE(do1b4e6)); AGEB2 lqda732 (.A1(ip54b06), .A0(doa230b), .B1(ip54b06), .B0(ukb98a2), .CI(do1b4e6), .GE(sj955b9)); FADD2 dbaadcd (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(sj955b9), .COUT1(), .COUT0(), .S1(), .S0(ym1fe39)); AGEB2 qgcb3e2 (.A1(blddc4d), .A0(viee26e), .B1(dob8c81[1]), .B0(dob8c81[0]), .CI(su43126), .GE(wy884a3)); AGEB2 zk42518 (.A1(nt9bc11), .A0(qgde08f), .B1(dob8c81[3]), .B0(dob8c81[2]), .CI(wy884a3), .GE(sj1de2c)); AGEB2 ayef164 (.A1(ecaa12), .A0(nr55090), .B1(dob8c81[5]), .B0(dob8c81[4]), .CI(sj1de2c), .GE(zm173b)); AGEB2 twb9da (.A1(shdc849), .A0(bye424c), .B1(dob8c81[7]), .B0(dob8c81[6]), .CI(zm173b), .GE(wl90856)); AGEB2 fp842b4 (.A1(xj710b1), .A0(aa8858e), .B1(dob8c81[9]), .B0(dob8c81[8]), .CI(wl90856), .GE(ou31068)); AGEB2 gq88340 (.A1(ip54b06), .A0(fp16be0), .B1(ip54b06), .B0(ip54b06), .CI(ou31068), .GE(gq5871)); VLO cb2c389 (.Z(ip54b06)); FADD2 xye26e (.A1(ip54b06), .A0(ip54b06), .B1(ip54b06), .B0(ip54b06), .CI(gq5871), .COUT1(), .COUT0(), .S1(), .S0(su49be4)); assign db3205d = of442bd; assign cb902ef = qgc498c; - -always@* begin hqbd2d7<={icdbb13>>1,nrf6ece[0]};jpe96ba<=nrf6ece[1];uv4b5d7<=nrf6ece[2];pf5aebd<=nrf6ece[3];jpd75ef<=nrf6ece[4];fpbaf7e<=nrf6ece[5];thd7bf6<=nrf6ece[6];jebdfb7<={ay77190>>1,nrf6ece[7]};ayefdbb<={dob8c81>>1,nrf6ece[8]};end -always@* begin bl7edd9[2047]<=fndd899;bl7edd9[2046]<=dzec4ce;bl7edd9[2044]<=ww62677;bl7edd9[2040]<=nt133b8;bl7edd9[2032]<=je99dc6;bl7edd9[2016]<=gocee32;bl7edd9[1984]<=ay77190[0];bl7edd9[1920]<=dob8c81[0];bl7edd9[1023]<=icdbb13[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[0]};jpe96ba<=nrf6ece[1];uv4b5d7<=nrf6ece[2];pf5aebd<=nrf6ece[3];jpd75ef<=nrf6ece[4];fpbaf7e<=nrf6ece[5];thd7bf6<=nrf6ece[6];jebdfb7<={ay77190>>1,nrf6ece[7]};ayefdbb<={dob8c81>>1,nrf6ece[8]};end -always@* begin bl7edd9[2047]<=fndd899;bl7edd9[2046]<=dzec4ce;bl7edd9[2044]<=ww62677;bl7edd9[2040]<=nt133b8;bl7edd9[2032]<=je99dc6;bl7edd9[2017]<=gocee32;bl7edd9[1987]<=ay77190[0];bl7edd9[1926]<=dob8c81[0];bl7edd9[1023]<=icdbb13[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[0]};jpe96ba<=nrf6ece[1];uv4b5d7<=nrf6ece[2];pf5aebd<=nrf6ece[3];jpd75ef<=nrf6ece[4];fpbaf7e<=nrf6ece[5];thd7bf6<=nrf6ece[6];jebdfb7<={ay77190>>1,nrf6ece[7]};ayefdbb<={dob8c81>>1,nrf6ece[8]};fpba667<=nrf6ece[9];wjd333f<=nrf6ece[10];do999fc<=nrf6ece[11];mrccfe2<=nrf6ece[12];ay67f15<=nrf6ece[13];vk3f8a9<=nrf6ece[14];rtfc54a<=nrf6ece[15];kde2a56<=nrf6ece[16];wy152b5<=nrf6ece[17];gqa95a9<=nrf6ece[18];xj4ad49<=nrf6ece[19];go56a4e<=nrf6ece[20];lfb5271<=nrf6ece[21];iea938e<=nrf6ece[22];kq49c71<=nrf6ece[23];mr4e389<=nrf6ece[24];dz71c4d<=nrf6ece[25];db8e26f<=nrf6ece[26];jp7137f<=nrf6ece[27];tw89bfe<=nrf6ece[28];fa4dff3<=nrf6ece[29];yx6ff9b<=nrf6ece[30];kd7fcdd<=nrf6ece[31];fafe6ec<=nrf6ece[32];xjf3763<=nrf6ece[33];hd9bb1f<=nrf6ece[34];xjdd8ff<=nrf6ece[35];rtec7fe<=nrf6ece[36];fa63ff7<=nrf6ece[37];ie1ffbb<=nrf6ece[38];cmffdd9<=nrf6ece[39];tufeec8<=nrf6ece[40];alf7642<=nrf6ece[41];epbb215<=nrf6ece[42];ofd90ad<=nrf6ece[43];blc856d<=nrf6ece[44];ne42b6e<=nrf6ece[45];aa15b72<=nrf6ece[46];jeadb90<=nrf6ece[47];os6dc82<=nrf6ece[48];fn6e410<=nrf6ece[49];ic72086<=nrf6ece[50];qv90431<=nrf6ece[51];ks8218d<=nrf6ece[52];gq10c69<=nrf6ece[53];fc86348<=nrf6ece[54];sw31a43<=nrf6ece[55];qi8d219<=nrf6ece[56];dm690c8<=nrf6ece[57];xw48643<=nrf6ece[58];go4321a<=nrf6ece[59];db190d1<=nrf6ece[60];rtc868f<=nrf6ece[61];kq4347e<=nrf6ece[62];gq1a3f1<=nrf6ece[63];icd1f88<=nrf6ece[64];wl8fc40<=nrf6ece[65];bl7e204<=nrf6ece[66];psf1027<=nrf6ece[67];ou8813a<=nrf6ece[68];pf409d0<=nrf6ece[69];vk4e87<=nrf6ece[70];tj2743b<=nrf6ece[71];ng3a1de<=nrf6ece[72];hod0ef3<=nrf6ece[73];mg8779a<=nrf6ece[74];wy3bcd1<=nrf6ece[75];wwde688<=nrf6ece[76];jpf3440<=nrf6ece[77];yz9a207<=nrf6ece[78];wwd103c<=nrf6ece[79];gq881e1<=nrf6ece[80];dz40f08<=nrf6ece[81];ep7847<=nrf6ece[82];ir3c23c<=nrf6ece[83];pse11e4<=nrf6ece[84];mt8f23<=nrf6ece[85];by4791d<=nrf6ece[86];kf3c8ea<=nrf6ece[87];jce4755<=nrf6ece[88];qv23aab<=nrf6ece[89];ux1d55d<=nrf6ece[90];uieaaed<=nrf6ece[91];fn55769<=nrf6ece[92];cbabb4f<=nrf6ece[93];ps5da7d<=nrf6ece[94];ened3ea<=nrf6ece[95];fa69f55<=nrf6ece[96];ld4faaa<=nrf6ece[97];os7d556<=nrf6ece[98];kqeaab0<=nrf6ece[99];dz55581<=nrf6ece[100];ntaac0f<=nrf6ece[101];yk5607f<=nrf6ece[102];vxb03f8<=nrf6ece[103];nt81fc6<=nrf6ece[104];ecfe37<=nrf6ece[105];mr7f1b8<=nrf6ece[106];alf8dc5<=nrf6ece[107];ipc6e2d<=nrf6ece[108];ph3716c<=nrf6ece[109];twb8b67<=nrf6ece[110];dmc5b3b<=nrf6ece[111];fp2d9db<=nrf6ece[112];jc6cede<=nrf6ece[113];os676f2<=nrf6ece[114];ym3b790<=nrf6ece[115];qgdbc81<=nrf6ece[116];osde409<=nrf6ece[117];wjf2048<=nrf6ece[118];yz90245<=nrf6ece[119];zz8122d<=nrf6ece[120];vx916e<=nrf6ece[121];rg48b76<=nrf6ece[122];rt45bb3<=nrf6ece[123];nt2dd9f<=nrf6ece[124];xj6ecfe<=nrf6ece[125];by767f7<=nrf6ece[126];ksb3fbb<=nrf6ece[127];cb9fdd8<=nrf6ece[128];hofeec5<=nrf6ece[129];ipf762a<=nrf6ece[130];qvbb155<=nrf6ece[131];hbd8aad<=nrf6ece[132];rgc556e<=nrf6ece[133];hq2ab72<=nrf6ece[134];fn55b93<=nrf6ece[135];xyadc9e<=nrf6ece[136];zx6e4f2<=nrf6ece[137];me72796<=nrf6ece[138];vk93cb1<=nrf6ece[139];bn9e58b<=nrf6ece[140];wjf2c5e<=nrf6ece[141];tw962f4<=nrf6ece[142];gdb17a2<=nrf6ece[143];xl8bd14<=nrf6ece[144];ip5e8a6<=nrf6ece[145];dmf4535<=nrf6ece[146];xya29aa<=nrf6ece[147];xy14d53<=nrf6ece[148];ksa6a9a<=nrf6ece[149];xy354d1<=nrf6ece[150];dbaa68a<=nrf6ece[151];su53456<=nrf6ece[152];yz9a2b0<=nrf6ece[153];wwd1584<=nrf6ece[154];ir8ac21<=nrf6ece[155];qg5610c<=nrf6ece[156];jrb0860<=nrf6ece[157];zz84307<=nrf6ece[158];sw2183e<=nrf6ece[159];hdc1f0<=nrf6ece[160];kd60f86<=nrf6ece[161];ux7c34<=nrf6ece[162];ec3e1a4<=nrf6ece[163];mef0d21<=nrf6ece[164];vk86909<=nrf6ece[165];mg3484a<=nrf6ece[166];wla4251<=nrf6ece[167];ou2128d<=nrf6ece[168];fp9469<=nrf6ece[169];vv4a34e<=nrf6ece[170];wj51a77<=nrf6ece[171];co8d3bc<=nrf6ece[172];vi69de0<=nrf6ece[173];ip4ef02<=nrf6ece[174];qg77814<=nrf6ece[175];wybc0a0<=nrf6ece[176];wwe0500<=nrf6ece[177];qv2801<=nrf6ece[178];zm1400c<=nrf6ece[179];hda0063<=nrf6ece[180];ym31f<=nrf6ece[181];ls18f8<=nrf6ece[182];rvc7c3<=nrf6ece[183];lq63e1e<=nrf6ece[184];ec1f0f3<=nrf6ece[185];uvf8798<=nrf6ece[186];ipc3cc4<=nrf6ece[187];ng1e624<=nrf6ece[188];pff3122<=nrf6ece[189];sw98917<=nrf6ece[190];ayc48b8<=nrf6ece[191];ec245c1<=nrf6ece[192];db22e09<=nrf6ece[193];ux1704f<=nrf6ece[194];ngb827c<=nrf6ece[195];cmc13e2<=nrf6ece[196];tj9f10<=nrf6ece[197];hb4f887<=nrf6ece[198];jc7c43e<=nrf6ece[199];yxe21f2<=nrf6ece[200];aa10f94<=nrf6ece[201];ie87ca0<=nrf6ece[202];mg3e500<=nrf6ece[203];alf2801<=nrf6ece[204];bn9400c<=nrf6ece[205];xla0067<=nrf6ece[206];wy33f<=nrf6ece[207];vk19f8<=nrf6ece[208];tjcfc3<=nrf6ece[209];ea67e1f<=nrf6ece[210];ba3f0f9<=nrf6ece[211];qtf87cb<=nrf6ece[212];czc3e5c<=nrf6ece[213];qi1f2e4<=nrf6ece[214];nrf9720<=nrf6ece[215];cmcb906<=nrf6ece[216];ui5c830<=nrf6ece[217];rge4180<=nrf6ece[218];ba20c03<=nrf6ece[219];bn601a<=nrf6ece[220];ng300d7<=nrf6ece[221];an806ba<=nrf6ece[222];db35d4<=nrf6ece[223];co1aea7<=nrf6ece[224];jpd7539<=nrf6ece[225];fpba9ce<=nrf6ece[226];qgd4e76<=nrf6ece[227];hqa73b0<=nrf6ece[228];wl39d82<=nrf6ece[229];aycec15<=nrf6ece[230];fa760a8<=nrf6ece[231];tjb0543<=nrf6ece[232];uk82a1e<=nrf6ece[233];ec150f0<=nrf6ece[234];twa8781<=nrf6ece[235];ui43c0b<=nrf6ece[236];fc1e058<=nrf6ece[237];ayf02c2<=nrf6ece[238];bn81610<=nrf6ece[239];jeb086<=nrf6ece[240];dm58433<=nrf6ece[241];rtc219b<= -nrf6ece[242];ks10cdf<=nrf6ece[243];ls866f8<=nrf6ece[244];qv337c3<=nrf6ece[245];db9be1d<=nrf6ece[246];psdf0ef<=nrf6ece[247];enf877a<=nrf6ece[248];kdc3bd4<=nrf6ece[249];ep1dea4<=nrf6ece[250];suef524<=nrf6ece[251];kd7a920<=nrf6ece[252];ead4904<=nrf6ece[253];qva4820<=nrf6ece[254];ou24104<=nrf6ece[255];do20821<=nrf6ece[256];pu410a<=nrf6ece[257];ri20852<=nrf6ece[258];xy4292<=nrf6ece[259];co21492<=nrf6ece[260];ksa491<=nrf6ece[261];lq52489<=nrf6ece[262];sw9244a<=nrf6ece[263];wy92250<=nrf6ece[264];fp91280<=nrf6ece[265];ba89407<=nrf6ece[266];pf4a03a<=nrf6ece[267];bl501d7<=nrf6ece[268];wl80ebf<=nrf6ece[269];an75fd<=nrf6ece[270];fc3afed<=nrf6ece[271];thd7f6a<=nrf6ece[272];lfbfb57<=nrf6ece[273];offdabe<=nrf6ece[274];qted5f5<=nrf6ece[275];yx6afad<=nrf6ece[276];jc57d6d<=nrf6ece[277];irbeb6b<=nrf6ece[278];osf5b5c<=nrf6ece[279];lsadae1<=nrf6ece[280];ea6d70a<=nrf6ece[281];hb6b851<=nrf6ece[282];cm5c28f<=nrf6ece[283];hoe1479<=nrf6ece[284];yma3cb<=nrf6ece[285];uv51e59<=nrf6ece[286];oh8f2cc<=nrf6ece[287];rg79665<=nrf6ece[288];iccb32a<=nrf6ece[289];ui59951<=nrf6ece[290];shcca88<=nrf6ece[291];yx65445<=nrf6ece[292];fc2a22d<=nrf6ece[293];kd5116a<=nrf6ece[294];ou88b55<=nrf6ece[295];th45aa9<=nrf6ece[296];db2d54f<=nrf6ece[297];yx6aa7f<=nrf6ece[298];ld553fd<=nrf6ece[299];wya9fef<=nrf6ece[300];rt4ff78<=nrf6ece[301];mr7fbc6<=nrf6ece[302];wjfde34<=nrf6ece[303];ayef1a5<=nrf6ece[304];ui78d28<=nrf6ece[305];mrc6941<=nrf6ece[306];end -always@* begin bl7edd9[2047]<=fndd899;bl7edd9[2046]<=dzec4ce;bl7edd9[2044]<=ww62677;bl7edd9[2043]<=tu57f16;bl7edd9[2040]<=nt133b8;bl7edd9[2038]<=jr22256;bl7edd9[2032]<=je99dc6;bl7edd9[2029]<=vve93e5;bl7edd9[2017]<=gocee32;bl7edd9[2013]<=go7861c;bl7edd9[2010]<=rv8444a;bl7edd9[2003]<=sj955b9;bl7edd9[1990]<=tueb653;bl7edd9[1987]<=ay77190[0];bl7edd9[1982]<=uvfde54;bl7edd9[1980]<=an95e84;bl7edd9[1979]<=dbb0f81;bl7edd9[1973]<=anb126c;bl7edd9[1963]<=rv132cf;bl7edd9[1958]<=su43126;bl7edd9[1957]<=thc74dd;bl7edd9[1953]<=cbbe941;bl7edd9[1942]<=ym24d57;bl7edd9[1932]<=fp32b4f;bl7edd9[1929]<=blddc4d;bl7edd9[1926]<=dob8c81[0];bl7edd9[1923]<=lf8b6b8;bl7edd9[1921]<=al4b77f;bl7edd9[1917]<=do1b4e6;bl7edd9[1914]<=os598c7;bl7edd9[1913]<=lfaf424;bl7edd9[1911]<=qi5b38;bl7edd9[1903]<=irb4e26;bl7edd9[1898]<=rgd0889;bl7edd9[1879]<=pu9967e;bl7edd9[1876]<=nrec274;bl7edd9[1872]<=xw57c80;bl7edd9[1868]<=qgc48c9;bl7edd9[1866]<=fp167b6;bl7edd9[1863]<=ou2e02a;bl7edd9[1858]<=fa7914e;bl7edd9[1837]<=cb26ab8;bl7edd9[1816]<=swa35b2;bl7edd9[1810]<=qgde08f;bl7edd9[1805]<=fnc8624;bl7edd9[1802]<=uk1f0b6;bl7edd9[1799]<=ymfd6c;bl7edd9[1795]<=kd7fb71;bl7edd9[1786]<=ukb98a2;bl7edd9[1783]<=zzaae34;bl7edd9[1780]<=zz3859e;bl7edd9[1778]<=gb7a126;bl7edd9[1775]<=aa87c0f;bl7edd9[1770]<=hbc2b1e;bl7edd9[1758]<=gd26ab9;bl7edd9[1748]<=czd624d;bl7edd9[1710]<=gocb3f3;bl7edd9[1704]<=sw9d6c9;bl7edd9[1701]<=ux2c1a6;bl7edd9[1699]<=db8b5f3;bl7edd9[1696]<=gbedb34;bl7edd9[1689]<=yz129fb;bl7edd9[1685]<=pf7b9f0;bl7edd9[1679]<=pu1bfe1;bl7edd9[1678]<=ba14af1;bl7edd9[1668]<=jpfc2d8;bl7edd9[1627]<=ls355c5;bl7edd9[1624]<=me49dfe;bl7edd9[1605]<=jcee6d6;bl7edd9[1589]<=wjd3853;bl7edd9[1584]<=hda5628;bl7edd9[1573]<=of5bb89;bl7edd9[1572]<=al659bb;bl7edd9[1567]<=ldc7df2;bl7edd9[1562]<=tw8c221;bl7edd9[1557]<=qte72d5;bl7edd9[1556]<=ou34b02;bl7edd9[1551]<=qi314e7;bl7edd9[1548]<=meff796;bl7edd9[1543]<=vv71966;bl7edd9[1524]<=doa230b;bl7edd9[1521]<=rg57660;bl7edd9[1519]<=icde57a;bl7edd9[1513]<=goc453f;bl7edd9[1512]<=yk437fc;bl7edd9[1509]<=dmd0935;bl7edd9[1504]<=su53d87;bl7edd9[1502]<=hqe431;bl7edd9[1499]<=bl4f76e;bl7edd9[1493]<=oh29703;bl7edd9[1492]<=rv816fe;bl7edd9[1469]<=gqb9aba;bl7edd9[1466]<=uif5fa8;bl7edd9[1448]<=jp5af9f;bl7edd9[1421]<=lfa0b69;bl7edd9[1417]<=byf4138;bl7edd9[1415]<=cmce96b;bl7edd9[1404]<=co2ed68;bl7edd9[1402]<=gq1ff73;bl7edd9[1400]<=aa3b409;bl7edd9[1398]<=jce47e4;bl7edd9[1377]<=kq7758f;bl7edd9[1374]<=uic45be;bl7edd9[1373]<=wy987d3;bl7edd9[1361]<=pu3ff3b;bl7edd9[1359]<=aa8858e;bl7edd9[1355]<=bn8b1b5;bl7edd9[1354]<=dm57357;bl7edd9[1350]<=wj7502b;bl7edd9[1349]<=vid0f0a;bl7edd9[1344]<=ep266b;bl7edd9[1343]<=xj710b1;bl7edd9[1341]<=sh51a76;bl7edd9[1330]<=zz94fdd;bl7edd9[1326]<=xy96d51;bl7edd9[1323]<=oh8012e;bl7edd9[1322]<=vif4de2;bl7edd9[1310]<=xwe16c6;bl7edd9[1308]<=ipd3301;bl7edd9[1305]<=tueea05;bl7edd9[1301]<=sj908ca;bl7edd9[1289]<=hbd8cdc;bl7edd9[1286]<=ou31068;bl7edd9[1280]<=sj95ca1;bl7edd9[1279]<=icce216;bl7edd9[1271]<=ieb9fef;bl7edd9[1224]<=do3f773;bl7edd9[1210]<=tud5b8a;bl7edd9[1207]<=fpbfc60;bl7edd9[1201]<=sw213fa;bl7edd9[1199]<=qgc498c;bl7edd9[1195]<=en60cda;bl7edd9[1193]<=bye424c;bl7edd9[1163]<=gbdc8fc;bl7edd9[1162]<=ps736b2;bl7edd9[1155]<=cmfa153;bl7edd9[1144]<=hbe6b7c;bl7edd9[1136]<=xy250b7;bl7edd9[1130]<=blf69c4;bl7edd9[1125]<=ipfdd40;bl7edd9[1120]<=qvd2ef;bl7edd9[1112]<=al7a1d4;bl7edd9[1110]<=yma69d4;bl7edd9[1104]<=kdd64f3;bl7edd9[1098]<=nt9bc11;bl7edd9[1096]<=sj2cddc;bl7edd9[1086]<=ww72fa5;bl7edd9[1076]<=xlb5ea4;bl7edd9[1067]<=blf31ce;bl7edd9[1065]<=thc2d84;bl7edd9[1060]<=mr5165e;bl7edd9[1054]<=rte3cf4;bl7edd9[1053]<=hoe16e9;bl7edd9[1051]<=su49be4;bl7edd9[1048]<=qgea1e2;bl7edd9[1039]<=uie5e73;bl7edd9[1026]<=fpa5ac0;bl7edd9[1023]<=icdbb13[0];bl7edd9[1021]<=fn4afe2;bl7edd9[1006]<=qib61f0;bl7edd9[1001]<=ym1fe39;bl7edd9[995]<=aaac960;bl7edd9[991]<=cz7fbca;bl7edd9[990]<=alf2bd0;bl7edd9[981]<=ldc2659;bl7edd9[978]<=xjc2cf6;bl7edd9[976]<=xw5d2c7;bl7edd9[971]<=jr849aa;bl7edd9[964]<=viee26e;bl7edd9[961]<=mr7fe6a;bl7edd9[960]<=zmb74b;bl7edd9[957]<=rv270b3;bl7edd9[951]<=rt6efb4;bl7edd9[938]<=ea53ad9;bl7edd9[936]<=co9d6b8;bl7edd9[931]<=ykeff6e;bl7edd9[901]<=jr3e16;bl7edd9[891]<=jrba3aa;bl7edd9[885]<=jp7e0e8;bl7edd9[850]<=fa66258;bl7edd9[849]<=yz9ac49;bl7edd9[839]<=gd1d5e2;bl7edd9[812]<=ym1f04f;bl7edd9[802]<=sj1de2c;bl7edd9[794]<=mg82af9;bl7edd9[786]<=jrb5458;bl7edd9[783]<=phc7fd;bl7edd9[778]<=tj91548;bl7edd9[774]<=lde38f6;bl7edd9[760]<=mga9411;bl7edd9[756]<=wl86ff;bl7edd9[752]<=hbddf20;bl7edd9[749]<=lqe474f;bl7edd9[746]<=gqa75b;bl7edd9[733]<=ld4f71c;bl7edd9[710]<=wjeddf6;bl7edd9[708]<=go59655;bl7edd9[707]<=byee645;bl7edd9[702]<=mrcc0e7;bl7edd9[701]<=yz90edd;bl7edd9[700]<=mg24fde;bl7edd9[699]<=jc66ee4;bl7edd9[688]<=fc3a70a;bl7edd9[687]<=goce132;bl7edd9[679]<=shdc849;bl7edd9[677]<=gqc04;bl7edd9[674]<=faeb649;bl7edd9[671]<=aydb909;bl7edd9[670]<=ph84dcf;bl7edd9[663]<=shc3703;bl7edd9[661]<=dm57475;bl7edd9[652]<=fc116be;bl7edd9[650]<=yxc69d3;bl7edd9[643]<=ph9e71b;bl7edd9[640]<=ay72dd2;bl7edd9[639]<=fp16be0;bl7edd9[635]<=rv373fd;bl7edd9[612]<=wy884a3;bl7edd9[605]<=neeba75;bl7edd9[599]<=of442bd;bl7edd9[597]<=db3dcc3;bl7edd9[596]<=ecaa12;bl7edd9[581]<=en5143a;bl7edd9[577]<=oua53b;bl7edd9[572]<=shc66e6;bl7edd9[568]<=doe394;bl7edd9[562]<=mec13c4;bl7edd9[556]<=fada633;bl7edd9[555]<=ks34e9c;bl7edd9[552]<=zkdac9e;bl7edd9[530]<=kdfd5c3;bl7edd9[526]<=nedaae1;bl7edd9[525]<=ng9c6f6;bl7edd9[513]<=ls20f3f;bl7edd9[510]<=xjdd849;bl7edd9[503]<=phbf54d;bl7edd9[495]<=ep28a7;bl7edd9[490]<=mg984cb;bl7edd9[482]<=end6ed2;bl7edd9[480]<=rgd570b;bl7edd9[465]<=nre96ef;bl7edd9[450]<=swbc266;bl7edd9[425]<=zz8e2af;bl7edd9[419]<=aa3e078;bl7edd9[406]<=cb8ae62;bl7edd9[401]<=fafbb9b;bl7edd9[389]<=je30903;bl7edd9[387]<=rtc259e;bl7edd9[373]<=uv5bd24;bl7edd9[366]<=oh8a7a4;bl7edd9[355]<=hbe9eed;bl7edd9[354]<=lf9fd1;bl7edd9[351]<=vvec21b;bl7edd9[350]<=zzb0cdc;bl7edd9[344]<=tj948d;bl7edd9[343]<=ykdbbf4;bl7edd9[339]<=hq1542;bl7edd9[338]<=gqb3bde;bl7edd9[335]<=lfb09b9;bl7edd9[321]<=ng93ce3;bl7edd9[298]<=oub3782;bl7edd9[290]<=ld6e292;bl7edd9[288]<=ip6f9da;bl7edd9[278]<=hbfc8e9;bl7edd9[276]<=zm173b;bl7edd9[263]<=wyb3db6;bl7edd9[251]<=mgb6c3e;bl7edd9[245]<=lq73099;bl7edd9[241]<=qt755c6;bl7edd9[240]<=lq7ced5;bl7edd9[232]<=rg47205;bl7edd9[225]<=dz6110a;bl7edd9[212]<=ayc4d57;bl7edd9[209]<=th454df;bl7edd9[203]<=qi2bc57;bl7edd9[194]<=dz6e32c;bl7edd9[193]<=jr1c457;bl7edd9[177]<=yzddb5;bl7edd9[175]<=and471;bl7edd9[172]<=fca74e1;bl7edd9[169]<=ps79094;bl7edd9[167]<=sh75b56;bl7edd9[160]<=wl90856;bl7edd9[149]<=nr55090;bl7edd9[145]<=fnf64cb;bl7edd9[144]<=mrdcd6f;bl7edd9[125]<=bnb0962;bl7edd9[122]<=kqce613;bl7edd9[120]<=xw5d5ed;bl7edd9[116]<=pfe6e08;bl7edd9[109]<=ip54b06;bl7edd9[104]<=kd5b24a;bl7edd9[97]<=dzf97da;bl7edd9[87]<=gq21e87;bl7edd9[84]<=gdabfd5;bl7edd9[83]<=zz16c26;bl7edd9[72]<=sh5441a;bl7edd9[61]<=ho79cc2;bl7edd9[60]<=gd2953a; -bl7edd9[58]<=gb5e468;bl7edd9[54]<=gq5871;bl7edd9[48]<=bl508a5;bl7edd9[42]<=ba1e4f6;bl7edd9[30]<=vk2f398;bl7edd9[21]<=ww781a8;bl7edd9[10]<=ip7f3bf;bl7edd9[5]<=uxbe6f6;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[1]};ie9813c<={blcd797>>1,nrf6ece[2]};dmc09e1<=nrf6ece[3];do4f0b<=nrf6ece[4];fp2785b<={oub3c7c>>1,nrf6ece[5]};kf3c2df<={jr9e3e0>>1,nrf6ece[6]};fae16fc<={hof1f06>>1,nrf6ece[7]};jeb7e3<={ir8f833>>1,nrf6ece[8]};en5bf1b<={rg7c19c>>1,nrf6ece[9]};xwdf8dd<={ice0ce2>>1,nrf6ece[10]};vvfc6eb<=nrf6ece[11];rte375e<=nrf6ece[12];xy1baf6<=nrf6ece[13];vvdd7b3<=nrf6ece[14];dmebd9f<={ou10f1c>>1,nrf6ece[15]};yx5ecfb<=nrf6ece[16];dzf67dd<=nrf6ece[17];aab3eef<={fne3804>>1,nrf6ece[18]};an9f778<=nrf6ece[19];nefbbc4<=nrf6ece[20];fndde22<={uk9f9>>1,nrf6ece[21]};ayef116<=nrf6ece[22];ui788b0<=nrf6ece[23];kqc4581<=nrf6ece[24];fp22c08<=nrf6ece[25];lf16047<=nrf6ece[26];vxb023e<={sh4bef4>>1,nrf6ece[27]};nt811f6<=nrf6ece[28];cb8fb6<=nrf6ece[29];zk47db5<=nrf6ece[30];sw3edaa<=nrf6ece[31];thf6d50<=nrf6ece[32];ukb6a86<=nrf6ece[33];fpb5430<=nrf6ece[34];phaa186<=nrf6ece[35];nr50c36<=nrf6ece[36];je861b6<={ww5c9fe>>1,nrf6ece[37]};zm30db3<=nrf6ece[38];vk86d9b<=nrf6ece[39];oh36cda<=nrf6ece[40];gqb66d4<=nrf6ece[41];ymb36a1<=nrf6ece[42];ph9b509<=nrf6ece[43];dmda84e<=nrf6ece[44];end -always@* begin bl7edd9[2047]<=zxf9af2[0];bl7edd9[2046]<=blcd797[0];bl7edd9[2044]<=pf6bcbe;bl7edd9[2040]<=qt5e5f7;bl7edd9[2032]<=oub3c7c[0];bl7edd9[2017]<=jr9e3e0[0];bl7edd9[1987]<=hof1f06[0];bl7edd9[1926]<=ir8f833[0];bl7edd9[1805]<=lf91727;bl7edd9[1804]<=rg7c19c[0];bl7edd9[1803]<=bn27e4b;bl7edd9[1761]<=qva4c8b;bl7edd9[1668]<=uif05d3;bl7edd9[1562]<=zz8b93f;bl7edd9[1560]<=ice0ce2[0];bl7edd9[1558]<=do3f25f;bl7edd9[1550]<=qi878e0;bl7edd9[1475]<=qv2645c;bl7edd9[1464]<=uide932;bl7edd9[1288]<=co82e98;bl7edd9[1076]<=ww5c9fe[0];bl7edd9[1072]<=fp6710;bl7edd9[1069]<=hbf92fb;bl7edd9[1052]<=an3c700;bl7edd9[1023]<=gbe_mode;bl7edd9[902]<=rv322e4;bl7edd9[901]<=je4fc9;bl7edd9[880]<=vif4991;bl7edd9[834]<=fafe0ba;bl7edd9[775]<=ou10f1c[0];bl7edd9[732]<=zkfbd26;bl7edd9[528]<=sj174c0;bl7edd9[450]<=uk9f9[0];bl7edd9[417]<=xy3fc17;bl7edd9[387]<=qte21e3;bl7edd9[366]<=vv5f7a4;bl7edd9[225]<=aye013f;bl7edd9[208]<=xl27f82;bl7edd9[193]<=do9c43c;bl7edd9[183]<=sh4bef4[0];bl7edd9[112]<=lf1c027;bl7edd9[104]<=hoe4ff0;bl7edd9[96]<=ux33887;bl7edd9[91]<=ipc97de;bl7edd9[56]<=fne3804[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[1]};dmc09e1<=nrf6ece[2];do4f0b<=nrf6ece[3];uk3b4aa<=nrf6ece[4];lqda551<=nrf6ece[5];zxd2a8a<={pfe37e6>>1,nrf6ece[6]};fp2785b<={oub3c7c>>1,nrf6ece[7]};kf3c2df<={jr9e3e0>>1,nrf6ece[8]};fae16fc<={hof1f06>>1,nrf6ece[9]};jeb7e3<={ir8f833>>1,nrf6ece[10]};en5bf1b<={rg7c19c>>1,nrf6ece[11]};xwdf8dd<={ice0ce2>>1,nrf6ece[12]};vvfc6eb<=nrf6ece[13];rte375e<=nrf6ece[14];xy1baf6<=nrf6ece[15];vvdd7b3<=nrf6ece[16];zk47db5<=nrf6ece[17];sw3edaa<=nrf6ece[18];rtdd291<=nrf6ece[19];nr50c36<=nrf6ece[20];je861b6<={ww5c9fe>>1,nrf6ece[21]};zm30db3<=nrf6ece[22];zz91ffa<=nrf6ece[23];cb8ffd6<=nrf6ece[24];cb8fb6<=nrf6ece[25];dmebd9f<={ou10f1c>>1,nrf6ece[26]};dzf67dd<=nrf6ece[27];yx5ecfb<=nrf6ece[28];uxb4845<=nrf6ece[29];ira422d<=nrf6ece[30];vxb023e<={sh4bef4>>1,nrf6ece[31]};lf16047<=nrf6ece[32];fp22c08<=nrf6ece[33];zz2da6f<=nrf6ece[34];me6d37e<=nrf6ece[35];rg69bf1<={nre371c>>1,nrf6ece[36]};by4df8a<=nrf6ece[37];sh6fc53<=nrf6ece[38];pf7e29d<=nrf6ece[39];xwf14ef<=nrf6ece[40];phaa186<=nrf6ece[41];ukb6a86<=nrf6ece[42];wy9dea9<=nrf6ece[43];vk86d9b<=nrf6ece[44];oh36cda<=nrf6ece[45];gqb66d4<=nrf6ece[46];ymb36a1<=nrf6ece[47];ph9b509<=nrf6ece[48];dmda84e<=nrf6ece[49];end -always@* begin bl7edd9[2047]<=blcd797[0];bl7edd9[2046]<=pf6bcbe;bl7edd9[2044]<=qt5e5f7;bl7edd9[2041]<=hdaff1b;bl7edd9[2034]<=en7f8df;bl7edd9[2021]<=pfe37e6[0];bl7edd9[2017]<=ww5c9fe[0];bl7edd9[1995]<=oub3c7c[0];bl7edd9[1986]<=hoe4ff0;bl7edd9[1943]<=jr9e3e0[0];bl7edd9[1925]<=ph38769;bl7edd9[1908]<=hbf92fb;bl7edd9[1864]<=ri1b8e6;bl7edd9[1855]<=qte21e3;bl7edd9[1838]<=hof1f06[0];bl7edd9[1803]<=uvc3b4e;bl7edd9[1769]<=zma78dc;bl7edd9[1680]<=yxdc733;bl7edd9[1662]<=uide932;bl7edd9[1628]<=ir8f833[0];bl7edd9[1559]<=zkfbd26;bl7edd9[1501]<=sh4bef4[0];bl7edd9[1490]<=oh3c6e3;bl7edd9[1487]<=ux33887;bl7edd9[1312]<=dze399d;bl7edd9[1276]<=vif4991;bl7edd9[1209]<=rg7c19c[0];bl7edd9[1155]<=lf91727;bl7edd9[1070]<=ou10f1c[0];bl7edd9[1048]<=xl27f82;bl7edd9[1023]<=gbe_mode;bl7edd9[1008]<=zz8b93f;bl7edd9[954]<=ipc97de;bl7edd9[932]<=nre371c[0];bl7edd9[927]<=do9c43c;bl7edd9[791]<=sj174c0;bl7edd9[750]<=epa4aa7;bl7edd9[743]<=fp6710;bl7edd9[577]<=vx1ccef;bl7edd9[524]<=ym9dfb4;bl7edd9[504]<=ri89c38;bl7edd9[395]<=co82e98;bl7edd9[375]<=nr74954;bl7edd9[371]<=ice0ce2[0];bl7edd9[262]<=qv2645c;bl7edd9[197]<=uif05d3;bl7edd9[187]<=qi878e0;bl7edd9[98]<=fafe0ba;bl7edd9[93]<=an3c700;bl7edd9[49]<=xy3fc17;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[2]};dmc09e1<=nrf6ece[3];do4f0b<=nrf6ece[4];kf9af7f<={aa90a>>1,nrf6ece[5]};fp2785b<={oub3c7c>>1,nrf6ece[6]};kf3c2df<={jr9e3e0>>1,nrf6ece[7]};fae16fc<={hof1f06>>1,nrf6ece[8]};jeb7e3<={ir8f833>>1,nrf6ece[9]};en5bf1b<={rg7c19c>>1,nrf6ece[10]};xwdf8dd<={ice0ce2>>1,nrf6ece[11]};vvfc6eb<=nrf6ece[12];rte375e<=nrf6ece[13];xy1baf6<=nrf6ece[14];vvdd7b3<=nrf6ece[15];je861b6<={ww5c9fe>>1,nrf6ece[16]};zm30db3<=nrf6ece[17];zz91ffa<=nrf6ece[18];cb8fb6<=nrf6ece[19];dmebd9f<={ou10f1c>>1,nrf6ece[20]};dzf67dd<=nrf6ece[21];yx5ecfb<=nrf6ece[22];vk86d9b<=nrf6ece[23];oh36cda<=nrf6ece[24];gqb66d4<=nrf6ece[25];ymb36a1<=nrf6ece[26];ph9b509<=nrf6ece[27];dmda84e<=nrf6ece[28];end -always@* begin bl7edd9[2047]<=ay534c0;bl7edd9[2046]<=blcd797[0];bl7edd9[2044]<=pf6bcbe;bl7edd9[2040]<=qt5e5f7;bl7edd9[2032]<=aa90a[0];bl7edd9[2017]<=oub3c7c[0];bl7edd9[1987]<=jr9e3e0[0];bl7edd9[1926]<=hof1f06[0];bl7edd9[1804]<=ir8f833[0];bl7edd9[1803]<=xl27f82;bl7edd9[1560]<=rg7c19c[0];bl7edd9[1558]<=xy3fc17;bl7edd9[1550]<=ww5c9fe[0];bl7edd9[1072]<=ice0ce2[0];bl7edd9[1069]<=fafe0ba;bl7edd9[1052]<=hoe4ff0;bl7edd9[1023]<=gbe_mode;bl7edd9[901]<=qi878e0;bl7edd9[775]<=qte21e3;bl7edd9[450]<=an3c700;bl7edd9[387]<=do9c43c;bl7edd9[366]<=sj174c0;bl7edd9[225]<=ou10f1c[0];bl7edd9[193]<=ux33887;bl7edd9[183]<=co82e98;bl7edd9[112]<=zkfbd26;bl7edd9[96]<=fp6710;bl7edd9[91]<=uif05d3;bl7edd9[56]<=ph38769;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[2]};dmc09e1<=nrf6ece[3];do4f0b<=nrf6ece[4];uk3b4aa<=nrf6ece[5];lqda551<=nrf6ece[6];kf9af7f<={aa90a>>1,nrf6ece[7]};fp2785b<={oub3c7c>>1,nrf6ece[8]};kf3c2df<={jr9e3e0>>1,nrf6ece[9]};fae16fc<={hof1f06>>1,nrf6ece[10]};jeb7e3<={ir8f833>>1,nrf6ece[11]};en5bf1b<={rg7c19c>>1,nrf6ece[12]};xwdf8dd<={ice0ce2>>1,nrf6ece[13]};vvfc6eb<=nrf6ece[14];rte375e<=nrf6ece[15];xy1baf6<=nrf6ece[16];vvdd7b3<=nrf6ece[17];je861b6<={ww5c9fe>>1,nrf6ece[18]};zm30db3<=nrf6ece[19];zz91ffa<=nrf6ece[20];cb8fb6<=nrf6ece[21];dmebd9f<={ou10f1c>>1,nrf6ece[22]};dzf67dd<=nrf6ece[23];yx5ecfb<=nrf6ece[24];uxb4845<=nrf6ece[25];ira422d<=nrf6ece[26];vk86d9b<=nrf6ece[27];oh36cda<=nrf6ece[28];gqb66d4<=nrf6ece[29];ymb36a1<=nrf6ece[30];ph9b509<=nrf6ece[31];dmda84e<=nrf6ece[32];end -always@* begin bl7edd9[2047]<=ay534c0;bl7edd9[2046]<=blcd797[0];bl7edd9[2044]<=pf6bcbe;bl7edd9[2041]<=qt5e5f7;bl7edd9[2035]<=hdaff1b;bl7edd9[2022]<=en7f8df;bl7edd9[1996]<=aa90a[0];bl7edd9[1945]<=oub3c7c[0];bl7edd9[1922]<=nr74954;bl7edd9[1842]<=jr9e3e0[0];bl7edd9[1797]<=epa4aa7;bl7edd9[1776]<=ou10f1c[0];bl7edd9[1637]<=hof1f06[0];bl7edd9[1622]<=fp6710;bl7edd9[1546]<=xl27f82;bl7edd9[1504]<=an3c700;bl7edd9[1468]<=ph38769;bl7edd9[1391]<=ww5c9fe[0];bl7edd9[1226]<=ir8f833[0];bl7edd9[1197]<=ux33887;bl7edd9[1044]<=xy3fc17;bl7edd9[1023]<=gbe_mode;bl7edd9[961]<=qi878e0;bl7edd9[888]<=zkfbd26;bl7edd9[811]<=ice0ce2[0];bl7edd9[734]<=hoe4ff0;bl7edd9[695]<=qte21e3;bl7edd9[405]<=rg7c19c[0];bl7edd9[347]<=do9c43c;bl7edd9[328]<=sj174c0;bl7edd9[164]<=co82e98;bl7edd9[82]<=uif05d3;bl7edd9[41]<=fafe0ba;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[5]};lf22e73<=nrf6ece[6];gd1739f<=nrf6ece[7];ecb9cfc<=nrf6ece[8];mece7e1<=nrf6ece[9];by73f09<=nrf6ece[10];ir9f84a<={qi82738>>1,nrf6ece[11]};fnfc255<={fp139c1>>1,nrf6ece[12]};rge12ae<={ba9ce0f>>1,nrf6ece[13]};db9573<={wje707a>>1,nrf6ece[14]};fn4ab9e<={nt383d4>>1,nrf6ece[15]};vv55cf6<=nrf6ece[16];wlae7b6<=nrf6ece[17];ps73db4<=nrf6ece[18];rv9eda2<=nrf6ece[19];zxf6d17<=nrf6ece[20];qib68be<=nrf6ece[21];yzb45f0<={fpbf92d>>1,nrf6ece[22]};jea2f84<=nrf6ece[23];qv17c23<={dme4b77>>1,nrf6ece[24]};mtbe11d<=nrf6ece[25];ykf08ed<={jr2ddd2>>1,nrf6ece[26]};ph84769<={rt6ee96>>1,nrf6ece[27]};sj23b4e<={ea774b7>>1,nrf6ece[28]};kf1da75<={thd2dcf>>1,nrf6ece[29]};qted3ac<={je96e7f>>1,nrf6ece[30]};xw69d65<={hqb73fb>>1,nrf6ece[31]};yx4eb2a<={gqb9fdb>>1,nrf6ece[32]};qt75954<={dmcfed9>>1,nrf6ece[33]};aaacaa5<={en7f6ca>>1,nrf6ece[34]};wj65528<=nrf6ece[35];pu2a945<=nrf6ece[36];qt54a2b<=nrf6ece[37];jra515c<=nrf6ece[38];rv28ae7<=nrf6ece[39];dz4573e<=nrf6ece[40];ym2b9f6<=nrf6ece[41];ic5cfb1<=nrf6ece[42];ale7d88<=nrf6ece[43];uk3ec45<=nrf6ece[44];jpf6228<=nrf6ece[45];yzb1147<=nrf6ece[46];ie88a3c<=nrf6ece[47];xj451e1<={rtd8916>>1,nrf6ece[48]};fp28f0e<=nrf6ece[49];jc47876<=nrf6ece[50];wl3c3b2<=nrf6ece[51];xwe1d94<=nrf6ece[52];tweca2<=nrf6ece[53];by76512<={cbb13f9>>1,nrf6ece[54]};lsb2893<=nrf6ece[55];lf9449a<=nrf6ece[56];xya24d7<=nrf6ece[57];ux126ba<=nrf6ece[58];ng935d4<={ofcc7af>>1,nrf6ece[59]};kf9aea2<=nrf6ece[60];vvd7515<=nrf6ece[61];xlba8ae<=nrf6ece[62];ead4576<=nrf6ece[63];twa2bb1<=nrf6ece[64];qi15d8b<={pfe367a>>1,nrf6ece[65]};iraec58<=nrf6ece[66];lq762c5<=nrf6ece[67];ohb162b<={sh7aca3>>1,nrf6ece[68]};end -always@* begin bl7edd9[2047]<=sgmii_mode;bl7edd9[2046]<=mr_main_reset;bl7edd9[2044]<=mr_restart_an;bl7edd9[2040]<=mr_an_enable;bl7edd9[2033]<=mr_adv_ability[1];bl7edd9[2019]<=ip70450;bl7edd9[1999]<=godb2ab;bl7edd9[1991]<=sj8a10b;bl7edd9[1981]<=lf22d89;bl7edd9[1958]<=bl4fe63;bl7edd9[1950]<=tucaac5;bl7edd9[1947]<=ho57893;bl7edd9[1934]<=zx5085d;bl7edd9[1914]<=hd16c4f;bl7edd9[1892]<=ene2fe4;bl7edd9[1868]<=of7f31e;bl7edd9[1852]<=dz5562a;bl7edd9[1851]<=nt383d4[0];bl7edd9[1847]<=qibc49b;bl7edd9[1820]<=db842ee;bl7edd9[1783]<=rtd8916[1];bl7edd9[1780]<=qib627f;bl7edd9[1737]<=cb17f25;bl7edd9[1689]<=rtf98f5;bl7edd9[1657]<=mtab157;bl7edd9[1654]<=cmc1ea6;bl7edd9[1647]<=cze24d8;bl7edd9[1610]<=dme4b77[0];bl7edd9[1608]<=lq7c6cf;bl7edd9[1593]<=ym21776;bl7edd9[1523]<=dmcfed9[0];bl7edd9[1519]<=suc48b6;bl7edd9[1513]<=cbb13f9[0];bl7edd9[1426]<=fpbf92d[0];bl7edd9[1404]<=hqb73fb[0];bl7edd9[1330]<=ofcc7af[1];bl7edd9[1267]<=ne58abc;bl7edd9[1260]<=ld40f17;bl7edd9[1246]<=ir126c4;bl7edd9[1225]<=vk1ebe3;bl7edd9[1199]<=ea774b7[0];bl7edd9[1173]<=pu25bba;bl7edd9[1169]<=pfe367a[0];bl7edd9[1163]<=sh7aca3[1];bl7edd9[1139]<=qi82738[0];bl7edd9[1023]<=gbe_mode;bl7edd9[999]<=en7f6ca[0];bl7edd9[990]<=sw245b1;bl7edd9[979]<=pu89fcc;bl7edd9[973]<=ba2af12;bl7edd9[946]<=an3c5fc;bl7edd9[925]<=wje707a[0];bl7edd9[891]<=xl9b122;bl7edd9[805]<=thfc96e;bl7edd9[804]<=vxaf8d9;bl7edd9[761]<=gqb9fdb[0];bl7edd9[702]<=je96e7f[0];bl7edd9[612]<=ne63d7c;bl7edd9[599]<=rt6ee96[0];bl7edd9[581]<=bycf594;bl7edd9[486]<=nec55e2;bl7edd9[473]<=qv78bf;bl7edd9[462]<=ba9ce0f[0];bl7edd9[445]<=vk93624;bl7edd9[402]<=cmf5f1b;bl7edd9[351]<=thd2dcf[0];bl7edd9[299]<=jr2ddd2[0];bl7edd9[290]<=hq1b3d6;bl7edd9[231]<=fp139c1[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[1]};czdc8a0<=nrf6ece[2];dme4504<=nrf6ece[3];gd1739f<=nrf6ece[4];hq1411f<=nrf6ece[5];tja08fb<={jceec52>>1,nrf6ece[6]};ng47de<=nrf6ece[7];cb23ef2<={th7b8fa>>1,nrf6ece[8]};ks1f795<={aldc7d6>>1,nrf6ece[9]};psfbca8<={the3eb5>>1,nrf6ece[10]};sude542<={qi1f5af>>1,nrf6ece[11]};czf2a10<={kqfad78>>1,nrf6ece[12]};qv95084<=nrf6ece[13];lsa8425<=nrf6ece[14];jc4212b<=nrf6ece[15];ym1095b<=nrf6ece[16];vx84ad8<=nrf6ece[17];ri256c7<=nrf6ece[18];aa2b63b<=nrf6ece[19];wj5b1d8<=nrf6ece[20];jpd8ec4<=nrf6ece[21];jpc7626<=nrf6ece[22];ym3b137<=nrf6ece[23];thd89b9<=nrf6ece[24];icc4dce<=nrf6ece[25];sj26e71<=nrf6ece[26];lf3738d<=nrf6ece[27];mgb9c6f<=nrf6ece[28];ykce379<=nrf6ece[29];vv71bc9<=nrf6ece[30];ou8de4f<=nrf6ece[31];sh6f279<=nrf6ece[32];jc793cc<=nrf6ece[33];yxc9e62<=nrf6ece[34];vv4f315<=nrf6ece[35];vi798af<=nrf6ece[36];uvcc57b<={ohd46e>>1,nrf6ece[37]};ic62bdc<={of6a374>>1,nrf6ece[38]};gq15ee1<=nrf6ece[39];hdaf708<=nrf6ece[40];bl7b846<=nrf6ece[41];mrdc236<=nrf6ece[42];jce11b5<=nrf6ece[43];qv8dab<=nrf6ece[44];go46d5d<=nrf6ece[45];yz36ae8<=nrf6ece[46];lfb5744<=nrf6ece[47];kfaba26<=nrf6ece[48];by5d135<=nrf6ece[49];ale89ab<=nrf6ece[50];wj44d5c<=nrf6ece[51];an26ae5<=nrf6ece[52];vk3572d<={sj2673b>>1,nrf6ece[53]};mtab96a<={gd339dc>>1,nrf6ece[54]};qg5cb55<={vk9cee4>>1,nrf6ece[55]};end -always@* begin bl7edd9[2047]<=rx_data[0];bl7edd9[2046]<=rx_kcntl;bl7edd9[2044]<=baa25a8;bl7edd9[2040]<=sj8a10b;bl7edd9[2032]<=rx_even;bl7edd9[2016]<=jceec52[0];bl7edd9[1985]<=xy9922f;bl7edd9[1922]<=th7b8fa[0];bl7edd9[1867]<=tw2fc19;bl7edd9[1804]<=sh7f840;bl7edd9[1797]<=aldc7d6[0];bl7edd9[1761]<=mg243fc;bl7edd9[1686]<=xj7e0cb;bl7edd9[1623]<=gd339dc[0];bl7edd9[1561]<=thfc204;bl7edd9[1558]<=ks1f1a4;bl7edd9[1547]<=the3eb5[0];bl7edd9[1542]<=th61a8d;bl7edd9[1490]<=fac0bf0;bl7edd9[1475]<=mg21fe1;bl7edd9[1413]<=wjf87c6;bl7edd9[1409]<=ec586a;bl7edd9[1324]<=icf065f;bl7edd9[1200]<=rv197c3;bl7edd9[1199]<=vk9cee4[1];bl7edd9[1074]<=zke1026;bl7edd9[1068]<=qtf8d20;bl7edd9[1047]<=qi1f5af[0];bl7edd9[1037]<=ohd46e[0];bl7edd9[1023]<=mr_main_reset;bl7edd9[933]<=sw5f83;bl7edd9[902]<=ieff08;bl7edd9[880]<=gda487f;bl7edd9[811]<=sj2673b[0];bl7edd9[779]<=yxc3e34;bl7edd9[771]<=mt2c351;bl7edd9[745]<=kq7817e;bl7edd9[706]<=bl5f0f8;bl7edd9[704]<=fc20b0d;bl7edd9[600]<=ls832f8;bl7edd9[440]<=xj7490f;bl7edd9[405]<=vk4ce7;bl7edd9[372]<=phaf02f;bl7edd9[353]<=wwcbe1f;bl7edd9[352]<=yza4161;bl7edd9[220]<=th6e921;bl7edd9[202]<=pf4099c;bl7edd9[186]<=lfb5e05;bl7edd9[176]<=wy3482c;bl7edd9[110]<=ou8dd24;bl7edd9[101]<=oh8133;bl7edd9[93]<=gbd6bc0;bl7edd9[88]<=gbc6905;bl7edd9[55]<=en51ba4;bl7edd9[46]<=kqfad78[0];bl7edd9[27]<=of6a374[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[2]};czdc8a0<=nrf6ece[3];dme4504<=nrf6ece[4];blf6706<={oh26038>>1,nrf6ece[5]};ksb3837<={zm301c4>>1,nrf6ece[6]};ba9c1b8<={sj80e22>>1,nrf6ece[7]};yke0dc3<=nrf6ece[8];db6e18<=nrf6ece[9];bn370c6<=nrf6ece[10];lsb8637<=nrf6ece[11];ofc31ba<=nrf6ece[12];oh18dd5<=nrf6ece[13];wjc6eac<=nrf6ece[14];xl37564<=nrf6ece[15];hdbab27<=nrf6ece[16];hod593e<={zz3850f>>1,nrf6ece[17]};end -always@* begin bl7edd9[2047]<=signal_detect;bl7edd9[2046]<=rx_data[0];bl7edd9[2044]<=rx_kcntl;bl7edd9[2040]<=baa25a8;bl7edd9[2033]<=oh26038[0];bl7edd9[2018]<=zm301c4[0];bl7edd9[1988]<=sj80e22[0];bl7edd9[1929]<=ux7115;bl7edd9[1811]<=lf388ad;bl7edd9[1574]<=qgc456f;bl7edd9[1247]<=cm78e14;bl7edd9[1101]<=bn22b78;bl7edd9[1023]<=mr_main_reset;bl7edd9[894]<=zz3850f[1];bl7edd9[623]<=of6f1c2;bl7edd9[447]<=zxc70a1;bl7edd9[311]<=zmade38;bl7edd9[155]<=co15bc7;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[3]};hq9c6d4<={fc83c7c>>1,nrf6ece[4]};xje36a3<=nrf6ece[5];tw1b51e<=nrf6ece[6];jcda8f2<={al41dd5>>1,nrf6ece[7]};kqd4793<={ip51c9c>>1,nrf6ece[8]};oua3c99<={xl8e4e4>>1,nrf6ece[9]};do1e4c9<=nrf6ece[10];mrf264a<=nrf6ece[11];vk93255<={ba9c9cb>>1,nrf6ece[12]};vk992aa<=nrf6ece[13];enc9553<=nrf6ece[14];nr4aa9c<={gd39696>>1,nrf6ece[15]};hb554e6<=nrf6ece[16];tjaa737<=nrf6ece[17];qg539be<=nrf6ece[18];ls9cdf1<=nrf6ece[19];zxe6f8a<=nrf6ece[20];ph37c57<=nrf6ece[21];qvbe2be<=nrf6ece[22];faf15f5<=nrf6ece[23];oh8afaa<=nrf6ece[24];cb8fb6<=nrf6ece[25];vxb023e<={sh4bef4>>1,nrf6ece[26]};kqf551c<=nrf6ece[27];fp22c08<=nrf6ece[28];yx54707<=nrf6ece[29];wya383d<=nrf6ece[30];rv1c1e9<=nrf6ece[31];wwe0f4f<=nrf6ece[32];nt811f6<=nrf6ece[33];vx3d3c4<=nrf6ece[34];rte9e26<=nrf6ece[35];dz4f136<=nrf6ece[36];go789b7<=nrf6ece[37];cmc4db9<=nrf6ece[38];wl26dc9<=nrf6ece[39];qv36e4d<=nrf6ece[40];xyb726c<={ykeaf80>>1,nrf6ece[41]};kf3c2df<={jr9e3e0>>1,nrf6ece[42]};fae16fc<={hof1f06>>1,nrf6ece[43]};lq4d8c5<={suf005d>>1,nrf6ece[44]};tu6c62b<={oh802e8>>1,nrf6ece[45]};vi6315b<=nrf6ece[46];ep18ada<=nrf6ece[47];tuc56d4<=nrf6ece[48];wy2b6a2<=nrf6ece[49];vvfc6eb<=nrf6ece[50];lqda884<=nrf6ece[51];ayd4423<=nrf6ece[52];nga2119<=nrf6ece[53];qi108ca<=nrf6ece[54];jr84650<=nrf6ece[55];wl23286<=nrf6ece[56];nt19434<={gq34695>>1,nrf6ece[57]};rgca1a7<={uka34a8>>1,nrf6ece[58]};vk86d9b<=nrf6ece[59];oh36cda<=nrf6ece[60];qi34ef2<={kf95007>>1,nrf6ece[61]};baa7791<={pua803d>>1,nrf6ece[62]};ym3bc8a<=nrf6ece[63];mede450<=nrf6ece[64];gbf2280<=nrf6ece[65];bn91405<=nrf6ece[66];wl8a02f<={zkebc66>>1,nrf6ece[67]};fn5017d<={sh5e333>>1,nrf6ece[68]};end -always@* begin bl7edd9[2047]<=hbe6383;bl7edd9[2046]<=gbe_mode;bl7edd9[2044]<=operational_rate[0];bl7edd9[2040]<=fc83c7c[0];bl7edd9[2032]<=pu1e3e2;bl7edd9[2018]<=jr9e3e0[0];bl7edd9[2017]<=dmf1f12;bl7edd9[1989]<=hof1f06[0];bl7edd9[1987]<=al41dd5[0];bl7edd9[1931]<=suf005d[0];bl7edd9[1927]<=ip51c9c[0];bl7edd9[1865]<=ykcb4b4;bl7edd9[1859]<=vv5f7a4;bl7edd9[1844]<=ls93934;bl7edd9[1815]<=oh802e8[0];bl7edd9[1806]<=xl8e4e4[0];bl7edd9[1682]<=vv5a5a1;bl7edd9[1674]<=uka34a8[0];bl7edd9[1671]<=qgeaaec;bl7edd9[1640]<=xy9c9a3;bl7edd9[1582]<=je1744;bl7edd9[1565]<=kq72727;bl7edd9[1488]<=vk93f55;bl7edd9[1485]<=zz224e4;bl7edd9[1326]<=sh4bef4[0];bl7edd9[1317]<=bld2d0e;bl7edd9[1300]<=xl27f82;bl7edd9[1297]<=cb7af1;bl7edd9[1295]<=zx55761;bl7edd9[1233]<=pse4d1a;bl7edd9[1210]<=hbf92fb;bl7edd9[1189]<=kq77722;bl7edd9[1172]<=anb43bb;bl7edd9[1116]<=vkba22;bl7edd9[1105]<=kf95007[0];bl7edd9[1092]<=zkebc66[1];bl7edd9[1087]<=vi5d87d;bl7edd9[1082]<=fc93939;bl7edd9[1023]<=tu76293;bl7edd9[1009]<=ykeaf80[0];bl7edd9[932]<=gd39696[0];bl7edd9[929]<=an9faab;bl7edd9[922]<=kf12726;bl7edd9[837]<=gq34695[0];bl7edd9[744]<=mrf27ea;bl7edd9[742]<=fp6710;bl7edd9[663]<=zkfbd26;bl7edd9[648]<=gqf5e;bl7edd9[605]<=zx64793;bl7edd9[594]<=rieee4;bl7edd9[586]<=vk96877;bl7edd9[552]<=xy3fc17;bl7edd9[546]<=tj3d78c;bl7edd9[543]<=gdabb0f;bl7edd9[504]<=ksfabe;bl7edd9[466]<=fp272d2;bl7edd9[418]<=ir268d2;bl7edd9[372]<=do1e4fd;bl7edd9[371]<=yxe8893;bl7edd9[331]<=gdbb911;bl7edd9[324]<=rt401eb;bl7edd9[297]<=ana1ddc;bl7edd9[252]<=jp61f57;bl7edd9[233]<=vie4e5a;bl7edd9[185]<=rg5d112;bl7edd9[162]<=pua803d[0];bl7edd9[136]<=sh5e333[1];bl7edd9[126]<=blec3ea;bl7edd9[116]<=ba9c9cb[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[0]};xje36a3<=nrf6ece[1];tw1b51e<=nrf6ece[2];jcda8f2<={al41dd5>>1,nrf6ece[3]};kqd4793<={ip51c9c>>1,nrf6ece[4]};oua3c99<={xl8e4e4>>1,nrf6ece[5]};do1e4c9<=nrf6ece[6];mrf264a<=nrf6ece[7];vk93255<={ba9c9cb>>1,nrf6ece[8]};vk992aa<=nrf6ece[9];enc9553<=nrf6ece[10];nr4aa9c<={gd39696>>1,nrf6ece[11]};hb554e6<=nrf6ece[12];tjaa737<=nrf6ece[13];qg539be<=nrf6ece[14];ls9cdf1<=nrf6ece[15];zxe6f8a<=nrf6ece[16];ph37c57<=nrf6ece[17];qvbe2be<=nrf6ece[18];faf15f5<=nrf6ece[19];oh8afaa<=nrf6ece[20];cb8fb6<=nrf6ece[21];vxb023e<={sh4bef4>>1,nrf6ece[22]};kqf551c<=nrf6ece[23];fp22c08<=nrf6ece[24];yx54707<=nrf6ece[25];wya383d<=nrf6ece[26];rv1c1e9<=nrf6ece[27];wwe0f4f<=nrf6ece[28];nt811f6<=nrf6ece[29];vx3d3c4<=nrf6ece[30];rte9e26<=nrf6ece[31];dz4f136<=nrf6ece[32];go789b7<=nrf6ece[33];cmc4db9<=nrf6ece[34];wl26dc9<=nrf6ece[35];qv36e4d<=nrf6ece[36];xyb726c<={ykeaf80>>1,nrf6ece[37]};wl8a02f<={zkebc66>>1,nrf6ece[38]};fn5017d<={sh5e333>>1,nrf6ece[39]};end -always@* begin bl7edd9[2047]<=pu1e3e2;bl7edd9[2046]<=dmf1f12;bl7edd9[2044]<=al41dd5[0];bl7edd9[2040]<=ip51c9c[0];bl7edd9[2033]<=xl8e4e4[0];bl7edd9[2019]<=kq72727;bl7edd9[1991]<=fc93939;bl7edd9[1934]<=ba9c9cb[0];bl7edd9[1898]<=vk96877;bl7edd9[1821]<=vie4e5a;bl7edd9[1749]<=anb43bb;bl7edd9[1707]<=kq77722;bl7edd9[1666]<=an9faab;bl7edd9[1595]<=fp272d2;bl7edd9[1450]<=ana1ddc;bl7edd9[1440]<=mrf27ea;bl7edd9[1384]<=hbf92fb;bl7edd9[1370]<=sh4bef4[0];bl7edd9[1366]<=gdbb911;bl7edd9[1284]<=vv5f7a4;bl7edd9[1142]<=gd39696[0];bl7edd9[1125]<=ykeaf80[0];bl7edd9[1041]<=zx55761;bl7edd9[1023]<=fc83c7c[0];bl7edd9[949]<=bld2d0e;bl7edd9[853]<=rieee4;bl7edd9[833]<=vk93f55;bl7edd9[720]<=do1e4fd;bl7edd9[692]<=zx64793;bl7edd9[685]<=zkfbd26;bl7edd9[562]<=ksfabe;bl7edd9[520]<=qgeaaec;bl7edd9[474]<=vv5a5a1;bl7edd9[407]<=sh5e333[1];bl7edd9[281]<=jp61f57;bl7edd9[237]<=ykcb4b4;bl7edd9[203]<=zkebc66[1];bl7edd9[140]<=blec3ea;bl7edd9[70]<=vi5d87d;bl7edd9[35]<=gdabb0f;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[0]};xje36a3<=nrf6ece[1];tw1b51e<=nrf6ece[2];oua3c99<={xl8e4e4>>1,nrf6ece[3]};do1e4c9<=nrf6ece[4];mrf264a<=nrf6ece[5];oh8afaa<=nrf6ece[6];cb8fb6<=nrf6ece[7];vxb023e<={sh4bef4>>1,nrf6ece[8]};kqf551c<=nrf6ece[9];fp22c08<=nrf6ece[10];yx54707<=nrf6ece[11];wya383d<=nrf6ece[12];rv1c1e9<=nrf6ece[13];nt811f6<=nrf6ece[14];rte9e26<=nrf6ece[15];dz4f136<=nrf6ece[16];go789b7<=nrf6ece[17];cmc4db9<=nrf6ece[18];wl26dc9<=nrf6ece[19];qv36e4d<=nrf6ece[20];end -always@* begin bl7edd9[2047]<=pu1e3e2;bl7edd9[2046]<=dmf1f12;bl7edd9[2044]<=xl8e4e4[0];bl7edd9[2040]<=kq72727;bl7edd9[2033]<=fc93939;bl7edd9[2019]<=gdbb911;bl7edd9[1990]<=zkfbd26;bl7edd9[1939]<=blec3ea;bl7edd9[1933]<=sh4bef4[0];bl7edd9[1831]<=jp61f57;bl7edd9[1819]<=zx64793;bl7edd9[1778]<=zx55761;bl7edd9[1615]<=ksfabe;bl7edd9[1591]<=hbf92fb;bl7edd9[1508]<=gdabb0f;bl7edd9[1135]<=do1e4fd;bl7edd9[1023]<=fc83c7c[0];bl7edd9[969]<=vi5d87d;bl7edd9[889]<=vv5f7a4;bl7edd9[444]<=vk93f55;bl7edd9[222]<=mrf27ea;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[3]};ic53c12<={pf55c79>>1,nrf6ece[4]};bn9e091<=nrf6ece[5];uif048e<=nrf6ece[6];co82470<={uice9eb>>1,nrf6ece[7]};wl12381<=nrf6ece[8];fp91c0c<=nrf6ece[9];ph84769<={rt6ee96>>1,nrf6ece[10]};sj23b4e<={ea774b7>>1,nrf6ece[11]};ykf08ed<={jr2ddd2>>1,nrf6ece[12]};ntcde7<=nrf6ece[13];jc66f3f<=nrf6ece[14];rv379fb<=nrf6ece[15];ecbcfde<={gbf25c0>>1,nrf6ece[16]};ofe7ef1<=nrf6ece[17];do3f78d<=nrf6ece[18];fafbc6b<=nrf6ece[19];ohb162b<={sh7aca3>>1,nrf6ece[20]};end -always@* begin bl7edd9[2047]<=tx_en;bl7edd9[2046]<=tx_er;bl7edd9[2044]<=sueab8f[0];bl7edd9[2040]<=pf55c79[0];bl7edd9[2032]<=anae3ce;bl7edd9[2017]<=gd8f3a7;bl7edd9[1987]<=uice9eb[0];bl7edd9[1927]<=ld74f58;bl7edd9[1865]<=gbf25c0[0];bl7edd9[1806]<=nga7ac7;bl7edd9[1682]<=ym92e05;bl7edd9[1565]<=rt6ee96[0];bl7edd9[1317]<=wy97029;bl7edd9[1172]<=sh7aca3[1];bl7edd9[1082]<=ea774b7[0];bl7edd9[1023]<=mr_main_reset;bl7edd9[932]<=mede4b8;bl7edd9[586]<=dm484c5;bl7edd9[466]<=ym3bc97;bl7edd9[233]<=jpc7792;bl7edd9[116]<=jr2ddd2[0];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[1]};fc35dd0<=nrf6ece[2];sjaee83<=nrf6ece[3];me7741d<=nrf6ece[4];xlba0e9<=nrf6ece[5];jcd074f<=nrf6ece[6];hq83a7b<={blf6935>>1,nrf6ece[7]};gd1d3da<=nrf6ece[8];pfe9ed5<=nrf6ece[9];nr4f6ae<={qv26bac>>1,nrf6ece[10]};ld7b577<={tw35d65>>1,nrf6ece[11]};rgdabbf<={anaeb2b>>1,nrf6ece[12]};xwd5dfb<={al7595d>>1,nrf6ece[13]};mtaefda<=nrf6ece[14];qg77ed5<=nrf6ece[15];zzbf6a8<=nrf6ece[16];zkfb547<=nrf6ece[17];zkdaa3b<=nrf6ece[18];jcd51db<=nrf6ece[19];hqa8edb<=nrf6ece[20];zk476da<=nrf6ece[21];wy3b6d3<=nrf6ece[22];aydb699<=nrf6ece[23];end -always@* begin bl7edd9[2047]<=vv74a74[0];bl7edd9[2046]<=rva53a7;bl7edd9[2044]<=cb29d3f;bl7edd9[2040]<=mr4e9fc;bl7edd9[2032]<=zx74fe4;bl7edd9[2016]<=jpfc90a;bl7edd9[1985]<=blf6935[0];bl7edd9[1922]<=irb49ae;bl7edd9[1796]<=qva4d75;bl7edd9[1544]<=qv26bac[6];bl7edd9[1302]<=cb29546;bl7edd9[1115]<=nr551ae;bl7edd9[1105]<=rg5da29;bl7edd9[1041]<=tw35d65[0];bl7edd9[1023]<=hq3f921;bl7edd9[651]<=nr452a8;bl7edd9[557]<=rt4aa35;bl7edd9[552]<=mg2bb45;bl7edd9[325]<=cm68a55;bl7edd9[276]<=mr65768;bl7edd9[162]<=uved14a;bl7edd9[138]<=coacaed;bl7edd9[69]<=al7595d[0];bl7edd9[34]<=anaeb2b[6];end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43>1,nrf6ece[4]};qi3b914<={rx_data>>1,nrf6ece[5]};czdc8a0<=nrf6ece[6];hq1411f<=nrf6ece[7];kq7d70f<=nrf6ece[8];faeb878<=nrf6ece[9];me5c3c3<=nrf6ece[10];jce1e19<={tx_d>>1,nrf6ece[11]};wy98a9e<=nrf6ece[12];hoc54f0<=nrf6ece[13];zz1c8b9<=nrf6ece[14];db94722<=nrf6ece[15];ksa3917<=nrf6ece[16];tja08fb<={jceec52>>1,nrf6ece[17]};mg88bdd<={fcbbb1>>1,nrf6ece[18]};dz45ee9<={tu5dd8a>>1,nrf6ece[19]};dme4504<=nrf6ece[20];vv7ba7a<={jebda89>>1,nrf6ece[21]};rtdd3d6<=nrf6ece[22];zxe9eb7<=nrf6ece[23];pf4f5be<=nrf6ece[24];al7adf7<=nrf6ece[25];end6fbc<=nrf6ece[26];twb7de5<=nrf6ece[27];wlbef2a<=nrf6ece[28];byf199c<=nrf6ece[29];vk86d9b<=nrf6ece[30];oh36cda<=nrf6ece[31];gqb66d4<=nrf6ece[32];ymb36a1<=nrf6ece[33];ph9b509<=nrf6ece[34];dmda84e<=nrf6ece[35];nt9729<=nrf6ece[36];gb4b94e<=nrf6ece[37];ay5ca74<=nrf6ece[38];mee53a0<=nrf6ece[39];oh29d01<=nrf6ece[40];en4e80c<=nrf6ece[41];nr74064<=nrf6ece[42];bna0326<=nrf6ece[43];do1937<=nrf6ece[44];fpc9bb<=nrf6ece[45];zx64ddf<=nrf6ece[46];kf26efe<={ba2a2bb>>1,nrf6ece[47]};zz377f5<=nrf6ece[48];wlbbfaf<=nrf6ece[49];xwdfd7c<={jc576ac>>1,nrf6ece[50]};tufebe3<=nrf6ece[51];ykf5f1a<=nrf6ece[52];phaf8d1<=nrf6ece[53];ps7c68f<=nrf6ece[54];vve347a<=nrf6ece[55];co1a3d6<=nrf6ece[56];cmd1eb0<=nrf6ece[57];end -always@* begin bl7edd9[2047]<=sgmii_mode;bl7edd9[2046]<=signal_detect;bl7edd9[2044]<=debug_link_timer_short;bl7edd9[2040]<=operational_rate[0];bl7edd9[2032]<=rx_data[0];bl7edd9[2017]<=rx_kcntl;bl7edd9[1987]<=rx_even;bl7edd9[1926]<=rx_disp_err;bl7edd9[1805]<=sj174c0;bl7edd9[1804]<=rx_cv_err;bl7edd9[1803]<=qt6a25d;bl7edd9[1761]<=fafe0ba;bl7edd9[1668]<=bydf425;bl7edd9[1562]<=tuebfab;bl7edd9[1560]<=rx_err_decode_mode;bl7edd9[1558]<=ri89765;bl7edd9[1550]<=mr_restart_an;bl7edd9[1475]<=uif05d3;bl7edd9[1464]<=xl27f82;bl7edd9[1288]<=uifa12a;bl7edd9[1076]<=xj5fd5b;bl7edd9[1072]<=tx_d[0];bl7edd9[1069]<=mr4bb2a;bl7edd9[1056]<=vx84a8a;bl7edd9[1052]<=jceec52[0];bl7edd9[1028]<=jc576ac[0];bl7edd9[1023]<=gbe_mode;bl7edd9[902]<=co82e98;bl7edd9[901]<=czed44b;bl7edd9[880]<=xy3fc17;bl7edd9[834]<=yx5be84;bl7edd9[775]<=mr_main_reset;bl7edd9[732]<=tu76293;bl7edd9[621]<=mtab449;bl7edd9[528]<=lqd0951;bl7edd9[514]<=ux8aed5;bl7edd9[450]<=jebda89[0];bl7edd9[417]<=kfab7d0;bl7edd9[387]<=mr_an_enable;bl7edd9[366]<=cz65516;bl7edd9[310]<=qi15689;bl7edd9[257]<=en515da;bl7edd9[225]<=baa25a8;bl7edd9[208]<=ykf56fa;bl7edd9[193]<=tx_er;bl7edd9[183]<=rtecaa2;bl7edd9[155]<=go62ad1;bl7edd9[128]<=ba2a2bb[0];bl7edd9[112]<=tu5dd8a[0];bl7edd9[104]<=tufeadf;bl7edd9[96]<=tx_en;bl7edd9[91]<=xw5d954;bl7edd9[77]<=ouac55a;bl7edd9[64]<=ri25457;bl7edd9[56]<=fcbbb1[0];bl7edd9[38]<=rgd58ab;bl7edd9[19]<=nedab15;bl7edd9[9]<=epbb562;end assign kd60607 = bl7edd9,nrf6ece = yz181ef; initial begin xweb9c8 = $fopen(".fred"); $fdisplay( xweb9c8, "%3h\n%3h", (czd9d9d >> 4) & gq9d818, (czd9d9d >> (vi76760+4)) & gq9d818 ); $fclose(xweb9c8); $readmemh(".fred", oh7beb); end always @ (kd60607) begin qgefae7 = oh7beb[1]; for (ay5ce43=0; ay5ce43kItJR+j7Zx1KF6@n8Cle_v!-bGg3U${I^6U(~Z^b7}bt(Yk9vQv7C< zX{Qk4i?bp>OW`$aHpz>L{`l?uoy7HjI2ujww18B>%d)=H^}o^z>VK(`q5kW4Dn$vi z|M2=>&)-ki&pW+*a(*@b^Wc3SO>^;V(qHW5>$Qviq+4U;xETGIcc+tDuk+uv?z>3= z8>u}kQR!#!uSWx^_MeYOlm2v6T-{MIu5bTg|KD0#YJG11cclJGHq+u{m``hGCwV*X zjvE)X{Q|0Vc|pZ)(|uKwjva98=?zW!T{`qJn6zbpM$ z@kzITS^wjUe*3h4I%@a2AJrq=zW!I1mKvYyzpCEu3U|}`cWhzt-7Pcc`Y)aTx0*}n z?A7{@?Ef2$tiJMj{J*7|KZv|m6AO3n@6kgr+ARAgw%;85?QrkK%VY8S&GFv$u6SDZ zj~U&8Knu)hdo;c(`e)};G2eYG8ufZ>0smPQCs$&>GoALkxj4!%`rXm6H|t`?E4D|) zcvN(z{n7AFB_U?aP$d4{Oq4`I(ZWCRdRIIjVa^8OXT`KMmzVv)U~)1lMo+|>L$S8f z$d*cJ-!2|4ZY@>{eZ0HBF0zHydVN95FXrDKZHdmXC$>AoPOtO0ls}gxTUe^EF03|| z7nadOi22dp4tXR8rAtlZmwAH%Mfk3UYjMr+xT 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zS@kjT+C^!R7(})YnX%QJv&Or>6rRkuN_Tpmodbh?DKTBUI^!{MNjy6*_^Ys&_zt+r z_VQq?(s3fbOO8SEB~#;7{ZM&lci(2QEod%3Z@w&B%l$ix;K|O_ZWpN`p)yW}5INA% z*c?@suw@Hg8V0lFe8Ef?RBtZNHeu|R6XO4e&T~)brthglr!;U%1E(}_N&}}fa7qKG cG;m4-r!;U%1E(}_N&}}fa7qLJUuocf0|l&$X#fBK diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/stdout.log b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/stdout.log deleted file mode 100755 index dac7faf..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs32/stdout.log +++ /dev/null @@ -1,42 +0,0 @@ -Running in Lattice mode - - -Starting: /opt/synplify/syn96L3/synplify_linux/linux/mbin/synbatch -Install: /opt/synplify/syn96L3/synplify_linux -Date: Thu Dec 10 15:57:42 2009 -Version: 9.6L3 - - -Arguments: -product synplify -batch /home/greg/NewHub2/hub2/ipexpress/sgmii_gbe_pcs32/syn_results/sgmii_gbe_pcs32.prj -ProductType: synplify - - - - - -Running synthesis on sgmii_gbe_pcs32:syn_results - -log file: "/home/greg/NewHub2/hub2/ipexpress/sgmii_gbe_pcs32/syn_results/sgmii_gbe_pcs32.srf" - - -Running Verilog Compiler... - -Verilog Compiler Completed -Return Code: 0 - - -Running lattice-ecp2m Mapper... - -Option not allowed with current settings and will be ignored: fixgatedclocks -Option not allowed with current settings and will be ignored: fixgeneratedclocks - -Option not allowed with current settings and will be ignored: fixgatedclocks -Option not allowed with current settings and will be ignored: fixgeneratedclocks - -lattice-ecp2m Mapper Completed with warnings -Return Code: 1 - - -exit status=0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/generate_core.tcl b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/generate_core.tcl deleted file mode 100644 index 473e9cf..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/generate_core.tcl +++ /dev/null @@ -1,43 +0,0 @@ - -#!/usr/local/bin/wish - -set Para(cmd) "" -if ![catch {set temp $argc} result] { - if {$argc > 0} { - for {set i 0} {$i < $argc} {incr i 2} { - set temp [lindex $argv $i] - set temp [string range $temp 1 end] - lappend argv_list $temp - lappend value_list [lindex $argv [expr $i+1]] - } - foreach argument $argv_list value $value_list { - switch $argument { - "cmd" {set Para(cmd) $value;} - } - } - } -} - -set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/sgmii_gbe_pcs34" -set Para(ModuleName) "sgmii_gbe_pcs34" -set Para(lib) "/home/greg/sgmii_gbepcs_v3.4/lib" -set Para(CoreName) "SGMII/Gb Ethernet PCS" -set Para(arch) "ep5m00" -set Para(family) "latticeecp2m" -set Para(Family) "latticeecp2m" -set Para(design) "VHDL" -set Para(install_dir) "/opt/lattice/diamond/1.1/bin/lin/../.." -set Para(Bin) "/opt/lattice/diamond/1.1/bin/lin" -set Para(SpeedGrade) "Para(spd)" -set Para(FPGAPath) "/opt/lattice/diamond/1.1/bin/lin/../../ispfpga/bin/sol" - -lappend auto_path "/home/greg/sgmii_gbepcs_v3.4/gui" - -lappend auto_path "/home/greg/sgmii_gbepcs_v3.4/script" -package require Core_Generate - -lappend auto_path "/opt/lattice/diamond/1.1/tcltk/lib/ipwidgets/ispipbuilder/../runproc" -package require runcmd - - -set Para(result) [GenerateCore] diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.ipx b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.ipx deleted file mode 100644 index cada8be..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.ipx +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.lpc b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.lpc deleted file mode 100644 index 78e9a7a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.lpc +++ /dev/null @@ -1,26 +0,0 @@ -[Device] -Family=ep5c00 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=IPCFG -CoreStatus=Demo -CoreName=SGMII/Gb Ethernet PCS -CoreRevision=3.4 -ModuleName=sgmii_gbe_pcs34 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=10/04/2011 -Time=13:50:08 - -[Parameters] -RX_CTC=2 -RX_CTC_LOW=16 -RX_CTC_HIGH=32 -EasyConnect=1 diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.ngo b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34.ngo deleted file mode 100644 index 0b24d2558683d8840971e6923e6fcce756742a4e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 389472 zcmb4M30$OQ{anfIb3ae&l(C)g1Dpg(|oRNe|!!yCc(jOK&jgTjp?HibblmVRi|h72)+avu{X zQ$W)}B1^{Uk4yqn1yugNgvqCQzr?d_d zL8PkWSRas54?}28+Ig7HaG(cB!=(^A1DvrLi9~sN!Bf|$^DOa1a+qFA=nVARoxlLa zeyfK_eL&-YgOTG!M$FJDGG&R>0sL{y)DQvqLyKAq@JALk4DkEyCNqX~{)0&Y%Jzr- z+Ibzqny>AFz+bd{L{2iGO#(|s_TpSmC1cQVp z+f5jaTX0*_1QBH2HzY`_YKYa{X&F+jR8ZR{gru{Bh&8;%2TbNc%E3r@&5Q|B>)e3g z*JFX{YKc`^5OcxWR>7w*h_WC;MHvSbhH0$x=@@3RA*N%H%!2iEItCsTG>+;R2HtG5 z#qRq4n8pL+`3buAPR;Ge==j^Vn=Qrv7z=2oeRFZ5;i32 zQ1}Dow9ep_tfPvTY~^`HOiQ zN|d!EX5#4j&2bZCG%S3PCB@G8g%pVH>FOBnV7U1wsLnvr$?x@YgFUythU*F2tDkX0wKXNa07u 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z=yql%z2tUfCXI4CGLuHT-Iz&Z+)m7-m)$PRq#CyaGij{beVO!%+j*Jvs@rv$^qSjo zne@8bZJFeJA57jm;|;gVGPPQ_!!l{S+g+LTrrTMWG{NnvOq%F+R3=SwyD5|2ayu!L z-iAJ@jueB_L7DUpobJh_$!_Ol(iFFAGU;9D9N@uJw_7r`X>O-vlCz_%rwbm`xgC;8 z&W^Iq8fm868JRT8?TSpA?RG>a&2hUSljgdekV*60F32S3e(1nVl5;<_Tr}r?=&h~P z-gmnmlNPugk4Yc6-Hu5M-A>1(58W=uqz1RcG0C|fI=G4Cv~B7hBRS0ld&ugY_HaGx zsV#Q98Izm_p2ydambhJvNpYvwZw|?6e04HU5tg}~i>WP#)3uoNncK0L@tI+(OT!gHBVo1nF<5 z5nP<~kJCIZM*7z+>`Xf3w6iNG{pYm6t0oVe%X-*FY@ufR$%}S_sbXuWFmJFwT8Z&o-({inW(N5^Is+rW;Y1r0AI>zaIkwxm_ z_L(L*_dW;4NZs6m%%tvaF=moe3i&FH)Wa>pOmf~SUENA@zJvdh%yFDsc$u2>p6R9t z$$8JzSA5QUrfZt0Wx0ixNhi5QmPseO1(r#txW$!8r@DoeNnW?8GD(3`P?@B<#gs{! zTS%F78k{1^B%fPAndH2;nlI68IE9m`o$eM*CY|B5eUyA>I!z_BsO30~C^gbqPV-8k zT(>|nwLG^tGD(M17?~7snsLfX4YwdNHD{0dhjEg#XKW8hXS+p^Nd;~JWRkO6eXOj- zatj|*bM~#v=U1J2xdo4@^+te0J)LZ~&@nY<2m7oNQjuHWm{jZ*HztMM!p5XNZc$^> TIc`B?lC!^kK^-aL7Bc>S&cFXr diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34_bb.v b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34_bb.v deleted file mode 100644 index 5b49cc1..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34_bb.v +++ /dev/null @@ -1,143 +0,0 @@ -//============================================================================= -// Verilog module generated by IPExpress 10/04/2011 13:50:20 -// Filename: sgmii_gbe_pcs34_bb.v -// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved. -//============================================================================= - -//--------------------------------------------------------------- -// sgmii_gbe_pcs34 synthesis black box definition -//--------------------------------------------------------------- - -/* WARNING - Changes to this file should be performed by re-running IPexpress -or modifying the .LPC file and regenerating the core. Other changes may lead -to inconsistent simulation and/or implemenation results */ - - - - - - -module sgmii_gbe_pcs34 ( - // Control Interface - rst_n, - signal_detect, - gbe_mode, - sgmii_mode, - operational_rate, - debug_link_timer_short, - force_isolate, - force_loopback, - force_unidir, - - rx_compensation_err, - ctc_drop_flag, - ctc_add_flag, - an_link_ok, - - // G/MII Interface - tx_clock_enable_sink , - tx_clock_enable_source , - tx_clk_125, - tx_d, - tx_en, - tx_er, - - rx_clock_enable_sink , - rx_clock_enable_source , - rx_clk_125, - rx_d, - rx_dv, - rx_er, - col, - crs, - - // 8-bit Interface - tx_data, - tx_kcntl, - tx_disparity_cntl, - xmit_autoneg, - - serdes_recovered_clk, - rx_data, - rx_kcntl, - rx_even , - rx_disp_err , - rx_cv_err , - rx_err_decode_mode , - - // Managment Control Outputs - mr_an_complete, - mr_page_rx, - mr_lp_adv_ability, - - // Managment Control Inputs - mr_main_reset, - mr_an_enable, - mr_restart_an, - mr_adv_ability - ); - - - -// Control Interface -input rst_n ; -input signal_detect ; -input gbe_mode ; -input sgmii_mode ; -input [1:0] operational_rate ; -input debug_link_timer_short ; -input force_isolate ; -input force_loopback ; -input force_unidir ; - -output rx_compensation_err ; -output ctc_drop_flag ; -output ctc_add_flag ; -output an_link_ok ; - -// G/MII Interface -input tx_clock_enable_sink; -output tx_clock_enable_source; -input tx_clk_125 ; -input [7:0] tx_d ; -input tx_en ; -input tx_er ; - -input rx_clock_enable_sink; -output rx_clock_enable_source; -input rx_clk_125 ; -output [7:0] rx_d ; -output rx_dv ; -output rx_er ; -output col ; -output crs ; - -// 8-bit Interface -output [7:0] tx_data ; -output tx_kcntl; -output tx_disparity_cntl; -output xmit_autoneg; - -input serdes_recovered_clk ; -input [7:0] rx_data ; -input rx_even ; -input rx_kcntl; -input rx_disp_err ; -input rx_cv_err ; -input rx_err_decode_mode ; - -// Managment Control Outputs -output mr_an_complete; -output mr_page_rx; -output [15:0] mr_lp_adv_ability; - -// Managment Control Inputs -input mr_main_reset; -input mr_an_enable; -input mr_restart_an; -input [15:0] mr_adv_ability; - - - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34_beh.v b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34_beh.v deleted file mode 100644 index e3a0f02..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs34/sgmii_gbe_pcs34_beh.v +++ /dev/null @@ -1,5440 +0,0 @@ -// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1 -// created on Wed Feb 23 18:52:49 CST 2011 -// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved -// obfuscator_exe version 1.mar0807 - -// top - - -`define SGMII_NO_ENC - -`define SGMII_YES_CTC_DYNAMIC - -`define SGMII_FIFO_FAMILY_ECP3 - -`define SGMII_YES_SINGLE_CLOCK - - - - -`timescale 1 ns / 100 ps -module tjb57bb (wlabdde, uv5eef5, wjf77ad, yzbbd6d, medeb6c, icf5b61, - puadb09, kq6d84a, xw6c250, dz61283, vx941f, th4a0fe, hb507f7, - ri83fbf); -input [17:0] wlabdde; -input uv5eef5; -input wjf77ad; -input yzbbd6d; -input medeb6c; -input icf5b61; -input puadb09; -input [9:0] kq6d84a; -input [9:0] xw6c250; -output [17:0] dz61283; -output vx941f; -output th4a0fe; -output hb507f7; -output ri83fbf; -reg [17 : 0] ng14a7f; -reg lfa53fa; -reg gd29fd7; -reg th4febc; -reg cz7f5e6; -reg wwfaf35; -reg zxd79a8; -reg [9 : 0] ecbcd47; -reg [9 : 0] pfe6a39; -reg [2047:0] ls351cf; -wire [8:0] jea8e7a; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -localparam ps473d2 = 9,wl39e93 = 32'hfdfff40b; -localparam [31:0] bycf49d = wl39e93; -localparam xjd275d = wl39e93 & 4'hf; -localparam [11:0] wy9d773 = 'h7ff; -wire [(1 << xjd275d) -1:0] jc5dccb; -reg [ps473d2-1:0] zk732d2; -reg [xjd275d-1:0] cmcb49b [0:1]; -reg [xjd275d-1:0] xjd26ce; -reg ls93676; -integer vx9b3b2; -integer ald9d96; - -AND2 mececb4 (.A(yzbbd6d), .B(fcb2d03), .Z(ng9681a)); INV ohb40d3 (.A(jra069c), .Z(fcb2d03)); AND2 ks1a73f (.A(medeb6c), .B(ls9cfc5), .Z(yxe7e2a)); INV fc3f155 (.A(wjf8aab), .Z(ls9cfc5)); OR2 je2aaea (.A(icf5b61), .B(puadb09), .Z(zk5d4fd)); XOR2 icea7eb (.A(go53f58), .B(kf9fac1), .Z(uvfd60d)); XOR2 hoeb06c (.A(kf9fac1), .B(icc1b13), .Z(sjd899)); XOR2 xw6c4cd (.A(icc1b13), .B(tj13358), .Z(fc99ac6)); XOR2 dzcd632 (.A(tj13358), .B(jc58cb6), .Z(ipc65b2)); XOR2 tj32d95 (.A(jc58cb6), .B(ymb6573), .Z(ngb2b99)); XOR2 an95cca (.A(ymb6573), .B(xw732a4), .Z(fc99523)); XOR2 faca91b (.A(xw732a4), .B(oha46d4), .Z(ep236a5)); XOR2 xy1b52c (.A(oha46d4), .B(god4b13), .Z(hda5898)); XOR2 wl2c4c6 (.A(god4b13), .B(hd131a8), .Z(mg98d46)); XOR2 gbc6a30 (.A(hd131a8), .B(baa8c22), .Z(cm46112)); XOR2 vk30891 (.A(rv8448b), .B(jr2245e), .Z(mt122f6)); XOR2 db917b4 (.A(jr2245e), .B(gb5ed3e), .Z(pff69f5)); XOR2 qvb4fae (.A(gb5ed3e), .B(co3ebab), .Z(suf5d58)); XOR2 sjaeac1 (.A(co3ebab), .B(irab06c), .Z(ho58364)); XOR2 uic1b23 (.A(irab06c), .B(lq6c8cd), .Z(hb6466a)); XOR2 an23357 (.A(lq6c8cd), .B(ldcd5e6), .Z(qt6af36)); XOR2 xw579b5 (.A(ldcd5e6), .B(rte6d59), .Z(cb36acf)); XOR2 rvb567c (.A(rte6d59), .B(qg59f34), .Z(lqcf9a0)); XOR2 ps7cd02 (.A(qg59f34), .B(mg3409f), .Z(tja04f8)); XOR2 sj27c7 (.A(mg3409f), .B(an9f1ef), .Z(off8f7c)); defparam rtc7be5.initval = 16'h6996 ; ROM16X1 rtc7be5 (.AD3(ayef977), .AD2(zk7cbb9), .AD1(yke5dcb), .AD0(aa2ee58), .DO0(yk772c1)) ; defparam mgb9609.initval = 16'h6996 ; ROM16X1 mgb9609 (.AD3(ne58241), .AD2(qgc120b), .AD1(bn9058), .AD0(ne482c6), .DO0(gb41632)) ; defparam xyb194.initval = 16'h6996 ; ROM16X1 xyb194 (.AD3(yke5dcb), .AD2(aa2ee58), .AD1(hd946ae), .AD0(hd946ae), .DO0(ou1abb8)) ; defparam zkd5dc1.initval = 16'h6996 ; ROM16X1 zkd5dc1 (.AD3(zk7cbb9), .AD2(yke5dcb), .AD1(aa2ee58), .AD0(hd946ae), .DO0(vv55280)) ; defparam yma9407.initval = 16'h6996 ; ROM16X1 yma9407 (.AD3(ne482c6), .AD2(ayef977), .AD1(zk7cbb9), .AD0(ou1abb8), .DO0(xwcff6d)) ; defparam ip7fb6a.initval = 16'h6996 ; ROM16X1 ip7fb6a (.AD3(bn9058), .AD2(ne482c6), .AD1(ayef977), .AD0(vv55280), .DO0(nta586c)) ; defparam sj2c366.initval = 16'h6996 ; ROM16X1 sj2c366 (.AD3(qgc120b), .AD2(bn9058), .AD1(ne482c6), .AD0(yk772c1), .DO0(wlaea9b)) ; defparam uv754dd.initval = 16'h6996 ; ROM16X1 uv754dd (.AD3(yk772c1), .AD2(gb41632), .AD1(hd946ae), .AD0(hd946ae), .DO0(dm661f6)) ; defparam pu30fb2.initval = 16'h6996 ; ROM16X1 pu30fb2 (.AD3(yk772c1), .AD2(gb41632), .AD1(dob2607), .AD0(hd946ae), .DO0(qi981da)) ; defparam psc0ed1.initval = 16'h6996 ; ROM16X1 psc0ed1 (.AD3(yk772c1), .AD2(gb41632), .AD1(sud174a), .AD0(dob2607), .DO0(dm5d28e)) ; defparam rte9473.initval = 16'h6996 ; ROM16X1 rte9473 (.AD3(of51cff), .AD2(sud174a), .AD1(dob2607), .AD0(hd946ae), .DO0(ykff9d5)) ; defparam pffcea8.initval = 16'h6996 ; ROM16X1 pffcea8 (.AD3(yk772c1), .AD2(gb41632), .AD1(ykff9d5), .AD0(hd946ae), .DO0(ep3c4d2)) ; defparam kde2694.initval = 16'h6996 ; ROM16X1 kde2694 (.AD3(wl9a526), .AD2(jpd2934), .AD1(jr949a7), .AD0(epa4d3e), .DO0(yz269f4)) ; defparam ec34fa5.initval = 16'h6996 ; ROM16X1 ec34fa5 (.AD3(ou3e94b), .AD2(lqf4a58), .AD1(pha52c3), .AD0(mt2961f), .DO0(sh4b0fd)) ; defparam xw587ed.initval = 16'h6996 ; ROM16X1 xw587ed (.AD3(jr949a7), .AD2(epa4d3e), .AD1(hd946ae), .AD0(hd946ae), .DO0(os5c36f)) ; defparam zke1b79.initval = 16'h6996 ; ROM16X1 zke1b79 (.AD3(jpd2934), .AD2(jr949a7), .AD1(epa4d3e), .AD0(hd946ae), .DO0(nr55112)) ; defparam nga8897.initval = 16'h6996 ; ROM16X1 nga8897 (.AD3(mt2961f), .AD2(wl9a526), .AD1(jpd2934), .AD0(os5c36f), .DO0(wwd4d46)) ; defparam coa6a30.initval = 16'h6996 ; ROM16X1 coa6a30 (.AD3(pha52c3), .AD2(mt2961f), .AD1(wl9a526), .AD0(nr55112), .DO0(iea456)) ; defparam vi522b1.initval = 16'h6996 ; ROM16X1 vi522b1 (.AD3(lqf4a58), .AD2(pha52c3), .AD1(mt2961f), .AD0(yz269f4), .DO0(fa57824)) ; defparam aabc123.initval = 16'h6996 ; ROM16X1 aabc123 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(hd946ae), .AD0(hd946ae), .DO0(xwc0665)) ; defparam fp332a.initval = 16'h6996 ; ROM16X1 fp332a (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(xy2afad), .AD0(hd946ae), .DO0(wlbeb5b)) ; defparam wwf5adc.initval = 16'h6996 ; ROM16X1 wwf5adc (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(wjdc2f5), .AD0(xy2afad), .DO0(fcbd6b)) ; defparam uv5eb5a.initval = 16'h6996 ; ROM16X1 uv5eb5a (.AD3(hqad6a9), .AD2(wjdc2f5), .AD1(xy2afad), .AD0(hd946ae), .DO0(uka97bb)) ; defparam en4bdd9.initval = 16'h6996 ; ROM16X1 en4bdd9 (.AD3(yz269f4), .AD2(sh4b0fd), .AD1(uka97bb), .AD0(hd946ae), .DO0(of65b65)) ; XOR2 bn2db2c (.A(baa8c22), .B(epa4d3e), .Z(gb65982)); XOR2 oh2cc14 (.A(aa2ee58), .B(an9f1ef), .Z(ou82912)); defparam je14890.initval = 16'h0410 ; ROM16X1 je14890 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(ks15d28)) ; defparam mtae940.initval = 16'h1004 ; ROM16X1 mtae940 (.AD3(db22415), .AD2(an9f1ef), .AD1(aa2ee58), .AD0(hd946ae), .DO0(je2fff9)) ; defparam uv7ffcb.initval = 16'h0140 ; ROM16X1 uv7ffcb (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(yke0381)) ; defparam fc1c09.initval = 16'h4001 ; ROM16X1 fc1c09 (.AD3(ykff2e0), .AD2(baa8c22), .AD1(epa4d3e), .AD0(hd946ae), .DO0(of5b9b5)) ; INV aldcdad (.A(pfe6d6c), .Z(mt36b67)); AND2 tjb5b3c (.A(zmad9e7), .B(mt36b67), .Z(ui679d2)); AND2 an3ce91 (.A(zmad9e7), .B(pfe6d6c), .Z(hbd2363)); defparam ph91b1e.CSDECODE_R = 3'b000 ; defparam ph91b1e.CSDECODE_W = 3'b000 ; defparam ph91b1e.GSR = "ENABLED" ; defparam ph91b1e.RESETMODE = "ASYNC" ; defparam ph91b1e.REGMODE = "NOREG" ; defparam ph91b1e.DATA_WIDTH_R = 18 ; defparam ph91b1e.DATA_WIDTH_W = 18 ; PDP16KA ph91b1e (.DI0(wlabdde[0]), .DI1(wlabdde[1]), .DI2(wlabdde[2]), .DI3(wlabdde[3]), .DI4(wlabdde[4]), .DI5(wlabdde[5]), .DI6(wlabdde[6]), .DI7(wlabdde[7]), .DI8(wlabdde[8]), .DI9(wlabdde[9]), .DI10(wlabdde[10]), .DI11(wlabdde[11]), .DI12(wlabdde[12]), .DI13(wlabdde[13]), .DI14(wlabdde[14]), .DI15(wlabdde[15]), .DI16(wlabdde[16]), .DI17(wlabdde[17]), .DI18(wlabdde[0]), .DI19(wlabdde[1]), .DI20(wlabdde[2]), .DI21(wlabdde[3]), .DI22(wlabdde[4]), .DI23(wlabdde[5]), .DI24(wlabdde[6]), .DI25(wlabdde[7]), .DI26(wlabdde[8]), .DI27(wlabdde[9]), .DI28(wlabdde[10]), .DI29(wlabdde[11]), .DI30(wlabdde[12]), .DI31(wlabdde[13]), .DI32(wlabdde[14]), .DI33(wlabdde[15]), .DI34(wlabdde[16]), .DI35(wlabdde[17]), .ADW0(ba1ecef), .ADW1(ba1ecef), .ADW2(hd946ae), .ADW3(hd946ae), .ADW4(meef7c0), .ADW5(pf7be00), .ADW6(tudf006), .ADW7(kdf8032), .ADW8(fac0194), .ADW9(ouca2), .ADW10(ph6511), .ADW11(xl3288f), .ADW12(db9447e), .ADW13(lsa23f7), .CEW(ng9681a), .CLKW(uv5eef5), .WE(ba1ecef), .CSW0(hd946ae), .CSW1(hd946ae), .CSW2(hd946ae), .ADR0(hd946ae), .ADR1(hd946ae), .ADR2(hd946ae), .ADR3(hd946ae), .ADR4(al7fc5f), .ADR5(dmfe2fc), .ADR6(faf17e3), .ADR7(ph8bf1a), .ADR8(xj5f8d6), .ADR9(vvfc6b7), .ADR10(rte35be), .ADR11(wy1adf6), .ADR12(mrd6fb1), .ADR13(fcb7d8d), .CER(yxe7e2a), .CLKR(wjf77ad), .CSR0(hd946ae), .CSR1(hd946ae), .CSR2(hd946ae), .RST(icf5b61), .DO0(dz61283[0]), .DO1(dz61283[1]), .DO2(dz61283[2]), .DO3(dz61283[3]), .DO4(dz61283[4]), .DO5(dz61283[5]), .DO6( -dz61283[6]), .DO7(dz61283[7]), .DO8(dz61283[8]), .DO9(dz61283[9]), .DO10(dz61283[10]), .DO11(dz61283[11]), .DO12(dz61283[12]), .DO13(dz61283[13]), .DO14(dz61283[14]), .DO15(dz61283[15]), .DO16(dz61283[16]), .DO17(dz61283[17]), .DO18(), .DO19(), .DO20(), .DO21(), .DO22(), .DO23(), .DO24(), .DO25(), .DO26(), .DO27(), .DO28(), .DO29(), .DO30(), .DO31(), .DO32(), .DO33(), .DO34(), .DO35()) ; defparam hq113f.GSR = "ENABLED" ; FD1P3BX hq113f (.D(gb44fd5), .SP(ng9681a), .CK(uv5eef5), .PD(icf5b61), .Q(go53f58)) ; defparam fcadec2.GSR = "ENABLED" ; FD1P3DX fcadec2 (.D(zx7b094), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kf9fac1)) ; defparam lsa7fee.GSR = "ENABLED" ; FD1P3DX lsa7fee (.D(qgffb9a), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(icc1b13)) ; defparam jcd0a9c.GSR = "ENABLED" ; FD1P3DX jcd0a9c (.D(hq2a714), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tj13358)) ; defparam fca22eb.GSR = "ENABLED" ; FD1P3DX fca22eb (.D(db8bad3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(jc58cb6)) ; defparam xl9e6b5.GSR = "ENABLED" ; FD1P3DX xl9e6b5 (.D(kf9ad77), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ymb6573)) ; defparam jebdbe8.GSR = "ENABLED" ; FD1P3DX jebdbe8 (.D(mr6fa1c), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xw732a4)) ; defparam wwe5146.GSR = "ENABLED" ; FD1P3DX wwe5146 (.D(dz4518e), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(oha46d4)) ; defparam zk76c4e.GSR = "ENABLED" ; FD1P3DX zk76c4e (.D(cbb1391), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(god4b13)) ; defparam pu8c74e.GSR = "ENABLED" ; FD1P3DX pu8c74e (.D(ir1d393), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(hd131a8)) ; defparam aa9dd4b.GSR = "ENABLED" ; FD1P3DX aa9dd4b (.D(al752c3), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(baa8c22)) ; defparam tj1c35c.GSR = "ENABLED" ; FD1P3DX tj1c35c (.D(uvfd60d), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pu3a9c4)) ; defparam sud4e22.GSR = "ENABLED" ; FD1P3DX sud4e22 (.D(sjd899), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(gq82e31)) ; defparam yz17188.GSR = "ENABLED" ; FD1P3DX yz17188 (.D(fc99ac6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ep23a0c)) ; defparam cb1d065.GSR = "ENABLED" ; FD1P3DX cb1d065 (.D(ipc65b2), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(os6dbe6)) ; defparam cm6df30.GSR = "ENABLED" ; FD1P3DX cm6df30 (.D(ngb2b99), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ks5795)) ; defparam co2bca8.GSR = "ENABLED" ; FD1P3DX co2bca8 (.D(fc99523), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tjc95d)) ; defparam hb64aef.GSR = "ENABLED" ; FD1P3DX hb64aef (.D(ep236a5), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(thf328f)) ; defparam zm9947f.GSR = "ENABLED" ; FD1P3DX zm9947f (.D(hda5898), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(godb92b)) ; defparam ofdc959.GSR = "ENABLED" ; FD1P3DX ofdc959 (.D(mg98d46), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ea62604)) ; defparam zz13020.GSR = "ENABLED" ; FD1P3DX zz13020 (.D(cm46112), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(co31697)) ; defparam rv8b4b8.GSR = "ENABLED" ; FD1P3DX rv8b4b8 (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ou3ee1e)) ; defparam mrf70f0.GSR = "ENABLED" ; FD1P3DX mrf70f0 (.D(go53f58), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(meef7c0)) ; defparam yx54463.GSR = "ENABLED" ; FD1P3DX yx54463 (.D(kf9fac1), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(pf7be00)) ; defparam by524e8.GSR = "ENABLED" ; FD1P3DX by524e8 (.D(icc1b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(tudf006)) ; defparam je83359.GSR = "ENABLED" ; FD1P3DX je83359 (.D(tj13358), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(kdf8032)) ; defparam rtf6c45.GSR = "ENABLED" ; FD1P3DX rtf6c45 (.D(jc58cb6), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(fac0194)) ; defparam ri8c3c7.GSR = "ENABLED" ; FD1P3DX ri8c3c7 (.D(ymb6573), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ouca2)) ; defparam kfb13d4.GSR = "ENABLED" ; FD1P3DX kfb13d4 (.D(xw732a4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ph6511)) ; defparam uk1f82d.GSR = "ENABLED" ; FD1P3DX uk1f82d (.D(oha46d4), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(xl3288f)) ; defparam kd703d5.GSR = "ENABLED" ; FD1P3DX kd703d5 (.D(god4b13), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(db9447e)) ; defparam qv39880.GSR = "ENABLED" ; FD1P3DX qv39880 (.D(hd131a8), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(lsa23f7)) ; defparam al6034d.GSR = "ENABLED" ; FD1P3DX al6034d (.D(baa8c22), .SP(ng9681a), .CK(uv5eef5), .CD(icf5b61), .Q(ykff2e0)) ; defparam su5c4cf.GSR = "ENABLED" ; FD1P3BX su5c4cf (.D(ph133cc), .SP(yxe7e2a), .CK(wjf77ad), .PD(zk5d4fd), .Q(rv8448b)) ; defparam lq664dd.GSR = "ENABLED" ; FD1P3DX lq664dd (.D(ba93757), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jr2245e)) ; defparam xlbafca.GSR = "ENABLED" ; FD1P3DX xlbafca (.D(tjbf2b7), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gb5ed3e)) ; defparam rvbfc8a.GSR = "ENABLED" ; FD1P3DX rvbfc8a (.D(czf22b3), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(co3ebab)) ; defparam gq9df00.GSR = "ENABLED" ; FD1P3DX gq9df00 (.D(lq7c001), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(irab06c)) ; defparam qia202.GSR = "ENABLED" ; FD1P3DX qia202 (.D(ym8808d), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(lq6c8cd)) ; defparam me68d50.GSR = "ENABLED" ; FD1P3DX me68d50 (.D(tw35400), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ldcd5e6)) ; defparam wl2de0.GSR = "ENABLED" ; FD1P3DX wl2de0 (.D(pub7827), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte6d59)) ; defparam pu3a01e.GSR = "ENABLED" ; FD1P3DX pu3a01e (.D(qv8079b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qg59f34)) ; defparam kddccbf.GSR = "ENABLED" ; FD1P3DX kddccbf (.D(zz32fe6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mg3409f)) ; defparam yz363bf.GSR = "ENABLED" ; FD1P3DX yz363bf (.D(nt8efed), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(an9f1ef)) ; defparam bl6e1ac.GSR = "ENABLED" ; FD1P3DX bl6e1ac (.D(mt122f6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(tw354c3)) ; defparam xlaa61a.GSR = "ENABLED" ; FD1P3DX xlaa61a (.D(pff69f5), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(jrb034c)) ; defparam vx81a66.GSR = "ENABLED" ; FD1P3DX vx81a66 (.D(suf5d58), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(gqbc45e)) ; defparam ale22f0.GSR = "ENABLED" ; FD1P3DX ale22f0 (.D(ho58364), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qv23d0e)) ; defparam tw1e875.GSR = "ENABLED" ; FD1P3DX tw1e875 (.D(hb6466a), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld5a8a4)) ; defparam ayd4527.GSR = "ENABLED" ; FD1P3DX ayd4527 (.D( -qt6af36), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb534)) ; defparam jp5a9a1.GSR = "ENABLED" ; FD1P3DX jp5a9a1 (.D(cb36acf), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(me78221)) ; defparam uic1108.GSR = "ENABLED" ; FD1P3DX uic1108 (.D(lqcf9a0), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(sw5867)) ; defparam ux2c339.GSR = "ENABLED" ; FD1P3DX ux2c339 (.D(tja04f8), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vv6ee2f)) ; defparam kq7717f.GSR = "ENABLED" ; FD1P3DX kq7717f (.D(off8f7c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(qgcb6ee)) ; defparam ip5b771.GSR = "ENABLED" ; FD1P3DX ip5b771 (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ld61cba)) ; defparam bae5d6.GSR = "ENABLED" ; FD1P3DX bae5d6 (.D(rv8448b), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(al7fc5f)) ; defparam lqc0d09.GSR = "ENABLED" ; FD1P3DX lqc0d09 (.D(jr2245e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(dmfe2fc)) ; defparam wwf0ba4.GSR = "ENABLED" ; FD1P3DX wwf0ba4 (.D(gb5ed3e), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(faf17e3)) ; defparam ps69f44.GSR = "ENABLED" ; FD1P3DX ps69f44 (.D(co3ebab), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(ph8bf1a)) ; defparam ntb093e.GSR = "ENABLED" ; FD1P3DX ntb093e (.D(irab06c), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(xj5f8d6)) ; defparam czf8e27.GSR = "ENABLED" ; FD1P3DX czf8e27 (.D(lq6c8cd), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(vvfc6b7)) ; defparam gb7f3f9.GSR = "ENABLED" ; FD1P3DX gb7f3f9 (.D(ldcd5e6), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(rte35be)) ; defparam al7abfc.GSR = "ENABLED" ; FD1P3DX al7abfc (.D(rte6d59), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(wy1adf6)) ; defparam kf179df.GSR = "ENABLED" ; FD1P3DX kf179df (.D(qg59f34), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(mrd6fb1)) ; defparam go4c0e6.GSR = "ENABLED" ; FD1P3DX go4c0e6 (.D(mg3409f), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(fcb7d8d)) ; defparam gq2ed9d.GSR = "ENABLED" ; FD1P3DX gq2ed9d (.D(an9f1ef), .SP(yxe7e2a), .CK(wjf77ad), .CD(zk5d4fd), .Q(db22415)) ; defparam gb5107f.GSR = "ENABLED" ; FD1S3DX gb5107f (.D(pu3a9c4), .CK(wjf77ad), .CD(icf5b61), .Q(ipfd144)) ; defparam qte8a24.GSR = "ENABLED" ; FD1S3DX qte8a24 (.D(gq82e31), .CK(wjf77ad), .CD(icf5b61), .Q(ks24da8)) ; defparam ux26d40.GSR = "ENABLED" ; FD1S3DX ux26d40 (.D(ep23a0c), .CK(wjf77ad), .CD(icf5b61), .Q(sw599f)) ; defparam ux2ccf9.GSR = "ENABLED" ; FD1S3DX ux2ccf9 (.D(os6dbe6), .CK(wjf77ad), .CD(icf5b61), .Q(wjcc527)) ; defparam yk6293c.GSR = "ENABLED" ; FD1S3DX yk6293c (.D(ks5795), .CK(wjf77ad), .CD(icf5b61), .Q(hoe153c)) ; defparam yma9e3.GSR = "ENABLED" ; FD1S3DX yma9e3 (.D(tjc95d), .CK(wjf77ad), .CD(icf5b61), .Q(gd188e6)) ; defparam icc4734.GSR = "ENABLED" ; FD1S3DX icc4734 (.D(thf328f), .CK(wjf77ad), .CD(icf5b61), .Q(pha0bb8)) ; defparam gq5dc6.GSR = "ENABLED" ; FD1S3DX gq5dc6 (.D(godb92b), .CK(wjf77ad), .CD(icf5b61), .Q(qi3125d)) ; defparam xy892e8.GSR = "ENABLED" ; FD1S3DX xy892e8 (.D(ea62604), .CK(wjf77ad), .CD(icf5b61), .Q(fa4211d)) ; defparam sw108eb.GSR = "ENABLED" ; FD1S3DX sw108eb (.D(co31697), .CK(wjf77ad), .CD(icf5b61), .Q(by58d6a)) ; defparam wjc6b52.GSR = "ENABLED" ; FD1S3DX wjc6b52 (.D(ou3ee1e), .CK(wjf77ad), .CD(icf5b61), .Q(lf946e3)) ; defparam wya371f.GSR = "ENABLED" ; FD1S3DX wya371f (.D(tw354c3), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjf8778)) ; defparam yxc3bc4.GSR = "ENABLED" ; FD1S3DX yxc3bc4 (.D(jrb034c), .CK(uv5eef5), .CD(zk5d4fd), .Q(aa24809)) ; defparam qi24048.GSR = "ENABLED" ; FD1S3DX qi24048 (.D(gqbc45e), .CK(uv5eef5), .CD(zk5d4fd), .Q(yx416b2)) ; defparam lsb594.GSR = "ENABLED" ; FD1S3DX lsb594 (.D(qv23d0e), .CK(uv5eef5), .CD(zk5d4fd), .Q(swa3f17)) ; defparam ie1f8b9.GSR = "ENABLED" ; FD1S3DX ie1f8b9 (.D(ld5a8a4), .CK(uv5eef5), .CD(zk5d4fd), .Q(gbc9d60)) ; defparam gb4eb05.GSR = "ENABLED" ; FD1S3DX gb4eb05 (.D(qgcb534), .CK(uv5eef5), .CD(zk5d4fd), .Q(qv2ca61)) ; defparam uv6530c.GSR = "ENABLED" ; FD1S3DX uv6530c (.D(me78221), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip65837)) ; defparam ep2c1bc.GSR = "ENABLED" ; FD1S3DX ep2c1bc (.D(sw5867), .CK(uv5eef5), .CD(zk5d4fd), .Q(kqe59b1)) ; defparam ux2cd88.GSR = "ENABLED" ; FD1S3DX ux2cd88 (.D(vv6ee2f), .CK(uv5eef5), .CD(zk5d4fd), .Q(ip44761)) ; defparam oh23b0c.GSR = "ENABLED" ; FD1S3DX oh23b0c (.D(qgcb6ee), .CK(uv5eef5), .CD(zk5d4fd), .Q(gb659f7)) ; defparam oh2cfbc.GSR = "ENABLED" ; FD1S3DX oh2cfbc (.D(ld61cba), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqe4221)) ; defparam ec2110b.GSR = "ENABLED" ; FD1S3DX ec2110b (.D(ipfd144), .CK(wjf77ad), .CD(icf5b61), .Q(of51cff)) ; defparam thcd858.GSR = "ENABLED" ; FD1S3DX thcd858 (.D(ks24da8), .CK(wjf77ad), .CD(icf5b61), .Q(sud174a)) ; defparam ou3bed7.GSR = "ENABLED" ; FD1S3DX ou3bed7 (.D(sw599f), .CK(wjf77ad), .CD(icf5b61), .Q(dob2607)) ; defparam zxc26f2.GSR = "ENABLED" ; FD1S3DX zxc26f2 (.D(wjcc527), .CK(wjf77ad), .CD(icf5b61), .Q(ne58241)) ; defparam cbbee21.GSR = "ENABLED" ; FD1S3DX cbbee21 (.D(hoe153c), .CK(wjf77ad), .CD(icf5b61), .Q(qgc120b)) ; defparam en65607.GSR = "ENABLED" ; FD1S3DX en65607 (.D(gd188e6), .CK(wjf77ad), .CD(icf5b61), .Q(bn9058)) ; defparam yxe86e6.GSR = "ENABLED" ; FD1S3DX yxe86e6 (.D(pha0bb8), .CK(wjf77ad), .CD(icf5b61), .Q(ne482c6)) ; defparam yma973a.GSR = "ENABLED" ; FD1S3DX yma973a (.D(qi3125d), .CK(wjf77ad), .CD(icf5b61), .Q(ayef977)) ; defparam zm8c118.GSR = "ENABLED" ; FD1S3DX zm8c118 (.D(fa4211d), .CK(wjf77ad), .CD(icf5b61), .Q(zk7cbb9)) ; defparam do1452e.GSR = "ENABLED" ; FD1S3DX do1452e (.D(by58d6a), .CK(wjf77ad), .CD(icf5b61), .Q(yke5dcb)) ; defparam jr9b583.GSR = "ENABLED" ; FD1S3DX jr9b583 (.D(lf946e3), .CK(wjf77ad), .CD(icf5b61), .Q(aa2ee58)) ; defparam xjf3992.GSR = "ENABLED" ; FD1S3DX xjf3992 (.D(wjf8778), .CK(uv5eef5), .CD(zk5d4fd), .Q(hqad6a9)) ; defparam vkb2dca.GSR = "ENABLED" ; FD1S3DX vkb2dca (.D(aa24809), .CK(uv5eef5), .CD(zk5d4fd), .Q(wjdc2f5)) ; defparam hq9361a.GSR = "ENABLED" ; FD1S3DX hq9361a (.D(yx416b2), .CK(uv5eef5), .CD(zk5d4fd), .Q(xy2afad)) ; defparam do96f47.GSR = "ENABLED" ; FD1S3DX do96f47 (.D(swa3f17), .CK(uv5eef5), .CD(zk5d4fd), .Q(ou3e94b)) ; defparam vida519.GSR = "ENABLED" ; FD1S3DX vida519 (.D(gbc9d60), .CK(uv5eef5), .CD(zk5d4fd), .Q(lqf4a58)) ; defparam xw57e3a.GSR = "ENABLED" ; FD1S3DX xw57e3a (.D(qv2ca61), .CK(uv5eef5), .CD(zk5d4fd), .Q(pha52c3)) ; defparam cb9fbdd.GSR = "ENABLED" ; FD1S3DX cb9fbdd (.D(ip65837), .CK(uv5eef5), .CD(zk5d4fd), .Q(mt2961f)) ; defparam ay6d1b4.GSR = "ENABLED" ; FD1S3DX ay6d1b4 (.D(kqe59b1), .CK(uv5eef5), .CD(zk5d4fd), .Q(wl9a526)) ; defparam kf8125.GSR = "ENABLED" ; FD1S3DX kf8125 (.D(ip44761), .CK(uv5eef5), .CD(zk5d4fd), .Q(jpd2934)) ; defparam kq67614.GSR = "ENABLED" ; FD1S3DX kq67614 (.D(gb659f7), .CK( -uv5eef5), .CD(zk5d4fd), .Q(jr949a7)) ; defparam ls1f9f.GSR = "ENABLED" ; FD1S3DX ls1f9f (.D(lqe4221), .CK(uv5eef5), .CD(zk5d4fd), .Q(epa4d3e)) ; defparam rtd8fa3.GSR = "ENABLED" ; FD1S3BX rtd8fa3 (.D(mg3e8f6), .CK(wjf77ad), .PD(zk5d4fd), .Q(wjf8aab)) ; defparam vvf608b.GSR = "ENABLED" ; FD1S3DX vvf608b (.D(ec822fe), .CK(uv5eef5), .CD(icf5b61), .Q(jra069c)) ; defparam jcfe2f7.GSR = "ENABLED" ; FD1S3BX jcfe2f7 (.D(jr8bdda), .CK(wjf77ad), .PD(zk5d4fd), .Q(hb507f7)) ; defparam vidad6d.GSR = "ENABLED" ; FD1S3DX vidad6d (.D(vxb5b5d), .CK(uv5eef5), .CD(icf5b61), .Q(ri83fbf)) ; CU2 xw5de8f (.CI(ba1ecef), .PC1(kf9fac1), .PC0(go53f58), .CO(cb8f428), .NC1(zx7b094), .NC0(gb44fd5)); CU2 oh8516a (.CI(cb8f428), .PC1(tj13358), .PC0(icc1b13), .CO(kd6a9bf), .NC1(hq2a714), .NC0(qgffb9a)); CU2 hd37f61 (.CI(kd6a9bf), .PC1(ymb6573), .PC0(jc58cb6), .CO(dz61daf), .NC1(kf9ad77), .NC0(db8bad3)); CU2 ntb5f92 (.CI(dz61daf), .PC1(oha46d4), .PC0(xw732a4), .CO(mg92ffd), .NC1(dz4518e), .NC0(mr6fa1c)); CU2 osffa4e (.CI(mg92ffd), .PC1(hd131a8), .PC0(god4b13), .CO(kd4e139), .NC1(ir1d393), .NC0(cbb1391)); CU2 jr2736f (.CI(kd4e139), .PC1(hd946ae), .PC0(baa8c22), .CO(uv6fd78), .NC1(), .NC0(al752c3)); CU2 qgf5e2e (.CI(ba1ecef), .PC1(jr2245e), .PC0(rv8448b), .CO(qi2e38b), .NC1(ba93757), .NC0(ph133cc)); CU2 rt7163f (.CI(qi2e38b), .PC1(co3ebab), .PC0(gb5ed3e), .CO(ri3fdd6), .NC1(czf22b3), .NC0(tjbf2b7)); CU2 phbac95 (.CI(ri3fdd6), .PC1(lq6c8cd), .PC0(irab06c), .CO(ep95d19), .NC1(ym8808d), .NC0(lq7c001)); CU2 qia332e (.CI(ep95d19), .PC1(rte6d59), .PC0(ldcd5e6), .CO(ym2e1ac), .NC1(pub7827), .NC0(tw35400)); CU2 tw3582a (.CI(ym2e1ac), .PC1(mg3409f), .PC0(qg59f34), .CO(pu2a660), .NC1(zz32fe6), .NC0(qv8079b)); CU2 yxcc082 (.CI(pu2a660), .PC1(hd946ae), .PC0(an9f1ef), .CO(ym82969), .NC1(), .NC0(nt8efed)); FSUB2 vxa5a42 (.A1(kf9fac1), .A0(go53f58), .B1(fcbd6b), .B0(of65b65), .BI(ba1ecef), .BOUT1(bab7697), .BOUT0(), .S1(mtbb4bb), .S0(zkda5dd)); FSUB2 hbd2eea (.A1(tj13358), .A0(icc1b13), .B1(xwc0665), .B0(wlbeb5b), .BI(bab7697), .BOUT1(fcb89ca), .BOUT0(), .S1(uic4e53), .S0(lf27299)); FSUB2 cb394ce (.A1(ymb6573), .A0(jc58cb6), .B1(iea456), .B0(fa57824), .BI(fcb89ca), .BOUT1(aaa3086), .BOUT0(), .S1(sj18430), .S0(hbc2185)); FSUB2 ie10c2f (.A1(oha46d4), .A0(xw732a4), .B1(yz269f4), .B0(wwd4d46), .BI(aaa3086), .BOUT1(ofc3750), .BOUT0(), .S1(ng1ba85), .S0(thdd42b)); FSUB2 meea15f (.A1(hd131a8), .A0(god4b13), .B1(os5c36f), .B0(nr55112), .BI(ofc3750), .BOUT1(czc6875), .BOUT0(), .S1(qi343ac), .S0(yza1d60)); FSUB2 baeb04 (.A1(hd946ae), .A0(gb65982), .B1(hd946ae), .B0(hd946ae), .BI(czc6875), .BOUT1(), .BOUT0(), .S1(), .S0(ym15317)); VHI wya98b9 (.Z(ba1ecef)); FSUB2 me62e40 (.A1(dm5d28e), .A0(ep3c4d2), .B1(jr2245e), .B0(rv8448b), .BI(ba1ecef), .BOUT1(xlc1b3), .BOUT0(), .S1(ip60d9e), .S0(fp6cf4)); FSUB2 qv367a6 (.A1(dm661f6), .A0(qi981da), .B1(co3ebab), .B0(gb5ed3e), .BI(xlc1b3), .BOUT1(ria8eca), .BOUT0(), .S1(by47652), .S0(mg3b293)); FSUB2 ald9499 (.A1(nta586c), .A0(wlaea9b), .B1(lq6c8cd), .B0(irab06c), .BI(ria8eca), .BOUT1(jp6b496), .BOUT0(), .S1(rt5a4b6), .S0(vvd25b6)); FSUB2 uk92db6 (.A1(yk772c1), .A0(xwcff6d), .B1(rte6d59), .B0(ldcd5e6), .BI(jp6b496), .BOUT1(rv8b00c), .BOUT0(), .S1(ps58067), .S0(hoc033b)); FSUB2 fc19da (.A1(ou1abb8), .A0(vv55280), .B1(mg3409f), .B0(qg59f34), .BI(rv8b00c), .BOUT1(yz9f055), .BOUT0(), .S1(pfe6d6c), .S0(mec1564)); FSUB2 swab20 (.A1(hd946ae), .A0(ou82912), .B1(hd946ae), .B0(hd946ae), .BI(yz9f055), .BOUT1(), .BOUT0(), .S1(), .S0(zmad9e7)); AGEB2 ri30ecf (.A1(jr2245e), .A0(rv8448b), .B1(dm5d28e), .B0(ep3c4d2), .CI(yxe7e2a), .GE(wjd931f)); AGEB2 mrc98fd (.A1(co3ebab), .A0(gb5ed3e), .B1(dm661f6), .B0(qi981da), .CI(wjd931f), .GE(go6866d)); AGEB2 ui43369 (.A1(lq6c8cd), .A0(irab06c), .B1(nta586c), .B0(wlaea9b), .CI(go6866d), .GE(ip4ee59)); AGEB2 qg772cc (.A1(rte6d59), .A0(ldcd5e6), .B1(yk772c1), .B0(xwcff6d), .CI(ip4ee59), .GE(cb8227)); AGEB2 wj4113c (.A1(mg3409f), .A0(qg59f34), .B1(ou1abb8), .B0(vv55280), .CI(cb8227), .GE(zm25bea)); AGEB2 lf2df52 (.A1(hd946ae), .A0(ks15d28), .B1(hd946ae), .B0(je2fff9), .CI(zm25bea), .GE(lfb501b)); FADD2 jea80de (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(lfb501b), .COUT1(), .COUT0(), .S1(), .S0(mg3e8f6)); AGEB2 ipf7637 (.A1(kf9fac1), .A0(go53f58), .B1(fcbd6b), .B0(of65b65), .CI(ng9681a), .GE(wjedd33)); AGEB2 rt6e99c (.A1(tj13358), .A0(icc1b13), .B1(xwc0665), .B0(wlbeb5b), .CI(wjedd33), .GE(je3f115)); AGEB2 czf88ab (.A1(ymb6573), .A0(jc58cb6), .B1(iea456), .B0(fa57824), .CI(je3f115), .GE(cze8e6b)); AGEB2 lq4735c (.A1(oha46d4), .A0(xw732a4), .B1(yz269f4), .B0(wwd4d46), .CI(cze8e6b), .GE(kf1ddcf)); AGEB2 pseee7c (.A1(hd131a8), .A0(god4b13), .B1(os5c36f), .B0(nr55112), .CI(kf1ddcf), .GE(vx19296)); AGEB2 enc94b7 (.A1(hd946ae), .A0(yke0381), .B1(hd946ae), .B0(of5b9b5), .CI(vx19296), .GE(ofe76d1)); FADD2 ym3b68c (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(ofe76d1), .COUT1(), .COUT0(), .S1(), .S0(ec822fe)); AGEB2 ho420bc (.A1(kq6d84a[1]), .A0(kq6d84a[0]), .B1(ip60d9e), .B0(fp6cf4), .CI(yxe7e2a), .GE(db19146)); AGEB2 rtc8a37 (.A1(kq6d84a[3]), .A0(kq6d84a[2]), .B1(by47652), .B0(mg3b293), .CI(db19146), .GE(nefec36)); AGEB2 fnf61b2 (.A1(kq6d84a[5]), .A0(kq6d84a[4]), .B1(rt5a4b6), .B0(vvd25b6), .CI(nefec36), .GE(fpbf551)); AGEB2 uifaa8f (.A1(kq6d84a[7]), .A0(kq6d84a[6]), .B1(ps58067), .B0(hoc033b), .CI(fpbf551), .GE(shc3d28)); AGEB2 pu1e944 (.A1(kq6d84a[9]), .A0(kq6d84a[8]), .B1(pfe6d6c), .B0(mec1564), .CI(shc3d28), .GE(fc1bfa4)); AGEB2 fadfd23 (.A1(hd946ae), .A0(hbd2363), .B1(hd946ae), .B0(ui679d2), .CI(fc1bfa4), .GE(vida762)); FADD2 ald3b12 (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(vida762), .COUT1(), .COUT0(), .S1(), .S0(jr8bdda)); AGEB2 vi4716a (.A1(mtbb4bb), .A0(zkda5dd), .B1(xw6c250[1]), .B0(xw6c250[0]), .CI(ng9681a), .GE(ep9f7e1)); AGEB2 tufbf0c (.A1(uic4e53), .A0(lf27299), .B1(xw6c250[3]), .B0(xw6c250[2]), .CI(ep9f7e1), .GE(tj13cb0)); AGEB2 lf9e587 (.A1(sj18430), .A0(hbc2185), .B1(xw6c250[5]), .B0(xw6c250[4]), .CI(tj13cb0), .GE(nef45c0)); AGEB2 zma2e02 (.A1(ng1ba85), .A0(thdd42b), .B1(xw6c250[7]), .B0(xw6c250[6]), .CI(nef45c0), .GE(vk9c4af)); AGEB2 ene257b (.A1(qi343ac), .A0(yza1d60), .B1(xw6c250[9]), .B0(xw6c250[8]), .CI(vk9c4af), .GE(wwe59b4)); AGEB2 mt2cda0 (.A1(hd946ae), .A0(ym15317), .B1(hd946ae), .B0(hd946ae), .CI(wwe59b4), .GE(qv23932)); VLO vx1c995 (.Z(hd946ae)); FADD2 kf26572 (.A1(hd946ae), .A0(hd946ae), .B1(hd946ae), .B0(hd946ae), .CI(qv23932), .COUT1(), .COUT0(), .S1(), .S0(vxb5b5d)); assign vx941f = wjf8aab; assign th4a0fe = jra069c; - -always@* begin ng14a7f<={wlabdde>>1,jea8e7a[0]};lfa53fa<=jea8e7a[1];gd29fd7<=jea8e7a[2];th4febc<=jea8e7a[3];cz7f5e6<=jea8e7a[4];wwfaf35<=jea8e7a[5];zxd79a8<=jea8e7a[6];ecbcd47<={kq6d84a>>1,jea8e7a[7]};pfe6a39<={xw6c250>>1,jea8e7a[8]};end -always@* begin ls351cf[2047]<=uv5eef5;ls351cf[2046]<=wjf77ad;ls351cf[2044]<=yzbbd6d;ls351cf[2040]<=medeb6c;ls351cf[2032]<=icf5b61;ls351cf[2016]<=puadb09;ls351cf[1984]<=kq6d84a[0];ls351cf[1920]<=xw6c250[0];ls351cf[1023]<=wlabdde[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[0]};lfa53fa<=jea8e7a[1];gd29fd7<=jea8e7a[2];th4febc<=jea8e7a[3];cz7f5e6<=jea8e7a[4];wwfaf35<=jea8e7a[5];zxd79a8<=jea8e7a[6];ecbcd47<={kq6d84a>>1,jea8e7a[7]};pfe6a39<={xw6c250>>1,jea8e7a[8]};end -always@* begin ls351cf[2047]<=uv5eef5;ls351cf[2046]<=wjf77ad;ls351cf[2044]<=yzbbd6d;ls351cf[2040]<=medeb6c;ls351cf[2032]<=icf5b61;ls351cf[2017]<=puadb09;ls351cf[1987]<=kq6d84a[0];ls351cf[1926]<=xw6c250[0];ls351cf[1023]<=wlabdde[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[0]};lfa53fa<=jea8e7a[1];gd29fd7<=jea8e7a[2];th4febc<=jea8e7a[3];cz7f5e6<=jea8e7a[4];wwfaf35<=jea8e7a[5];zxd79a8<=jea8e7a[6];ecbcd47<={kq6d84a>>1,jea8e7a[7]};pfe6a39<={xw6c250>>1,jea8e7a[8]};qgf59ea<=jea8e7a[9];aaacf51<=jea8e7a[10];ui67a88<=jea8e7a[11];bn3d441<=jea8e7a[12];kqea20e<=jea8e7a[13];yx51070<=jea8e7a[14];wy88385<=jea8e7a[15];al41c28<=jea8e7a[16];fce145<=jea8e7a[17];yx70a2b<=jea8e7a[18];oh8515d<=jea8e7a[19];lf28aec<=jea8e7a[20];hb45766<=jea8e7a[21];ec2bb36<=jea8e7a[22];fa5d9b1<=jea8e7a[23];dzecd8a<=jea8e7a[24];tu66c56<=jea8e7a[25];sj362b3<=jea8e7a[26];sjb159d<=jea8e7a[27];oh8acec<=jea8e7a[28];me56764<=jea8e7a[29];aab3b20<=jea8e7a[30];ym9d900<=jea8e7a[31];zxec800<=jea8e7a[32];pf64006<=jea8e7a[33];ls20037<=jea8e7a[34];ec1bb<=jea8e7a[35];gqdd8<=jea8e7a[36];db6ec1<=jea8e7a[37];bn3760e<=jea8e7a[38];mtbb077<=jea8e7a[39];bld83bd<=jea8e7a[40];ykc1def<=jea8e7a[41];puef79<=jea8e7a[42];ui77bca<=jea8e7a[43];dobde50<=jea8e7a[44];eaef283<=jea8e7a[45];by79418<=jea8e7a[46];lqca0c2<=jea8e7a[47];vv50613<=jea8e7a[48];zm8309f<=jea8e7a[49];yz184fb<=jea8e7a[50];dzc27dd<=jea8e7a[51];fp13eef<=jea8e7a[52];cb9f77f<=jea8e7a[53];dmfbbfc<=jea8e7a[54];dzddfe2<=jea8e7a[55];kqeff16<=jea8e7a[56];cz7f8b1<=jea8e7a[57];vvfc58c<=jea8e7a[58];qte2c66<=jea8e7a[59];vx16335<=jea8e7a[60];wlb19ae<=jea8e7a[61];xy8cd75<=jea8e7a[62];lq66bab<=jea8e7a[63];fc35d5b<=jea8e7a[64];sjaeadb<=jea8e7a[65];of756dd<=jea8e7a[66];irab6ec<=jea8e7a[67];ip5b764<=jea8e7a[68];ykdbb24<=jea8e7a[69];dzdd921<=jea8e7a[70];nrec90e<=jea8e7a[71];xj64876<=jea8e7a[72];sw243b6<=jea8e7a[73];ie21db1<=jea8e7a[74];doed88<=jea8e7a[75];dm76c42<=jea8e7a[76];wyb6212<=jea8e7a[77];yzb1091<=jea8e7a[78];ie8848c<=jea8e7a[79];rg42460<=jea8e7a[80];mt12303<=jea8e7a[81];db9181c<=jea8e7a[82];hq8c0e6<=jea8e7a[83];kd60732<=jea8e7a[84];zz3995<=jea8e7a[85];vx1ccae<=jea8e7a[86];ble6576<=jea8e7a[87];bn32bb6<=jea8e7a[88];ir95db6<=jea8e7a[89];wlaedb4<=jea8e7a[90];tu76da5<=jea8e7a[91];ukb6d2a<=jea8e7a[92];cob6950<=jea8e7a[93];qvb4a80<=jea8e7a[94];dba5405<=jea8e7a[95];tw2a02f<=jea8e7a[96];th5017a<=jea8e7a[97];kf80bd7<=jea8e7a[98];gq5ebd<=jea8e7a[99];ba2f5e9<=jea8e7a[100];en7af4a<=jea8e7a[101];ldd7a54<=jea8e7a[102];xybd2a7<=jea8e7a[103];hbe953a<=jea8e7a[104];fn4a9d7<=jea8e7a[105];uv54ebe<=jea8e7a[106];nga75f4<=jea8e7a[107];ri3afa2<=jea8e7a[108];ldd7d12<=jea8e7a[109];yzbe897<=jea8e7a[110];nef44bc<=jea8e7a[111];zma25e2<=jea8e7a[112];kf12f12<=jea8e7a[113];ou97895<=jea8e7a[114];ukbc4a9<=jea8e7a[115];ipe2548<=jea8e7a[116];ep12a44<=jea8e7a[117];ux95225<=jea8e7a[118];qia912d<=jea8e7a[119];xw48969<=jea8e7a[120];mr44b4b<=jea8e7a[121];xy25a5d<=jea8e7a[122];vx2d2ea<=jea8e7a[123];lq69757<=jea8e7a[124];kd4babb<=jea8e7a[125];ho5d5dc<=jea8e7a[126];uieaee3<=jea8e7a[127];dm57719<=jea8e7a[128];irbb8ca<=jea8e7a[129];qtdc654<=jea8e7a[130];rte32a5<=jea8e7a[131];zz1952e<=jea8e7a[132];jcca977<=jea8e7a[133];al54bba<=jea8e7a[134];lfa5dd4<=jea8e7a[135];aa2eea6<=jea8e7a[136];yk77531<=jea8e7a[137];phba989<=jea8e7a[138];sud4c4e<=jea8e7a[139];wya6270<=jea8e7a[140];ks31380<=jea8e7a[141];ba89c00<=jea8e7a[142];sh4e003<=jea8e7a[143];yx7001d<=jea8e7a[144];kf800ec<=jea8e7a[145];co764<=jea8e7a[146];tj3b20<=jea8e7a[147];yz1d906<=jea8e7a[148];zxec834<=jea8e7a[149];pf641a6<=jea8e7a[150];ls20d37<=jea8e7a[151];db69ba<=jea8e7a[152];ym34dd6<=jea8e7a[153];mga6eb1<=jea8e7a[154];ph37589<=jea8e7a[155];vxbac4f<=jea8e7a[156];qtd627e<=jea8e7a[157];irb13f4<=jea8e7a[158];ls89fa4<=jea8e7a[159];vv4fd23<=jea8e7a[160];th7e91e<=jea8e7a[161];zkf48f6<=jea8e7a[162];wla47b3<=jea8e7a[163];qv23d9d<=jea8e7a[164];tw1eced<=jea8e7a[165];pff676b<=jea8e7a[166];swb3b5f<=jea8e7a[167];mg9daf8<=jea8e7a[168];gbed7c0<=jea8e7a[169];xj6be05<=jea8e7a[170];dz5f02f<=jea8e7a[171];mrf817e<=jea8e7a[172];vic0bf4<=jea8e7a[173];qi5fa3<=jea8e7a[174];do2fd19<=jea8e7a[175];zx7e8cb<=jea8e7a[176];vif465e<=jea8e7a[177];ksa32f2<=jea8e7a[178];vx19790<=jea8e7a[179];cmcbc87<=jea8e7a[180];wj5e438<=jea8e7a[181];ipf21c4<=jea8e7a[182];qv90e25<=jea8e7a[183];gq8712c<=jea8e7a[184];db38961<=jea8e7a[185];eac4b0f<=jea8e7a[186];ls25879<=jea8e7a[187];cb2c3ca<=jea8e7a[188];rt61e55<=jea8e7a[189];wyf2ae<=jea8e7a[190];dm79571<=jea8e7a[191];bycab8a<=jea8e7a[192];pf55c52<=jea8e7a[193];anae296<=jea8e7a[194];xj714b4<=jea8e7a[195];cb8a5a6<=jea8e7a[196];zk52d35<=jea8e7a[197];fc969ab<=jea8e7a[198];cbb4d5b<=jea8e7a[199];swa6add<=jea8e7a[200];je356e9<=jea8e7a[201];uxab74a<=jea8e7a[202];al5ba54<=jea8e7a[203];thdd2a5<=jea8e7a[204];pfe952f<=jea8e7a[205];rt4a97f<=jea8e7a[206];mr54bfe<=jea8e7a[207];dba5ff4<=jea8e7a[208];pu2ffa6<=jea8e7a[209];qt7fd33<=jea8e7a[210];byfe99c<=jea8e7a[211];lqf4ce2<=jea8e7a[212];mga6713<=jea8e7a[213];kf33898<=jea8e7a[214];ba9c4c4<=jea8e7a[215];ale2623<=jea8e7a[216];tj1311c<=jea8e7a[217];ec988e6<=jea8e7a[218];suc4730<=jea8e7a[219];qv23980<=jea8e7a[220];vx1cc05<=jea8e7a[221];ble602e<=jea8e7a[222];zm30176<=jea8e7a[223];sj80bb2<=jea8e7a[224];sw5d95<=jea8e7a[225];sw2eca9<=jea8e7a[226];ne76549<=jea8e7a[227];dob2a4b<=jea8e7a[228];yz9525a<=jea8e7a[229];wya92d5<=jea8e7a[230];su496a9<=jea8e7a[231];uv4b548<=jea8e7a[232];pf5aa45<=jea8e7a[233];hod522f<=jea8e7a[234];qia917b<=jea8e7a[235];xw48bd9<=jea8e7a[236];nr45ecb<=jea8e7a[237];fc2f65f<=jea8e7a[238];ld7b2fa<=jea8e7a[239];shd97d7<=jea8e7a[240];eacbebd<=jea8e7a[241];nr5f5e8<= -jea8e7a[242];mefaf46<=jea8e7a[243];xjd7a30<=jea8e7a[244];pubd187<=jea8e7a[245];uve8c3a<=jea8e7a[246];yk461d4<=jea8e7a[247];pu30ea1<=jea8e7a[248];sw8750b<=jea8e7a[249];tw3a859<=jea8e7a[250];ykd42ca<=jea8e7a[251];yza1651<=jea8e7a[252];fcb28d<=jea8e7a[253];ww5946b<=jea8e7a[254];lqca359<=jea8e7a[255];uv51acb<=jea8e7a[256];mg8d65c<=jea8e7a[257];zx6b2e0<=jea8e7a[258];me59706<=jea8e7a[259];iccb831<=jea8e7a[260];qg5c188<=jea8e7a[261];ose0c41<=jea8e7a[262];bn6208<=jea8e7a[263];mg31047<=jea8e7a[264];qi88238<=jea8e7a[265];en411c0<=jea8e7a[266];ir8e04<=jea8e7a[267];vi47025<=jea8e7a[268];tj3812b<=jea8e7a[269];zkc095e<=jea8e7a[270];xy4af3<=jea8e7a[271];hq2579b<=jea8e7a[272];ym2bcdb<=jea8e7a[273];kd5e6d9<=jea8e7a[274];rtf36cc<=jea8e7a[275];lf9b667<=jea8e7a[276];wwdb33e<=jea8e7a[277];ipd99f0<=jea8e7a[278];alccf84<=jea8e7a[279];ic67c25<=jea8e7a[280];gq3e129<=jea8e7a[281];cmf0949<=jea8e7a[282];vx84a49<=jea8e7a[283];ri2524f<=jea8e7a[284];cb2927b<=jea8e7a[285];os493dd<=jea8e7a[286];me49ee8<=jea8e7a[287];dz4f741<=jea8e7a[288];jp7ba0f<=jea8e7a[289];zxdd07e<=jea8e7a[290];kde83f7<=jea8e7a[291];cz41fbd<=jea8e7a[292];ukfded<=jea8e7a[293];ld7ef68<=jea8e7a[294];off7b46<=jea8e7a[295];hqbda34<=jea8e7a[296];mred1a3<=jea8e7a[297];qg68d1d<=jea8e7a[298];su468e8<=jea8e7a[299];ou34740<=jea8e7a[300];gqa3a00<=jea8e7a[301];sj1d001<=jea8e7a[302];gbe800d<=jea8e7a[303];xj4006d<=jea8e7a[304];co36e<=jea8e7a[305];ri1b70<=jea8e7a[306];end -always@* begin ls351cf[2047]<=uv5eef5;ls351cf[2046]<=wjf77ad;ls351cf[2044]<=yzbbd6d;ls351cf[2043]<=ui4cc84;ls351cf[2040]<=medeb6c;ls351cf[2038]<=fp6cf4;ls351cf[2032]<=icf5b61;ls351cf[2029]<=ba1ecef;ls351cf[2017]<=puadb09;ls351cf[2013]<=gbc9d60;ls351cf[2010]<=ip60d9e;ls351cf[2003]<=vida762;ls351cf[1990]<=cb8f428;ls351cf[1987]<=kq6d84a[0];ls351cf[1982]<=mrf7047;ls351cf[1980]<=faf17e3;ls351cf[1979]<=pha52c3;ls351cf[1973]<=mg3b293;ls351cf[1963]<=xl3288f;ls351cf[1958]<=ng9681a;ls351cf[1957]<=gb659f7;ls351cf[1953]<=wlbeb5b;ls351cf[1942]<=wy1adf6;ls351cf[1932]<=db8bad3;ls351cf[1929]<=mtbb4bb;ls351cf[1926]<=xw6c250[0];ls351cf[1923]<=ep95d19;ls351cf[1921]<=hda5898;ls351cf[1917]<=fc1bfa4;ls351cf[1914]<=kqe59b1;ls351cf[1913]<=ph8bf1a;ls351cf[1911]<=qv2ca61;ls351cf[1903]<=qt6af36;ls351cf[1898]<=xlc1b3;ls351cf[1879]<=db9447e;ls351cf[1876]<=hoe153c;ls351cf[1872]<=godb92b;ls351cf[1868]<=tw837a6;ls351cf[1866]<=epa4d3e;ls351cf[1863]<=vx19296;ls351cf[1858]<=xwc0665;ls351cf[1837]<=mrd6fb1;ls351cf[1816]<=kf9ad77;ls351cf[1810]<=lf27299;ls351cf[1805]<=fcb2d03;ls351cf[1802]<=qg4c66b;ls351cf[1799]<=qv8079b;ls351cf[1795]<=mg98d46;ls351cf[1786]<=ui679d2;ls351cf[1783]<=off8f7c;ls351cf[1780]<=jpd2934;ls351cf[1778]<=xj5f8d6;ls351cf[1775]<=mt2961f;ls351cf[1770]<=ks5795;ls351cf[1758]<=cb36acf;ls351cf[1748]<=by47652;ls351cf[1710]<=lsa23f7;ls351cf[1704]<=bn9058;ls351cf[1701]<=ou1abb8;ls351cf[1699]<=rt5a4b6;ls351cf[1696]<=ea62604;ls351cf[1689]<=kf85586;ls351cf[1685]<=lqe4221;ls351cf[1679]<=uvfd60d;ls351cf[1678]<=of5b9b5;ls351cf[1668]<=icc1b13;ls351cf[1627]<=fcb7d8d;ls351cf[1624]<=ou82912;ls351cf[1605]<=uka31d0;ls351cf[1589]<=yk772c1;ls351cf[1584]<=kd6a9bf;ls351cf[1573]<=bab7697;ls351cf[1572]<=rv8448b;ls351cf[1567]<=aa24809;ls351cf[1562]<=ls9cfc5;ls351cf[1557]<=ba93757;ls351cf[1556]<=db19146;ls351cf[1551]<=zz32fe6;ls351cf[1548]<=ir1d393;ls351cf[1543]<=cm46112;ls351cf[1524]<=hbd2363;ls351cf[1521]<=qgffb9a;ls351cf[1519]<=al7fc5f;ls351cf[1513]<=ip44761;ls351cf[1512]<=kf9fac1;ls351cf[1509]<=vvfc6b7;ls351cf[1504]<=tw35400;ls351cf[1502]<=ip65837;ls351cf[1499]<=ho58364;ls351cf[1493]<=wjcc527;ls351cf[1492]<=tjc95d;ls351cf[1469]<=lqcf9a0;ls351cf[1466]<=ep23a0c;ls351cf[1448]<=vvd25b6;ls351cf[1421]<=ip4ee59;ls351cf[1417]<=ep3c4d2;ls351cf[1415]<=wjf8778;ls351cf[1404]<=zx7b094;ls351cf[1402]<=fcbd6b;ls351cf[1400]<=ym8808d;ls351cf[1398]<=pff69f5;ls351cf[1377]<=lf946e3;ls351cf[1374]<=mt8fd07;ls351cf[1373]<=ykff2e0;ls351cf[1361]<=gd188e6;ls351cf[1359]<=yza1d60;ls351cf[1355]<=of51cff;ls351cf[1354]<=qg59f34;ls351cf[1350]<=hoc033b;ls351cf[1349]<=pha0bb8;ls351cf[1344]<=co31697;ls351cf[1343]<=qi343ac;ls351cf[1341]<=fpbf551;ls351cf[1330]<=do2ac34;ls351cf[1326]<=sud174a;ls351cf[1323]<=tuee7bc;ls351cf[1322]<=zm25bea;ls351cf[1310]<=sjd899;ls351cf[1308]<=yke0381;ls351cf[1305]<=ps58067;ls351cf[1301]<=qi3125d;ls351cf[1289]<=tj13358;ls351cf[1286]<=wwe59b4;ls351cf[1280]<=tw354c3;ls351cf[1279]<=czc6875;ls351cf[1271]<=ieb67b8;ls351cf[1224]<=fpb0d18;ls351cf[1210]<=dob2607;ls351cf[1207]<=db22415;ls351cf[1201]<=hb7191b;ls351cf[1199]<=jra069c;ls351cf[1195]<=ks15d28;ls351cf[1193]<=thdd42b;ls351cf[1163]<=gb5ed3e;ls351cf[1162]<=wl18e80;ls351cf[1155]<=wwd4d46;ls351cf[1144]<=ipc65b2;ls351cf[1136]<=ofe76d1;ls351cf[1130]<=ldcd5e6;ls351cf[1125]<=rv8b00c;ls351cf[1120]<=mr6fa1c;ls351cf[1112]<=wlaea9b;ls351cf[1110]<=fa4211d;ls351cf[1104]<=zkd013b;ls351cf[1098]<=uic4e53;ls351cf[1096]<=jr2245e;ls351cf[1086]<=xy2afad;ls351cf[1076]<=ykff9d5;ls351cf[1067]<=kdd6f0e;ls351cf[1065]<=rv19ac2;ls351cf[1060]<=fa57824;ls351cf[1054]<=ym2e1ac;ls351cf[1053]<=oha46d4;ls351cf[1051]<=vxb5b5d;ls351cf[1048]<=mg92ffd;ls351cf[1039]<=meef7c0;ls351cf[1026]<=gqbc45e;ls351cf[1023]<=wlabdde[0];ls351cf[1021]<=an29990;ls351cf[1006]<=lqf4a58;ls351cf[1001]<=jr8bdda;ls351cf[995]<=hq2a714;ls351cf[991]<=jr9ee08;ls351cf[990]<=dmfe2fc;ls351cf[981]<=ph6511;ls351cf[978]<=jr949a7;ls351cf[976]<=wjedd33;ls351cf[971]<=rte35be;ls351cf[964]<=zkda5dd;ls351cf[961]<=pub7827;ls351cf[960]<=ep236a5;ls351cf[957]<=wl9a526;ls351cf[951]<=hb6466a;ls351cf[938]<=qgc120b;ls351cf[936]<=thf328f;ls351cf[931]<=hd131a8;ls351cf[901]<=ba898cd;ls351cf[891]<=tja04f8;ls351cf[885]<=os6dbe6;ls351cf[850]<=vv55280;ls351cf[849]<=ria8eca;ls351cf[839]<=yz29b02;ls351cf[812]<=yz9f055;ls351cf[802]<=tj13cb0;ls351cf[794]<=xwcff6d;ls351cf[786]<=dm5d28e;ls351cf[783]<=wjdc2f5;ls351cf[778]<=ph133cc;ls351cf[774]<=cbb1391;ls351cf[760]<=je18d7;ls351cf[756]<=go53f58;ls351cf[752]<=ri3fdd6;ls351cf[749]<=suf5d58;ls351cf[746]<=ne58241;ls351cf[733]<=gq82e31;ls351cf[710]<=lq6c8cd;ls351cf[708]<=wj44e94;ls351cf[707]<=hqad6a9;ls351cf[702]<=gb44fd5;ls351cf[701]<=of65b65;ls351cf[700]<=lq7c001;ls351cf[699]<=mt122f6;ls351cf[688]<=aa2ee58;ls351cf[687]<=lfb501b;ls351cf[679]<=ng1ba85;ls351cf[677]<=ld61cba;ls351cf[674]<=ne482c6;ls351cf[671]<=ofc3750;ls351cf[670]<=zxc2db3;ls351cf[663]<=ipfd144;ls351cf[661]<=mg3409f;ls351cf[652]<=jp6b496;ls351cf[650]<=ayef977;ls351cf[643]<=ph276eb;ls351cf[640]<=ou3ee1e;ls351cf[639]<=ym15317;ls351cf[635]<=ymb6cf7;ls351cf[612]<=ep9f7e1;ls351cf[605]<=ks24da8;ls351cf[599]<=wjf8aab;ls351cf[597]<=je2fff9;ls351cf[596]<=sj18430;ls351cf[581]<=dm661f6;ls351cf[577]<=cze8e6b;ls351cf[572]<=fc99ac6;ls351cf[568]<=ec822fe;ls351cf[562]<=mec1564;ls351cf[556]<=go6866d;ls351cf[555]<=zk7cbb9;ls351cf[552]<=zm3a027;ls351cf[530]<=je3f115;ls351cf[526]<=xw732a4;ls351cf[525]<=cmdbaf1;ls351cf[513]<=jrb034c;ls351cf[510]<=gb65982;ls351cf[503]<=swa3f17;ls351cf[495]<=shc3d28;ls351cf[490]<=ouca2;ls351cf[482]<=pu2a660;ls351cf[480]<=fc99523;ls351cf[465]<=god4b13;ls351cf[450]<=mtaeb3b;ls351cf[425]<=cb8227;ls351cf[419]<=sh4b0fd;ls351cf[406]<=zmad9e7;ls351cf[401]<=ri868c7;ls351cf[389]<=kd4e139;ls351cf[387]<=dz61daf;ls351cf[373]<=sw599f;ls351cf[366]<=pu3a9c4;ls351cf[355]<=irab06c;ls351cf[354]<=hq8c8df;ls351cf[351]<=zk5d4fd;ls351cf[350]<=qi2e38b;ls351cf[344]<=by58d6a;ls351cf[343]<=mg3e8f6;ls351cf[339]<=aaa3086;ls351cf[338]<=qgcb6ee;ls351cf[335]<=rg585b6;ls351cf[321]<=ba4edd;ls351cf[298]<=fcb89ca;ls351cf[290]<=qi981da;ls351cf[288]<=ymb6573;ls351cf[278]<=co3ebab;ls351cf[276]<=nef45c0;ls351cf[263]<=yz269f4;ls351cf[251]<=ou3e94b;ls351cf[245]<=fac0194;ls351cf[241]<=an9f1ef;ls351cf[240]<=ngb2b99;ls351cf[232]<=os5c36f;ls351cf[225]<=yxe7e2a;ls351cf[212]<=rte6d59;ls351cf[209]<=uka97bb;ls351cf[203]<=pfe6d6c;ls351cf[194]<=baa8c22;ls351cf[193]<=dz4518e;ls351cf[177]<=nta586c;ls351cf[175]<=czf22b3;ls351cf[172]<=yke5dcb;ls351cf[169]<=vv6ee2f;ls351cf[167]<=nefec36;ls351cf[160]<=vk9c4af;ls351cf[149]<=hbc2185;ls351cf[145]<=wjd931f;ls351cf[144]<=jc58cb6;ls351cf[125]<=yx416b2;ls351cf[122]<=kdf8032;ls351cf[120]<=ym82969;ls351cf[116]<=nr55112;ls351cf[109]<=hd946ae;ls351cf[104]<=gb41632;ls351cf[97]<=uv6fd78;ls351cf[87]<=tjbf2b7;ls351cf[84]<=sw5867;ls351cf[83]<=vvcd616;ls351cf[72]<=iea456;ls351cf[61]<=tudf006;ls351cf[60]<=nt8efed; -ls351cf[58]<=kf1ddcf;ls351cf[54]<=qv23932;ls351cf[48]<=al752c3;ls351cf[42]<=me78221;ls351cf[30]<=pf7be00;ls351cf[21]<=qgcb534;ls351cf[10]<=ld5a8a4;ls351cf[5]<=qv23d0e;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[1]};aa98036<=jea8e7a[2];rgc01b1<={zz38f51>>1,jea8e7a[3]};gqd8a<=jea8e7a[4];db6c51<=jea8e7a[5];an3628e<={ic59746>>1,jea8e7a[6]};epb1475<={cmcba31>>1,jea8e7a[7]};gd8a3ac<={vi5d188>>1,jea8e7a[8]};gb51d65<={ene8c43>>1,jea8e7a[9]};hd8eb2c<={ay4621c>>1,jea8e7a[10]};kd75966<={ec310e1>>1,jea8e7a[11]};ecacb35<=jea8e7a[12];cz659a8<=jea8e7a[13];ir2cd44<=jea8e7a[14];ho66a24<=jea8e7a[15];zm35123<={kf803b>>1,jea8e7a[16]};ria891a<=jea8e7a[17];cz448d2<=jea8e7a[18];uk24695<={kf7731>>1,jea8e7a[19]};an234a9<=jea8e7a[20];qi1a54c<=jea8e7a[21];nrd2a60<={pfe6344>>1,jea8e7a[22]};oh95307<=jea8e7a[23];uka983d<=jea8e7a[24];yk4c1e8<=jea8e7a[25];qt60f40<=jea8e7a[26];qv7a04<=jea8e7a[27];bn3d024<={ie3102c>>1,jea8e7a[28]};mre8126<=jea8e7a[29];th40935<=jea8e7a[30];ba49af<=jea8e7a[31];mg24d7b<=jea8e7a[32];kf26bd8<=jea8e7a[33];xy35ec5<=jea8e7a[34];hdaf62b<=jea8e7a[35];bl7b15e<=jea8e7a[36];rtd8af7<=jea8e7a[37];tuc57be<={ea6d36f>>1,jea8e7a[38]};wy2bdf2<=jea8e7a[39];uv5ef91<=jea8e7a[40];wjf7c8d<=jea8e7a[41];uxbe46c<=jea8e7a[42];mrf2365<=jea8e7a[43];xl91b2d<=jea8e7a[44];ks8d96e<=jea8e7a[45];lq6cb71<=jea8e7a[46];gb65b8a<=jea8e7a[47];end -always@* begin ls351cf[2047]<=hod0e3d[0];ls351cf[2046]<=force_isolate;ls351cf[2044]<=zz38f51[0];ls351cf[2040]<=blc7a8f;ls351cf[2032]<=lf3d47e;ls351cf[2017]<=ic59746[0];ls351cf[1987]<=cmcba31[0];ls351cf[1926]<=vi5d188[0];ls351cf[1805]<=mt7369;ls351cf[1804]<=ene8c43[0];ls351cf[1803]<=gq31a26;ls351cf[1761]<=qv2c039;ls351cf[1668]<=mr6f298;ls351cf[1562]<=yz39b4d;ls351cf[1560]<=ay4621c[0];ls351cf[1558]<=ym8d131;ls351cf[1550]<=kf803b[0];ls351cf[1475]<=yx601cd;ls351cf[1464]<=jp40b00;ls351cf[1288]<=ne794c4;ls351cf[1076]<=thcda6d;ls351cf[1072]<=ec310e1[0];ls351cf[1069]<=os68988;ls351cf[1056]<=go53113;ls351cf[1052]<=jp401dc;ls351cf[1023]<=gbe_mode;ls351cf[902]<=ece6d;ls351cf[901]<=pfe6344[0];ls351cf[880]<=ym5807;ls351cf[834]<=cm6de53;ls351cf[775]<=fae1007;ls351cf[732]<=ks88160;ls351cf[528]<=dmca622;ls351cf[450]<=aldcc68;ls351cf[417]<=jc4dbca;ls351cf[387]<=fp1c200;ls351cf[366]<=ie3102c[0];ls351cf[225]<=gq3b98d;ls351cf[208]<=fa69b79;ls351cf[193]<=kq43840;ls351cf[183]<=mt26205;ls351cf[128]<=suc44c0;ls351cf[112]<=kf7731[0];ls351cf[104]<=ea6d36f[0];ls351cf[96]<=ec88708;ls351cf[91]<=en44c40;ls351cf[64]<=ec98898;ls351cf[56]<=ukee6;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[2]};gqd8a<=jea8e7a[3];db6c51<=jea8e7a[4];zk42a46<=jea8e7a[5];sw15232<=jea8e7a[6];aaa9191<={vi7928a>>1,jea8e7a[7]};an3628e<={ic59746>>1,jea8e7a[8]};epb1475<={cmcba31>>1,jea8e7a[9]};gd8a3ac<={vi5d188>>1,jea8e7a[10]};gb51d65<={ene8c43>>1,jea8e7a[11]};hd8eb2c<={ay4621c>>1,jea8e7a[12]};kd75966<={ec310e1>>1,jea8e7a[13]};ecacb35<=jea8e7a[14];cz659a8<=jea8e7a[15];ir2cd44<=jea8e7a[16];ho66a24<=jea8e7a[17];ba49af<=jea8e7a[18];mg24d7b<=jea8e7a[19];jc42a1b<=jea8e7a[20];rtd8af7<=jea8e7a[21];tuc57be<={ea6d36f>>1,jea8e7a[22]};wy2bdf2<=jea8e7a[23];ls1b459<=jea8e7a[24];xwda2ca<=jea8e7a[25];th40935<=jea8e7a[26];zm35123<={kf803b>>1,jea8e7a[27]};cz448d2<=jea8e7a[28];ria891a<=jea8e7a[29];fa523cb<=jea8e7a[30];zz91e5a<=jea8e7a[31];bn3d024<={ie3102c>>1,jea8e7a[32]};qv7a04<=jea8e7a[33];qt60f40<=jea8e7a[34];pf5ad51<=jea8e7a[35];ipd6a8f<=jea8e7a[36];bnb547d<={dz64739>>1,jea8e7a[37]};jraa3ee<=jea8e7a[38];qt51f76<=jea8e7a[39];ir8fbb4<=jea8e7a[40];qg7dda4<=jea8e7a[41];bl7b15e<=jea8e7a[42];xy35ec5<=jea8e7a[43];anb485a<=jea8e7a[44];uv5ef91<=jea8e7a[45];wjf7c8d<=jea8e7a[46];uxbe46c<=jea8e7a[47];mrf2365<=jea8e7a[48];xl91b2d<=jea8e7a[49];ks8d96e<=jea8e7a[50];lq6cb71<=jea8e7a[51];gb65b8a<=jea8e7a[52];end -always@* begin ls351cf[2047]<=force_isolate;ls351cf[2046]<=zz38f51[0];ls351cf[2044]<=blc7a8f;ls351cf[2041]<=lf3d47e;ls351cf[2034]<=do20bc9;ls351cf[2021]<=ou5e4a;ls351cf[2017]<=thcda6d;ls351cf[1995]<=vi7928a[0];ls351cf[1986]<=ea6d36f[0];ls351cf[1943]<=ic59746[0];ls351cf[1925]<=fa69b79;ls351cf[1908]<=mt26205;ls351cf[1864]<=dz64739[0];ls351cf[1855]<=fp1c200;ls351cf[1838]<=cmcba31[0];ls351cf[1803]<=kqfa2f5;ls351cf[1769]<=en44c40;ls351cf[1680]<=ux239cf;ls351cf[1662]<=fae1007;ls351cf[1628]<=vi5d188[0];ls351cf[1583]<=go53113;ls351cf[1559]<=icd17a9;ls351cf[1501]<=mr4ea09;ls351cf[1490]<=hd991c;ls351cf[1487]<=ec88708;ls351cf[1312]<=bn1ce7d;ls351cf[1276]<=ym5807;ls351cf[1209]<=ene8c43[0];ls351cf[1155]<=mt39f74;ls351cf[1118]<=ec98898;ls351cf[1070]<=jp40b00;ls351cf[1048]<=byee951;ls351cf[1023]<=gbe_mode;ls351cf[1008]<=god13fa;ls351cf[954]<=ie3102c[0];ls351cf[932]<=me4c8e7;ls351cf[927]<=kq43840;ls351cf[791]<=dmca622;ls351cf[750]<=kq49d41;ls351cf[743]<=ec310e1[0];ls351cf[577]<=wje73ee;ls351cf[524]<=ece6d;ls351cf[504]<=qv2c039;ls351cf[395]<=ne794c4;ls351cf[375]<=jp401dc;ls351cf[371]<=ay4621c[0];ls351cf[262]<=yz39b4d;ls351cf[197]<=mr6f298;ls351cf[189]<=suc44c0;ls351cf[187]<=ukee6;ls351cf[98]<=cm6de53;ls351cf[93]<=kf803b[0];ls351cf[49]<=jc4dbca;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[3]};gqd8a<=jea8e7a[4];db6c51<=jea8e7a[5];epa1d8f<={zz38960>>1,jea8e7a[6]};an3628e<={ic59746>>1,jea8e7a[7]};epb1475<={cmcba31>>1,jea8e7a[8]};gd8a3ac<={vi5d188>>1,jea8e7a[9]};gb51d65<={ene8c43>>1,jea8e7a[10]};hd8eb2c<={ay4621c>>1,jea8e7a[11]};kd75966<={ec310e1>>1,jea8e7a[12]};ecacb35<=jea8e7a[13];cz659a8<=jea8e7a[14];ir2cd44<=jea8e7a[15];ho66a24<=jea8e7a[16];tuc57be<={ea6d36f>>1,jea8e7a[17]};wy2bdf2<=jea8e7a[18];ls1b459<=jea8e7a[19];th40935<=jea8e7a[20];zm35123<={kf803b>>1,jea8e7a[21]};cz448d2<=jea8e7a[22];ria891a<=jea8e7a[23];uv5ef91<=jea8e7a[24];wjf7c8d<=jea8e7a[25];uxbe46c<=jea8e7a[26];mrf2365<=jea8e7a[27];xl91b2d<=jea8e7a[28];ks8d96e<=jea8e7a[29];lq6cb71<=jea8e7a[30];gb65b8a<=jea8e7a[31];end -always@* begin ls351cf[2047]<=db3242c;ls351cf[2046]<=force_isolate;ls351cf[2044]<=zz38f51[0];ls351cf[2040]<=blc7a8f;ls351cf[2032]<=lf3d47e;ls351cf[2017]<=zz38960[0];ls351cf[1987]<=ic59746[0];ls351cf[1926]<=cmcba31[0];ls351cf[1804]<=vi5d188[0];ls351cf[1803]<=jp401dc;ls351cf[1560]<=ene8c43[0];ls351cf[1558]<=jc4dbca;ls351cf[1550]<=fae1007;ls351cf[1464]<=ec98898;ls351cf[1072]<=ay4621c[0];ls351cf[1069]<=cm6de53;ls351cf[1052]<=ea6d36f[0];ls351cf[1023]<=gbe_mode;ls351cf[901]<=ukee6;ls351cf[880]<=suc44c0;ls351cf[775]<=fp1c200;ls351cf[732]<=go53113;ls351cf[450]<=kf803b[0];ls351cf[387]<=kq43840;ls351cf[366]<=dmca622;ls351cf[225]<=jp40b00;ls351cf[193]<=ec88708;ls351cf[183]<=ne794c4;ls351cf[112]<=kqfa2f5;ls351cf[96]<=ec310e1[0];ls351cf[91]<=mr6f298;ls351cf[56]<=fa69b79;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[3]};gqd8a<=jea8e7a[4];db6c51<=jea8e7a[5];zk42a46<=jea8e7a[6];sw15232<=jea8e7a[7];epa1d8f<={zz38960>>1,jea8e7a[8]};an3628e<={ic59746>>1,jea8e7a[9]};epb1475<={cmcba31>>1,jea8e7a[10]};gd8a3ac<={vi5d188>>1,jea8e7a[11]};gb51d65<={ene8c43>>1,jea8e7a[12]};hd8eb2c<={ay4621c>>1,jea8e7a[13]};kd75966<={ec310e1>>1,jea8e7a[14]};ecacb35<=jea8e7a[15];cz659a8<=jea8e7a[16];ir2cd44<=jea8e7a[17];ho66a24<=jea8e7a[18];tuc57be<={ea6d36f>>1,jea8e7a[19]};wy2bdf2<=jea8e7a[20];ls1b459<=jea8e7a[21];th40935<=jea8e7a[22];zm35123<={kf803b>>1,jea8e7a[23]};cz448d2<=jea8e7a[24];ria891a<=jea8e7a[25];fa523cb<=jea8e7a[26];zz91e5a<=jea8e7a[27];uv5ef91<=jea8e7a[28];wjf7c8d<=jea8e7a[29];uxbe46c<=jea8e7a[30];mrf2365<=jea8e7a[31];xl91b2d<=jea8e7a[32];ks8d96e<=jea8e7a[33];lq6cb71<=jea8e7a[34];gb65b8a<=jea8e7a[35];end -always@* begin ls351cf[2047]<=force_isolate;ls351cf[2046]<=db3242c;ls351cf[2044]<=zz38f51[0];ls351cf[2041]<=blc7a8f;ls351cf[2035]<=lf3d47e;ls351cf[2022]<=do20bc9;ls351cf[1996]<=ou5e4a;ls351cf[1945]<=zz38960[0];ls351cf[1922]<=jp401dc;ls351cf[1842]<=ic59746[0];ls351cf[1797]<=kq49d41;ls351cf[1776]<=jp40b00;ls351cf[1637]<=cmcba31[0];ls351cf[1622]<=ec310e1[0];ls351cf[1546]<=mr4ea09;ls351cf[1504]<=kf803b[0];ls351cf[1468]<=fa69b79;ls351cf[1391]<=fae1007;ls351cf[1312]<=ec98898;ls351cf[1226]<=vi5d188[0];ls351cf[1197]<=ec88708;ls351cf[1044]<=jc4dbca;ls351cf[1023]<=gbe_mode;ls351cf[961]<=ukee6;ls351cf[888]<=kqfa2f5;ls351cf[811]<=ay4621c[0];ls351cf[734]<=ea6d36f[0];ls351cf[695]<=fp1c200;ls351cf[656]<=go53113;ls351cf[576]<=suc44c0;ls351cf[405]<=ene8c43[0];ls351cf[347]<=kq43840;ls351cf[328]<=dmca622;ls351cf[164]<=ne794c4;ls351cf[82]<=mr6f298;ls351cf[41]<=cm6de53;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[6]};sw9203a<=jea8e7a[7];yz901d0<=jea8e7a[8];yz80e85<=jea8e7a[9];qv742d<=jea8e7a[10];do3a16d<=jea8e7a[11];fad0b6b<={kq68466>>1,jea8e7a[12]};yz85b5a<={by42331>>1,jea8e7a[13]};rv2dad5<={ng1198b>>1,jea8e7a[14]};ay6d6ae<={je8cc5a>>1,jea8e7a[15]};bl6b571<={dm662d3>>1,jea8e7a[16]};fn5ab8e<=jea8e7a[17];fad5c77<=jea8e7a[18];yzae3ba<=jea8e7a[19];hb71dd4<=jea8e7a[20];jr8eea7<=jea8e7a[21];yk7753e<=jea8e7a[22];phba9f1<={xya2ed8>>1,jea8e7a[23]};sud4f8e<=jea8e7a[24];xya7c70<={uxbb61c>>1,jea8e7a[25]};wy3e383<=jea8e7a[26];byf1c19<={rtd8728>>1,jea8e7a[27]};nt8e0cb<={yxc3947>>1,jea8e7a[28]};kd7065f<={nt1ca3c>>1,jea8e7a[29]};ba832fc<={ph28f31>>1,jea8e7a[30]};ph197e3<={lq4798e>>1,jea8e7a[31]};gocbf1f<={mt3cc72>>1,jea8e7a[32]};dz5f8f8<={ble6395>>1,jea8e7a[33]};rtfc7c7<={ym31cae>>1,jea8e7a[34]};lde3e3e<={ph8e571>>1,jea8e7a[35]};ec1f1f7<=jea8e7a[36];uvf8fb8<=jea8e7a[37];nrc7dc5<=jea8e7a[38];aa3ee2e<=jea8e7a[39];enf7170<=jea8e7a[40];jeb8b85<=jea8e7a[41];byc5c2b<=jea8e7a[42];mg2e15b<=jea8e7a[43];of70ad8<=jea8e7a[44];mt856c5<=jea8e7a[45];sw2b62c<=jea8e7a[46];kd5b160<=jea8e7a[47];rtd8b04<=jea8e7a[48];tuc5826<={off70d0>>1,jea8e7a[49]};cb2c133<=jea8e7a[50];qt6099d<=jea8e7a[51];pu4cec<=jea8e7a[52];wl26763<=jea8e7a[53];mt33b1c<=jea8e7a[54];qi9d8e4<={ls2aa14>>1,jea8e7a[55]};nrec720<=jea8e7a[56];zk63907<=jea8e7a[57];ph1c83b<=jea8e7a[58];dme41de<=jea8e7a[59];tw20ef3<={gqa3ed3>>1,jea8e7a[60]};oh779a<=jea8e7a[61];mg3bcd5<=jea8e7a[62];uide6a8<=jea8e7a[63];thf3540<=jea8e7a[64];an9aa07<=jea8e7a[65];rgd503d<={thc86a3>>1,jea8e7a[66]};twa81eb<=jea8e7a[67];xj40f5b<=jea8e7a[68];ir7adf<=jea8e7a[69];ph3d6fc<={gqa3c49>>1,jea8e7a[70]};end -always@* begin ls351cf[2047]<=sgmii_mode;ls351cf[2046]<=force_unidir;ls351cf[2044]<=mr_main_reset;ls351cf[2040]<=mr_restart_an;ls351cf[2033]<=mr_an_enable;ls351cf[2019]<=mr_adv_ability[1];ls351cf[1999]<=ph8e571[0];ls351cf[1991]<=nr4ae92;ls351cf[1981]<=ofc342a;ls351cf[1958]<=ld550a3;ls351cf[1950]<=kf95c78;ls351cf[1947]<=bn27a48;ls351cf[1934]<=bld2597;ls351cf[1914]<=mg1a155;ls351cf[1892]<=ls8cd17;ls351cf[1868]<=xya851f;ls351cf[1852]<=pf71e24;ls351cf[1851]<=je8cc5a[0];ls351cf[1847]<=fp3d247;ls351cf[1820]<=qi92cbe;ls351cf[1783]<=ym3ee1a;ls351cf[1780]<=fad0aa8;ls351cf[1737]<=tu668bb;ls351cf[1689]<=by428fb;ls351cf[1657]<=ux8f127;ls351cf[1654]<=dm662d3[0];ls351cf[1647]<=the923e;ls351cf[1610]<=yz176c3;ls351cf[1608]<=uvd321a;ls351cf[1593]<=ls965f1;ls351cf[1523]<=ble6395[0];ls351cf[1519]<=off70d0[1];ls351cf[1513]<=yz85542;ls351cf[1426]<=qi345db;ls351cf[1404]<=lq4798e[0];ls351cf[1330]<=je147da;ls351cf[1267]<=me7893d;ls351cf[1260]<=ou3169a;ls351cf[1246]<=ui491f7;ls351cf[1225]<=qi1f699;ls351cf[1199]<=yxc3947[0];ls351cf[1173]<=uxbb61c[0];ls351cf[1169]<=ng990d4;ls351cf[1163]<=ec1a8f1;ls351cf[1139]<=twb2f8a;ls351cf[1023]<=gbe_mode;ls351cf[999]<=ym31cae[0];ls351cf[990]<=lsb8685;ls351cf[979]<=ls2aa14[0];ls351cf[973]<=ou24f49;ls351cf[946]<=bl719a2;ls351cf[925]<=ng1198b[0];ls351cf[891]<=dm47dc3;ls351cf[805]<=xya2ed8[0];ls351cf[804]<=rgda643;ls351cf[761]<=mt3cc72[0];ls351cf[702]<=ph28f31[0];ls351cf[612]<=gqa3ed3[1];ls351cf[599]<=rtd8728[0];ls351cf[581]<=ay4351e;ls351cf[556]<=gqa3c49[1];ls351cf[486]<=ykc49e9;ls351cf[473]<=hoee334;ls351cf[462]<=by42331[0];ls351cf[445]<=jc48fb8;ls351cf[402]<=lqfb4c8;ls351cf[351]<=nt1ca3c[0];ls351cf[299]<=kqdb0e5;ls351cf[290]<=thc86a3[0];ls351cf[278]<=wwd4789;ls351cf[231]<=kq68466[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[4]};co9db4a<=jea8e7a[5];eneda50<=jea8e7a[6];yz901d0<=jea8e7a[7];zk69421<=jea8e7a[8];th4a10b<={vif148d>>1,jea8e7a[9]};hb5085f<=jea8e7a[10];ph842fe<=jea8e7a[11];qi217f6<=jea8e7a[12];twbfb1<={xj718b7>>1,jea8e7a[13]};dz5fd8a<={fc8c5bf>>1,jea8e7a[14]};psfec57<={su62dfa>>1,jea8e7a[15]};vvf62ba<={lf16fd1>>1,jea8e7a[16]};qvb15d7<={xyb7e8f>>1,jea8e7a[17]};yz8aebc<=jea8e7a[18];ps575e4<=jea8e7a[19];bnbaf22<=jea8e7a[20];nrd7916<=jea8e7a[21];mgbc8b7<=jea8e7a[22];zke45b9<=jea8e7a[23];ph22dcb<=jea8e7a[24];nt16e5f<=jea8e7a[25];ngb72ff<=jea8e7a[26];cob97fb<=jea8e7a[27];sucbfd8<=jea8e7a[28];vv5fec0<=jea8e7a[29];cmff607<=jea8e7a[30];xwfb039<=jea8e7a[31];ldd81cb<=jea8e7a[32];byc0e5f<=jea8e7a[33];oh72fb<=jea8e7a[34];oh397dd<=jea8e7a[35];kqcbeec<=jea8e7a[36];jp5f760<=jea8e7a[37];hofbb06<=jea8e7a[38];jpdd832<=jea8e7a[39];jpec196<=jea8e7a[40];uv60cb7<=jea8e7a[41];xl65bc<={me77a0e>>1,jea8e7a[42]};jr32de7<={ribd070>>1,jea8e7a[43]};tw96f3e<=jea8e7a[44];jeb79f3<=jea8e7a[45];swbcf9a<=jea8e7a[46];wje7cd1<=jea8e7a[47];ou3e68d<=jea8e7a[48];rtf3469<=jea8e7a[49];kf9a34f<=jea8e7a[50];osd1a7c<=jea8e7a[51];qi8d3e0<=jea8e7a[52];dm69f00<=jea8e7a[53];vv4f802<=jea8e7a[54];rg7c016<=jea8e7a[55];ice00b2<=jea8e7a[56];gq591<=jea8e7a[57];yz2c88<={mrc9186>>1,jea8e7a[58]};nt16444<={xw48c34>>1,jea8e7a[59]};twa81eb<=jea8e7a[60];xj40f5b<=jea8e7a[61];ec8899f<=jea8e7a[62];qt44cf9<=jea8e7a[63];ep267cd<=jea8e7a[64];yz33e6c<=jea8e7a[65];uv5ef91<=jea8e7a[66];wjf7c8d<=jea8e7a[67];pfcd927<={psd01ce>>1,jea8e7a[68]};end -always@* begin ls351cf[2047]<=sgmii_mode;ls351cf[2046]<=gbe_mode;ls351cf[2044]<=jp6bc27;ls351cf[2040]<=rx_data[0];ls351cf[2032]<=rx_kcntl;ls351cf[2016]<=db84fe1;ls351cf[1985]<=bld2597;ls351cf[1927]<=hq868cb;ls351cf[1922]<=rx_even;ls351cf[1867]<=eafa3d7;ls351cf[1807]<=ec3465a;ls351cf[1804]<=wj7056b;ls351cf[1797]<=vif148d[0];ls351cf[1761]<=kde8382;ls351cf[1686]<=med1eb9;ls351cf[1623]<=qi7c9;ls351cf[1567]<=eca32d0;ls351cf[1561]<=sw82b5c;ls351cf[1558]<=by661fc;ls351cf[1547]<=cb8082d;ls351cf[1542]<=zxc2d31;ls351cf[1505]<=ay4351e;ls351cf[1490]<=xyb7e8f[0];ls351cf[1475]<=cz41c15;ls351cf[1413]<=dz45987;ls351cf[1409]<=tj130b4;ls351cf[1400]<=mrc9186[0];ls351cf[1324]<=cb8f5c8;ls351cf[1200]<=fnd722c;ls351cf[1199]<=bn3e48;ls351cf[1086]<=zz19680;ls351cf[1074]<=ou15ae0;ls351cf[1068]<=zm30fe2;ls351cf[1047]<=vk416d;ls351cf[1037]<=vx1698e;ls351cf[1023]<=mr_main_reset;ls351cf[963]<=ec1a8f1;ls351cf[933]<=dbbf47a;ls351cf[902]<=vke0ad;ls351cf[880]<=ribd070[0];ls351cf[811]<=goe00f9;ls351cf[779]<=ep2cc3f;ls351cf[771]<=ec985a6;ls351cf[752]<=xw48c34[0];ls351cf[745]<=lf16fd1[0];ls351cf[706]<=zxc8b30;ls351cf[704]<=ale2616;ls351cf[700]<=blf9230;ls351cf[600]<=al7ae45;ls351cf[503]<=psd01ce[1];ls351cf[440]<=me77a0e[0];ls351cf[405]<=cm5c01f;ls351cf[372]<=su62dfa[0];ls351cf[353]<=wyb9166;ls351cf[352]<=thfc4c2;ls351cf[350]<=ie1f246;ls351cf[251]<=cm6de53;ls351cf[220]<=bn8ef41;ls351cf[202]<=hb6b803;ls351cf[186]<=fc8c5bf[0];ls351cf[176]<=fc3f898;ls351cf[125]<=jc4dbca;ls351cf[110]<=gq31de8;ls351cf[101]<=riad700;ls351cf[93]<=xj718b7[0];ls351cf[88]<=uk87f13;ls351cf[55]<=coa63bd;ls351cf[46]<=ic6d48e;ls351cf[27]<=anb4c77;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[2]};co9db4a<=jea8e7a[3];eneda50<=jea8e7a[4];qge0b9f<={hoee83b>>1,jea8e7a[5]};ou5cf8<={fn741db>>1,jea8e7a[6]};mg2e7c1<={pha0ede>>1,jea8e7a[7]};ne73e08<=jea8e7a[8];an9f042<=jea8e7a[9];twa81eb<=jea8e7a[10];xj40f5b<=jea8e7a[11];ep8520<=jea8e7a[12];lq42904<=jea8e7a[13];ls14822<=jea8e7a[14];uxa4112<=jea8e7a[15];zm20895<=jea8e7a[16];je44aa<=jea8e7a[17];xl22552<=jea8e7a[18];ux12a96<={wlb1063>>1,jea8e7a[19]};end -always@* begin ls351cf[2047]<=signal_detect;ls351cf[2046]<=rx_data[0];ls351cf[2044]<=rx_kcntl;ls351cf[2040]<=db84fe1;ls351cf[2033]<=hoee83b[0];ls351cf[2018]<=fn741db[0];ls351cf[1988]<=pha0ede[0];ls351cf[1929]<=ir76f6;ls351cf[1811]<=qi3b7b5;ls351cf[1789]<=zk7620c;ls351cf[1574]<=ay4351e;ls351cf[1530]<=wlb1063[1];ls351cf[1247]<=ui493b1;ls351cf[1101]<=ec1a8f1;ls351cf[1023]<=mr_main_reset;ls351cf[894]<=wj4ec41;ls351cf[623]<=gqa9276;ls351cf[447]<=ic49d88;ls351cf[311]<=bnb524e;ls351cf[155]<=nrf6a49;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[4]};wy2155a<={wwef1be>>1,jea8e7a[5]};ouaad1<=jea8e7a[6];pf55688<=jea8e7a[7];epab447<={uk31c93>>1,jea8e7a[8]};dz5a23c<={lq79093>>1,jea8e7a[9]};kqd11e6<={pfc849a>>1,jea8e7a[10]};ou88f31<=jea8e7a[11];rg47989<=jea8e7a[12];ir3cc4a<={xy9359c>>1,jea8e7a[13]};vve6255<=jea8e7a[14];co312ae<=jea8e7a[15];pu89570<={ksb38ac>>1,jea8e7a[16]};xj4ab82<=jea8e7a[17];jp55c16<=jea8e7a[18];epae0b6<=jea8e7a[19];cz705b4<=jea8e7a[20];ou82da4<=jea8e7a[21];lf16d20<=jea8e7a[22];wyb6907<=jea8e7a[23];uxb4838<=jea8e7a[24];ira41c5<=jea8e7a[25];th40935<=jea8e7a[26];bn3d024<={ie3102c>>1,jea8e7a[27]};bn38b55<=jea8e7a[28];qt60f40<=jea8e7a[29];xl2d57b<=jea8e7a[30];cz6abdf<=jea8e7a[31];rt55efd<=jea8e7a[32];rvaf7ee<=jea8e7a[33];mre8126<=jea8e7a[34];bydfbb6<=jea8e7a[35];alfddb3<=jea8e7a[36];hoeed9d<=jea8e7a[37];dm76ceb<=jea8e7a[38];wyb675a<=jea8e7a[39];wyb3ad1<=jea8e7a[40];sw9d688<=jea8e7a[41];faeb441<={hbe6897>>1,jea8e7a[42]};epb1475<={cmcba31>>1,jea8e7a[43]};gd8a3ac<={vi5d188>>1,jea8e7a[44]};gq882b1<={mt12fc2>>1,jea8e7a[45]};cz41588<={ec97e15>>1,jea8e7a[46]};qiac44<=jea8e7a[47];cm56220<=jea8e7a[48];anb1100<=jea8e7a[49];ym88804<=jea8e7a[50];ecacb35<=jea8e7a[51];fc2010c<=jea8e7a[52];ie863<=jea8e7a[53];ri4319<=jea8e7a[54];gq218ca<=jea8e7a[55];phc650<=jea8e7a[56];vi63286<=jea8e7a[57];fp19432<={yz33c09>>1,jea8e7a[58]};faca197<={lf9e04c>>1,jea8e7a[59]};uv5ef91<=jea8e7a[60];wjf7c8d<=jea8e7a[61];ph32ef3<={ph9986>>1,jea8e7a[62]};ou9779e<={yk4cc37>>1,jea8e7a[63]};sjbbcf0<=jea8e7a[64];qgde784<=jea8e7a[65];nrf3c20<=jea8e7a[66];bn9e106<=jea8e7a[67];uif0836<=jea8e7a[68];jr841b1<=jea8e7a[69];vk20d8e<=jea8e7a[70];fp6c72<=jea8e7a[71];qv36396<=jea8e7a[72];cbb1cb5<=jea8e7a[73];vx8e5ad<=jea8e7a[74];ui72d6f<=jea8e7a[75];do96b78<={qg72b18>>1,jea8e7a[76]};ntb5bc3<={yz958c0>>1,jea8e7a[77]};end -always@* begin ls351cf[2047]<=an_link_ok;ls351cf[2046]<=ic626ef;ls351cf[2044]<=gbe_mode;ls351cf[2040]<=operational_rate[0];ls351cf[2032]<=wwef1be[0];ls351cf[2018]<=hbe6897[0];ls351cf[2017]<=os78df0;ls351cf[1989]<=cmcba31[0];ls351cf[1987]<=qtc6f81;ls351cf[1931]<=vi5d188[0];ls351cf[1927]<=uk31c93[0];ls351cf[1865]<=ksb38ac[0];ls351cf[1859]<=an80a07;ls351cf[1844]<=rg7cc46;ls351cf[1815]<=mt12fc2[0];ls351cf[1806]<=lq79093[0];ls351cf[1682]<=ba9c560;ls351cf[1674]<=yz33c09[0];ls351cf[1671]<=ks88160;ls351cf[1640]<=pfe6233;ls351cf[1582]<=ec97e15[0];ls351cf[1565]<=pfc849a[0];ls351cf[1488]<=qgea028;ls351cf[1485]<=ec88708;ls351cf[1326]<=jp40b00;ls351cf[1317]<=ale2b03;ls351cf[1300]<=lf9e04c[0];ls351cf[1297]<=ng30dca;ls351cf[1295]<=jr281e8;ls351cf[1233]<=gq3119e;ls351cf[1210]<=ay6df50;ls351cf[1189]<=mt1d06e;ls351cf[1172]<=mgac0e8;ls351cf[1124]<=xwc5cac;ls351cf[1116]<=vxbf0a9;ls351cf[1105]<=cm6de53;ls351cf[1094]<=ep9ae18;ls351cf[1092]<=bn3729a;ls351cf[1087]<=sj7a3f;ls351cf[1082]<=vi424d6;ls351cf[1023]<=mr_main_reset;ls351cf[1009]<=do3f9a2;ls351cf[932]<=kdd6715;ls351cf[929]<=vv50140;ls351cf[922]<=vv4f988;ls351cf[837]<=me46781;ls351cf[744]<=su7d405;ls351cf[742]<=uk153e6;ls351cf[663]<=cz41bad;ls351cf[648]<=tu661b9;ls351cf[605]<=ie3102c[0];ls351cf[594]<=lf3a0d;ls351cf[586]<=uk1581d;ls351cf[562]<=yz18b95;ls351cf[552]<=jc4dbca;ls351cf[547]<=ww535c3;ls351cf[546]<=do86e53;ls351cf[543]<=vv40f47;ls351cf[504]<=xw47f34;ls351cf[466]<=mt9ace2;ls351cf[418]<=uk88cf0;ls351cf[400]<=yz958c0[1];ls351cf[372]<=en44c40;ls351cf[371]<=jpc2a7c;ls351cf[331]<=kde8375;ls351cf[324]<=yk4cc37[0];ls351cf[297]<=sh60741;ls351cf[281]<=bab862e;ls351cf[273]<=faca6b8;ls351cf[252]<=kde8fe6;ls351cf[233]<=xy9359c[0];ls351cf[200]<=qg72b18[1];ls351cf[185]<=uvf854f;ls351cf[162]<=ph9986[0];ls351cf[140]<=zxd70c5;ls351cf[136]<=ksb94d7;ls351cf[126]<=rv3d1fc;ls351cf[116]<=sj126b3;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[1]};ouaad1<=jea8e7a[2];pf55688<=jea8e7a[3];epab447<={uk31c93>>1,jea8e7a[4]};dz5a23c<={lq79093>>1,jea8e7a[5]};kqd11e6<={pfc849a>>1,jea8e7a[6]};ou88f31<=jea8e7a[7];rg47989<=jea8e7a[8];ir3cc4a<={xy9359c>>1,jea8e7a[9]};vve6255<=jea8e7a[10];co312ae<=jea8e7a[11];pu89570<={ksb38ac>>1,jea8e7a[12]};xj4ab82<=jea8e7a[13];jp55c16<=jea8e7a[14];epae0b6<=jea8e7a[15];cz705b4<=jea8e7a[16];ou82da4<=jea8e7a[17];lf16d20<=jea8e7a[18];wyb6907<=jea8e7a[19];uxb4838<=jea8e7a[20];ira41c5<=jea8e7a[21];th40935<=jea8e7a[22];bn3d024<={ie3102c>>1,jea8e7a[23]};bn38b55<=jea8e7a[24];qt60f40<=jea8e7a[25];xl2d57b<=jea8e7a[26];cz6abdf<=jea8e7a[27];rt55efd<=jea8e7a[28];rvaf7ee<=jea8e7a[29];mre8126<=jea8e7a[30];bydfbb6<=jea8e7a[31];alfddb3<=jea8e7a[32];hoeed9d<=jea8e7a[33];dm76ceb<=jea8e7a[34];wyb675a<=jea8e7a[35];wyb3ad1<=jea8e7a[36];sw9d688<=jea8e7a[37];faeb441<={hbe6897>>1,jea8e7a[38]};uif0836<=jea8e7a[39];jr841b1<=jea8e7a[40];vk20d8e<=jea8e7a[41];fp6c72<=jea8e7a[42];qv36396<=jea8e7a[43];cbb1cb5<=jea8e7a[44];vx8e5ad<=jea8e7a[45];ui72d6f<=jea8e7a[46];do96b78<={qg72b18>>1,jea8e7a[47]};ntb5bc3<={yz958c0>>1,jea8e7a[48]};end -always@* begin ls351cf[2047]<=wwef1be[0];ls351cf[2046]<=os78df0;ls351cf[2044]<=qtc6f81;ls351cf[2040]<=uk31c93[0];ls351cf[2033]<=lq79093[0];ls351cf[2019]<=pfc849a[0];ls351cf[1991]<=vi424d6;ls351cf[1934]<=sj126b3;ls351cf[1929]<=qg72b18[1];ls351cf[1898]<=uk1581d;ls351cf[1821]<=xy9359c[0];ls351cf[1810]<=yz958c0[1];ls351cf[1749]<=mgac0e8;ls351cf[1707]<=mt1d06e;ls351cf[1666]<=vv50140;ls351cf[1630]<=ww535c3;ls351cf[1595]<=mt9ace2;ls351cf[1506]<=yz18b95;ls351cf[1450]<=sh60741;ls351cf[1440]<=su7d405;ls351cf[1384]<=ay6df50;ls351cf[1370]<=jp40b00;ls351cf[1366]<=kde8375;ls351cf[1284]<=an80a07;ls351cf[1212]<=ep9ae18;ls351cf[1142]<=kdd6715;ls351cf[1125]<=do3f9a2;ls351cf[1041]<=jr281e8;ls351cf[1023]<=mr_main_reset;ls351cf[964]<=xwc5cac;ls351cf[949]<=ale2b03;ls351cf[853]<=lf3a0d;ls351cf[833]<=qgea028;ls351cf[815]<=faca6b8;ls351cf[753]<=bab862e;ls351cf[720]<=en44c40;ls351cf[692]<=ie3102c[0];ls351cf[685]<=cz41bad;ls351cf[562]<=xw47f34;ls351cf[520]<=ks88160;ls351cf[474]<=ba9c560;ls351cf[407]<=ksb94d7;ls351cf[376]<=zxd70c5;ls351cf[281]<=kde8fe6;ls351cf[237]<=ksb38ac[0];ls351cf[203]<=hbe6897[0];ls351cf[140]<=rv3d1fc;ls351cf[70]<=sj7a3f;ls351cf[35]<=vv40f47;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[1]};ouaad1<=jea8e7a[2];pf55688<=jea8e7a[3];kqd11e6<={pfc849a>>1,jea8e7a[4]};ou88f31<=jea8e7a[5];rg47989<=jea8e7a[6];ira41c5<=jea8e7a[7];th40935<=jea8e7a[8];bn3d024<={ie3102c>>1,jea8e7a[9]};bn38b55<=jea8e7a[10];qt60f40<=jea8e7a[11];xl2d57b<=jea8e7a[12];cz6abdf<=jea8e7a[13];rt55efd<=jea8e7a[14];mre8126<=jea8e7a[15];alfddb3<=jea8e7a[16];hoeed9d<=jea8e7a[17];dm76ceb<=jea8e7a[18];wyb675a<=jea8e7a[19];wyb3ad1<=jea8e7a[20];sw9d688<=jea8e7a[21];uif0836<=jea8e7a[22];jr841b1<=jea8e7a[23];vk20d8e<=jea8e7a[24];fp6c72<=jea8e7a[25];end -always@* begin ls351cf[2047]<=wwef1be[0];ls351cf[2046]<=os78df0;ls351cf[2044]<=qtc6f81;ls351cf[2040]<=pfc849a[0];ls351cf[2033]<=vi424d6;ls351cf[2019]<=sj126b3;ls351cf[1990]<=cz41bad;ls351cf[1939]<=rv3d1fc;ls351cf[1933]<=jp40b00;ls351cf[1831]<=kde8fe6;ls351cf[1819]<=ie3102c[0];ls351cf[1778]<=ks88160;ls351cf[1615]<=xw47f34;ls351cf[1591]<=ay6df50;ls351cf[1508]<=vv40f47;ls351cf[1271]<=ww535c3;ls351cf[1182]<=do3f9a2;ls351cf[1135]<=en44c40;ls351cf[1023]<=mr_main_reset;ls351cf[969]<=sj7a3f;ls351cf[889]<=vv50140;ls351cf[635]<=faca6b8;ls351cf[495]<=ep9ae18;ls351cf[444]<=qgea028;ls351cf[317]<=ksb94d7;ls351cf[222]<=su7d405;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[4]};xjdd188<={ri20af6>>1,jea8e7a[5]};uve8c47<=jea8e7a[6];yk4623c<=jea8e7a[7];ou311e1<={vkb206f>>1,jea8e7a[8]};gq88f08<=jea8e7a[9];fa47841<=jea8e7a[10];nt8e0cb<={yxc3947>>1,jea8e7a[11]};kd7065f<={nt1ca3c>>1,jea8e7a[12]};byf1c19<={rtd8728>>1,jea8e7a[13]};mr4151c<=jea8e7a[14];swa8e4<=jea8e7a[15];uv54720<=jea8e7a[16];qia3905<={zxecd89>>1,jea8e7a[17]};vx1c829<={ne66c4e>>1,jea8e7a[18]};zke414e<=jea8e7a[19];ng20a73<=jea8e7a[20];qi539a<=jea8e7a[21];twa81eb<=jea8e7a[22];xj40f5b<=jea8e7a[23];dm73425<=jea8e7a[24];cb9a12b<=jea8e7a[25];ph3d6fc<={gqa3c49>>1,jea8e7a[26]};end -always@* begin ls351cf[2047]<=force_unidir;ls351cf[2046]<=tx_en;ls351cf[2044]<=tx_er;ls351cf[2040]<=ph8415e[0];ls351cf[2032]<=ri20af6[0];ls351cf[2017]<=wy57b2;ls351cf[1987]<=en5ec81;ls351cf[1927]<=vkb206f[0];ls351cf[1865]<=cm7d9b1;ls351cf[1806]<=qv9037b;ls351cf[1682]<=zxecd89[0];ls351cf[1565]<=nt81bdd;ls351cf[1326]<=gqa3c49[1];ls351cf[1317]<=ne66c4e[0];ls351cf[1189]<=ec1a8f1;ls351cf[1172]<=yzb139d;ls351cf[1082]<=yxc3947[0];ls351cf[1023]<=mr_main_reset;ls351cf[932]<=uiefb36;ls351cf[663]<=xjec750;ls351cf[594]<=ay4351e;ls351cf[586]<=wl36273;ls351cf[466]<=blddf66;ls351cf[331]<=ou9d8ea;ls351cf[297]<=je89cec;ls351cf[233]<=rtd8728[0];ls351cf[116]<=nt1ca3c[0];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[1]};jc42507<=jea8e7a[2];an1283b<=jea8e7a[3];ph941dd<=jea8e7a[4];fpa0eef<=jea8e7a[5];gd777e<=jea8e7a[6];aa3bbf5<={uvcc12a>>1,jea8e7a[7]};fnddfa8<=jea8e7a[8];ayefd46<=jea8e7a[9];bl7ea31<={ba25523>>1,jea8e7a[10]};kqf518e<={do2a91b>>1,jea8e7a[11]};baa8c70<={yx548db>>1,jea8e7a[12]};cm46382<={uxa46dc>>1,jea8e7a[13]};uk31c11<=jea8e7a[14];jr8e089<=jea8e7a[15];en7044f<=jea8e7a[16];ec8227c<=jea8e7a[17];ls113e1<=jea8e7a[18];xy89f0b<=jea8e7a[19];nr4f85b<=jea8e7a[20];fa7c2de<=jea8e7a[21];rge16f2<=jea8e7a[22];bab793<=jea8e7a[23];end -always@* begin ls351cf[2047]<=fc30929[0];ls351cf[2046]<=tj8494b;ls351cf[2044]<=aa24a5f;ls351cf[2040]<=ri252f8;ls351cf[2032]<=cb297c3;ls351cf[2016]<=ym211e0;ls351cf[1985]<=uvcc12a[0];ls351cf[1922]<=kd60954;ls351cf[1796]<=tw4aa4;ls351cf[1544]<=ba25523[6];ls351cf[1302]<=xy11828;ls351cf[1115]<=qt60a12;ls351cf[1105]<=gbdcb11;ls351cf[1041]<=do2a91b[0];ls351cf[1023]<=qgc423c;ls351cf[651]<=ea62305;ls351cf[557]<=ls8c142;ls351cf[552]<=sudb962;ls351cf[325]<=ep2c460;ls351cf[276]<=ri1b72c;ls351cf[162]<=ice588c;ls351cf[138]<=an236e5;ls351cf[69]<=uxa46dc[0];ls351cf[34]<=yx548db[6];end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96>1,jea8e7a[7]};ho73b69<={rx_data>>1,jea8e7a[8]};co9db4a<=jea8e7a[9];zk69421<=jea8e7a[10];kfa1f51<=jea8e7a[11];swfa8c<=jea8e7a[12];su7d460<=jea8e7a[13];qgea300<={tx_d>>1,jea8e7a[14]};rt50ee8<=jea8e7a[15];ou87746<=jea8e7a[16];xj4a480<=jea8e7a[17];qg49292<=jea8e7a[18];cm49490<=jea8e7a[19];th4a10b<={vif148d>>1,jea8e7a[20]};tj22a0a<={uk97c52>>1,jea8e7a[21]};qi15057<={sjbe291>>1,jea8e7a[22]};eneda50<=jea8e7a[23];kd415cb<={zkda3ae>>1,jea8e7a[24]};coae5c<=jea8e7a[25];vi572e0<=jea8e7a[26];ukb9702<=jea8e7a[27];gocb810<=jea8e7a[28];ay5c080<=jea8e7a[29];qge0401<=jea8e7a[30];ux2009<=jea8e7a[31];uv5ef91<=jea8e7a[32];wjf7c8d<=jea8e7a[33];uxbe46c<=jea8e7a[34];mrf2365<=jea8e7a[35];xl91b2d<=jea8e7a[36];ks8d96e<=jea8e7a[37];cm4c5d2<=jea8e7a[38];ui62e90<=jea8e7a[39];an17481<=jea8e7a[40];lfba40c<=jea8e7a[41];thd2067<=jea8e7a[42];gd9033e<=jea8e7a[43];lf819f5<=jea8e7a[44];rvcfaf<={fafbf50>>1,jea8e7a[45]};os67d7f<=jea8e7a[46];co3ebf9<=jea8e7a[47];suf5fc8<={meea09c>>1,jea8e7a[48]};tjafe41<=jea8e7a[49];wj7f20f<=jea8e7a[50];dzf907d<=jea8e7a[51];dzc83ee<=jea8e7a[52];en41f76<=jea8e7a[53];ksfbb5<=jea8e7a[54];go7dda8<={bl7b16b>>1,jea8e7a[55]};dmeed41<=jea8e7a[56];xw76a0b<=jea8e7a[57];dbb505a<=jea8e7a[58];xya82d6<=jea8e7a[59];cz416b3<=jea8e7a[60];end -always@* begin ls351cf[2047]<=sgmii_mode;ls351cf[2046]<=signal_detect;ls351cf[2044]<=debug_link_timer_short;ls351cf[2040]<=force_isolate;ls351cf[2032]<=force_loopback;ls351cf[2017]<=force_unidir;ls351cf[1987]<=operational_rate[0];ls351cf[1926]<=rx_data[0];ls351cf[1805]<=ne794c4;ls351cf[1804]<=rx_kcntl;ls351cf[1803]<=db84fe1;ls351cf[1761]<=jc4dbca;ls351cf[1668]<=oh907df;ls351cf[1562]<=dmca622;ls351cf[1560]<=rx_even;ls351cf[1558]<=zkda3ae[0];ls351cf[1550]<=tx_er;ls351cf[1475]<=cm6de53;ls351cf[1464]<=ba86b0c;ls351cf[1288]<=vk83efd;ls351cf[1242]<=db2d7f3;ls351cf[1076]<=go53113;ls351cf[1072]<=rx_disp_err;ls351cf[1069]<=ead1d72;ls351cf[1056]<=fafbf50[0];ls351cf[1052]<=mr_an_enable;ls351cf[1028]<=co82707;ls351cf[1023]<=gbe_mode;ls351cf[902]<=mr6f298;ls351cf[901]<=sjbe291[0];ls351cf[880]<=je35862;ls351cf[874]<=th5fcff;ls351cf[834]<=lf320fb;ls351cf[775]<=tx_en;ls351cf[732]<=mt90d61;ls351cf[621]<=tuc5afe;ls351cf[528]<=mg1f7ea;ls351cf[514]<=pf504e0;ls351cf[450]<=uk97c52[0];ls351cf[437]<=zx6bf9f;ls351cf[417]<=hq8641f;ls351cf[387]<=tx_d[0];ls351cf[366]<=os721ac;ls351cf[310]<=rtd8b5f;ls351cf[257]<=meea09c[0];ls351cf[225]<=vif148d[0];ls351cf[208]<=hdb0c83;ls351cf[193]<=rx_err_decode_mode;ls351cf[183]<=wlae435;ls351cf[155]<=bl7b16b[0];ls351cf[128]<=yxfd413;ls351cf[112]<=mr_restart_an;ls351cf[104]<=xw76190;ls351cf[96]<=rx_cv_err;ls351cf[91]<=rv8eb90;ls351cf[77]<=pscf62d;ls351cf[64]<=rgdfa82;ls351cf[56]<=mr_main_reset;ls351cf[38]<=oh39ec5;ls351cf[19]<=pu9c1cf;ls351cf[9]<=xl13839;end assign jc5dccb = ls351cf,jea8e7a = zk732d2; initial begin vx9b3b2 = $fopen(".fred"); $fdisplay( vx9b3b2, "%3h\n%3h", (bycf49d >> 4) & wy9d773, (bycf49d >> (xjd275d+4)) & wy9d773 ); $fclose(vx9b3b2); $readmemh(".fred", cmcb49b); end always @ (jc5dccb) begin xjd26ce = cmcb49b[1]; for (ald9d96=0; ald9d96 0} { - for {set i 0} {$i < $argc} {incr i 2} { - set temp [lindex $argv $i] - set temp [string range $temp 1 end] - lappend argv_list $temp - lappend value_list [lindex $argv [expr $i+1]] - } - foreach argument $argv_list value $value_list { - switch $argument { - "cmd" {set Para(cmd) $value;} - } - } - } -} - -set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35" -set Para(ModuleName) "sgmii_gbe_pcs35" -set Para(lib) "/home/greg/sgmii_gbepcs_v3.5/lib" -set Para(CoreName) "SGMII/Gb Ethernet PCS" -set Para(arch) "ep5c00" -set Para(family) "latticeecp3" -set Para(Family) "latticeecp3" -set Para(design) "VHDL" -set Para(install_dir) "/opt/lattice/diamond/1.4.2.105/bin/lin/../.." -set Para(Bin) "/opt/lattice/diamond/1.4.2.105/bin/lin" -set Para(SpeedGrade) "Para(spd)" -set Para(FPGAPath) "/opt/lattice/diamond/1.4.2.105/bin/lin/../../ispfpga/bin/sol" - -lappend auto_path "/home/greg/sgmii_gbepcs_v3.5/gui" - -lappend auto_path "/home/greg/sgmii_gbepcs_v3.5/script" -package require Core_Generate - -lappend auto_path "/opt/lattice/diamond/1.4.2.105/tcltk/lib/ipwidgets/ispipbuilder/../runproc" -package require runcmd - - -set Para(result) [GenerateCore] diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ipx b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ipx deleted file mode 100644 index 5e5982e..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ipx +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.lpc b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.lpc deleted file mode 100644 index 38611bd..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.lpc +++ /dev/null @@ -1,26 +0,0 @@ -[Device] -Family=ep5c00 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=IPCFG -CoreStatus=Demo -CoreName=SGMII/Gb Ethernet PCS -CoreRevision=3.5 -ModuleName=sgmii_gbe_pcs35 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=06/19/2012 -Time=09:57:17 - -[Parameters] -RX_CTC=2 -RX_CTC_LOW=16 -RX_CTC_HIGH=32 -EasyConnect=1 diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo deleted file mode 100644 index a1ce723aa77bc106b0319797e0c73625ab824b09..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 389045 zcmb4s34B~ty?>LIG6G^mz+|#b(kzqGHZzlCW|FozNxCG^C3JzX&ZJ4&MA{}KT>>IR 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zr;yGe@JJ5nJOYnJNEZ<3T4PgO0|cG}DHeg}b4ftpC60(|gup8))EXnutB7pT$dFI(arYo&M?6Q|i;SHGqz934 zKx*!Sj6-?U9zw>^6w<@UI95S=6d7{G6W0|Pr^J_yj5?Y3No1VMrtfKF{F^}PhM=Q{ z6hSaX=y?R=>ZrYdVB;!M4+NW*kX}MCzKHZPf-Q1Ly%20uN$QPY+j7!t2+IG-aeWY! z?A?V6x^bG`)#rGzH?IlYdf+-U1kKj#G%K!w^B=cJcdcqt#5JBA}y^Wx^g7gl8 z>BXdX5j4D{d;~kjlLjH!DW5bL!F%#Z?;&_!F6n&)AIKzqfZ#(i!dlY%;bLmT5PVE% zID$`?Q2Q9cZlaAqFd`#HBKT|pqt@bu&sCE~A=o`a8jau!RirTp_K*t3BKQ)heS%=m zBGNbnd)1IWMX}W=8+a6lvhGpgwTLG($5GD2B{pO_f66ggoc!nmLXIiv;B(DuzYI2BQ(60v>c(4 zVbV&3MwOCQAvD$oN8B2O#$}P#A~Zgm^d~|Sib?Abnk4hCM@X*b;x-^OrIOK&2z?$; z+Jw*-1*9s3zLc6bBlMMI-h$BA#f)x6s3ecH4WVyE+m6t8xzu(bG`)zl6QLRTq-um_ z7Ls-$G%JU+8=={v{e{rn2(>*3%_|}8MQFZc*@sYB8MXZgEtKd1gnr7Wb`T-?ULfue zLgl5@4kNTQOgf6tFBPP72yMUTdq9(V+510}UbXjrCiS-WeJ17Fdp?t1 zv-W|mBlUr`*E6ZFz0Wi0by#~mldSVqqau=ZzG{*~vd&k{WDe_mb&X`U&Q~oZpLM>v zHlIH0eAO5(otC?hdCK==< zy>IW)OtL|EApH7D5QTxE&mzl&pnMoho`!SP-*?TdQKC<^=CJnduU?zQR@4rkM zVeh?68fovlOe(bZTqcdO_gf~7w)a{ljj{JxCXKcCSSEd9@2^aYww3lnr82X zO#05=2bnb8-UFHRy}kc2X@B>zuf}g0#@y%a~-{50!r*VD*JJm-?*xp?#zR>wai% z8GY9M(B7hz!`ic$+7f%eV$xE3uVT_Nd!J&`FZLeAq+jj*iAlfNdlQqa^XW1h9H_AO zBqlAl_ai2)u=gS+t+e+cCjDXWK}=c&YyV-A^*N;=k5p;zG)!7+?=noXKAp%_2CTE~ zZznzm(xe^s64Iod z_VUrBYJ2Hu(k^>%WRmrXQ?t&tt4c^m>}8-y)_J$Gm~;%*^3SANd+BG=aeLWk(g|2g zK9f$`%RQ6+wwHP)owApCCY`pIcqW~(mv<)B*-JZ<&f3d5lm4-nbS9m%mvbhax0iAz zU9gvNCjDzK;Y_+{FW+oaBWtbE>S|Jyy=*fn8rG7{Bk-aQ4$$FaYG108=N{1IyYho|OOlpdodq^!;Tbt=-Q)^}~ zzf6j^mtH0{x0hWeS)Y`K$%q#Aa?8|O+Dk2ytWQsQ1tja!lYEoa$olj&Tryjqo+1*p zK0Q5COJ7^uJVdfs-Rif?9PR9-lo_?U)rZEDtZwzJ6p~^upG>m4)w`M`t6TjE@g>O{)vew$k7RYL%RQS$R=0X?4mGP=y>Bkb>Q;Xv zn`CvX_Yadi_AU)V9Dz5oCK diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35_bb.v b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35_bb.v deleted file mode 100644 index b233912..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35_bb.v +++ /dev/null @@ -1,143 +0,0 @@ -//============================================================================= -// Verilog module generated by IPExpress 06/19/2012 09:57:30 -// Filename: sgmii_gbe_pcs35_bb.v -// Copyright(c) 2008 Lattice Semiconductor Corporation. All rights reserved. -//============================================================================= - -//--------------------------------------------------------------- -// sgmii_gbe_pcs35 synthesis black box definition -//--------------------------------------------------------------- - -/* WARNING - Changes to this file should be performed by re-running IPexpress -or modifying the .LPC file and regenerating the core. Other changes may lead -to inconsistent simulation and/or implemenation results */ - - - - - - -module sgmii_gbe_pcs35 ( - // Control Interface - rst_n, - signal_detect, - gbe_mode, - sgmii_mode, - operational_rate, - debug_link_timer_short, - force_isolate, - force_loopback, - force_unidir, - - rx_compensation_err, - ctc_drop_flag, - ctc_add_flag, - an_link_ok, - - // G/MII Interface - tx_clock_enable_sink , - tx_clock_enable_source , - tx_clk_125, - tx_d, - tx_en, - tx_er, - - rx_clock_enable_sink , - rx_clock_enable_source , - rx_clk_125, - rx_d, - rx_dv, - rx_er, - col, - crs, - - // 8-bit Interface - tx_data, - tx_kcntl, - tx_disparity_cntl, - xmit_autoneg, - - serdes_recovered_clk, - rx_data, - rx_kcntl, - rx_even , - rx_disp_err , - rx_cv_err , - rx_err_decode_mode , - - // Managment Control Outputs - mr_an_complete, - mr_page_rx, - mr_lp_adv_ability, - - // Managment Control Inputs - mr_main_reset, - mr_an_enable, - mr_restart_an, - mr_adv_ability - ); - - - -// Control Interface -input rst_n ; -input signal_detect ; -input gbe_mode ; -input sgmii_mode ; -input [1:0] operational_rate ; -input debug_link_timer_short ; -input force_isolate ; -input force_loopback ; -input force_unidir ; - -output rx_compensation_err ; -output ctc_drop_flag ; -output ctc_add_flag ; -output an_link_ok ; - -// G/MII Interface -input tx_clock_enable_sink; -output tx_clock_enable_source; -input tx_clk_125 ; -input [7:0] tx_d ; -input tx_en ; -input tx_er ; - -input rx_clock_enable_sink; -output rx_clock_enable_source; -input rx_clk_125 ; -output [7:0] rx_d ; -output rx_dv ; -output rx_er ; -output col ; -output crs ; - -// 8-bit Interface -output [7:0] tx_data ; -output tx_kcntl; -output tx_disparity_cntl; -output xmit_autoneg; - -input serdes_recovered_clk ; -input [7:0] rx_data ; -input rx_even ; -input rx_kcntl; -input rx_disp_err ; -input rx_cv_err ; -input rx_err_decode_mode ; - -// Managment Control Outputs -output mr_an_complete; -output mr_page_rx; -output [15:0] mr_lp_adv_ability; - -// Managment Control Inputs -input mr_main_reset; -input mr_an_enable; -input mr_restart_an; -input [15:0] mr_adv_ability; - - - -endmodule - diff --git a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35_beh.v b/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35_beh.v deleted file mode 100644 index 65d30ce..0000000 --- a/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35_beh.v +++ /dev/null @@ -1,3372 +0,0 @@ -// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1 -// created on Fri Mar 23 11:01:38 CST 2012 -// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved -// obfuscator_exe version 1.mar0807 -// top -`define SGMII_NO_ENC -`define SGMII_YES_CTC_DYNAMIC -`define SGMII_FIFO_FAMILY_ECP3 -`define SGMII_YES_SINGLE_CLOCK -`timescale 1 ns / 100 ps -module vi7cf1f (uve78fb, an3c7dd, fne3eec, ie1f767, zkfbb38, xjdd9c2, - rtece16, ay670b6, tj385b0, blc2d86, lf16c36, wyb61b7, zzb0db9, - vk86dcf); -input [17:0] uve78fb; -input an3c7dd; -input fne3eec; -input ie1f767; -input zkfbb38; -input xjdd9c2; -input rtece16; -input [9:0] ay670b6; -input [9:0] tj385b0; -output [17:0] blc2d86; -output lf16c36; -output wyb61b7; -output zzb0db9; -output vk86dcf; -reg [17 : 0] icc175e; -reg ngbaf0; -reg fa5d782; -reg faebc13; -reg of5e09b; -reg uif04dc; -reg co826e0; -reg [9 : 0] xl13701; -reg [9 : 0] nt9b80e; -reg [2047:0] shdc077; -wire [8:0] eae03bd; -localparam ba1de9 = 9,ngef4b = 32'hfdffc68b; -localparam [31:0] ea77a5a = ngef4b; -localparam the9682 = ngef4b & 4'hf; -localparam [11:0] fn5a0bd = 'h7ff; -wire [(1 << the9682) -1:0] uk82f73; -reg [ba1de9-1:0] jebdcc5; -reg [the9682-1:0] dm7315a [0:1]; -reg [the9682-1:0] nec5698; -reg aa2b4c2; -integer xj5a610; -integer qtd3086; -AND2 gq98434 (.A(ie1f767), .B(uk10d0f), .Z(ng86878)); INV aa343c2 (.A(ana1e10), .Z(uk10d0f)); AND2 go78421 (.A(zkfbb38), .B(mg10847), .Z(db84238)); INV ym211c6 (.A(gd8e31), .Z(mg10847)); OR2 vx38c6b (.A(xjdd9c2), .B(rtece16), .Z(ou8d7e9)); XOR2 pf6bf48 (.A(rt5fa47), .B(yxfd23f), .Z(pfe91fc)); XOR2 ps48fe7 (.A(yxfd23f), .B(tw3f9da), .Z(blfced2)); XOR2 qte7697 (.A(tw3f9da), .B(psda5e1), .Z(fnd2f0a)); XOR2 aa97857 (.A(psda5e1), .B(vie15c8), .Z(gqae43)); XOR2 by57218 (.A(vie15c8), .B(dzc8610), .Z(cm43086)); XOR2 wl18431 (.A(dzc8610), .B(ec10c6f), .Z(pu86378)); XOR2 uk31bc3 (.A(ec10c6f), .B(gb6f0c9), .Z(qg7864c)); XOR2 czc3260 (.A(gb6f0c9), .B(uvc982f), .Z(me4c17d)); XOR2 yx60be8 (.A(uvc982f), .B(fc2fa21), .Z(me7d10b)); XOR2 wje8858 (.A(fc2fa21), .B(ym21624), .Z(fcb121)); XOR2 xw5890b (.A(osc485a), .B(mg242d1), .Z(mg21689)); XOR2 ngb449 (.A(mg242d1), .B(wwd125e), .Z(hq892f1)); XOR2 ic4978a (.A(wwd125e), .B(uv5e284), .Z(rgf1424)); XOR2 gd8a122 (.A(uv5e284), .B(ph848ae), .Z(uk24577)); XOR2 bn22bb9 (.A(ph848ae), .B(anaee78), .Z(yk773c5)); XOR2 mgb9e29 (.A(anaee78), .B(ay78a4b), .Z(hoc5259)); XOR2 gd292ca (.A(ay78a4b), .B(kd4b2a8), .Z(kq59545)); XOR2 tucaa29 (.A(kd4b2a8), .B(lsa8a57), .Z(hb452ba)); XOR2 gd295d6 (.A(lsa8a57), .B(ho575ae), .Z(phbad72)); XOR2 uvd6b96 (.A(ho575ae), .B(anae5af), .Z(ui72d7c)); defparam do96be0.initval = 16'h6996 ; ROM16X1 do96be0 (.AD3(fpaf81f), .AD2(ne7c0ff), .AD1(cme07fa), .AD0(nt3fd1), .DO0(aa1fe8e)) ; defparam qgff471.initval = 16'h6996 ; ROM16X1 qgff471 (.AD3(med1c49), .AD2(db8e248), .AD1(jp71247), .AD0(tw8923e), .DO0(ay491f2)) ; defparam fa48f90.initval = 16'h6996 ; ROM16X1 fa48f90 (.AD3(cme07fa), .AD2(nt3fd1), .AD1(oh9068d), .AD0(oh9068d), .DO0(qi1a36b)) ; defparam kqd1b58.initval = 16'h6996 ; ROM16X1 kqd1b58 (.AD3(ne7c0ff), .AD2(cme07fa), .AD1(nt3fd1), .AD0(oh9068d), .DO0(ba139a)) ; defparam lf9cd2.initval = 16'h6996 ; ROM16X1 lf9cd2 (.AD3(tw8923e), .AD2(fpaf81f), .AD1(ne7c0ff), .AD0(qi1a36b), .DO0(xybd739)) ; defparam faeb9ca.initval = 16'h6996 ; ROM16X1 faeb9ca (.AD3(jp71247), .AD2(tw8923e), .AD1(fpaf81f), .AD0(ba139a), .DO0(wy98918)) ; defparam goc48c0.initval = 16'h6996 ; ROM16X1 goc48c0 (.AD3(db8e248), .AD2(jp71247), .AD1(tw8923e), .AD0(aa1fe8e), .DO0(ph9952)) ; defparam yk4ca97.initval = 16'h6996 ; ROM16X1 yk4ca97 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(oh9068d), .AD0(oh9068d), .DO0(jpcd4c1)) ; defparam al6a60e.initval = 16'h6996 ; ROM16X1 al6a60e (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rie809), .AD0(oh9068d), .DO0(bna0256)) ; defparam do12b7.initval = 16'h6996 ; ROM16X1 do12b7 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(rib75b1), .AD0(rie809), .DO0(ofd6c5e)) ; defparam ukb62f5.initval = 16'h6996 ; ROM16X1 ukb62f5 (.AD3(nt8bd4c), .AD2(rib75b1), .AD1(rie809), .AD0(oh9068d), .DO0(su4cd40)) ; defparam xw66a01.initval = 16'h6996 ; ROM16X1 xw66a01 (.AD3(aa1fe8e), .AD2(ay491f2), .AD1(su4cd40), .AD0(oh9068d), .DO0(ld5a793)) ; defparam yxd3c9e.initval = 16'h6996 ; ROM16X1 yxd3c9e (.AD3(gbf27ae), .AD2(zm93d75), .AD1(hd9ebab), .AD0(uif5d5f), .DO0(iraeaf9)) ; defparam mr757cd.initval = 16'h6996 ; ROM16X1 mr757cd (.AD3(pf5f365), .AD2(fnf9b2e), .AD1(xjcd977), .AD0(lq6cbbf), .DO0(gb65dfa)) ; defparam mg2efd4.initval = 16'h6996 ; ROM16X1 mg2efd4 (.AD3(hd9ebab), .AD2(uif5d5f), .AD1(oh9068d), .AD0(oh9068d), .DO0(sj8e0d)) ; defparam xw4706d.initval = 16'h6996 ; ROM16X1 xw4706d (.AD3(zm93d75), .AD2(hd9ebab), .AD1(uif5d5f), .AD0(oh9068d), .DO0(al5e34f)) ; defparam nef1a7c.initval = 16'h6996 ; ROM16X1 nef1a7c (.AD3(lq6cbbf), .AD2(gbf27ae), .AD1(zm93d75), .AD0(sj8e0d), .DO0(ux18596)) ; defparam xjc2cb5.initval = 16'h6996 ; ROM16X1 xjc2cb5 (.AD3(xjcd977), .AD2(lq6cbbf), .AD1(gbf27ae), .AD0(al5e34f), .DO0(vi764fd)) ; defparam pub27eb.initval = 16'h6996 ; ROM16X1 pub27eb (.AD3(fnf9b2e), .AD2(xjcd977), .AD1(lq6cbbf), .AD0(iraeaf9), .DO0(medbb14)) ; defparam lddd8a1.initval = 16'h6996 ; ROM16X1 lddd8a1 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(oh9068d), .AD0(oh9068d), .DO0(ay772e2)) ; defparam cob9711.initval = 16'h6996 ; ROM16X1 cob9711 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(ng1100c), .AD0(oh9068d), .DO0(zx40318)) ; defparam tw18c6.initval = 16'h6996 ; ROM16X1 tw18c6 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(mrc6794), .AD0(ng1100c), .DO0(lf9e52c)) ; defparam yxf2966.initval = 16'h6996 ; ROM16X1 yxf2966 (.AD3(vxa59a6), .AD2(mrc6794), .AD1(ng1100c), .AD0(oh9068d), .DO0(swa6d19)) ; defparam kf368c9.initval = 16'h6996 ; ROM16X1 kf368c9 (.AD3(iraeaf9), .AD2(gb65dfa), .AD1(swa6d19), .AD0(oh9068d), .DO0(xj641e9)) ; XOR2 xy20f4f (.A(ym21624), .B(uif5d5f), .Z(jpe9ea6)); XOR2 rt4f536 (.A(nt3fd1), .B(anae5af), .Z(iea6de0)); defparam ir36f01.initval = 16'h0410 ; ROM16X1 ir36f01 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(su6205e)) ; defparam ec102f0.initval = 16'h1004 ; ROM16X1 ec102f0 (.AD3(iebc062), .AD2(anae5af), .AD1(nt3fd1), .AD0(oh9068d), .DO0(fce507)) ; defparam ww7283b.initval = 16'h0140 ; ROM16X1 ww7283b (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(fnc7d4e)) ; defparam ou3ea76.initval = 16'h4001 ; ROM16X1 ou3ea76 (.AD3(bna0ec7), .AD2(ym21624), .AD1(uif5d5f), .AD0(oh9068d), .DO0(cb8011e)) ; INV qi8f4 (.A(do47a1), .Z(an23d0a)); AND2 vk1e855 (.A(dmf42ab), .B(an23d0a), .Z(ecaad5)); AND2 nr556a8 (.A(dmf42ab), .B(do47a1), .Z(fad51e7)); defparam baa8f3b.CSDECODE_R = 3'b000 ; defparam baa8f3b.CSDECODE_W = 3'b000 ; defparam baa8f3b.GSR = "ENABLED" ; defparam baa8f3b.RESETMODE = "ASYNC" ; defparam baa8f3b.REGMODE = "NOREG" ; defparam baa8f3b.DATA_WIDTH_R = 18 ; defparam baa8f3b.DATA_WIDTH_W = 18 ; PDP16KA baa8f3b (.DI0(uve78fb[0]), .DI1(uve78fb[1]), .DI2(uve78fb[2]), .DI3(uve78fb[3]), .DI4(uve78fb[4]), .DI5(uve78fb[5]), .DI6(uve78fb[6]), .DI7(uve78fb[7]), .DI8(uve78fb[8]), .DI9(uve78fb[9]), .DI10(uve78fb[10]), .DI11(uve78fb[11]), .DI12(uve78fb[12]), .DI13(uve78fb[13]), .DI14(uve78fb[14]), .DI15(uve78fb[15]), .DI16(uve78fb[16]), .DI17(uve78fb[17]), .DI18(uve78fb[0]), .DI19(uve78fb[1]), .DI20(uve78fb[2]), .DI21(uve78fb[3]), .DI22(uve78fb[4]), .DI23(uve78fb[5]), .DI24(uve78fb[6]), .DI25(uve78fb[7]), .DI26(uve78fb[8]), .DI27(uve78fb[9]), .DI28(uve78fb[10]), .DI29(uve78fb[11]), .DI30(uve78fb[12]), .DI31(uve78fb[13]), .DI32(uve78fb[14]), .DI33(uve78fb[15]), .DI34(uve78fb[16]), .DI35(uve78fb[17]), .ADW0(oh3c44c), .ADW1(oh3c44c), .ADW2(oh9068d), .ADW3(oh9068d), .ADW4(me4c91b), .ADW5(dz648d9), .ADW6(ou246ce), .ADW7(ep23671), .ADW8(xy1b38c), .ADW9(qtd9c62), .ADW10(kqce314), .ADW11(nr718a1), .ADW12(do8c50f), .ADW13(cm6287a), .CEW(ng86878), .CLKW(an3c7dd), .WE(oh3c44c), .CSW0(oh9068d), .CSW1(oh9068d), .CSW2(oh9068d), .ADR0(oh9068d), .ADR1(oh9068d), .ADR2(oh9068d), .ADR3(oh9068d), .ADR4(yx4e2a2), .ADR5(vv71515), .ADR6(mt8a8ae), .ADR7(yx54574), .ADR8(xya2ba5), .ADR9(wy15d2b), .ADR10(epae958), .ADR11(hb74ac5), .ADR12(jra562f), .ADR13(ou2b17f), .CER(db84238), .CLKR(fne3eec), .CSR0(oh9068d), .CSR1(oh9068d), .CSR2(oh9068d), .RST(xjdd9c2), .DO0(blc2d86[0]), .DO1(blc2d86[1]), .DO2(blc2d86[2]), .DO3(blc2d86[3]), .DO4(blc2d86[4]), .DO5(blc2d86[5]), .DO6(blc2d86[6]), .DO7 -(blc2d86[7]), .DO8(blc2d86[8]), .DO9(blc2d86[9]), .DO10(blc2d86[10]), .DO11(blc2d86[11]), .DO12(blc2d86[12]), .DO13(blc2d86[13]), .DO14(blc2d86[14]), .DO15(blc2d86[15]), .DO16(blc2d86[16]), .DO17(blc2d86[17]), .DO18(), .DO19(), .DO20(), .DO21(), .DO22(), .DO23(), .DO24(), .DO25(), .DO26(), .DO27(), .DO28(), .DO29(), .DO30(), .DO31(), .DO32(), .DO33(), .DO34(), .DO35()) ; defparam vi478a0.GSR = "ENABLED" ; FD1P3BX vi478a0 (.D(mre2814), .SP(ng86878), .CK(an3c7dd), .PD(xjdd9c2), .Q(rt5fa47)) ; defparam hda57e2.GSR = "ENABLED" ; FD1P3DX hda57e2 (.D(ld5f8b9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(yxfd23f)) ; defparam hocfd61.GSR = "ENABLED" ; FD1P3DX hocfd61 (.D(mef5856), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tw3f9da)) ; defparam irb13c0.GSR = "ENABLED" ; FD1P3DX irb13c0 (.D(vv4f023), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(psda5e1)) ; defparam ou1f0d5.GSR = "ENABLED" ; FD1P3DX ou1f0d5 (.D(yxc3544), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(vie15c8)) ; defparam hq252d5.GSR = "ENABLED" ; FD1P3DX hq252d5 (.D(al4b55d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dzc8610)) ; defparam kdedeea.GSR = "ENABLED" ; FD1P3DX kdedeea (.D(hb7baa4), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ec10c6f)) ; defparam sj26e64.GSR = "ENABLED" ; FD1P3DX sj26e64 (.D(mgb992f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gb6f0c9)) ; defparam ne79b92.GSR = "ENABLED" ; FD1P3DX ne79b92 (.D(fn6e49f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(uvc982f)) ; defparam vife21d.GSR = "ENABLED" ; FD1P3DX vife21d (.D(uk8875a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fc2fa21)) ; defparam dmd0156.GSR = "ENABLED" ; FD1P3DX dmd0156 (.D(wy559d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ym21624)) ; defparam she8601.GSR = "ENABLED" ; FD1P3DX she8601 (.D(pfe91fc), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fa69a9c)) ; defparam jc4d4e2.GSR = "ENABLED" ; FD1P3DX jc4d4e2 (.D(blfced2), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(fp942e5)) ; defparam cba172f.GSR = "ENABLED" ; FD1P3DX cba172f (.D(fnd2f0a), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(eaea018)) ; defparam dz500c0.GSR = "ENABLED" ; FD1P3DX dz500c0 (.D(gqae43), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(gd3cf5c)) ; defparam ene7ae5.GSR = "ENABLED" ; FD1P3DX ene7ae5 (.D(cm43086), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ld6e606)) ; defparam fa73036.GSR = "ENABLED" ; FD1P3DX fa73036 (.D(pu86378), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(pu997a9)) ; defparam gocbd4b.GSR = "ENABLED" ; FD1P3DX gocbd4b (.D(qg7864c), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dmc506a)) ; defparam bn28352.GSR = "ENABLED" ; FD1P3DX bn28352 (.D(me4c17d), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(twbd919)) ; defparam fnec8cb.GSR = "ENABLED" ; FD1P3DX fnec8cb (.D(me7d10b), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ipf79c5)) ; defparam ksbce2c.GSR = "ENABLED" ; FD1P3DX ksbce2c (.D(fcb121), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(zzceee)) ; defparam ay67777.GSR = "ENABLED" ; FD1P3DX ay67777 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(tuc0cca)) ; defparam db6653.GSR = "ENABLED" ; FD1P3DX db6653 (.D(rt5fa47), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(me4c91b)) ; defparam pseb66c.GSR = "ENABLED" ; FD1P3DX pseb66c (.D(yxfd23f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(dz648d9)) ; defparam cba4eca.GSR = "ENABLED" ; FD1P3DX cba4eca (.D(tw3f9da), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ou246ce)) ; defparam aa31aa0.GSR = "ENABLED" ; FD1P3DX aa31aa0 (.D(psda5e1), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(ep23671)) ; defparam xj45bd5.GSR = "ENABLED" ; FD1P3DX xj45bd5 (.D(vie15c8), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(xy1b38c)) ; defparam jcf48be.GSR = "ENABLED" ; FD1P3DX jcf48be (.D(dzc8610), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(qtd9c62)) ; defparam suefb70.GSR = "ENABLED" ; FD1P3DX suefb70 (.D(ec10c6f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(kqce314)) ; defparam ic4cd37.GSR = "ENABLED" ; FD1P3DX ic4cd37 (.D(gb6f0c9), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(nr718a1)) ; defparam su593c1.GSR = "ENABLED" ; FD1P3DX su593c1 (.D(uvc982f), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(do8c50f)) ; defparam kd6f03b.GSR = "ENABLED" ; FD1P3DX kd6f03b (.D(fc2fa21), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(cm6287a)) ; defparam tj3a29.GSR = "ENABLED" ; FD1P3DX tj3a29 (.D(ym21624), .SP(ng86878), .CK(an3c7dd), .CD(xjdd9c2), .Q(bna0ec7)) ; defparam mgacd25.GSR = "ENABLED" ; FD1P3BX mgacd25 (.D(uk34943), .SP(db84238), .CK(fne3eec), .PD(ou8d7e9), .Q(osc485a)) ; defparam jr198f9.GSR = "ENABLED" ; FD1P3DX jr198f9 (.D(rg63e74), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mg242d1)) ; defparam gqa31c6.GSR = "ENABLED" ; FD1P3DX gqa31c6 (.D(xjc7184), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wwd125e)) ; defparam nt27f5f.GSR = "ENABLED" ; FD1P3DX nt27f5f (.D(qtfd7fa), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uv5e284)) ; defparam osd47c8.GSR = "ENABLED" ; FD1P3DX osd47c8 (.D(ym1f209), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ph848ae)) ; defparam vi48da6.GSR = "ENABLED" ; FD1P3DX vi48da6 (.D(gd36998), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anaee78)) ; defparam qgc4a28.GSR = "ENABLED" ; FD1P3DX qgc4a28 (.D(vx28a0b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ay78a4b)) ; defparam mr5ede2.GSR = "ENABLED" ; FD1P3DX mr5ede2 (.D(jeb78ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kd4b2a8)) ; defparam os72144.GSR = "ENABLED" ; FD1P3DX os72144 (.D(cb8510c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(lsa8a57)) ; defparam th64d07.GSR = "ENABLED" ; FD1P3DX th64d07 (.D(co341f5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ho575ae)) ; defparam fca8d00.GSR = "ENABLED" ; FD1P3DX fca8d00 (.D(mg34010), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(anae5af)) ; defparam ux80e29.GSR = "ENABLED" ; FD1P3DX ux80e29 (.D(mg21689), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kq6dea3)) ; defparam yx6f518.GSR = "ENABLED" ; FD1P3DX yx6f518 (.D(hq892f1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ks24221)) ; defparam wy21109.GSR = "ENABLED" ; FD1P3DX wy21109 (.D(rgf1424), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ne4d871)) ; defparam jc6c38b.GSR = "ENABLED" ; FD1P3DX jc6c38b (.D(uk24577), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(kqde7bd)) ; defparam rtf3de8.GSR = "ENABLED" ; FD1P3DX rtf3de8 (.D(yk773c5), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hd378a0)) ; defparam cobc506.GSR = "ENABLED" ; FD1P3DX cobc506 (.D(hoc5259), .SP( -db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ir857bb)) ; defparam mg2bddc.GSR = "ENABLED" ; FD1P3DX mg2bddc (.D(kq59545), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(uxdb2a)) ; defparam me6d955.GSR = "ENABLED" ; FD1P3DX me6d955 (.D(hb452ba), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vi42afb)) ; defparam mg157da.GSR = "ENABLED" ; FD1P3DX mg157da (.D(phbad72), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qi8dcd0)) ; defparam jp6e681.GSR = "ENABLED" ; FD1P3DX jp6e681 (.D(ui72d7c), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ps738fb)) ; defparam pu9c7da.GSR = "ENABLED" ; FD1P3DX pu9c7da (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(qv9f0d5)) ; defparam mrf86ac.GSR = "ENABLED" ; FD1P3DX mrf86ac (.D(osc485a), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx4e2a2)) ; defparam ux29433.GSR = "ENABLED" ; FD1P3DX ux29433 (.D(mg242d1), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(vv71515)) ; defparam nr7e701.GSR = "ENABLED" ; FD1P3DX nr7e701 (.D(wwd125e), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(mt8a8ae)) ; defparam jpf32c7.GSR = "ENABLED" ; FD1P3DX jpf32c7 (.D(uv5e284), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(yx54574)) ; defparam shd959b.GSR = "ENABLED" ; FD1P3DX shd959b (.D(ph848ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(xya2ba5)) ; defparam xj503f8.GSR = "ENABLED" ; FD1P3DX xj503f8 (.D(anaee78), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(wy15d2b)) ; defparam qtf8b73.GSR = "ENABLED" ; FD1P3DX qtf8b73 (.D(ay78a4b), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(epae958)) ; defparam sh5ec8b.GSR = "ENABLED" ; FD1P3DX sh5ec8b (.D(kd4b2a8), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(hb74ac5)) ; defparam dz7bf90.GSR = "ENABLED" ; FD1P3DX dz7bf90 (.D(lsa8a57), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(jra562f)) ; defparam zz9bb1d.GSR = "ENABLED" ; FD1P3DX zz9bb1d (.D(ho575ae), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(ou2b17f)) ; defparam kdf770e.GSR = "ENABLED" ; FD1P3DX kdf770e (.D(anae5af), .SP(db84238), .CK(fne3eec), .CD(ou8d7e9), .Q(iebc062)) ; defparam en654a8.GSR = "ENABLED" ; FD1S3DX en654a8 (.D(fa69a9c), .CK(fne3eec), .CD(xjdd9c2), .Q(ld454ea)) ; defparam ls2a756.GSR = "ENABLED" ; FD1S3DX ls2a756 (.D(fp942e5), .CK(fne3eec), .CD(xjdd9c2), .Q(pub2248)) ; defparam vx91243.GSR = "ENABLED" ; FD1S3DX vx91243 (.D(eaea018), .CK(fne3eec), .CD(xjdd9c2), .Q(uk1f410)) ; defparam qgfa080.GSR = "ENABLED" ; FD1S3DX qgfa080 (.D(gd3cf5c), .CK(fne3eec), .CD(xjdd9c2), .Q(fc164c)) ; defparam pub262.GSR = "ENABLED" ; FD1S3DX pub262 (.D(ld6e606), .CK(fne3eec), .CD(xjdd9c2), .Q(bn13340)) ; defparam ri99a06.GSR = "ENABLED" ; FD1S3DX ri99a06 (.D(pu997a9), .CK(fne3eec), .CD(xjdd9c2), .Q(zz32c7f)) ; defparam ri963fe.GSR = "ENABLED" ; FD1S3DX ri963fe (.D(dmc506a), .CK(fne3eec), .CD(xjdd9c2), .Q(kdf2b23)) ; defparam cb9591c.GSR = "ENABLED" ; FD1S3DX cb9591c (.D(twbd919), .CK(fne3eec), .CD(xjdd9c2), .Q(pse41ee)) ; defparam ls20f73.GSR = "ENABLED" ; FD1S3DX ls20f73 (.D(ipf79c5), .CK(fne3eec), .CD(xjdd9c2), .Q(an9a9d3)) ; defparam qgd4e9d.GSR = "ENABLED" ; FD1S3DX qgd4e9d (.D(zzceee), .CK(fne3eec), .CD(xjdd9c2), .Q(qte84e9)) ; defparam xw4274d.GSR = "ENABLED" ; FD1S3DX xw4274d (.D(tuc0cca), .CK(fne3eec), .CD(xjdd9c2), .Q(rt6be72)) ; defparam hb5f397.GSR = "ENABLED" ; FD1S3DX hb5f397 (.D(kq6dea3), .CK(an3c7dd), .CD(ou8d7e9), .Q(anbee41)) ; defparam enf720c.GSR = "ENABLED" ; FD1S3DX enf720c (.D(ks24221), .CK(an3c7dd), .CD(ou8d7e9), .Q(cz651af)) ; defparam nt28d7d.GSR = "ENABLED" ; FD1S3DX nt28d7d (.D(ne4d871), .CK(an3c7dd), .CD(ou8d7e9), .Q(lqee0f9)) ; defparam gb707ca.GSR = "ENABLED" ; FD1S3DX gb707ca (.D(kqde7bd), .CK(an3c7dd), .CD(ou8d7e9), .Q(kd54432)) ; defparam pua2195.GSR = "ENABLED" ; FD1S3DX pua2195 (.D(hd378a0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hdaa0f5)) ; defparam bl507ae.GSR = "ENABLED" ; FD1S3DX bl507ae (.D(ir857bb), .CK(an3c7dd), .CD(ou8d7e9), .Q(os774cd)) ; defparam ntba669.GSR = "ENABLED" ; FD1S3DX ntba669 (.D(uxdb2a), .CK(an3c7dd), .CD(ou8d7e9), .Q(xj4f8b2)) ; defparam ho7c596.GSR = "ENABLED" ; FD1S3DX ho7c596 (.D(vi42afb), .CK(an3c7dd), .CD(ou8d7e9), .Q(lsb2b92)) ; defparam kf95c92.GSR = "ENABLED" ; FD1S3DX kf95c92 (.D(qi8dcd0), .CK(an3c7dd), .CD(ou8d7e9), .Q(hd94841)) ; defparam oha420e.GSR = "ENABLED" ; FD1S3DX oha420e (.D(ps738fb), .CK(an3c7dd), .CD(ou8d7e9), .Q(wj7532a)) ; defparam swa9954.GSR = "ENABLED" ; FD1S3DX swa9954 (.D(qv9f0d5), .CK(an3c7dd), .CD(ou8d7e9), .Q(nta035d)) ; defparam vk1aef.GSR = "ENABLED" ; FD1S3DX vk1aef (.D(ld454ea), .CK(fne3eec), .CD(xjdd9c2), .Q(nt8bd4c)) ; defparam kddce86.GSR = "ENABLED" ; FD1S3DX kddce86 (.D(pub2248), .CK(fne3eec), .CD(xjdd9c2), .Q(rib75b1)) ; defparam gda4691.GSR = "ENABLED" ; FD1S3DX gda4691 (.D(uk1f410), .CK(fne3eec), .CD(xjdd9c2), .Q(rie809)) ; defparam lq6c1b1.GSR = "ENABLED" ; FD1S3DX lq6c1b1 (.D(fc164c), .CK(fne3eec), .CD(xjdd9c2), .Q(med1c49)) ; defparam ay5cd66.GSR = "ENABLED" ; FD1S3DX ay5cd66 (.D(bn13340), .CK(fne3eec), .CD(xjdd9c2), .Q(db8e248)) ; defparam ie87613.GSR = "ENABLED" ; FD1S3DX ie87613 (.D(zz32c7f), .CK(fne3eec), .CD(xjdd9c2), .Q(jp71247)) ; defparam qtc9ff3.GSR = "ENABLED" ; FD1S3DX qtc9ff3 (.D(kdf2b23), .CK(fne3eec), .CD(xjdd9c2), .Q(tw8923e)) ; defparam dmee8f0.GSR = "ENABLED" ; FD1S3DX dmee8f0 (.D(pse41ee), .CK(fne3eec), .CD(xjdd9c2), .Q(fpaf81f)) ; defparam ls1e282.GSR = "ENABLED" ; FD1S3DX ls1e282 (.D(an9a9d3), .CK(fne3eec), .CD(xjdd9c2), .Q(ne7c0ff)) ; defparam ks92bcc.GSR = "ENABLED" ; FD1S3DX ks92bcc (.D(qte84e9), .CK(fne3eec), .CD(xjdd9c2), .Q(cme07fa)) ; defparam zzcce6.GSR = "ENABLED" ; FD1S3DX zzcce6 (.D(rt6be72), .CK(fne3eec), .CD(xjdd9c2), .Q(nt3fd1)) ; defparam ntba8bf.GSR = "ENABLED" ; FD1S3DX ntba8bf (.D(anbee41), .CK(an3c7dd), .CD(ou8d7e9), .Q(vxa59a6)) ; defparam zkf1773.GSR = "ENABLED" ; FD1S3DX zkf1773 (.D(cz651af), .CK(an3c7dd), .CD(ou8d7e9), .Q(mrc6794)) ; defparam end649d.GSR = "ENABLED" ; FD1S3DX end649d (.D(lqee0f9), .CK(an3c7dd), .CD(ou8d7e9), .Q(ng1100c)) ; defparam by630c7.GSR = "ENABLED" ; FD1S3DX by630c7 (.D(kd54432), .CK(an3c7dd), .CD(ou8d7e9), .Q(pf5f365)) ; defparam lqd5b3a.GSR = "ENABLED" ; FD1S3DX lqd5b3a (.D(hdaa0f5), .CK(an3c7dd), .CD(ou8d7e9), .Q(fnf9b2e)) ; defparam ym9241e.GSR = "ENABLED" ; FD1S3DX ym9241e (.D(os774cd), .CK(an3c7dd), .CD(ou8d7e9), .Q(xjcd977)) ; defparam cb80a90.GSR = "ENABLED" ; FD1S3DX cb80a90 (.D(xj4f8b2), .CK(an3c7dd), .CD(ou8d7e9), .Q(lq6cbbf)) ; defparam bn284a4.GSR = "ENABLED" ; FD1S3DX bn284a4 (.D(lsb2b92), .CK(an3c7dd), .CD(ou8d7e9), .Q(gbf27ae)) ; defparam wy3bba6.GSR = "ENABLED" ; FD1S3DX wy3bba6 (.D(hd94841), .CK(an3c7dd), .CD(ou8d7e9), .Q(zm93d75)) ; defparam ri867c3.GSR = "ENABLED" ; FD1S3DX ri867c3 (.D(wj7532a), .CK(an3c7dd), . -CD(ou8d7e9), .Q(hd9ebab)) ; defparam mrdc92b.GSR = "ENABLED" ; FD1S3DX mrdc92b (.D(nta035d), .CK(an3c7dd), .CD(ou8d7e9), .Q(uif5d5f)) ; defparam gbe20c9.GSR = "ENABLED" ; FD1S3BX gbe20c9 (.D(fc83261), .CK(fne3eec), .PD(ou8d7e9), .Q(gd8e31)) ; defparam pf617e8.GSR = "ENABLED" ; FD1S3DX pf617e8 (.D(rt5fa3a), .CK(an3c7dd), .CD(xjdd9c2), .Q(ana1e10)) ; defparam do3af23.GSR = "ENABLED" ; FD1S3BX do3af23 (.D(ksbc8d7), .CK(fne3eec), .PD(ou8d7e9), .Q(zzb0db9)) ; defparam bld72e1.GSR = "ENABLED" ; FD1S3DX bld72e1 (.D(aycb870), .CK(an3c7dd), .CD(xjdd9c2), .Q(vk86dcf)) ; CU2 gb70053 (.CI(oh3c44c), .PC1(yxfd23f), .PC0(rt5fa47), .CO(ay53911), .NC1(ld5f8b9), .NC0(mre2814)); CU2 xl22253 (.CI(ay53911), .PC1(psda5e1), .PC0(tw3f9da), .CO(qg53cd7), .NC1(vv4f023), .NC0(mef5856)); CU2 ux9ae77 (.CI(qg53cd7), .PC1(dzc8610), .PC0(vie15c8), .CO(qg77b88), .NC1(al4b55d), .NC0(yxc3544)); CU2 rt7101a (.CI(qg77b88), .PC1(gb6f0c9), .PC0(ec10c6f), .CO(co1ac37), .NC1(mgb992f), .NC0(hb7baa4)); CU2 fc86e67 (.CI(co1ac37), .PC1(fc2fa21), .PC0(uvc982f), .CO(me675cd), .NC1(uk8875a), .NC0(fn6e49f)); CU2 aab9a16 (.CI(me675cd), .PC1(oh9068d), .PC0(ym21624), .CO(xl1638a), .NC1(), .NC0(wy559d)); CU2 xl8e2b5 (.CI(oh3c44c), .PC1(mg242d1), .PC0(osc485a), .CO(vxb5fa1), .NC1(rg63e74), .NC0(uk34943)); CU2 hof43fe (.CI(vxb5fa1), .PC1(uv5e284), .PC0(wwd125e), .CO(dmfe504), .NC1(qtfd7fa), .NC0(xjc7184)); CU2 rva08e7 (.CI(dmfe504), .PC1(anaee78), .PC0(ph848ae), .CO(mre7cae), .NC1(gd36998), .NC0(ym1f209)); CU2 an95d4c (.CI(mre7cae), .PC1(kd4b2a8), .PC0(ay78a4b), .CO(cm4c960), .NC1(jeb78ae), .NC0(vx28a0b)); CU2 kf2c072 (.CI(cm4c960), .PC1(ho575ae), .PC0(lsa8a57), .CO(yk72b5b), .NC1(co341f5), .NC0(cb8510c)); CU2 ld6b623 (.CI(yk72b5b), .PC1(oh9068d), .PC0(anae5af), .CO(wl23d30), .NC1(), .NC0(mg34010)); FSUB2 hof4c2b (.A1(yxfd23f), .A0(rt5fa47), .B1(lf9e52c), .B0(xj641e9), .BI(oh3c44c), .BOUT1(dzd8704), .BOUT0(), .S1(qtc3827), .S0(bn1c13c)); FSUB2 yke09e7 (.A1(psda5e1), .A0(tw3f9da), .B1(ay772e2), .B0(zx40318), .BI(dzd8704), .BOUT1(alc3f66), .BOUT0(), .S1(aa1fb34), .S0(shfd9a1)); FSUB2 xjecd0d (.A1(dzc8610), .A0(vie15c8), .B1(vi764fd), .B0(medbb14), .BI(alc3f66), .BOUT1(jc7312e), .BOUT0(), .S1(wy98973), .S0(goc4b98)); FSUB2 ba25cc1 (.A1(gb6f0c9), .A0(ec10c6f), .B1(iraeaf9), .B0(ux18596), .BI(jc7312e), .BOUT1(xj50641), .BOUT0(), .S1(pu8320f), .S0(xl1907b)); FSUB2 vvc83df (.A1(fc2fa21), .A0(uvc982f), .B1(sj8e0d), .B0(al5e34f), .BI(xj50641), .BOUT1(ayf539a), .BOUT0(), .S1(yma9cd0), .S0(gb4e680)); FSUB2 fa73405 (.A1(oh9068d), .A0(jpe9ea6), .B1(oh9068d), .B0(oh9068d), .BI(ayf539a), .BOUT1(), .BOUT0(), .S1(), .S0(ay5c741)); VHI the3a09 (.Z(oh3c44c)); FSUB2 gbe827d (.A1(ofd6c5e), .A0(ld5a793), .B1(mg242d1), .B0(osc485a), .BI(oh3c44c), .BOUT1(dm6cf8c), .BOUT0(), .S1(su67c62), .S0(ie3e311)); FSUB2 tuf1889 (.A1(jpcd4c1), .A0(bna0256), .B1(uv5e284), .B0(wwd125e), .BI(dm6cf8c), .BOUT1(xj5a0d5), .BOUT0(), .S1(psd06ae), .S0(do83573)); FSUB2 co1ab9b (.A1(wy98918), .A0(ph9952), .B1(anaee78), .B0(ph848ae), .BI(xj5a0d5), .BOUT1(jcca8f5), .BOUT0(), .S1(al547aa), .S0(mga3d55)); FSUB2 ng1eaa9 (.A1(aa1fe8e), .A0(xybd739), .B1(kd4b2a8), .B0(ay78a4b), .BI(jcca8f5), .BOUT1(by58fcd), .BOUT0(), .S1(xjc7e6a), .S0(do3f356)); FSUB2 hbf9ab3 (.A1(qi1a36b), .A0(ba139a), .B1(ho575ae), .B0(lsa8a57), .BI(by58fcd), .BOUT1(fafea05), .BOUT0(), .S1(do47a1), .S0(xya8150)); FSUB2 dz40a83 (.A1(oh9068d), .A0(iea6de0), .B1(oh9068d), .B0(oh9068d), .BI(fafea05), .BOUT1(), .BOUT0(), .S1(), .S0(dmf42ab)); AGEB2 dzc2e84 (.A1(mg242d1), .A0(osc485a), .B1(ofd6c5e), .B0(ld5a793), .CI(db84238), .GE(mg34ebd)); AGEB2 vka75e9 (.A1(uv5e284), .A0(wwd125e), .B1(jpcd4c1), .B0(bna0256), .CI(mg34ebd), .GE(ps52ebf)); AGEB2 co975fb (.A1(anaee78), .A0(ph848ae), .B1(wy98918), .B0(ph9952), .CI(ps52ebf), .GE(yxc6fde)); AGEB2 nt37ef4 (.A1(kd4b2a8), .A0(ay78a4b), .B1(aa1fe8e), .B0(xybd739), .CI(yxc6fde), .GE(vx37459)); AGEB2 rvba2cf (.A1(ho575ae), .A0(lsa8a57), .B1(qi1a36b), .B0(ba139a), .CI(vx37459), .GE(nrf9e15)); AGEB2 hocf0af (.A1(oh9068d), .A0(su6205e), .B1(oh9068d), .B0(fce507), .CI(nrf9e15), .GE(xjd8c37)); FADD2 qtc61be (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(xjd8c37), .COUT1(), .COUT0(), .S1(), .S0(fc83261)); AGEB2 th5ad04 (.A1(yxfd23f), .A0(rt5fa47), .B1(lf9e52c), .B0(xj641e9), .CI(ng86878), .GE(lf3d99f)); AGEB2 theccff (.A1(psda5e1), .A0(tw3f9da), .B1(ay772e2), .B0(zx40318), .CI(lf3d99f), .GE(off2943)); AGEB2 jr94a1c (.A1(dzc8610), .A0(vie15c8), .B1(vi764fd), .B0(medbb14), .CI(off2943), .GE(lf37e37)); AGEB2 lfbf1be (.A1(gb6f0c9), .A0(ec10c6f), .B1(iraeaf9), .B0(ux18596), .CI(lf37e37), .GE(dobd9a4)); AGEB2 hbecd23 (.A1(fc2fa21), .A0(uvc982f), .B1(sj8e0d), .B0(al5e34f), .CI(dobd9a4), .GE(ldf336a)); AGEB2 ng99b57 (.A1(oh9068d), .A0(fnc7d4e), .B1(oh9068d), .B0(cb8011e), .CI(ldf336a), .GE(bld7356)); FADD2 qib9ab6 (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(bld7356), .COUT1(), .COUT0(), .S1(), .S0(rt5fa3a)); AGEB2 yx7526e (.A1(ay670b6[1]), .A0(ay670b6[0]), .B1(su67c62), .B0(ie3e311), .CI(db84238), .GE(ana12fe)); AGEB2 xl97f5 (.A1(ay670b6[3]), .A0(ay670b6[2]), .B1(psd06ae), .B0(do83573), .CI(ana12fe), .GE(fn74e8d)); AGEB2 ria746f (.A1(ay670b6[5]), .A0(ay670b6[4]), .B1(al547aa), .B0(mga3d55), .CI(fn74e8d), .GE(ofd3065)); AGEB2 qi9832c (.A1(ay670b6[7]), .A0(ay670b6[6]), .B1(xjc7e6a), .B0(do3f356), .CI(ofd3065), .GE(nt9f2f)); AGEB2 ld4f97f (.A1(ay670b6[9]), .A0(ay670b6[8]), .B1(do47a1), .B0(xya8150), .CI(nt9f2f), .GE(xjf30e3)); AGEB2 ec9871f (.A1(oh9068d), .A0(fad51e7), .B1(oh9068d), .B0(ecaad5), .CI(xjf30e3), .GE(ipccfc7)); FADD2 ui67e3d (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(ipccfc7), .COUT1(), .COUT0(), .S1(), .S0(ksbc8d7)); AGEB2 lq5ddbc (.A1(qtc3827), .A0(bn1c13c), .B1(tj385b0[1]), .B0(tj385b0[0]), .CI(ng86878), .GE(xl13484)); AGEB2 mt9a426 (.A1(aa1fb34), .A0(shfd9a1), .B1(tj385b0[3]), .B0(tj385b0[2]), .CI(xl13484), .GE(eca69e9)); AGEB2 aa34f49 (.A1(wy98973), .A0(goc4b98), .B1(tj385b0[5]), .B0(tj385b0[4]), .CI(eca69e9), .GE(ip4bdc0)); AGEB2 sh5ee04 (.A1(pu8320f), .A0(xl1907b), .B1(tj385b0[7]), .B0(tj385b0[6]), .CI(ip4bdc0), .GE(db2d4da)); AGEB2 yx6a6d7 (.A1(yma9cd0), .A0(gb4e680), .B1(tj385b0[9]), .B0(tj385b0[8]), .CI(db2d4da), .GE(sue0cf8)); AGEB2 hd67c0 (.A1(oh9068d), .A0(ay5c741), .B1(oh9068d), .B0(oh9068d), .CI(sue0cf8), .GE(cb3c91c)); VLO xwe48e5 (.Z(oh9068d)); FADD2 kf23951 (.A1(oh9068d), .A0(oh9068d), .B1(oh9068d), .B0(oh9068d), .CI(cb3c91c), .COUT1(), .COUT0(), .S1(), .S0(aycb870)); assign lf16c36 = gd8e31; assign wyb61b7 = ana1e10; -always@* begin icc175e<={uve78fb>>1,eae03bd[0]};ngbaf0<=eae03bd[1];fa5d782<=eae03bd[2];faebc13<=eae03bd[3];of5e09b<=eae03bd[4];uif04dc<=eae03bd[5];co826e0<=eae03bd[6];xl13701<={ay670b6>>1,eae03bd[7]};nt9b80e<={tj385b0>>1,eae03bd[8]};end -always@* begin shdc077[2047]<=an3c7dd;shdc077[2046]<=fne3eec;shdc077[2044]<=ie1f767;shdc077[2040]<=zkfbb38;shdc077[2032]<=xjdd9c2;shdc077[2017]<=rtece16;shdc077[1987]<=ay670b6[0];shdc077[1926]<=tj385b0[0];shdc077[1023]<=uve78fb[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[0]};ngbaf0<=eae03bd[1];fa5d782<=eae03bd[2];faebc13<=eae03bd[3];of5e09b<=eae03bd[4];uif04dc<=eae03bd[5];co826e0<=eae03bd[6];xl13701<={ay670b6>>1,eae03bd[7]};nt9b80e<={tj385b0>>1,eae03bd[8]};end -always@* begin shdc077[2047]<=an3c7dd;shdc077[2046]<=fne3eec;shdc077[2044]<=ie1f767;shdc077[2040]<=zkfbb38;shdc077[2032]<=xjdd9c2;shdc077[2017]<=rtece16;shdc077[1987]<=ay670b6[0];shdc077[1926]<=tj385b0[0];shdc077[1023]<=uve78fb[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[0]};ngbaf0<=eae03bd[1];fa5d782<=eae03bd[2];faebc13<=eae03bd[3];of5e09b<=eae03bd[4];uif04dc<=eae03bd[5];co826e0<=eae03bd[6];xl13701<={ay670b6>>1,eae03bd[7]};nt9b80e<={tj385b0>>1,eae03bd[8]};puad6d2<=eae03bd[9];rt6b693<=eae03bd[10];cz5b49e<=eae03bd[11];dmda4f4<=eae03bd[12];nrd27a2<=eae03bd[13];je93d16<=eae03bd[14];jr9e8b3<=eae03bd[15];lqf459f<=eae03bd[16];jea2cfa<=eae03bd[17];rv167d3<=eae03bd[18];oub3e9e<=eae03bd[19];ir9f4f0<=eae03bd[20];ykfa784<=eae03bd[21];shd3c21<=eae03bd[22];db9e10d<=eae03bd[23];kqf086e<=eae03bd[24];hd84371<=eae03bd[25];ec21b8e<=eae03bd[26];yzdc70<=eae03bd[27];vv6e385<=eae03bd[28];jp71c2e<=eae03bd[29];zz8e177<=eae03bd[30];cz70bbf<=eae03bd[31];ux85dfd<=eae03bd[32];ie2efed<=eae03bd[33];kq77f69<=eae03bd[34];dbbfb48<=eae03bd[35];czfda46<=eae03bd[36];yxed235<=eae03bd[37];jc691ad<=eae03bd[38];tu48d6b<=eae03bd[39];ea46b5b<=eae03bd[40];hq35ad8<=eae03bd[41];hqad6c3<=eae03bd[42];fn6b61b<=eae03bd[43];kd5b0de<=eae03bd[44];rtd86f4<=eae03bd[45];yxc37a7<=eae03bd[46];pu1bd3d<=eae03bd[47];gode9eb<=eae03bd[48];nef4f59<=eae03bd[49];doa7acb<=eae03bd[50];vx3d65b<=eae03bd[51];pseb2de<=eae03bd[52];kq596f2<=eae03bd[53];sucb791<=eae03bd[54];yx5bc89<=eae03bd[55];ayde44d<=eae03bd[56];off2268<=eae03bd[57];nt91345<=eae03bd[58];ng89a2f<=eae03bd[59];jc4d17b<=eae03bd[60];yk68bda<=eae03bd[61];hb45ed0<=eae03bd[62];je2f687<=eae03bd[63];rt7b43a<=eae03bd[64];neda1d7<=eae03bd[65];ned0eba<=eae03bd[66];ie875d2<=eae03bd[67];ri3ae91<=eae03bd[68];ldd748a<=eae03bd[69];vxba456<=eae03bd[70];vvd22b7<=eae03bd[71];xl915be<=eae03bd[72];qv8adf7<=eae03bd[73];cm56fbc<=eae03bd[74];dob7de1<=eae03bd[75];yzbef0a<=eae03bd[76];off7854<=eae03bd[77];gqbc2a4<=eae03bd[78];zke1520<=eae03bd[79];mga903<=eae03bd[80];yx54818<=eae03bd[81];uxa40c4<=eae03bd[82];zm20625<=eae03bd[83];ph312b<=eae03bd[84];wl1895f<=eae03bd[85];goc4afc<=eae03bd[86];ba257e1<=eae03bd[87];co2bf0b<=eae03bd[88];rt5f859<=eae03bd[89];zxfc2cf<=eae03bd[90];vie167e<=eae03bd[91];hqb3f3<=eae03bd[92];me59f9b<=eae03bd[93];facfcd8<=eae03bd[94];vv7e6c2<=eae03bd[95];vvf3617<=eae03bd[96];rv9b0bf<=eae03bd[97];vvd85fe<=eae03bd[98];fnc2ff7<=eae03bd[99];qv17fbe<=eae03bd[100];ntbfdf5<=eae03bd[101];dmfefae<=eae03bd[102];czf7d72<=eae03bd[103];qvbeb94<=eae03bd[104];ayf5ca4<=eae03bd[105];epae521<=eae03bd[106];ay7290c<=eae03bd[107];bn94860<=eae03bd[108];sja4306<=eae03bd[109];ie21835<=eae03bd[110];fpc1a8<=eae03bd[111];uv60d46<=eae03bd[112];xl6a34<=eae03bd[113];do351a6<=eae03bd[114];xya8d32<=eae03bd[115];ww46992<=eae03bd[116];uk34c90<=eae03bd[117];gqa6481<=eae03bd[118];ph32408<=eae03bd[119];sw92047<=eae03bd[120];yz90238<=eae03bd[121];zz811c5<=eae03bd[122];ux8e2e<=eae03bd[123];ne47175<=eae03bd[124];hd38bab<=eae03bd[125];lqc5d5f<=eae03bd[126];ou2eafb<=eae03bd[127];ip757d9<=eae03bd[128];mtabecc<=eae03bd[129];th5f665<=eae03bd[130];jcfb32e<=eae03bd[131];czd9973<=eae03bd[132];enccb9c<=eae03bd[133];qt65ce5<=eae03bd[134];ou2e72c<=eae03bd[135];dm73960<=eae03bd[136];xy9cb02<=eae03bd[137];ose5812<=eae03bd[138];an2c090<=eae03bd[139];al60485<=eae03bd[140];wl242d<=eae03bd[141];an1216d<=eae03bd[142];kf90b6c<=eae03bd[143];mt85b64<=eae03bd[144];zz2db25<=eae03bd[145];me6d92e<=eae03bd[146];ne6c970<=eae03bd[147];xj64b82<=eae03bd[148];tw25c16<=eae03bd[149];mg2e0b2<=eae03bd[150];of70590<=eae03bd[151];gq82c84<=eae03bd[152];zz16420<=eae03bd[153];bab2106<=eae03bd[154];mt90833<=eae03bd[155];db8419c<=eae03bd[156];zm20ce6<=eae03bd[157];lf6732<=eae03bd[158];qv33997<=eae03bd[159];xy9ccbc<=eae03bd[160];rte65e2<=eae03bd[161];zz32f16<=eae03bd[162];qi978b6<=eae03bd[163];ksbc5b1<=eae03bd[164];gbe2d88<=eae03bd[165];tj16c45<=eae03bd[166];ieb622f<=eae03bd[167];qvb1179<=eae03bd[168];wy88bcc<=eae03bd[169];fn45e61<=eae03bd[170];tw2f30f<=eae03bd[171];rg7987a<=eae03bd[172];ofcc3d3<=eae03bd[173];pf61e9c<=eae03bd[174];gqf4e6<=eae03bd[175];gb7a731<=eae03bd[176];end398d<=eae03bd[177];tw9cc6d<=eae03bd[178];lde636a<=eae03bd[179];aa31b56<=eae03bd[180];co8dab1<=eae03bd[181];yk6d589<=eae03bd[182];kd6ac49<=eae03bd[183];ay5624d<=eae03bd[184];kfb1268<=eae03bd[185];ba89344<=eae03bd[186];me49a22<=eae03bd[187];by4d111<=eae03bd[188];me6888a<=eae03bd[189];of44450<=eae03bd[190];lf22284<=eae03bd[191];ba11426<=eae03bd[192];wl8a133<=eae03bd[193];fn5099d<=eae03bd[194];zz84cee<=eae03bd[195];yz26777<=eae03bd[196];cb33bbc<=eae03bd[197];ou9dde4<=eae03bd[198];vieef20<=eae03bd[199];kq77903<=eae03bd[200];aabc818<=eae03bd[201];hoe40c1<=eae03bd[202];zm2060b<=eae03bd[203];ph305b<=eae03bd[204];wl182df<=eae03bd[205];kqc16fd<=eae03bd[206];dob7e8<=eae03bd[207];ip5bf43<=eae03bd[208];dmdfa1d<=eae03bd[209];qtfd0eb<=eae03bd[210];cze875c<=eae03bd[211];os43ae5<=eae03bd[212];kf1d728<=eae03bd[213];tueb945<=eae03bd[214];ui5ca2b<=eae03bd[215];qge5158<=eae03bd[216];vx28ac1<=eae03bd[217];jp4560e<=eae03bd[218];uk2b076<=eae03bd[219];zk583b0<=eae03bd[220];icc1d83<=eae03bd[221];riec19<=eae03bd[222];lq760ca<=eae03bd[223];phb0653<=eae03bd[224];pu8329e<=eae03bd[225];xl194f3<=eae03bd[226];tuca79f<=eae03bd[227];ea53cfb<=eae03bd[228];vx9e7d9<=eae03bd[229];blf3ece<=eae03bd[230];ir9f676<=eae03bd[231];zkfb3b4<=eae03bd[232];ald9da3<=eae03bd[233];meced1c<=eae03bd[234];xw768e0<=eae03bd[235];cbb4702<=eae03bd[236];oua3814<=eae03bd[237];fp1c0a1<=eae03bd[238];eae050f<=eae03bd[239];cb2879<=eae03bd[240];ri143cc<=eae03bd[241];uxa1e63<= -eae03bd[242];ukf31c<=eae03bd[243];ne798e1<=eae03bd[244];ipcc70b<=eae03bd[245];rg6385c<=eae03bd[246];db1c2e3<=eae03bd[247];pse171f<=eae03bd[248];lsb8fb<=eae03bd[249];os5c7da<=eae03bd[250];ble3ed1<=eae03bd[251];co1f68f<=eae03bd[252];dmfb478<=eae03bd[253];fada3c3<=eae03bd[254];ayd1e1a<=eae03bd[255];kf8f0d0<=eae03bd[256];kq78685<=eae03bd[257];gbc3428<=eae03bd[258];aa1a145<=eae03bd[259];ned0a28<=eae03bd[260];kf85142<=eae03bd[261];fp28a14<=eae03bd[262];ld450a6<=eae03bd[263];nt28536<=eae03bd[264];zk429b7<=eae03bd[265];tw14dba<=eae03bd[266];eca6dd2<=eae03bd[267];cb36e91<=eae03bd[268];pub748c<=eae03bd[269];vxba463<=eae03bd[270];vvd231f<=eae03bd[271];xl918fe<=eae03bd[272];ls8c7f6<=eae03bd[273];ps63fb2<=eae03bd[274];ks1fd93<=eae03bd[275];tufec99<=eae03bd[276];blf64ca<=eae03bd[277];lsb2657<=eae03bd[278];ng932bb<=eae03bd[279];je995da<=eae03bd[280];lqcaed3<=eae03bd[281];ps5769a<=eae03bd[282];anbb4d2<=eae03bd[283];hoda695<=eae03bd[284];shd34aa<=eae03bd[285];yz9a554<=eae03bd[286];zxd2aa4<=eae03bd[287];gd95527<=eae03bd[288];lfaa93d<=eae03bd[289];kd549ef<=eae03bd[290];mta4f7c<=eae03bd[291];lf27be4<=eae03bd[292];hd3df27<=eae03bd[293];kqef93f<=eae03bd[294];by7c9f9<=eae03bd[295];pse4fcb<=eae03bd[296];jr27e5a<=eae03bd[297];pu3f2d7<=eae03bd[298];zxf96bb<=eae03bd[299];uicb5de<=eae03bd[300];pf5aef1<=eae03bd[301];jpd778f<=eae03bd[302];epbbc7e<=eae03bd[303];icde3f4<=eae03bd[304];zkf1fa0<=eae03bd[305];wl8fd03<=eae03bd[306];end -always@* begin shdc077[2047]<=an3c7dd;shdc077[2046]<=fne3eec;shdc077[2044]<=ie1f767;shdc077[2040]<=zkfbb38;shdc077[2032]<=xjdd9c2;shdc077[2030]<=vxb5fa1;shdc077[2028]<=tw8923e;shdc077[2017]<=rtece16;shdc077[2012]<=ym1f209;shdc077[2008]<=kdf2b23;shdc077[2005]<=fc83261;shdc077[1992]<=psd06ae;shdc077[1988]<=uxdb2a;shdc077[1987]<=ay670b6[0];shdc077[1977]<=gd36998;shdc077[1969]<=fpaf81f;shdc077[1962]<=xjd8c37;shdc077[1937]<=mga3d55;shdc077[1928]<=vi42afb;shdc077[1926]<=tj385b0[0];shdc077[1906]<=dmfe504;shdc077[1891]<=pse41ee;shdc077[1877]<=db84238;shdc077[1876]<=ho73e4e;shdc077[1866]<=lsb2b92;shdc077[1842]<=qg77b88;shdc077[1837]<=qtc3827;shdc077[1831]<=cb8510c;shdc077[1826]<=xj5a0d5;shdc077[1809]<=qi8dcd0;shdc077[1805]<=cm6287a;shdc077[1804]<=uk10d0f;shdc077[1803]<=me4c17d;shdc077[1801]<=ksbc8d7;shdc077[1764]<=vx28a0b;shdc077[1761]<=kqce314;shdc077[1748]<=gd3cf5c;shdc077[1746]<=xl1907b;shdc077[1739]<=ofd3065;shdc077[1734]<=ne7c0ff;shdc077[1733]<=ux18596;shdc077[1727]<=fc164c;shdc077[1707]<=vx960d;shdc077[1705]<=xj641e9;shdc077[1696]<=dmc506a;shdc077[1684]<=zm93d75;shdc077[1683]<=gb4e680;shdc077[1681]<=uvd9701;shdc077[1668]<=hoc5259;shdc077[1660]<=oh3c44c;shdc077[1636]<=fn6e49f;shdc077[1633]<=mrc6794;shdc077[1628]<=nt9f2f;shdc077[1627]<=shfd9a1;shdc077[1614]<=co341f5;shdc077[1607]<=xl1638a;shdc077[1604]<=al547aa;shdc077[1587]<=qte84e9;shdc077[1578]<=gb6f0c9;shdc077[1574]<=vid06a9;shdc077[1571]<=ps738fb;shdc077[1567]<=qi1a36b;shdc077[1563]<=oh9068d;shdc077[1562]<=bna0ec7;shdc077[1560]<=mg10847;shdc077[1558]<=me7d10b;shdc077[1555]<=pf5f365;shdc077[1554]<=ipccfc7;shdc077[1550]<=pfe91fc;shdc077[1548]<=yxc6fde;shdc077[1531]<=jp71247;shdc077[1493]<=rt5fa3a;shdc077[1484]<=hb7baa4;shdc077[1481]<=jeb78ae;shdc077[1475]<=nr718a1;shdc077[1474]<=ecaad5;shdc077[1464]<=xy1b38c;shdc077[1460]<=alc3f66;shdc077[1458]<=uide76b;shdc077[1448]<=ld6e606;shdc077[1444]<=jc7312e;shdc077[1431]<=shed630;shdc077[1420]<=an9a9d3;shdc077[1418]<=iraeaf9;shdc077[1417]<=ip4bdc0;shdc077[1411]<=ph848ae;shdc077[1406]<=db8e248;shdc077[1397]<=cb8011e;shdc077[1395]<=al4b55d;shdc077[1388]<=kdc379d;shdc077[1378]<=ps79fd0;shdc077[1373]<=fc2fa21;shdc077[1371]<=ana12fe;shdc077[1366]<=jc760c3;shdc077[1362]<=lf9e52c;shdc077[1354]<=yxfd23f;shdc077[1345]<=twbd919;shdc077[1334]<=medbb14;shdc077[1323]<=gd9f8df;shdc077[1321]<=zx40318;shdc077[1320]<=hd94841;shdc077[1318]<=xj50641;shdc077[1314]<=kf90665;shdc077[1300]<=nga760e;shdc077[1288]<=kq59545;shdc077[1287]<=zzceee;shdc077[1273]<=su67c62;shdc077[1257]<=lq6cbbf;shdc077[1253]<=anae5af;shdc077[1242]<=fa69a9c;shdc077[1240]<=vie15c8;shdc077[1234]<=fafea05;shdc077[1231]<=aaa6dde;shdc077[1224]<=uk8875a;shdc077[1219]<=uv4b659;shdc077[1218]<=cz651af;shdc077[1208]<=yxc6172;shdc077[1206]<=dzd8704;shdc077[1198]<=vv4f023;shdc077[1196]<=vv6bbcf;shdc077[1190]<=tw3f9da;shdc077[1186]<=wj7532a;shdc077[1180]<=cm4c960;shdc077[1177]<=ay5c741;shdc077[1167]<=ym21624;shdc077[1161]<=do3f356;shdc077[1160]<=ofd6c5e;shdc077[1150]<=rg63e74;shdc077[1131]<=pub2248;shdc077[1126]<=nt3fd1;shdc077[1112]<=uv5e284;shdc077[1109]<=dobd9a4;shdc077[1106]<=ana1e10;shdc077[1101]<=xya8150;shdc077[1100]<=db2d4da;shdc077[1094]<=qv9f0d5;shdc077[1093]<=mg34ebd;shdc077[1086]<=lsa8a57;shdc077[1076]<=mg21689;shdc077[1072]<=su4cd40;shdc077[1069]<=fcb121;shdc077[1063]<=kd54432;shdc077[1061]<=ng86878;shdc077[1056]<=phbad72;shdc077[1055]<=kq6dea3;shdc077[1052]<=blfced2;shdc077[1048]<=xybd739;shdc077[1028]<=yx54574;shdc077[1023]<=uve78fb[0];shdc077[1015]<=qtfd7fa;shdc077[1014]<=zz32c7f;shdc077[1002]<=su6205e;shdc077[996]<=dm6cf8c;shdc077[994]<=ir857bb;shdc077[938]<=bld7356;shdc077[933]<=gbf27ae;shdc077[921]<=mgb992f;shdc077[918]<=bn1c13c;shdc077[915]<=mre7cae;shdc077[902]<=do8c50f;shdc077[901]<=qg7864c;shdc077[900]<=fad51e7;shdc077[880]<=qtd9c62;shdc077[874]<=eaea018;shdc077[873]<=wy98973;shdc077[869]<=thf3b58;shdc077[866]<=lf37e37;shdc077[863]<=med1c49;shdc077[848]<=pu997a9;shdc077[841]<=pu8320f;shdc077[840]<=ie3b2e0;shdc077[834]<=yk773c5;shdc077[830]<=ie3e311;shdc077[816]<=anbee41;shdc077[814]<=pf6b185;shdc077[803]<=wy559d;shdc077[793]<=cme07fa;shdc077[789]<=ec10c6f;shdc077[787]<=sufa0d5;shdc077[783]<=ba139a;shdc077[781]<=cb3c91c;shdc077[777]<=lqee0f9;shdc077[775]<=twb7f1d;shdc077[774]<=anaee78;shdc077[765]<=bn13340;shdc077[746]<=fnc7d4e;shdc077[742]<=qg53cd7;shdc077[737]<=xjf30e3;shdc077[732]<=ep23671;shdc077[730]<=goc4b98;shdc077[729]<=fn74e8d;shdc077[708]<=xwcfe83;shdc077[705]<=wy98918;shdc077[698]<=ldf336a;shdc077[697]<=yxc3544;shdc077[694]<=mt186f3;shdc077[689]<=eca69e9;shdc077[686]<=uvc982f;shdc077[685]<=zzb061b;shdc077[677]<=rt5fa47;shdc077[667]<=off2943;shdc077[661]<=ld5f8b9;shdc077[660]<=lf3d99f;shdc077[650]<=nta035d;shdc077[643]<=ipf79c5;shdc077[628]<=os774cd;shdc077[626]<=wl23d30;shdc077[621]<=iebc062;shdc077[620]<=vi764fd;shdc077[617]<=dmf42ab;shdc077[615]<=jpe9ea6;shdc077[609]<=sue0cf8;shdc077[599]<=mef5856;shdc077[598]<=xl13484;shdc077[595]<=ay772e2;shdc077[593]<=hd9ebab;shdc077[588]<=yma9cd0;shdc077[580]<=ld5a793;shdc077[575]<=uk34943;shdc077[565]<=rib75b1;shdc077[556]<=wwd125e;shdc077[553]<=gd8e31;shdc077[550]<=xjc7e6a;shdc077[546]<=mg242d1;shdc077[528]<=hb452ba;shdc077[527]<=tuc0cca;shdc077[514]<=mt8a8ae;shdc077[507]<=xjc7184;shdc077[501]<=fce507;shdc077[498]<=do83573;shdc077[497]<=hd378a0;shdc077[466]<=xj4f8b2;shdc077[459]<=yk72b5b;shdc077[450]<=pu86378;shdc077[437]<=fp942e5;shdc077[433]<=dzc8610;shdc077[431]<=uk1f410;shdc077[420]<=iea6de0;shdc077[417]<=uk24577;shdc077[415]<=wl36ef1;shdc077[408]<=vxa59a6;shdc077[401]<=co1ac37;shdc077[391]<=vx37459;shdc077[390]<=aycb870;shdc077[388]<=ng1100c;shdc077[387]<=gb65dfa;shdc077[368]<=pu30b95;shdc077[366]<=ou246ce;shdc077[365]<=aa1fb34;shdc077[352]<=ph9952;shdc077[348]<=ay53911;shdc077[344]<=lq5de7f;shdc077[343]<=sj8e0d;shdc077[333]<=psda5e1;shdc077[330]<=mre2814;shdc077[325]<=uif5d5f;shdc077[314]<=xjcd977;shdc077[313]<=mg34010;shdc077[310]<=ou2b17f;shdc077[308]<=do47a1;shdc077[307]<=ayf539a;shdc077[304]<=lqd52d9;shdc077[299]<=ks5aef;shdc077[287]<=me675cd;shdc077[282]<=ld454ea;shdc077[278]<=jpcd4c1;shdc077[275]<=jcca8f5;shdc077[273]<=osc485a;shdc077[257]<=vv71515;shdc077[253]<=jpe9cf9;shdc077[250]<=nrf9e15;shdc077[248]<=kqde7bd;shdc077[225]<=cm43086;shdc077[215]<=rie809;shdc077[208]<=rgf1424;shdc077[204]<=rt6be72;shdc077[195]<=kd4b2a8;shdc077[193]<=swa6d19;shdc077[183]<=dz648d9;shdc077[176]<=ps52ebf;shdc077[171]<=al5e34f;shdc077[165]<=ou8d7e9;shdc077[157]<=hdaa0f5;shdc077[155]<=jra562f;shdc077[154]<=by58fcd;shdc077[152]<=wy1aa5b;shdc077[149]<=rt40b5d;shdc077[141]<=nt8bd4c;shdc077[139]<=bna0256;shdc077[128]<=yx4e2a2;shdc077[125]<=ho575ae;shdc077[124]<=ne4d871;shdc077[112]<=gqae43;shdc077[104]<=hq892f1;shdc077[97]<=ay78a4b;shdc077[96]<=ay491f2;shdc077[91]<=me4c91b;shdc077[78]<=fnf9b2e;shdc077[77]<=hb74ac5;shdc077[74]<= -ls960a9;shdc077[64]<=ui72d7c;shdc077[62]<=ks24221;shdc077[56]<=fnd2f0a;shdc077[48]<=aa1fe8e;shdc077[38]<=epae958;shdc077[19]<=wy15d2b;shdc077[9]<=xya2ba5;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[1]};ohb4114<=eae03bd[2];jra08a4<={an8c7c>>1,eae03bd[3]};ls4526<=eae03bd[4];nt22932<=eae03bd[5];vk14997<={mrc99c0>>1,eae03bd[6]};wla4cba<={ay4ce05>>1,eae03bd[7]};mt265d4<={ic67029>>1,eae03bd[8]};lf32ea4<={fp38148>>1,eae03bd[9]};ie97526<={rgc0a46>>1,eae03bd[10]};xlba930<={ks5233>>1,eae03bd[11]};ead4986<=eae03bd[12];qva4c30<=eae03bd[13];qv26184<=eae03bd[14];pu30c24<=eae03bd[15];tw86123<={co98acd>>1,eae03bd[16]};ba3091b<=eae03bd[17];nt848db<=eae03bd[18];ec246df<={ea59a10>>1,eae03bd[19]};cb236f9<=eae03bd[20];hq1b7cc<=eae03bd[21];qgdbe62<={xw42031>>1,eae03bd[22]};psdf311<=eae03bd[23];fnf988a<=eae03bd[24];wjcc457<=eae03bd[25];yk622bc<=eae03bd[26];ba115e0<=eae03bd[27];wl8af03<={su59bc7>>1,eae03bd[28]};zk5781c<=eae03bd[29];ecbc0e3<=eae03bd[30];ice0718<=eae03bd[31];jr38c1<=eae03bd[32];xl1c60e<=eae03bd[33];vve3077<=eae03bd[34];ep183be<=eae03bd[35];wwc1df5<=eae03bd[36];zmefa9<=eae03bd[37];ww77d4a<={gb7fd10>>1,eae03bd[38]};uxbea50<=eae03bd[39];gof5284<=eae03bd[40];uka9420<=eae03bd[41];fn4a101<=eae03bd[42];zx5080f<=eae03bd[43];db8407e<=eae03bd[44];zm203f6<=eae03bd[45];ng1fb3<=eae03bd[46];ecfd9b<=eae03bd[47];end -always@* begin shdc077[2047]<=ph28231[0];shdc077[2046]<=force_isolate;shdc077[2044]<=an8c7c[0];shdc077[2041]<=ic463e5;shdc077[2034]<=qi31f29;shdc077[2021]<=mrc99c0[0];shdc077[2017]<=qg68406;shdc077[1995]<=ay4ce05[0];shdc077[1986]<=xw42031[0];shdc077[1943]<=ic67029[0];shdc077[1925]<=gq1018b;shdc077[1908]<=vx38f0f;shdc077[1864]<=aaffa2;shdc077[1855]<=co98acd[0];shdc077[1838]<=fp38148[0];shdc077[1803]<=kf80c59;shdc077[1769]<=vvc787f;shdc077[1680]<=gb7fd10[0];shdc077[1662]<=dmc5668;shdc077[1628]<=rgc0a46[0];shdc077[1559]<=jr62cd;shdc077[1501]<=go78e3c;shdc077[1490]<=oh3c3fe;shdc077[1487]<=ww4662b;shdc077[1312]<=zkfe884;shdc077[1276]<=ym2b342;shdc077[1209]<=ks5233[0];shdc077[1155]<=lsa2112;shdc077[1070]<=ym3166f;shdc077[1048]<=nt22486;shdc077[1023]<=gbe_mode;shdc077[1008]<=vvcd080;shdc077[954]<=fnc71e1;shdc077[932]<=lqe1ff4;shdc077[927]<=an33159;shdc077[750]<=ip6f1c7;shdc077[743]<=fa48cc5;shdc077[577]<=vif4422;shdc077[524]<=lf84490;shdc077[504]<=ea59a10[0];shdc077[375]<=dzcde38;shdc077[371]<=ep29198;shdc077[262]<=aa10892;shdc077[197]<=ep90da0;shdc077[187]<=su59bc7[0];shdc077[98]<=wy921b4;shdc077[93]<=lf8b378;shdc077[49]<=sj12436;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[2]};ls4526<=eae03bd[3];nt22932<=eae03bd[4];jp553cf<=eae03bd[5];gqa9e7f<=eae03bd[6];th4f3f8<={ayead3e>>1,eae03bd[7]};vk14997<={mrc99c0>>1,eae03bd[8]};wla4cba<={ay4ce05>>1,eae03bd[9]};mt265d4<={ic67029>>1,eae03bd[10]};lf32ea4<={fp38148>>1,eae03bd[11]};ie97526<={rgc0a46>>1,eae03bd[12]};xlba930<={ks5233>>1,eae03bd[13]};ead4986<=eae03bd[14];qva4c30<=eae03bd[15];qv26184<=eae03bd[16];pu30c24<=eae03bd[17];ice0718<=eae03bd[18];jr38c1<=eae03bd[19];rt5a511<=eae03bd[20];zmefa9<=eae03bd[21];ww77d4a<={gb7fd10>>1,eae03bd[22]};uxbea50<=eae03bd[23];do11dfa<=eae03bd[24];jr8efd2<=eae03bd[25];ecbc0e3<=eae03bd[26];tw86123<={co98acd>>1,eae03bd[27]};nt848db<=eae03bd[28];ba3091b<=eae03bd[29];ri961cf<=eae03bd[30];rvb0e7a<=eae03bd[31];wl8af03<={su59bc7>>1,eae03bd[32]};ba115e0<=eae03bd[33];yk622bc<=eae03bd[34];wj7ae6b<=eae03bd[35];zxd735c<=eae03bd[36];aab9ae6<={pu2fa51>>1,eae03bd[37]};jpcd731<=eae03bd[38];bl6b98e<=eae03bd[39];go5cc77<=eae03bd[40];lde63b8<=eae03bd[41];wwc1df5<=eae03bd[42];vve3077<=eae03bd[43];su7718e<=eae03bd[44];gof5284<=eae03bd[45];uka9420<=eae03bd[46];fn4a101<=eae03bd[47];zx5080f<=eae03bd[48];db8407e<=eae03bd[49];zm203f6<=eae03bd[50];ng1fb3<=eae03bd[51];ecfd9b<=eae03bd[52];end -always@* begin shdc077[2047]<=force_isolate;shdc077[2046]<=an8c7c[0];shdc077[2044]<=ic463e5;shdc077[2040]<=qi31f29;shdc077[2032]<=qva4f56;shdc077[2017]<=rv27ab4;shdc077[1987]<=ayead3e[0];shdc077[1926]<=mrc99c0[0];shdc077[1805]<=ba20be9;shdc077[1804]<=ay4ce05[0];shdc077[1803]<=zkfe884;shdc077[1761]<=su59bc7[0];shdc077[1668]<=lqe1ff4;shdc077[1562]<=ym5f4a;shdc077[1560]<=ic67029[0];shdc077[1558]<=ng837ab;shdc077[1550]<=ww4662b;shdc077[1475]<=lf8b378;shdc077[1464]<=medb224;shdc077[1288]<=vvc787f;shdc077[1076]<=pu2fa51[0];shdc077[1072]<=fp38148[0];shdc077[1069]<=fc1bd5b;shdc077[1056]<=vif4422;shdc077[1052]<=an33159;shdc077[1028]<=sj12436;shdc077[1023]<=gbe_mode;shdc077[902]<=ym3166f;shdc077[901]<=gb7fd10[0];shdc077[880]<=gbd9120;shdc077[834]<=sh5163f;shdc077[775]<=fa48cc5;shdc077[732]<=dmc5668;shdc077[528]<=thc7f7a;shdc077[514]<=nt22486;shdc077[450]<=aaffa2;shdc077[417]<=bl4a2c7;shdc077[387]<=ep29198;shdc077[366]<=ym2b342;shdc077[257]<=lf84490;shdc077[225]<=tw35e83;shdc077[208]<=nre9458;shdc077[193]<=ks5233[0];shdc077[183]<=co98acd[0];shdc077[128]<=aa10892;shdc077[112]<=fnc71e1;shdc077[104]<=os7d28b;shdc077[96]<=rgc0a46[0];shdc077[91]<=ip6f1c7;shdc077[64]<=lsa2112;shdc077[56]<=go78e3c;shdc077[19]<=ep90da0;shdc077[9]<=wy921b4;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[3]};ls4526<=eae03bd[4];nt22932<=eae03bd[5];vk25af2<={gb5e68a>>1,eae03bd[6]};vk14997<={mrc99c0>>1,eae03bd[7]};wla4cba<={ay4ce05>>1,eae03bd[8]};mt265d4<={ic67029>>1,eae03bd[9]};lf32ea4<={fp38148>>1,eae03bd[10]};ie97526<={rgc0a46>>1,eae03bd[11]};xlba930<={ks5233>>1,eae03bd[12]};ead4986<=eae03bd[13];qva4c30<=eae03bd[14];qv26184<=eae03bd[15];pu30c24<=eae03bd[16];ww77d4a<={gb7fd10>>1,eae03bd[17]};uxbea50<=eae03bd[18];do11dfa<=eae03bd[19];ecbc0e3<=eae03bd[20];tw86123<={co98acd>>1,eae03bd[21]};nt848db<=eae03bd[22];ba3091b<=eae03bd[23];gof5284<=eae03bd[24];uka9420<=eae03bd[25];fn4a101<=eae03bd[26];zx5080f<=eae03bd[27];db8407e<=eae03bd[28];zm203f6<=eae03bd[29];ng1fb3<=eae03bd[30];ecfd9b<=eae03bd[31];end -always@* begin shdc077[2047]<=fa47021;shdc077[2046]<=force_isolate;shdc077[2044]<=an8c7c[0];shdc077[2041]<=ic463e5;shdc077[2035]<=qi31f29;shdc077[2022]<=gb5e68a[0];shdc077[1996]<=mrc99c0[0];shdc077[1945]<=ay4ce05[0];shdc077[1922]<=lsa2112;shdc077[1842]<=ic67029[0];shdc077[1797]<=aa10892;shdc077[1776]<=ym2b342;shdc077[1637]<=fp38148[0];shdc077[1622]<=fa48cc5;shdc077[1546]<=lf84490;shdc077[1504]<=dmc5668;shdc077[1468]<=ip6f1c7;shdc077[1391]<=zkfe884;shdc077[1226]<=rgc0a46[0];shdc077[1197]<=ww4662b;shdc077[1044]<=nt22486;shdc077[1023]<=gbe_mode;shdc077[961]<=vif4422;shdc077[888]<=co98acd[0];shdc077[811]<=ep29198;shdc077[734]<=ng837ab;shdc077[695]<=gb7fd10[0];shdc077[405]<=ks5233[0];shdc077[347]<=an33159;shdc077[164]<=ep90da0;shdc077[82]<=wy921b4;shdc077[41]<=sj12436;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[3]};ls4526<=eae03bd[4];nt22932<=eae03bd[5];jp553cf<=eae03bd[6];gqa9e7f<=eae03bd[7];vk25af2<={gb5e68a>>1,eae03bd[8]};vk14997<={mrc99c0>>1,eae03bd[9]};wla4cba<={ay4ce05>>1,eae03bd[10]};mt265d4<={ic67029>>1,eae03bd[11]};lf32ea4<={fp38148>>1,eae03bd[12]};ie97526<={rgc0a46>>1,eae03bd[13]};xlba930<={ks5233>>1,eae03bd[14]};ead4986<=eae03bd[15];qva4c30<=eae03bd[16];qv26184<=eae03bd[17];pu30c24<=eae03bd[18];ww77d4a<={gb7fd10>>1,eae03bd[19]};uxbea50<=eae03bd[20];do11dfa<=eae03bd[21];ecbc0e3<=eae03bd[22];tw86123<={co98acd>>1,eae03bd[23]};nt848db<=eae03bd[24];ba3091b<=eae03bd[25];ri961cf<=eae03bd[26];rvb0e7a<=eae03bd[27];gof5284<=eae03bd[28];uka9420<=eae03bd[29];fn4a101<=eae03bd[30];zx5080f<=eae03bd[31];db8407e<=eae03bd[32];zm203f6<=eae03bd[33];ng1fb3<=eae03bd[34];ecfd9b<=eae03bd[35];end -always@* begin shdc077[2047]<=force_isolate;shdc077[2046]<=fa47021;shdc077[2044]<=an8c7c[0];shdc077[2040]<=ic463e5;shdc077[2033]<=qi31f29;shdc077[2019]<=qva4f56;shdc077[1999]<=ep90da0;shdc077[1991]<=rv27ab4;shdc077[1934]<=gb5e68a[0];shdc077[1892]<=zkfe884;shdc077[1851]<=ep29198;shdc077[1820]<=mrc99c0[0];shdc077[1737]<=ng837ab;shdc077[1654]<=fa48cc5;shdc077[1610]<=ym2b342;shdc077[1593]<=ay4ce05[0];shdc077[1523]<=sj12436;shdc077[1426]<=ip6f1c7;shdc077[1404]<=lf84490;shdc077[1260]<=ww4662b;shdc077[1199]<=vif4422;shdc077[1173]<=dmc5668;shdc077[1139]<=ic67029[0];shdc077[1023]<=gbe_mode;shdc077[999]<=wy921b4;shdc077[946]<=gb7fd10[0];shdc077[925]<=ks5233[0];shdc077[805]<=co98acd[0];shdc077[761]<=nt22486;shdc077[702]<=aa10892;shdc077[599]<=gbd9120;shdc077[473]<=an33159;shdc077[462]<=rgc0a46[0];shdc077[351]<=lsa2112;shdc077[299]<=medb224;shdc077[231]<=fp38148[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[6]};tu795c3<=eae03bd[7];zkcae1a<=eae03bd[8];xw570d2<=eae03bd[9];lsb8692<=eae03bd[10];ofc3492<=eae03bd[11];mg1a495<={cb850a4>>1,eae03bd[12]};hbd24a8<={tj28524>>1,eae03bd[13]};mg92546<={vi42927>>1,eae03bd[14]};aa92a30<={ng1493a>>1,eae03bd[15]};oh95181<={kfa49d2>>1,eae03bd[16]};vka8c0d<=eae03bd[17];go4606a<=eae03bd[18];ba30351<=eae03bd[19];jr81a8a<=eae03bd[20];and457<=eae03bd[21];gb6a2bc<=eae03bd[22];sh515e4<={gb7a77f>>1,eae03bd[23]};cb8af25<=eae03bd[24];vi5792c<={sw9dfed>>1,eae03bd[25]};ymbc963<=eae03bd[26];rge4b19<={al7fb41>>1,eae03bd[27]};xy258ca<={enfda0c>>1,eae03bd[28]};ux2c652<={ofed065>>1,eae03bd[29]};dm63295<={wj41969>>1,eae03bd[30]};rv194aa<={bncb4d>>1,eae03bd[31]};xwca557<={sh65a6f>>1,eae03bd[32]};lq52abb<={hd2d37c>>1,eae03bd[33]};yz955db<={dm69be7>>1,eae03bd[34]};zzaaedd<={tu4df3a>>1,eae03bd[35]};rg576ef<=eae03bd[36];qvbb77a<=eae03bd[37];eadbbd5<=eae03bd[38];zxddea9<=eae03bd[39];eaef54e<=eae03bd[40];cz7aa70<=eae03bd[41];tud5384<=eae03bd[42];iea9c23<=eae03bd[43];ip4e118<=eae03bd[44];wj708c5<=eae03bd[45];zz8462d<=eae03bd[46];ux2316e<=eae03bd[47];wl18b74<=eae03bd[48];hoc5ba4<={suefa11>>1,eae03bd[49]};lf2dd23<=eae03bd[50];hb6e91e<=eae03bd[51];fn748f7<=eae03bd[52];sja47bf<=eae03bd[53];kf23dfd<=eae03bd[54];xy1efed<={rg48ada>>1,eae03bd[55]};uvf7f6b<=eae03bd[56];fpbfb5c<=eae03bd[57];shfdae6<=eae03bd[58];wjed735<=eae03bd[59];vv6b9ad<={wjd3c22>>1,eae03bd[60]};kq5cd6f<=eae03bd[61];rte6b78<=eae03bd[62];ba35bc7<=eae03bd[63];lsade3b<=eae03bd[64];gb6f1da<=eae03bd[65];qg78ed4<={qvae3b8>>1,eae03bd[66]};hbc76a1<=eae03bd[67];ie3b50f<=eae03bd[68];tuda879<=eae03bd[69];med43cb<={fcb89f1>>1,eae03bd[70]};end -always@* begin shdc077[2047]<=sgmii_mode;shdc077[2046]<=force_unidir;shdc077[2044]<=mr_main_reset;shdc077[2040]<=mr_restart_an;shdc077[2032]<=mr_an_enable;shdc077[2016]<=mr_adv_ability[1];shdc077[2014]<=fcb89f1[1];shdc077[1985]<=fp9ed2a;shdc077[1927]<=gof08ae;shdc077[1922]<=lfa55f5;shdc077[1867]<=ri1427a;shdc077[1807]<=bn84571;shdc077[1804]<=hocfbe8;shdc077[1797]<=fc2afaf;shdc077[1761]<=zxe967d;shdc077[1686]<=uxa13d3;shdc077[1623]<=vk8915b;shdc077[1567]<=lf22b8e;shdc077[1561]<=ic7df42;shdc077[1558]<=enfda0c[0];shdc077[1547]<=ne57d7b;shdc077[1542]<=vi7ce9d;shdc077[1505]<=wjd3c22[1];shdc077[1490]<=sw24e94;shdc077[1475]<=sh4b3ef;shdc077[1413]<=ayeff68;shdc077[1409]<=dm69be7[0];shdc077[1400]<=sh5b4f0;shdc077[1324]<=bn9e9d;shdc077[1200]<=gb7a77f[0];shdc077[1199]<=rg48ada[0];shdc077[1086]<=ec15c77;shdc077[1074]<=suefa11[1];shdc077[1068]<=ofed065[0];shdc077[1047]<=ohbebdb;shdc077[1037]<=vk3a75c;shdc077[1023]<=gbe_mode;shdc077[1007]<=kq7713e;shdc077[963]<=jr9e115;shdc077[933]<=ps4284f;shdc077[902]<=ww59f7d;shdc077[880]<=ep1d2cf;shdc077[811]<=ba1122b;shdc077[779]<=al7fb41[0];shdc077[771]<=tu4df3a[0];shdc077[752]<=byda784;shdc077[745]<=kfa49d2[0];shdc077[706]<=sw9dfed[0];shdc077[704]<=hd2d37c[0];shdc077[700]<=gq2b69e;shdc077[600]<=th4f4ef;shdc077[503]<=rv8ee27;shdc077[440]<=ble3a59;shdc077[405]<=tu42245;shdc077[372]<=ng1493a[0];shdc077[353]<=end3bfd;shdc077[352]<=sh65a6f[0];shdc077[350]<=rt456d3;shdc077[251]<=vv71dc4;shdc077[220]<=os5c74b;shdc077[202]<=wje8448;shdc077[186]<=vi42927[0];shdc077[176]<=bncb4d[0];shdc077[125]<=qvae3b8[0];shdc077[110]<=pseb8e9;shdc077[101]<=me7d089;shdc077[93]<=tj28524[0];shdc077[88]<=wj41969[0];shdc077[55]<=qi9d71d;shdc077[46]<=cb850a4[0];shdc077[27]<=uvd3ae3;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[4]};wje70fc<=eae03bd[5];nt387e4<=eae03bd[6];zkcae1a<=eae03bd[7];gq1f934<=eae03bd[8];pffc9a1<={bl7b70e>>1,eae03bd[9]};xwe4d0f<=eae03bd[10];ux2687a<=eae03bd[11];ym343d5<=eae03bd[12];kfa1ea8<={mg249fa>>1,eae03bd[13]};swf544<={ie24fd0>>1,eae03bd[14]};yx7aa21<={fp27e80>>1,eae03bd[15]};ned510c<={je3f407>>1,eae03bd[16]};nga8863<={ayfa03b>>1,eae03bd[17]};wj4431a<=eae03bd[18];uk218d4<=eae03bd[19];xlc6a0<=eae03bd[20];ho63506<=eae03bd[21];uk1a832<=eae03bd[22];uid4191<=eae03bd[23];tja0c89<=eae03bd[24];ph644e<=eae03bd[25];xl32277<=eae03bd[26];hd913bf<=eae03bd[27];ri89dff<=eae03bd[28];qt4effb<=eae03bd[29];cm77fdc<=eae03bd[30];rvbfee0<=eae03bd[31];icff706<=eae03bd[32];tufb831<=eae03bd[33];aldc18a<=eae03bd[34];qge0c55<=eae03bd[35];rv62a8<=eae03bd[36];ks31547<=eae03bd[37];cb8aa38<=eae03bd[38];xj551c4<=eae03bd[39];pua8e27<=eae03bd[40];lq4713a<=eae03bd[41];rv389d3<={lf382f0>>1,eae03bd[42]};mec4e9f<={mec1786>>1,eae03bd[43]};zz274f9<=eae03bd[44];je3a7ce<=eae03bd[45];czd3e73<=eae03bd[46];ep9f39d<=eae03bd[47];vvf9cec<=eae03bd[48];suce767<=eae03bd[49];xw73b39<=eae03bd[50];aa9d9ca<=eae03bd[51];pfece50<=eae03bd[52];kq67286<=eae03bd[53];ux39430<=eae03bd[54];hoca184<=eae03bd[55];pf50c23<=eae03bd[56];zm8611e<=eae03bd[57];xy308f3<={ip5e6ab>>1,eae03bd[58]};hd8479b<={blf355c>>1,eae03bd[59]};hbc76a1<=eae03bd[60];ie3b50f<=eae03bd[61];vvf37aa<=eae03bd[62];rv9bd57<=eae03bd[63];wwdeabf<=eae03bd[64];kqf55f9<=eae03bd[65];gof5284<=eae03bd[66];uka9420<=eae03bd[67];rvbf23b<={ipe8b9b>>1,eae03bd[68]};end -always@* begin shdc077[2047]<=sgmii_mode;shdc077[2046]<=gbe_mode;shdc077[2044]<=zzbf298;shdc077[2041]<=hb5a0eb;shdc077[2040]<=rx_data[0];shdc077[2035]<=rgd075e;shdc077[2033]<=rx_kcntl;shdc077[2024]<=ie3b2ed;shdc077[2022]<=tw83af3;shdc077[2018]<=su531f3;shdc077[2001]<=uvd9769;shdc077[1997]<=yz1d79a;shdc077[1988]<=lfa55f5;shdc077[1954]<=uicbb4d;shdc077[1946]<=byebcd5;shdc077[1929]<=rx_even;shdc077[1874]<=kd51cbd;shdc077[1860]<=jc5da68;shdc077[1851]<=ipe8b9b[1];shdc077[1845]<=ip5e6ab[0];shdc077[1811]<=bl7b70e[0];shdc077[1789]<=hod01d9;shdc077[1721]<=kq5cf5d;shdc077[1700]<=nt8e5ec;shdc077[1673]<=iped342;shdc077[1643]<=blf355c[0];shdc077[1574]<=sudbf39;shdc077[1530]<=sj80ecb;shdc077[1486]<=vif4422;shdc077[1395]<=qte7ae8;shdc077[1353]<=ic72f67;shdc077[1317]<=pubd9c1;shdc077[1311]<=tw860a1;shdc077[1299]<=lq69a15;shdc077[1258]<=lq5228e;shdc077[1247]<=fp27e80[0];shdc077[1239]<=vv71dc4;shdc077[1187]<=twbc30;shdc077[1172]<=me6705e;shdc077[1151]<=gq8285a;shdc077[1102]<=su68552;shdc077[1101]<=fadf9c9;shdc077[1023]<=mr_main_reset;shdc077[1020]<=twb41d;shdc077[1012]<=ux765d;shdc077[937]<=an8a397;shdc077[925]<=lsa2112;shdc077[894]<=ayfa03b[0];shdc077[860]<=irab9eb;shdc077[743]<=vx3d745;shdc077[658]<=ks97b38;shdc077[655]<=cmf0c14;shdc077[629]<=phaa451;shdc077[623]<=ie24fd0[0];shdc077[593]<=mec1786[0];shdc077[586]<=zxece0b;shdc077[575]<=ba3050b;shdc077[551]<=fa4d0aa;shdc077[510]<=qva1683;shdc077[468]<=vx91472;shdc077[447]<=je3f407[0];shdc077[430]<=rv8ee27;shdc077[327]<=cz5e182;shdc077[314]<=aa1548a;shdc077[311]<=mg249fa[0];shdc077[296]<=lf382f0[0];shdc077[255]<=xy142d0;shdc077[157]<=ne42a91;shdc077[155]<=gbc97e4;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[2]};wje70fc<=eae03bd[3];nt387e4<=eae03bd[4];mefa1aa<={ldddfe4>>1,eae03bd[5]};zkd0d51<={wweff26>>1,eae03bd[6]};ba86a8a<={uv7f931>>1,eae03bd[7]};je35452<=eae03bd[8];vxaa292<=eae03bd[9];hbc76a1<=eae03bd[10];ie3b50f<=eae03bd[11];jc525ad<=eae03bd[12];co92d6a<=eae03bd[13];do96b51<=eae03bd[14];ntb5a8b<=eae03bd[15];doad45f<=eae03bd[16];yx6a2fb<=eae03bd[17];gb517dc<=eae03bd[18];lf8bee5<={pfc235b>>1,eae03bd[19]};end -always@* begin shdc077[2047]<=signal_detect;shdc077[2046]<=rx_data[0];shdc077[2044]<=rx_kcntl;shdc077[2040]<=su531f3;shdc077[2032]<=ldddfe4[0];shdc077[2017]<=wweff26[0];shdc077[1987]<=uv7f931[0];shdc077[1927]<=jpfc98c;shdc077[1865]<=cba1611;shdc077[1806]<=bye4c67;shdc077[1682]<=lsb08d;shdc077[1565]<=vv71dc4;shdc077[1317]<=tu5846b;shdc077[1082]<=rv8ee27;shdc077[1023]<=mr_main_reset;shdc077[932]<=sud42c2;shdc077[586]<=pfc235b[1];shdc077[466]<=pu3a858;shdc077[233]<=qg6750b;shdc077[116]<=ba8cea1;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[4]};cm43cd0<={ykcb59e>>1,eae03bd[5]};ri1e680<=eae03bd[6];vvf3402<=eae03bd[7];qv9a017<={xl27f82>>1,eae03bd[8]};lqd00bc<={ald3027>>1,eae03bd[9]};yz805e3<={ie9813c>>1,eae03bd[10]};mt2f1c<=eae03bd[11];ux178e4<=eae03bd[12];qibc725<={fp2785b>>1,eae03bd[13]};dze3928<=eae03bd[14];vx1c947<=eae03bd[15];zke4a3e<={jeb7e3>>1,eae03bd[16]};je251f2<=eae03bd[17];rv28f93<=eae03bd[18];by47c9e<=eae03bd[19];ie3e4f2<=eae03bd[20];uvf2791<=eae03bd[21];hq93c8d<=eae03bd[22];tj9e46b<=eae03bd[23];kdf235e<=eae03bd[24];hd91af5<=eae03bd[25];ecbc0e3<=eae03bd[26];wl8af03<={su59bc7>>1,eae03bd[27]};sh5eb87<=eae03bd[28];yk622bc<=eae03bd[29];kfae1e9<=eae03bd[30];yx70f4c<=eae03bd[31];mg87a65<=eae03bd[32];vx3d328<=eae03bd[33];zk5781c<=eae03bd[34];ay4ca36<=eae03bd[35];kd651b1<=eae03bd[36];zz28d8d<=eae03bd[37];me46c6e<=eae03bd[38];ux36370<=eae03bd[39];irb1b85<=eae03bd[40];ou8dc2d<=eae03bd[41];th6e169<={zm30db3>>1,eae03bd[42]};wla4cba<={ay4ce05>>1,eae03bd[43]};mt265d4<={ic67029>>1,eae03bd[44]};vx2d3ad<={gqb66d4>>1,eae03bd[45]};lq69d6f<={ymb36a1>>1,eae03bd[46]};gb4eb7a<=eae03bd[47];cz75bd4<=eae03bd[48];twadea5<=eae03bd[49];sh6f52a<=eae03bd[50];ead4986<=eae03bd[51];ead4aa4<=eae03bd[52];rva5520<=eae03bd[53];ba2a907<=eae03bd[54];ip5483b<=eae03bd[55];wla41dc<=eae03bd[56];pu20ee5<=eae03bd[57];ir772a<={hoeb5e8>>1,eae03bd[58]};qi3b955<={bl5af42>>1,eae03bd[59]};gof5284<=eae03bd[60];uka9420<=eae03bd[61];ls2aa21<={qte85fa>>1,eae03bd[62]};ld5510b<={xw42fd5>>1,eae03bd[63]};xya885f<=eae03bd[64];yx442fa<=eae03bd[65];ks217d4<=eae03bd[66];xybea1<=eae03bd[67];jp5f50a<=eae03bd[68];gofa856<=eae03bd[69];ykd42b0<=eae03bd[70];yza1581<=eae03bd[71];ecac0d<=eae03bd[72];kq56068<=eae03bd[73];ntb0340<=eae03bd[74];bn81a06<=eae03bd[75];ohd037<={co215fe>>1,eae03bd[76]};me681bc<={ksaff1>>1,eae03bd[77]};end -always@* begin shdc077[2047]<=an_link_ok;shdc077[2046]<=tu58fcb;shdc077[2044]<=gbe_mode;shdc077[2040]<=operational_rate[0];shdc077[2033]<=ykcb59e[0];shdc077[2019]<=vv5acf1;shdc077[1991]<=end678f;shdc077[1934]<=xl27f82[0];shdc077[1929]<=ph9b509;shdc077[1898]<=fae16fc;shdc077[1821]<=ald3027[0];shdc077[1813]<=zzb0857;shdc077[1810]<=dmda84e;shdc077[1749]<=jeb7e3[0];shdc077[1707]<=vvfc6eb;shdc077[1666]<=ui788b0;shdc077[1630]<=nr50c36;shdc077[1617]<=vxbf555;shdc077[1595]<=ie9813c[0];shdc077[1579]<=co215fe[1];shdc077[1572]<=osd4273;shdc077[1506]<=gqb66d4[0];shdc077[1450]<=en5bf1b;shdc077[1440]<=ip6f1c7;shdc077[1428]<=xw42fd5[0];shdc077[1384]<=yx5ecfb;shdc077[1370]<=vvdd7b3;shdc077[1366]<=rte375e;shdc077[1308]<=nr55e1f;shdc077[1284]<=ym3166f;shdc077[1212]<=zm30db3[0];shdc077[1202]<=vif4422;shdc077[1187]<=sufaaaf;shdc077[1174]<=ui7d6bd;shdc077[1170]<=hq99beb;shdc077[1142]<=dmc09e1;shdc077[1137]<=ea787f6;shdc077[1125]<=thf6d50;shdc077[1110]<=ksaff1[1];shdc077[1097]<=wla1399;shdc077[1041]<=lf16047;shdc077[1023]<=mr_main_reset;shdc077[964]<=ymb36a1[0];shdc077[949]<=kf3c2df;shdc077[906]<=jpf610a;shdc077[853]<=xwdf8dd;shdc077[833]<=su59bc7[0];shdc077[815]<=phaa186;shdc077[808]<=ep17eaa;shdc077[753]<=ic67029[0];shdc077[720]<=dzf67dd;shdc077[714]<=qte85fa[0];shdc077[692]<=dmebd9f;shdc077[685]<=xy1baf6;shdc077[654]<=vxaabc3;shdc077[601]<=bl5af42[0];shdc077[587]<=gb6fad7;shdc077[585]<=ho7337d;shdc077[568]<=lfaf0fe;shdc077[562]<=sw3edaa;shdc077[520]<=fp22c08;shdc077[474]<=fp2785b[0];shdc077[453]<=co1fd84;shdc077[407]<=fpb5430;shdc077[376]<=ay4ce05[0];shdc077[357]<=lsa2112;shdc077[327]<=rgd5578;shdc077[300]<=hoeb5e8[0];shdc077[293]<=thcdf5a;shdc077[292]<=qt4e66f;shdc077[281]<=zk47db5;shdc077[237]<=do4f0b;shdc077[226]<=kdc3fb0;shdc077[203]<=ukb6a86;shdc077[146]<=ep29198;shdc077[140]<=dzcde38;shdc077[70]<=nt811f6;shdc077[35]<=vxb023e;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[1]};ri1e680<=eae03bd[2];vvf3402<=eae03bd[3];qv9a017<={xl27f82>>1,eae03bd[4]};lqd00bc<={ald3027>>1,eae03bd[5]};yz805e3<={ie9813c>>1,eae03bd[6]};mt2f1c<=eae03bd[7];ux178e4<=eae03bd[8];qibc725<={fp2785b>>1,eae03bd[9]};dze3928<=eae03bd[10];vx1c947<=eae03bd[11];zke4a3e<={jeb7e3>>1,eae03bd[12]};je251f2<=eae03bd[13];rv28f93<=eae03bd[14];by47c9e<=eae03bd[15];ie3e4f2<=eae03bd[16];uvf2791<=eae03bd[17];hq93c8d<=eae03bd[18];tj9e46b<=eae03bd[19];kdf235e<=eae03bd[20];hd91af5<=eae03bd[21];ecbc0e3<=eae03bd[22];wl8af03<={su59bc7>>1,eae03bd[23]};sh5eb87<=eae03bd[24];yk622bc<=eae03bd[25];kfae1e9<=eae03bd[26];yx70f4c<=eae03bd[27];mg87a65<=eae03bd[28];vx3d328<=eae03bd[29];zk5781c<=eae03bd[30];ay4ca36<=eae03bd[31];kd651b1<=eae03bd[32];zz28d8d<=eae03bd[33];me46c6e<=eae03bd[34];ux36370<=eae03bd[35];irb1b85<=eae03bd[36];ou8dc2d<=eae03bd[37];th6e169<={zm30db3>>1,eae03bd[38]};jp5f50a<=eae03bd[39];gofa856<=eae03bd[40];ykd42b0<=eae03bd[41];yza1581<=eae03bd[42];ecac0d<=eae03bd[43];kq56068<=eae03bd[44];ntb0340<=eae03bd[45];bn81a06<=eae03bd[46];ohd037<={co215fe>>1,eae03bd[47]};me681bc<={ksaff1>>1,eae03bd[48]};end -always@* begin shdc077[2047]<=ykcb59e[0];shdc077[2046]<=vv5acf1;shdc077[2044]<=end678f;shdc077[2040]<=xl27f82[0];shdc077[2033]<=ald3027[0];shdc077[2019]<=ie9813c[0];shdc077[1994]<=ea787f6;shdc077[1990]<=dmc09e1;shdc077[1981]<=lf16047;shdc077[1965]<=sw3edaa;shdc077[1940]<=kdc3fb0;shdc077[1939]<=vvdd7b3;shdc077[1933]<=do4f0b;shdc077[1914]<=vxb023e;shdc077[1883]<=thf6d50;shdc077[1832]<=co1fd84;shdc077[1831]<=dmebd9f;shdc077[1819]<=fp2785b[0];shdc077[1785]<=vxaabc3;shdc077[1781]<=nt811f6;shdc077[1778]<=vvfc6eb;shdc077[1719]<=ukb6a86;shdc077[1616]<=jpf610a;shdc077[1615]<=yx5ecfb;shdc077[1591]<=kf3c2df;shdc077[1522]<=nr55e1f;shdc077[1515]<=dzcde38;shdc077[1508]<=rte375e;shdc077[1470]<=nr50c36;shdc077[1391]<=fpb5430;shdc077[1271]<=ui788b0;shdc077[1184]<=zzb0857;shdc077[1182]<=dzf67dd;shdc077[1135]<=fae16fc;shdc077[1023]<=mr_main_reset;shdc077[997]<=lfaf0fe;shdc077[990]<=fp22c08;shdc077[982]<=zk47db5;shdc077[969]<=xy1baf6;shdc077[892]<=zm30db3[0];shdc077[889]<=xwdf8dd;shdc077[735]<=phaa186;shdc077[643]<=ksaff1[1];shdc077[635]<=su59bc7[0];shdc077[495]<=ym3166f;shdc077[444]<=en5bf1b;shdc077[321]<=co215fe[1];shdc077[317]<=ip6f1c7;shdc077[222]<=jeb7e3[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[1]};ri1e680<=eae03bd[2];vvf3402<=eae03bd[3];yz805e3<={ie9813c>>1,eae03bd[4]};mt2f1c<=eae03bd[5];ux178e4<=eae03bd[6];hd91af5<=eae03bd[7];ecbc0e3<=eae03bd[8];wl8af03<={su59bc7>>1,eae03bd[9]};sh5eb87<=eae03bd[10];yk622bc<=eae03bd[11];kfae1e9<=eae03bd[12];yx70f4c<=eae03bd[13];mg87a65<=eae03bd[14];zk5781c<=eae03bd[15];kd651b1<=eae03bd[16];zz28d8d<=eae03bd[17];me46c6e<=eae03bd[18];ux36370<=eae03bd[19];irb1b85<=eae03bd[20];ou8dc2d<=eae03bd[21];jp5f50a<=eae03bd[22];gofa856<=eae03bd[23];ykd42b0<=eae03bd[24];yza1581<=eae03bd[25];end -always@* begin shdc077[2047]<=ykcb59e[0];shdc077[2046]<=vv5acf1;shdc077[2044]<=end678f;shdc077[2040]<=ie9813c[0];shdc077[2032]<=dmc09e1;shdc077[2017]<=do4f0b;shdc077[1987]<=dzf67dd;shdc077[1927]<=ip6f1c7;shdc077[1865]<=sw3edaa;shdc077[1806]<=su59bc7[0];shdc077[1682]<=thf6d50;shdc077[1565]<=ui788b0;shdc077[1317]<=ukb6a86;shdc077[1189]<=nr55e1f;shdc077[1172]<=phaa186;shdc077[1082]<=ym3166f;shdc077[1023]<=mr_main_reset;shdc077[932]<=dzcde38;shdc077[663]<=ea787f6;shdc077[594]<=vxaabc3;shdc077[586]<=fpb5430;shdc077[466]<=vxb023e;shdc077[331]<=lfaf0fe;shdc077[297]<=nr50c36;shdc077[233]<=lf16047;shdc077[116]<=fp22c08;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[4]};ir29604<={pf5a753>>1,eae03bd[5]};mr4b025<=eae03bd[6];by5812d<=eae03bd[7];zkc096b<={ph9ea41>>1,eae03bd[8]};xy4b5b<=eae03bd[9];hq25adb<=eae03bd[10];xy258ca<={enfda0c>>1,eae03bd[11]};ux2c652<={ofed065>>1,eae03bd[12]};rge4b19<={al7fb41>>1,eae03bd[13]};qgdb5f4<=eae03bd[14];lqdafa0<=eae03bd[15];dzd7d03<=eae03bd[16];mtbe81f<={dz55200>>1,eae03bd[17]};vif40fc<={ksa9007>>1,eae03bd[18]};nta07e2<=eae03bd[19];xl3f17<=eae03bd[20];co1f8be<=eae03bd[21];hbc76a1<=eae03bd[22];ie3b50f<=eae03bd[23];gd17c75<=eae03bd[24];kfbe3ad<=eae03bd[25];med43cb<={fcb89f1>>1,eae03bd[26]};end -always@* begin shdc077[2047]<=force_unidir;shdc077[2046]<=tx_en;shdc077[2044]<=tx_er;shdc077[2040]<=hqb4ea[0];shdc077[2032]<=pf5a753[0];shdc077[2016]<=end3a9e;shdc077[1985]<=eaea7a9;shdc077[1922]<=ph9ea41[0];shdc077[1796]<=gof520f;shdc077[1544]<=uka9078;shdc077[1302]<=qie56;shdc077[1115]<=rv8ee27;shdc077[1105]<=dz55200[0];shdc077[1041]<=enfda0c[0];shdc077[1023]<=mr_main_reset;shdc077[728]<=fcb89f1[1];shdc077[651]<=pf401ca;shdc077[557]<=vv71dc4;shdc077[552]<=gqaa40;shdc077[364]<=qg56362;shdc077[325]<=by48039;shdc077[276]<=eac1548;shdc077[182]<=vicac6c;shdc077[162]<=ksa9007[0];shdc077[138]<=kq782a9;shdc077[69]<=al7fb41[0];shdc077[34]<=ofed065[0];end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[1]};gb60d49<=eae03bd[2];ph6a4c<=eae03bd[3];ri35266<=eae03bd[4];eca9332<=eae03bd[5];ea49991<=eae03bd[6];os4cc89<={kf85f2c>>1,eae03bd[7]};rg66449<=eae03bd[8];zz3224a<=eae03bd[9];xl91257<={eae595b>>1,eae03bd[10]};pu892bf<={yz2cad8>>1,eae03bd[11]};ui495fa<={gb656c4>>1,eae03bd[12]};ld4afd0<={qi2b625>>1,eae03bd[13]};ps57e86<=eae03bd[14];fpbf433<=eae03bd[15];uifa19f<=eae03bd[16];lqd0cf9<=eae03bd[17];tw867ca<=eae03bd[18];cb33e53<=eae03bd[19];qv9f29c<=eae03bd[20];nrf94e4<=eae03bd[21];dmca726<=eae03bd[22];go53933<=eae03bd[23];end -always@* begin shdc077[2047]<=nrcd8ab[0];shdc077[2046]<=jc6c55f;shdc077[2044]<=su62afb;shdc077[2040]<=ie157d9;shdc077[2032]<=anabec9;shdc077[2017]<=ead4576;shdc077[1987]<=kf85f2c[0];shdc077[1926]<=hq2f965;shdc077[1804]<=dm7cb2b;shdc077[1803]<=wj5eb06;shdc077[1560]<=eae595b[6];shdc077[1550]<=icc4a26;shdc077[1072]<=yz2cad8[0];shdc077[1052]<=ri25131;shdc077[1023]<=xlba8ae;shdc077[901]<=ph8bd60;shdc077[775]<=thd8944;shdc077[450]<=sw317ac;shdc077[387]<=uv5b128;shdc077[225]<=kf262f5;shdc077[193]<=qi2b625[0];shdc077[112]<=uv44c5e;shdc077[96]<=gb656c4[6];shdc077[56]<=db2898b;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086>1,eae03bd[7]};ofdce1f<={rx_data>>1,eae03bd[8]};wje70fc<=eae03bd[9];gq1f934<=eae03bd[10];qi8892d<=eae03bd[11];ip44969<=eae03bd[12];qi24b4d<=eae03bd[13];pu25a68<={tx_d>>1,eae03bd[14]};ea6214b<=eae03bd[15];wy10a58<=eae03bd[16];qg59e57<=eae03bd[17];nef1679<=eae03bd[18];bn8b3ca<=eae03bd[19];pffc9a1<={bl7b70e>>1,eae03bd[20]};ntba454<={kqf5edc>>1,eae03bd[21]};jpd22a7<={hdaf6e1>>1,eae03bd[22]};nt387e4<=eae03bd[23];cb8a9f7<={psc5e98>>1,eae03bd[24]};wj54fbc<=eae03bd[25];doa7de4<=eae03bd[26];sw3ef23<=eae03bd[27];shf7918<=eae03bd[28];mgbc8c4<=eae03bd[29];zke4621<=eae03bd[30];oh2310b<=eae03bd[31];gof5284<=eae03bd[32];uka9420<=eae03bd[33];fn4a101<=eae03bd[34];zx5080f<=eae03bd[35];db8407e<=eae03bd[36];zm203f6<=eae03bd[37];xy20283<=eae03bd[38];xy141b<=eae03bd[39];coa0da<=eae03bd[40];bl506d1<=eae03bd[41];vk8368f<=eae03bd[42];ri1b47b<=eae03bd[43];tuda3da<=eae03bd[44];icd1ed2<={ld4ff63>>1,eae03bd[45]};wl8f690<=eae03bd[46];fn7b485<=eae03bd[47];vida42f<={zxec7a5>>1,eae03bd[48]};bld217a<=eae03bd[49];sj90bd6<=eae03bd[50];yz85eb4<=eae03bd[51];pu2f5a5<=eae03bd[52];mr7ad2a<=eae03bd[53];wjd6954<=eae03bd[54];irb4aa5<={gode5c1>>1,eae03bd[55]};rva552d<=eae03bd[56];ba2a96f<=eae03bd[57];ip54b7b<=eae03bd[58];xla5bdc<=eae03bd[59];vx2dee6<=eae03bd[60];end -always@* begin shdc077[2047]<=sgmii_mode;shdc077[2046]<=signal_detect;shdc077[2044]<=debug_link_timer_short;shdc077[2040]<=force_isolate;shdc077[2032]<=force_loopback;shdc077[2016]<=force_unidir;shdc077[1985]<=operational_rate[0];shdc077[1925]<=the6c4f;shdc077[1922]<=rx_data[0];shdc077[1802]<=sj3627f;shdc077[1796]<=rx_kcntl;shdc077[1567]<=kdf2e08;shdc077[1556]<=sjb13fd;shdc077[1544]<=rx_even;shdc077[1505]<=mg1f9b1;shdc077[1415]<=cmdbcb8;shdc077[1324]<=rg63d2f;shdc077[1316]<=mg986ac;shdc077[1200]<=zkf4bdb;shdc077[1169]<=gq1ab0d;shdc077[1163]<=vif4422;shdc077[1118]<=lf84490;shdc077[1106]<=su531f3;shdc077[1087]<=aa97044;shdc077[1065]<=ng89fec;shdc077[1041]<=mr_an_enable;shdc077[1040]<=rx_disp_err;shdc077[1023]<=gbe_mode;shdc077[962]<=ldfcd89;shdc077[783]<=gode5c1[0];shdc077[752]<=mga3f36;shdc077[707]<=cmdb797;shdc077[662]<=zxec7a5[0];shdc077[658]<=ip7a61a;shdc077[600]<=ba1e97b;shdc077[584]<=kdc3561;shdc077[581]<=ieac34a;shdc077[559]<=aa10892;shdc077[553]<=hdaf6e1[0];shdc077[520]<=tx_er;shdc077[508]<=wl8810;shdc077[376]<=sj12436;shdc077[353]<=xla5edb;shdc077[331]<=czfd8f4;shdc077[329]<=vk2f4c3;shdc077[290]<=ned5869;shdc077[279]<=lsa2112;shdc077[276]<=kqf5edc[0];shdc077[260]<=tx_en;shdc077[254]<=wwc1102;shdc077[188]<=nt22486;shdc077[165]<=qt7fb1e;shdc077[164]<=psc5e98[0];shdc077[138]<=bl7b70e[0];shdc077[130]<=tx_d[0];shdc077[127]<=jeb8220;shdc077[82]<=ld4ff63[0];shdc077[69]<=mr_restart_an;shdc077[65]<=rx_err_decode_mode;shdc077[34]<=mr_main_reset;shdc077[32]<=rx_cv_err;end assign uk82f73 = shdc077,eae03bd = jebdcc5; initial begin xj5a610 = $fopen(".fred"); $fdisplay( xj5a610, "%3h\n%3h", (ea77a5a >> 4) & fn5a0bd, (ea77a5a >> (the9682+4)) & fn5a0bd ); $fclose(xj5a610); $readmemh(".fred", dm7315a); end always @ (uk82f73) begin nec5698 = dm7315a[1]; for (qtd3086=0; qtd3086 - - - - - - - - - diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem.jhd b/gbe2_ecp3/ipcores_ecp3/statts_mem.jhd deleted file mode 100644 index c179a51..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem.jhd +++ /dev/null @@ -1,7 +0,0 @@ -MODULE statts_mem DEFIN statts_mem.vhd - SUBMODULE PDPW16KC - INSTANCE statts_mem_0_0_0 - SUBMODULE VLO - INSTANCE scuba_vlo_inst - SUBMODULE VHI - INSTANCE scuba_vhi_inst diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem.lpc b/gbe2_ecp3/ipcores_ecp3/statts_mem.lpc deleted file mode 100644 index c24e581..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem.lpc +++ /dev/null @@ -1,53 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=RAM_DP -CoreRevision=6.1 -ModuleName=statts_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/05/2011 -Time=22:40:38 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -RAddress=1020 -RData=8 -WAddress=255 -WData=32 -enByte=0 -ByteSize=9 -adPipeline=0 -inPipeline=0 -outPipeline=0 -MOR=0 -InData=Registered -AdControl=Registered -MemFile= -MemFormat=bin -Reset=Sync -GSR=Enabled -Pad=0 -EnECC=0 -Optimization=Speed -EnSleep=ENABLED -Pipeline=0 - -[FilesGenerated] -=mem diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem.naf b/gbe2_ecp3/ipcores_ecp3/statts_mem.naf deleted file mode 100644 index 29865ef..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem.naf +++ /dev/null @@ -1,64 +0,0 @@ -WrAddress[7] i -WrAddress[6] i -WrAddress[5] i -WrAddress[4] i -WrAddress[3] i -WrAddress[2] i -WrAddress[1] i -WrAddress[0] i -RdAddress[9] i -RdAddress[8] i -RdAddress[7] i -RdAddress[6] i -RdAddress[5] i -RdAddress[4] i -RdAddress[3] i -RdAddress[2] i -RdAddress[1] i -RdAddress[0] i -Data[31] i -Data[30] i -Data[29] i -Data[28] i -Data[27] i -Data[26] i -Data[25] i -Data[24] i -Data[23] i -Data[22] i -Data[21] i -Data[20] i -Data[19] i -Data[18] i -Data[17] i -Data[16] i -Data[15] i -Data[14] i -Data[13] i -Data[12] i -Data[11] i -Data[10] i -Data[9] i -Data[8] i -Data[7] i -Data[6] i -Data[5] i -Data[4] i -Data[3] i -Data[2] i -Data[1] i -Data[0] i -WE i -RdClock i -RdClockEn i -Reset i -WrClock i -WrClockEn i -Q[7] o -Q[6] o -Q[5] o -Q[4] o -Q[3] o -Q[2] o -Q[1] o -Q[0] o diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem.sort b/gbe2_ecp3/ipcores_ecp3/statts_mem.sort deleted file mode 100644 index c7d53c5..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem.sort +++ /dev/null @@ -1 +0,0 @@ -statts_mem.vhd diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem.srp b/gbe2_ecp3/ipcores_ecp3/statts_mem.srp deleted file mode 100644 index 15fab7a..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem.srp +++ /dev/null @@ -1,28 +0,0 @@ -SCUBA, Version Diamond_1.3_Production (92) -Mon Dec 5 22:40:38 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n statts_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -device LFE3-150EA -type ramdps -raddr_width 10 -rwidth 8 -waddr_width 8 -wwidth 32 -rnum_words 1020 -wnum_words 255 -cascade -1 -e - Circuit name : statts_mem - Module type : RAM_DP - Module Version : 6.1 - Ports : - Inputs : WrAddress[7:0], RdAddress[9:0], Data[31:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn - Outputs : Q[7:0] - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : statts_mem.vhd - VHDL template : statts_mem_tmpl.vhd - VHDL testbench : tb_statts_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : statts_mem.srp - Element Usage : - PDPW16KC : 1 - Estimated Resource Usage: - EBR : 1 diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem.sym b/gbe2_ecp3/ipcores_ecp3/statts_mem.sym deleted file mode 100644 index aaac4c0b78a103ac32362f3f08b941abeeb13d07..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 442 zcmXw$F-yZx6ot=C)shS$gE(g>QXC{AD0YgPI%*6`#2`{lT(q?$8Jwh(gHtC5M{z9T zEE@tWNsDHT6*K~Z6?Do@ zvcA^x&VUn&0Ro-aQM#R`c~%t3mP&g}9l6kHJxX_PZZEI#Kh_@eRgp^Y8q{}VUW#0k^BeCxCx=X&BV?NENSHD{I+t9wphNMp|y zEF31f2OzbB<0GbvR#A4!vN-Q%U0_w3@-93An&O}>J7U7)_f?O5;i5RhWt}SSllyX| uI3$OXEB45q+$(m-jyx)!!sSh$*t6QT%X(2fAP?}S*eCnUExx%!{-ZzWO-(HT diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd b/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd deleted file mode 100644 index 2a03d69..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd +++ /dev/null @@ -1,159 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 6.1 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 8 -data_width 32 -num_rows 255 -cascade -1 -e - --- Mon Dec 5 22:40:38 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity statts_mem is - port ( - WrAddress: in std_logic_vector(7 downto 0); - RdAddress: in std_logic_vector(9 downto 0); - Data: in std_logic_vector(31 downto 0); - WE: in std_logic; - RdClock: in std_logic; - RdClockEn: in std_logic; - Reset: in std_logic; - WrClock: in std_logic; - WrClockEn: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end statts_mem; - -architecture Structure of statts_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component PDPW16KC - generic (GSR : in String; CSDECODE_R : in String; - CSDECODE_W : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of statts_mem_0_0_0 : label is "statts_mem.lpc"; - attribute MEM_INIT_FILE of statts_mem_0_0_0 : label is ""; - attribute RESETMODE of statts_mem_0_0_0 : label is "SYNC"; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - statts_mem_0_0_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10), - DI12=>Data(11), DI13=>Data(12), DI14=>Data(13), - DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo, - DI18=>Data(16), DI19=>Data(17), DI20=>Data(18), - DI21=>Data(19), DI22=>Data(20), DI23=>Data(21), - DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo, - DI27=>Data(24), DI28=>Data(25), DI29=>Data(26), - DI30=>Data(27), DI31=>Data(28), DI32=>Data(29), - DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo, - ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2), - ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5), - ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>scuba_vlo, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>RdAddress(0), - ADR4=>RdAddress(1), ADR5=>RdAddress(2), ADR6=>RdAddress(3), - ADR7=>RdAddress(4), ADR8=>RdAddress(5), ADR9=>RdAddress(6), - ADR10=>RdAddress(7), ADR11=>RdAddress(8), - ADR12=>RdAddress(9), ADR13=>scuba_vlo, CER=>RdClockEn, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), - DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), - DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, - DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, - DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open, - DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open, - DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open, - DO33=>open, DO34=>open, DO35=>open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of statts_mem is - for Structure - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem_generate.log b/gbe2_ecp3/ipcores_ecp3/statts_mem_generate.log deleted file mode 100644 index 5b91f8b..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem_generate.log +++ /dev/null @@ -1,46 +0,0 @@ -Starting process: Module - -Starting process: - -SCUBA, Version Diamond_1.3_Production (92) -Mon Dec 5 22:40:38 2011 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n statts_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -device LFE3-150EA -type ramdps -raddr_width 10 -rwidth 8 -waddr_width 8 -wwidth 32 -rnum_words 1020 -wnum_words 255 -cascade -1 -e - Circuit name : statts_mem - Module type : RAM_DP - Module Version : 6.1 - Ports : - Inputs : WrAddress[7:0], RdAddress[9:0], Data[31:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn - Outputs : Q[7:0] - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : statts_mem.vhd - VHDL template : statts_mem_tmpl.vhd - VHDL testbench : tb_statts_mem_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : statts_mem.srp - Estimated Resource Usage: - EBR : 1 - -END SCUBA Module Synthesis - -File: statts_mem.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe2_ecp3/ipcores_ecp3/statts_mem_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/statts_mem_tmpl.vhd deleted file mode 100644 index 9953b55..0000000 --- a/gbe2_ecp3/ipcores_ecp3/statts_mem_tmpl.vhd +++ /dev/null @@ -1,19 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 6.1 --- Mon Dec 5 22:40:38 2011 - --- parameterized module component declaration -component statts_mem - port (WrAddress: in std_logic_vector(7 downto 0); - RdAddress: in std_logic_vector(9 downto 0); - Data: in std_logic_vector(31 downto 0); WE: in std_logic; - RdClock: in std_logic; RdClockEn: in std_logic; - Reset: in std_logic; WrClock: in std_logic; - WrClockEn: in std_logic; Q: out std_logic_vector(7 downto 0)); -end component; - --- parameterized module component instance -__ : statts_mem - port map (WrAddress(7 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(31 downto 0)=>__, - WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__, - WrClockEn=>__, Q(7 downto 0)=>__); diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_1024x16x8_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_1024x16x8_tmpl.vhd deleted file mode 100644 index 2d1eced..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_1024x16x8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_1024x16x8 - port (Data : in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(17 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_1024x16x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 1027 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 1027 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 1027 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_2048x8_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_2048x8_tmpl.vhd deleted file mode 100755 index 343af71..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_2048x8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_2048x8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_2048x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 2051 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_2048x8x16_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_2048x8x16_tmpl.vhd deleted file mode 100644 index ceb4df6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_2048x8x16_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_2048x8x16 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(17 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(17 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_2048x8x16 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 2051 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_mb2_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_mb2_tmpl.vhd deleted file mode 100644 index f14d662..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_mb2_tmpl.vhd +++ /dev/null @@ -1,115 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8_mb2 - port (Data : in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic - ); - end component; - - signal Data : std_logic_vector(17 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0'); - signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0'); - signal Q : std_logic_vector(8 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; - signal AlmostEmpty: std_logic; - signal AlmostFull: std_logic; -begin - u1 : fifo_32kx16x8_mb2 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full, - AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_mb_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_mb_tmpl.vhd deleted file mode 100755 index 1ad6e7d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_mb_tmpl.vhd +++ /dev/null @@ -1,115 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8_mb - port (Data : in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic - ); - end component; - - signal Data : std_logic_vector(15 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0'); - signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0'); - signal Q : std_logic_vector(7 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; - signal AlmostEmpty: std_logic; - signal AlmostFull: std_logic; -begin - u1 : fifo_32kx16x8_mb - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full, - AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_tmpl.vhd deleted file mode 100755 index 3bbafb6..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_32kx16x8_tmpl.vhd +++ /dev/null @@ -1,106 +0,0 @@ --- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8 - port (Data : in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(15 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_32kx16x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_4096x32_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_4096x32_tmpl.vhd deleted file mode 100755 index 0559dd7..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_4096x32_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x32 - port (Data : in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(31 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x32 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_4096x9_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_4096x9_tmpl.vhd deleted file mode 100755 index 9352be8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_4096x9_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x9 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x9 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x32_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x32_tmpl.vhd deleted file mode 100644 index 7353ce2..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x32_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x32 - port (Data : in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(31 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x32 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x64_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x64_tmpl.vhd deleted file mode 100644 index dc94036..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x64_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x64 - port (Data : in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(71 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(71 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(71 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x64 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x72_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x72_tmpl.vhd deleted file mode 100644 index 7c36749..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_512x72_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x72 - port (Data : in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(71 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(71 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(71 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x72 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx8_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx8_tmpl.vhd deleted file mode 100755 index 2096041..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_64kx8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_64kx8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 65539 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx9_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx9_tmpl.vhd deleted file mode 100644 index d47fc48..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_fifo_64kx9_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_64kx9 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_64kx9 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 65539 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_ip_mem_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_ip_mem_tmpl.vhd deleted file mode 100755 index 862c84d..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_ip_mem_tmpl.vhd +++ /dev/null @@ -1,174 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component ip_mem - port (DataInA : in std_logic_vector(31 downto 0); - DataInB : in std_logic_vector(31 downto 0); - AddressA : in std_logic_vector(7 downto 0); - AddressB : in std_logic_vector(7 downto 0); ClockA: in std_logic; - ClockB: in std_logic; ClockEnA: in std_logic; - ClockEnB: in std_logic; WrA: in std_logic; WrB: in std_logic; - ResetA: in std_logic; ResetB: in std_logic; - QA : out std_logic_vector(31 downto 0); - QB : out std_logic_vector(31 downto 0) - ); - end component; - - signal DataInA : std_logic_vector(31 downto 0) := (others => '0'); - signal DataInB : std_logic_vector(31 downto 0) := (others => '0'); - signal AddressA : std_logic_vector(7 downto 0) := (others => '0'); - signal AddressB : std_logic_vector(7 downto 0) := (others => '0'); - signal ClockA: std_logic := '0'; - signal ClockB: std_logic := '0'; - signal ClockEnA: std_logic := '0'; - signal ClockEnB: std_logic := '0'; - signal WrA: std_logic := '0'; - signal WrB: std_logic := '0'; - signal ResetA: std_logic := '0'; - signal ResetB: std_logic := '0'; - signal QA : std_logic_vector(31 downto 0); - signal QB : std_logic_vector(31 downto 0); -begin - u1 : ip_mem - port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA, - AddressB => AddressB, ClockA => ClockA, ClockB => ClockB, - ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB, - ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB - ); - - process - - begin - DataInA <= (others => '0') ; - wait for 100 ns; - wait until ResetA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - DataInA <= DataInA + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - DataInB <= (others => '0') ; - wait for 100 ns; - wait until ResetB = '0'; - wait until WrB = '1'; - for i in 0 to 259 loop - wait until ClockB'event and ClockB = '1'; - DataInB <= DataInB + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - AddressA <= (others => '0') ; - wait for 100 ns; - wait until ResetA = '0'; - for i in 0 to 518 loop - wait until ClockA'event and ClockA = '1'; - AddressA <= AddressA + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - AddressB <= (others => '0') ; - wait for 100 ns; - wait until ResetB = '0'; - wait until WrB = '1'; - for i in 0 to 518 loop - wait until ClockB'event and ClockB = '1'; - AddressB <= AddressB + '1' after 1 ns; - end loop; - wait; - end process; - - ClockA <= not ClockA after 5.00 ns; - - ClockB <= not ClockB after 5.00 ns; - - process - - begin - ClockEnA <= '0' ; - wait for 100 ns; - wait until ResetA = '0'; - ClockEnA <= '1' ; - wait; - end process; - - process - - begin - ClockEnB <= '0' ; - wait for 100 ns; - wait until ResetB = '0'; - ClockEnB <= '1' ; - wait; - end process; - - process - - begin - WrA <= '0' ; - wait until ResetA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - WrA <= '1' after 1 ns; - end loop; - WrA <= '0' ; - wait; - end process; - - process - - begin - WrB <= '0' ; - wait until ResetB = '0'; - wait until WrA = '1'; - wait until WrA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - end loop; - for i in 0 to 259 loop - wait until ClockB'event and ClockB = '1'; - WrB <= '1' after 1 ns; - end loop; - WrB <= '0' ; - wait; - end process; - - process - - begin - ResetA <= '1' ; - wait for 100 ns; - ResetA <= '0' ; - wait; - end process; - - process - - begin - ResetB <= '1' ; - wait for 100 ns; - ResetB <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_mac_init_mem_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_mac_init_mem_tmpl.vhd deleted file mode 100755 index 701eaf3..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_mac_init_mem_tmpl.vhd +++ /dev/null @@ -1,64 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component mac_init_mem - port (Address : in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q : out std_logic_vector(7 downto 0) - ); - end component; - - signal Address : std_logic_vector(5 downto 0) := (others => '0'); - signal OutClock: std_logic := '0'; - signal OutClockEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); -begin - u1 : mac_init_mem - port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn, - Reset => Reset, Q => Q - ); - - process - - begin - Address <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 57 loop - wait until OutClock'event and OutClock = '1'; - Address <= Address + '1' after 1 ns; - end loop; - wait; - end process; - - OutClock <= not OutClock after 5.00 ns; - - process - - begin - OutClockEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - OutClockEn <= '1' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tb_statts_mem_tmpl.vhd b/gbe2_ecp3/ipcores_ecp3/tb_statts_mem_tmpl.vhd deleted file mode 100644 index 8428650..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tb_statts_mem_tmpl.vhd +++ /dev/null @@ -1,124 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component statts_mem - port (WrAddress : in std_logic_vector(7 downto 0); - RdAddress : in std_logic_vector(9 downto 0); - Data : in std_logic_vector(31 downto 0); WE: in std_logic; - RdClock: in std_logic; RdClockEn: in std_logic; - Reset: in std_logic; WrClock: in std_logic; - WrClockEn: in std_logic; Q : out std_logic_vector(7 downto 0) - ); - end component; - - signal WrAddress : std_logic_vector(7 downto 0) := (others => '0'); - signal RdAddress : std_logic_vector(9 downto 0) := (others => '0'); - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WE: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal RdClockEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal WrClock: std_logic := '0'; - signal WrClockEn: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); -begin - u1 : statts_mem - port map (WrAddress => WrAddress, RdAddress => RdAddress, Data => Data, - WE => WE, RdClock => RdClock, RdClockEn => RdClockEn, Reset => Reset, - WrClock => WrClock, WrClockEn => WrClockEn, Q => Q - ); - - process - - begin - WrAddress <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 516 loop - wait until WrClock'event and WrClock = '1'; - WrAddress <= WrAddress + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - RdAddress <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 516 loop - wait until RdClock'event and RdClock = '1'; - RdAddress <= RdAddress + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 258 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - WE <= '0' ; - wait until Reset = '0'; - for i in 0 to 258 loop - wait until WrClock'event and WrClock = '1'; - WE <= '1' after 1 ns; - end loop; - WE <= '0' ; - wait; - end process; - - RdClock <= not RdClock after 20.00 ns; - - process - - begin - RdClockEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - RdClockEn <= '1' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - process - - begin - WrClockEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - WrClockEn <= '1' ; - wait; - end process; - -end architecture test; diff --git a/gbe2_ecp3/ipcores_ecp3/tsmac3/generate_core.tcl b/gbe2_ecp3/ipcores_ecp3/tsmac3/generate_core.tcl deleted file mode 100755 index d6f3ade..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tsmac3/generate_core.tcl +++ /dev/null @@ -1,39 +0,0 @@ - -#!/usr/local/bin/wish - -set Para(cmd) "" -if ![catch {set temp $argc} result] { - if {$argc > 0} { - for {set i 0} {$i < $argc} {incr i 2} { - set temp [lindex $argv $i] - set temp [string range $temp 1 end] - lappend argv_list $temp - lappend value_list [lindex $argv [expr $i+1]] - } - foreach argument $argv_list value $value_list { - switch $argument { - "cmd" {set Para(cmd) $value;} - } - } - } -} - -set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/tsmac3" -set Para(ModuleName) "tsmac3" -set Para(lib) "/home/greg/trispeed_mac_v3.4/lib" -set Para(CoreName) "Tri-Speed Ethernet MAC" -set Para(family) "latticeecp2m" -set Para(Family) "ep5m00" -set Para(design) "VHDL" - -lappend auto_path "/home/greg/trispeed_mac_v3.4/gui" - -lappend auto_path "/home/greg/trispeed_mac_v3.4/script" -package require Core_Generate - -lappend auto_path "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../runproc" -package require runcmd - -set Para(install_dir) "/opt/lattice/ispLEVER8.1/isptools/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../../../../.." - -set Para(result) [GenerateCore] diff --git a/gbe2_ecp3/ipcores_ecp3/tsmac3/orcapp_head b/gbe2_ecp3/ipcores_ecp3/tsmac3/orcapp_head deleted file mode 100644 index 3b0bf92..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tsmac3/orcapp_head +++ /dev/null @@ -1,4 +0,0 @@ -#define USER_NAME tsmac3 -#define SGMII_TSMAC -#define DEVICE_ECP2M -#define DEVICE_ECP2_ECP2M diff --git a/gbe2_ecp3/ipcores_ecp3/tsmac3/pmi_ram_dpEbnonessdn208256208256.ngo b/gbe2_ecp3/ipcores_ecp3/tsmac3/pmi_ram_dpEbnonessdn208256208256.ngo deleted file mode 100755 index 47d679a603be8ceb0e8a2a16f117aed5249c7e32..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 11279 zcma)C4Rlr2m3~S1*$8U2r;3W z1+|m0v_seUlW9kd|EZ!xtZl49BZ5Xija4+Xj7G~$ku^H;2hBpuWR2r6``i26m;3H} zYdOy)?DL)P?6c24=iamT-3*N!9WVEl&Gq3ojjSzQ{C8ga`qos(s`aU+_TcKa4QSLvTV3da0QENE_@x8CpfQQLKWXx3gGEUzo~2Ypm>Z=(RAs%T}j!AEP4 zY(={|7!NH*_kmt+<}Ho}E3IJ43e^Q;R%Kn-Ck9Nv8e^ngSiTz0JHpmkh@n; ze2Mvz{N7I^hYkhQiaM;z~(#n>zO7S`3Km7Q= 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zh1pGr%V)X0CL(^Dh1n#;7s-sth~MvE7DRkqGZjMoz6vUg;(jtNg7~~vW>LiNwNO(K z=_x(O5b14Y7Dwd#CaN5f3)*1nH5HKyEz~qb`Z}oTh**Nu3`F`RsGAY#A&+t+&RRKT%YcAJf%9b}JNV7sf7bLYUey@9$FL;fwN=E7!9QS)HyF5~9I*0Y6KC2V=M z)B@OgH&Y8?>r+83f=xb+@3k1V{<7O`uocv?x&*et_0&?>E=^Ji*siFimcdpe9V~}! zl+0KGn>;u6S_#{Y4vsVK%dN>c>1,mef0f02[1]};ic538ab<=mef0f02[2];zm9c559<=mef0f02[3];kde2acb<=mef0f02[4];wy1565d<=mef0f02[5];irab2e9<=mef0f02[6];go5974c<=mef0f02[7];mecba61<=mef0f02[8];xw5d308<=mef0f02[9];go4c21e<={os5391b>>1,mef0f02[10]};dz610f0<={vk9c8d9>>1,mef0f02[11]};ic43c3c<={oh23653>>1,mef0f02[12]};end -always@* begin ng1e1e0[2047]<=ls86aa0[0];ng1e1e0[2046]<=ls35502;ng1e1e0[2044]<=lfaa812;ng1e1e0[2040]<=wl95504;ng1e1e0[2032]<=zkee699;ng1e1e0[2016]<=ne734ca;ng1e1e0[1984]<=ep9a653;ng1e1e0[1920]<=uvd329c;ng1e1e0[1793]<=ng994e4;ng1e1e0[1539]<=os5391b[0];ng1e1e0[1030]<=vk9c8d9[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[13]<=oh23653[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};al4b56a<=mef0f02[1];zm9c559<=mef0f02[2];byd5aaf<=mef0f02[3];gb6abd3<={uv70d29>>1,mef0f02[4]};ntaf4ee<={hq8694d>>1,mef0f02[5]};czd3bb5<={ec34a6a>>1,mef0f02[6]};dmeed68<={lfa5351>>1,mef0f02[7]};dbb5a1a<={gd29a8f>>1,mef0f02[8]};go686bb<={rg4d47c>>1,mef0f02[9]};ie1aec9<={mr6a3e2>>1,mef0f02[10]};yzbb24e<={of51f14>>1,mef0f02[11]};gbc93ad<={sj8f8a4>>1,mef0f02[12]};ay49d6c<=mef0f02[13];kd4eb61<=mef0f02[14];ip75b0c<=mef0f02[15];lq6c32a<={wla48aa>>1,mef0f02[16]};ld61953<=mef0f02[17];dbca9e<=mef0f02[18];ip654f7<=mef0f02[19];hq2a7bd<=mef0f02[20];yk53dea<=mef0f02[21];zz9ef51<=mef0f02[22];kdf7a8f<=mef0f02[23];babd47c<=mef0f02[24];yx51f10<={wj5b24d>>1,mef0f02[25]};jc7c424<={enc9365>>1,mef0f02[26]};yxe2122<=mef0f02[27];aa10914<=mef0f02[28];lf848a0<=mef0f02[29];ou24507<=mef0f02[30];fp22839<=mef0f02[31];je141cf<=mef0f02[32];jra0e7b<=mef0f02[33];mt73de<=mef0f02[34];rgcf7ad<={jra5ef8>>1,mef0f02[35]};icdeb5e<={hb7be32>>1,mef0f02[36]};cmf5af1<=mef0f02[37];twad789<=mef0f02[38];cz5e25f<={bn32cad>>1,mef0f02[39]};dmf12fc<=mef0f02[40];xy897e2<=mef0f02[41];ip4bf12<=mef0f02[42];th5f894<=mef0f02[43];pffc4a7<=mef0f02[44];wl129f4<={co928b1>>1,mef0f02[45]};doa7d2e<={baa2c4f>>1,mef0f02[46]};sw3e973<=mef0f02[47];rgf4b98<=mef0f02[48];lfa5cc3<=mef0f02[49];aa2e61e<=mef0f02[50];vi730f0<=mef0f02[51];ou98783<=mef0f02[52];alc3c19<=mef0f02[53];ba1e0cc<=mef0f02[54];uif0662<=mef0f02[55];do83310<=mef0f02[56];fp19883<=mef0f02[57];end -always@* begin ng1e1e0[2047]<=cb25ef;ng1e1e0[2046]<=lfaa812;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=uv70d29[0];ng1e1e0[2032]<=hq8694d[0];ng1e1e0[2017]<=ec34a6a[0];ng1e1e0[1987]<=lfa5351[0];ng1e1e0[1980]<=je89ef4;ng1e1e0[1963]<=xyb52f;ng1e1e0[1942]<=ksa3f8a;ng1e1e0[1926]<=gd29a8f[0];ng1e1e0[1921]<=ks152d9;ng1e1e0[1913]<=fn4f7a3;ng1e1e0[1903]<=an95b92;ng1e1e0[1879]<=nr5a97b;ng1e1e0[1837]<=wy1fc51;ng1e1e0[1805]<=rg4d47c[0];ng1e1e0[1795]<=oua96c9;ng1e1e0[1783]<=baa2c4f[0];ng1e1e0[1778]<=zx7bd1f;ng1e1e0[1758]<=jeadc94;ng1e1e0[1710]<=jra5ef8[0];ng1e1e0[1679]<=wla48aa[0];ng1e1e0[1627]<=lqfe289;ng1e1e0[1562]<=mr6a3e2[0];ng1e1e0[1543]<=wj5b24d[0];ng1e1e0[1519]<=fp1627b;ng1e1e0[1509]<=uide8fe;ng1e1e0[1499]<=hq9656e;ng1e1e0[1469]<=rt6e4a2;ng1e1e0[1398]<=shf8cb2;ng1e1e0[1373]<=hb7be32[0];ng1e1e0[1310]<=fac526c;ng1e1e0[1207]<=rgf144b;ng1e1e0[1144]<=ww49b15;ng1e1e0[1076]<=of51f14[0];ng1e1e0[1039]<=enc9365[0];ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[990]<=yzb13de;ng1e1e0[981]<=xj616a5;ng1e1e0[971]<=vif47f1;ng1e1e0[960]<=cm62a5b;ng1e1e0[951]<=ngb2b72;ng1e1e0[891]<=co928b1[0];ng1e1e0[839]<=vk14915;ng1e1e0[749]<=bn32cad[0];ng1e1e0[699]<=hodf196;ng1e1e0[572]<=qv29362;ng1e1e0[490]<=gd2c2d4;ng1e1e0[480]<=ho6c54b;ng1e1e0[419]<=ale2922;ng1e1e0[245]<=sh6585a;ng1e1e0[240]<=dm4d8a9;ng1e1e0[209]<=tu7c524;ng1e1e0[122]<=tu6cb0b;ng1e1e0[104]<=sj8f8a4[0];ng1e1e0[61]<=lq4d961;ng1e1e0[30]<=kq49b2c;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f= 7'h42); - - -assign sw21a46 = zx4f6f2 & ~ofed2bb; -assign zz84348 = bna0270 & ~mg875ed & ~bn9c3a & ~sh4e1d7; - - -assign al70eaa = bldd794 & aa3404e[18]; - - - - - - -assign fpaaa53 = (bna0270 | rx_write) & wwde5f9 & ~mg875ed & ~bn9c3a; - -always@* begin zx4f6f2<=mef0f02[0];dz7b797<=mef0f02[1];eadbcbf<={epae410>>1,mef0f02[2]};wwde5f9<=mef0f02[3];ks97e44<={ep90421>>1,mef0f02[4]};pff910f<={of4bc4f>>1,mef0f02[5]};wj443f7<={vif13e4>>1,mef0f02[6]};ukfde0<={hd9bdf7>>1,mef0f02[7]};off7806<={wjf7df9>>1,mef0f02[8]};gqbc034<=mef0f02[9];yke01a0<=mef0f02[10];ecd01<=mef0f02[11];aa3404e<={tw3fb87>>1,mef0f02[12]};bna0270<=mef0f02[13];do1387<=mef0f02[14];bn9c3a<=mef0f02[15];sh4e1d7<=mef0f02[16];yx70ebd<=mef0f02[17];mg875ed<=mef0f02[18];xy3af69<=mef0f02[19];ribda57<={coa94ff>>1,mef0f02[20]};ofed2bb<=mef0f02[21];fn4aeeb<={wl9fe79>>1,mef0f02[22]};gdbbaf2<={ldf9e69>>1,mef0f02[23]};bldd794<=mef0f02[24];zkebca7<=mef0f02[25];sh5e53b<=mef0f02[26];czf29dc<=mef0f02[27];end -always@* begin ng1e1e0[2047]<=wy15c82;ng1e1e0[2046]<=epae410[0];ng1e1e0[2044]<=rx_fifo_full;ng1e1e0[2040]<=ep90421[0];ng1e1e0[2032]<=of4bc4f[0];ng1e1e0[2017]<=vif13e4[0];ng1e1e0[1987]<=hd9bdf7[0];ng1e1e0[1926]<=wjf7df9[0];ng1e1e0[1921]<=ldf9e69[0];ng1e1e0[1805]<=ipf7e64;ng1e1e0[1795]<=rgcf34f;ng1e1e0[1679]<=co87555;ng1e1e0[1562]<=ntbf324;ng1e1e0[1543]<=ps79a7b;ng1e1e0[1310]<=vk3aaa9;ng1e1e0[1144]<=fpaaa53;ng1e1e0[1076]<=jpf9927;ng1e1e0[1039]<=zxcd3db;ng1e1e0[1023]<=tu42b90;ng1e1e0[960]<=wl9fe79[0];ng1e1e0[839]<=al70eaa;ng1e1e0[572]<=psd554a;ng1e1e0[480]<=rt4a7f9;ng1e1e0[419]<=hoee1d5;ng1e1e0[240]<=coa94ff[0];ng1e1e0[209]<=alfdc3a;ng1e1e0[104]<=tw3fb87[0];ng1e1e0[30]<=xw69ede;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};zm9c559<=mef0f02[1];fp81339<=mef0f02[2];byd5aaf<=mef0f02[3];os4ce77<=mef0f02[4];qv39dc8<={ba25a85>>1,mef0f02[5]};eacee45<=mef0f02[6];kq77228<=mef0f02[7];ldc8a08<={gq3eb5e>>1,mef0f02[8]};vv45047<=mef0f02[9];ph2823e<=mef0f02[10];qt411f7<=mef0f02[11];an8fbc<=mef0f02[12];jc47de5<=mef0f02[13];uk3ef2a<=mef0f02[14];ipf7950<=mef0f02[15];ksbca84<=mef0f02[16];ice5421<=mef0f02[17];bl5084a<={do1ba48>>1,mef0f02[18]};tj84256<=mef0f02[19];wy212b6<=mef0f02[20];rv95b1<=mef0f02[21];nr4ad8e<=mef0f02[22];swb63b1<={qi1fe10>>1,mef0f02[23]};fp19883<=mef0f02[24];end -always@* begin ng1e1e0[2047]<=lfaa812;ng1e1e0[2046]<=jc4d12d;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=gb44b50;ng1e1e0[2032]<=ba25a85[0];ng1e1e0[2017]<=ukf3ec;ng1e1e0[1987]<=zz22aa1;ng1e1e0[1926]<=gq3eb5e[0];ng1e1e0[1804]<=mg8d20b;ng1e1e0[1803]<=qi1fe10[0];ng1e1e0[1560]<=xw69058;ng1e1e0[1558]<=rgf144b;ng1e1e0[1550]<=co1a8dd;ng1e1e0[1072]<=by482c3;ng1e1e0[1052]<=god46e9;ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[901]<=dm487f8;ng1e1e0[775]<=qtc351b;ng1e1e0[450]<=qg490ff;ng1e1e0[387]<=dm586a3;ng1e1e0[225]<=zxe921f;ng1e1e0[193]<=jeb0d4;ng1e1e0[112]<=rtdd243;ng1e1e0[96]<=of4161a;ng1e1e0[56]<=do1ba48[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};wl9fec7<=mef0f02[1];kqff63d<=mef0f02[2];jcfb1e9<=mef0f02[3];dzd8f4b<=mef0f02[4];nrc7a5e<={vif4c35>>1,mef0f02[5]};db3d2f6<={zm3f362>>1,mef0f02[6]};dze97b6<={ps6c4ff>>1,mef0f02[7]};yx4bdb7<={os627fb>>1,mef0f02[8]};end -always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uk317a6;ng1e1e0[2044]<=fp8bd30;ng1e1e0[2041]<=uv5e986;ng1e1e0[2034]<=vif4c35[0];ng1e1e0[2021]<=zm3f362[0];ng1e1e0[1995]<=ps6c4ff[0];ng1e1e0[1943]<=os627fb[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f= 14'd64); - - - - -assign wy15c82 = ((~gq88319) ? (lfaa812 & ~gq3e3e7) : 1'b0) | (zzb0517 & ~qi828be) | (dob2655 & ~ba932ab) | (vvc8b97 & ux7990 & lfaa812) | (pu3a20c & lfaa812); - -assign cz65043 = al4b56a | (zxcd67f & an8a74); - - -assign nt2821d = gb44b50; -assign al410ef = gb44b50 & ea437a9; - - -assign ui43be4 = (~xl84bbc) ? hofec14 -14'd4 : fc83768; - -assign kf17a95 = 32'hffffffff; - -assign jc52b50 = ls35502; -assign fp8bd30 = ~vi7ce5c & kfa4f8f; - -assign ks24554 = al4b56a | yk5c720; - - - -assign ri4632 = cz418c8 & ir90977 & wwcb8e4 & gq3e3e7 & ~(hd9b63f | xj45cbf); - -always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin gdab323 <= 1'b0; zkd5664 <= 1'b0; mrcc8e0 <= 14'b0; ldd22e2 <= 14'b0; bn8b8b7 <= 14'b0; me5c5be <= 1'b0; ux8420 <= 1'b0; uvc64a4 <= 1'b0; ps79d12 <= 1'b0; wwce893 <= 1'b0; bl74498 <= 1'b0; hqa24c6 <= 1'b0; ir23192 <= 1'b0; fa58e7c <= 1'b0; je2f3a2 <= 1'b0; psf1bd5 <= 14'd0; ux2382f <= 14'd0; bldd558 <= 9'd0; ykeaac7 <= 1'b0; wl12632 <= 1'b0; lqfe289 <= 1'b0; end else if (rxmac_clk_en) begin ykeaac7 <= mt29d2e & ~czf29dc; if (mt29d2e && !czf29dc) bldd558 <= ayf0d93; ir23192 <= fp8bd30; fa58e7c <= wl3971c; if (czf8071) je2f3a2 <= czf8071; else if (ls35502 && !czf8071) je2f3a2 <= 1'b0; else if (zzb0517) je2f3a2 <= 1'b0; else je2f3a2 <= qifcdb; hqa24c6 <= ~vk1f9b; if (rvba149 & zm1b29c) bl74498 <= rvba149; else if (mt29d2e) bl74498 <= 1'b0; else bl74498 <= hd9b63f; if (zke407e) wwce893 <= zke407e; else if (mt29d2e) wwce893 <= 1'b0; else wwce893 <= xjf36c7; lqfe289 <= al4b56a; if (do83310) ps79d12 <= kf8527a; if (yzab1cf) wl12632 <= ayd4a7c; uvc64a4 <= al4b56a | (yk5c720 & zm1b29c); mrcc8e0 <= tj137d0; zkd5664 <= dze3901; gdab323 <= vidf437; if (zxcd67f && !hqe313) ux8420 <= ls1bd49; me5c5be <= hqe313; if (zxcd67f && !hqe313) ldd22e2 <= pff9acf; if (hqe313) begin bn8b8b7 <= pff9acf + 14'd1; end else bn8b8b7 <= 14'd0; if (tw8c4df && xl84bbc && su49641) ux2382f <= fc83768 + 14'd1; if (pf7189b && !xl84bbc && an8a74) psf1bd5 <= hofec14 + 14'd1; else if (jpf60a2) psf1bd5 <= 14'd0; end -end - - - -assign yzab1cf = jpf60a2; - - -assign lf32525 = gd3cc84 ? (ks97e6b > (ho6322e + 14'd4)) : ks97e6b > ho6322e; -assign mg9292f = (ks97e6b < 14'd64); -assign hd94979 = wwff00e; - -assign gd1df20 = (ks97e6b[6:0] != 7'd64); -assign icef904 = (hd3212e != qvbe0dd); -assign oha4bce = vx1c80f ? 1'b0 : ux7990 | xl84bbc ? hd9be86 : hq25de7 ? 1'b0 : fca2f83; - -assign zm25e74 = ~(hd9b63f | xj45cbf | ng203f3); -assign vx33b0[31] = zm145f0; -assign vx33b0[30] = vx1c80f; -assign vx33b0[29] = fn7e6d8; -assign vx33b0[28] = nrd8ff0; -assign vx33b0[27] = xjf36c7; -assign vx33b0[26] = qifcdb; -assign vx33b0[25] = xj45cbf; -assign vx33b0[24] = ng203f3; -assign vx33b0[23] = vk1f9b; -assign vx33b0[22] = th4f83c; -assign vx33b0[21] = by7c1e6; -assign vx33b0[20] = ned0a4f; -assign vx33b0[19] = uk2ef3a; -assign vx33b0[18] = ux7990; -assign vx33b0[17] = ir90977; -assign vx33b0[16] = gd3cc84; -assign vx33b0[15:14] = 2'b00; -assign vx33b0[13:0] = ks97e6b; - -assign jr32885[0] = ir90977; -assign jr32885[1] = xj45cbf; -assign jr32885[2] = hd9b63f; -assign jr32885[3] = zm145f0; -assign jr32885[4] = vx1c80f; -assign jr32885[5] = fn7e6d8; -assign jr32885[6] = th4f83c; -assign jr32885[7] = by7c1e6; -assign jr32885[8] = gd3cc84; - -always@* begin zm1b29c<=mef0f02[0];ic77429<=mef0f02[1];rvba149<=mef0f02[2];ned0a4f<=mef0f02[3];kf8527a<=mef0f02[4];je896ad<={bn1ce70>>1,mef0f02[5]};al4b56a<=mef0f02[6];qt7a94f<=mef0f02[7];ayd4a7c<=mef0f02[8];lfa53e0<=mef0f02[9];gd29f07<=mef0f02[10];th4f83c<=mef0f02[11];by7c1e6<=mef0f02[12];kqe0f32<=mef0f02[13];ux7990<=mef0f02[14];gd3cc84<=mef0f02[15];hd3212e<={dm579a3>>1,mef0f02[16]};ir90977<=mef0f02[17];xl84bbc<=mef0f02[18];hq25de7<=mef0f02[19];uk2ef3a<=mef0f02[20];cm779d1<=mef0f02[21];qte7441<={lde68d9>>1,mef0f02[22]};pu3a20c<=mef0f02[23];wwd1063<=mef0f02[24];gq88319<=mef0f02[25];cz418c8<=mef0f02[26];ho6322e<={ldcd808>>1,mef0f02[27]};xl19172<=mef0f02[28];vvc8b97<=mef0f02[29];xj45cbf<=mef0f02[30];qg72ff8<={je2fc44>>1,mef0f02[31]};wy97fc0<=mef0f02[32];jrbfe01<=mef0f02[33];wwff00e<=mef0f02[34];czf8071<=mef0f02[35];tuc038c<=mef0f02[36];xy1c62<=mef0f02[37];hqe313<=mef0f02[38];pf7189b<=mef0f02[39];tw8c4df<=mef0f02[40];tj137d0<={ui43be4>>1,mef0f02[41]};hd9be86<=mef0f02[42];vidf437<=mef0f02[43];rgd0dd1<={rge410b>>1,mef0f02[44]};pu86e8a<=mef0f02[45];tj37452<=mef0f02[46];bnba297<={sw216d2>>1,mef0f02[47]};osd14bf<=mef0f02[48];wl8a5f9<=mef0f02[49];ks97e6b<={ldd22e2>>1,mef0f02[50]};pff9acf<={bn8b8b7>>1,mef0f02[51]};zxcd67f<=mef0f02[52];zx6b3fe<=mef0f02[53];me59ff6<=mef0f02[54];facffb0<=mef0f02[55];hofec14<={psf1bd5>>1,mef0f02[56]};jpf60a2<=mef0f02[57];zzb0517<=mef0f02[58];qi828be<=mef0f02[59];zm145f0<=mef0f02[60];fca2f83<=mef0f02[61];qvbe0dd<={mrcc8e0>>1,mef0f02[62]};fc83768<={ux2382f>>1,mef0f02[63]};tw1bb43<=mef0f02[64];pfdda1b<=mef0f02[65];ened0de<=mef0f02[66];ea686f5<=mef0f02[67];ea437a9<=mef0f02[68];ls1bd49<=mef0f02[69];aydea4b<=mef0f02[70];wya92c8<={ngb200>>1,mef0f02[71]};su49641<=mef0f02[72];uv4b208<=mef0f02[73];me59045<=mef0f02[74];qt4114e<={vx33b0>>1,mef0f02[75]};an8a74<=mef0f02[76];ld453a5<=mef0f02[77];mt29d2e<=mef0f02[78];czf29dc<=mef0f02[79];pf74ba4<=mef0f02[80];vxa5d27<=mef0f02[81];rt749f1<={ym1f042>>1,mef0f02[82]};kfa4f8f<=mef0f02[83];vx27c7c<=mef0f02[84];gq3e3e7<=mef0f02[85];dmf1f39<=mef0f02[86];cb8f9cb<={ym10823>>1,mef0f02[87]};vi7ce5c<=mef0f02[88];do83310<=mef0f02[89];wl3971c<=mef0f02[90];wwcb8e4<=mef0f02[91];yk5c720<=mef0f02[92];dze3901<=mef0f02[93];vx1c80f<=mef0f02[94];zke407e<=mef0f02[95];ng203f3<=mef0f02[96];vk1f9b<=mef0f02[97];qifcdb<=mef0f02[98];fn7e6d8<=mef0f02[99];xjf36c7<=mef0f02[100];hd9b63f<=mef0f02[101];qgdb1fe<=mef0f02[102];nrd8ff0<=mef0f02[103];pfc7f86<=mef0f02[104];ri3fc36<=mef0f02[105];ayf0d93<={jr32885>>1,mef0f02[106]};do86c99<={vx9442e>>1,mef0f02[107]};an364ca<=mef0f02[108];dob2655<=mef0f02[109];ba932ab<=mef0f02[110];end -always@* begin ng1e1e0[2047]<=fa6c2d4;ng1e1e0[2046]<=pf616a3;ng1e1e0[2044]<=lsb51f;ng1e1e0[2040]<=vv5a8fb;ng1e1e0[2032]<=bn1ce70[0];ng1e1e0[2028]<=uvc64a4;ng1e1e0[2017]<=cb25ef;ng1e1e0[2008]<=lf32525;ng1e1e0[1988]<=vx33b0[0];ng1e1e0[1987]<=wl12f7d;ng1e1e0[1969]<=mg9292f;ng1e1e0[1928]<=iccec3e;ng1e1e0[1926]<=rva04bd;ng1e1e0[1891]<=hd94979;ng1e1e0[1809]<=rg761f0;ng1e1e0[1805]<=kf23e8c;ng1e1e0[1804]<=mg1550f;ng1e1e0[1803]<=yz172cd;ng1e1e0[1761]<=tuf111f;ng1e1e0[1748]<=gdab323;ng1e1e0[1734]<=oha4bce;ng1e1e0[1727]<=ym10823[0];ng1e1e0[1696]<=bn1c17d;ng1e1e0[1668]<=gd1df20;ng1e1e0[1633]<=do93194;ng1e1e0[1587]<=ps79d12;ng1e1e0[1571]<=lfb0f83;ng1e1e0[1562]<=gofa328;ng1e1e0[1560]<=hdaa879;ng1e1e0[1558]<=ignore_pkt;ng1e1e0[1555]<=zma2177;ng1e1e0[1550]<=dm579a3[0];ng1e1e0[1531]<=ri4632;ng1e1e0[1475]<=uk888fa;ng1e1e0[1464]<=bl7b98b;ng1e1e0[1448]<=mrcc8e0[0];ng1e1e0[1420]<=zm25e74;ng1e1e0[1406]<=vx84118;ng1e1e0[1345]<=yke0bef;ng1e1e0[1288]<=icef904;ng1e1e0[1287]<=fc2fbc1;ng1e1e0[1242]<=yx6f559;ng1e1e0[1218]<=gq98ca2;ng1e1e0[1131]<=yxf8210;ng1e1e0[1126]<=wwce893;ng1e1e0[1094]<=xw69ede;ng1e1e0[1076]<=zm8ca08;ng1e1e0[1072]<=en543cf;ng1e1e0[1069]<=qgcb360;ng1e1e0[1063]<=ie10bba;ng1e1e0[1056]<=ba2085b;ng1e1e0[1055]<=ykef059;ng1e1e0[1052]<=ec346cf;ng1e1e0[1028]<=ldd22e2[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[1014]<=ir23192;ng1e1e0[994]<=vv400ce;ng1e1e0[902]<=of447d1;ng1e1e0[901]<=lde68d9[0];ng1e1e0[880]<=je2fc44[0];ng1e1e0[874]<=zkd5664;ng1e1e0[863]<=jc42104;ng1e1e0[848]<=ux2382f[0];ng1e1e0[834]<=ui43be4[0];ng1e1e0[816]<=wl12632;ng1e1e0[793]<=je2f3a2;ng1e1e0[777]<=vx9442e[0];ng1e1e0[775]<=hq2af34;ng1e1e0[765]<=lqfe289;ng1e1e0[732]<=wj6023b;ng1e1e0[643]<=aa5f78;ng1e1e0[621]<=sw8deab;ng1e1e0[565]<=ym1f042[0];ng1e1e0[528]<=rge410b[0];ng1e1e0[527]<=me7de0b;ng1e1e0[514]<=en5b48b;ng1e1e0[497]<=fnc8019;ng1e1e0[450]<=ksbcd1b;ng1e1e0[437]<=gb7aacc;ng1e1e0[431]<=ux8420;ng1e1e0[417]<=al410ef;ng1e1e0[408]<=hqa24c6;ng1e1e0[388]<=jr32885[0];ng1e1e0[387]<=ep855e6;ng1e1e0[366]<=tu6c047;ng1e1e0[310]<=psf1bd5[0];ng1e1e0[282]<=uif07c1;ng1e1e0[257]<=jeb691;ng1e1e0[248]<=ic59003;ng1e1e0[225]<=rgc0518;ng1e1e0[215]<=mec1084;ng1e1e0[208]<=nt2821d;ng1e1e0[204]<=bl74498;ng1e1e0[193]<=jp50abc;ng1e1e0[183]<=ldcd808[0];ng1e1e0[155]<=fcb7c6f;ng1e1e0[141]<=sw3e0f8;ng1e1e0[128]<=sw216d2[0];ng1e1e0[124]<=ngb200[0];ng1e1e0[112]<=xy1b3c0;ng1e1e0[104]<=cz65043;ng1e1e0[96]<=uxa1e7d;ng1e1e0[91]<=go59b01;ng1e1e0[78]<=wl85dd0;ng1e1e0[77]<=zz16f8d;ng1e1e0[64]<=zm42da;ng1e1e0[62]<=ea782c8;ng1e1e0[56]<=eca3678;ng1e1e0[38]<=kde2df1;ng1e1e0[19]<=me5c5be;ng1e1e0[9]<=bn8b8b7[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[3]};rvba149<=mef0f02[4];ned0a4f<=mef0f02[5];kf8527a<=mef0f02[6];gb6abd3<={uv70d29>>1,mef0f02[7]};ntaf4ee<={hq8694d>>1,mef0f02[8]};czd3bb5<={ec34a6a>>1,mef0f02[9]};dmeed68<={lfa5351>>1,mef0f02[10]};dbb5a1a<={gd29a8f>>1,mef0f02[11]};go686bb<={rg4d47c>>1,mef0f02[12]};ie1aec9<={mr6a3e2>>1,mef0f02[13]};yzbb24e<={of51f14>>1,mef0f02[14]};gbc93ad<={sj8f8a4>>1,mef0f02[15]};ay49d6c<=mef0f02[16];kd4eb61<=mef0f02[17];ip75b0c<=mef0f02[18];qv39dc8<={ba25a85>>1,mef0f02[19]};gq88319<=mef0f02[20];cz418c8<=mef0f02[21];ho6322e<={ldcd808>>1,mef0f02[22]};xl19172<=mef0f02[23];vvc8b97<=mef0f02[24];wwde5f9<=mef0f02[25];wwd1063<=mef0f02[26];ym3e93a<={xw791a7>>1,mef0f02[27]};epa4e83<={me469d7>>1,mef0f02[28]};zz2741c<=mef0f02[29];je3a0e6<=mef0f02[30];byd0733<=mef0f02[31];vk8399b<=mef0f02[32];ph1ccda<=mef0f02[33];gd336b6<={qia590>>1,mef0f02[34]};bn9b5b5<=mef0f02[35];vidadae<=mef0f02[36];end6d73<=mef0f02[37];swb6b9d<=mef0f02[38];phb5ce8<=mef0f02[39];zk73a3c<={nr5a773>>1,mef0f02[40]};qte8f11<={uk9dcf5>>1,mef0f02[41]};yz3c462<={by73d42>>1,mef0f02[42]};ofe2314<=mef0f02[43];zm118a4<=mef0f02[44];ba8c522<=mef0f02[45];me62912<=mef0f02[46];ng14891<=mef0f02[47];kfa448a<=mef0f02[48];zz22455<=mef0f02[49];kf122ae<=mef0f02[50];nt91574<=mef0f02[51];oh8aba7<=mef0f02[52];pf55d3c<=mef0f02[53];anae9e6<=mef0f02[54];bl74f35<=mef0f02[55];lsa79af<=mef0f02[56];fne6bdd<={czfd46f>>1,mef0f02[57]};je35eef<=mef0f02[58];zzaf77b<=mef0f02[59];vvddef6<={mr6f821>>1,mef0f02[60]};ykef7b6<=mef0f02[61];hb7bdb0<=mef0f02[62];pff6c31<={sw82127>>1,mef0f02[63]};ntb0c71<={zz849c8>>1,mef0f02[64]};co31c7b<={nt27238>>1,mef0f02[65]};xj71ecf<={thc8e34>>1,mef0f02[66]};gd8f67f<=mef0f02[67];hb7b3fd<=mef0f02[68];facff7c<={ec34efc>>1,mef0f02[69]};end -always@* begin ng1e1e0[2047]<=ks10d54;ng1e1e0[2046]<=fa6c2d4;ng1e1e0[2044]<=ls86aa0[0];ng1e1e0[2041]<=pf616a3;ng1e1e0[2035]<=lsb51f;ng1e1e0[2029]<=czfd46f[0];ng1e1e0[2022]<=vv5a8fb;ng1e1e0[2011]<=suea37c;ng1e1e0[1996]<=uv70d29[0];ng1e1e0[1974]<=kd51be0;ng1e1e0[1945]<=hq8694d[0];ng1e1e0[1943]<=rib86e8;ng1e1e0[1922]<=rx_fifo_full;ng1e1e0[1901]<=mr6f821[0];ng1e1e0[1842]<=ec34a6a[0];ng1e1e0[1839]<=kdc3742;ng1e1e0[1797]<=ignore_pkt;ng1e1e0[1791]<=fa471a7;ng1e1e0[1778]<=ho425c3;ng1e1e0[1776]<=ldcd808[0];ng1e1e0[1759]<=zz849c8[0];ng1e1e0[1755]<=rg7c10d;ng1e1e0[1637]<=lfa5351[0];ng1e1e0[1631]<=hq1ba15;ng1e1e0[1622]<=of51f14[0];ng1e1e0[1546]<=xw791a7[0];ng1e1e0[1535]<=vx38d3b;ng1e1e0[1531]<=ym157ea;ng1e1e0[1509]<=kf12e1b;ng1e1e0[1504]<=tu6c047;ng1e1e0[1471]<=nt27238[0];ng1e1e0[1468]<=qgcb360;ng1e1e0[1463]<=ice086a;ng1e1e0[1391]<=vk14915;ng1e1e0[1312]<=qia590[0];ng1e1e0[1226]<=gd29a8f[0];ng1e1e0[1215]<=xjdd0ab;ng1e1e0[1197]<=sj8f8a4[0];ng1e1e0[1153]<=ri9640b;ng1e1e0[1044]<=me469d7[0];ng1e1e0[1037]<=tj8169d;ng1e1e0[1023]<=reset_n;ng1e1e0[1022]<=ec34efc[0];ng1e1e0[1014]<=yzabf51;ng1e1e0[971]<=ou970dd;ng1e1e0[961]<=wj6023b;ng1e1e0[895]<=thc8e34[0];ng1e1e0[889]<=baa84b8;ng1e1e0[888]<=go59b01;ng1e1e0[879]<=sw82127[0];ng1e1e0[811]<=mr6a3e2[0];ng1e1e0[765]<=dm42afd;ng1e1e0[734]<=ba25a85[0];ng1e1e0[695]<=ale2922;ng1e1e0[656]<=ngb8296;ng1e1e0[576]<=ho52c81;ng1e1e0[518]<=ux902d3;ng1e1e0[444]<=kqf5097;ng1e1e0[405]<=rg4d47c[0];ng1e1e0[382]<=uve855f;ng1e1e0[347]<=tu7c524;ng1e1e0[328]<=hbd7052;ng1e1e0[259]<=pub205a;ng1e1e0[222]<=jr9ea12;ng1e1e0[164]<=xy3ae0a;ng1e1e0[111]<=by73d42[0];ng1e1e0[82]<=ria75c1;ng1e1e0[55]<=uk9dcf5[0];ng1e1e0[41]<=sw34eb8;ng1e1e0[27]<=nr5a773[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};kd4e479<=mef0f02[2];kq723cd<=mef0f02[3];hd91e69<={gqb35c6>>1,mef0f02[4]};oh8f34e<={an9ae31>>1,mef0f02[5]};rg79a75<=mef0f02[6];pfcd3ab<={tu73a4e>>1,mef0f02[7]};end -always@* begin ng1e1e0[2047]<=ep29d6d[0];ng1e1e0[2046]<=aa82cd7;ng1e1e0[2044]<=db166b8;ng1e1e0[2040]<=gqb35c6[0];ng1e1e0[2033]<=an9ae31[0];ng1e1e0[2019]<=thd718d;ng1e1e0[1991]<=tu73a4e[0];ng1e1e0[1023]<=of653ad;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};wl9fec7<=mef0f02[1];dzd8f4b<=mef0f02[2];nrc7a5e<={vif4c35>>1,mef0f02[3]};db3d2f6<={zm3f362>>1,mef0f02[4]};dze97b6<={ps6c4ff>>1,mef0f02[5]};end -always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uv5e986;ng1e1e0[2044]<=vif4c35[0];ng1e1e0[2040]<=zm3f362[0];ng1e1e0[2032]<=ps6c4ff[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};ip6f847<=mef0f02[2];lq7c23d<=mef0f02[3];wl8f53<={cm531bb>>1,mef0f02[4]};bn3d4ea<={yxc6ec0>>1,mef0f02[5]};kqea756<=mef0f02[6];ww53ab0<=mef0f02[7];gq9d581<=mef0f02[8];qg56049<={bl7b7f8>>1,mef0f02[9]};vx81246<={icff1cb>>1,mef0f02[10]};ph9236<=mef0f02[11];end -always@* begin ng1e1e0[2047]<=ay625cf[0];ng1e1e0[2046]<=sj12e78;ng1e1e0[2044]<=aa973c5;ng1e1e0[2040]<=cm531bb[0];ng1e1e0[2033]<=yxc6ec0[0];ng1e1e0[2018]<=nt37604;ng1e1e0[1988]<=pfd813d;ng1e1e0[1929]<=hoc09ef;ng1e1e0[1811]<=bl7b7f8[0];ng1e1e0[1574]<=icff1cb[0];ng1e1e0[1101]<=uvf8e59;ng1e1e0[1023]<=xjec4b9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};tw25ed4<={kd4ec72>>1,mef0f02[8]};ng2f6a2<=mef0f02[9];xj7b512<=mef0f02[10];jcda897<=mef0f02[11];kqd44bb<=mef0f02[12];ir12eca<={jr94778>>1,mef0f02[13]};ym97655<=mef0f02[14];uxbb2a8<=mef0f02[15];jccaa2d<={ayef1cc>>1,mef0f02[16]};bl5516a<=mef0f02[17];vka8b57<=mef0f02[18];bn2d5d7<={gd3980f>>1,mef0f02[19]};ip6aebf<=mef0f02[20];lq575fd<=mef0f02[21];vxbafea<=mef0f02[22];rtd7f56<=mef0f02[23];vxbfab7<=mef0f02[24];qtfd5be<=mef0f02[25];ayeadf4<=mef0f02[26];ww53ab0<={pfd813d>>1,mef0f02[27]};gq9d581<={hoc09ef>>1,mef0f02[28]};cbbe84a<=mef0f02[29];tuf4254<=mef0f02[30];rv9515<={kdd9d10>>1,mef0f02[31]};gb54576<={pf74420>>1,mef0f02[32]};ou15dab<={gq10832>>1,mef0f02[33]};sjaed58<=mef0f02[34];ne76ac5<=mef0f02[35];bnb562a<=mef0f02[36];irab156<=mef0f02[37];ho58ab4<=mef0f02[38];rgc55a2<=mef0f02[39];hq2ad12<={hbe3c76>>1,mef0f02[40]};cm56893<={zm1e3b7>>1,mef0f02[41]};epb4499<=mef0f02[42];fca24cc<=mef0f02[43];gd12662<=mef0f02[44];fc93314<=mef0f02[45];xy998a2<=mef0f02[46];qtcc512<=mef0f02[47];ls144a1<={go782f6>>1,mef0f02[48]};xya250b<=mef0f02[49];ux1285a<=mef0f02[50];tj942d5<=mef0f02[51];kfa16af<={gq15fa4>>1,mef0f02[52]};xyb57d<=mef0f02[53];nr5abeb<=mef0f02[54];rgd5f5f<={rgf483e>>1,mef0f02[55]};rvafafa<=mef0f02[56];ea7d7d7<=mef0f02[57];jcebeb8<=mef0f02[58];vv5f5c3<=mef0f02[59];ykfae1e<=mef0f02[60];pfd70f0<=mef0f02[61];zmb8786<=mef0f02[62];wjc3c32<=mef0f02[63];vk1e194<=mef0f02[64];ykf0ca2<={xj4aae6>>1,mef0f02[65]};ng86511<={jp55736>>1,mef0f02[66]};hd3288b<={irab9b7>>1,mef0f02[67]};fp9445e<=mef0f02[68];baa22f7<=mef0f02[69];zm117ba<=mef0f02[70];end -always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=yk775cd;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=vvd734e;ng1e1e0[2032]<=ukb9a76;ng1e1e0[2018]<=faf1dba;ng1e1e0[2017]<=nrcd3b1[0];ng1e1e0[1989]<=tj8edd3;ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1931]<=czd3c9f;ng1e1e0[1927]<=kd4ec72[0];ng1e1e0[1865]<=ayef1cc[0];ng1e1e0[1859]<=gq10832[0];ng1e1e0[1844]<=hdafd20;ng1e1e0[1815]<=fp9e4fd;ng1e1e0[1806]<=ho76394;ng1e1e0[1682]<=ui78e60;ng1e1e0[1674]<=qv90c78;ng1e1e0[1671]<=lf32197;ng1e1e0[1640]<=fn7e907;ng1e1e0[1582]<=czf27ee;ng1e1e0[1565]<=irb1ca3;ng1e1e0[1488]<=kdd9d10[0];ng1e1e0[1485]<=kf8057e;ng1e1e0[1326]<=gb6560e;ng1e1e0[1317]<=tucf141;ng1e1e0[1300]<=sj23348;ng1e1e0[1297]<=xj4aae6[0];ng1e1e0[1295]<=oh90cbf;ng1e1e0[1233]<=rgf483e[0];ng1e1e0[1210]<=hoc09ef[0];ng1e1e0[1189]<=cz4eb6c;ng1e1e0[1172]<=encc07d;ng1e1e0[1116]<=ld55e0b;ng1e1e0[1105]<=rv9bb69;ng1e1e0[1092]<=irab9b7[0];ng1e1e0[1087]<=ym97f1e;ng1e1e0[1082]<=tx_fifoavail;ng1e1e0[1023]<=gof5dd7;ng1e1e0[1009]<=zm1e3b7[0];ng1e1e0[932]<=sj1de39;ng1e1e0[929]<=pf74420[0];ng1e1e0[922]<=gq15fa4[0];ng1e1e0[837]<=xy20f9d;ng1e1e0[744]<=je1b674;ng1e1e0[742]<=lfb00af;ng1e1e0[663]<=ldecac1;ng1e1e0[648]<=mgad95;ng1e1e0[605]<=pfd813d[0];ng1e1e0[594]<=ng1f65;ng1e1e0[586]<=gd3980f[0];ng1e1e0[552]<=by69136;ng1e1e0[547]<=cb36f47;ng1e1e0[546]<=jp55736[0];ng1e1e0[543]<=ri865fc;ng1e1e0[504]<=hbe3c76[0];ng1e1e0[466]<=gqa3bc7;ng1e1e0[418]<=kfa41f3;ng1e1e0[372]<=mt236ce;ng1e1e0[371]<=rtf6015;ng1e1e0[331]<=ieb9e28;ng1e1e0[324]<=zx7e856;ng1e1e0[297]<=mr603ec;ng1e1e0[273]<=rte6de8;ng1e1e0[252]<=xjfc78e;ng1e1e0[233]<=jr94778[0];ng1e1e0[185]<=go782f6[0];ng1e1e0[162]<=qg6d3f4;ng1e1e0[136]<=kq5cdbd;ng1e1e0[126]<=zzbf8f1;ng1e1e0[116]<=os728ef;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[3]};ec31d79<=mef0f02[4];lf8ebc9<=mef0f02[5];dbaf275<={tj19519>>1,mef0f02[6]};ng2f6a2<=mef0f02[7];alc9d72<=mef0f02[8];kd4eb95<=mef0f02[9];ip75cac<=mef0f02[10];qvae565<=mef0f02[11];su72b2c<=mef0f02[12];oh95960<=mef0f02[13];qiacb04<=mef0f02[14];uv65820<=mef0f02[15];wl2c104<=mef0f02[16];uv60825<=mef0f02[17];vk412c<=mef0f02[18];ng20962<=mef0f02[19];ri4b12<=mef0f02[20];ls25893<=mef0f02[21];ay49c8f<={ep29d6d>>1,mef0f02[22]};an126a8<=mef0f02[23];je93544<=mef0f02[24];ep9aa22<=mef0f02[25];xwd5115<=mef0f02[26];pua88ab<=mef0f02[27];vx22ad4<={uv4b7df>>1,mef0f02[28]};gq156a7<=mef0f02[29];zx5a9cc<={fafbf6a>>1,mef0f02[30]};icd4e67<=mef0f02[31];vka7338<=mef0f02[32];ep399c2<=mef0f02[33];ofcce15<=mef0f02[34];qg670ad<=mef0f02[35];rv38568<=mef0f02[36];ldc2b46<=mef0f02[37];ks15a36<=mef0f02[38];lsad1b0<=mef0f02[39];ic68d83<=mef0f02[40];go46c18<=mef0f02[41];yz360c0<=mef0f02[42];phb0605<=mef0f02[43];pu8302e<=mef0f02[44];wl18173<=mef0f02[45];lqc0b9d<=mef0f02[46];ou5ceb<=mef0f02[47];mg2e759<=mef0f02[48];ne73ac8<=mef0f02[49];ym9d642<=mef0f02[50];byeb211<=mef0f02[51];jpc8451<={ww78015>>1,mef0f02[52]};zk4228e<=mef0f02[53];xy11473<=mef0f02[54];qv8a39b<=mef0f02[55];ip51cdd<=mef0f02[56];xl8e6ec<=mef0f02[57];lq73767<=mef0f02[58];ph9bb3b<=mef0f02[59];jpdd9df<=mef0f02[60];jpecefe<=mef0f02[61];os677f6<=mef0f02[62];end -always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=tx_sndpausreq;ng1e1e0[2044]<=tx_sndpaustim[0];ng1e1e0[2040]<=wyb3e52;ng1e1e0[2033]<=ux9f290;ng1e1e0[2019]<=tj19519[0];ng1e1e0[1991]<=ho76394;ng1e1e0[1934]<=by52133;ng1e1e0[1929]<=bydf8eb;ng1e1e0[1898]<=jc63c02;ng1e1e0[1821]<=bycf546;ng1e1e0[1810]<=blfc75b;ng1e1e0[1749]<=fc9c68c;ng1e1e0[1707]<=xyea19;ng1e1e0[1666]<=uv4b7df[0];ng1e1e0[1630]<=ng30125;ng1e1e0[1595]<=qg4671a;ng1e1e0[1572]<=wl1d6f7;ng1e1e0[1506]<=fc25558;ng1e1e0[1450]<=nga2e8e;ng1e1e0[1440]<=vid0974;ng1e1e0[1384]<=oh9a12e;ng1e1e0[1370]<=ep29d6d[0];ng1e1e0[1366]<=tx_discfrm;ng1e1e0[1284]<=of5befd;ng1e1e0[1212]<=an8092a;ng1e1e0[1202]<=vvecbf5;ng1e1e0[1174]<=wj44d9d;ng1e1e0[1170]<=aa8748b;ng1e1e0[1142]<=ep338d1;ng1e1e0[1125]<=gq988c6;ng1e1e0[1097]<=dz55311;ng1e1e0[1041]<=shed49d;ng1e1e0[1023]<=gof5dd7;ng1e1e0[964]<=je2aac3;ng1e1e0[949]<=hq8c780;ng1e1e0[853]<=qi2b075;ng1e1e0[833]<=ps5d2df;ng1e1e0[815]<=ofc6024;ng1e1e0[753]<=sw24aab;ng1e1e0[720]<=xjc8b1c;ng1e1e0[714]<=icced42;ng1e1e0[692]<=hd13425;ng1e1e0[685]<=mec1d43;ng1e1e0[601]<=bl4f4d7;ng1e1e0[587]<=ui67dfc;ng1e1e0[585]<=je35187;ng1e1e0[562]<=db13118;ng1e1e0[520]<=fafbf6a[0];ng1e1e0[474]<=hbe3463;ng1e1e0[407]<=an18c04;ng1e1e0[376]<=fc4955;ng1e1e0[357]<=yma3c6e;ng1e1e0[300]<=ww6d020;ng1e1e0[293]<=gb5efc8;ng1e1e0[292]<=ww78015[0];ng1e1e0[281]<=yk62623;ng1e1e0[237]<=uk1a31e;ng1e1e0[203]<=oh23180;ng1e1e0[146]<=ww4c478;ng1e1e0[140]<=mred898;ng1e1e0[70]<=qi9db13;ng1e1e0[35]<=of6a4ed;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[2]};je3a537<={xl285a7>>1,mef0f02[3]};dzd29bb<={by42d3f>>1,mef0f02[4]};ww53ab0<=mef0f02[5];gq9d581<=mef0f02[6];jr377f1<=mef0f02[7];end -always@* begin ng1e1e0[2047]<=ls1fac;ng1e1e0[2046]<=oufd63[0];ng1e1e0[2044]<=xl285a7[0];ng1e1e0[2040]<=by42d3f[0];ng1e1e0[2033]<=pfd813d;ng1e1e0[2019]<=hoc09ef;ng1e1e0[1990]<=vk3f5eb;ng1e1e0[1023]<=yz803f5;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};ipd346d<=mef0f02[2];wl9a36c<=mef0f02[3];god1b64<=mef0f02[4];vk412c<=mef0f02[5];dm6c808<={ym9de6f>>1,mef0f02[6]};hq20217<={ps79bc0>>1,mef0f02[7]};ux85da<={cz6f01f>>1,mef0f02[8]};wl176a2<={fac07e0>>1,mef0f02[9]};neda8a5<={gq1f816>>1,mef0f02[10]};lsa2959<={sue058e>>1,mef0f02[11]};zza565a<={fp1638c>>1,mef0f02[12]};me596b8<={ph8e335>>1,mef0f02[13]};xj5ae09<={ls8cd7f>>1,mef0f02[14]};vkb827e<={ri35fdb>>1,mef0f02[15]};lf9f90<={kd7f6df>>1,mef0f02[16]};th7e43e<={aydb7eb>>1,mef0f02[17]};kf90fbd<={jcdfac1>>1,mef0f02[18]};co3ef60<={vieb05c>>1,mef0f02[19]};dobd804<={uic1713>>1,mef0f02[20]};hbec023<=mef0f02[21];en6011f<=mef0f02[22];end -always@* begin ng1e1e0[2047]<=tx_fifodata[0];ng1e1e0[2046]<=tx_fifoeof;ng1e1e0[2044]<=tx_fifoempty;ng1e1e0[2040]<=tx_fifoctrl;ng1e1e0[2032]<=qi2b075;ng1e1e0[2017]<=ym9de6f[0];ng1e1e0[1987]<=ps79bc0[0];ng1e1e0[1927]<=cz6f01f[0];ng1e1e0[1865]<=kd7f6df[0];ng1e1e0[1806]<=fac07e0[0];ng1e1e0[1682]<=aydb7eb[0];ng1e1e0[1565]<=gq1f816[0];ng1e1e0[1317]<=jcdfac1[0];ng1e1e0[1172]<=uic1713[0];ng1e1e0[1082]<=sue058e[0];ng1e1e0[1023]<=tx_discfrm;ng1e1e0[932]<=ri35fdb[0];ng1e1e0[594]<=su5c4c2;ng1e1e0[586]<=vieb05c[0];ng1e1e0[466]<=ls8cd7f[0];ng1e1e0[297]<=fcb898;ng1e1e0[233]<=ph8e335[0];ng1e1e0[116]<=fp1638c[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[5]};cm5681e<={vvf96fb>>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};al7a68d<={tx_fifodata>>1,mef0f02[8]};ipd346d<=mef0f02[9];wl9a36c<=mef0f02[10];jcda897<=mef0f02[11];ay463af<={tx_sndpaustim>>1,mef0f02[12]};end918e<=mef0f02[13];god1b64<=mef0f02[14];ipd9356<=mef0f02[15];ps4d5ad<={cb90622>>1,mef0f02[16]};ipe2514<=mef0f02[17];ux3c4a2<=mef0f02[18];tw25ed4<={kd4ec72>>1,mef0f02[19]};jccaa2d<={ayef1cc>>1,mef0f02[20]};bn2d5d7<={gd3980f>>1,mef0f02[21]};ip6aebf<=mef0f02[22];dbaf275<={tj19519>>1,mef0f02[23]};ir12eca<={jr94778>>1,mef0f02[24]};ay49c8f<={ep29d6d>>1,mef0f02[25]};kd4eb95<=mef0f02[26];lf81c3e<=mef0f02[27];al70fbb<={nr5a6ca>>1,mef0f02[28]};qi3eee8<={tj9b2b4>>1,mef0f02[29]};end -always@* begin ng1e1e0[2047]<=gof5dd7;ng1e1e0[2046]<=anaeeb9;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=yk775cd;ng1e1e0[2032]<=vk3f2df[0];ng1e1e0[2017]<=vvf96fb[0];ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1926]<=tx_fifodata[0];ng1e1e0[1804]<=tx_fifoeof;ng1e1e0[1803]<=tj19519[0];ng1e1e0[1560]<=tx_fifoempty;ng1e1e0[1558]<=jr94778[0];ng1e1e0[1550]<=cb90622[0];ng1e1e0[1072]<=tx_fifoavail;ng1e1e0[1069]<=ep29d6d[0];ng1e1e0[1052]<=ukb9a76;ng1e1e0[1023]<=ir3994e;ng1e1e0[901]<=encc07d;ng1e1e0[775]<=zk520c4;ng1e1e0[732]<=tj9b2b4[0];ng1e1e0[450]<=gd3980f[0];ng1e1e0[387]<=tx_fifoctrl;ng1e1e0[366]<=nr5a6ca[0];ng1e1e0[225]<=ayef1cc[0];ng1e1e0[193]<=tx_sndpausreq;ng1e1e0[183]<=sh7aa33;ng1e1e0[112]<=kd4ec72[0];ng1e1e0[96]<=tx_sndpaustim[0];ng1e1e0[91]<=bycf546;ng1e1e0[56]<=vvd734e;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};go781e5<={hdatain>>1,mef0f02[1]};zkc0f28<=mef0f02[2];yz7943<=mef0f02[3];mt3ca1c<=mef0f02[4];yke50e5<=mef0f02[5];cm4394f<={ene2fd7>>1,mef0f02[6]};tj1ca78<=mef0f02[7];ir29e31<={bldd558>>1,mef0f02[8]};jp4f18c<=mef0f02[9];cm78c67<=mef0f02[10];yxc6339<=mef0f02[11];ou319cd<=mef0f02[12];ls8ce69<=mef0f02[13];su6734b<=mef0f02[14];fncd2c5<={kdd3961>>1,mef0f02[15]};wj4b173<={cme586a>>1,mef0f02[16]};lqc5cea<={nr61a85>>1,mef0f02[17]};dm73a98<={uv6a174>>1,mef0f02[18]};wy9d4c2<=mef0f02[19];ww53088<={fn4f950>>1,mef0f02[20]};jpc2201<={cme5433>>1,mef0f02[21]};ec8807b<={hb50cca>>1,mef0f02[22]};ba1ec6<={gd332b3>>1,mef0f02[23]};dz7b199<={jccaceb>>1,mef0f02[24]};hbd8ccf<={yk5675a>>1,mef0f02[25]};shc667e<=mef0f02[26];hq99fad<={jceb401>>1,mef0f02[27]};nr7eb52<={tud0056>>1,mef0f02[28]};twad4b1<={do159c>>1,mef0f02[29]};ps52c5c<={os56710>>1,mef0f02[30]};irb171a<={xy9c400>>1,mef0f02[31]};ea5c6a6<={uk1001c>>1,mef0f02[32]};ie1a98e<={ou70c>>1,mef0f02[33]};yma6388<={nt1c306>>1,mef0f02[34]};aa31c40<=mef0f02[35];fp8e201<=mef0f02[36];qi8807e<={db6eb4>>1,mef0f02[37]};pu1f86<={ntbad37>>1,mef0f02[38]};ld7e198<={uxb4df5>>1,mef0f02[39]};ba86639<={tj37d69>>1,mef0f02[40]};ks98e5d<={wwf5a74>>1,mef0f02[41]};mt39747<={by69d0b>>1,mef0f02[42]};jc5d1e0<={nr742d4>>1,mef0f02[43]};ne4781c<={vkb535>>1,mef0f02[44]};cb3c0e2<={xj5a9ab>>1,mef0f02[45]};lf38a1<={wya6af8>>1,mef0f02[46]};she2877<={qvabe0a>>1,mef0f02[47]};je143bd<=mef0f02[48];ira1deb<=mef0f02[49];doef5c<=mef0f02[50];pubd710<={jp55d00>>1,mef0f02[51]};tueb882<=mef0f02[52];ui5c413<=mef0f02[53];end -always@* begin ng1e1e0[2047]<=hdatain[0];ng1e1e0[2046]<=hread_n;ng1e1e0[2044]<=hwrite_n;ng1e1e0[2040]<=hcs_n;ng1e1e0[2032]<=aye5ebc;ng1e1e0[2016]<=ene2fd7[0];ng1e1e0[1985]<=cb17ebd;ng1e1e0[1925]<=wwf5a74[0];ng1e1e0[1922]<=bldd558[0];ng1e1e0[1802]<=by69d0b[0];ng1e1e0[1796]<=ykeaac7;ng1e1e0[1556]<=nr742d4[0];ng1e1e0[1544]<=gq3baab;ng1e1e0[1505]<=uxb4df5[0];ng1e1e0[1324]<=gbf82ae;ng1e1e0[1316]<=jceb401[0];ng1e1e0[1200]<=jp55d00[0];ng1e1e0[1169]<=do159c[0];ng1e1e0[1163]<=uk1001c[0];ng1e1e0[1118]<=rge1837;ng1e1e0[1106]<=gd332b3[0];ng1e1e0[1065]<=vkb535[0];ng1e1e0[1041]<=nr61a85[0];ng1e1e0[1040]<=xw734fa;ng1e1e0[1023]<=haddr[0];ng1e1e0[962]<=tj37d69[0];ng1e1e0[752]<=ntbad37[0];ng1e1e0[707]<=hb74035;ng1e1e0[662]<=zx5f055;ng1e1e0[658]<=swb3ad0;ng1e1e0[600]<=ykc1574;ng1e1e0[584]<=tud0056[0];ng1e1e0[581]<=xy9c400[0];ng1e1e0[559]<=nt1c306[0];ng1e1e0[553]<=hb50cca[0];ng1e1e0[520]<=cme586a[0];ng1e1e0[376]<=db6eb4[0];ng1e1e0[353]<=epae806;ng1e1e0[331]<=qvabe0a[0];ng1e1e0[329]<=yk5675a[0];ng1e1e0[290]<=os56710[0];ng1e1e0[279]<=ou70c[0];ng1e1e0[276]<=cme5433[0];ng1e1e0[260]<=kdd3961[0];ng1e1e0[188]<=zzc1ba;ng1e1e0[165]<=wya6af8[0];ng1e1e0[164]<=jccaceb[0];ng1e1e0[138]<=fn4f950[0];ng1e1e0[130]<=qv9f4e5;ng1e1e0[82]<=xj5a9ab[0];ng1e1e0[69]<=pu353e5;ng1e1e0[65]<=kdd3e9c;ng1e1e0[34]<=uv6a174[0];ng1e1e0[32]<=gd9a7d3;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};ho5da61<={kdc64dc>>1,mef0f02[1]};shed30a<=mef0f02[2];ne69855<=mef0f02[3];ui4c2aa<=mef0f02[4];ecaa87<={iccb7a2>>1,mef0f02[5]};phaa1c7<={kqde88d>>1,mef0f02[6]};ie871f6<={vka234a>>1,mef0f02[7]};fnc7d8f<={gq8d292>>1,mef0f02[8]};nrf63f0<={jp4a483>>1,mef0f02[9]};kf8fc3d<={gq920fa>>1,mef0f02[10]};ayf0f67<={je83e85>>1,mef0f02[11]};tj3d9c8<={qgfa150>>1,mef0f02[12]};ic6723e<={yz8540a>>1,mef0f02[13]};ldc8f84<={hb502a2>>1,mef0f02[14]};tu47c27<=mef0f02[15];wy3e13a<=mef0f02[16];ayf09d1<=mef0f02[17];fp84e89<=mef0f02[18];vx2744f<=mef0f02[19];end -always@* begin ng1e1e0[2047]<=kdc64dc[0];ng1e1e0[2046]<=xy9372f;ng1e1e0[2044]<=mdi;ng1e1e0[2040]<=lf2de5b;ng1e1e0[2032]<=iccb7a2[0];ng1e1e0[2017]<=kqde88d[0];ng1e1e0[1987]<=vka234a[0];ng1e1e0[1926]<=gq8d292[0];ng1e1e0[1804]<=jp4a483[0];ng1e1e0[1614]<=wya8be;ng1e1e0[1561]<=gq920fa[0];ng1e1e0[1180]<=al545f0;ng1e1e0[1074]<=je83e85[0];ng1e1e0[1023]<=gd18c9b[0];ng1e1e0[807]<=tj81517;ng1e1e0[625]<=wl17c2b;ng1e1e0[403]<=hb502a2[0];ng1e1e0[312]<=nga2f85;ng1e1e0[201]<=yz8540a[0];ng1e1e0[100]<=qgfa150[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};hbc2a27<=mef0f02[1];ec1513e<=mef0f02[2];twa89f1<=mef0f02[3];sh44f8a<=mef0f02[4];vx27c55<=mef0f02[5];gq3e2af<=mef0f02[6];dmf1579<=mef0f02[7];yz8abca<=mef0f02[8];rt55e54<={rxd_pos>>1,mef0f02[9]};rvaf2a6<={rxd_neg>>1,mef0f02[10]};by79536<=mef0f02[11];lqca9b2<=mef0f02[12];qt54d92<=mef0f02[13];gqa6c94<=mef0f02[14];sj364a1<=mef0f02[15];rib250d<=mef0f02[16];ie9286b<=mef0f02[17];bn94359<=mef0f02[18];wla1acf<=mef0f02[19];mtd67c<=mef0f02[20];me59f26<={pf748cc>>1,mef0f02[21]};tu7c982<={an2333d>>1,mef0f02[22]};qv2609a<={kdccf66>>1,mef0f02[23]};ou826a2<={dm66a7e>>1,mef0f02[24]};an9a88e<={uka9f9a>>1,mef0f02[25]};qgd4475<=mef0f02[26];lsa23a9<=mef0f02[27];ba11d4a<=mef0f02[28];tj8ea52<=mef0f02[29];cz75296<=mef0f02[30];oua94b4<=mef0f02[31];jp4a5a1<=mef0f02[32];dm52d0f<=mef0f02[33];ls9687b<=mef0f02[34];yzb43db<=mef0f02[35];swf6e4<={hoc0bc3>>1,mef0f02[36]};zx7b721<=mef0f02[37];ykdb90f<=mef0f02[38];czdc879<=mef0f02[39];dme43cc<=mef0f02[40];sw21e63<=mef0f02[41];ecf318<=mef0f02[42];ps798c1<=mef0f02[43];yxcc60b<=mef0f02[44];ir182e2<={xy2aaf4>>1,mef0f02[45]};cmc1715<=mef0f02[46];kq5c542<={sh5e8fd>>1,mef0f02[47]};uve2a11<={faf47ed>>1,mef0f02[48]};ym1508d<={mga3f6a>>1,mef0f02[49]};xya8469<=mef0f02[50];by4234b<=mef0f02[51];ng11a5b<=mef0f02[52];ie8d2da<=mef0f02[53];rg696d0<=mef0f02[54];gb4b683<=mef0f02[55];gb5b41d<=mef0f02[56];jcda0ec<=mef0f02[57];hod0762<=mef0f02[58];end -always@* begin ng1e1e0[2047]<=zx6e28f;ng1e1e0[2046]<=pf7147e;ng1e1e0[2044]<=ned0632;ng1e1e0[2040]<=kq53683;ng1e1e0[2032]<=rx_dv_pos;ng1e1e0[2016]<=rx_dv_neg;ng1e1e0[1985]<=rx_er_pos;ng1e1e0[1922]<=rx_er_neg;ng1e1e0[1867]<=tu693a4;ng1e1e0[1804]<=sh5e8fd[0];ng1e1e0[1797]<=rxd_pos[0];ng1e1e0[1761]<=th50aab;ng1e1e0[1686]<=ui49d23;ng1e1e0[1623]<=mr5136c;ng1e1e0[1561]<=faf47ed[0];ng1e1e0[1558]<=wl9a1bf;ng1e1e0[1547]<=rxd_neg[0];ng1e1e0[1542]<=hoc0bc3[0];ng1e1e0[1490]<=nr74349;ng1e1e0[1475]<=xy2aaf4[0];ng1e1e0[1413]<=pf7e686;ng1e1e0[1409]<=xla5605;ng1e1e0[1400]<=xw6cad8;ng1e1e0[1324]<=pf748cc[0];ng1e1e0[1200]<=kdccf66[0];ng1e1e0[1199]<=fc89b65;ng1e1e0[1074]<=mga3f6a[0];ng1e1e0[1068]<=ng86fe2;ng1e1e0[1047]<=qv9f880;ng1e1e0[1037]<=ie5e1b;ng1e1e0[1023]<=fncdc51[0];ng1e1e0[933]<=ana1a4e;ng1e1e0[902]<=dz557a3;ng1e1e0[880]<=byca155;ng1e1e0[811]<=cz6a26d;ng1e1e0[779]<=zxf3437;ng1e1e0[771]<=wy2b02f;ng1e1e0[745]<=ie2e869;ng1e1e0[706]<=uka9f9a[0];ng1e1e0[704]<=ieb6958;ng1e1e0[700]<=kq6d95b;ng1e1e0[600]<=an2333d[0];ng1e1e0[440]<=yxd942a;ng1e1e0[405]<=kded44d;ng1e1e0[372]<=uk5d0d;ng1e1e0[353]<=dm66a7e[0];ng1e1e0[352]<=ymb6d2b;ng1e1e0[350]<=xw4db2b;ng1e1e0[220]<=ls1b285;ng1e1e0[202]<=kdfda89;ng1e1e0[186]<=cb80ba1;ng1e1e0[176]<=vk96da5;ng1e1e0[110]<=enc3650;ng1e1e0[101]<=mg1fb51;ng1e1e0[93]<=kde202e;ng1e1e0[88]<=db37f12;ng1e1e0[55]<=ay786ca;ng1e1e0[46]<=rtfc405;ng1e1e0[27]<=ri2f0d9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};go781e5<={hdatain>>1,mef0f02[2]};mt3ca1c<=mef0f02[3];yz7943<=mef0f02[4];zkc0f28<=mef0f02[5];al7a68d<={tx_fifodata>>1,mef0f02[6]};jcda897<=mef0f02[7];ipd346d<=mef0f02[8];wl9a36c<=mef0f02[9];ay463af<={tx_sndpaustim>>1,mef0f02[10]};end918e<=mef0f02[11];god1b64<=mef0f02[12];wwde5f9<=mef0f02[13];wwd1063<=mef0f02[14];ks9259a<={ie2197a>>1,mef0f02[15]};ks92cd0<=mef0f02[16];pu96681<=mef0f02[17];ir29e31<={bldd558>>1,mef0f02[18]};jp4f18c<=mef0f02[19];vid028c<={ned0f15>>1,mef0f02[20]};bn81463<=mef0f02[21];iea31e<=mef0f02[22];wj518f1<={mre2a84>>1,mef0f02[23]};do8c78c<=mef0f02[24];dm63c62<=mef0f02[25];tw1e313<=mef0f02[26];jcf189a<=mef0f02[27];xy8c4d3<=mef0f02[28];go6269a<={ep29dbb>>1,mef0f02[29]};ph134d0<=mef0f02[30];an9a686<=mef0f02[31];ofd3434<=mef0f02[32];sj9a1a4<=mef0f02[33];byd0d24<=mef0f02[34];ri86922<=mef0f02[35];gq34912<=mef0f02[36];ana4891<=mef0f02[37];qi2448c<=mef0f02[38];vx22461<={xwe47ba>>1,mef0f02[39]};ep1230e<={yz23dd3>>1,mef0f02[40]};rv91874<={fc1ee9d>>1,mef0f02[41]};pu8c3a6<={gbf74eb>>1,mef0f02[42]};xj61d32<={bnba75d>>1,mef0f02[43]};twe996<={qtd3aef>>1,mef0f02[44]};dz74cb2<={ks9d77d>>1,mef0f02[45]};aaa6597<={tuebbe9>>1,mef0f02[46]};tj32cb8<={vi5df4b>>1,mef0f02[47]};vk965c6<={ykefa5a>>1,mef0f02[48]};vkb2e32<={ic7d2d1>>1,mef0f02[49]};ks97192<={rte9688>>1,mef0f02[50]};lsb8c90<={gb4b447>>1,mef0f02[51]};shc6483<=mef0f02[52];vx3241d<={qgd11ee>>1,mef0f02[53]};ou920ef<=mef0f02[54];sj90778<=mef0f02[55];ba83bc5<=mef0f02[56];kf1de2a<=mef0f02[57];osef154<=mef0f02[58];cm78aa0<=mef0f02[59];xwc5501<=mef0f02[60];do2a80a<=mef0f02[61];yx54053<={hq965a2>>1,mef0f02[62]};zza029d<={ngb2d12>>1,mef0f02[63]};ng14ef<=mef0f02[64];aaa77a<=mef0f02[65];ic53bd1<=mef0f02[66];ym9de89<=mef0f02[67];wwef448<={ou92714>>1,mef0f02[68]};qt7a240<={ri938a0>>1,mef0f02[69]};end -always@* begin ng1e1e0[2047]<=haddr[0];ng1e1e0[2046]<=hdatain[0];ng1e1e0[2044]<=hcs_n;ng1e1e0[2040]<=hwrite_n;ng1e1e0[2033]<=hread_n;ng1e1e0[2019]<=tx_fifodata[0];ng1e1e0[1994]<=gbf74eb[0];ng1e1e0[1990]<=tx_fifoavail;ng1e1e0[1981]<=tj84a76;ng1e1e0[1965]<=lsb7722;ng1e1e0[1940]<=bnba75d[0];ng1e1e0[1939]<=bldd558[0];ng1e1e0[1933]<=tx_fifoeof;ng1e1e0[1914]<=ba253b7;ng1e1e0[1883]<=ohbb913;ng1e1e0[1832]<=qtd3aef[0];ng1e1e0[1831]<=ykeaac7;ng1e1e0[1819]<=tx_fifoempty;ng1e1e0[1785]<=xwe47ba[0];ng1e1e0[1781]<=ep29dbb[0];ng1e1e0[1778]<=ie2197a[0];ng1e1e0[1740]<=hoee257;ng1e1e0[1719]<=mrdc89c;ng1e1e0[1634]<=mrd6596;ng1e1e0[1616]<=ks9d77d[0];ng1e1e0[1615]<=ned0f15[0];ng1e1e0[1591]<=tx_sndpaustim[0];ng1e1e0[1579]<=zm96892;ng1e1e0[1522]<=yz23dd3[0];ng1e1e0[1515]<=cz4eddc;ng1e1e0[1508]<=fpcbd0;ng1e1e0[1470]<=db1391e;ng1e1e0[1432]<=bl712ba;ng1e1e0[1406]<=ri938a0[0];ng1e1e0[1391]<=fae44e4;ng1e1e0[1286]<=ic7d2d1[0];ng1e1e0[1271]<=mg15425;ng1e1e0[1221]<=bab2cb4;ng1e1e0[1184]<=tuebbe9[0];ng1e1e0[1182]<=ie878aa;ng1e1e0[1135]<=tx_sndpausreq;ng1e1e0[1111]<=gdb4493;ng1e1e0[1051]<=gb4b447[0];ng1e1e0[1023]<=reset_n;ng1e1e0[997]<=fc1ee9d[0];ng1e1e0[990]<=bl5094e;ng1e1e0[982]<=vi76ee4;ng1e1e0[969]<=yx65e87;ng1e1e0[892]<=ls9c8f7;ng1e1e0[889]<=ignore_pkt;ng1e1e0[870]<=nt3dc4a;ng1e1e0[817]<=hq895d6;ng1e1e0[789]<=ngb2d12[0];ng1e1e0[735]<=lf22723;ng1e1e0[703]<=ou92714[0];ng1e1e0[643]<=ykefa5a[0];ng1e1e0[635]<=mre2a84[0];ng1e1e0[525]<=rte9688[0];ng1e1e0[495]<=hdaa129;ng1e1e0[444]<=rx_fifo_full;ng1e1e0[435]<=lq47b89;ng1e1e0[394]<=hq965a2[0];ng1e1e0[351]<=ep124e2;ng1e1e0[321]<=vi5df4b[0];ng1e1e0[317]<=oh3c550;ng1e1e0[222]<=tx_fifoctrl;ng1e1e0[217]<=ks88f71;ng1e1e0[175]<=vka249c;ng1e1e0[108]<=qgd11ee[0];ng1e1e0[54]<=hb5a23d;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f 0} { - for {set i 0} {$i < $argc} {incr i 2} { - set temp [lindex $argv $i] - set temp [string range $temp 1 end] - lappend argv_list $temp - lappend value_list [lindex $argv [expr $i+1]] - } - foreach argument $argv_list value $value_list { - switch $argument { - "cmd" {set Para(cmd) $value;} - } - } - } -} - -set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp2m/ipcores/tsmac34" -set Para(ModuleName) "tsmac34" -set Para(lib) "/home/greg/trispeed_mac_v3.4/lib" -set Para(CoreName) "Tri-Speed Ethernet MAC" -set Para(arch) "ep5m00" -set Para(family) "latticeecp2m" -set Para(Family) "latticeecp2m" -set Para(design) "VHDL" -set Para(install_dir) "/opt/lattice/diamond/1.1/bin/lin/../.." -set Para(Bin) "/opt/lattice/diamond/1.1/bin/lin" -set Para(SpeedGrade) "Para(spd)" -set Para(FPGAPath) "/opt/lattice/diamond/1.1/bin/lin/../../ispfpga/bin/sol" - -lappend auto_path "/home/greg/trispeed_mac_v3.4/gui" - -lappend auto_path "/home/greg/trispeed_mac_v3.4/script" -package require Core_Generate - -lappend auto_path "/opt/lattice/diamond/1.1/tcltk/lib/ipwidgets/ispipbuilder/../runproc" -package require runcmd - - -set Para(result) [GenerateCore] diff --git a/gbe2_ecp3/ipcores_ecp3/tsmac34/pmi_ram_dpEbnonessdn208256208256.ngo b/gbe2_ecp3/ipcores_ecp3/tsmac34/pmi_ram_dpEbnonessdn208256208256.ngo deleted file mode 100644 index f0262707dcf0e6f5204d798333f9126f2abbe3ed..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 11243 zcmai44Rl=9ab8Kb7_hO03qd%+?5UkZp%7LQwuNns{?_s$?c3Ggz9&rdXB$hg5sD2| zJ%pYmX^R3$DhMG03WyVzii8BE2U3@&uAJl;0j4OJB;u#Zx^6%OY6K)87YLni=I-k5 z+dYTP37Yxtcki8h?|XM<-gt64HCGWRuMFT)(eJITBZ;c8Nscorg=?Kv3 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All rights reserved. -//============================================================================= - -/* WARNING - Changes to this file should be performed by re-running IPexpress -or modifying the .LPC file and regenerating the core. Other changes may lead -to inconsistent simulation and/or implemenation results */ -module tsmac34 ( - // clock and reset - hclk, - txmac_clk, - rxmac_clk, - reset_n, - txmac_clk_en, - rxmac_clk_en, - - // Input signals to the GMII - rxd, - rx_dv, - rx_er, - col, - crs, - // Input signals to the CPU Interface - haddr, - hdatain, - hcs_n, - hwrite_n, - hread_n, - - // Input signals to the MII Management Interface - - // Input signals to the Tx MAC FIFO Interface - tx_fifodata, - tx_fifoavail, - tx_fifoeof, - tx_fifoempty, - tx_sndpaustim, - tx_sndpausreq, - tx_fifoctrl, - - // Input signals to the Rx MAC FIFO Interface - rx_fifo_full, - ignore_pkt, - - // Output signals from the GMII - txd, - tx_en, - tx_er, - - // Output signals from the CPU Interface - hdataout, - hdataout_en_n, - hready_n, - cpu_if_gbit_en, - - // Output signals from the MII Management Interface - - // Output signals from the Tx MAC FIFO Interface - tx_macread, - tx_discfrm, - tx_staten, - tx_statvec, - tx_done, - - // Output signals from the Rx MAC FIFO Interface - rx_fifo_error, - rx_stat_vector, - rx_dbout, - rx_write, - rx_stat_en, - rx_eof, - rx_error - ); - - // ------------------------- clock and reset inputs --------------------- - input hclk; // clock to the CPU I/F - input txmac_clk; // clock to the Tx MAC - input rxmac_clk; // clock to the RX MAC - input reset_n; // Global reset - input txmac_clk_en; // clock enable to the Tx MAC - input rxmac_clk_en; // clock enable to the RX MAC - - // ----------------------- Input signals to the GMII ------------------- - input [7:0] rxd; // Receive data - input rx_dv; // Receive data valid - input rx_er; // Receive data error - input col; // Collision detect - input crs; // Carrier Sense - // -------------------- Input signals to the CPU I/F ------------------- - input [7:0] haddr; // Address Bus - input [7:0] hdatain; // Input data Bus - input hcs_n; // Chip select - input hwrite_n; // Register write - input hread_n; // Register read - - // -------------------- Input signals to the MII I/F ------------------- - - - // ---------------- Input signals to the Tx MAC FIFO I/F --------------- - input [7:0] tx_fifodata; // Data Input from FIFO - input tx_fifoavail; // Data Available in FIFO - input tx_fifoeof; // End of Frame - input tx_fifoempty; // FIFO Empty - input [15:0] tx_sndpaustim; // Pause frame parameter - input tx_sndpausreq; // Transmit PAUSE frame - input tx_fifoctrl; // Control frame or Not - - // ---------------- Input signals to the Rx MAC FIFO I/F --------------- - input rx_fifo_full; // Receive FIFO Full - input ignore_pkt; // Ignore the frame - - // -------------------- Output signals from the GMII ----------------------- - output [7:0] txd; // Transmit data - output tx_en; // Transmit Enable - output tx_er; // Transmit Error - - // -------------------- Output signals from the CPU I/F ------------------- - output [7:0] hdataout; // Output data Bus - output hdataout_en_n; // Data Out Enable - output hready_n; // Ready signal - output cpu_if_gbit_en; // Gig or 10/100 mode - - // -------------------- Output signals from the MII I/F ------------------- - - - // ---------------- Output signals from the Tx MAC FIFO I/F --------------- - output tx_macread; // Read FIFO - output tx_discfrm; // Discard Frame - output tx_staten; // Status Vector Valid - output tx_done; // Transmit of Frame done - output [30:0] tx_statvec; // Tx Status Vector - - // ---------------- Output signals from the Rx MAC FIFO I/F --------------- - output rx_fifo_error; // FIFO full detected - output [31:0] rx_stat_vector; // Rx Status Vector - output [7:0] rx_dbout; // Data Output to FIFO - output rx_write; // Write FIFO - output rx_stat_en; // Status Vector Valid - output rx_eof; // Entire frame written - output rx_error; // Erroneous frame - - tsmac_core U1_LSC_ts_mac_core ( - - // clock and reset - .hclk(hclk), - .txmac_clk(txmac_clk), - .rxmac_clk(rxmac_clk), - .reset_n(reset_n), - .txmac_clk_en(txmac_clk_en), - .rxmac_clk_en(rxmac_clk_en), - - // Input signals to the GMII - .rxd(rxd), - .rx_dv(rx_dv), - .rx_er(rx_er), - .col(col), - .crs(crs), - // Input signals to the CPU Interface - .haddr(haddr), - .hdatain(hdatain), - .hcs_n(hcs_n), - .hwrite_n(hwrite_n), - .hread_n(hread_n), - - // Input signals to the MII Management Interface - - // Input signals to the Tx MAC FIFO Interface - .tx_fifodata(tx_fifodata), - .tx_fifoavail(tx_fifoavail), - .tx_fifoeof(tx_fifoeof), - .tx_fifoempty(tx_fifoempty), - .tx_sndpaustim(tx_sndpaustim), - .tx_sndpausreq(tx_sndpausreq), - .tx_fifoctrl(tx_fifoctrl), - - // Input signals to the Rx MAC FIFO Interface - .rx_fifo_full(rx_fifo_full), - .ignore_pkt(ignore_pkt), - - // Output signals from the GMII - .txd(txd), - .tx_en(tx_en), - .tx_er(tx_er), - - // Output signals from the CPU Interface - .hdataout(hdataout), - .hdataout_en_n(hdataout_en_n), - .hready_n(hready_n), - .cpu_if_gbit_en(cpu_if_gbit_en), - - // Output signals from the MII Management Interface - - // Output signals from the Tx MAC FIFO Interface - .tx_macread(tx_macread), - .tx_discfrm(tx_discfrm), - .tx_staten(tx_staten), - .tx_statvec(tx_statvec), - .tx_done(tx_done), - - // Output signals from the Rx MAC FIFO Interface - .rx_fifo_error(rx_fifo_error), - .rx_stat_vector(rx_stat_vector), - .rx_dbout(rx_dbout), - .rx_write(rx_write), - .rx_stat_en(rx_stat_en), - .rx_eof(rx_eof), - .rx_error(rx_error) - ); -endmodule diff --git a/gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_bb.v b/gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_bb.v deleted file mode 100644 index 815186c..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_bb.v +++ /dev/null @@ -1,145 +0,0 @@ -//============================================================================= -// Verilog module generated by IPExpress -// Filename: USERNAME_bb.v -// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. -//============================================================================= - -/* WARNING - Changes to this file should be performed by re-running IPexpress -or modifying the .LPC file and regenerating the core. Other changes may lead -to inconsistent simulation and/or implemenation results */ -module tsmac34 ( - // clock and reset - hclk, - txmac_clk, - rxmac_clk, - reset_n, - txmac_clk_en, - rxmac_clk_en, - - // Input signals to the GMII - rxd, - rx_dv, - rx_er, - col, - crs, - - // Input signals to the CPU Interface - haddr, - hdatain, - hcs_n, - hwrite_n, - hread_n, - - // Input signals to the MII Management Interface - - // Input signals to the Tx MAC FIFO Interface - tx_fifodata, - tx_fifoavail, - tx_fifoeof, - tx_fifoempty, - tx_sndpaustim, - tx_sndpausreq, - tx_fifoctrl, - - // Input signals to the Rx MAC FIFO Interface - rx_fifo_full, - ignore_pkt, - - // Output signals from the GMII - txd, - tx_en, - tx_er, - - // Output signals from the CPU Interface - hdataout, - hdataout_en_n, - hready_n, - cpu_if_gbit_en, - - // Output signals from the MII Management Interface - - // Output signals from the Tx MAC FIFO Interface - tx_macread, - tx_discfrm, - tx_staten, - tx_statvec, - tx_done, - - // Output signals from the Rx MAC FIFO Interface - rx_fifo_error, - rx_stat_vector, - rx_dbout, - rx_write, - rx_stat_en, - rx_eof, - rx_error - ); - - // ------------------------- clock and reset inputs --------------------- - input hclk; // clock to the CPU I/F - input txmac_clk; // clock to the Tx MAC - input rxmac_clk; // clock to the RX MAC - input reset_n; // Global reset - input txmac_clk_en; // clock enable to the Tx MAC - input rxmac_clk_en; // clock enable to the RX MAC - - // ----------------------- Input signals to the GMII ------------------- - input [7:0] rxd; // Receive data - input rx_dv; // Receive data valid - input rx_er; // Receive data error - input col; // Collision detect - input crs; // Carrier Sense - // -------------------- Input signals to the CPU I/F ------------------- - input [7:0] haddr; // Address Bus - input [7:0] hdatain; // Input data Bus - input hcs_n; // Chip select - input hwrite_n; // Register write - input hread_n; // Register read - - // -------------------- Input signals to the MII I/F ------------------- - - - // ---------------- Input signals to the Tx MAC FIFO I/F --------------- - input [7:0] tx_fifodata; // Data Input from FIFO - input tx_fifoavail; // Data Available in FIFO - input tx_fifoeof; // End of Frame - input tx_fifoempty; // FIFO Empty - input [15:0] tx_sndpaustim; // Pause frame parameter - input tx_sndpausreq; // Transmit PAUSE frame - input tx_fifoctrl; // Control frame or Not - - // ---------------- Input signals to the Rx MAC FIFO I/F --------------- - input rx_fifo_full; // Receive FIFO Full - input ignore_pkt; // Ignore the frame - - // -------------------- Output signals from the GMII ----------------------- - output [7:0] txd; // Transmit data - output tx_en; // Transmit Enable - output tx_er; // Transmit Error - - // -------------------- Output signals from the CPU I/F ------------------- - output [7:0] hdataout; // Output data Bus - output hdataout_en_n; // Data Out Enable - output hready_n; // Ready signal - output cpu_if_gbit_en; // Gig or 10/100 mode - - // -------------------- Output signals from the MII I/F ------------------- - - - // ---------------- Output signals from the Tx MAC FIFO I/F --------------- - output tx_macread; // Read FIFO - output tx_discfrm; // Discard Frame - output tx_staten; // Status Vector Valid - output tx_done; // Transmit of Frame done - output [30:0] tx_statvec; // Tx Status Vector - - // ---------------- Output signals from the Rx MAC FIFO I/F --------------- - output rx_fifo_error; // FIFO full detected - output [31:0] rx_stat_vector; // Rx Status Vector - output [7:0] rx_dbout; // Data Output to FIFO - output rx_write; // Write FIFO - output rx_stat_en; // Status Vector Valid - output rx_eof; // Entire frame written - output rx_error; // Erroneous frame - -endmodule diff --git a/gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_beh.v b/gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_beh.v deleted file mode 100644 index 84453b8..0000000 --- a/gbe2_ecp3/ipcores_ecp3/tsmac34/tsmac34_beh.v +++ /dev/null @@ -1,5840 +0,0 @@ -// ts_mac_core_beh.v generated by Lattice IP Model Creator version 1 -// created on Wed Mar 23 11:57:00 CST 2011 -// Copyright(c) 2007~2011 Lattice Semiconductor Corporation. All rights reserved -// obfuscator_exe version 1.mar0807 - -// top - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`timescale 1 ns / 100 ps -module hd2df10 ( - rxmac_clk, - reset_n, - rxmac_clk_en, - - - ks10d54, - ls86aa0, - - - ls35502, - lfaa812, - - - kd54097, - rva04bd, - cb25ef, - wl12f7d -); -parameter gq97bed = 8; -input rxmac_clk; -input reset_n; -input rxmac_clk_en; -input ks10d54; -input ls35502; -input lfaa812; -input [gq97bed-1:0] ls86aa0; -output rva04bd; -output cb25ef; -output wl12f7d; -output [gq97bed-1:0] kd54097; -reg rva04bd; -reg cb25ef; -reg wl12f7d; -reg [gq97bed-1:0] kd54097; -reg wl95504; -parameter jraa825 = 2; -parameter uv5412f = 2'b01; -parameter tja097d = 2'b10; -parameter ng4bee = 0; -parameter fc25f73 = 1; -parameter fc2fb9a = 8'hd5; -parameter me7dcd3 = 8'h55; -wire zkee699; -wire ne734ca; -reg ep9a653; -reg uvd329c; -reg ng994e4; -reg [jraa825-1:0] os5391b; -reg [2:0] vk9c8d9; -reg [jraa825-1:0] oh23653; -reg zm1b29c; -reg [gq97bed - 1 : 0] neca715; -reg ic538ab; -reg zm9c559; -reg kde2acb; -reg wy1565d; -reg irab2e9; -reg go5974c; -reg mecba61; -reg xw5d308; -reg [jraa825 - 1 : 0] go4c21e; -reg [2 : 0] dz610f0; -reg [jraa825 - 1 : 0] ic43c3c; -reg [2047:0] ng1e1e0; -wire [12:0] mef0f02; - -localparam uk87811 = 13,gd3c088 = 32'hfdfff40b; -localparam [31:0] yke0444 = gd3c088; -localparam ba1110d = gd3c088 & 4'hf; -localparam [11:0] of44359 = 'h7ff; -wire [(1 << ba1110d) -1:0] epd660; -reg [uk87811-1:0] ui59826; -reg [ba1110d-1:0] uv60984 [0:1]; -reg [ba1110d-1:0] sj26123; -reg fc3091c; -integer tj848e3; -integer aa2471f; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin kd54097 <= 0; end else if (rxmac_clk_en) begin if (zm1b29c) begin kd54097 <= neca715; end end -end - - - - -assign zkee699 = neca715[7:0] == fc2fb9a; -assign ne734ca = neca715[7:0] == me7dcd3; - - - - - - -always @(posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin oh23653 <= uv5412f; vk9c8d9 <= 3'b0; rva04bd <= 1'b0; wl12f7d <= 1'b0; wl95504 <= 1'b0; cb25ef <= 1'b0; end else if (rxmac_clk_en) begin oh23653 <= go4c21e; wl95504 <= go5974c; cb25ef <= kde2acb; rva04bd <= 1'b0; - vk9c8d9 <= xw5d308 ? 3'h1 : (|dz610f0) ? (dz610f0+3'h1) : ic43c3c[ng4bee] ? 3'h0 : dz610f0; - if (mecba61) begin wl12f7d <= 1'b1; end else if (zm9c559) begin wl12f7d <= 1'b0; end else if (ic538ab) begin wl12f7d <= 1'b0; end end -end - - -always @(ic43c3c or ic538ab or irab2e9 or wy1565d or dz610f0) begin case(ic43c3c) uv5412f : begin if (ic538ab && wy1565d) begin os5391b = uv5412f; ep9a653 = 1'b1; uvd329c = 1'b0; ng994e4 = 1'b0; end else if (ic538ab && irab2e9) begin os5391b = tja097d; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b1; end else if (ic538ab && !wy1565d && !irab2e9) begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b1; ng994e4 = 1'b0; end - else begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end end - tja097d : begin if (wy1565d) begin os5391b = uv5412f; ep9a653 = 1'b1; uvd329c = 1'b0; ng994e4 = 1'b0; end else if (~|dz610f0 & ~irab2e9) begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b1; ng994e4 = 1'b0; end else begin os5391b = tja097d; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end - end - default : begin os5391b = uv5412f; ep9a653 = 1'b0; uvd329c = 1'b0; ng994e4 = 1'b0; end endcase -end - -always@* begin zm1b29c<=mef0f02[0];neca715<={ls86aa0>>1,mef0f02[1]};ic538ab<=mef0f02[2];zm9c559<=mef0f02[3];kde2acb<=mef0f02[4];wy1565d<=mef0f02[5];irab2e9<=mef0f02[6];go5974c<=mef0f02[7];mecba61<=mef0f02[8];xw5d308<=mef0f02[9];go4c21e<={os5391b>>1,mef0f02[10]};dz610f0<={vk9c8d9>>1,mef0f02[11]};ic43c3c<={oh23653>>1,mef0f02[12]};end -always@* begin ng1e1e0[2047]<=ls86aa0[0];ng1e1e0[2046]<=ls35502;ng1e1e0[2044]<=lfaa812;ng1e1e0[2040]<=wl95504;ng1e1e0[2032]<=zkee699;ng1e1e0[2016]<=ne734ca;ng1e1e0[1984]<=ep9a653;ng1e1e0[1920]<=uvd329c;ng1e1e0[1793]<=ng994e4;ng1e1e0[1539]<=os5391b[0];ng1e1e0[1030]<=vk9c8d9[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[13]<=oh23653[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};al4b56a<=mef0f02[1];zm9c559<=mef0f02[2];byd5aaf<=mef0f02[3];gb6abd3<={uv70d29>>1,mef0f02[4]};ntaf4ee<={hq8694d>>1,mef0f02[5]};czd3bb5<={ec34a6a>>1,mef0f02[6]};dmeed68<={lfa5351>>1,mef0f02[7]};dbb5a1a<={gd29a8f>>1,mef0f02[8]};go686bb<={rg4d47c>>1,mef0f02[9]};ie1aec9<={mr6a3e2>>1,mef0f02[10]};yzbb24e<={of51f14>>1,mef0f02[11]};gbc93ad<={sj8f8a4>>1,mef0f02[12]};ay49d6c<=mef0f02[13];kd4eb61<=mef0f02[14];ip75b0c<=mef0f02[15];lq6c32a<={wla48aa>>1,mef0f02[16]};ld61953<=mef0f02[17];dbca9e<=mef0f02[18];ip654f7<=mef0f02[19];hq2a7bd<=mef0f02[20];yk53dea<=mef0f02[21];zz9ef51<=mef0f02[22];kdf7a8f<=mef0f02[23];babd47c<=mef0f02[24];yx51f10<={wj5b24d>>1,mef0f02[25]};jc7c424<={enc9365>>1,mef0f02[26]};yxe2122<=mef0f02[27];aa10914<=mef0f02[28];lf848a0<=mef0f02[29];ou24507<=mef0f02[30];fp22839<=mef0f02[31];je141cf<=mef0f02[32];jra0e7b<=mef0f02[33];mt73de<=mef0f02[34];rgcf7ad<={jra5ef8>>1,mef0f02[35]};icdeb5e<={hb7be32>>1,mef0f02[36]};cmf5af1<=mef0f02[37];twad789<=mef0f02[38];cz5e25f<={bn32cad>>1,mef0f02[39]};dmf12fc<=mef0f02[40];xy897e2<=mef0f02[41];ip4bf12<=mef0f02[42];th5f894<=mef0f02[43];pffc4a7<=mef0f02[44];wl129f4<={co928b1>>1,mef0f02[45]};doa7d2e<={baa2c4f>>1,mef0f02[46]};sw3e973<=mef0f02[47];rgf4b98<=mef0f02[48];lfa5cc3<=mef0f02[49];aa2e61e<=mef0f02[50];vi730f0<=mef0f02[51];ou98783<=mef0f02[52];alc3c19<=mef0f02[53];ba1e0cc<=mef0f02[54];uif0662<=mef0f02[55];do83310<=mef0f02[56];fp19883<=mef0f02[57];end -always@* begin ng1e1e0[2047]<=cb25ef;ng1e1e0[2046]<=lfaa812;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=uv70d29[0];ng1e1e0[2032]<=hq8694d[0];ng1e1e0[2017]<=ec34a6a[0];ng1e1e0[1987]<=lfa5351[0];ng1e1e0[1980]<=je89ef4;ng1e1e0[1963]<=xyb52f;ng1e1e0[1942]<=ksa3f8a;ng1e1e0[1926]<=gd29a8f[0];ng1e1e0[1921]<=ks152d9;ng1e1e0[1913]<=fn4f7a3;ng1e1e0[1903]<=an95b92;ng1e1e0[1879]<=nr5a97b;ng1e1e0[1837]<=wy1fc51;ng1e1e0[1805]<=rg4d47c[0];ng1e1e0[1795]<=oua96c9;ng1e1e0[1783]<=baa2c4f[0];ng1e1e0[1778]<=zx7bd1f;ng1e1e0[1758]<=jeadc94;ng1e1e0[1710]<=jra5ef8[0];ng1e1e0[1679]<=wla48aa[0];ng1e1e0[1627]<=lqfe289;ng1e1e0[1562]<=mr6a3e2[0];ng1e1e0[1543]<=wj5b24d[0];ng1e1e0[1519]<=fp1627b;ng1e1e0[1509]<=uide8fe;ng1e1e0[1499]<=hq9656e;ng1e1e0[1469]<=rt6e4a2;ng1e1e0[1398]<=shf8cb2;ng1e1e0[1373]<=hb7be32[0];ng1e1e0[1310]<=fac526c;ng1e1e0[1207]<=rgf144b;ng1e1e0[1144]<=ww49b15;ng1e1e0[1076]<=of51f14[0];ng1e1e0[1039]<=enc9365[0];ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[990]<=yzb13de;ng1e1e0[981]<=xj616a5;ng1e1e0[971]<=vif47f1;ng1e1e0[960]<=cm62a5b;ng1e1e0[951]<=ngb2b72;ng1e1e0[891]<=co928b1[0];ng1e1e0[839]<=vk14915;ng1e1e0[749]<=bn32cad[0];ng1e1e0[699]<=hodf196;ng1e1e0[572]<=qv29362;ng1e1e0[490]<=gd2c2d4;ng1e1e0[480]<=ho6c54b;ng1e1e0[419]<=ale2922;ng1e1e0[245]<=sh6585a;ng1e1e0[240]<=dm4d8a9;ng1e1e0[209]<=tu7c524;ng1e1e0[122]<=tu6cb0b;ng1e1e0[104]<=sj8f8a4[0];ng1e1e0[61]<=lq4d961;ng1e1e0[30]<=kq49b2c;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f= 7'h42); - - -assign sw21a46 = zx4f6f2 & ~ofed2bb; -assign zz84348 = bna0270 & ~mg875ed & ~bn9c3a & ~sh4e1d7; - - -assign al70eaa = bldd794 & aa3404e[18]; - - - - - - -assign fpaaa53 = (bna0270 | rx_write) & wwde5f9 & ~mg875ed & ~bn9c3a; - -always@* begin zx4f6f2<=mef0f02[0];dz7b797<=mef0f02[1];eadbcbf<={epae410>>1,mef0f02[2]};wwde5f9<=mef0f02[3];ks97e44<={ep90421>>1,mef0f02[4]};pff910f<={of4bc4f>>1,mef0f02[5]};wj443f7<={vif13e4>>1,mef0f02[6]};ukfde0<={hd9bdf7>>1,mef0f02[7]};off7806<={wjf7df9>>1,mef0f02[8]};gqbc034<=mef0f02[9];yke01a0<=mef0f02[10];ecd01<=mef0f02[11];aa3404e<={tw3fb87>>1,mef0f02[12]};bna0270<=mef0f02[13];do1387<=mef0f02[14];bn9c3a<=mef0f02[15];sh4e1d7<=mef0f02[16];yx70ebd<=mef0f02[17];mg875ed<=mef0f02[18];xy3af69<=mef0f02[19];ribda57<={coa94ff>>1,mef0f02[20]};ofed2bb<=mef0f02[21];fn4aeeb<={wl9fe79>>1,mef0f02[22]};gdbbaf2<={ldf9e69>>1,mef0f02[23]};bldd794<=mef0f02[24];zkebca7<=mef0f02[25];sh5e53b<=mef0f02[26];czf29dc<=mef0f02[27];end -always@* begin ng1e1e0[2047]<=wy15c82;ng1e1e0[2046]<=epae410[0];ng1e1e0[2044]<=rx_fifo_full;ng1e1e0[2040]<=ep90421[0];ng1e1e0[2032]<=of4bc4f[0];ng1e1e0[2017]<=vif13e4[0];ng1e1e0[1987]<=hd9bdf7[0];ng1e1e0[1926]<=wjf7df9[0];ng1e1e0[1921]<=ldf9e69[0];ng1e1e0[1805]<=ipf7e64;ng1e1e0[1795]<=rgcf34f;ng1e1e0[1679]<=co87555;ng1e1e0[1562]<=ntbf324;ng1e1e0[1543]<=ps79a7b;ng1e1e0[1310]<=vk3aaa9;ng1e1e0[1144]<=fpaaa53;ng1e1e0[1076]<=jpf9927;ng1e1e0[1039]<=zxcd3db;ng1e1e0[1023]<=tu42b90;ng1e1e0[960]<=wl9fe79[0];ng1e1e0[839]<=al70eaa;ng1e1e0[572]<=psd554a;ng1e1e0[480]<=rt4a7f9;ng1e1e0[419]<=hoee1d5;ng1e1e0[240]<=coa94ff[0];ng1e1e0[209]<=alfdc3a;ng1e1e0[104]<=tw3fb87[0];ng1e1e0[30]<=xw69ede;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};zm9c559<=mef0f02[1];fp81339<=mef0f02[2];byd5aaf<=mef0f02[3];os4ce77<=mef0f02[4];qv39dc8<={ba25a85>>1,mef0f02[5]};eacee45<=mef0f02[6];kq77228<=mef0f02[7];ldc8a08<={gq3eb5e>>1,mef0f02[8]};vv45047<=mef0f02[9];ph2823e<=mef0f02[10];qt411f7<=mef0f02[11];an8fbc<=mef0f02[12];jc47de5<=mef0f02[13];uk3ef2a<=mef0f02[14];ipf7950<=mef0f02[15];ksbca84<=mef0f02[16];ice5421<=mef0f02[17];bl5084a<={do1ba48>>1,mef0f02[18]};tj84256<=mef0f02[19];wy212b6<=mef0f02[20];rv95b1<=mef0f02[21];nr4ad8e<=mef0f02[22];swb63b1<={qi1fe10>>1,mef0f02[23]};fp19883<=mef0f02[24];end -always@* begin ng1e1e0[2047]<=lfaa812;ng1e1e0[2046]<=jc4d12d;ng1e1e0[2044]<=ykce1a5;ng1e1e0[2040]<=gb44b50;ng1e1e0[2032]<=ba25a85[0];ng1e1e0[2017]<=ukf3ec;ng1e1e0[1987]<=zz22aa1;ng1e1e0[1926]<=gq3eb5e[0];ng1e1e0[1804]<=mg8d20b;ng1e1e0[1803]<=qi1fe10[0];ng1e1e0[1560]<=xw69058;ng1e1e0[1558]<=rgf144b;ng1e1e0[1550]<=co1a8dd;ng1e1e0[1072]<=by482c3;ng1e1e0[1052]<=god46e9;ng1e1e0[1023]<=bn1ce70[0];ng1e1e0[901]<=dm487f8;ng1e1e0[775]<=qtc351b;ng1e1e0[450]<=qg490ff;ng1e1e0[387]<=dm586a3;ng1e1e0[225]<=zxe921f;ng1e1e0[193]<=jeb0d4;ng1e1e0[112]<=rtdd243;ng1e1e0[96]<=of4161a;ng1e1e0[56]<=do1ba48[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};wl9fec7<=mef0f02[1];kqff63d<=mef0f02[2];jcfb1e9<=mef0f02[3];dzd8f4b<=mef0f02[4];nrc7a5e<={vif4c35>>1,mef0f02[5]};db3d2f6<={zm3f362>>1,mef0f02[6]};dze97b6<={ps6c4ff>>1,mef0f02[7]};yx4bdb7<={os627fb>>1,mef0f02[8]};end -always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uk317a6;ng1e1e0[2044]<=fp8bd30;ng1e1e0[2041]<=uv5e986;ng1e1e0[2034]<=vif4c35[0];ng1e1e0[2021]<=zm3f362[0];ng1e1e0[1995]<=ps6c4ff[0];ng1e1e0[1943]<=os627fb[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f= 14'd64); - - - - -assign wy15c82 = ((~gq88319) ? (lfaa812 & ~gq3e3e7) : 1'b0) | (zzb0517 & ~qi828be) | (dob2655 & ~ba932ab) | (vvc8b97 & ux7990 & lfaa812) | (pu3a20c & lfaa812); - -assign cz65043 = al4b56a | (zxcd67f & an8a74); - - -assign nt2821d = gb44b50; -assign al410ef = gb44b50 & ea437a9; - - -assign ui43be4 = (~xl84bbc) ? hofec14 -14'd4 : fc83768; - -assign kf17a95 = 32'hffffffff; - -assign jc52b50 = ls35502; -assign fp8bd30 = ~vi7ce5c & kfa4f8f; - -assign ks24554 = al4b56a | yk5c720; - - - -assign ri4632 = cz418c8 & ir90977 & wwcb8e4 & gq3e3e7 & ~(hd9b63f | xj45cbf); - -always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin gdab323 <= 1'b0; zkd5664 <= 1'b0; mrcc8e0 <= 14'b0; ldd22e2 <= 14'b0; bn8b8b7 <= 14'b0; me5c5be <= 1'b0; ux8420 <= 1'b0; uvc64a4 <= 1'b0; ps79d12 <= 1'b0; wwce893 <= 1'b0; bl74498 <= 1'b0; hqa24c6 <= 1'b0; ir23192 <= 1'b0; fa58e7c <= 1'b0; je2f3a2 <= 1'b0; psf1bd5 <= 14'd0; ux2382f <= 14'd0; bldd558 <= 9'd0; ykeaac7 <= 1'b0; wl12632 <= 1'b0; lqfe289 <= 1'b0; end else if (rxmac_clk_en) begin ykeaac7 <= mt29d2e & ~czf29dc; if (mt29d2e && !czf29dc) bldd558 <= ayf0d93; ir23192 <= fp8bd30; fa58e7c <= wl3971c; if (czf8071) je2f3a2 <= czf8071; else if (ls35502 && !czf8071) je2f3a2 <= 1'b0; else if (zzb0517) je2f3a2 <= 1'b0; else je2f3a2 <= qifcdb; hqa24c6 <= ~vk1f9b; if (rvba149 & zm1b29c) bl74498 <= rvba149; else if (mt29d2e) bl74498 <= 1'b0; else bl74498 <= hd9b63f; if (zke407e) wwce893 <= zke407e; else if (mt29d2e) wwce893 <= 1'b0; else wwce893 <= xjf36c7; lqfe289 <= al4b56a; if (do83310) ps79d12 <= kf8527a; if (yzab1cf) wl12632 <= ayd4a7c; uvc64a4 <= al4b56a | (yk5c720 & zm1b29c); mrcc8e0 <= tj137d0; zkd5664 <= dze3901; gdab323 <= vidf437; if (zxcd67f && !hqe313) ux8420 <= ls1bd49; me5c5be <= hqe313; if (zxcd67f && !hqe313) ldd22e2 <= pff9acf; if (hqe313) begin bn8b8b7 <= pff9acf + 14'd1; end else bn8b8b7 <= 14'd0; if (tw8c4df && xl84bbc && su49641) ux2382f <= fc83768 + 14'd1; if (pf7189b && !xl84bbc && an8a74) psf1bd5 <= hofec14 + 14'd1; else if (jpf60a2) psf1bd5 <= 14'd0; end -end - - - -assign yzab1cf = jpf60a2; - - -assign lf32525 = gd3cc84 ? (ks97e6b > (ho6322e + 14'd4)) : ks97e6b > ho6322e; -assign mg9292f = (ks97e6b < 14'd64); -assign hd94979 = wwff00e; - -assign gd1df20 = (ks97e6b[6:0] != 7'd64); -assign icef904 = (hd3212e != qvbe0dd); -assign oha4bce = vx1c80f ? 1'b0 : ux7990 | xl84bbc ? hd9be86 : hq25de7 ? 1'b0 : fca2f83; - -assign zm25e74 = ~(hd9b63f | xj45cbf | ng203f3); -assign vx33b0[31] = zm145f0; -assign vx33b0[30] = vx1c80f; -assign vx33b0[29] = fn7e6d8; -assign vx33b0[28] = nrd8ff0; -assign vx33b0[27] = xjf36c7; -assign vx33b0[26] = qifcdb; -assign vx33b0[25] = xj45cbf; -assign vx33b0[24] = ng203f3; -assign vx33b0[23] = vk1f9b; -assign vx33b0[22] = th4f83c; -assign vx33b0[21] = by7c1e6; -assign vx33b0[20] = ned0a4f; -assign vx33b0[19] = uk2ef3a; -assign vx33b0[18] = ux7990; -assign vx33b0[17] = ir90977; -assign vx33b0[16] = gd3cc84; -assign vx33b0[15:14] = 2'b00; -assign vx33b0[13:0] = ks97e6b; - -assign jr32885[0] = ir90977; -assign jr32885[1] = xj45cbf; -assign jr32885[2] = hd9b63f; -assign jr32885[3] = zm145f0; -assign jr32885[4] = vx1c80f; -assign jr32885[5] = fn7e6d8; -assign jr32885[6] = th4f83c; -assign jr32885[7] = by7c1e6; -assign jr32885[8] = gd3cc84; - -always@* begin zm1b29c<=mef0f02[0];ic77429<=mef0f02[1];rvba149<=mef0f02[2];ned0a4f<=mef0f02[3];kf8527a<=mef0f02[4];je896ad<={bn1ce70>>1,mef0f02[5]};al4b56a<=mef0f02[6];qt7a94f<=mef0f02[7];ayd4a7c<=mef0f02[8];lfa53e0<=mef0f02[9];gd29f07<=mef0f02[10];th4f83c<=mef0f02[11];by7c1e6<=mef0f02[12];kqe0f32<=mef0f02[13];ux7990<=mef0f02[14];gd3cc84<=mef0f02[15];hd3212e<={dm579a3>>1,mef0f02[16]};ir90977<=mef0f02[17];xl84bbc<=mef0f02[18];hq25de7<=mef0f02[19];uk2ef3a<=mef0f02[20];cm779d1<=mef0f02[21];qte7441<={lde68d9>>1,mef0f02[22]};pu3a20c<=mef0f02[23];wwd1063<=mef0f02[24];gq88319<=mef0f02[25];cz418c8<=mef0f02[26];ho6322e<={ldcd808>>1,mef0f02[27]};xl19172<=mef0f02[28];vvc8b97<=mef0f02[29];xj45cbf<=mef0f02[30];qg72ff8<={je2fc44>>1,mef0f02[31]};wy97fc0<=mef0f02[32];jrbfe01<=mef0f02[33];wwff00e<=mef0f02[34];czf8071<=mef0f02[35];tuc038c<=mef0f02[36];xy1c62<=mef0f02[37];hqe313<=mef0f02[38];pf7189b<=mef0f02[39];tw8c4df<=mef0f02[40];tj137d0<={ui43be4>>1,mef0f02[41]};hd9be86<=mef0f02[42];vidf437<=mef0f02[43];rgd0dd1<={rge410b>>1,mef0f02[44]};pu86e8a<=mef0f02[45];tj37452<=mef0f02[46];bnba297<={sw216d2>>1,mef0f02[47]};osd14bf<=mef0f02[48];wl8a5f9<=mef0f02[49];ks97e6b<={ldd22e2>>1,mef0f02[50]};pff9acf<={bn8b8b7>>1,mef0f02[51]};zxcd67f<=mef0f02[52];zx6b3fe<=mef0f02[53];me59ff6<=mef0f02[54];facffb0<=mef0f02[55];hofec14<={psf1bd5>>1,mef0f02[56]};jpf60a2<=mef0f02[57];zzb0517<=mef0f02[58];qi828be<=mef0f02[59];zm145f0<=mef0f02[60];fca2f83<=mef0f02[61];qvbe0dd<={mrcc8e0>>1,mef0f02[62]};fc83768<={ux2382f>>1,mef0f02[63]};tw1bb43<=mef0f02[64];pfdda1b<=mef0f02[65];ened0de<=mef0f02[66];ea686f5<=mef0f02[67];ea437a9<=mef0f02[68];ls1bd49<=mef0f02[69];aydea4b<=mef0f02[70];wya92c8<={ngb200>>1,mef0f02[71]};su49641<=mef0f02[72];uv4b208<=mef0f02[73];me59045<=mef0f02[74];qt4114e<={vx33b0>>1,mef0f02[75]};an8a74<=mef0f02[76];ld453a5<=mef0f02[77];mt29d2e<=mef0f02[78];czf29dc<=mef0f02[79];pf74ba4<=mef0f02[80];vxa5d27<=mef0f02[81];rt749f1<={ym1f042>>1,mef0f02[82]};kfa4f8f<=mef0f02[83];vx27c7c<=mef0f02[84];gq3e3e7<=mef0f02[85];dmf1f39<=mef0f02[86];cb8f9cb<={ym10823>>1,mef0f02[87]};vi7ce5c<=mef0f02[88];do83310<=mef0f02[89];wl3971c<=mef0f02[90];wwcb8e4<=mef0f02[91];yk5c720<=mef0f02[92];dze3901<=mef0f02[93];vx1c80f<=mef0f02[94];zke407e<=mef0f02[95];ng203f3<=mef0f02[96];vk1f9b<=mef0f02[97];qifcdb<=mef0f02[98];fn7e6d8<=mef0f02[99];xjf36c7<=mef0f02[100];hd9b63f<=mef0f02[101];qgdb1fe<=mef0f02[102];nrd8ff0<=mef0f02[103];pfc7f86<=mef0f02[104];ri3fc36<=mef0f02[105];ayf0d93<={jr32885>>1,mef0f02[106]};do86c99<={vx9442e>>1,mef0f02[107]};an364ca<=mef0f02[108];dob2655<=mef0f02[109];ba932ab<=mef0f02[110];end -always@* begin ng1e1e0[2047]<=fa6c2d4;ng1e1e0[2046]<=pf616a3;ng1e1e0[2044]<=lsb51f;ng1e1e0[2040]<=vv5a8fb;ng1e1e0[2032]<=bn1ce70[0];ng1e1e0[2028]<=uvc64a4;ng1e1e0[2017]<=cb25ef;ng1e1e0[2008]<=lf32525;ng1e1e0[1988]<=vx33b0[0];ng1e1e0[1987]<=wl12f7d;ng1e1e0[1969]<=mg9292f;ng1e1e0[1928]<=iccec3e;ng1e1e0[1926]<=rva04bd;ng1e1e0[1891]<=hd94979;ng1e1e0[1809]<=rg761f0;ng1e1e0[1805]<=kf23e8c;ng1e1e0[1804]<=mg1550f;ng1e1e0[1803]<=yz172cd;ng1e1e0[1761]<=tuf111f;ng1e1e0[1748]<=gdab323;ng1e1e0[1734]<=oha4bce;ng1e1e0[1727]<=ym10823[0];ng1e1e0[1696]<=bn1c17d;ng1e1e0[1668]<=gd1df20;ng1e1e0[1633]<=do93194;ng1e1e0[1587]<=ps79d12;ng1e1e0[1571]<=lfb0f83;ng1e1e0[1562]<=gofa328;ng1e1e0[1560]<=hdaa879;ng1e1e0[1558]<=ignore_pkt;ng1e1e0[1555]<=zma2177;ng1e1e0[1550]<=dm579a3[0];ng1e1e0[1531]<=ri4632;ng1e1e0[1475]<=uk888fa;ng1e1e0[1464]<=bl7b98b;ng1e1e0[1448]<=mrcc8e0[0];ng1e1e0[1420]<=zm25e74;ng1e1e0[1406]<=vx84118;ng1e1e0[1345]<=yke0bef;ng1e1e0[1288]<=icef904;ng1e1e0[1287]<=fc2fbc1;ng1e1e0[1242]<=yx6f559;ng1e1e0[1218]<=gq98ca2;ng1e1e0[1131]<=yxf8210;ng1e1e0[1126]<=wwce893;ng1e1e0[1094]<=xw69ede;ng1e1e0[1076]<=zm8ca08;ng1e1e0[1072]<=en543cf;ng1e1e0[1069]<=qgcb360;ng1e1e0[1063]<=ie10bba;ng1e1e0[1056]<=ba2085b;ng1e1e0[1055]<=ykef059;ng1e1e0[1052]<=ec346cf;ng1e1e0[1028]<=ldd22e2[0];ng1e1e0[1023]<=ks10d54;ng1e1e0[1014]<=ir23192;ng1e1e0[994]<=vv400ce;ng1e1e0[902]<=of447d1;ng1e1e0[901]<=lde68d9[0];ng1e1e0[880]<=je2fc44[0];ng1e1e0[874]<=zkd5664;ng1e1e0[863]<=jc42104;ng1e1e0[848]<=ux2382f[0];ng1e1e0[834]<=ui43be4[0];ng1e1e0[816]<=wl12632;ng1e1e0[793]<=je2f3a2;ng1e1e0[777]<=vx9442e[0];ng1e1e0[775]<=hq2af34;ng1e1e0[765]<=lqfe289;ng1e1e0[732]<=wj6023b;ng1e1e0[643]<=aa5f78;ng1e1e0[621]<=sw8deab;ng1e1e0[565]<=ym1f042[0];ng1e1e0[528]<=rge410b[0];ng1e1e0[527]<=me7de0b;ng1e1e0[514]<=en5b48b;ng1e1e0[497]<=fnc8019;ng1e1e0[450]<=ksbcd1b;ng1e1e0[437]<=gb7aacc;ng1e1e0[431]<=ux8420;ng1e1e0[417]<=al410ef;ng1e1e0[408]<=hqa24c6;ng1e1e0[388]<=jr32885[0];ng1e1e0[387]<=ep855e6;ng1e1e0[366]<=tu6c047;ng1e1e0[310]<=psf1bd5[0];ng1e1e0[282]<=uif07c1;ng1e1e0[257]<=jeb691;ng1e1e0[248]<=ic59003;ng1e1e0[225]<=rgc0518;ng1e1e0[215]<=mec1084;ng1e1e0[208]<=nt2821d;ng1e1e0[204]<=bl74498;ng1e1e0[193]<=jp50abc;ng1e1e0[183]<=ldcd808[0];ng1e1e0[155]<=fcb7c6f;ng1e1e0[141]<=sw3e0f8;ng1e1e0[128]<=sw216d2[0];ng1e1e0[124]<=ngb200[0];ng1e1e0[112]<=xy1b3c0;ng1e1e0[104]<=cz65043;ng1e1e0[96]<=uxa1e7d;ng1e1e0[91]<=go59b01;ng1e1e0[78]<=wl85dd0;ng1e1e0[77]<=zz16f8d;ng1e1e0[64]<=zm42da;ng1e1e0[62]<=ea782c8;ng1e1e0[56]<=eca3678;ng1e1e0[38]<=kde2df1;ng1e1e0[19]<=me5c5be;ng1e1e0[9]<=bn8b8b7[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[3]};rvba149<=mef0f02[4];ned0a4f<=mef0f02[5];kf8527a<=mef0f02[6];gb6abd3<={uv70d29>>1,mef0f02[7]};ntaf4ee<={hq8694d>>1,mef0f02[8]};czd3bb5<={ec34a6a>>1,mef0f02[9]};dmeed68<={lfa5351>>1,mef0f02[10]};dbb5a1a<={gd29a8f>>1,mef0f02[11]};go686bb<={rg4d47c>>1,mef0f02[12]};ie1aec9<={mr6a3e2>>1,mef0f02[13]};yzbb24e<={of51f14>>1,mef0f02[14]};gbc93ad<={sj8f8a4>>1,mef0f02[15]};ay49d6c<=mef0f02[16];kd4eb61<=mef0f02[17];ip75b0c<=mef0f02[18];qv39dc8<={ba25a85>>1,mef0f02[19]};gq88319<=mef0f02[20];cz418c8<=mef0f02[21];ho6322e<={ldcd808>>1,mef0f02[22]};xl19172<=mef0f02[23];vvc8b97<=mef0f02[24];wwde5f9<=mef0f02[25];wwd1063<=mef0f02[26];ym3e93a<={xw791a7>>1,mef0f02[27]};epa4e83<={me469d7>>1,mef0f02[28]};zz2741c<=mef0f02[29];je3a0e6<=mef0f02[30];byd0733<=mef0f02[31];vk8399b<=mef0f02[32];ph1ccda<=mef0f02[33];gd336b6<={qia590>>1,mef0f02[34]};bn9b5b5<=mef0f02[35];vidadae<=mef0f02[36];end6d73<=mef0f02[37];swb6b9d<=mef0f02[38];phb5ce8<=mef0f02[39];zk73a3c<={nr5a773>>1,mef0f02[40]};qte8f11<={uk9dcf5>>1,mef0f02[41]};yz3c462<={by73d42>>1,mef0f02[42]};ofe2314<=mef0f02[43];zm118a4<=mef0f02[44];ba8c522<=mef0f02[45];me62912<=mef0f02[46];ng14891<=mef0f02[47];kfa448a<=mef0f02[48];zz22455<=mef0f02[49];kf122ae<=mef0f02[50];nt91574<=mef0f02[51];oh8aba7<=mef0f02[52];pf55d3c<=mef0f02[53];anae9e6<=mef0f02[54];bl74f35<=mef0f02[55];lsa79af<=mef0f02[56];fne6bdd<={czfd46f>>1,mef0f02[57]};je35eef<=mef0f02[58];zzaf77b<=mef0f02[59];vvddef6<={mr6f821>>1,mef0f02[60]};ykef7b6<=mef0f02[61];hb7bdb0<=mef0f02[62];pff6c31<={sw82127>>1,mef0f02[63]};ntb0c71<={zz849c8>>1,mef0f02[64]};co31c7b<={nt27238>>1,mef0f02[65]};xj71ecf<={thc8e34>>1,mef0f02[66]};gd8f67f<=mef0f02[67];hb7b3fd<=mef0f02[68];facff7c<={ec34efc>>1,mef0f02[69]};end -always@* begin ng1e1e0[2047]<=ks10d54;ng1e1e0[2046]<=fa6c2d4;ng1e1e0[2044]<=ls86aa0[0];ng1e1e0[2041]<=pf616a3;ng1e1e0[2035]<=lsb51f;ng1e1e0[2029]<=czfd46f[0];ng1e1e0[2022]<=vv5a8fb;ng1e1e0[2011]<=suea37c;ng1e1e0[1996]<=uv70d29[0];ng1e1e0[1974]<=kd51be0;ng1e1e0[1945]<=hq8694d[0];ng1e1e0[1943]<=rib86e8;ng1e1e0[1922]<=rx_fifo_full;ng1e1e0[1901]<=mr6f821[0];ng1e1e0[1842]<=ec34a6a[0];ng1e1e0[1839]<=kdc3742;ng1e1e0[1797]<=ignore_pkt;ng1e1e0[1791]<=fa471a7;ng1e1e0[1778]<=ho425c3;ng1e1e0[1776]<=ldcd808[0];ng1e1e0[1759]<=zz849c8[0];ng1e1e0[1755]<=rg7c10d;ng1e1e0[1637]<=lfa5351[0];ng1e1e0[1631]<=hq1ba15;ng1e1e0[1622]<=of51f14[0];ng1e1e0[1546]<=xw791a7[0];ng1e1e0[1535]<=vx38d3b;ng1e1e0[1531]<=ym157ea;ng1e1e0[1509]<=kf12e1b;ng1e1e0[1504]<=tu6c047;ng1e1e0[1471]<=nt27238[0];ng1e1e0[1468]<=qgcb360;ng1e1e0[1463]<=ice086a;ng1e1e0[1391]<=vk14915;ng1e1e0[1312]<=qia590[0];ng1e1e0[1226]<=gd29a8f[0];ng1e1e0[1215]<=xjdd0ab;ng1e1e0[1197]<=sj8f8a4[0];ng1e1e0[1153]<=ri9640b;ng1e1e0[1044]<=me469d7[0];ng1e1e0[1037]<=tj8169d;ng1e1e0[1023]<=reset_n;ng1e1e0[1022]<=ec34efc[0];ng1e1e0[1014]<=yzabf51;ng1e1e0[971]<=ou970dd;ng1e1e0[961]<=wj6023b;ng1e1e0[895]<=thc8e34[0];ng1e1e0[889]<=baa84b8;ng1e1e0[888]<=go59b01;ng1e1e0[879]<=sw82127[0];ng1e1e0[811]<=mr6a3e2[0];ng1e1e0[765]<=dm42afd;ng1e1e0[734]<=ba25a85[0];ng1e1e0[695]<=ale2922;ng1e1e0[656]<=ngb8296;ng1e1e0[576]<=ho52c81;ng1e1e0[518]<=ux902d3;ng1e1e0[444]<=kqf5097;ng1e1e0[405]<=rg4d47c[0];ng1e1e0[382]<=uve855f;ng1e1e0[347]<=tu7c524;ng1e1e0[328]<=hbd7052;ng1e1e0[259]<=pub205a;ng1e1e0[222]<=jr9ea12;ng1e1e0[164]<=xy3ae0a;ng1e1e0[111]<=by73d42[0];ng1e1e0[82]<=ria75c1;ng1e1e0[55]<=uk9dcf5[0];ng1e1e0[41]<=sw34eb8;ng1e1e0[27]<=nr5a773[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};kd4e479<=mef0f02[2];kq723cd<=mef0f02[3];hd91e69<={gqb35c6>>1,mef0f02[4]};oh8f34e<={an9ae31>>1,mef0f02[5]};rg79a75<=mef0f02[6];pfcd3ab<={tu73a4e>>1,mef0f02[7]};end -always@* begin ng1e1e0[2047]<=ep29d6d[0];ng1e1e0[2046]<=aa82cd7;ng1e1e0[2044]<=db166b8;ng1e1e0[2040]<=gqb35c6[0];ng1e1e0[2033]<=an9ae31[0];ng1e1e0[2019]<=thd718d;ng1e1e0[1991]<=tu73a4e[0];ng1e1e0[1023]<=of653ad;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};wl9fec7<=mef0f02[1];dzd8f4b<=mef0f02[2];nrc7a5e<={vif4c35>>1,mef0f02[3]};db3d2f6<={zm3f362>>1,mef0f02[4]};dze97b6<={ps6c4ff>>1,mef0f02[5]};end -always@* begin ng1e1e0[2047]<=hbe62f4;ng1e1e0[2046]<=uv5e986;ng1e1e0[2044]<=vif4c35[0];ng1e1e0[2040]<=zm3f362[0];ng1e1e0[2032]<=ps6c4ff[0];ng1e1e0[1023]<=mrdcc5e[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};ip6f847<=mef0f02[2];lq7c23d<=mef0f02[3];wl8f53<={cm531bb>>1,mef0f02[4]};bn3d4ea<={yxc6ec0>>1,mef0f02[5]};kqea756<=mef0f02[6];ww53ab0<=mef0f02[7];gq9d581<=mef0f02[8];qg56049<={bl7b7f8>>1,mef0f02[9]};vx81246<={icff1cb>>1,mef0f02[10]};ph9236<=mef0f02[11];end -always@* begin ng1e1e0[2047]<=ay625cf[0];ng1e1e0[2046]<=sj12e78;ng1e1e0[2044]<=aa973c5;ng1e1e0[2040]<=cm531bb[0];ng1e1e0[2033]<=yxc6ec0[0];ng1e1e0[2018]<=nt37604;ng1e1e0[1988]<=pfd813d;ng1e1e0[1929]<=hoc09ef;ng1e1e0[1811]<=bl7b7f8[0];ng1e1e0[1574]<=icff1cb[0];ng1e1e0[1101]<=uvf8e59;ng1e1e0[1023]<=xjec4b9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};tw25ed4<={kd4ec72>>1,mef0f02[8]};ng2f6a2<=mef0f02[9];xj7b512<=mef0f02[10];jcda897<=mef0f02[11];kqd44bb<=mef0f02[12];ir12eca<={jr94778>>1,mef0f02[13]};ym97655<=mef0f02[14];uxbb2a8<=mef0f02[15];jccaa2d<={ayef1cc>>1,mef0f02[16]};bl5516a<=mef0f02[17];vka8b57<=mef0f02[18];bn2d5d7<={gd3980f>>1,mef0f02[19]};ip6aebf<=mef0f02[20];lq575fd<=mef0f02[21];vxbafea<=mef0f02[22];rtd7f56<=mef0f02[23];vxbfab7<=mef0f02[24];qtfd5be<=mef0f02[25];ayeadf4<=mef0f02[26];ww53ab0<={pfd813d>>1,mef0f02[27]};gq9d581<={hoc09ef>>1,mef0f02[28]};cbbe84a<=mef0f02[29];tuf4254<=mef0f02[30];rv9515<={kdd9d10>>1,mef0f02[31]};gb54576<={pf74420>>1,mef0f02[32]};ou15dab<={gq10832>>1,mef0f02[33]};sjaed58<=mef0f02[34];ne76ac5<=mef0f02[35];bnb562a<=mef0f02[36];irab156<=mef0f02[37];ho58ab4<=mef0f02[38];rgc55a2<=mef0f02[39];hq2ad12<={hbe3c76>>1,mef0f02[40]};cm56893<={zm1e3b7>>1,mef0f02[41]};epb4499<=mef0f02[42];fca24cc<=mef0f02[43];gd12662<=mef0f02[44];fc93314<=mef0f02[45];xy998a2<=mef0f02[46];qtcc512<=mef0f02[47];ls144a1<={go782f6>>1,mef0f02[48]};xya250b<=mef0f02[49];ux1285a<=mef0f02[50];tj942d5<=mef0f02[51];kfa16af<={gq15fa4>>1,mef0f02[52]};xyb57d<=mef0f02[53];nr5abeb<=mef0f02[54];rgd5f5f<={rgf483e>>1,mef0f02[55]};rvafafa<=mef0f02[56];ea7d7d7<=mef0f02[57];jcebeb8<=mef0f02[58];vv5f5c3<=mef0f02[59];ykfae1e<=mef0f02[60];pfd70f0<=mef0f02[61];zmb8786<=mef0f02[62];wjc3c32<=mef0f02[63];vk1e194<=mef0f02[64];ykf0ca2<={xj4aae6>>1,mef0f02[65]};ng86511<={jp55736>>1,mef0f02[66]};hd3288b<={irab9b7>>1,mef0f02[67]};fp9445e<=mef0f02[68];baa22f7<=mef0f02[69];zm117ba<=mef0f02[70];end -always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=yk775cd;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=vvd734e;ng1e1e0[2032]<=ukb9a76;ng1e1e0[2018]<=faf1dba;ng1e1e0[2017]<=nrcd3b1[0];ng1e1e0[1989]<=tj8edd3;ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1931]<=czd3c9f;ng1e1e0[1927]<=kd4ec72[0];ng1e1e0[1865]<=ayef1cc[0];ng1e1e0[1859]<=gq10832[0];ng1e1e0[1844]<=hdafd20;ng1e1e0[1815]<=fp9e4fd;ng1e1e0[1806]<=ho76394;ng1e1e0[1682]<=ui78e60;ng1e1e0[1674]<=qv90c78;ng1e1e0[1671]<=lf32197;ng1e1e0[1640]<=fn7e907;ng1e1e0[1582]<=czf27ee;ng1e1e0[1565]<=irb1ca3;ng1e1e0[1488]<=kdd9d10[0];ng1e1e0[1485]<=kf8057e;ng1e1e0[1326]<=gb6560e;ng1e1e0[1317]<=tucf141;ng1e1e0[1300]<=sj23348;ng1e1e0[1297]<=xj4aae6[0];ng1e1e0[1295]<=oh90cbf;ng1e1e0[1233]<=rgf483e[0];ng1e1e0[1210]<=hoc09ef[0];ng1e1e0[1189]<=cz4eb6c;ng1e1e0[1172]<=encc07d;ng1e1e0[1116]<=ld55e0b;ng1e1e0[1105]<=rv9bb69;ng1e1e0[1092]<=irab9b7[0];ng1e1e0[1087]<=ym97f1e;ng1e1e0[1082]<=tx_fifoavail;ng1e1e0[1023]<=gof5dd7;ng1e1e0[1009]<=zm1e3b7[0];ng1e1e0[932]<=sj1de39;ng1e1e0[929]<=pf74420[0];ng1e1e0[922]<=gq15fa4[0];ng1e1e0[837]<=xy20f9d;ng1e1e0[744]<=je1b674;ng1e1e0[742]<=lfb00af;ng1e1e0[663]<=ldecac1;ng1e1e0[648]<=mgad95;ng1e1e0[605]<=pfd813d[0];ng1e1e0[594]<=ng1f65;ng1e1e0[586]<=gd3980f[0];ng1e1e0[552]<=by69136;ng1e1e0[547]<=cb36f47;ng1e1e0[546]<=jp55736[0];ng1e1e0[543]<=ri865fc;ng1e1e0[504]<=hbe3c76[0];ng1e1e0[466]<=gqa3bc7;ng1e1e0[418]<=kfa41f3;ng1e1e0[372]<=mt236ce;ng1e1e0[371]<=rtf6015;ng1e1e0[331]<=ieb9e28;ng1e1e0[324]<=zx7e856;ng1e1e0[297]<=mr603ec;ng1e1e0[273]<=rte6de8;ng1e1e0[252]<=xjfc78e;ng1e1e0[233]<=jr94778[0];ng1e1e0[185]<=go782f6[0];ng1e1e0[162]<=qg6d3f4;ng1e1e0[136]<=kq5cdbd;ng1e1e0[126]<=zzbf8f1;ng1e1e0[116]<=os728ef;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[3]};ec31d79<=mef0f02[4];lf8ebc9<=mef0f02[5];dbaf275<={tj19519>>1,mef0f02[6]};ng2f6a2<=mef0f02[7];alc9d72<=mef0f02[8];kd4eb95<=mef0f02[9];ip75cac<=mef0f02[10];qvae565<=mef0f02[11];su72b2c<=mef0f02[12];oh95960<=mef0f02[13];qiacb04<=mef0f02[14];uv65820<=mef0f02[15];wl2c104<=mef0f02[16];uv60825<=mef0f02[17];vk412c<=mef0f02[18];ng20962<=mef0f02[19];ri4b12<=mef0f02[20];ls25893<=mef0f02[21];ay49c8f<={ep29d6d>>1,mef0f02[22]};an126a8<=mef0f02[23];je93544<=mef0f02[24];ep9aa22<=mef0f02[25];xwd5115<=mef0f02[26];pua88ab<=mef0f02[27];vx22ad4<={uv4b7df>>1,mef0f02[28]};gq156a7<=mef0f02[29];zx5a9cc<={fafbf6a>>1,mef0f02[30]};icd4e67<=mef0f02[31];vka7338<=mef0f02[32];ep399c2<=mef0f02[33];ofcce15<=mef0f02[34];qg670ad<=mef0f02[35];rv38568<=mef0f02[36];ldc2b46<=mef0f02[37];ks15a36<=mef0f02[38];lsad1b0<=mef0f02[39];ic68d83<=mef0f02[40];go46c18<=mef0f02[41];yz360c0<=mef0f02[42];phb0605<=mef0f02[43];pu8302e<=mef0f02[44];wl18173<=mef0f02[45];lqc0b9d<=mef0f02[46];ou5ceb<=mef0f02[47];mg2e759<=mef0f02[48];ne73ac8<=mef0f02[49];ym9d642<=mef0f02[50];byeb211<=mef0f02[51];jpc8451<={ww78015>>1,mef0f02[52]};zk4228e<=mef0f02[53];xy11473<=mef0f02[54];qv8a39b<=mef0f02[55];ip51cdd<=mef0f02[56];xl8e6ec<=mef0f02[57];lq73767<=mef0f02[58];ph9bb3b<=mef0f02[59];jpdd9df<=mef0f02[60];jpecefe<=mef0f02[61];os677f6<=mef0f02[62];end -always@* begin ng1e1e0[2047]<=anaeeb9;ng1e1e0[2046]<=tx_sndpausreq;ng1e1e0[2044]<=tx_sndpaustim[0];ng1e1e0[2040]<=wyb3e52;ng1e1e0[2033]<=ux9f290;ng1e1e0[2019]<=tj19519[0];ng1e1e0[1991]<=ho76394;ng1e1e0[1934]<=by52133;ng1e1e0[1929]<=bydf8eb;ng1e1e0[1898]<=jc63c02;ng1e1e0[1821]<=bycf546;ng1e1e0[1810]<=blfc75b;ng1e1e0[1749]<=fc9c68c;ng1e1e0[1707]<=xyea19;ng1e1e0[1666]<=uv4b7df[0];ng1e1e0[1630]<=ng30125;ng1e1e0[1595]<=qg4671a;ng1e1e0[1572]<=wl1d6f7;ng1e1e0[1506]<=fc25558;ng1e1e0[1450]<=nga2e8e;ng1e1e0[1440]<=vid0974;ng1e1e0[1384]<=oh9a12e;ng1e1e0[1370]<=ep29d6d[0];ng1e1e0[1366]<=tx_discfrm;ng1e1e0[1284]<=of5befd;ng1e1e0[1212]<=an8092a;ng1e1e0[1202]<=vvecbf5;ng1e1e0[1174]<=wj44d9d;ng1e1e0[1170]<=aa8748b;ng1e1e0[1142]<=ep338d1;ng1e1e0[1125]<=gq988c6;ng1e1e0[1097]<=dz55311;ng1e1e0[1041]<=shed49d;ng1e1e0[1023]<=gof5dd7;ng1e1e0[964]<=je2aac3;ng1e1e0[949]<=hq8c780;ng1e1e0[853]<=qi2b075;ng1e1e0[833]<=ps5d2df;ng1e1e0[815]<=ofc6024;ng1e1e0[753]<=sw24aab;ng1e1e0[720]<=xjc8b1c;ng1e1e0[714]<=icced42;ng1e1e0[692]<=hd13425;ng1e1e0[685]<=mec1d43;ng1e1e0[601]<=bl4f4d7;ng1e1e0[587]<=ui67dfc;ng1e1e0[585]<=je35187;ng1e1e0[562]<=db13118;ng1e1e0[520]<=fafbf6a[0];ng1e1e0[474]<=hbe3463;ng1e1e0[407]<=an18c04;ng1e1e0[376]<=fc4955;ng1e1e0[357]<=yma3c6e;ng1e1e0[300]<=ww6d020;ng1e1e0[293]<=gb5efc8;ng1e1e0[292]<=ww78015[0];ng1e1e0[281]<=yk62623;ng1e1e0[237]<=uk1a31e;ng1e1e0[203]<=oh23180;ng1e1e0[146]<=ww4c478;ng1e1e0[140]<=mred898;ng1e1e0[70]<=qi9db13;ng1e1e0[35]<=of6a4ed;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[2]};je3a537<={xl285a7>>1,mef0f02[3]};dzd29bb<={by42d3f>>1,mef0f02[4]};ww53ab0<=mef0f02[5];gq9d581<=mef0f02[6];jr377f1<=mef0f02[7];end -always@* begin ng1e1e0[2047]<=ls1fac;ng1e1e0[2046]<=oufd63[0];ng1e1e0[2044]<=xl285a7[0];ng1e1e0[2040]<=by42d3f[0];ng1e1e0[2033]<=pfd813d;ng1e1e0[2019]<=hoc09ef;ng1e1e0[1990]<=vk3f5eb;ng1e1e0[1023]<=yz803f5;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};ipd346d<=mef0f02[2];wl9a36c<=mef0f02[3];god1b64<=mef0f02[4];vk412c<=mef0f02[5];dm6c808<={ym9de6f>>1,mef0f02[6]};hq20217<={ps79bc0>>1,mef0f02[7]};ux85da<={cz6f01f>>1,mef0f02[8]};wl176a2<={fac07e0>>1,mef0f02[9]};neda8a5<={gq1f816>>1,mef0f02[10]};lsa2959<={sue058e>>1,mef0f02[11]};zza565a<={fp1638c>>1,mef0f02[12]};me596b8<={ph8e335>>1,mef0f02[13]};xj5ae09<={ls8cd7f>>1,mef0f02[14]};vkb827e<={ri35fdb>>1,mef0f02[15]};lf9f90<={kd7f6df>>1,mef0f02[16]};th7e43e<={aydb7eb>>1,mef0f02[17]};kf90fbd<={jcdfac1>>1,mef0f02[18]};co3ef60<={vieb05c>>1,mef0f02[19]};dobd804<={uic1713>>1,mef0f02[20]};hbec023<=mef0f02[21];en6011f<=mef0f02[22];end -always@* begin ng1e1e0[2047]<=tx_fifodata[0];ng1e1e0[2046]<=tx_fifoeof;ng1e1e0[2044]<=tx_fifoempty;ng1e1e0[2040]<=tx_fifoctrl;ng1e1e0[2032]<=qi2b075;ng1e1e0[2017]<=ym9de6f[0];ng1e1e0[1987]<=ps79bc0[0];ng1e1e0[1927]<=cz6f01f[0];ng1e1e0[1865]<=kd7f6df[0];ng1e1e0[1806]<=fac07e0[0];ng1e1e0[1682]<=aydb7eb[0];ng1e1e0[1565]<=gq1f816[0];ng1e1e0[1317]<=jcdfac1[0];ng1e1e0[1172]<=uic1713[0];ng1e1e0[1082]<=sue058e[0];ng1e1e0[1023]<=tx_discfrm;ng1e1e0[932]<=ri35fdb[0];ng1e1e0[594]<=su5c4c2;ng1e1e0[586]<=vieb05c[0];ng1e1e0[466]<=ls8cd7f[0];ng1e1e0[297]<=fcb898;ng1e1e0[233]<=ph8e335[0];ng1e1e0[116]<=fp1638c[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[5]};cm5681e<={vvf96fb>>1,mef0f02[6]};ng1497b<={fa69d8e>>1,mef0f02[7]};al7a68d<={tx_fifodata>>1,mef0f02[8]};ipd346d<=mef0f02[9];wl9a36c<=mef0f02[10];jcda897<=mef0f02[11];ay463af<={tx_sndpaustim>>1,mef0f02[12]};end918e<=mef0f02[13];god1b64<=mef0f02[14];ipd9356<=mef0f02[15];ps4d5ad<={cb90622>>1,mef0f02[16]};ipe2514<=mef0f02[17];ux3c4a2<=mef0f02[18];tw25ed4<={kd4ec72>>1,mef0f02[19]};jccaa2d<={ayef1cc>>1,mef0f02[20]};bn2d5d7<={gd3980f>>1,mef0f02[21]};ip6aebf<=mef0f02[22];dbaf275<={tj19519>>1,mef0f02[23]};ir12eca<={jr94778>>1,mef0f02[24]};ay49c8f<={ep29d6d>>1,mef0f02[25]};kd4eb95<=mef0f02[26];lf81c3e<=mef0f02[27];al70fbb<={nr5a6ca>>1,mef0f02[28]};qi3eee8<={tj9b2b4>>1,mef0f02[29]};end -always@* begin ng1e1e0[2047]<=gof5dd7;ng1e1e0[2046]<=anaeeb9;ng1e1e0[2044]<=phbae69;ng1e1e0[2040]<=yk775cd;ng1e1e0[2032]<=vk3f2df[0];ng1e1e0[2017]<=vvf96fb[0];ng1e1e0[1987]<=fa69d8e[0];ng1e1e0[1926]<=tx_fifodata[0];ng1e1e0[1804]<=tx_fifoeof;ng1e1e0[1803]<=tj19519[0];ng1e1e0[1560]<=tx_fifoempty;ng1e1e0[1558]<=jr94778[0];ng1e1e0[1550]<=cb90622[0];ng1e1e0[1072]<=tx_fifoavail;ng1e1e0[1069]<=ep29d6d[0];ng1e1e0[1052]<=ukb9a76;ng1e1e0[1023]<=ir3994e;ng1e1e0[901]<=encc07d;ng1e1e0[775]<=zk520c4;ng1e1e0[732]<=tj9b2b4[0];ng1e1e0[450]<=gd3980f[0];ng1e1e0[387]<=tx_fifoctrl;ng1e1e0[366]<=nr5a6ca[0];ng1e1e0[225]<=ayef1cc[0];ng1e1e0[193]<=tx_sndpausreq;ng1e1e0[183]<=sh7aa33;ng1e1e0[112]<=kd4ec72[0];ng1e1e0[96]<=tx_sndpaustim[0];ng1e1e0[91]<=bycf546;ng1e1e0[56]<=vvd734e;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};go781e5<={hdatain>>1,mef0f02[1]};zkc0f28<=mef0f02[2];yz7943<=mef0f02[3];mt3ca1c<=mef0f02[4];yke50e5<=mef0f02[5];cm4394f<={ene2fd7>>1,mef0f02[6]};tj1ca78<=mef0f02[7];ir29e31<={bldd558>>1,mef0f02[8]};jp4f18c<=mef0f02[9];cm78c67<=mef0f02[10];yxc6339<=mef0f02[11];ou319cd<=mef0f02[12];ls8ce69<=mef0f02[13];su6734b<=mef0f02[14];fncd2c5<={kdd3961>>1,mef0f02[15]};wj4b173<={cme586a>>1,mef0f02[16]};lqc5cea<={nr61a85>>1,mef0f02[17]};dm73a98<={uv6a174>>1,mef0f02[18]};wy9d4c2<=mef0f02[19];ww53088<={fn4f950>>1,mef0f02[20]};jpc2201<={cme5433>>1,mef0f02[21]};ec8807b<={hb50cca>>1,mef0f02[22]};ba1ec6<={gd332b3>>1,mef0f02[23]};dz7b199<={jccaceb>>1,mef0f02[24]};hbd8ccf<={yk5675a>>1,mef0f02[25]};shc667e<=mef0f02[26];hq99fad<={jceb401>>1,mef0f02[27]};nr7eb52<={tud0056>>1,mef0f02[28]};twad4b1<={do159c>>1,mef0f02[29]};ps52c5c<={os56710>>1,mef0f02[30]};irb171a<={xy9c400>>1,mef0f02[31]};ea5c6a6<={uk1001c>>1,mef0f02[32]};ie1a98e<={ou70c>>1,mef0f02[33]};yma6388<={nt1c306>>1,mef0f02[34]};aa31c40<=mef0f02[35];fp8e201<=mef0f02[36];qi8807e<={db6eb4>>1,mef0f02[37]};pu1f86<={ntbad37>>1,mef0f02[38]};ld7e198<={uxb4df5>>1,mef0f02[39]};ba86639<={tj37d69>>1,mef0f02[40]};ks98e5d<={wwf5a74>>1,mef0f02[41]};mt39747<={by69d0b>>1,mef0f02[42]};jc5d1e0<={nr742d4>>1,mef0f02[43]};ne4781c<={vkb535>>1,mef0f02[44]};cb3c0e2<={xj5a9ab>>1,mef0f02[45]};lf38a1<={wya6af8>>1,mef0f02[46]};she2877<={qvabe0a>>1,mef0f02[47]};je143bd<=mef0f02[48];ira1deb<=mef0f02[49];doef5c<=mef0f02[50];pubd710<={jp55d00>>1,mef0f02[51]};tueb882<=mef0f02[52];ui5c413<=mef0f02[53];end -always@* begin ng1e1e0[2047]<=hdatain[0];ng1e1e0[2046]<=hread_n;ng1e1e0[2044]<=hwrite_n;ng1e1e0[2040]<=hcs_n;ng1e1e0[2032]<=aye5ebc;ng1e1e0[2016]<=ene2fd7[0];ng1e1e0[1985]<=cb17ebd;ng1e1e0[1925]<=wwf5a74[0];ng1e1e0[1922]<=bldd558[0];ng1e1e0[1802]<=by69d0b[0];ng1e1e0[1796]<=ykeaac7;ng1e1e0[1556]<=nr742d4[0];ng1e1e0[1544]<=gq3baab;ng1e1e0[1505]<=uxb4df5[0];ng1e1e0[1324]<=gbf82ae;ng1e1e0[1316]<=jceb401[0];ng1e1e0[1200]<=jp55d00[0];ng1e1e0[1169]<=do159c[0];ng1e1e0[1163]<=uk1001c[0];ng1e1e0[1118]<=rge1837;ng1e1e0[1106]<=gd332b3[0];ng1e1e0[1065]<=vkb535[0];ng1e1e0[1041]<=nr61a85[0];ng1e1e0[1040]<=xw734fa;ng1e1e0[1023]<=haddr[0];ng1e1e0[962]<=tj37d69[0];ng1e1e0[752]<=ntbad37[0];ng1e1e0[707]<=hb74035;ng1e1e0[662]<=zx5f055;ng1e1e0[658]<=swb3ad0;ng1e1e0[600]<=ykc1574;ng1e1e0[584]<=tud0056[0];ng1e1e0[581]<=xy9c400[0];ng1e1e0[559]<=nt1c306[0];ng1e1e0[553]<=hb50cca[0];ng1e1e0[520]<=cme586a[0];ng1e1e0[376]<=db6eb4[0];ng1e1e0[353]<=epae806;ng1e1e0[331]<=qvabe0a[0];ng1e1e0[329]<=yk5675a[0];ng1e1e0[290]<=os56710[0];ng1e1e0[279]<=ou70c[0];ng1e1e0[276]<=cme5433[0];ng1e1e0[260]<=kdd3961[0];ng1e1e0[188]<=zzc1ba;ng1e1e0[165]<=wya6af8[0];ng1e1e0[164]<=jccaceb[0];ng1e1e0[138]<=fn4f950[0];ng1e1e0[130]<=qv9f4e5;ng1e1e0[82]<=xj5a9ab[0];ng1e1e0[69]<=pu353e5;ng1e1e0[65]<=kdd3e9c;ng1e1e0[34]<=uv6a174[0];ng1e1e0[32]<=gd9a7d3;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};ho5da61<={kdc64dc>>1,mef0f02[1]};shed30a<=mef0f02[2];ne69855<=mef0f02[3];ui4c2aa<=mef0f02[4];ecaa87<={iccb7a2>>1,mef0f02[5]};phaa1c7<={kqde88d>>1,mef0f02[6]};ie871f6<={vka234a>>1,mef0f02[7]};fnc7d8f<={gq8d292>>1,mef0f02[8]};nrf63f0<={jp4a483>>1,mef0f02[9]};kf8fc3d<={gq920fa>>1,mef0f02[10]};ayf0f67<={je83e85>>1,mef0f02[11]};tj3d9c8<={qgfa150>>1,mef0f02[12]};ic6723e<={yz8540a>>1,mef0f02[13]};ldc8f84<={hb502a2>>1,mef0f02[14]};tu47c27<=mef0f02[15];wy3e13a<=mef0f02[16];ayf09d1<=mef0f02[17];fp84e89<=mef0f02[18];vx2744f<=mef0f02[19];end -always@* begin ng1e1e0[2047]<=kdc64dc[0];ng1e1e0[2046]<=xy9372f;ng1e1e0[2044]<=mdi;ng1e1e0[2040]<=lf2de5b;ng1e1e0[2032]<=iccb7a2[0];ng1e1e0[2017]<=kqde88d[0];ng1e1e0[1987]<=vka234a[0];ng1e1e0[1926]<=gq8d292[0];ng1e1e0[1804]<=jp4a483[0];ng1e1e0[1614]<=wya8be;ng1e1e0[1561]<=gq920fa[0];ng1e1e0[1180]<=al545f0;ng1e1e0[1074]<=je83e85[0];ng1e1e0[1023]<=gd18c9b[0];ng1e1e0[807]<=tj81517;ng1e1e0[625]<=wl17c2b;ng1e1e0[403]<=hb502a2[0];ng1e1e0[312]<=nga2f85;ng1e1e0[201]<=yz8540a[0];ng1e1e0[100]<=qgfa150[0];end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[0]};hbc2a27<=mef0f02[1];ec1513e<=mef0f02[2];twa89f1<=mef0f02[3];sh44f8a<=mef0f02[4];vx27c55<=mef0f02[5];gq3e2af<=mef0f02[6];dmf1579<=mef0f02[7];yz8abca<=mef0f02[8];rt55e54<={rxd_pos>>1,mef0f02[9]};rvaf2a6<={rxd_neg>>1,mef0f02[10]};by79536<=mef0f02[11];lqca9b2<=mef0f02[12];qt54d92<=mef0f02[13];gqa6c94<=mef0f02[14];sj364a1<=mef0f02[15];rib250d<=mef0f02[16];ie9286b<=mef0f02[17];bn94359<=mef0f02[18];wla1acf<=mef0f02[19];mtd67c<=mef0f02[20];me59f26<={pf748cc>>1,mef0f02[21]};tu7c982<={an2333d>>1,mef0f02[22]};qv2609a<={kdccf66>>1,mef0f02[23]};ou826a2<={dm66a7e>>1,mef0f02[24]};an9a88e<={uka9f9a>>1,mef0f02[25]};qgd4475<=mef0f02[26];lsa23a9<=mef0f02[27];ba11d4a<=mef0f02[28];tj8ea52<=mef0f02[29];cz75296<=mef0f02[30];oua94b4<=mef0f02[31];jp4a5a1<=mef0f02[32];dm52d0f<=mef0f02[33];ls9687b<=mef0f02[34];yzb43db<=mef0f02[35];swf6e4<={hoc0bc3>>1,mef0f02[36]};zx7b721<=mef0f02[37];ykdb90f<=mef0f02[38];czdc879<=mef0f02[39];dme43cc<=mef0f02[40];sw21e63<=mef0f02[41];ecf318<=mef0f02[42];ps798c1<=mef0f02[43];yxcc60b<=mef0f02[44];ir182e2<={xy2aaf4>>1,mef0f02[45]};cmc1715<=mef0f02[46];kq5c542<={sh5e8fd>>1,mef0f02[47]};uve2a11<={faf47ed>>1,mef0f02[48]};ym1508d<={mga3f6a>>1,mef0f02[49]};xya8469<=mef0f02[50];by4234b<=mef0f02[51];ng11a5b<=mef0f02[52];ie8d2da<=mef0f02[53];rg696d0<=mef0f02[54];gb4b683<=mef0f02[55];gb5b41d<=mef0f02[56];jcda0ec<=mef0f02[57];hod0762<=mef0f02[58];end -always@* begin ng1e1e0[2047]<=zx6e28f;ng1e1e0[2046]<=pf7147e;ng1e1e0[2044]<=ned0632;ng1e1e0[2040]<=kq53683;ng1e1e0[2032]<=rx_dv_pos;ng1e1e0[2016]<=rx_dv_neg;ng1e1e0[1985]<=rx_er_pos;ng1e1e0[1922]<=rx_er_neg;ng1e1e0[1867]<=tu693a4;ng1e1e0[1804]<=sh5e8fd[0];ng1e1e0[1797]<=rxd_pos[0];ng1e1e0[1761]<=th50aab;ng1e1e0[1686]<=ui49d23;ng1e1e0[1623]<=mr5136c;ng1e1e0[1561]<=faf47ed[0];ng1e1e0[1558]<=wl9a1bf;ng1e1e0[1547]<=rxd_neg[0];ng1e1e0[1542]<=hoc0bc3[0];ng1e1e0[1490]<=nr74349;ng1e1e0[1475]<=xy2aaf4[0];ng1e1e0[1413]<=pf7e686;ng1e1e0[1409]<=xla5605;ng1e1e0[1400]<=xw6cad8;ng1e1e0[1324]<=pf748cc[0];ng1e1e0[1200]<=kdccf66[0];ng1e1e0[1199]<=fc89b65;ng1e1e0[1074]<=mga3f6a[0];ng1e1e0[1068]<=ng86fe2;ng1e1e0[1047]<=qv9f880;ng1e1e0[1037]<=ie5e1b;ng1e1e0[1023]<=fncdc51[0];ng1e1e0[933]<=ana1a4e;ng1e1e0[902]<=dz557a3;ng1e1e0[880]<=byca155;ng1e1e0[811]<=cz6a26d;ng1e1e0[779]<=zxf3437;ng1e1e0[771]<=wy2b02f;ng1e1e0[745]<=ie2e869;ng1e1e0[706]<=uka9f9a[0];ng1e1e0[704]<=ieb6958;ng1e1e0[700]<=kq6d95b;ng1e1e0[600]<=an2333d[0];ng1e1e0[440]<=yxd942a;ng1e1e0[405]<=kded44d;ng1e1e0[372]<=uk5d0d;ng1e1e0[353]<=dm66a7e[0];ng1e1e0[352]<=ymb6d2b;ng1e1e0[350]<=xw4db2b;ng1e1e0[220]<=ls1b285;ng1e1e0[202]<=kdfda89;ng1e1e0[186]<=cb80ba1;ng1e1e0[176]<=vk96da5;ng1e1e0[110]<=enc3650;ng1e1e0[101]<=mg1fb51;ng1e1e0[93]<=kde202e;ng1e1e0[88]<=db37f12;ng1e1e0[55]<=ay786ca;ng1e1e0[46]<=rtfc405;ng1e1e0[27]<=ri2f0d9;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f>1,mef0f02[1]};go781e5<={hdatain>>1,mef0f02[2]};mt3ca1c<=mef0f02[3];yz7943<=mef0f02[4];zkc0f28<=mef0f02[5];al7a68d<={tx_fifodata>>1,mef0f02[6]};jcda897<=mef0f02[7];ipd346d<=mef0f02[8];wl9a36c<=mef0f02[9];ay463af<={tx_sndpaustim>>1,mef0f02[10]};end918e<=mef0f02[11];god1b64<=mef0f02[12];wwde5f9<=mef0f02[13];wwd1063<=mef0f02[14];ks9259a<={ie2197a>>1,mef0f02[15]};ks92cd0<=mef0f02[16];pu96681<=mef0f02[17];ir29e31<={bldd558>>1,mef0f02[18]};jp4f18c<=mef0f02[19];vid028c<={ned0f15>>1,mef0f02[20]};bn81463<=mef0f02[21];iea31e<=mef0f02[22];wj518f1<={mre2a84>>1,mef0f02[23]};do8c78c<=mef0f02[24];dm63c62<=mef0f02[25];tw1e313<=mef0f02[26];jcf189a<=mef0f02[27];xy8c4d3<=mef0f02[28];go6269a<={ep29dbb>>1,mef0f02[29]};ph134d0<=mef0f02[30];an9a686<=mef0f02[31];ofd3434<=mef0f02[32];sj9a1a4<=mef0f02[33];byd0d24<=mef0f02[34];ri86922<=mef0f02[35];gq34912<=mef0f02[36];ana4891<=mef0f02[37];qi2448c<=mef0f02[38];vx22461<={xwe47ba>>1,mef0f02[39]};ep1230e<={yz23dd3>>1,mef0f02[40]};rv91874<={fc1ee9d>>1,mef0f02[41]};pu8c3a6<={gbf74eb>>1,mef0f02[42]};xj61d32<={bnba75d>>1,mef0f02[43]};twe996<={qtd3aef>>1,mef0f02[44]};dz74cb2<={ks9d77d>>1,mef0f02[45]};aaa6597<={tuebbe9>>1,mef0f02[46]};tj32cb8<={vi5df4b>>1,mef0f02[47]};vk965c6<={ykefa5a>>1,mef0f02[48]};vkb2e32<={ic7d2d1>>1,mef0f02[49]};ks97192<={rte9688>>1,mef0f02[50]};lsb8c90<={gb4b447>>1,mef0f02[51]};shc6483<=mef0f02[52];vx3241d<={qgd11ee>>1,mef0f02[53]};ou920ef<=mef0f02[54];sj90778<=mef0f02[55];ba83bc5<=mef0f02[56];kf1de2a<=mef0f02[57];osef154<=mef0f02[58];cm78aa0<=mef0f02[59];xwc5501<=mef0f02[60];do2a80a<=mef0f02[61];yx54053<={hq965a2>>1,mef0f02[62]};zza029d<={ngb2d12>>1,mef0f02[63]};ng14ef<=mef0f02[64];aaa77a<=mef0f02[65];ic53bd1<=mef0f02[66];ym9de89<=mef0f02[67];wwef448<={ou92714>>1,mef0f02[68]};qt7a240<={ri938a0>>1,mef0f02[69]};end -always@* begin ng1e1e0[2047]<=haddr[0];ng1e1e0[2046]<=hdatain[0];ng1e1e0[2044]<=hcs_n;ng1e1e0[2040]<=hwrite_n;ng1e1e0[2033]<=hread_n;ng1e1e0[2019]<=tx_fifodata[0];ng1e1e0[1994]<=gbf74eb[0];ng1e1e0[1990]<=tx_fifoavail;ng1e1e0[1981]<=tj84a76;ng1e1e0[1965]<=lsb7722;ng1e1e0[1940]<=bnba75d[0];ng1e1e0[1939]<=bldd558[0];ng1e1e0[1933]<=tx_fifoeof;ng1e1e0[1914]<=ba253b7;ng1e1e0[1883]<=ohbb913;ng1e1e0[1832]<=qtd3aef[0];ng1e1e0[1831]<=ykeaac7;ng1e1e0[1819]<=tx_fifoempty;ng1e1e0[1785]<=xwe47ba[0];ng1e1e0[1781]<=ep29dbb[0];ng1e1e0[1778]<=ie2197a[0];ng1e1e0[1740]<=hoee257;ng1e1e0[1719]<=mrdc89c;ng1e1e0[1634]<=mrd6596;ng1e1e0[1616]<=ks9d77d[0];ng1e1e0[1615]<=ned0f15[0];ng1e1e0[1591]<=tx_sndpaustim[0];ng1e1e0[1579]<=zm96892;ng1e1e0[1522]<=yz23dd3[0];ng1e1e0[1515]<=cz4eddc;ng1e1e0[1508]<=fpcbd0;ng1e1e0[1470]<=db1391e;ng1e1e0[1432]<=bl712ba;ng1e1e0[1406]<=ri938a0[0];ng1e1e0[1391]<=fae44e4;ng1e1e0[1286]<=ic7d2d1[0];ng1e1e0[1271]<=mg15425;ng1e1e0[1221]<=bab2cb4;ng1e1e0[1184]<=tuebbe9[0];ng1e1e0[1182]<=ie878aa;ng1e1e0[1135]<=tx_sndpausreq;ng1e1e0[1111]<=gdb4493;ng1e1e0[1051]<=gb4b447[0];ng1e1e0[1023]<=reset_n;ng1e1e0[997]<=fc1ee9d[0];ng1e1e0[990]<=bl5094e;ng1e1e0[982]<=vi76ee4;ng1e1e0[969]<=yx65e87;ng1e1e0[892]<=ls9c8f7;ng1e1e0[889]<=ignore_pkt;ng1e1e0[870]<=nt3dc4a;ng1e1e0[817]<=hq895d6;ng1e1e0[789]<=ngb2d12[0];ng1e1e0[735]<=lf22723;ng1e1e0[703]<=ou92714[0];ng1e1e0[643]<=ykefa5a[0];ng1e1e0[635]<=mre2a84[0];ng1e1e0[525]<=rte9688[0];ng1e1e0[495]<=hdaa129;ng1e1e0[444]<=rx_fifo_full;ng1e1e0[435]<=lq47b89;ng1e1e0[394]<=hq965a2[0];ng1e1e0[351]<=ep124e2;ng1e1e0[321]<=vi5df4b[0];ng1e1e0[317]<=oh3c550;ng1e1e0[222]<=tx_fifoctrl;ng1e1e0[217]<=ks88f71;ng1e1e0[175]<=vka249c;ng1e1e0[108]<=qgd11ee[0];ng1e1e0[54]<=hb5a23d;end assign epd660 = ng1e1e0,mef0f02 = ui59826; initial begin tj848e3 = $fopen(".fred"); $fdisplay( tj848e3, "%3h\n%3h", (yke0444 >> 4) & of44359, (yke0444 >> (ba1110d+4)) & of44359 ); $fclose(tj848e3); $readmemh(".fred", uv60984); end always @ (epd660) begin sj26123 = uv60984[1]; for (aa2471f=0; aa2471f 0} { - for {set i 0} {$i < $argc} {incr i 2} { - set temp [lindex $argv $i] - set temp [string range $temp 1 end] - lappend argv_list $temp - lappend value_list [lindex $argv [expr $i+1]] - } - foreach argument $argv_list value $value_list { - switch $argument { - "cmd" {set Para(cmd) $value;} - } - } - } -} - -set Para(ProjectPath) "/home/greg/projects/trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35" -set Para(ModuleName) "tsmac35" -set Para(lib) "/home/greg/trispeed_mac_v3.5/lib" -set Para(CoreName) "Tri-Speed Ethernet MAC" -set Para(arch) "ep5c00" -set Para(family) "latticeecp3" -set Para(Family) "latticeecp3" -set Para(design) "VHDL" -set Para(install_dir) "/opt/lattice/diamond/1.4.2.105/bin/lin/../.." -set Para(Bin) "/opt/lattice/diamond/1.4.2.105/bin/lin" -set Para(SpeedGrade) "Para(spd)" -set Para(FPGAPath) "/opt/lattice/diamond/1.4.2.105/bin/lin/../../ispfpga/bin/sol" - -lappend auto_path "/home/greg/trispeed_mac_v3.5/gui" - -lappend auto_path "/home/greg/trispeed_mac_v3.5/script" -package require Core_Generate - -lappend auto_path "/opt/lattice/diamond/1.4.2.105/tcltk/lib/ipwidgets/ispipbuilder/../runproc" -package require runcmd - - -set Para(result) [GenerateCore] diff --git a/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn208256208256.ngo b/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn208256208256.ngo deleted file mode 100644 index f89c6c1887090fe81f0e9715e5e30d305b9f0228..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 11243 zcmai44RBo5bzZIfb7U|U;09x3TZ0u>ZVK$mU@tafuPm*lMcUPBCGUH-1zOt@m474) z+Zd4oRzhs45L2ZziD(imU?$@x5CjHlf+0#e&4>VwO5LKSoz{&RSLLUpgia7~ZF;_Q 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zRPuSQSs^OzbG)e^0V2M4f_n zNF8+=-ZWA2`M;jB;w-$maaPa4ds`WmK(I-6IS+5Fk=dW{4wLEy1YZ_<*ea3&HJPW=-&hE2t~*?v)AtM)2->X8*vOUqfAmx4o?R7on#my9V$7WbJi$ z$E2tFx+R}?9Al@N!7KMmx;2Mat7Fyzu7f}zFQl3<-hxG zfcF>9(ycAb2C1gOE6)LRYX@(ml55+;?2J+!;5{R!bwp^CidiR^Zx<=yy;RPuGrX5& zf-dl0wJ=M5%I4N6)eQyBMBP!)yp~z=lQ%z1r+T8GEw8*=IttR_%zD9WOi;aHzNLoh zgMw~yMqd=9S29aJ4$X^G{ZMeD^xcR8m1HWIHp(rOd>neKpM3*RFjPqmM1e+b-9a!9 z)G`~4f=tWXUPOzH>rZaNJFcjP#XI};i#)y)SL)%%H z-Hd`er7sf&cO{r_hqROlrhn=wGfaO*sM}!rrINZG=Aj}B zij)=1teA9f4V8_eo=wykO!6qHJ5bcSips$xZy9BSR~{30OTO}KVVqg=m1n*fmHZvh zN>TFN7i$}s-G!jbPbJ@nF~vb8e+P6lLM7jaF+QzpbUj zlC8^FWv7;92|sc}5Rw4;!jG7U;FeNY+=MQe_gHq}@vub$Elye#LZLQ5!GKg32omI1 z6sJuAZ6d{N5``c|Vp~Z>T7%LOZAa5V+n#(+{`<`LoOAEFnc3{Sch9?rn!Jaxp_?S{ zVQg$9%|U#mW+3ljZ0(mavgTrmo;7F5dlQoHaa)ub9tcLZ6BP;oUx>tfhp%~a|c=9f^b zfL)#yR9y zu}>iPQH_w^7eg&t*CUx%P1=Cu_%x{+$qAVx>4H(HvC;)&Y6-PXNEYbYHY2I~tt|P~ zZAhF}=?^=kgCzZ7=lV%C7%^OF3xZ$h99t3mw360s`0m@9z0}RUQ$=k%vJa_s2a2v+ z)SgDpWwqAAxtULGCyKiINU}>vSCgK>yp~SVZrBf`NK)N#pORE}O!TNpbw@~Zk?M|H zbVYk$|EHJMy|8aYNc&)4)!FJ`U(z}D!)}ey`aJAEDjk6RN)5Go*e5jNAnfBxFTg&m z;~j#%-%r28u=jM6j=wnIQSm{D+RLc; zsEH&e(F0li7Aw;_ubf18>)PZby4|CnJnN0=BgwPg8udGg#K8cyQ%LM=B)x*fsubx} zB&O+Xe?X$lP?O#qgLRZtbP;8_nIzdgjZKkc_p~mb)QOUTZ}xXkI$dY`Gs=c} zv`T&AX+x4*k#_h=?_%D+)GGHQ?Nw_RqFVyAcBAap2p;4KvK4XC`zVd*-{mTT zPgPO-8%C!xNpi-sUB{Cixj7+fJ;+_tNxFt$O$X^i6m|BH`_`;h-{&?@KhvtlGUmtUxK6QlmpFJ)wXjzU*+{sQLbero@PIimAQ=iUX()R%$6 z-Y1?9lysqNOH&TdbP?Ozxuu4lRJJb=Hin(e(wy??<=rAswV-#_d7{n z#Urt5(%0Y(4v?hcvQEeQI))F`33CCN^fTz22D4Tpro&X# z({BdMI*(Kgv!j-DAI#1esRU+s38@t3IYYW1X0PTl69pTqs67DdW+iDB-0nWoY$S*G zLx%4`B(obyVI)Udr0*d)qLVZS$zX`|eI)OSljb6+XJoz~AQ{k+=b`*Wgx2{;-mbYs zkQ~-8W%w4r8KLWV2+pVmYEd|&dq`z)#%7Yr;pBu#3*nd=(huR}_L5?7@(gJaoS^zG zhO@Yd+QTR~tPvHkKJchXw~-QyGf8pe{7pv=-%FBby*sK&D`CFVL6WYVp)g6ha*k2@G0fN|YO7#OCP_MV z=Eg|UsdHQdNjh~-s3)z4nb=2?o}C3HBEk&=*CBm8IY@?2`kd)Gmv0?%OVjjw0+YuENKYcy0ckzVsV33}xYso2YPe@~yp3>Q zucq}Ea9d)eO>oodw;67$j`B;PMp~bO+or4h72NhJYBg}*h>*6xeKSnj3ioV3WcaoT z^^txJ_nc>1,ea5c9d9[1]};bn3da3f<=ea5c9d9[2];qted1ff<=ea5c9d9[3];ww68ffd<=ea5c9d9[4];ps47fe8<=ea5c9d9[5];ri3ff42<=ea5c9d9[6];icffa12<=ea5c9d9[7];qtfd090<=ea5c9d9[8];cze8484<=ea5c9d9[9];wl1212b<={cb1d810>>1,ea5c9d9[10]};ep9095c<={fnec084>>1,ea5c9d9[11]};ls25727<={ep213d>>1,ea5c9d9[12]};end -always@* begin ec2b93b[2047]<=ald93fd[0];ec2b93b[2046]<=shc9fed;ec2b93b[2044]<=zx4ff6d;ec2b93b[2040]<=kf3941a;ec2b93b[2032]<=zkfb248;ec2b93b[2016]<=ald9243;ec2b93b[1984]<=shc921d;ec2b93b[1920]<=su490ec;ec2b93b[1793]<=tu48760;ec2b93b[1539]<=cb1d810[0];ec2b93b[1030]<=fnec084[0];ec2b93b[1023]<=mtbb27f;ec2b93b[13]<=ep213d[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[0]};aa21756<=ea5c9d9[1];qted1ff<=ea5c9d9[2];rg5d58a<=ea5c9d9[3];su56299<={en41ecd>>1,ea5c9d9[4]};kf8a644<={ksf66d>>1,ea5c9d9[5]};ls99128<={nr7b369>>1,ea5c9d9[6]};ip44a1f<={ipd9b4f>>1,ea5c9d9[7]};db287eb<={blcda7c>>1,ea5c9d9[8]};uk1faf8<={qg6d3e7>>1,ea5c9d9[9]};xwebe0c<={xw69f39>>1,ea5c9d9[10]};mrf831e<={zx4f9ca>>1,ea5c9d9[11]};lfc7a1<={xw7ce56>>1,ea5c9d9[12]};ps63d0e<=ea5c9d9[13];ls1e873<=ea5c9d9[14];byf439b<=ea5c9d9[15];doe6d4<={ic56722>>1,ea5c9d9[16]};ho736a3<=ea5c9d9[17];jr9b51b<=ea5c9d9[18];hoda8de<=ea5c9d9[19];uid46f3<=ea5c9d9[20];qia3799<=ea5c9d9[21];pu1bcc8<=ea5c9d9[22];gode643<=ea5c9d9[23];ldf3218<=ea5c9d9[24];thc863b<={fne60e5>>1,ea5c9d9[25]};gd18ef1<={ng83972>>1,ea5c9d9[26]};ldc778c<=ea5c9d9[27];ou3bc67<=ea5c9d9[28];kqde338<=ea5c9d9[29];psf19c0<=ea5c9d9[30];tw8ce03<=ea5c9d9[31];ea6701b<=ea5c9d9[32];zz380d8<=ea5c9d9[33];vic06c6<=ea5c9d9[34];vk1b197<={jr95a2>>1,ea5c9d9[35]};wjc65d6<={me568b6>>1,ea5c9d9[36]};bn32eb5<=ea5c9d9[37];gq975ae<=ea5c9d9[38];ipd6b86<={gqb631f>>1,ea5c9d9[39]};bnb5c35<=ea5c9d9[40];mtae1af<=ea5c9d9[41];of70d7c<=ea5c9d9[42];ls86be5<=ea5c9d9[43];ls35f2a<=ea5c9d9[44];ps7ca9f<={kd6a63e>>1,ea5c9d9[45]};pu2a7d9<={co98fa0>>1,ea5c9d9[46]};kq53eca<=ea5c9d9[47];qv9f651<=ea5c9d9[48];lqfb28c<=ea5c9d9[49];shd9463<=ea5c9d9[50];faca31d<=ea5c9d9[51];yx518eb<=ea5c9d9[52];tw8c75c<=ea5c9d9[53];by63ae2<=ea5c9d9[54];ep1d713<=ea5c9d9[55];xweb89d<=ea5c9d9[56];ay5c4eb<=ea5c9d9[57];end -always@* begin ec2b93b[2047]<=qtedba5;ec2b93b[2046]<=zx4ff6d;ec2b93b[2044]<=uve83d9;ec2b93b[2040]<=en41ecd[0];ec2b93b[2032]<=ksf66d[0];ec2b93b[2017]<=nr7b369[0];ec2b93b[1987]<=ipd9b4f[0];ec2b93b[1980]<=lqf4030;ec2b93b[1963]<=xlb004a;ec2b93b[1942]<=mg82e7a;ec2b93b[1926]<=blcda7c[0];ec2b93b[1921]<=fac0f30;ec2b93b[1913]<=lfa0182;ec2b93b[1903]<=dm63e6a;ec2b93b[1879]<=cb80256;ec2b93b[1837]<=ux173d0;ec2b93b[1805]<=qg6d3e7[0];ec2b93b[1795]<=ux7983;ec2b93b[1783]<=co98fa0[0];ec2b93b[1778]<=ecc17;ec2b93b[1758]<=sw1f353;ec2b93b[1710]<=jr95a2[0];ec2b93b[1679]<=ic56722[0];ec2b93b[1627]<=mgb9e84;ec2b93b[1562]<=xw69f39[0];ec2b93b[1543]<=fne60e5[0];ec2b93b[1519]<=fnc7d00;ec2b93b[1509]<=nt60b9;ec2b93b[1499]<=anb18f9;ec2b93b[1469]<=dzf9a98;ec2b93b[1398]<=vka2d8c;ec2b93b[1373]<=me568b6[0];ec2b93b[1310]<=wya34af;ec2b93b[1207]<=zkcf421;ec2b93b[1144]<=rtd2bc0;ec2b93b[1076]<=zx4f9ca[0];ec2b93b[1039]<=ng83972[0];ec2b93b[1023]<=nt32741[0];ec2b93b[990]<=ou3e806;ec2b93b[981]<=vk96009;ec2b93b[971]<=fc305cf;ec2b93b[960]<=kq781e6;ec2b93b[951]<=do8c7cd;ec2b93b[891]<=kd6a63e[0];ec2b93b[839]<=hocace4;ec2b93b[749]<=gqb631f[0];ec2b93b[699]<=gdb45b1;ec2b93b[572]<=ks1a578;ec2b93b[490]<=ou92c01;ec2b93b[480]<=phaf03c;ec2b93b[419]<=ux3959c;ec2b93b[245]<=ic72580;ec2b93b[240]<=ux95e07;ec2b93b[209]<=kde72b3;ec2b93b[122]<=sw2e4b0;ec2b93b[104]<=xw7ce56[0];ec2b93b[61]<=kqe5c96;ec2b93b[30]<=db1cb92;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162= 7'h42); - - -assign wy825ad = cmde2e8 & ~pffcf51; -assign yz904b5 = pu14c26 & ~ph320fc & ~ba30990 & ~nt84c83; - - -assign zm9c42e = yz8fb84 & fnc2984[18]; - - - - - - -assign ou2e705 = (pu14c26 | rx_write) & xw5d016 & ~ph320fc & ~ba30990; - -always@* begin cmde2e8<=ea5c9d9[0];dmf1740<=ea5c9d9[1];zz8ba02<={ie9dcf2>>1,ea5c9d9[2]};xw5d016<=ea5c9d9[3];fn4059d<={ne73c82>>1,ea5c9d9[4]};bn16774<={zk79681>>1,ea5c9d9[5]};wy9dd30<={pf5a051>>1,ea5c9d9[6]};fn74c03<={vk8ceb3>>1,ea5c9d9[7]};pu300f8<={vk3acd8>>1,ea5c9d9[8]};qv807c2<=ea5c9d9[9];bn3e14<=ea5c9d9[10];ie1f0a6<=ea5c9d9[11];fnc2984<={ww77ce2>>1,ea5c9d9[12]};pu14c26<=ea5c9d9[13];yma6132<=ea5c9d9[14];ba30990<=ea5c9d9[15];nt84c83<=ea5c9d9[16];gd2641f<=ea5c9d9[17];ph320fc<=ea5c9d9[18];ux907e7<=ea5c9d9[19];gq1f9ea<={xy9c142>>1,ea5c9d9[20]};pffcf51<=ea5c9d9[21];hd3d47d<={jr284c0>>1,ea5c9d9[22]};sh51f70<={db1303b>>1,ea5c9d9[23]};yz8fb84<=ea5c9d9[24];os7dc24<=ea5c9d9[25];psee121<=ea5c9d9[26];mr7090a<=ea5c9d9[27];end -always@* begin ec2b93b[2047]<=lq73b9e;ec2b93b[2046]<=ie9dcf2[0];ec2b93b[2044]<=rx_fifo_full;ec2b93b[2040]<=ne73c82[0];ec2b93b[2032]<=zk79681[0];ec2b93b[2017]<=pf5a051[0];ec2b93b[1987]<=vk8ceb3[0];ec2b93b[1926]<=vk3acd8[0];ec2b93b[1921]<=db1303b[0];ec2b93b[1805]<=gqb3614;ec2b93b[1795]<=gq981de;ec2b93b[1679]<=kde2173;ec2b93b[1562]<=bn9b0a1;ec2b93b[1543]<=nec0ef1;ec2b93b[1310]<=sw10b9c;ec2b93b[1144]<=ou2e705;ec2b93b[1076]<=xjd850e;ec2b93b[1039]<=gd778b;ec2b93b[1023]<=pf6e773;ec2b93b[960]<=jr284c0[0];ec2b93b[839]<=zm9c42e;ec2b93b[572]<=yz85ce0;ec2b93b[480]<=sue0a13;ec2b93b[419]<=nrf3885;ec2b93b[240]<=xy9c142[0];ec2b93b[209]<=uxbe710;ec2b93b[104]<=ww77ce2[0];ec2b93b[30]<=aa3bc5d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[0]};qted1ff<=ea5c9d9[1];pfc2f4a<=ea5c9d9[2];rg5d58a<=ea5c9d9[3];babd2b5<=ea5c9d9[4];bl4ad57<={fc30be7>>1,ea5c9d9[5]};me56abe<=ea5c9d9[6];hdb55f1<=ea5c9d9[7];ne57c77<={osfa629>>1,ea5c9d9[8]};ohbe3bb<=ea5c9d9[9];psf1ddd<=ea5c9d9[10];vx8eeeb<=ea5c9d9[11];qg7775e<=ea5c9d9[12];cbbbaf1<=ea5c9d9[13];vvdd78c<=ea5c9d9[14];dmebc67<=ea5c9d9[15];yx5e33b<=ea5c9d9[16];xwf19dc<=ea5c9d9[17];ww6771b<={pff6af9>>1,ea5c9d9[18]};ks3b8d8<=ea5c9d9[19];gbdc6c0<=ea5c9d9[20];pfe3605<=ea5c9d9[21];hq1b02e<=ea5c9d9[22];nec0b97<={xw76bb8>>1,ea5c9d9[23]};ay5c4eb<=ea5c9d9[24];end -always@* begin ec2b93b[2047]<=zx4ff6d;ec2b93b[2046]<=thec185;ec2b93b[2044]<=uve83d9;ec2b93b[2040]<=nt617c;ec2b93b[2032]<=fc30be7[0];ec2b93b[2017]<=qv278c;ec2b93b[1987]<=do9c880;ec2b93b[1926]<=osfa629[0];ec2b93b[1804]<=qgefd3d;ec2b93b[1803]<=xw76bb8[0];ec2b93b[1560]<=zx7e9e9;ec2b93b[1558]<=zkcf421;ec2b93b[1550]<=lq737b5;ec2b93b[1072]<=vif4f4e;ec2b93b[1052]<=ph9bdab;ec2b93b[1023]<=nt32741[0];ec2b93b[901]<=rtf9dae;ec2b93b[775]<=kd4e6f6;ec2b93b[450]<=xj5f3b5;ec2b93b[387]<=fne9cde;ec2b93b[225]<=gdabe76;ec2b93b[193]<=nt3d39b;ec2b93b[112]<=rvb57ce;ec2b93b[96]<=pua7a73;ec2b93b[56]<=pff6af9[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[0]};ymbc546<=ea5c9d9[1];ofe2a30<=ea5c9d9[2];co15185<=ea5c9d9[3];doa8c29<=ea5c9d9[4];su4614a<={wjc9dd9>>1,ea5c9d9[5]};tw30a51<={jp50046>>1,ea5c9d9[6]};an8528b<={cb8de2>>1,ea5c9d9[7]};cb2945c<={yk46f15>>1,ea5c9d9[8]};end -always@* begin ec2b93b[2047]<=rvc2c9;ec2b93b[2046]<=nr6164e;ec2b93b[2044]<=vkb277;ec2b93b[2041]<=ui593bb;ec2b93b[2034]<=wjc9dd9[0];ec2b93b[2021]<=jp50046[0];ec2b93b[1995]<=cb8de2[0];ec2b93b[1943]<=yk46f15[0];ec2b93b[1023]<=ykc1859[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162= 14'd64); - - - - -assign lq73b9e = ((~lf28710) ? (zx4ff6d & ~qg494db) : 1'b0) | (wl90a44 & ~ep85224) | (ep1d525 & ~wwea92d) | (rv38f01 & go72a4c & zx4ff6d) | (do20a1c & zx4ff6d); - -assign zx6128f = aa21756 | (pu933ac & aa98f3e); - - -assign ph947f = nt617c; -assign xj4a3fe = nt617c & zz32ee; - - -assign cb8ffbc = (~yx60a48) ? cm62429 -14'd4 : hq25740; - -assign uk8d311 = 32'hffffffff; - -assign me62210 = shc9fed; -assign vkb277 = ~fp9b638 & ngad253; - -assign ukb3910 = aa21756 | vx38c37; - - - -assign ice51f2 = ic43887 & me4c149 & fnc7186 & qg494db & ~(ald6d17 | pfc780f); - -always @ (posedge rxmac_clk or negedge reset_n) begin if (!reset_n) begin gd8ad7 <= 1'b0; ld6115a <= 1'b0; ec2b5ee <= 14'b0; yx51ee9 <= 14'b0; pf7ba65 <= 14'b0; vvdd32e <= 1'b0; al41f9c <= 1'b0; qi3e472 <= 1'b0; zx6ee71 <= 1'b0; qg7738f <= 1'b0; aab9c79 <= 1'b0; goce3c9 <= 1'b0; jr28f91 <= 1'b0; ou10166 <= 1'b0; sw8ddce <= 1'b0; ay77c61 <= 14'd0; rtd7b87 <= 14'd0; ayc1110 <= 9'd0; cb8880 <= 1'b0; hb71e49 <= 1'b0; mgb9e84 <= 1'b0; end else if (rxmac_clk_en) begin cb8880 <= sj3cf86 & ~mr7090a; if (sj3cf86 && !mr7090a) ayc1110 <= ipe88ea; jr28f91 <= vkb277; ou10166 <= pfd8e30; if (hof42c6) sw8ddce <= hof42c6; else if (shc9fed && !hof42c6) sw8ddce <= 1'b0; else if (wl90a44) sw8ddce <= 1'b0; else sw8ddce <= uvfd6b6; goce3c9 <= ~phbfad6; if (wj70363 & ks109ed) aab9c79 <= wj70363; else if (sj3cf86) aab9c79 <= 1'b0; else aab9c79 <= ald6d17; if (xy86feb) qg7738f <= xy86feb; else if (sj3cf86) qg7738f <= 1'b0; else qg7738f <= bl5ada2; mgb9e84 <= aa21756; if (xweb89d) zx6ee71 <= sjd8e7; if (db2202c) hb71e49 <= nt3d6f5; qi3e472 <= aa21756 | (vx38c37 & ks109ed); ec2b5ee <= qvab575; ld6115a <= uvc61bf; gd8ad7 <= dmd5d67; if (pu933ac && !rg58cab) al41f9c <= zz19777; vvdd32e <= rg58cab; if (pu933ac && !rg58cab) yx51ee9 <= ep12675; if (rg58cab) begin pf7ba65 <= ep12675 + 14'd1; end else pf7ba65 <= 14'd0; if (lf32ad5 && yx60a48 && ui77e13) rtd7b87 <= hq25740 + 14'd1; if (uvc655a && !yx60a48 && aa98f3e) ay77c61 <= cm62429 + 14'd1; else if (ir12148) ay77c61 <= 14'd0; end -end - - - -assign db2202c = ir12148; - - -assign gbf2391 = wl95260 ? (fn40499 > (ipe21c7 + 14'd4)) : fn40499 > ipe21c7; -assign bn91c8d = (fn40499 < 14'd64); -assign tj8e46e = hb7e858; - -assign wj7fde4 = (fn40499[6:0] != 7'd64); -assign xwfef24 = (ui49829 != ie2495d); -assign ea72377 = je30dfd ? 1'b0 : go72a4c | yx60a48 ? vv5abac : aa5244 ? 1'b0 : lq48925; - -assign lf91bb9 = ~(ald6d17 | pfc780f | fp37f5a); -assign qgdb280[31] = ir29124; -assign qgdb280[30] = je30dfd; -assign qgdb280[29] = hoeb5b4; -assign qgdb280[28] = sjb45e8; -assign qgdb280[27] = bl5ada2; -assign qgdb280[26] = uvfd6b6; -assign qgdb280[25] = pfc780f; -assign qgdb280[24] = fp37f5a; -assign qgdb280[23] = phbfad6; -assign qgdb280[22] = uideb95; -assign qgdb280[21] = uif5ca9; -assign qgdb280[20] = vx81b1c; -assign qgdb280[19] = cb29220; -assign qgdb280[18] = go72a4c; -assign qgdb280[17] = me4c149; -assign qgdb280[16] = wl95260; -assign qgdb280[15:14] = 2'b00; -assign qgdb280[13:0] = fn40499; - -assign cm49f54[0] = me4c149; -assign cm49f54[1] = pfc780f; -assign cm49f54[2] = ald6d17; -assign cm49f54[3] = ir29124; -assign cm49f54[4] = je30dfd; -assign cm49f54[5] = hoeb5b4; -assign cm49f54[6] = uideb95; -assign cm49f54[7] = uif5ca9; -assign cm49f54[8] = wl95260; - -always@* begin ks109ed<=ea5c9d9[0];vke06c<=ea5c9d9[1];wj70363<=ea5c9d9[2];vx81b1c<=ea5c9d9[3];sjd8e7<=ea5c9d9[4];nt842ea<={nt32741>>1,ea5c9d9[5]};aa21756<=ea5c9d9[6];cze7ade<=ea5c9d9[7];nt3d6f5<=ea5c9d9[8];dmeb7ae<=ea5c9d9[9];uv5bd72<=ea5c9d9[10];uideb95<=ea5c9d9[11];uif5ca9<=ea5c9d9[12];irae549<=ea5c9d9[13];go72a4c<=ea5c9d9[14];wl95260<=ea5c9d9[15];ui49829<={jpdd6e0>>1,ea5c9d9[16]};me4c149<=ea5c9d9[17];yx60a48<=ea5c9d9[18];aa5244<=ea5c9d9[19];cb29220<=ea5c9d9[20];os49105<=ea5c9d9[21];kd44143<={gb5b83a>>1,ea5c9d9[22]};do20a1c<=ea5c9d9[23];ou50e2<=ea5c9d9[24];lf28710<=ea5c9d9[25];ic43887<=ea5c9d9[26];ipe21c7<={yx44fac>>1,ea5c9d9[27]};co10e3c<=ea5c9d9[28];ym871e0<=ea5c9d9[29];rv38f01<=ea5c9d9[30];pfc780f<=ea5c9d9[31];qge03f4<={ph2864e>>1,ea5c9d9[32]};tw1fa1<=ea5c9d9[33];aafd0b<=ea5c9d9[34];hb7e858<=ea5c9d9[35];hof42c6<=ea5c9d9[36];epa1632<=ea5c9d9[37];bab195<=ea5c9d9[38];rg58cab<=ea5c9d9[39];uvc655a<=ea5c9d9[40];lf32ad5<=ea5c9d9[41];qvab575<={cb8ffbc>>1,ea5c9d9[42]};vv5abac<=ea5c9d9[43];dmd5d67<=ea5c9d9[44];mr759d5<={ukbc914>>1,ea5c9d9[45]};ukacead<=ea5c9d9[46];yk67568<=ea5c9d9[47];ba3ab40<={xl22851>>1,ea5c9d9[48]};lqd5a02<=ea5c9d9[49];twad012<=ea5c9d9[50];fn40499<={yx51ee9>>1,ea5c9d9[51]};ep12675<={pf7ba65>>1,ea5c9d9[52]};pu933ac<=ea5c9d9[53];zm99d62<=ea5c9d9[54];eaceb12<=ea5c9d9[55];mr75890<=ea5c9d9[56];cm62429<={ay77c61>>1,ea5c9d9[57]};ir12148<=ea5c9d9[58];wl90a44<=ea5c9d9[59];ep85224<=ea5c9d9[60];ir29124<=ea5c9d9[61];lq48925<=ea5c9d9[62];ie2495d<={ec2b5ee>>1,ea5c9d9[63]};hq25740<={rtd7b87>>1,ea5c9d9[64]};ym2ba03<=ea5c9d9[65];jc5d019<=ea5c9d9[66];mre80cb<=ea5c9d9[67];th4065d<=ea5c9d9[68];zz32ee<=ea5c9d9[69];zz19777<=ea5c9d9[70];iccbbbf<=ea5c9d9[71];tueefc2<={fca86db>>1,ea5c9d9[72]};ui77e13<=ea5c9d9[73];fpbf098<=ea5c9d9[74];wjf84c7<=ea5c9d9[75];zz131e7<={qgdb280>>1,ea5c9d9[76]};aa98f3e<=ea5c9d9[77];pfc79f0<=ea5c9d9[78];sj3cf86<=ea5c9d9[79];mr7090a<=ea5c9d9[80];ou3e1ad<=ea5c9d9[81];osf0d69<=ea5c9d9[82];ls35a4a<={ldfc20f>>1,ea5c9d9[83]};ngad253<=ea5c9d9[84];zk6929b<=ea5c9d9[85];qg494db<=ea5c9d9[86];fn4a6d8<=ea5c9d9[87];ww536c7<={nr7e728>>1,ea5c9d9[88]};fp9b638<=ea5c9d9[89];xweb89d<=ea5c9d9[90];pfd8e30<=ea5c9d9[91];fnc7186<=ea5c9d9[92];vx38c37<=ea5c9d9[93];uvc61bf<=ea5c9d9[94];je30dfd<=ea5c9d9[95];xy86feb<=ea5c9d9[96];fp37f5a<=ea5c9d9[97];phbfad6<=ea5c9d9[98];uvfd6b6<=ea5c9d9[99];hoeb5b4<=ea5c9d9[100];bl5ada2<=ea5c9d9[101];ald6d17<=ea5c9d9[102];mgb68bd<=ea5c9d9[103];sjb45e8<=ea5c9d9[104];nga2f44<=ea5c9d9[105];wl17a23<=ea5c9d9[106];ipe88ea<={cm49f54>>1,ea5c9d9[107]};ip44754<={bl4faa1>>1,ea5c9d9[108]};oh23aa4<=ea5c9d9[109];ep1d525<=ea5c9d9[110];wwea92d<=ea5c9d9[111];end -always@* begin ec2b93b[2047]<=ou1a400;ec2b93b[2046]<=xjd2000;ec2b93b[2044]<=mt90006;ec2b93b[2040]<=gd80035;ec2b93b[2032]<=nt32741[0];ec2b93b[2028]<=jr28f91;ec2b93b[2017]<=qtedba5;ec2b93b[2008]<=qi3e472;ec2b93b[1988]<=osdb6ca;ec2b93b[1987]<=su6dd2c;ec2b93b[1969]<=gbf2391;ec2b93b[1928]<=qgdb280[0];ec2b93b[1926]<=offdb74;ec2b93b[1891]<=bn91c8d;ec2b93b[1809]<=jcca005;ec2b93b[1805]<=wj4ee7d;ec2b93b[1804]<=lqe4402;ec2b93b[1803]<=fpa0744;ec2b93b[1761]<=ph2864e[0];ec2b93b[1748]<=ld6115a;ec2b93b[1734]<=tj8e46e;ec2b93b[1727]<=ecfce5;ec2b93b[1696]<=rtd7b87[0];ec2b93b[1668]<=cb8ffbc[0];ec2b93b[1633]<=hb71e49;ec2b93b[1587]<=sw8ddce;ec2b93b[1571]<=fn5002b;ec2b93b[1562]<=yk773ec;ec2b93b[1560]<=hd22013;ec2b93b[1558]<=ignore_pkt;ec2b93b[1555]<=bl4faa1[0];ec2b93b[1550]<=jpdd6e0[0];ec2b93b[1531]<=mgb9e84;ec2b93b[1475]<=ph193b9;ec2b93b[1464]<=cmf5978;ec2b93b[1448]<=gd8ad7;ec2b93b[1420]<=ea72377;ec2b93b[1406]<=nr7e728[0];ec2b93b[1345]<=twbdc3f;ec2b93b[1288]<=wj7fde4;ec2b93b[1287]<=uv70fda;ec2b93b[1242]<=anbe308;ec2b93b[1218]<=ir8f24f;ec2b93b[1131]<=ldfc20f[0];ec2b93b[1126]<=zx6ee71;ec2b93b[1094]<=cb8015f;ec2b93b[1076]<=zkcfb09;ec2b93b[1072]<=uk1009e;ec2b93b[1069]<=mt1d13e;ec2b93b[1063]<=me7d50e;ec2b93b[1056]<=ukbc914[0];ec2b93b[1055]<=xy3f6a8;ec2b93b[1052]<=ofdc1d5;ec2b93b[1028]<=qva147b;ec2b93b[1023]<=mtbb27f;ec2b93b[1014]<=ice51f2;ec2b93b[994]<=xy1b6d9;ec2b93b[902]<=ipc9dcf;ec2b93b[901]<=gb5b83a[0];ec2b93b[880]<=ou9830b;ec2b93b[874]<=hq8c22b;ec2b93b[863]<=al41f9c;ec2b93b[848]<=ec2b5ee[0];ec2b93b[834]<=xj4a3fe;ec2b93b[816]<=goce3c9;ec2b93b[793]<=lf91bb9;ec2b93b[777]<=cm49f54[0];ec2b93b[775]<=uk3badc;ec2b93b[765]<=jpf3947;ec2b93b[732]<=aa3eb2f;ec2b93b[643]<=dmee1fb;ec2b93b[621]<=ay77c61[0];ec2b93b[565]<=qi2bf08;ec2b93b[528]<=xwfef24;ec2b93b[527]<=gq87ed5;ec2b93b[514]<=xy1428f;ec2b93b[497]<=me436db;ec2b93b[450]<=lqeb707;ec2b93b[437]<=hof1845;ec2b93b[431]<=wl83f3;ec2b93b[417]<=ph947f;ec2b93b[408]<=aab9c79;ec2b93b[388]<=vi7927d;ec2b93b[387]<=uve775b;ec2b93b[366]<=rv27d65;ec2b93b[310]<=wj65df1;ec2b93b[282]<=co57e1;ec2b93b[257]<=xl22851[0];ec2b93b[248]<=fca86db[0];ec2b93b[225]<=qg68a93;ec2b93b[215]<=nee107e;ec2b93b[208]<=zx6128f;ec2b93b[204]<=qg7738f;ec2b93b[193]<=vi7ceeb;ec2b93b[183]<=yx44fac[0];ec2b93b[157]<=en54381;ec2b93b[155]<=ic4cbbe;ec2b93b[141]<=aa3bc5d;ec2b93b[128]<=aa2450a;ec2b93b[124]<=bydaa1b;ec2b93b[112]<=cb7568;ec2b93b[104]<=dzec251;ec2b93b[96]<=sj804f1;ec2b93b[91]<=kde89f5;ec2b93b[78]<=uiea870;ec2b93b[77]<=fne9977;ec2b93b[64]<=lqe48a1;ec2b93b[62]<=jcfb543;ec2b93b[56]<=yke0ead;ec2b93b[38]<=vvdd32e;ec2b93b[19]<=pf7ba65[0];ec2b93b[9]<=yx51ee9[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[3]};wj70363<=ea5c9d9[4];vx81b1c<=ea5c9d9[5];sjd8e7<=ea5c9d9[6];su56299<={en41ecd>>1,ea5c9d9[7]};kf8a644<={ksf66d>>1,ea5c9d9[8]};ls99128<={nr7b369>>1,ea5c9d9[9]};ip44a1f<={ipd9b4f>>1,ea5c9d9[10]};db287eb<={blcda7c>>1,ea5c9d9[11]};uk1faf8<={qg6d3e7>>1,ea5c9d9[12]};xwebe0c<={xw69f39>>1,ea5c9d9[13]};mrf831e<={zx4f9ca>>1,ea5c9d9[14]};lfc7a1<={xw7ce56>>1,ea5c9d9[15]};ps63d0e<=ea5c9d9[16];ls1e873<=ea5c9d9[17];byf439b<=ea5c9d9[18];bl4ad57<={fc30be7>>1,ea5c9d9[19]};lf28710<=ea5c9d9[20];ic43887<=ea5c9d9[21];ipe21c7<={yx44fac>>1,ea5c9d9[22]};co10e3c<=ea5c9d9[23];ym871e0<=ea5c9d9[24];rv38f01<=ea5c9d9[25];xw5d016<=ea5c9d9[26];ou50e2<=ea5c9d9[27];rg76258<={pfcd085>>1,ea5c9d9[28]};ba8961c<={dm42171>>1,ea5c9d9[29]};of4b0e2<=ea5c9d9[30];rg58715<=ea5c9d9[31];yxc38ab<=ea5c9d9[32];nt1c55c<=ea5c9d9[33];she2ae7<=ea5c9d9[34];anab9e9<={vic51ba>>1,ea5c9d9[35]};yk5cf4d<=ea5c9d9[36];yxe7a68<=ea5c9d9[37];hd3d345<=ea5c9d9[38];jpe9a2e<=ea5c9d9[39];ps4d176<=ea5c9d9[40];bl45d90<={tjb0ffa>>1,ea5c9d9[41]};rg76439<={ls3feb8>>1,ea5c9d9[42]};yz90e5b<={ykfae11>>1,ea5c9d9[43]};sw872dc<=ea5c9d9[44];ux396e1<=ea5c9d9[45];gocb70c<=ea5c9d9[46];gb5b861<=ea5c9d9[47];ofdc30d<=ea5c9d9[48];zke186d<=ea5c9d9[49];lfc36a<=ea5c9d9[50];rt61b56<=ea5c9d9[51];yzdab6<=ea5c9d9[52];su6d5b5<=ea5c9d9[53];of6ada9<=ea5c9d9[54];go56d4d<=ea5c9d9[55];ieb6a69<=ea5c9d9[56];ntb5348<=ea5c9d9[57];fa4d230<={cm6db6e>>1,ea5c9d9[58]};tu69182<=ea5c9d9[59];vi48c13<=ea5c9d9[60];je304d9<={fn6e000>>1,ea5c9d9[61]};sw826ca<=ea5c9d9[62];vx13651<=ea5c9d9[63];qtd9476<={vk2038d>>1,ea5c9d9[64]};al51dab<={jee35b>>1,ea5c9d9[65]};ps76ae6<={qi8d6df>>1,ea5c9d9[66]};gdab996<={kd5b7c6>>1,ea5c9d9[67]};ui5ccb5<=ea5c9d9[68];the65a8<=ea5c9d9[69];pu96a36<={enc6855>>1,ea5c9d9[70]};end -always@* begin ec2b93b[2047]<=mtbb27f;ec2b93b[2046]<=ou1a400;ec2b93b[2045]<=enc6855[0];ec2b93b[2044]<=ald93fd[0];ec2b93b[2041]<=xjd2000;ec2b93b[2035]<=mt90006;ec2b93b[2029]<=wl85b6d;ec2b93b[2022]<=gd80035;ec2b93b[2011]<=cm6db6e[0];ec2b93b[1996]<=en41ecd[0];ec2b93b[1974]<=kq6db70;ec2b93b[1945]<=ksf66d[0];ec2b93b[1943]<=go465d9;ec2b93b[1922]<=cmf5978;ec2b93b[1901]<=ww6db80;ec2b93b[1842]<=nr7b369[0];ec2b93b[1839]<=db32ec9;ec2b93b[1797]<=rx_fifo_full;ec2b93b[1791]<=kd5b7c6[0];ec2b93b[1778]<=xjc2232;ec2b93b[1776]<=yx44fac[0];ec2b93b[1759]<=vk2038d[0];ec2b93b[1755]<=fn6e000[0];ec2b93b[1637]<=ipd9b4f[0];ec2b93b[1631]<=wy9764e;ec2b93b[1622]<=zx4f9ca[0];ec2b93b[1546]<=ignore_pkt;ec2b93b[1535]<=osdbe34;ec2b93b[1531]<=kd4e16d;ec2b93b[1509]<=hq11197;ec2b93b[1504]<=rv27d65;ec2b93b[1471]<=jee35b[0];ec2b93b[1468]<=mt1d13e;ec2b93b[1463]<=kd70006;ec2b93b[1391]<=hocace4;ec2b93b[1312]<=zz8b146;ec2b93b[1226]<=blcda7c[0];ec2b93b[1215]<=epbb270;ec2b93b[1197]<=xw7ce56[0];ec2b93b[1153]<=ph28dd2;ec2b93b[1044]<=pfcd085[0];ec2b93b[1037]<=tjba587;ec2b93b[1023]<=reset_n;ec2b93b[1022]<=zkdf1a1;ec2b93b[1014]<=mr70b6d;ec2b93b[971]<=qi88cbb;ec2b93b[961]<=aa3eb2f;ec2b93b[895]<=qi8d6df[0];ec2b93b[889]<=zmb8446;ec2b93b[888]<=kde89f5;ec2b93b[879]<=cb80034;ec2b93b[811]<=xw69f39[0];ec2b93b[765]<=alc9c2d;ec2b93b[734]<=fc30be7[0];ec2b93b[695]<=ux3959c;ec2b93b[656]<=dz71628;ec2b93b[576]<=vic51ba[0];ec2b93b[518]<=fp374b0;ec2b93b[444]<=pfd7088;ec2b93b[405]<=qg6d3e7[0];ec2b93b[382]<=ofd9385;ec2b93b[347]<=kde72b3;ec2b93b[328]<=ec2e2c5;ec2b93b[259]<=kq46e96;ec2b93b[222]<=ykfae11[0];ec2b93b[164]<=an85c58;ec2b93b[111]<=ls3feb8[0];ec2b93b[82]<=co10b8b;ec2b93b[55]<=tjb0ffa[0];ec2b93b[41]<=dm42171[0];ec2b93b[27]<=fnd2c3f;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[1]};ipd608e<=ea5c9d9[2];xlb0474<=ea5c9d9[3];aa823a6<={xw588d7>>1,ea5c9d9[4]};fc11d31<={osc46ba>>1,ea5c9d9[5]};zz8e98a<=ea5c9d9[6];zx74c56<={aa21dd6>>1,ea5c9d9[7]};end -always@* begin ec2b93b[2047]<=os6dafc[0];ec2b93b[2046]<=hof1623;ec2b93b[2044]<=fp8b11a;ec2b93b[2040]<=xw588d7[0];ec2b93b[2033]<=osc46ba[0];ec2b93b[2019]<=kf235d0;ec2b93b[1991]<=aa21dd6[0];ec2b93b[1023]<=wjedb5f;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[0]};ymbc546<=ea5c9d9[1];doa8c29<=ea5c9d9[2];su4614a<={wjc9dd9>>1,ea5c9d9[3]};tw30a51<={jp50046>>1,ea5c9d9[4]};an8528b<={cb8de2>>1,ea5c9d9[5]};end -always@* begin ec2b93b[2047]<=rvc2c9;ec2b93b[2046]<=ui593bb;ec2b93b[2044]<=wjc9dd9[0];ec2b93b[2040]<=jp50046[0];ec2b93b[2032]<=cb8de2[0];ec2b93b[1023]<=ykc1859[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[1]};ou1f200<=ea5c9d9[2];xjf9000<=ea5c9d9[3];ld40036<={osd15dd>>1,ea5c9d9[4]};codb0<={zk5774c>>1,ea5c9d9[5]};xl6d81<=ea5c9d9[6];ep36c0e<=ea5c9d9[7];ecb6074<=ea5c9d9[8];lf81d0e<={suf0299>>1,ea5c9d9[9]};xj743ba<={go53231>>1,ea5c9d9[10]};cba1dd6<=ea5c9d9[11];end -always@* begin ec2b93b[2047]<=sj23ba9[0];ec2b93b[2046]<=kf1dd4d;ec2b93b[2044]<=pseea6c;ec2b93b[2040]<=osd15dd[0];ec2b93b[2033]<=zk5774c[0];ec2b93b[2018]<=cbbba62;ec2b93b[1988]<=fne98a7;ec2b93b[1929]<=ic4c53e;ec2b93b[1811]<=suf0299[0];ec2b93b[1574]<=go53231[0];ec2b93b[1101]<=fc99188;ec2b93b[1023]<=gq24775;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[6]};bn9ef58<={dzcdac4>>1,ea5c9d9[7]};zmbd63c<={go6d627>>1,ea5c9d9[8]};vieb1e2<=ea5c9d9[9];ho58f12<=ea5c9d9[10];thc7892<=ea5c9d9[11];yz3c496<=ea5c9d9[12];an125a4<={ir39c8e>>1,ea5c9d9[13]};ie92d24<=ea5c9d9[14];zm96921<=ea5c9d9[15];ana485d<={zz91d49>>1,ea5c9d9[16]};qi242ec<=ea5c9d9[17];sw21761<=ea5c9d9[18];zk5d84a<={eca93b4>>1,ea5c9d9[19]};hbec252<=ea5c9d9[20];fn61297<=ea5c9d9[21];lf94bf<=ea5c9d9[22];rt4a5fe<=ea5c9d9[23];ps52ff7<=ea5c9d9[24];co97fbb<=ea5c9d9[25];fpbfdd9<=ea5c9d9[26];ep36c0e<={fne98a7>>1,ea5c9d9[27]};ecb6074<={ic4c53e>>1,ea5c9d9[28]};gdbb395<=ea5c9d9[29];end9cad<=ea5c9d9[30];ww72b61<={ep8f4f2>>1,ea5c9d9[31]};ngad844<={gbd3cad>>1,ea5c9d9[32]};nr61113<={yxf2b6e>>1,ea5c9d9[33]};wl889f<=ea5c9d9[34];en444fd<=ea5c9d9[35];jr227ec<=ea5c9d9[36];nt13f66<=ea5c9d9[37];oh9fb37<=ea5c9d9[38];alfd9bd<=ea5c9d9[39];jpecded<={kdfdc02>>1,ea5c9d9[40]};ps66f6e<={jcee015>>1,ea5c9d9[41]};nt37b73<=ea5c9d9[42];zmbdb9e<=ea5c9d9[43];aledcf3<=ea5c9d9[44];xj6e79c<=ea5c9d9[45];xw73ce6<=ea5c9d9[46];db9e732<=ea5c9d9[47];zm9ccb6<={ayd4afe>>1,ea5c9d9[48]};hbe65b2<=ea5c9d9[49];xl32d96<=ea5c9d9[50];ba96cb6<=ea5c9d9[51];ukb65b3<={necf64d>>1,ea5c9d9[52]};hqb2d99<=ea5c9d9[53];do96cca<=ea5c9d9[54];ksb6653<={gbc9afd>>1,ea5c9d9[55]};ecb3299<=ea5c9d9[56];je994c9<=ea5c9d9[57];lqca64b<=ea5c9d9[58];su5325b<=ea5c9d9[59];xy992d8<=ea5c9d9[60];uvc96c3<=ea5c9d9[61];kd4b61c<=ea5c9d9[62];mr5b0e5<=ea5c9d9[63];hbd872c<=ea5c9d9[64];wjc3967<={uv4e5c7>>1,ea5c9d9[65]};xl1cb3c<={me72e3d>>1,ea5c9d9[66]};ose59e6<={qi971e8>>1,ea5c9d9[67]};an2cf30<=ea5c9d9[68];ui67984<=ea5c9d9[69];an3cc21<=ea5c9d9[70];end -always@* begin ec2b93b[2047]<=mg8dfdb;ec2b93b[2046]<=cz6fed9;ec2b93b[2044]<=qt7f6cd;ec2b93b[2040]<=fafb66d;ec2b93b[2032]<=uidb36b;ec2b93b[2018]<=qt700aa;ec2b93b[2017]<=shd9b58[0];ec2b93b[1989]<=yz80554;ec2b93b[1987]<=dzcdac4[0];ec2b93b[1931]<=yx5490f;ec2b93b[1927]<=go6d627[0];ec2b93b[1865]<=zz91d49[0];ec2b93b[1859]<=yxf2b6e[0];ec2b93b[1844]<=ld7b26b;ec2b93b[1815]<=uxa487c;ec2b93b[1806]<=xj6b139;ec2b93b[1682]<=db8ea4e;ec2b93b[1674]<=lqe4c7d;ec2b93b[1671]<=dz6e910;ec2b93b[1640]<=shd935f;ec2b93b[1582]<=uk243e4;ec2b93b[1565]<=xw589ce;ec2b93b[1488]<=ep8f4f2[0];ec2b93b[1485]<=qi873d9;ec2b93b[1326]<=ay4c52f;ec2b93b[1317]<=wya9b1c;ec2b93b[1300]<=mr54301;ec2b93b[1297]<=uv4e5c7[0];ec2b93b[1295]<=zx74887;ec2b93b[1233]<=gbc9afd[0];ec2b93b[1210]<=ic4c53e[0];ec2b93b[1189]<=cm6d7e0;ec2b93b[1172]<=ea49da1;ec2b93b[1116]<=db3752b;ec2b93b[1105]<=gdaba9a;ec2b93b[1092]<=qi971e8[0];ec2b93b[1087]<=wy10fee;ec2b93b[1082]<=tx_fifoavail;ec2b93b[1023]<=lqf1bfb;ec2b93b[1009]<=jcee015[0];ec2b93b[932]<=ww723a9;ec2b93b[929]<=gbd3cad[0];ec2b93b[922]<=necf64d[0];ec2b93b[837]<=vv6bf6a;ec2b93b[744]<=zz223d3;ec2b93b[742]<=suf0e7b;ec2b93b[663]<=zz98a5;ec2b93b[648]<=qi571b;ec2b93b[605]<=fne98a7[0];ec2b93b[594]<=dm7684c;ec2b93b[586]<=eca93b4[0];ec2b93b[552]<=wj60366;ec2b93b[547]<=db3d01e;ec2b93b[546]<=me72e3d[0];ec2b93b[543]<=wla443f;ec2b93b[504]<=kdfdc02[0];ec2b93b[466]<=suce475;ec2b93b[418]<=fa4d7ed;ec2b93b[372]<=xwe447a;ec2b93b[371]<=vife1cf;ec2b93b[331]<=qt75363;ec2b93b[324]<=irab02b;ec2b93b[297]<=qt4ed09;ec2b93b[273]<=nrc7a03;ec2b93b[252]<=ri3fb80;ec2b93b[233]<=ir39c8e[0];ec2b93b[185]<=ayd4afe[0];ec2b93b[162]<=kq53558;ec2b93b[136]<=hqb8f40;ec2b93b[126]<=co87f70;ec2b93b[116]<=ph27391;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[3]};fp32995<=ea5c9d9[4];ph94cae<=ea5c9d9[5];db32bb0<={yk56400>>1,ea5c9d9[6]};vieb1e2<=ea5c9d9[7];uxaec34<=ea5c9d9[8];dm761a5<=ea5c9d9[9];dbb0d2b<=ea5c9d9[10];ba8695f<=ea5c9d9[11];ie34afa<=ea5c9d9[12];rva57d1<=ea5c9d9[13];aa2be8f<=ea5c9d9[14];bl5f479<=ea5c9d9[15];uifa3ce<=ea5c9d9[16];kqd1e71<=ea5c9d9[17];mt8f388<=ea5c9d9[18];by79c45<=ea5c9d9[19];osce22b<=ea5c9d9[20];th71159<=ea5c9d9[21];hdbac11<={os6dafc>>1,ea5c9d9[22]};qi2b38e<=ea5c9d9[23];su59c70<=ea5c9d9[24];ayce380<=ea5c9d9[25];ld71c01<=ea5c9d9[26];ph8e00f<=ea5c9d9[27];an803fc<={hb40a02>>1,ea5c9d9[28]};ba1fe4<=ea5c9d9[29];yx7f918<={rt405c7>>1,ea5c9d9[30]};pffc8c4<=ea5c9d9[31];xwe4627<=ea5c9d9[32];yz2313b<=ea5c9d9[33];cb189dc<=ea5c9d9[34];cmc4ee4<=ea5c9d9[35];xl27721<=ea5c9d9[36];sw3b90e<=ea5c9d9[37];shdc870<=ea5c9d9[38];bye4384<=ea5c9d9[39];co21c23<=ea5c9d9[40];hqe118<=ea5c9d9[41];of708c3<=ea5c9d9[42];nt8461d<=ea5c9d9[43];cb230ee<=ea5c9d9[44];ir18774<=ea5c9d9[45];enc3ba5<=ea5c9d9[46];ir1dd2c<=ea5c9d9[47];zkee964<=ea5c9d9[48];th74b23<=ea5c9d9[49];bna591f<=ea5c9d9[50];an2c8fe<=ea5c9d9[51];yz23fa7<={kqf5e19>>1,ea5c9d9[52]};ec1fd3d<=ea5c9d9[53];xwfe9e9<=ea5c9d9[54];faf4f4a<=ea5c9d9[55];ria7a53<=ea5c9d9[56];db3d29b<=ea5c9d9[57];dze94de<=ea5c9d9[58];zx4a6f7<=ea5c9d9[59];ay537bf<=ea5c9d9[60];lf9bdf8<=ea5c9d9[61];aydefc7<=ea5c9d9[62];end -always@* begin ec2b93b[2047]<=mg8dfdb;ec2b93b[2046]<=tx_sndpausreq;ec2b93b[2044]<=tx_sndpaustim[0];ec2b93b[2040]<=co1f530;ec2b93b[2033]<=cmfa980;ec2b93b[2019]<=yk56400[0];ec2b93b[1991]<=xj6b139;ec2b93b[1934]<=ls30000;ec2b93b[1929]<=rib79b4;ec2b93b[1898]<=wj4e2f6;ec2b93b[1821]<=mg760;ec2b93b[1810]<=ecbcda2;ec2b93b[1749]<=jr69e9;ec2b93b[1707]<=ng2f056;ec2b93b[1666]<=hb40a02[0];ec2b93b[1630]<=zm14b38;ec2b93b[1595]<=cz601a7;ec2b93b[1572]<=mt3688f;ec2b93b[1506]<=hd385a0;ec2b93b[1450]<=kqeaf42;ec2b93b[1440]<=rg76bbd;ec2b93b[1384]<=mtaed77;ec2b93b[1370]<=os6dafc[0];ec2b93b[1366]<=tx_discfrm;ec2b93b[1284]<=ie5017;ec2b93b[1212]<=dba59c2;ec2b93b[1202]<=ks98c6f;ec2b93b[1174]<=jebd235;ec2b93b[1170]<=vk256ef;ec2b93b[1142]<=ksd3d;ec2b93b[1125]<=kf1da82;ec2b93b[1097]<=lf2251b;ec2b93b[1041]<=rib8fa4;ec2b93b[1023]<=lqf1bfb;ec2b93b[964]<=jpc2d06;ec2b93b[949]<=nre9c5e;ec2b93b[853]<=ea62978;ec2b93b[833]<=os49028;ec2b93b[815]<=qi82967;ec2b93b[753]<=su670b4;ec2b93b[720]<=jea8807;ec2b93b[714]<=db38e5b;ec2b93b[692]<=bnb5dae;ec2b93b[685]<=tja5e0a;ec2b93b[601]<=jp7e997;ec2b93b[587]<=hoc5078;ec2b93b[585]<=ng1c25;ec2b93b[562]<=ba83b50;ec2b93b[520]<=rt405c7[0];ec2b93b[474]<=uk34f4e;ec2b93b[407]<=hb5052c;ec2b93b[376]<=qv2ce16;ec2b93b[357]<=cb2930a;ec2b93b[300]<=uxbb0ba;ec2b93b[293]<=zkc5c3e;ec2b93b[292]<=kqf5e19[0];ec2b93b[281]<=kqf076a;ec2b93b[237]<=hqa7a71;ec2b93b[203]<=yx6a0a5;ec2b93b[146]<=fp946f5;ec2b93b[140]<=oh23c1d;ec2b93b[70]<=mta4783;ec2b93b[35]<=pfc7d23;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[2]};cme5a0a<={su4ce51>>1,ea5c9d9[3]};jr2d050<={ww67289>>1,ea5c9d9[4]};ep36c0e<=ea5c9d9[5];ecb6074<=ea5c9d9[6];iea1cc<=ea5c9d9[7];end -always@* begin ec2b93b[2047]<=cze82fe;ec2b93b[2046]<=qt417f5[0];ec2b93b[2044]<=su4ce51[0];ec2b93b[2040]<=ww67289[0];ec2b93b[2033]<=fne98a7;ec2b93b[2019]<=ic4c53e;ec2b93b[1990]<=hq8911d;ec2b93b[1023]<=db3d05f;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[1]};lqf49e3<=ea5c9d9[2];oha4f1b<=ea5c9d9[3];bn278dc<=ea5c9d9[4];mt8f388<=ea5c9d9[5];ba1b9e6<={ho57372>>1,ea5c9d9[6]};ofe799c<={blcdc91>>1,ea5c9d9[7]};pfe672d<={qg7247e>>1,ea5c9d9[8]};ls9cb74<={lf91f88>>1,ea5c9d9[9]};nt2dd10<={ld7e234>>1,ea5c9d9[10]};dz74437<={ec88d3a>>1,ea5c9d9[11]};sw10df2<={ie34e88>>1,ea5c9d9[12]};fp37c82<={hq3a20a>>1,ea5c9d9[13]};qtf20b5<={ou88299>>1,ea5c9d9[14]};co82d6d<={iea644>>1,ea5c9d9[15]};lfb5b47<={ng99108>>1,ea5c9d9[16]};ui6d1fa<={gb4421f>>1,ea5c9d9[17]};lq47e88<={qv87e1>>1,ea5c9d9[18]};qgfa213<={qi1f860>>1,ea5c9d9[19]};sw884c9<={jce180e>>1,ea5c9d9[20]};tu42648<=ea5c9d9[21];db13243<=ea5c9d9[22];end -always@* begin ec2b93b[2047]<=tx_fifodata[0];ec2b93b[2046]<=tx_fifoeof;ec2b93b[2044]<=tx_fifoempty;ec2b93b[2040]<=tx_fifoctrl;ec2b93b[2032]<=ea62978;ec2b93b[2017]<=ho57372[0];ec2b93b[1987]<=blcdc91[0];ec2b93b[1927]<=qg7247e[0];ec2b93b[1865]<=ng99108[0];ec2b93b[1806]<=lf91f88[0];ec2b93b[1682]<=gb4421f[0];ec2b93b[1565]<=ld7e234[0];ec2b93b[1317]<=qv87e1[0];ec2b93b[1172]<=jce180e[0];ec2b93b[1082]<=ec88d3a[0];ec2b93b[1023]<=tx_discfrm;ec2b93b[932]<=iea644[0];ec2b93b[594]<=gb60396;ec2b93b[586]<=qi1f860[0];ec2b93b[466]<=ou88299[0];ec2b93b[297]<=ntc072;ec2b93b[233]<=hq3a20a[0];ec2b93b[116]<=ie34e88[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[5]};tud5982<={wld91c>>1,ea5c9d9[6]};bn9ef58<={dzcdac4>>1,ea5c9d9[7]};je1e93c<={tx_fifodata>>1,ea5c9d9[8]};lqf49e3<=ea5c9d9[9];oha4f1b<=ea5c9d9[10];thc7892<=ea5c9d9[11];qtc6532<={tx_sndpaustim>>1,ea5c9d9[12]};xj6b194<=ea5c9d9[13];bn278dc<=ea5c9d9[14];an2999d<=ea5c9d9[15];ne66761<={nr716da>>1,ea5c9d9[16]};phb5d9e<=ea5c9d9[17];fnf6bb3<=ea5c9d9[18];zmbd63c<={go6d627>>1,ea5c9d9[19]};ana485d<={zz91d49>>1,ea5c9d9[20]};zk5d84a<={eca93b4>>1,ea5c9d9[21]};hbec252<=ea5c9d9[22];db32bb0<={yk56400>>1,ea5c9d9[23]};an125a4<={ir39c8e>>1,ea5c9d9[24]};hdbac11<={os6dafc>>1,ea5c9d9[25]};dm761a5<=ea5c9d9[26];ui59c6a<=ea5c9d9[27];jp71a81<={aye0014>>1,ea5c9d9[28]};al6a078<={ec508>>1,ea5c9d9[29]};end -always@* begin ec2b93b[2047]<=lqf1bfb;ec2b93b[2046]<=mg8dfdb;ec2b93b[2044]<=qt7f6cd;ec2b93b[2040]<=cz6fed9;ec2b93b[2032]<=uxa1b23[0];ec2b93b[2017]<=wld91c[0];ec2b93b[1987]<=dzcdac4[0];ec2b93b[1926]<=tx_fifodata[0];ec2b93b[1804]<=tx_fifoeof;ec2b93b[1803]<=yk56400[0];ec2b93b[1560]<=tx_fifoempty;ec2b93b[1558]<=ir39c8e[0];ec2b93b[1550]<=nr716da[0];ec2b93b[1072]<=tx_fifoavail;ec2b93b[1069]<=os6dafc[0];ec2b93b[1052]<=uidb36b;ec2b93b[1023]<=baa7b6d;ec2b93b[901]<=ea49da1;ec2b93b[775]<=psee2db;ec2b93b[732]<=ec508[0];ec2b93b[450]<=eca93b4[0];ec2b93b[387]<=tx_fifoctrl;ec2b93b[366]<=aye0014[0];ec2b93b[225]<=zz91d49[0];ec2b93b[193]<=tx_sndpausreq;ec2b93b[183]<=vx3b00;ec2b93b[112]<=go6d627[0];ec2b93b[96]<=tx_sndpaustim[0];ec2b93b[91]<=mg760;ec2b93b[56]<=fafb66d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[0]};ksacbe6<={hdatain>>1,ea5c9d9[1]};yx65f30<=ea5c9d9[2];ba2f984<=ea5c9d9[3];ho7cc23<=ea5c9d9[4];nre611b<=ea5c9d9[5];lf846f3<={lq4d15b>>1,ea5c9d9[6]};mt2379e<=ea5c9d9[7];kqde7a3<={ayc1110>>1,ea5c9d9[8]};rtf3d18<=ea5c9d9[9];hd9e8c6<=ea5c9d9[10];vif4637<=ea5c9d9[11];ksa31ba<=ea5c9d9[12];ux18dd0<=ea5c9d9[13];shc6e84<=ea5c9d9[14];lfba127<={zz2d9e0>>1,ea5c9d9[15]};rv849fa<={ui67832>>1,ea5c9d9[16]};vx27eb8<={cme0c8c>>1,ea5c9d9[17]};kqfae3b<={bn32307>>1,ea5c9d9[18]};hbd71d8<=ea5c9d9[19];jpc7633<={oha44e6>>1,ea5c9d9[20]};thd8cf9<={hd139ae>>1,ea5c9d9[21]};ir33e75<={vve6bba>>1,ea5c9d9[22]};hbf9d64<={iraeebb>>1,ea5c9d9[23]};ip75938<={hdbaee9>>1,ea5c9d9[24]};ouac9c5<={jpd774e>>1,ea5c9d9[25]};fn64e28<=ea5c9d9[26];xl38a36<={dze9da7>>1,ea5c9d9[27]};xl28dba<={jc769f4>>1,ea5c9d9[28]};wl36eb0<={hqa7d15>>1,ea5c9d9[29]};bnbac23<={nef4558>>1,ea5c9d9[30]};dbb08f4<={mg15613>>1,ea5c9d9[31]};an23d3e<={rg584cc>>1,ea5c9d9[32]};dmf4fab<={zz1331f>>1,ea5c9d9[33]};co3eadb<={wjcc7f2>>1,ea5c9d9[34]};suf56d8<=ea5c9d9[35];ohab6c0<=ea5c9d9[36];sudb024<={czf28cb>>1,ea5c9d9[37]};psc0907<={swa32e7>>1,ea5c9d9[38]};qi241db<={uicb9c7>>1,ea5c9d9[39]};oh76ca<={ale71c0>>1,ea5c9d9[40]};ykdb2a9<={fnc7027>>1,ea5c9d9[41]};bycaa45<={psc09fe>>1,ea5c9d9[42]};coa9157<={tj27f9b>>1,ea5c9d9[43]};bl455cb<={jcfe6fa>>1,ea5c9d9[44]};je2ae5e<={dzf37d3>>1,ea5c9d9[45]};ecb979a<={psdf4ff>>1,ea5c9d9[46]};sh5e680<={yxd3fd1>>1,ea5c9d9[47]};dzf3404<=ea5c9d9[48];cb9a027<=ea5c9d9[49];dmd013c<=ea5c9d9[50];xy4f1d<={ym8da48>>1,ea5c9d9[51]};jr278eb<=ea5c9d9[52];qv3c75f<=ea5c9d9[53];end -always@* begin ec2b93b[2047]<=hdatain[0];ec2b93b[2046]<=hread_n;ec2b93b[2044]<=hwrite_n;ec2b93b[2040]<=hcs_n;ec2b93b[2032]<=ie552b;ec2b93b[2016]<=lq4d15b[0];ec2b93b[1985]<=os68ada;ec2b93b[1925]<=fnc7027[0];ec2b93b[1922]<=ayc1110[0];ec2b93b[1802]<=psc09fe[0];ec2b93b[1796]<=cb8880;ec2b93b[1556]<=tj27f9b[0];ec2b93b[1544]<=qg78222;ec2b93b[1505]<=uicb9c7[0];ec2b93b[1324]<=ayff46d;ec2b93b[1316]<=dze9da7[0];ec2b93b[1200]<=ym8da48[0];ec2b93b[1169]<=hqa7d15[0];ec2b93b[1163]<=rg584cc[0];ec2b93b[1118]<=zk63f94;ec2b93b[1106]<=iraeebb[0];ec2b93b[1065]<=jcfe6fa[0];ec2b93b[1041]<=cme0c8c[0];ec2b93b[1040]<=of7a6e5;ec2b93b[1023]<=haddr[0];ec2b93b[962]<=ale71c0[0];ec2b93b[752]<=swa32e7[0];ec2b93b[707]<=ne69209;ec2b93b[662]<=yz9fe8d;ec2b93b[658]<=epbba76;ec2b93b[600]<=gofa369;ec2b93b[584]<=jc769f4[0];ec2b93b[581]<=mg15613[0];ec2b93b[559]<=wjcc7f2[0];ec2b93b[553]<=vve6bba[0];ec2b93b[520]<=ui67832[0];ec2b93b[376]<=czf28cb[0];ec2b93b[353]<=su6d241;ec2b93b[331]<=yxd3fd1[0];ec2b93b[329]<=jpd774e[0];ec2b93b[290]<=nef4558[0];ec2b93b[279]<=zz1331f[0];ec2b93b[276]<=hd139ae[0];ec2b93b[260]<=zz2d9e0[0];ec2b93b[188]<=mg1fca3;ec2b93b[165]<=psdf4ff[0];ec2b93b[164]<=hdbaee9[0];ec2b93b[138]<=oha44e6[0];ec2b93b[130]<=mrdcb67;ec2b93b[82]<=dzf37d3[0];ec2b93b[69]<=enf2913;ec2b93b[65]<=jr9b96c;ec2b93b[34]<=bn32307[0];ec2b93b[32]<=qtd372d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[0]};en7a94c<={sj808c0>>1,ea5c9d9[1]};icd4a64<=ea5c9d9[2];xla5320<=ea5c9d9[3];yz29907<=ea5c9d9[4];rt641e1<={sh7ad9a>>1,ea5c9d9[5]};an787a<={aab66a5>>1,ea5c9d9[6]};tue1ea4<={ux9a949>>1,ea5c9d9[7]};cz7a911<={pha5268>>1,ea5c9d9[8]};yza4460<={qg49a3d>>1,ea5c9d9[9]};vk1182e<={ic68f4a>>1,ea5c9d9[10]};sh60b92<={hd3d282>>1,ea5c9d9[11]};ks2e4a1<={vv4a0b7>>1,ea5c9d9[12]};wy92841<={ou82dff>>1,ea5c9d9[13]};ira104f<={xyb7fc7>>1,ea5c9d9[14]};ir827d<=ea5c9d9[15];sh413ec<=ea5c9d9[16];rv9f64<=ea5c9d9[17];rt4fb27<=ea5c9d9[18];kq7d93e<=ea5c9d9[19];end -always@* begin ec2b93b[2047]<=sj808c0[0];ec2b93b[2046]<=yz2302a;ec2b93b[2044]<=mdi;ec2b93b[2040]<=zxd8bd6;ec2b93b[2032]<=sh7ad9a[0];ec2b93b[2017]<=aab66a5[0];ec2b93b[1987]<=ux9a949[0];ec2b93b[1926]<=pha5268[0];ec2b93b[1804]<=qg49a3d[0];ec2b93b[1614]<=ayff1d6;ec2b93b[1561]<=ic68f4a[0];ec2b93b[1180]<=ipf8eb1;ec2b93b[1074]<=hd3d282[0];ec2b93b[1023]<=mef0118[0];ec2b93b[807]<=dbbfe3a;ec2b93b[625]<=ri3ac6f;ec2b93b[403]<=xyb7fc7[0];ec2b93b[312]<=vvc758d;ec2b93b[201]<=ou82dff[0];ec2b93b[100]<=vv4a0b7[0];end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[0]};yxcc68d<=ea5c9d9[1];ps6346c<=ea5c9d9[2];gq1a362<=ea5c9d9[3];co10e3c<=ea5c9d9[4];uk8d880<=ea5c9d9[5];ne6c401<=ea5c9d9[6];yk6200b<=ea5c9d9[7];aa10058<=ea5c9d9[8];oh802c1<={rxd_pos>>1,ea5c9d9[9]};je160c<={rxd_neg>>1,ea5c9d9[10]};vkb062<=ea5c9d9[11];vi58313<=ea5c9d9[12];cmc189b<=ea5c9d9[13];xlc4d9<=ea5c9d9[14];go626ce<=ea5c9d9[15];ph13670<=ea5c9d9[16];bn9b386<=ea5c9d9[17];wjd9c36<=ea5c9d9[18];goce1b4<=ea5c9d9[19];gb70da1<=ea5c9d9[20];ux3686a<={vk2f2fc>>1,ea5c9d9[21]};gda1aa4<={gocbf12>>1,ea5c9d9[22]};of6a924<={rtfc487>>1,ea5c9d9[23]};wla492c<={qi87d24>>1,ea5c9d9[24]};sw24b20<={nef4900>>1,ea5c9d9[25]};fc25900<=ea5c9d9[26];gd2c802<=ea5c9d9[27];th64014<=ea5c9d9[28];ri200a7<=ea5c9d9[29];aa53b<=ea5c9d9[30];cb29d8<=ea5c9d9[31];ri14ec4<=ea5c9d9[32];pua7622<=ea5c9d9[33];gq3b112<=ea5c9d9[34];fnd8891<=ea5c9d9[35];db22470<={ea430f5>>1,ea5c9d9[36]};qv12386<=ea5c9d9[37];jr91c34<=ea5c9d9[38];fp8e1a6<=ea5c9d9[39];yx70d37<=ea5c9d9[40];ng869bd<=ea5c9d9[41];aa34dea<=ea5c9d9[42];coa6f51<=ea5c9d9[43];nt37a89<=ea5c9d9[44];uiea272<={dmc06d5>>1,ea5c9d9[45]};al51390<=ea5c9d9[46];kd4e42b<={nedaaba>>1,ea5c9d9[47]};kq7215d<={rgd55d3>>1,ea5c9d9[48]};gd90ae9<={vxaae9b>>1,ea5c9d9[49]};gd8574c<=ea5c9d9[50];wy2ba64<=ea5c9d9[51];tu5d321<=ea5c9d9[52];pfe990b<=ea5c9d9[53];kq4c85e<=ea5c9d9[54];nr642f1<=ea5c9d9[55];uk2178f<=ea5c9d9[56];zmbc79<=ea5c9d9[57];yx5e3ca<=ea5c9d9[58];end -always@* begin ec2b93b[2047]<=shc6a74;ec2b93b[2046]<=pu353a4;ec2b93b[2044]<=ls1bc04;ec2b93b[2040]<=rv27d65;ec2b93b[2032]<=rx_dv_pos;ec2b93b[2016]<=rx_dv_neg;ec2b93b[1985]<=rx_er_pos;ec2b93b[1922]<=rx_er_neg;ec2b93b[1867]<=hq1979;ec2b93b[1804]<=nedaaba[0];ec2b93b[1797]<=rxd_pos[0];ec2b93b[1761]<=ps6301b;ec2b93b[1686]<=lfcbcb;ec2b93b[1623]<=hodf5e7;ec2b93b[1561]<=rgd55d3[0];ec2b93b[1558]<=ks70b;ec2b93b[1547]<=rxd_neg[0];ec2b93b[1542]<=ea430f5[0];ec2b93b[1490]<=kf2380c;ec2b93b[1475]<=dmc06d5[0];ec2b93b[1413]<=wy2401c;ec2b93b[1409]<=pua7a18;ec2b93b[1400]<=kde7439;ec2b93b[1324]<=vk2f2fc[0];ec2b93b[1200]<=rtfc487[0];ec2b93b[1199]<=qgfaf3a;ec2b93b[1074]<=vxaae9b[0];ec2b93b[1068]<=rv1c2c6;ec2b93b[1047]<=ui4c131;ec2b93b[1037]<=mt187a9;ec2b93b[1023]<=ux18d4e[0];ec2b93b[933]<=zz1c065;ec2b93b[902]<=bn36aa;ec2b93b[880]<=ps6c603;ec2b93b[811]<=ph9bebc;ec2b93b[779]<=pu200e1;ec2b93b[771]<=nt3d0c3;ec2b93b[745]<=of44701;ec2b93b[706]<=nef4900[0];ec2b93b[704]<=fada9e8;ec2b93b[700]<=ksbce87;ec2b93b[600]<=gocbf12[0];ec2b93b[440]<=rg4d8c0;ec2b93b[405]<=uvd37d7;ec2b93b[372]<=uk888e0;ec2b93b[353]<=qi87d24[0];ec2b93b[352]<=medb53d;ec2b93b[350]<=dzd79d0;ec2b93b[220]<=gqa9b18;ec2b93b[202]<=vxba6fa;ec2b93b[186]<=gq3111c;ec2b93b[176]<=epbb6a7;ec2b93b[110]<=osf5363;ec2b93b[101]<=lq574df;ec2b93b[93]<=tw4c44;ec2b93b[88]<=xwe1637;ec2b93b[55]<=do1ea6c;ec2b93b[46]<=kd60988;ec2b93b[27]<=kdc3d4d;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162>1,ea5c9d9[1]};ksacbe6<={hdatain>>1,ea5c9d9[2]};ho7cc23<=ea5c9d9[3];ba2f984<=ea5c9d9[4];yx65f30<=ea5c9d9[5];je1e93c<={tx_fifodata>>1,ea5c9d9[6]};thc7892<=ea5c9d9[7];lqf49e3<=ea5c9d9[8];oha4f1b<=ea5c9d9[9];qtc6532<={tx_sndpaustim>>1,ea5c9d9[10]};xj6b194<=ea5c9d9[11];bn278dc<=ea5c9d9[12];xw5d016<=ea5c9d9[13];ou50e2<=ea5c9d9[14];hq8672b<={ls1f5e>>1,ea5c9d9[15]};kf3395b<=ea5c9d9[16];ba9cadc<=ea5c9d9[17];kqde7a3<={ayc1110>>1,ea5c9d9[18]};rtf3d18<=ea5c9d9[19];gb5b888<={hbf301c>>1,ea5c9d9[20]};ofdc445<=ea5c9d9[21];ale222d<=ea5c9d9[22];ri1116c<={db39ca>>1,ea5c9d9[23]};sw88b63<=ea5c9d9[24];zx45b19<=ea5c9d9[25];zz2d8cf<=ea5c9d9[26];ne6c67e<=ea5c9d9[27];zk633f3<=ea5c9d9[28];lf19f9a<={ksb6911>>1,ea5c9d9[29]};xwcfcd6<=ea5c9d9[30];jp7e6b2<=ea5c9d9[31];dzf3597<=ea5c9d9[32];cb9acbf<=ea5c9d9[33];ipd65fd<=ea5c9d9[34];vkb2fec<=ea5c9d9[35];ks97f62<=ea5c9d9[36];rvbfb11<=ea5c9d9[37];kdfd88e<=ea5c9d9[38];ldec475<={fc99fb3>>1,ea5c9d9[39]};ic623af<={bycfd9a>>1,ea5c9d9[40]};do11d78<={pf7ecd2>>1,ea5c9d9[41]};jr8ebc2<={vvf6696>>1,ea5c9d9[42]};al75e16<={oub34b7>>1,ea5c9d9[43]};fpaf0b5<={mt9a5b9>>1,ea5c9d9[44]};ic785ae<={hbd2dcc>>1,ea5c9d9[45]};rtc2d70<={ri96e67>>1,ea5c9d9[46]};jr16b86<={twb733b>>1,ea5c9d9[47]};jrb5c37<={ymb99db>>1,ea5c9d9[48]};yzae1bf<={shcced9>>1,ea5c9d9[49]};gb70dfc<={ww676cd>>1,ea5c9d9[50]};zm86fe5<={ks3b668>>1,ea5c9d9[51]};vx37f2a<=ea5c9d9[52];ntbf956<={ald9a08>>1,ea5c9d9[53]};fnfcab6<=ea5c9d9[54];uie55b7<=ea5c9d9[55];zm2adb9<=ea5c9d9[56];qg56dcb<=ea5c9d9[57];ksb6e59<=ea5c9d9[58];bab72c8<=ea5c9d9[59];ksb9643<=ea5c9d9[60];eacb218<=ea5c9d9[61];os590c1<={th61733>>1,ea5c9d9[62]};blc8609<={rib99f>>1,ea5c9d9[63]};me4304e<=ea5c9d9[64];yz18271<=ea5c9d9[65];ayc138d<=ea5c9d9[66];db9c68<=ea5c9d9[67];ip4e347<={osfa1a4>>1,ea5c9d9[68]};xj71a3d<={psd0d21>>1,ea5c9d9[69]};end -always@* begin ec2b93b[2047]<=haddr[0];ec2b93b[2046]<=hdatain[0];ec2b93b[2044]<=hcs_n;ec2b93b[2040]<=hwrite_n;ec2b93b[2033]<=hread_n;ec2b93b[2019]<=tx_fifodata[0];ec2b93b[1994]<=vvf6696[0];ec2b93b[1990]<=tx_fifoavail;ec2b93b[1981]<=vicada4;ec2b93b[1965]<=bn2222d;ec2b93b[1940]<=oub34b7[0];ec2b93b[1939]<=ayc1110[0];ec2b93b[1933]<=tx_fifoeof;ec2b93b[1914]<=qg56d22;ec2b93b[1883]<=zm1116e;ec2b93b[1832]<=mt9a5b9[0];ec2b93b[1831]<=cb8880;ec2b93b[1819]<=tx_fifoempty;ec2b93b[1785]<=fc99fb3[0];ec2b93b[1781]<=ksb6911[0];ec2b93b[1778]<=ls1f5e[0];ec2b93b[1740]<=ir898c;ec2b93b[1719]<=ec88b73;ec2b93b[1634]<=hd2d85c;ec2b93b[1616]<=hbd2dcc[0];ec2b93b[1615]<=hbf301c[0];ec2b93b[1591]<=tx_sndpaustim[0];ec2b93b[1579]<=kq5ccfa;ec2b93b[1522]<=bycfd9a[0];ec2b93b[1515]<=cbb4888;ec2b93b[1508]<=oufaf3;ec2b93b[1470]<=xj6e67e;ec2b93b[1432]<=wj44c65;ec2b93b[1406]<=psd0d21[0];ec2b93b[1391]<=rt45b99;ec2b93b[1286]<=shcced9[0];ec2b93b[1271]<=bn1ce56;ec2b93b[1221]<=zk6c2e6;ec2b93b[1184]<=ri96e67[0];ec2b93b[1182]<=gq980e7;ec2b93b[1135]<=tx_sndpausreq;ec2b93b[1111]<=rte67d0;ec2b93b[1051]<=ks3b668[0];ec2b93b[1023]<=reset_n;ec2b93b[997]<=pf7ecd2[0];ec2b93b[990]<=mt395b4;ec2b93b[982]<=uxa4445;ec2b93b[969]<=me7d798;ec2b93b[892]<=xw733f6;ec2b93b[889]<=ignore_pkt;ec2b93b[870]<=en41131;ec2b93b[817]<=an2632d;ec2b93b[789]<=rib99f[0];ec2b93b[735]<=nt2dccf;ec2b93b[703]<=osfa1a4[0];ec2b93b[643]<=ymb99db[0];ec2b93b[635]<=db39ca[0];ec2b93b[525]<=ww676cd[0];ec2b93b[495]<=wje72b6;ec2b93b[444]<=rx_fifo_full;ec2b93b[435]<=ui68226;ec2b93b[394]<=th61733[0];ec2b93b[351]<=kf9f434;ec2b93b[321]<=twb733b[0];ec2b93b[317]<=nec0739;ec2b93b[222]<=tx_fifoctrl;ec2b93b[217]<=pfcd044;ec2b93b[175]<=yz33e86;ec2b93b[108]<=ald9a08[0];ec2b93b[54]<=icdb341;end assign mg8dcb5 = ec2b93b,ea5c9d9 = su72d4e; initial begin xy83c2c = $fopen(".fred"); $fdisplay( xy83c2c, "%3h\n%3h", (gq3b216 >> 4) & fp16372, (gq3b216 >> (zxc858d+4)) & fp16372 ); $fclose(xy83c2c); $readmemh(".fred", phb5383); end always @ (mg8dcb5) begin en4e0f0 = phb5383[1]; for (do1e162=0; do1e162 if ( (HCS_N = '0') and (HREAD_N = '0') ) then - HC_NEXT_STATE <= HC_READ; - elsif( (HCS_N = '0') and (HWRITE_N = '0') ) then - HC_NEXT_STATE <= HC_WRITE; - else - HC_NEXT_STATE <= HC_SLEEP; - end if; - when HC_READ => HC_NEXT_STATE <= HC_RACK; - hdataout_en_n_comb <= '0'; - hready_n_comb <= '0'; - when HC_RACK => HC_NEXT_STATE <= HC_SLEEP; - when HC_WRITE => HC_NEXT_STATE <= HC_WACK; - hready_n_comb <= '0'; - when HC_WACK => HC_NEXT_STATE <= HC_SLEEP; - when others => HC_NEXT_STATE <= HC_SLEEP; - end case; -end process HC_STATE_TRANSFORM; - -HREADY_N <= hready_n_buf; -HDATAOUT_EN_N <= hdataout_en_n_buf; - ------------------------------------------------------------------------------- --- state machine for "transmission" ------------------------------------------------------------------------------- - --- preread counter -THE_PREREAD_CTR: process( TX_MAC_CLK ) -begin - if ( RESET_N = '0' ) then - preread_ctr <= (others => '0'); - elsif( rising_edge(TX_MAC_CLK) ) then - if ( preread_rst_comb = '1' ) then - preread_ctr <= (others => '0'); - elsif( preread_ce_comb = '1' ) then - preread_ctr <= preread_ctr + 1; - end if; - end if; -end process THE_PREREAD_CTR; -preread_done_comb <= '1' when (preread_ctr = x"6") - else '0'; - --- state registers -TX_STATE_MEM: process( TX_MAC_CLK, RESET_N ) -begin - if ( RESET_N = '0' ) then - TX_CURRENT_STATE <= TX_SLEEP; - tx_done_buf <= '0'; - elsif( rising_edge(TX_MAC_CLK) ) then - TX_CURRENT_STATE <= TX_NEXT_STATE; - tx_done_buf <= tx_done_comb; - end if; -end process TX_STATE_MEM; - -tx_macread_comb <= preread_ce_comb or read_on_comb; - --- state transitions -TX_STATE_TRANSFORM: process( TX_CURRENT_STATE, TX_FIFOEMPTY, TX_FIFOAVAIL, TX_FIFOEOF, preread_done_comb ) -begin - TX_NEXT_STATE <= TX_SLEEP; -- avoid latches - preread_ce_comb <= '0'; - preread_rst_comb <= '0'; - read_on_comb <= '0'; - tx_done_comb <= '0'; - case TX_CURRENT_STATE is - when TX_SLEEP => tx_bsm <= x"0"; - if( TX_FIFOEMPTY = '0' ) then - TX_NEXT_STATE <= TX_READ; - preread_ce_comb <= '1'; - else - TX_NEXT_STATE <= TX_SLEEP; - end if; - when TX_READ => tx_bsm <= x"1"; - if ( TX_FIFOEMPTY = '1' ) then - TX_NEXT_STATE <= TX_DELAY; - preread_rst_comb <= '1'; - elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '0') ) then - TX_NEXT_STATE <= TX_DELAY; - preread_rst_comb <= '1'; - elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '1') ) then - TX_NEXT_STATE <= TX_TRANS; - preread_rst_comb <= '1'; - read_on_comb <= '1'; - else - TX_NEXT_STATE <= TX_READ; - preread_ce_comb <= '1'; - end if; - when TX_DELAY => tx_bsm <= x"2"; - if( TX_FIFOAVAIL = '1' ) then - TX_NEXT_STATE <= TX_TRANS; - read_on_comb <= '1'; - else - TX_NEXT_STATE <= TX_DELAY; - end if; - when TX_TRANS => tx_bsm <= x"3"; - if( TX_FIFOEOF = '1' ) then - TX_NEXT_STATE <= TX_CHECK; - tx_done_comb <= '1'; -- don't know if this is realistic - else - TX_NEXT_STATE <= TX_TRANS; - read_on_comb <= '1'; - end if; - when TX_CHECK => tx_bsm <= x"4"; - if( (TX_FIFOEMPTY = '0') and (TX_FIFOAVAIL = '1') ) then - TX_NEXT_STATE <= TX_READ; - preread_ce_comb <= '1'; - else - TX_NEXT_STATE <= TX_SLEEP; - end if; - when others => tx_bsm <= x"f"; - TX_NEXT_STATE <= TX_SLEEP; - end case; -end process TX_STATE_TRANSFORM; - - - - ------------------------------------------------------------------------------- --- Fake signals ------------------------------------------------------------------------------- -RX_DBOUT <= preread_ctr & tx_bsm; -- x"00"; -RX_FIFO_ERROR <= '0'; -RX_STAT_VECTOR <= x"0000_0000"; -RX_STAT_EN <= '0'; -RX_WRITE <= '0'; -RX_EOF <= '0'; -RX_ERROR <= '0'; - -TX_DISCFRM <= '0'; -TX_EN <= '0'; -TX_ER <= '0'; -TX_STATVEC <= (others => '0'); -TX_STATEN <= '0'; -TXD <= x"00"; - -CPU_IF_GBIT_EN <= '0'; - -TX_DONE <= tx_done_buf; -TX_MACREAD <= tx_macread_comb; - -HDATAOUT <= x"00"; - - -end mb_mac_sim; - - ---port map( --- -------------------------------------------------------------------------- --- --------------- clock, reset, clock enable ------------------------------- --- hclk => CLK, -- (in) host clock (100MHz) --- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz) --- rxmac_clk => '0', -- (in) not used (no receiving on GbE) --- reset_n => GSR_N, -- (in) global set/reset --- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation --- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation --- -------------------------------------------------------------------------- --- --------------- SGMII receive interface ---------------------------------- --- rxd => x"00", -- (in) receive data from SGMII core --- rx_dv => '0', -- (in) data valid from SGMII core --- rx_er => '0', -- (in) receive data error --- col => TSM_COL_IN, -- (in) collision from SGMII core --- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core --- -------------------------------------------------------------------------- --- --------------- SGMII transmit interface --------------------------------- --- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core --- tx_en => CH_TX_EN_OUT, -- (out) transmit enable --- tx_er => CH_TX_ER_OUT, -- (out) transmit error --- -------------------------------------------------------------------------- --- --------------- CPU configuration interface ------------------------------ --- haddr => haddr, -- (in) host address bus for configuration --- hdatain => hdataout, -- (in) host data bus for write accesses --- hcs_n => hcs, -- (in) host chip select signal --- hwrite_n => hwrite, -- (in) host write strobe signal --- hread_n => hread, -- (in) host read strobe signal --- hdataout => hdatain, -- (out) host data bus for read accesses --- hdataout_en_n => hdataout_en, -- (out) read data valid signal --- hready_n => hready, -- (out) data acknowledge signal --- cpu_if_gbit_en => open, -- (out) status bit --- -------------------------------------------------------------------------- --- --------------- Transmit FIFO interface ---------------------------------- --- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus --- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available --- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame --- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty --- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read --- tx_done => mac_tx_done, -- (out) transmit done (without errors) --- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer --- tx_sndpausreq => '0', -- (in) PAUSE frame request --- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control) --- tx_discfrm => open, -- (out) discard frame --- tx_staten => open, -- (out) transmit statistics vector enable --- tx_statvec => open, -- (out) transmit statistics vector --- -------------------------------------------------------------------------- --- --------------- Receive FIFO interface ----------------------------------- --- rx_dbout => open, -- (out) receive FIFO data output --- rx_fifo_full => '0', -- (in) receive FIFO full --- ignore_pkt => '0', -- (in) ignore next packet --- rx_fifo_error => open, -- (out) receive FIFO error --- rx_stat_vector => open, -- (out) receive statistics vector --- rx_stat_en => open, -- (out) receive statistics vector enable --- rx_write => open, -- (out) receive FIFO write --- rx_eof => open, -- (out) end of frame --- rx_error => open -- (out) receive packet error ---); diff --git a/gbe2_ecp3/slv_mac_memory.vhd b/gbe2_ecp3/slv_mac_memory.vhd deleted file mode 100755 index bd74e03..0000000 --- a/gbe2_ecp3/slv_mac_memory.vhd +++ /dev/null @@ -1,178 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; - -entity slv_mac_memory is -port( - CLK : in std_logic; - RESET : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(7 downto 0); - MEM_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG -); -end entity; - -architecture Behavioral of slv_mac_memory is - -component ip_mem is -port( - DataInA : in std_logic_vector(31 downto 0); - DataInB : in std_logic_vector(31 downto 0); - AddressA : in std_logic_vector(7 downto 0); - AddressB : in std_logic_vector(7 downto 0); - ClockA : in std_logic; - ClockB : in std_logic; - ClockEnA : in std_logic; - ClockEnB : in std_logic; - WrA : in std_logic; - WrB : in std_logic; - ResetA : in std_logic; - ResetB : in std_logic; - QA : out std_logic_vector(31 downto 0); - QB : out std_logic_vector(31 downto 0) -); -end component ip_mem; - --- Signals -type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); -signal CURRENT_STATE, NEXT_STATE: STATES; - --- slave bus signals -signal slv_busy_x : std_logic; -signal slv_busy : std_logic; -signal slv_ack_x : std_logic; -signal slv_ack : std_logic; -signal store_wr_x : std_logic; -signal store_wr : std_logic; -signal store_rd_x : std_logic; -signal store_rd : std_logic; - -signal reg_busy : std_logic; - -begin - --- Fake -reg_busy <= busy_in; -stat <= (others => '0'); - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- --- State memory process -STATE_MEM: process( clk ) -begin - if( rising_edge(clk) ) then - if( reset = '1' ) then - CURRENT_STATE <= SLEEP; - slv_busy <= '0'; - slv_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - slv_busy <= slv_busy_x; - slv_ack <= slv_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; -end process STATE_MEM; - --- Transition matrix -TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) -begin - NEXT_STATE <= SLEEP; - slv_busy_x <= '0'; - slv_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_RDY; - store_rd_x <= '1'; - elsif( (reg_busy = '0') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_RDY; - store_wr_x <= '1'; - elsif( (reg_busy = '1') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_BSY; - elsif( (reg_busy = '1') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_BSY; - else - NEXT_STATE <= SLEEP; - end if; - when RD_RDY => NEXT_STATE <= RD_ACK; - when WR_RDY => NEXT_STATE <= WR_ACK; - when RD_ACK => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - slv_ack_x <= '1'; - else - NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - end if; - when WR_ACK => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - slv_ack_x <= '1'; - else - NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - end if; - when RD_BSY => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; - end if; - when WR_BSY => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; - end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - ---------------------------------------------------------- --- data handling -- ---------------------------------------------------------- - -THE_MAC_MEM: ip_mem -port map( - DataInA => slv_data_in, - AddressA => slv_addr_in, - ClockA => clk, - ClockEnA => '1', - QA => slv_data_out, - WrA => store_wr, - ResetA => reset, - DataInB => x"0000_0000", - AddressB => mem_addr_in, - ClockB => mem_clk_in, - ClockEnB => '1', - WrB => '0', -- never write - ResetB => reset, - QB => mem_data_out -); - --- output signals -slv_ack_out <= slv_ack; -slv_busy_out <= slv_busy; - -end Behavioral; diff --git a/gbe2_ecp3/slv_register.vhd b/gbe2_ecp3/slv_register.vhd deleted file mode 100755 index 763550b..0000000 --- a/gbe2_ecp3/slv_register.vhd +++ /dev/null @@ -1,177 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; ---use work.adcmv3_components.all; - - -entity slv_register is -generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - REG_DATA_IN : in std_logic_vector(31 downto 0); - REG_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); -end entity; - -architecture Behavioral of slv_register is - --- Signals - - type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- slave bus signals - signal slv_busy_x : std_logic; - signal slv_busy : std_logic; - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input - signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data - signal reg_busy : std_logic; - -begin - --- Fake -reg_busy <= busy_in; -stat <= (others => '0'); - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- --- State memory process -STATE_MEM: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - slv_busy <= '0'; - slv_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - slv_busy <= slv_busy_x; - slv_ack <= slv_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; -end process STATE_MEM; - --- Transition matrix -TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) -begin - NEXT_STATE <= SLEEP; - slv_busy_x <= '0'; - slv_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_RDY; - store_rd_x <= '1'; - elsif( (reg_busy = '0') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_RDY; - store_wr_x <= '1'; - elsif( (reg_busy = '1') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; -- added 23022009 - elsif( (reg_busy = '1') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; -- added 23022009 - else - NEXT_STATE <= SLEEP; - end if; - when RD_RDY => NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - when WR_RDY => NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - when RD_ACK => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - end if; - when WR_ACK => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - end if; - when RD_BSY => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; - end if; - when WR_BSY => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; - end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - ---------------------------------------------------------- --- data handling -- ---------------------------------------------------------- - --- register write -THE_WRITE_REG_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - reg_slv_data_in <= RESET_VALUE; - elsif( store_wr = '1' ) then - reg_slv_data_in <= slv_data_in; - end if; - end if; -end process THE_WRITE_REG_PROC; - --- register read -THE_READ_REG_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - reg_slv_data_out <= (others => '0'); - elsif( store_rd = '1' ) then - reg_slv_data_out <= reg_data_in; - end if; - end if; -end process THE_READ_REG_PROC; - --- output signals -slv_ack_out <= slv_ack; -slv_busy_out <= slv_busy; -slv_data_out <= reg_slv_data_out; - ---------------------------------------------------------- --- signals to backend -- ---------------------------------------------------------- - -reg_data_out <= reg_slv_data_in; - -end Behavioral; diff --git a/gbe2_ecp3/tb_feeder.vhd b/gbe2_ecp3/tb_feeder.vhd deleted file mode 100755 index d526404..0000000 --- a/gbe2_ecp3/tb_feeder.vhd +++ /dev/null @@ -1,300 +0,0 @@ - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT feeder - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); - CTS_CODE_IN : IN std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : IN std_logic; - CTS_READ_IN : IN std_logic; - FEE_DATA_IN : IN std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : IN std_logic; - FEE_BUSY_IN : IN std_logic; - FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); - PC_READY_IN : IN std_logic; - CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : OUT std_logic; - CTS_READOUT_FINISHED_OUT : OUT std_logic; - CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); - FEE_READ_OUT : OUT std_logic; - PC_WR_EN_OUT : OUT std_logic; - PC_DATA_OUT : OUT std_logic_vector(7 downto 0); - PC_SOS_OUT : OUT std_logic; - PC_EOD_OUT : OUT std_logic; - PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); - PC_PADDING_OUT : OUT std_logic; - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : OUT std_logic; - DBG_SF_WR_EN_OUT : OUT std_logic; - DBG_SF_EMPTY_OUT : OUT std_logic; - DBG_SF_FULL_OUT : OUT std_logic; - DBG_SF_AFULL_OUT : OUT std_logic; - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL PC_WR_EN_OUT : std_logic; - SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL PC_READY_IN : std_logic; - SIGNAL PC_SOS_OUT : std_logic; - SIGNAL PC_EOD_OUT : std_logic; - SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_PADDING_OUT : std_logic; - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); - SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); - SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RD_EN_OUT : std_logic; - SIGNAL DBG_SF_WR_EN_OUT : std_logic; - SIGNAL DBG_SF_EMPTY_OUT : std_logic; - SIGNAL DBG_SF_FULL_OUT : std_logic; - SIGNAL DBG_SF_AFULL_OUT : std_logic; - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: feeder PORT MAP( - CLK => CLK, - RESET => RESET, - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => CTS_READ_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - PC_WR_EN_OUT => PC_WR_EN_OUT, - PC_DATA_OUT => PC_DATA_OUT, - PC_READY_IN => PC_READY_IN, - PC_SOS_OUT => PC_SOS_OUT, - PC_EOD_OUT => PC_EOD_OUT, - PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, - PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, - PC_PADDING_OUT => PC_PADDING_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, - DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, - DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, - DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, - DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, - DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, - DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, - DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, - DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, - DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, - DEBUG_OUT => DEBUG_OUT - ); - -CLOCK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN; - --- Testbench -TESTBENCH_PROC: process -variable test_data_len : integer range 0 to 65535 := 49; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; -begin - -- Setup signals - reset <= '0'; - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"0000_0000"; - fee_busy_in <= '0'; - pc_ready_in <= '0'; - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 9; - test_data_len := 14; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - -- IPU transmission starts - wait until rising_edge(clk); - cts_number_in <= std_logic_vector( trigger_counter ); - cts_code_in <= x"aa"; - cts_information_in <= x"de"; - cts_readout_type_in <= x"1"; - cts_start_readout_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - fee_busy_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - -- ONE DATA TRANSMISSION - -- calculate the needed variables --- test_data_len := 4096; - test_loop_len := 2*(test_data_len - 1) + 1; - test_hdr_len := to_unsigned( test_data_len + 1, 16 ); - test_evt_len := to_unsigned( test_data_len, 16 ); - - -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) - fee_dataready_in <= '1'; - fee_data_in <= x"10aa"; - wait until rising_edge(clk); - fee_data_in <= std_logic_vector( trigger_counter ); - wait until rising_edge(clk); - fee_data_in <= std_logic_vector( test_hdr_len ); - wait until rising_edge(clk); - fee_data_in <= x"ff21"; - wait until rising_edge(clk); - fee_data_in <= std_logic_vector( test_evt_len ); - wait until rising_edge(clk); - fee_data_in <= x"ff22"; - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - wait until rising_edge(clk); - fee_data_in <= std_logic_vector(test_data); - end loop MY_DATA_LOOP; - - fee_busy_in <= '0'; -- correct? - wait until rising_edge(clk); - fee_dataready_in <= '0'; - fee_data_in <= x"0000"; - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_read_in <= '1'; - wait until rising_edge(clk); - cts_read_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_start_readout_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - end loop MY_TRIGGER_LOOP; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - - - wait for 300 ns; - - -- Start packet_constructor - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_ready_in <= '1'; - wait until rising_edge(clk); - - wait; - - wait until rising_edge(clk); - wait until pc_eod_out = '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_ready_in <= '0'; - - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - - -END; diff --git a/gbe2_ecp3/tb_frame_receiver.vhd b/gbe2_ecp3/tb_frame_receiver.vhd deleted file mode 100644 index 8b0ed20..0000000 --- a/gbe2_ecp3/tb_frame_receiver.vhd +++ /dev/null @@ -1,2686 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -USE ieee.math_real.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity tb_frame_receiver is -end tb_frame_receiver; - -architecture behavior of tb_frame_receiver is - -component trb_net16_hub_streaming_port_sctrl is - generic( - --hub control - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; - CLOCK_FREQUENCY : integer range 1 to 200 := 100; - USE_ONEWIRE : integer range 0 to 2 := c_YES; - BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; - --media interfaces - MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; - MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); - MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); - MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO) - ); - - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - --Media Interface - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0); - MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0); - - --Event information coming from CTS - CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); - CTS_CODE_OUT : out std_logic_vector (7 downto 0); - CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - CTS_START_READOUT_OUT : out std_logic; - - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_IN : in std_logic_vector (31 downto 0); - CTS_DATAREADY_IN : in std_logic; - CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM - CTS_READ_OUT : out std_logic; - CTS_LENGTH_IN : in std_logic_vector (15 downto 0); - CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - - -- Data from Frontends - FEE_DATA_OUT : out std_logic_vector (15 downto 0); - FEE_DATAREADY_OUT : out std_logic; - FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready - FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - FEE_BUSY_OUT : out std_logic; - - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - - COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs - COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs - ONEWIRE : inout std_logic; - ONEWIRE_MONITOR_IN : in std_logic; - ONEWIRE_MONITOR_OUT : out std_logic; - MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - UNIQUE_ID_OUT : out std_logic_vector (63 downto 0); - - --REGIO INTERFACE - REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); - REGIO_READ_ENABLE_OUT : out std_logic; - REGIO_WRITE_ENABLE_OUT : out std_logic; - REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); - REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); - REGIO_DATAREADY_IN : in std_logic := '0'; - REGIO_NO_MORE_DATA_IN : in std_logic := '0'; - REGIO_WRITE_ACK_IN : in std_logic := '0'; - REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; - REGIO_TIMEOUT_OUT : out std_logic; - - - --Gbe Sctrl Input - GSC_INIT_DATAREADY_IN : in std_logic; - GSC_INIT_DATA_IN : in std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_INIT_READ_OUT : out std_logic; - GSC_REPLY_DATAREADY_OUT : out std_logic; - GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_REPLY_READ_IN : in std_logic; - GSC_BUSY_OUT : out std_logic; - - --status and control ports - HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); - HUB_STAT_GEN : out std_logic_vector (31 downto 0); - MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); - MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); - STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs - STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs - --Debugging registers - STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging - CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging - ); -end component; - -signal CLK : std_logic; -signal RESET : std_logic; -signal LINK_OK_IN : std_logic; -signal ALLOW_RX_IN : std_logic; -signal RX_MAC_CLK : std_logic; -signal MAC_RX_EOF_IN : std_logic; -signal MAC_RX_ER_IN : std_logic; -signal MAC_RXD_IN : std_logic_vector(7 downto 0); -signal MAC_RX_EN_IN : std_logic; -signal MAC_RX_FIFO_ERR_IN : std_logic; -signal MAC_RX_FIFO_FULL_OUT : std_logic; -signal MAC_RX_STAT_EN_IN : std_logic; -signal MAC_RX_STAT_VEC_IN : std_logic_vector(31 downto 0); -signal FR_Q_OUT : std_logic_vector(8 downto 0); -signal FR_RD_EN_IN : std_logic; -signal FR_FRAME_VALID_OUT : std_logic; -signal FR_GET_FRAME_IN : std_logic; -signal FR_FRAME_SIZE_OUT : std_logic_vector(15 downto 0); -signal FR_FRAME_PROTO_OUT : std_logic_vector(15 downto 0); -signal DEBUG_OUT : std_logic_vector(95 downto 0); -signal FR_ALLOWED_TYPES_IN : std_logic_vector(31 downto 0); - -signal RC_RD_EN_IN : std_logic; -signal RC_Q_OUT : std_logic_vector(8 downto 0); -signal RC_FRAME_WAITING_OUT : std_logic; -signal RC_LOADING_DONE_IN : std_logic; -signal RC_FRAME_SIZE_OUT : std_logic_vector(15 downto 0); -signal FRAMES_RECEIVED_OUT : std_logic_vector(31 downto 0); -signal BYTES_RECEIVED_OUT : std_logic_vector(31 downto 0); - -signal MC_TRANSMIT_CTRL_OUT : std_logic; -signal MC_TRANSMIT_DATA_OUT : std_logic; -signal MC_DATA_OUT : std_logic_vector(8 downto 0); -signal MC_RD_EN_IN : std_logic; -signal MC_FRAME_SIZE_OUT : std_logic_vector(15 downto 0); -signal MC_BUSY_IN : std_logic; -signal MC_TRANSMIT_DONE_IN : std_logic; -signal RC_FRAME_PROTO_OUT : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - -signal fc_data : std_logic_vector(7 downto 0); -signal fc_wr_en : std_logic; -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_h_ready : std_logic; -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal fc_ready : std_logic; -signal fc_dest_mac : std_logic_vector(47 downto 0); -signal fc_dest_ip : std_logic_vector(31 downto 0); -signal fc_dest_udp : std_logic_vector(15 downto 0); -signal fc_src_mac : std_logic_vector(47 downto 0); -signal fc_src_ip : std_logic_vector(31 downto 0); -signal fc_src_udp : std_logic_vector(15 downto 0); -signal fc_type : std_logic_vector(15 downto 0); -signal mc_type : std_logic_vector(15 downto 0); -signal fc_ihl : std_logic_vector(7 downto 0); -signal fc_tos : std_logic_vector(7 downto 0); -signal fc_ident : std_logic_vector(15 downto 0); -signal fc_flags : std_logic_vector(15 downto 0); -signal fc_ttl : std_logic_vector(7 downto 0); -signal fc_proto : std_logic_vector(7 downto 0); -signal fr_src_mac : std_logic_vector(47 downto 0); -signal fr_dest_mac : std_logic_vector(47 downto 0); -signal fr_src_ip : std_logic_vector(31 downto 0); -signal fr_dest_ip : std_logic_vector(31 downto 0); -signal fr_src_udp : std_logic_vector(15 downto 0); -signal fr_dest_udp : std_logic_vector(15 downto 0); -signal rc_src_mac : std_logic_vector(47 downto 0); -signal rc_dest_mac : std_logic_vector(47 downto 0); -signal rc_src_ip : std_logic_vector(31 downto 0); -signal rc_dest_ip : std_logic_vector(31 downto 0); -signal rc_src_udp : std_logic_vector(15 downto 0); -signal rc_dest_udp : std_logic_vector(15 downto 0); - -signal mc_dest_mac : std_logic_vector(47 downto 0); -signal mc_dest_ip : std_logic_vector(31 downto 0); -signal mc_dest_udp : std_logic_vector(15 downto 0); -signal mc_src_mac : std_logic_vector(47 downto 0); -signal mc_src_ip : std_logic_vector(31 downto 0); -signal mc_src_udp : std_logic_vector(15 downto 0); - -signal fr_allowed_ip : std_logic_vector(31 downto 0); -signal fr_allowed_udp : std_logic_vector(31 downto 0); - -signal fr_ip_proto : std_logic_vector(7 downto 0); -signal mc_ip_proto : std_logic_vector(7 downto 0); - -signal additional_rand_pause : std_logic; - -signal pc_ready, pc_sos, pc_transmit_on, pc_wr_en, pc_sod, pc_eod, pc_fc_h_ready, pc_fc_ready : std_logic; -signal pc_data : std_logic_vector(7 downto 0); -signal pc_ip_size, pc_udp_size : std_logic_vector(15 downto 0); -signal gsc_init_read, gsc_init_dataready : std_logic; -signal gsc_reply_read, gsc_reply_dataready : std_logic; -signal gsc_reply_data, gsc_init_data : std_logic_vector(15 downto 0); -signal gsc_busy : std_logic; -signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); -signal mc_flags, mc_ip_size, mc_udp_size : std_logic_vector(15 downto 0); - -begin - -HUB_STR : trb_net16_hub_streaming_port_sctrl - generic map( - --media interfaces - MII_NUMBER => 5, - MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), - MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), - MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0) - ) - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => '1', - - --Media Interface - MED_DATAREADY_OUT => open, - MED_DATA_OUT => open, - MED_PACKET_NUM_OUT => open, - MED_READ_IN => (others => '0'), - MED_DATAREADY_IN => (others => '0'), - MED_DATA_IN => (others => '0'), - MED_PACKET_NUM_IN => (others => '0'), - MED_READ_OUT => open, - MED_STAT_OP => x"0007_0007_0007_0007_0007", - MED_CTRL_OP => open, - - --Event information coming from CTS - CTS_NUMBER_OUT => open, - CTS_CODE_OUT => open, - CTS_INFORMATION_OUT => open, - CTS_READOUT_TYPE_OUT => open, - CTS_START_READOUT_OUT => open, - - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_IN => (others => '0'), - CTS_DATAREADY_IN => '0', - CTS_READOUT_FINISHED_IN => '0', - CTS_READ_OUT => open, - CTS_LENGTH_IN => (others => '0'), - CTS_STATUS_BITS_IN => (others => '0'), - - -- Data from Frontends - FEE_DATA_OUT => open, - FEE_DATAREADY_OUT => open, - FEE_READ_IN => '0', - FEE_STATUS_BITS_OUT => open, - FEE_BUSY_OUT => open, - - MY_ADDRESS_IN => (others => '0'), - - COMMON_STAT_REGS => open, - COMMON_CTRL_REGS => open, - ONEWIRE => open, - ONEWIRE_MONITOR_IN => '0', - ONEWIRE_MONITOR_OUT => open, - MY_ADDRESS_OUT => open, - UNIQUE_ID_OUT => open, - - --REGIO INTERFACE - REGIO_ADDR_OUT => open, - REGIO_READ_ENABLE_OUT => open, - REGIO_WRITE_ENABLE_OUT => open, - REGIO_DATA_OUT => open, - REGIO_DATA_IN => (others => '0'), - REGIO_DATAREADY_IN => '0', - REGIO_NO_MORE_DATA_IN => '0', - REGIO_WRITE_ACK_IN => '0', - REGIO_UNKNOWN_ADDR_IN => '0', - REGIO_TIMEOUT_OUT => open, - - - --Gbe Sctrl Input - GSC_INIT_DATAREADY_IN => gsc_init_dataready, - GSC_INIT_DATA_IN => gsc_init_data, - GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, - GSC_INIT_READ_OUT => gsc_init_read, - GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, - GSC_REPLY_DATA_OUT => gsc_reply_data, - GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, - GSC_REPLY_READ_IN => gsc_reply_read, - GSC_BUSY_OUT => gsc_busy, - - --status and control ports - HUB_STAT_CHANNEL => open, - HUB_STAT_GEN => open, - MPLEX_CTRL => (others => '0'), - MPLEX_STAT => open, - STAT_REGS => open, - STAT_CTRL_REGS => open, - --Debugging registers - STAT_DEBUG => open, - CTRL_DEBUG => (others => '0') - ); - -packet_constr : trb_net16_gbe_packet_constr -port map( - RESET => RESET, - CLK => CLK, - MULT_EVT_ENABLE_IN => '0', - -- ports for user logic - PC_WR_EN_IN => '0', - PC_DATA_IN => (others => '0'), - PC_READY_OUT => pc_ready, - PC_START_OF_SUB_IN => pc_sos, - PC_END_OF_SUB_IN => '0', - PC_END_OF_DATA_IN => '0', - PC_TRANSMIT_ON_OUT => pc_transmit_on, - -- queue and subevent layer headers - PC_SUB_SIZE_IN => (others => '0'), - PC_PADDING_IN => '0', - PC_DECODING_IN => (others => '0'), - PC_EVENT_ID_IN => (others => '0'), - PC_TRIG_NR_IN => (others => '0'), - PC_QUEUE_DEC_IN => (others => '0'), - PC_MAX_FRAME_SIZE_IN => (others => '0'), - PC_DELAY_IN => (others => '0'), - -- FrameConstructor ports - TC_WR_EN_OUT => pc_wr_en, - TC_DATA_OUT => pc_data, - TC_H_READY_IN => pc_fc_h_ready, - TC_READY_IN => pc_fc_ready, - TC_IP_SIZE_OUT => pc_ip_size, - TC_UDP_SIZE_OUT => pc_udp_size, - TC_FLAGS_OFFSET_OUT => open, - TC_SOD_OUT => pc_sod, - TC_EOD_OUT => pc_eod, - DEBUG_OUT => open -); - -receiver : trb_net16_gbe_frame_receiver -port map ( - CLK => CLK, - RESET => RESET, - LINK_OK_IN => LINK_OK_IN, - ALLOW_RX_IN => ALLOW_RX_IN, - RX_MAC_CLK => RX_MAC_CLK, - - MAC_RX_EOF_IN => MAC_RX_EOF_IN, - MAC_RX_ER_IN => MAC_RX_ER_IN, - MAC_RXD_IN => MAC_RXD_IN, - MAC_RX_EN_IN => MAC_RX_EN_IN, - MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN, - MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFO_FULL_OUT, - MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN, - MAC_RX_STAT_VEC_IN => MAC_RX_STAT_VEC_IN, - - FR_Q_OUT => FR_Q_OUT, - FR_RD_EN_IN => FR_RD_EN_IN, - FR_FRAME_VALID_OUT => FR_FRAME_VALID_OUT, - FR_GET_FRAME_IN => FR_GET_FRAME_IN, - FR_FRAME_SIZE_OUT => FR_FRAME_SIZE_OUT, - FR_FRAME_PROTO_OUT => FR_FRAME_PROTO_OUT, - FR_IP_PROTOCOL_OUT => fr_ip_proto, - FR_ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN, - FR_ALLOWED_IP_IN => fr_allowed_ip, - FR_ALLOWED_UDP_IN => fr_allowed_udp, - FR_VLAN_ID_IN => x"aabb_0000", - - FR_SRC_MAC_ADDRESS_OUT => fr_src_mac, - FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac, - FR_SRC_IP_ADDRESS_OUT => fr_src_ip, - FR_DEST_IP_ADDRESS_OUT => fr_dest_ip, - FR_SRC_UDP_PORT_OUT => fr_src_udp, - FR_DEST_UDP_PORT_OUT => fr_dest_udp, - - DEBUG_OUT => DEBUG_OUT -); - -receive_controler : trb_net16_gbe_receive_control -port map( - CLK => CLK, - RESET => RESET, - --- signals to/from frame_receiver - RC_DATA_IN => FR_Q_OUT, - FR_RD_EN_OUT => FR_RD_EN_IN, - FR_FRAME_VALID_IN => FR_FRAME_VALID_OUT, - FR_GET_FRAME_OUT => FR_GET_FRAME_IN, - FR_FRAME_SIZE_IN => FR_FRAME_SIZE_OUT, - FR_FRAME_PROTO_IN => FR_FRAME_PROTO_OUT, - FR_IP_PROTOCOL_IN => fr_ip_proto, - - FR_SRC_MAC_ADDRESS_IN => fr_src_mac, - FR_DEST_MAC_ADDRESS_IN => fr_dest_mac, - FR_SRC_IP_ADDRESS_IN => fr_src_ip, - FR_DEST_IP_ADDRESS_IN => fr_dest_ip, - FR_SRC_UDP_PORT_IN => fr_src_udp, - FR_DEST_UDP_PORT_IN => fr_dest_udp, - --- signals to/from main controller - RC_RD_EN_IN => RC_RD_EN_IN, - RC_Q_OUT => RC_Q_OUT, - RC_FRAME_WAITING_OUT => RC_FRAME_WAITING_OUT, - RC_LOADING_DONE_IN => RC_LOADING_DONE_IN, - RC_FRAME_SIZE_OUT => RC_FRAME_SIZE_OUT, - RC_FRAME_PROTO_OUT => RC_FRAME_PROTO_OUT, - - RC_SRC_MAC_ADDRESS_OUT => rc_src_mac, - RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac, - RC_SRC_IP_ADDRESS_OUT => rc_src_ip, - RC_DEST_IP_ADDRESS_OUT => rc_dest_ip, - RC_SRC_UDP_PORT_OUT => rc_src_udp, - RC_DEST_UDP_PORT_OUT => rc_dest_udp, - --- statistics - FRAMES_RECEIVED_OUT => open, - BYTES_RECEIVED_OUT => open, - - DEBUG_OUT => open -); - -main_controller : trb_net16_gbe_main_control -port map ( - CLK => CLK, - CLK_125 => RX_MAC_CLK, - RESET => RESET, - - MC_LINK_OK_OUT => open, - MC_RESET_LINK_IN => '0', - --- signals to/from receive controller - RC_FRAME_WAITING_IN => RC_FRAME_WAITING_OUT, - RC_LOADING_DONE_OUT => RC_LOADING_DONE_IN, - RC_DATA_IN => RC_Q_OUT, - RC_RD_EN_OUT => RC_RD_EN_IN, - RC_FRAME_SIZE_IN => RC_FRAME_SIZE_OUT, - RC_FRAME_PROTO_IN => RC_FRAME_PROTO_OUT, - - RC_SRC_MAC_ADDRESS_IN => rc_src_mac, - RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, - RC_SRC_IP_ADDRESS_IN => rc_src_ip, - RC_DEST_IP_ADDRESS_IN => rc_dest_ip, - RC_SRC_UDP_PORT_IN => rc_src_udp, - RC_DEST_UDP_PORT_IN => rc_dest_udp, - --- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT => MC_TRANSMIT_CTRL_OUT, - TC_TRANSMIT_DATA_OUT => MC_TRANSMIT_DATA_OUT, - TC_DATA_OUT => MC_DATA_OUT, - TC_RD_EN_IN => MC_RD_EN_IN, - TC_FRAME_SIZE_OUT => MC_FRAME_SIZE_OUT, - TC_FRAME_TYPE_OUT => mc_type, - TC_IP_PROTOCOL_OUT => mc_ip_proto, - - TC_DEST_MAC_OUT => mc_dest_mac, - TC_DEST_IP_OUT => mc_dest_ip, - TC_DEST_UDP_OUT => mc_dest_udp, - TC_SRC_MAC_OUT => mc_src_mac, - TC_SRC_IP_OUT => mc_src_ip, - TC_SRC_UDP_OUT => mc_src_udp, - - TC_IP_SIZE_OUT => mc_ip_size, - TC_UDP_SIZE_OUT => mc_udp_size, - TC_FLAGS_OFFSET_OUT => mc_flags, - - TC_BUSY_IN => MC_BUSY_IN, - TC_TRANSMIT_DONE_IN => MC_TRANSMIT_DONE_IN, - --- signals to/from packet constructor - PC_READY_IN => pc_ready, - PC_TRANSMIT_ON_IN => pc_transmit_on, - PC_SOD_IN => pc_sod, - --- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN => '1', - --- signals to/from hub - MC_UNIQUE_ID_IN => (others => '0'), - - GSC_CLK_IN => CLK, - GSC_INIT_DATAREADY_OUT => gsc_init_dataready, - GSC_INIT_DATA_OUT => gsc_init_data, - GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, - GSC_INIT_READ_IN => gsc_init_read, - GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, - GSC_REPLY_DATA_IN => gsc_reply_data, - GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, - GSC_REPLY_READ_OUT => gsc_reply_read, - GSC_BUSY_IN => gsc_busy, - --- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT => open, - TSM_HDATA_OUT => open, - TSM_HCS_N_OUT => open, - TSM_HWRITE_N_OUT => open, - TSM_HREAD_N_OUT => open, - TSM_HREADY_N_IN => '0', - TSM_HDATA_EN_N_IN => '1', - TSM_RX_STAT_VEC_IN => (others => '0'), - TSM_RX_STAT_EN_IN => '0', - - DEBUG_OUT => open -); - -transmit_controller : trb_net16_gbe_transmit_control -port map( - CLK => CLK, - RESET => RESET, - --- signals to/from packet constructor - PC_READY_IN => pc_ready, --'1', - PC_DATA_IN => pc_data, --(others => '0'), - PC_WR_EN_IN => pc_wr_en, --'0', - PC_IP_SIZE_IN => pc_ip_size, - PC_UDP_SIZE_IN => pc_udp_size, - PC_FLAGS_OFFSET_IN => (others => '0'), - PC_SOD_IN => pc_sod, - PC_EOD_IN => pc_eod, - PC_FC_READY_OUT => pc_fc_ready, - PC_FC_H_READY_OUT => pc_fc_h_ready, - PC_TRANSMIT_ON_IN => '0', - - -- signals from ip_configurator used by packet constructor - IC_DEST_MAC_ADDRESS_IN => x"112233445566", - IC_DEST_IP_ADDRESS_IN => x"aabbccdd", - IC_DEST_UDP_PORT_IN => x"0101", - IC_SRC_MAC_ADDRESS_IN => x"665544332211", - IC_SRC_IP_ADDRESS_IN => x"ddccbbaa", - IC_SRC_UDP_PORT_IN => x"0202", - --- signal to/from main controller - MC_TRANSMIT_CTRL_IN => MC_TRANSMIT_CTRL_OUT, - MC_TRANSMIT_DATA_IN => MC_TRANSMIT_DATA_OUT, - MC_DATA_IN => MC_DATA_OUT, - MC_RD_EN_OUT => MC_RD_EN_IN, - MC_FRAME_SIZE_IN => MC_FRAME_SIZE_OUT, - MC_FRAME_TYPE_IN => mc_type, - MC_IP_PROTOCOL_IN => mc_ip_proto, - - MC_DEST_MAC_IN => mc_dest_mac, - MC_DEST_IP_IN => mc_dest_ip, - MC_DEST_UDP_IN => mc_dest_udp, - MC_SRC_MAC_IN => mc_src_mac, - MC_SRC_IP_IN => mc_src_ip, - MC_SRC_UDP_IN => mc_src_udp, - - MC_IP_SIZE_IN => mc_ip_size, - MC_UDP_SIZE_IN => mc_udp_size, - MC_FLAGS_OFFSET_IN => mc_flags, - - MC_BUSY_OUT => MC_BUSY_IN, - MC_TRANSMIT_DONE_OUT => MC_TRANSMIT_DONE_IN, - --- signal to/from frame constructor - FC_DATA_OUT => fc_data, - FC_WR_EN_OUT => fc_wr_en, - FC_READY_IN => fc_ready, - FC_H_READY_IN => fc_h_ready, - FC_FRAME_TYPE_OUT => fc_type, - FC_IP_SIZE_OUT => fc_ip_size, - FC_UDP_SIZE_OUT => fc_udp_size, - FC_IDENT_OUT => fc_ident, - FC_FLAGS_OFFSET_OUT => fc_flags, - FC_SOD_OUT => fc_sod, - FC_EOD_OUT => fc_eod, - FC_IP_PROTOCOL_OUT => fc_proto, - - DEST_MAC_ADDRESS_OUT => fc_dest_mac, - DEST_IP_ADDRESS_OUT => fc_dest_ip, - DEST_UDP_PORT_OUT => fc_dest_udp, - SRC_MAC_ADDRESS_OUT => fc_src_mac, - SRC_IP_ADDRESS_OUT => fc_src_ip, - SRC_UDP_PORT_OUT => fc_src_udp, - - DEBUG_OUT => open -); - -frame_constructor : trb_net16_gbe_frame_constr -port map( - -- ports for user logic - RESET => RESET, - CLK => CLK, - LINK_OK_IN => '1', - -- - WR_EN_IN => fc_wr_en, - DATA_IN => fc_data, - START_OF_DATA_IN => fc_sod, - END_OF_DATA_IN => fc_eod, - IP_F_SIZE_IN => fc_ip_size, - UDP_P_SIZE_IN => fc_udp_size, - HEADERS_READY_OUT => fc_h_ready, - READY_OUT => fc_ready, - DEST_MAC_ADDRESS_IN => fc_dest_mac, - DEST_IP_ADDRESS_IN => fc_dest_ip, - DEST_UDP_PORT_IN => fc_dest_udp, - SRC_MAC_ADDRESS_IN => fc_src_mac, - SRC_IP_ADDRESS_IN => fc_src_ip, - SRC_UDP_PORT_IN => fc_src_udp, - FRAME_TYPE_IN => fc_type, - IHL_VERSION_IN => fc_ihl, - TOS_IN => fc_tos, - IDENTIFICATION_IN => fc_ident, - FLAGS_OFFSET_IN => fc_flags, - TTL_IN => fc_ttl, - PROTOCOL_IN => fc_proto, - FRAME_DELAY_IN => x"0000_0000", - -- ports for packetTransmitter - RD_CLK => RX_MAC_CLK, - FT_DATA_OUT => open, - FT_TX_EMPTY_OUT => open, - FT_TX_RD_EN_IN => '1', - FT_START_OF_PACKET_OUT => open, - FT_TX_DONE_IN => '1', - FT_TX_DISCFRM_IN => '0', - -- debug ports - BSM_CONSTR_OUT => open, - BSM_TRANS_OUT => open, - DEBUG_OUT => open -); - --- 100 MHz system clock -CLOCK_GEN_PROC: process -begin - CLK <= '1'; wait for 5.0 ns; - CLK <= '0'; wait for 5.0 ns; -end process CLOCK_GEN_PROC; - --- 125 MHz MAC clock -CLOCK2_GEN_PROC: process -begin - RX_MAC_CLK <= '1'; wait for 3.0 ns; - RX_MAC_CLK <= '0'; wait for 4.0 ns; -end process CLOCK2_GEN_PROC; - -CHECK_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - assert DEBUG_OUT(1) = '0' and DEBUG_OUT(3) = '0' report "FIFO FULL" severity error; - end if; -end process CHECK_PROC; - - -TESTBENCH_PROC : process - -variable seed1 : positive; -- seed for random generator -variable seed2 : positive; -- seed for random generator -variable rand : real; -- random value (0.0 ... 1.0) -variable int_rand : integer; -- random value, scaled to your needs - -begin - - wait for 50 ns; - RESET <= '1'; - - LINK_OK_IN <= '1'; - ALLOW_RX_IN <= '1'; - - MAC_RX_EOF_IN <= '0'; - MAC_RX_ER_IN <= '0'; - MAC_RXD_IN <= x"00"; - MAC_RX_EN_IN <= '0'; - MAC_RX_FIFO_ERR_IN <= '0'; - FR_ALLOWED_TYPES_IN <= x"0000_000f"; - fr_allowed_ip <= x"0000_000f"; - fr_allowed_udp <= x"0000_000f"; - additional_rand_pause <= '0'; - pc_sos <= '0'; --- gsc_init_read <= '0'; --- gsc_busy <= '0'; --- gsc_reply_data <= (others => '0'); --- gsc_reply_dataready <= '0'; --- - wait for 10 ns; - RESET <= '0'; - wait for 50 ns; - - --for i in 0 to 1000 loop - - wait for 400 ns; - - -- FIRST FRAME UDP - DHCP Offer - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; -- udp - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- udp headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"43"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"2c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; --- dhcp data - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"de"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ad"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"fa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ce"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - - for i in 0 to 219 loop - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - end loop; - - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"35"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - wait for 1 us; - - -- FIRST FRAME UDP - DHCP Offer - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; -- udp - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- udp headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"43"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"2c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; --- dhcp data - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"de"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ad"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"fa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ce"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - - for i in 0 to 219 loop - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - end loop; - - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"35"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"05"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - - wait; - - - -- FIRST FRAME (ARP Request) - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- arp frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); --- hardware type - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- protocol type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- hardware size - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); --- protocol size - MAC_RXD_IN <= x"04"; - wait until rising_edge(RX_MAC_CLK); --- opcode (request) - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- sender mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- sender ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a9"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- target mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- target ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"65"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - -- FIRST FRAME UDP - SCTRL READ REQUEST --- wait until rising_edge(RX_MAC_CLK); --- MAC_RX_EN_IN <= '1'; ----- dest mac --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); ----- src mac --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"aa"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"bb"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"cc"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"dd"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ee"; --- wait until rising_edge(RX_MAC_CLK); ----- frame type --- MAC_RXD_IN <= x"08"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); ----- ip headers --- MAC_RXD_IN <= x"45"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"10"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"01"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"5a"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"49"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"11"; -- udp --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"cc"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"cc"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"c0"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"a8"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"01"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"c0"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"a8"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"02"; ----- udp headers --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"43"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"61"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"a8"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"02"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"2c"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"aa"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"bb"; ----- sctrl data --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"31"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ff"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"08"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"30"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"50"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"af"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"fe"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"de"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"ad"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"33"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"08"; --- MAC_RX_EOF_IN <= '1'; --- wait until rising_edge(RX_MAC_CLK); --- --- MAC_RX_EN_IN <='0'; --- MAC_RX_EOF_IN <= '0'; - - --- wait until rising_edge(gsc_init_dataready); --- wait until rising_edge(CLK); --- gsc_init_read <= '1'; --- --- wait until falling_edge(gsc_init_dataready); --- wait until rising_edge(CLK); --- gsc_init_read <= '0'; --- --- --wait for 100 ns; --- --wait until rising_edge(gsc_reply_read); --- wait until rising_edge(CLK); --- wait until rising_edge(CLK); --- wait until rising_edge(CLK); --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0101"; --- gsc_reply_dataready <= '1'; --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0202"; --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0303"; --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0404"; --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0505"; --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0606"; --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0707"; --- wait until rising_edge(CLK); --- gsc_reply_data <= x"0808"; --- wait until rising_edge(CLK); --- gsc_reply_dataready <= '0'; - - - -- STOP HERE - wait; - - - -- FIRST FRAME (ARP Request) - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- arp frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); --- hardware type - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- protocol type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- hardware size - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); --- protocol size - MAC_RXD_IN <= x"04"; - wait until rising_edge(RX_MAC_CLK); --- opcode (request) - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- sender mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- sender ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a9"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- target mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- target ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"65"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - wait; - - - - --- FIRST FRAME UDP - DHCP Offer - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; -- udp - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- udp headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"43"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"2c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; --- dhcp data - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"de"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ad"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"fa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ce"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - - for i in 0 to 219 loop - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - end loop; - - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"35"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - wait for 100 us; - - - - wait; - - - - - - - - - - - - - - -- FIRST FRAME IP - ICMP Ping request - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- ping headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"47"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"d3"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"3c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- ping data - MAC_RXD_IN <= x"8c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"da"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"e7"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"4d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"36"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c4"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"09"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0b"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0e"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0f"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - MAC_RXD_IN <= x"aa"; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - wait for 1500 ns; - - - - wait; - - - - - - -- FIRST FRAME IP - ICMP Ping request - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; -- icmp - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- ping headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"47"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"d3"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"3c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- ping data - MAC_RXD_IN <= x"8c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"da"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"e7"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"4d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"36"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c4"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"09"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0b"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0d"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0e"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"0f"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - MAC_RXD_IN <= x"aa"; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - --- end loop; - - wait for 1500 ns; - - - -- FIRST FRAME (ARP Request) - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- arp frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); --- hardware type - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- protocol type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- hardware size - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); --- protocol size - MAC_RXD_IN <= x"04"; - wait until rising_edge(RX_MAC_CLK); --- opcode (request) - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- sender mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- sender ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a9"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- target mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- target ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"65"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - - - - --- FIRST FRAME UDP - DHCP Offer - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ef"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; -- udp - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- udp headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"43"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"2c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; --- dhcp data - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"de"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ad"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"fa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ce"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - - for i in 0 to 219 loop - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - end loop; - - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"35"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - wait for 100 us; - - --- FIRST FRAME UDP - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ab"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"40"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- udp headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"2c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); --- few data words - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"03"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"04"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - wait for 100 ns; - - -- FIRST FRAME (ARP Request) - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- arp frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"07"; - wait until rising_edge(RX_MAC_CLK); --- hardware type - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- protocol type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- hardware size - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); --- protocol size - MAC_RXD_IN <= x"04"; - wait until rising_edge(RX_MAC_CLK); --- opcode (request) - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- sender mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- sender ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a9"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); --- target mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- target ip - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a9"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); --- cs - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"03"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"04"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - wait for 100 ns; - --- SECOND FRAME - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); --- data - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); --- cs - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"03"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"04"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - wait for 50 ns; - --- THIRD FRAME - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); --- data - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); --- cs - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"03"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"04"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - wait for 100 ns; - - - wait; - - FRAMES_LOOP : for i in 0 to 100 loop - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; - -- dest mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); - -- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"22"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"33"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"55"; - wait until rising_edge(RX_MAC_CLK); - -- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - -- data - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - -- cs - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"03"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"04"; - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - wait for 100 ns; - end loop FRAMES_LOOP; - - wait for 1000 ns; - -end process; - - -end architecture; diff --git a/gbe2_ecp3/tb_gbe_buf.vhd b/gbe2_ecp3/tb_gbe_buf.vhd deleted file mode 100755 index d953228..0000000 --- a/gbe2_ecp3/tb_gbe_buf.vhd +++ /dev/null @@ -1,946 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.math_real.all; -USE ieee.numeric_std.ALL; - -use work.trb_net_gbe_components.all; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS --- component trb_net16_gbe_buf is --- generic( --- DO_SIMULATION : integer range 0 to 1 := 1; --- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 --- ); --- port( --- CLK : in std_logic; --- TEST_CLK : in std_logic; -- only for simulation! --- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode --- RESET : in std_logic; --- GSR_N : in std_logic; --- -- Debug --- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); --- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); --- -- configuration interface --- IP_CFG_START_IN : in std_logic; --- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); --- IP_CFG_DONE_OUT : out std_logic; --- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); --- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); --- IP_CFG_MEM_CLK_OUT : out std_logic; --- MR_RESET_IN : in std_logic; --- MR_MODE_IN : in std_logic; --- MR_RESTART_IN : in std_logic; --- -- gk 29.03.10 --- SLV_ADDR_IN : in std_logic_vector(7 downto 0); --- SLV_READ_IN : in std_logic; --- SLV_WRITE_IN : in std_logic; --- SLV_BUSY_OUT : out std_logic; --- SLV_ACK_OUT : out std_logic; --- SLV_DATA_IN : in std_logic_vector(31 downto 0); --- SLV_DATA_OUT : out std_logic_vector(31 downto 0); --- -- gk 22.04.10 --- -- registers setup interface --- BUS_ADDR_IN : in std_logic_vector(7 downto 0); --- BUS_DATA_IN : in std_logic_vector(31 downto 0); --- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 --- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 --- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 --- BUS_ACK_OUT : out std_logic; -- gk 26.04.10 --- -- gk 23.04.10 --- LED_PACKET_SENT_OUT : out std_logic; --- LED_AN_DONE_N_OUT : out std_logic; --- -- CTS interface --- CTS_NUMBER_IN : in std_logic_vector (15 downto 0); --- CTS_CODE_IN : in std_logic_vector (7 downto 0); --- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); --- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); --- CTS_START_READOUT_IN : in std_logic; --- CTS_DATA_OUT : out std_logic_vector (31 downto 0); --- CTS_DATAREADY_OUT : out std_logic; --- CTS_READOUT_FINISHED_OUT : out std_logic; --- CTS_READ_IN : in std_logic; --- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); --- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); --- -- Data payload interface --- FEE_DATA_IN : in std_logic_vector (15 downto 0); --- FEE_DATAREADY_IN : in std_logic; --- FEE_READ_OUT : out std_logic; --- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --- FEE_BUSY_IN : in std_logic; --- --SFP Connection --- SFP_RXD_P_IN : in std_logic; --- SFP_RXD_N_IN : in std_logic; --- SFP_TXD_P_OUT : out std_logic; --- SFP_TXD_N_OUT : out std_logic; --- SFP_REFCLK_P_IN : in std_logic; --- SFP_REFCLK_N_IN : in std_logic; --- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) --- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) --- SFP_TXDIS_OUT : out std_logic; -- SFP disable --- --- -- interface between main_controller and hub logic --- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); --- GSC_CLK_IN : in std_logic; --- GSC_INIT_DATAREADY_OUT : out std_logic; --- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); --- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); --- GSC_INIT_READ_IN : in std_logic; --- GSC_REPLY_DATAREADY_IN : in std_logic; --- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); --- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); --- GSC_REPLY_READ_OUT : out std_logic; --- GSC_BUSY_IN : in std_logic; --- --- MAKE_RESET_OUT : out std_logic; --- --- -- for simulation of receiving part only --- MAC_RX_EOF_IN : in std_logic; --- MAC_RXD_IN : in std_logic_vector(7 downto 0); --- MAC_RX_EN_IN : in std_logic; --- --- --- -- debug ports --- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) ---); --- END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL TEST_CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL GSR_N : std_logic; - SIGNAL STAGE_STAT_REGS_OUT : std_logic_vector(31 downto 0); - SIGNAL STAGE_CTRL_REGS_IN : std_logic_vector(31 downto 0); - SIGNAL IP_CFG_START_IN : std_logic; - SIGNAL IP_CFG_BANK_SEL_IN : std_logic_vector(3 downto 0); - SIGNAL IP_CFG_MEM_DATA_IN : std_logic_vector(31 downto 0); - SIGNAL MR_RESET_IN : std_logic; - SIGNAL MR_MODE_IN : std_logic; - SIGNAL MR_RESTART_IN : std_logic; - SIGNAL IP_CFG_MEM_CLK_OUT : std_logic; - SIGNAL IP_CFG_DONE_OUT : std_logic; - SIGNAL IP_CFG_MEM_ADDR_OUT : std_logic_vector(7 downto 0); - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL SFP_RXD_P_IN : std_logic; - SIGNAL SFP_RXD_N_IN : std_logic; - SIGNAL SFP_TXD_P_OUT : std_logic; - SIGNAL SFP_TXD_N_OUT : std_logic; - SIGNAL SFP_REFCLK_P_IN : std_logic; - SIGNAL SFP_REFCLK_N_IN : std_logic; - SIGNAL SFP_PRSNT_N_IN : std_logic; - SIGNAL SFP_LOS_IN : std_logic; - SIGNAL SFP_TXDIS_OUT : std_logic; - SIGNAL ANALYZER_DEBUG_OUT : std_logic_vector(63 downto 0); - --gk 29.03.10 - signal SLV_ADDR_IN : std_logic_vector(7 downto 0); - signal SLV_READ_IN : std_logic; - signal SLV_WRITE_IN : std_logic; - signal SLV_BUSY_OUT : std_logic; - signal SLV_ACK_OUT : std_logic; - signal SLV_DATA_IN : std_logic_vector(31 downto 0); - signal SLV_DATA_OUT : std_logic_vector(31 downto 0); - -- for simulation of receiving part only - signal MAC_RX_EOF_IN : std_logic; - signal MAC_RXD_IN : std_logic_vector(7 downto 0); - signal MAC_RX_EN_IN : std_logic; - - signal reply_busy, reply_dataready : std_logic; - signal reply_data : std_logic_vector(15 downto 0); - - signal RX_MAC_CLK : std_logic; - - -BEGIN - -RX_MAC_CLK <= test_clk; - --- Please check and add your generic clause manually - uut: trb_net16_gbe_buf - GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 ) - PORT MAP( - CLK => CLK, - CLK_125_IN => '0', - TEST_CLK => TEST_CLK, - RESET => RESET, - GSR_N => GSR_N, - STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT, - STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN, - IP_CFG_START_IN => IP_CFG_START_IN, - IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN, - IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_RESTART_IN => MR_RESTART_IN, - IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT, - IP_CFG_DONE_OUT => IP_CFG_DONE_OUT, - IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT, - -- gk 29.03.10 - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - -- gk 22.04.10 - -- registers setup interface - BUS_ADDR_IN => x"00", - BUS_DATA_IN => x"0000_0000", - BUS_DATA_OUT => open, - BUS_WRITE_EN_IN => '0', - BUS_READ_EN_IN => '0', - BUS_ACK_OUT => open, - -- gk 23.04.10 - LED_PACKET_SENT_OUT => open, - LED_AN_DONE_N_OUT => open, - -------------------------- - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - SFP_RXD_P_IN => SFP_RXD_P_IN, - SFP_RXD_N_IN => SFP_RXD_N_IN, - SFP_TXD_P_OUT => SFP_TXD_P_OUT, - SFP_TXD_N_OUT => SFP_TXD_N_OUT, - SFP_REFCLK_P_IN => SFP_REFCLK_P_IN, - SFP_REFCLK_N_IN => SFP_REFCLK_N_IN, - SFP_PRSNT_N_IN => SFP_PRSNT_N_IN, - SFP_LOS_IN => SFP_LOS_IN, - SFP_TXDIS_OUT => SFP_TXDIS_OUT, - - MC_UNIQUE_ID_IN => (others => '0'), - GSC_CLK_IN => test_clk, - GSC_INIT_DATAREADY_OUT => open, - GSC_INIT_DATA_OUT => open, - GSC_INIT_PACKET_NUM_OUT => open, - GSC_INIT_READ_IN => '0', - GSC_REPLY_DATAREADY_IN => reply_dataready, - GSC_REPLY_DATA_IN => reply_data, --(others => '0'), - GSC_REPLY_PACKET_NUM_IN => (others => '0'), - GSC_REPLY_READ_OUT => open, - GSC_BUSY_IN => reply_busy, - - MAKE_RESET_OUT => open, - - - -- for simulation of receiving part only - MAC_RX_EOF_IN => MAC_RX_EOF_IN, - MAC_RXD_IN => MAC_RXD_IN, - MAC_RX_EN_IN => MAC_RX_EN_IN, - ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT - ); - - - --- 100 MHz system clock -CLOCK_GEN_PROC: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN_PROC; - --- 125 MHz MAC clock -CLOCK2_GEN_PROC: process -begin - test_clk <= '1'; wait for 4.0 ns; - test_clk <= '0'; wait for 4.0 ns; -end process CLOCK2_GEN_PROC; - - ---SCTRL_TESTBENCH_PROC : process ---begin --- ---for j in 0 to 5000 loop --- --- reply_dataready <= '0'; --- reply_busy <= '0'; --- reply_data <= (others => '0'); --- --- wait for 76 us; --- --- for i in 0 to 1000 loop --- --- wait until rising_edge(clk); --- reply_dataready <= '1'; --- reply_busy <= '1'; --- reply_data <= std_logic_vector(to_unsigned(i, 16)); --- --- end loop; --- wait until rising_edge(clk); --- reply_dataready <= '0'; --- reply_busy <= '0'; --- --- wait for 13 us; ---end loop; --- ---end process SCTRL_TESTBENCH_PROC; - - - - - - - --- Testbench -TESTBENCH_PROC: process --- test data from TRBnet -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; -variable test_data2 : unsigned(7 downto 0) := x"ff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; - --- 1400 bytes MTU => 350 as limit for fragmentation -variable max_event_size : real := 512.0; - -variable seed1 : positive; -- seed for random generator -variable seed2 : positive; -- seed for random generator -variable rand : real; -- random value (0.0 ... 1.0) -variable int_rand : integer; -- random value, scaled to your needs -variable cts_random_number : std_logic_vector(7 downto 0); -variable up_down_switch : integer := 0; -variable stim : std_logic_vector(15 downto 0); -variable random_size : integer := 1; --- RND test ---UNIFORM(seed1, seed2, rand); ---int_rand := INTEGER(TRUNC(rand*65536.0)); ---stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH)); - -begin - -- Setup signals - reset <= '0'; - gsr_n <= '1'; - - stage_ctrl_regs_in <= x"0000_0000"; - - --ip_cfg_start_in <= '0'; - --ip_cfg_bank_sel_in <= x"0"; - --ip_cfg_mem_data_in <= x"0000_0000"; - mr_reset_in <= '0'; - mr_mode_in <= '0'; - mr_restart_in <= '0'; - SLV_ADDR_IN <= x"00"; - SLV_READ_IN <= '0'; - SLV_WRITE_IN <= '0'; - SLV_DATA_IN <= x"0000_0000"; - - sfp_los_in <= '0'; -- signal from SFP is present - sfp_prsnt_n_in <= '0'; -- SFP itself is present - sfp_refclk_n_in <= '0'; - sfp_refclk_p_in <= '1'; - - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"1234_5678"; - fee_busy_in <= '0'; - - MAC_RX_EN_IN <= '0'; - MAC_RX_EOF_IN <= '0'; - MAC_RXD_IN <= (others => '0'); - - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - gsr_n <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - gsr_n <= '1'; - wait until rising_edge(clk); - --wait for 100 ns; - - -- Tests may start here --- wait until ft_bsm_init_tst = x"7"; - - --ip_cfg_start_in <= '1'; - - wait for 700 us; - - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 5000; - - wait until rising_edge(test_clk); - - -- FIRST FRAME UDP - DHCP Offer - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac --- MAC_RXD_IN <= x"02"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"be"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); --- MAC_RXD_IN <= x"00"; --- wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; -- udp - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- udp headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"43"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"2c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; --- dhcp data - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"fa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ce"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - - for i in 0 to 219 loop - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - end loop; - - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"35"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - wait for 1 us; - - - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <= '1'; --- dest mac - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"be"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- src mac - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"dd"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ee"; - wait until rising_edge(RX_MAC_CLK); --- frame type - MAC_RXD_IN <= x"08"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); --- ip headers - MAC_RXD_IN <= x"45"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"5a"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"49"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ff"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"11"; -- udp - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"cc"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; --- udp headers - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"43"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"44"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"2c"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"aa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"bb"; --- dhcp data - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"06"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"fa"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"ce"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"c0"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"a8"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"10"; - - for i in 0 to 219 loop - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - end loop; - - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"35"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"01"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"02"; - wait until rising_edge(RX_MAC_CLK); - MAC_RXD_IN <= x"00"; - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EOF_IN <= '1'; - - wait until rising_edge(RX_MAC_CLK); - MAC_RX_EN_IN <='0'; - MAC_RX_EOF_IN <= '0'; - - - - --- RECEIVE_LOOP: for J in 0 to 1 loop --- --- wait for 200 ns; --- --- -- IPU transmission starts --- wait until rising_edge(test_clk); --- --- test_data2 := x"ff"; --- MY_DATA_LOOP2: for k in 0 to 200 + (J * 10) loop --- test_data2 := test_data2 + 1; --- wait until rising_edge(test_clk); --- MAC_RXD_IN <= std_logic_vector(test_data2); --- MAC_RX_EN_IN <= '1'; --- end loop MY_DATA_LOOP2; --- --- MAC_RX_EN_IN <= '0'; --- MAC_RXD_IN <= "00000000"; --- MAC_RX_EOF_IN <= '1'; --- wait until rising_edge(test_clk); --- MAC_RX_EOF_IN <= '0'; --- --- --wait for 3 us; --- --- end loop RECEIVE_LOOP; - test_data_len := 20; -- + (1 - J) * 200; - --- MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop --- -- generate a real random byte for CTS --- UNIFORM(seed1, seed2, rand); --- int_rand := INTEGER(TRUNC(rand*256.0)); --- cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); --- --- -- IPU transmission starts --- wait until rising_edge(clk); --- cts_number_in <= std_logic_vector( trigger_counter ); --- cts_code_in <= cts_random_number; --- cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10 --- cts_readout_type_in <= x"1"; --- cts_start_readout_in <= '1'; --- wait until rising_edge(clk); --- wait for 400 ns; --- --- wait until rising_edge(clk); --- fee_busy_in <= '1'; --- wait for 300 ns; --- wait until rising_edge(clk); --- --- -- ONE DATA TRANSMISSION --- -- dice a length --- UNIFORM(seed1, seed2, rand); --- --test_data_len := INTEGER(TRUNC(rand * 800.0)) + 1; --- --- --test_data_len := 9685; ----- test_data_len := 2000; -- + (1 - J) * 200; --- --- --test_data_len := INTEGER(TRUNC(rand*7500.0)); --20; -- + (1 - J) * 200; --- test_data_len := 349; --- --- -- calculate the needed variables --- test_loop_len := 2*(test_data_len - 1) + 1; --- test_hdr_len := to_unsigned( test_data_len + 1, 16 ); --- test_evt_len := to_unsigned( test_data_len, 16 ); --- --- -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) --- fee_dataready_in <= '1'; --- fee_data_in <= x"1111"; --x"10" & cts_random_number; --- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word --- fee_dataready_in <= '0'; --- wait until rising_edge(clk); -- BLA --- wait until rising_edge(clk); -- BLA --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- fee_dataready_in <= '1'; --- fee_data_in <= x"2222"; --std_logic_vector( trigger_counter ); --- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word --- fee_dataready_in <= '0'; --- wait until rising_edge(clk); -- BLA --- wait until rising_edge(clk); -- BLA --- wait until rising_edge(clk); -- BLA --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- fee_dataready_in <= '1'; --- fee_data_in <= std_logic_vector( test_hdr_len ); --- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word --- fee_data_in <= x"3333"; --x"ff21"; --- wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word --- fee_dataready_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- fee_dataready_in <= '1'; --- fee_data_in <= std_logic_vector( test_evt_len ); --- wait until rising_edge(clk) and (fee_read_out = '1'); --- fee_data_in <= x"ff22"; --- wait until rising_edge(clk) and (fee_read_out = '1'); --- fee_dataready_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- --- test_data := x"ffff"; --- MY_DATA_LOOP: for J in 0 to test_loop_len loop --- test_data := test_data + 1; --- wait until rising_edge(clk) and (fee_read_out = '1'); --- fee_data_in <= std_logic_vector(test_data); ----- if( (test_data MOD 5) = 0 ) then ----- fee_dataready_in <= '0'; ----- wait until rising_edge(clk); ----- wait until rising_edge(clk); ----- wait until rising_edge(clk); ----- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ------- wait until rising_edge(clk); ----- fee_dataready_in <= '1'; ----- else ----- fee_dataready_in <= '1'; ----- end if; --- fee_dataready_in <= '1'; --- end loop MY_DATA_LOOP; --- -- there must be padding words to get multiple of four LWs --- --- wait until rising_edge(clk); --- fee_dataready_in <= '0'; --- fee_data_in <= x"0000"; --- --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- fee_busy_in <= '0'; --- --- --- trigger_loop := trigger_loop + 1; --- trigger_counter := trigger_counter + 1; --- --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- cts_read_in <= '1'; --- wait until rising_edge(clk); --- cts_read_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- cts_start_readout_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- --- test_data_len := test_data_len + 111; --- --- --wait for 8 us; --- --- end loop MY_TRIGGER_LOOP; - - - - - - - - - --- wait for 8 us; -------------------------------------------------------------------------------- --- end of loop -------------------------------------------------------------------------------- - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - -END; - diff --git a/gbe2_ecp3/tb_ip_configurator.vhd b/gbe2_ecp3/tb_ip_configurator.vhd deleted file mode 100755 index 6188d42..0000000 --- a/gbe2_ecp3/tb_ip_configurator.vhd +++ /dev/null @@ -1,145 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT ip_configurator - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - START_CONFIG_IN : IN std_logic; - BANK_SELECT_IN : IN std_logic_vector(3 downto 0); - MEM_DATA_IN : IN std_logic_vector(31 downto 0); - CONFIG_DONE_OUT : OUT std_logic; - MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0); - MEM_CLK_OUT : OUT std_logic; - DEST_MAC_OUT : OUT std_logic_vector(47 downto 0); - DEST_IP_OUT : OUT std_logic_vector(31 downto 0); - DEST_UDP_OUT : OUT std_logic_vector(15 downto 0); - SRC_MAC_OUT : OUT std_logic_vector(47 downto 0); - SRC_IP_OUT : OUT std_logic_vector(31 downto 0); - SRC_UDP_OUT : OUT std_logic_vector(15 downto 0); - MTU_OUT : OUT std_logic_vector(15 downto 0); - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL START_CONFIG_IN : std_logic; - SIGNAL BANK_SELECT_IN : std_logic_vector(3 downto 0); - SIGNAL CONFIG_DONE_OUT : std_logic; - SIGNAL MEM_ADDR_OUT : std_logic_vector(7 downto 0); - SIGNAL MEM_DATA_IN : std_logic_vector(31 downto 0); - SIGNAL MEM_CLK_OUT : std_logic; - SIGNAL DEST_MAC_OUT : std_logic_vector(47 downto 0); - SIGNAL DEST_IP_OUT : std_logic_vector(31 downto 0); - SIGNAL DEST_UDP_OUT : std_logic_vector(15 downto 0); - SIGNAL SRC_MAC_OUT : std_logic_vector(47 downto 0); - SIGNAL SRC_IP_OUT : std_logic_vector(31 downto 0); - SIGNAL SRC_UDP_OUT : std_logic_vector(15 downto 0); - SIGNAL MTU_OUT : std_logic_vector(15 downto 0); - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: ip_configurator PORT MAP( - CLK => CLK, - RESET => RESET, - START_CONFIG_IN => START_CONFIG_IN, - BANK_SELECT_IN => BANK_SELECT_IN, - CONFIG_DONE_OUT => CONFIG_DONE_OUT, - MEM_ADDR_OUT => MEM_ADDR_OUT, - MEM_DATA_IN => MEM_DATA_IN, - MEM_CLK_OUT => MEM_CLK_OUT, - DEST_MAC_OUT => DEST_MAC_OUT, - DEST_IP_OUT => DEST_IP_OUT, - DEST_UDP_OUT => DEST_UDP_OUT, - SRC_MAC_OUT => SRC_MAC_OUT, - SRC_IP_OUT => SRC_IP_OUT, - SRC_UDP_OUT => SRC_UDP_OUT, - MTU_OUT => MTU_OUT, - DEBUG_OUT => DEBUG_OUT - ); - - -CLK_GEN_PROC: process -begin - clk <= '0'; wait for 5.0 ns; - clk <= '1'; wait for 5.0 ns; -end process CLK_GEN_PROC; - -THE_TESTBENCH: process -begin - -- Setup signals - reset <= '0'; - start_config_in <= '0'; - bank_select_in <= x"0"; - mem_data_in <= x"0000_0000"; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait for 100 ns; - wait until rising_edge(clk); - - -- Tests may start now - wait until rising_edge(clk); - start_config_in <= '1'; - wait until mem_addr_out(3 downto 0) = x"1"; - wait until rising_edge(clk); - mem_data_in <= x"4902d745"; -- dest MAC low - wait until rising_edge(clk); - mem_data_in <= x"00006cf0"; -- dest MAC high - wait until rising_edge(clk); - mem_data_in <= x"c0a80002"; -- dest IP - wait until rising_edge(clk); - mem_data_in <= x"0000c350"; -- dest port - wait until rising_edge(clk); - mem_data_in <= x"eeeeeeee"; -- src MAC low - wait until rising_edge(clk); - mem_data_in <= x"0000eeee"; -- src MAC high - wait until rising_edge(clk); - mem_data_in <= x"c0a80005"; -- src IP - wait until rising_edge(clk); - mem_data_in <= x"0000c350"; -- src port - wait until rising_edge(clk); - mem_data_in <= x"00000578"; -- MTU - wait until rising_edge(clk); - mem_data_in <= x"99999999"; - wait until rising_edge(clk); - mem_data_in <= x"aaaaaaaa"; - wait until rising_edge(clk); - mem_data_in <= x"bbbbbbbb"; - wait until rising_edge(clk); - mem_data_in <= x"cccccccc"; - wait until rising_edge(clk); - mem_data_in <= x"dddddddd"; - wait until rising_edge(clk); - mem_data_in <= x"eeeeeeee"; - wait until rising_edge(clk); - mem_data_in <= x"ffffffff"; - wait until rising_edge(clk); - mem_data_in <= x"00000000"; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - start_config_in <= '0'; - - -- Stay a while... stay forever!!! Muahahaha!!!!! - wait; -end process THE_TESTBENCH; - - -END; diff --git a/gbe2_ecp3/tb_ipu2gbe.vhd b/gbe2_ecp3/tb_ipu2gbe.vhd deleted file mode 100755 index 065e674..0000000 --- a/gbe2_ecp3/tb_ipu2gbe.vhd +++ /dev/null @@ -1,428 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.math_real.all; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_ipu2gbe - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - START_CONFIG_OUT : OUT std_logic; - BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0); - CONFIG_DONE_IN : IN std_logic; - DATA_GBE_ENABLE_IN : IN std_logic; - DATA_IPU_ENABLE_IN : IN std_logic; - MULTI_EVT_ENABLE_IN : IN std_logic; - CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); - CTS_CODE_IN : IN std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : IN std_logic; - CTS_READ_IN : IN std_logic; - FEE_DATA_IN : IN std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : IN std_logic; - FEE_BUSY_IN : IN std_logic; - FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); - PC_READY_IN : IN std_logic; - CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : OUT std_logic; - CTS_READOUT_FINISHED_OUT : OUT std_logic; - CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); - FEE_READ_OUT : OUT std_logic; - PC_WR_EN_OUT : OUT std_logic; - PC_DATA_OUT : OUT std_logic_vector(7 downto 0); - PC_SOS_OUT : OUT std_logic; - PC_EOD_OUT : OUT std_logic; - PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); - PC_PADDING_OUT : OUT std_logic; - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : OUT std_logic; - DBG_SF_WR_EN_OUT : OUT std_logic; - DBG_SF_EMPTY_OUT : OUT std_logic; - DBG_SF_AEMPTY_OUT : OUT std_logic; - DBG_SF_FULL_OUT : OUT std_logic; - DBG_SF_AFULL_OUT : OUT std_logic; - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL START_CONFIG_OUT : std_logic; - SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0); - SIGNAL CONFIG_DONE_IN : std_logic; - SIGNAL DATA_GBE_ENABLE_IN : std_logic; - SIGNAL DATA_IPU_ENABLE_IN : std_logic; - SIGNAL MULTI_EVT_ENABLE_IN : std_logic; - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL PC_WR_EN_OUT : std_logic; - SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL PC_READY_IN : std_logic; - SIGNAL PC_SOS_OUT : std_logic; - SIGNAL PC_EOD_OUT : std_logic; - SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_PADDING_OUT : std_logic; - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); - SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); - SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RD_EN_OUT : std_logic; - SIGNAL DBG_SF_WR_EN_OUT : std_logic; - SIGNAL DBG_SF_EMPTY_OUT : std_logic; - SIGNAL DBG_SF_AEMPTY_OUT : std_logic; - SIGNAL DBG_SF_FULL_OUT : std_logic; - SIGNAL DBG_SF_AFULL_OUT : std_logic; - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_ipu2gbe PORT MAP( - CLK => CLK, - RESET => RESET, - START_CONFIG_OUT => START_CONFIG_OUT, - BANK_SELECT_OUT => BANK_SELECT_OUT, - CONFIG_DONE_IN => CONFIG_DONE_IN, - DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN, - DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN, - MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN, - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => CTS_READ_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - PC_WR_EN_OUT => PC_WR_EN_OUT, - PC_DATA_OUT => PC_DATA_OUT, - PC_READY_IN => PC_READY_IN, - PC_SOS_OUT => PC_SOS_OUT, - PC_EOD_OUT => PC_EOD_OUT, - PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, - PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, - PC_PADDING_OUT => PC_PADDING_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, - DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, - DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, - DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, - DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, - DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, - DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, - DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, - DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT, - DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, - DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, - DEBUG_OUT => DEBUG_OUT - ); - -CLOCK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN; - -PC_READY_PROC: process -begin - pc_ready_in <= '0'; - wait for 500 ns; - pc_ready_in <= '1'; - wait for 500 ns; - pc_ready_in <= '0'; - wait for 99 us; -end process PC_READY_PROC; - --- Testbench -TESTBENCH_PROC: process --- test data from TRBnet -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; - --- 1400 bytes MTU => 350 as limit for fragmentation ---variable max_event_size : real := 512.0; -variable max_event_size : real := 17.0; - -variable seed1 : positive; -- seed for random generator -variable seed2 : positive; -- seed for random generator -variable rand : real; -- random value (0.0 ... 1.0) -variable int_rand : integer; -- random value, scaled to your needs -variable cts_random_number : std_logic_vector(7 downto 0); - -variable stim : std_logic_vector(15 downto 0); - -begin - -- Setup signals - reset <= '0'; - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"0000_0000"; - fee_busy_in <= '0'; --- pc_ready_in <= '0'; - - config_done_in <= '1'; - data_gbe_enable_in <= '1'; - data_ipu_enable_in <= '0'; - multi_evt_enable_in <= '0'; - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - ---------------------------- - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 2; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - -- generate a real random byte for CTS - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand*256.0)); - cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); - - -- IPU transmission starts - wait until rising_edge(clk); - cts_number_in <= std_logic_vector( trigger_counter ); - cts_code_in <= cts_random_number; - cts_information_in <= x"de"; - cts_readout_type_in <= x"1"; - cts_start_readout_in <= '1'; - wait until rising_edge(clk); - wait for 400 ns; - - wait until rising_edge(clk); - fee_busy_in <= '1'; - wait for 300 ns; - wait until rising_edge(clk); - - -- ONE DATA TRANSMISSION - -- dice a length - UNIFORM(seed1, seed2, rand); - test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; - --- test_data_len := 9685; - - -- calculate the needed variables - test_loop_len := 2*(test_data_len - 1) + 1; - test_hdr_len := to_unsigned( test_data_len + 1, 16 ); - test_evt_len := to_unsigned( test_data_len, 16 ); - - -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) - fee_dataready_in <= '1'; - fee_data_in <= x"10" & cts_random_number; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( trigger_counter ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_hdr_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word - fee_data_in <= x"ff21"; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_evt_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_data_in <= x"ff22"; - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - wait until rising_edge(clk) and (fee_read_out = '1'); -- - fee_data_in <= std_logic_vector(test_data); - if( (test_data MOD 5) = 0 ) then - fee_dataready_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - else - fee_dataready_in <= '1'; - end if; - end loop MY_DATA_LOOP; - -- there must be padding words to get multiple of four LWs - - wait until rising_edge(clk); - fee_dataready_in <= '0'; - fee_data_in <= x"0000"; - - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_busy_in <= '0'; - - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_read_in <= '1'; - wait until rising_edge(clk); - cts_read_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_start_readout_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - --wait for 8 us; - - end loop MY_TRIGGER_LOOP; - - - ---------------------------- ---------------------------- - wait for 300 ns; - - wait; - - -- Start packet_constructor - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '1'; - wait until rising_edge(clk); - - wait until rising_edge(clk); - wait until pc_eod_out = '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '0'; - - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - - -END; diff --git a/gbe2_ecp3/tb_ipu2gbe_NEW.vhd b/gbe2_ecp3/tb_ipu2gbe_NEW.vhd deleted file mode 100755 index bd8b288..0000000 --- a/gbe2_ecp3/tb_ipu2gbe_NEW.vhd +++ /dev/null @@ -1,428 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.math_real.all; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_ipu2gbe_new - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - START_CONFIG_OUT : OUT std_logic; - BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0); - CONFIG_DONE_IN : IN std_logic; - DATA_GBE_ENABLE_IN : IN std_logic; - DATA_IPU_ENABLE_IN : IN std_logic; - MULTI_EVT_ENABLE_IN : IN std_logic; - CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); - CTS_CODE_IN : IN std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : IN std_logic; - CTS_READ_IN : IN std_logic; - FEE_DATA_IN : IN std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : IN std_logic; - FEE_BUSY_IN : IN std_logic; - FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); - PC_READY_IN : IN std_logic; - CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : OUT std_logic; - CTS_READOUT_FINISHED_OUT : OUT std_logic; - CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); - FEE_READ_OUT : OUT std_logic; - PC_WR_EN_OUT : OUT std_logic; - PC_DATA_OUT : OUT std_logic_vector(7 downto 0); - PC_SOS_OUT : OUT std_logic; - PC_EOD_OUT : OUT std_logic; - PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); - PC_PADDING_OUT : OUT std_logic; - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : OUT std_logic; - DBG_SF_WR_EN_OUT : OUT std_logic; - DBG_SF_EMPTY_OUT : OUT std_logic; - DBG_SF_AEMPTY_OUT : OUT std_logic; - DBG_SF_FULL_OUT : OUT std_logic; - DBG_SF_AFULL_OUT : OUT std_logic; - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL START_CONFIG_OUT : std_logic; - SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0); - SIGNAL CONFIG_DONE_IN : std_logic; - SIGNAL DATA_GBE_ENABLE_IN : std_logic; - SIGNAL DATA_IPU_ENABLE_IN : std_logic; - SIGNAL MULTI_EVT_ENABLE_IN : std_logic; - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL PC_WR_EN_OUT : std_logic; - SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL PC_READY_IN : std_logic; - SIGNAL PC_SOS_OUT : std_logic; - SIGNAL PC_EOD_OUT : std_logic; - SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_PADDING_OUT : std_logic; - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); - SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); - SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RD_EN_OUT : std_logic; - SIGNAL DBG_SF_WR_EN_OUT : std_logic; - SIGNAL DBG_SF_EMPTY_OUT : std_logic; - SIGNAL DBG_SF_AEMPTY_OUT : std_logic; - SIGNAL DBG_SF_FULL_OUT : std_logic; - SIGNAL DBG_SF_AFULL_OUT : std_logic; - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_ipu2gbe_new PORT MAP( - CLK => CLK, - RESET => RESET, - START_CONFIG_OUT => START_CONFIG_OUT, - BANK_SELECT_OUT => BANK_SELECT_OUT, - CONFIG_DONE_IN => CONFIG_DONE_IN, - DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN, - DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN, - MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN, - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => CTS_READ_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - PC_WR_EN_OUT => PC_WR_EN_OUT, - PC_DATA_OUT => PC_DATA_OUT, - PC_READY_IN => PC_READY_IN, - PC_SOS_OUT => PC_SOS_OUT, - PC_EOD_OUT => PC_EOD_OUT, - PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, - PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, - PC_PADDING_OUT => PC_PADDING_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, - DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, - DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, - DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, - DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, - DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, - DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, - DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, - DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT, - DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, - DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, - DEBUG_OUT => DEBUG_OUT - ); - -CLOCK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN; - -PC_READY_PROC: process -begin - pc_ready_in <= '0'; - wait for 500 ns; - pc_ready_in <= '1'; - wait for 500 ns; - pc_ready_in <= '0'; - wait for 99 us; -end process PC_READY_PROC; - --- Testbench -TESTBENCH_PROC: process --- test data from TRBnet -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; - --- 1400 bytes MTU => 350 as limit for fragmentation ---variable max_event_size : real := 512.0; -variable max_event_size : real := 17.0; - -variable seed1 : positive; -- seed for random generator -variable seed2 : positive; -- seed for random generator -variable rand : real; -- random value (0.0 ... 1.0) -variable int_rand : integer; -- random value, scaled to your needs -variable cts_random_number : std_logic_vector(7 downto 0); - -variable stim : std_logic_vector(15 downto 0); - -begin - -- Setup signals - reset <= '0'; - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"0000_0000"; - fee_busy_in <= '0'; --- pc_ready_in <= '0'; - - config_done_in <= '1'; - data_gbe_enable_in <= '1'; - data_ipu_enable_in <= '0'; - multi_evt_enable_in <= '0'; - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - ---------------------------- - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 2; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - -- generate a real random byte for CTS - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand*256.0)); - cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); - - -- IPU transmission starts - wait until rising_edge(clk); - cts_number_in <= std_logic_vector( trigger_counter ); - cts_code_in <= cts_random_number; - cts_information_in <= x"de"; - cts_readout_type_in <= x"1"; - cts_start_readout_in <= '1'; - wait until rising_edge(clk); - wait for 400 ns; - - wait until rising_edge(clk); - fee_busy_in <= '1'; - wait for 300 ns; - wait until rising_edge(clk); - - -- ONE DATA TRANSMISSION - -- dice a length - UNIFORM(seed1, seed2, rand); - test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; - --- test_data_len := 9685; - - -- calculate the needed variables - test_loop_len := 2*(test_data_len - 1) + 1; - test_hdr_len := to_unsigned( test_data_len + 1, 16 ); - test_evt_len := to_unsigned( test_data_len, 16 ); - - -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) - fee_dataready_in <= '1'; - fee_data_in <= x"10" & cts_random_number; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word --- fee_dataready_in <= '0'; --- wait until rising_edge(clk); -- BLA --- wait until rising_edge(clk); -- BLA --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( trigger_counter ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_hdr_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word - fee_data_in <= x"ff21"; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_evt_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_data_in <= x"ff22"; - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - wait until rising_edge(clk) and (fee_read_out = '1'); -- - fee_data_in <= std_logic_vector(test_data); - if( (test_data MOD 5) = 0 ) then - fee_dataready_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - else - fee_dataready_in <= '1'; - end if; - end loop MY_DATA_LOOP; - -- there must be padding words to get multiple of four LWs - - wait until rising_edge(clk); - fee_dataready_in <= '0'; - fee_data_in <= x"0000"; - - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_busy_in <= '0'; - - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_read_in <= '1'; - wait until rising_edge(clk); - cts_read_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_start_readout_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - --wait for 8 us; - - end loop MY_TRIGGER_LOOP; - - - ---------------------------- ---------------------------- - wait for 300 ns; - - wait; - - -- Start packet_constructor - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '1'; - wait until rising_edge(clk); - - wait until rising_edge(clk); - wait until pc_eod_out = '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '0'; - - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - - -END; diff --git a/gbe2_ecp3/tb_ipu2gbe_OLD.vhd b/gbe2_ecp3/tb_ipu2gbe_OLD.vhd deleted file mode 100755 index 088bfb2..0000000 --- a/gbe2_ecp3/tb_ipu2gbe_OLD.vhd +++ /dev/null @@ -1,428 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.math_real.all; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_ipu2gbe - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - START_CONFIG_OUT : OUT std_logic; - BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0); - CONFIG_DONE_IN : IN std_logic; - DATA_GBE_ENABLE_IN : IN std_logic; - DATA_IPU_ENABLE_IN : IN std_logic; - MULTI_EVT_ENABLE_IN : IN std_logic; - CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); - CTS_CODE_IN : IN std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : IN std_logic; - CTS_READ_IN : IN std_logic; - FEE_DATA_IN : IN std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : IN std_logic; - FEE_BUSY_IN : IN std_logic; - FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); - PC_READY_IN : IN std_logic; - CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : OUT std_logic; - CTS_READOUT_FINISHED_OUT : OUT std_logic; - CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); - FEE_READ_OUT : OUT std_logic; - PC_WR_EN_OUT : OUT std_logic; - PC_DATA_OUT : OUT std_logic_vector(7 downto 0); - PC_SOS_OUT : OUT std_logic; - PC_EOD_OUT : OUT std_logic; - PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); - PC_PADDING_OUT : OUT std_logic; - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : OUT std_logic; - DBG_SF_WR_EN_OUT : OUT std_logic; - DBG_SF_EMPTY_OUT : OUT std_logic; - DBG_SF_AEMPTY_OUT : OUT std_logic; - DBG_SF_FULL_OUT : OUT std_logic; - DBG_SF_AFULL_OUT : OUT std_logic; - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL START_CONFIG_OUT : std_logic; - SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0); - SIGNAL CONFIG_DONE_IN : std_logic; - SIGNAL DATA_GBE_ENABLE_IN : std_logic; - SIGNAL DATA_IPU_ENABLE_IN : std_logic; - SIGNAL MULTI_EVT_ENABLE_IN : std_logic; - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL PC_WR_EN_OUT : std_logic; - SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL PC_READY_IN : std_logic; - SIGNAL PC_SOS_OUT : std_logic; - SIGNAL PC_EOD_OUT : std_logic; - SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_PADDING_OUT : std_logic; - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); - SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); - SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RD_EN_OUT : std_logic; - SIGNAL DBG_SF_WR_EN_OUT : std_logic; - SIGNAL DBG_SF_EMPTY_OUT : std_logic; - SIGNAL DBG_SF_AEMPTY_OUT : std_logic; - SIGNAL DBG_SF_FULL_OUT : std_logic; - SIGNAL DBG_SF_AFULL_OUT : std_logic; - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_ipu2gbe PORT MAP( - CLK => CLK, - RESET => RESET, - START_CONFIG_OUT => START_CONFIG_OUT, - BANK_SELECT_OUT => BANK_SELECT_OUT, - CONFIG_DONE_IN => CONFIG_DONE_IN, - DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN, - DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN, - MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN, - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => CTS_READ_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - PC_WR_EN_OUT => PC_WR_EN_OUT, - PC_DATA_OUT => PC_DATA_OUT, - PC_READY_IN => PC_READY_IN, - PC_SOS_OUT => PC_SOS_OUT, - PC_EOD_OUT => PC_EOD_OUT, - PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, - PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, - PC_PADDING_OUT => PC_PADDING_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, - DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, - DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, - DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, - DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, - DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, - DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, - DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, - DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT, - DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, - DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, - DEBUG_OUT => DEBUG_OUT - ); - -CLOCK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN; - -PC_READY_PROC: process -begin - pc_ready_in <= '0'; - wait for 500 ns; - pc_ready_in <= '1'; - wait for 500 ns; - pc_ready_in <= '0'; - wait for 99 us; -end process PC_READY_PROC; - --- Testbench -TESTBENCH_PROC: process --- test data from TRBnet -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; - --- 1400 bytes MTU => 350 as limit for fragmentation -variable max_event_size : real := 512.0; ---variable max_event_size : real := 1024.0; - -variable seed1 : positive; -- seed for random generator -variable seed2 : positive; -- seed for random generator -variable rand : real; -- random value (0.0 ... 1.0) -variable int_rand : integer; -- random value, scaled to your needs -variable cts_random_number : std_logic_vector(7 downto 0); - -variable stim : std_logic_vector(15 downto 0); - -begin - -- Setup signals - reset <= '0'; - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"0000_0000"; - fee_busy_in <= '0'; --- pc_ready_in <= '0'; - - config_done_in <= '1'; - data_gbe_enable_in <= '1'; - data_ipu_enable_in <= '0'; - multi_evt_enable_in <= '0'; - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - ---------------------------- - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 40; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - -- generate a real random byte for CTS - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand*256.0)); - cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); - - -- IPU transmission starts - wait until rising_edge(clk); - cts_number_in <= std_logic_vector( trigger_counter ); - cts_code_in <= cts_random_number; - cts_information_in <= x"de"; - cts_readout_type_in <= x"1"; - cts_start_readout_in <= '1'; - wait until rising_edge(clk); - wait for 400 ns; - - wait until rising_edge(clk); - fee_busy_in <= '1'; - wait for 300 ns; - wait until rising_edge(clk); - - -- ONE DATA TRANSMISSION - -- dice a length - UNIFORM(seed1, seed2, rand); - test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; - --- test_data_len := 9685; - - -- calculate the needed variables - test_loop_len := 2*(test_data_len - 1) + 1; - test_hdr_len := to_unsigned( test_data_len + 1, 16 ); - test_evt_len := to_unsigned( test_data_len, 16 ); - - -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) - fee_dataready_in <= '1'; - fee_data_in <= x"10" & cts_random_number; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( trigger_counter ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_hdr_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word - fee_data_in <= x"ff21"; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_evt_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_data_in <= x"ff22"; - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - wait until rising_edge(clk) and (fee_read_out = '1'); -- - fee_data_in <= std_logic_vector(test_data); - if( (test_data MOD 5) = 0 ) then - fee_dataready_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - else - fee_dataready_in <= '1'; - end if; - end loop MY_DATA_LOOP; - -- there must be padding words to get multiple of four LWs - - wait until rising_edge(clk); - fee_dataready_in <= '0'; - fee_data_in <= x"0000"; - - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_busy_in <= '0'; - - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_read_in <= '1'; - wait until rising_edge(clk); - cts_read_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_start_readout_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - --wait for 8 us; - - end loop MY_TRIGGER_LOOP; - - - ---------------------------- ---------------------------- - wait for 300 ns; - - wait; - - -- Start packet_constructor - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '1'; - wait until rising_edge(clk); - - wait until rising_edge(clk); - wait until pc_eod_out = '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '0'; - - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - - -END; diff --git a/gbe2_ecp3/tb_lsm.vhd b/gbe2_ecp3/tb_lsm.vhd deleted file mode 100755 index 6e86029..0000000 --- a/gbe2_ecp3/tb_lsm.vhd +++ /dev/null @@ -1,113 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_lsm_sfp_gbe - PORT( - SYSCLK : IN std_logic; - RESET : IN std_logic; - CLEAR : IN std_logic; - SFP_MISSING_IN : IN std_logic; - SFP_LOS_IN : IN std_logic; - SD_LINK_OK_IN : IN std_logic; - SD_LOS_IN : IN std_logic; - SD_TXCLK_BAD_IN : IN std_logic; - SD_RXCLK_BAD_IN : IN std_logic; - FULL_RESET_OUT : OUT std_logic; - LANE_RESET_OUT : OUT std_logic; - USER_RESET_OUT : OUT std_logic; - TIMING_CTR_OUT : OUT std_logic_vector(18 downto 0); - BSM_OUT : OUT std_logic_vector(3 downto 0); - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL SYSCLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL CLEAR : std_logic; - SIGNAL SFP_MISSING_IN : std_logic; - SIGNAL SFP_LOS_IN : std_logic; - SIGNAL SD_LINK_OK_IN : std_logic; - SIGNAL SD_LOS_IN : std_logic; - SIGNAL SD_TXCLK_BAD_IN : std_logic; - SIGNAL SD_RXCLK_BAD_IN : std_logic; - SIGNAL FULL_RESET_OUT : std_logic; - SIGNAL LANE_RESET_OUT : std_logic; - SIGNAL USER_RESET_OUT : std_logic; - SIGNAL TIMING_CTR_OUT : std_logic_vector(18 downto 0); - SIGNAL BSM_OUT : std_logic_vector(3 downto 0); - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_lsm_sfp_gbe PORT MAP( - SYSCLK => SYSCLK, - RESET => RESET, - CLEAR => CLEAR, - SFP_MISSING_IN => SFP_MISSING_IN, - SFP_LOS_IN => SFP_LOS_IN, - SD_LINK_OK_IN => SD_LINK_OK_IN, - SD_LOS_IN => SD_LOS_IN, - SD_TXCLK_BAD_IN => SD_TXCLK_BAD_IN, - SD_RXCLK_BAD_IN => SD_RXCLK_BAD_IN, - FULL_RESET_OUT => FULL_RESET_OUT, - LANE_RESET_OUT => LANE_RESET_OUT, - USER_RESET_OUT => USER_RESET_OUT, - TIMING_CTR_OUT => TIMING_CTR_OUT, - BSM_OUT => BSM_OUT, - DEBUG_OUT => DEBUG_OUT - ); - - -CLOCK_GEN: process -begin - sysclk <= '1'; wait for 4.0 ns; - sysclk <= '0'; wait for 4.0 ns; -end process CLOCK_GEN; - -THE_TESTBENCH: process -begin - -- Setup signals - reset <= '0'; - clear <= '0'; - sfp_missing_in <= '0'; - sfp_los_in <= '0'; - sd_link_ok_in <= '0'; - sd_los_in <= '0'; - sd_txclk_bad_in <= '1'; - sd_rxclk_bad_in <= '1'; - wait for 100 ns; - - -- Reset - clear <= '1'; - wait for 100 ns; - clear <= '0'; - wait for 10 ns; - - -- Tests may start now - wait until falling_edge(full_reset_out); - wait for 123 ns; - sd_txclk_bad_in <= '0'; - wait for 433 ns; - sd_rxclk_bad_in <= '0'; - - wait for 1.1 us; - sd_rxclk_bad_in <= '1'; - wait for 33 ns; - sd_rxclk_bad_in <= '0'; - - - wait until rising_edge(sysclk); - - -- Stay a while.... stay forever!!! Muahahaha!!!! - wait; - -end process THE_TESTBENCH; - -END; \ No newline at end of file diff --git a/gbe2_ecp3/tb_pc.vhd b/gbe2_ecp3/tb_pc.vhd deleted file mode 100755 index ac85375..0000000 --- a/gbe2_ecp3/tb_pc.vhd +++ /dev/null @@ -1,310 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_gbe_packet_constr - PORT( - RESET : IN std_logic; - CLK : IN std_logic; - PC_WR_EN_IN : IN std_logic; - PC_DATA_IN : IN std_logic_vector(7 downto 0); - PC_START_OF_SUB_IN : IN std_logic; - PC_END_OF_DATA_IN : IN std_logic; - PC_SUB_SIZE_IN : IN std_logic_vector(31 downto 0); - PC_DECODING_IN : IN std_logic_vector(31 downto 0); - PC_EVENT_ID_IN : IN std_logic_vector(31 downto 0); - PC_TRIG_NR_IN : IN std_logic_vector(31 downto 0); - PC_QUEUE_DEC_IN : IN std_logic_vector(31 downto 0); - PC_MAX_FRAME_SIZE_IN : IN std_logic_vector(15 downto 0); - FC_H_READY_IN : IN std_logic; - FC_READY_IN : IN std_logic; - PC_READY_OUT : OUT std_logic; - FC_WR_EN_OUT : OUT std_logic; - FC_DATA_OUT : OUT std_logic_vector(7 downto 0); - FC_IP_SIZE_OUT : OUT std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : OUT std_logic_vector(15 downto 0); - FC_IDENT_OUT : OUT std_logic_vector(15 downto 0); - FC_FLAGS_OFFSET_OUT : OUT std_logic_vector(15 downto 0); - FC_SOD_OUT : OUT std_logic; - FC_EOD_OUT : OUT std_logic; - BSM_CONSTR_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - DBG_SHF_EMPTY : OUT std_logic; - DBG_SHF_FULL : OUT std_logic; - DBG_SHF_WR_EN : OUT std_logic; - DBG_SHF_RD_EN : OUT std_logic; - DBG_DF_EMPTY : OUT std_logic; - DBG_DF_FULL : OUT std_logic; - DBG_DF_WR_EN : OUT std_logic; - DBG_DF_RD_EN : OUT std_logic; - DBG_ALL_CTR : OUT std_logic_vector(4 downto 0); - DBG_SUB_CTR : OUT std_logic_vector(4 downto 0); - DBG_MY_CTR : OUT std_logic_vector(1 downto 0); - DBG_BYTES_LOADED : OUT std_logic_vector(15 downto 0); - DBG_SIZE_LEFT : OUT std_logic_vector(31 downto 0); - DBG_SUB_SIZE_TO_SAVE : OUT std_logic_vector(31 downto 0); - DBG_SUB_SIZE_LOADED : OUT std_logic_vector(31 downto 0); - DBG_SUB_BYTES_LOADED : OUT std_logic_vector(31 downto 0); - DBG_QUEUE_SIZE : OUT std_logic_vector(31 downto 0); - DBG_ACT_QUEUE_SIZE : OUT std_logic_vector(31 downto 0); - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL RESET : std_logic; - SIGNAL CLK : std_logic; - SIGNAL PC_WR_EN_IN : std_logic; - SIGNAL PC_DATA_IN : std_logic_vector(7 downto 0); - SIGNAL PC_READY_OUT : std_logic; - SIGNAL PC_START_OF_SUB_IN : std_logic; - SIGNAL PC_END_OF_DATA_IN : std_logic; - SIGNAL PC_SUB_SIZE_IN : std_logic_vector(31 downto 0); - SIGNAL PC_DECODING_IN : std_logic_vector(31 downto 0); - SIGNAL PC_EVENT_ID_IN : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_IN : std_logic_vector(31 downto 0); - SIGNAL PC_QUEUE_DEC_IN : std_logic_vector(31 downto 0); - SIGNAL PC_MAX_FRAME_SIZE_IN : std_logic_vector(15 downto 0); - SIGNAL FC_WR_EN_OUT : std_logic; - SIGNAL FC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL FC_H_READY_IN : std_logic; - SIGNAL FC_READY_IN : std_logic; - SIGNAL FC_IP_SIZE_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_UDP_SIZE_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_IDENT_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_FLAGS_OFFSET_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_SOD_OUT : std_logic; - SIGNAL FC_EOD_OUT : std_logic; - SIGNAL BSM_CONSTR_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_SHF_EMPTY : std_logic; - SIGNAL DBG_SHF_FULL : std_logic; - SIGNAL DBG_SHF_WR_EN : std_logic; - SIGNAL DBG_SHF_RD_EN : std_logic; - SIGNAL DBG_DF_EMPTY : std_logic; - SIGNAL DBG_DF_FULL : std_logic; - SIGNAL DBG_DF_WR_EN : std_logic; - SIGNAL DBG_DF_RD_EN : std_logic; - SIGNAL DBG_ALL_CTR : std_logic_vector(4 downto 0); - SIGNAL DBG_SUB_CTR : std_logic_vector(4 downto 0); - SIGNAL DBG_MY_CTR : std_logic_vector(1 downto 0); - SIGNAL DBG_BYTES_LOADED : std_logic_vector(15 downto 0); - SIGNAL DBG_SIZE_LEFT : std_logic_vector(31 downto 0); - SIGNAL DBG_SUB_SIZE_TO_SAVE : std_logic_vector(31 downto 0); - SIGNAL DBG_SUB_SIZE_LOADED : std_logic_vector(31 downto 0); - SIGNAL DBG_SUB_BYTES_LOADED : std_logic_vector(31 downto 0); - SIGNAL DBG_QUEUE_SIZE : std_logic_vector(31 downto 0); - SIGNAL DBG_ACT_QUEUE_SIZE : std_logic_vector(31 downto 0); - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_gbe_packet_constr PORT MAP( - RESET => RESET, - CLK => CLK, - PC_WR_EN_IN => PC_WR_EN_IN, - PC_DATA_IN => PC_DATA_IN, - PC_READY_OUT => PC_READY_OUT, - PC_START_OF_SUB_IN => PC_START_OF_SUB_IN, - PC_END_OF_DATA_IN => PC_END_OF_DATA_IN, - PC_SUB_SIZE_IN => PC_SUB_SIZE_IN, - PC_DECODING_IN => PC_DECODING_IN, - PC_EVENT_ID_IN => PC_EVENT_ID_IN, - PC_TRIG_NR_IN => PC_TRIG_NR_IN, - PC_QUEUE_DEC_IN => PC_QUEUE_DEC_IN, - PC_MAX_FRAME_SIZE_IN => PC_MAX_FRAME_SIZE_IN, - FC_WR_EN_OUT => FC_WR_EN_OUT, - FC_DATA_OUT => FC_DATA_OUT, - FC_H_READY_IN => FC_H_READY_IN, - FC_READY_IN => FC_READY_IN, - FC_IP_SIZE_OUT => FC_IP_SIZE_OUT, - FC_UDP_SIZE_OUT => FC_UDP_SIZE_OUT, - FC_IDENT_OUT => FC_IDENT_OUT, - FC_FLAGS_OFFSET_OUT => FC_FLAGS_OFFSET_OUT, - FC_SOD_OUT => FC_SOD_OUT, - FC_EOD_OUT => FC_EOD_OUT, - BSM_CONSTR_OUT => BSM_CONSTR_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - DBG_SHF_EMPTY => DBG_SHF_EMPTY, - DBG_SHF_FULL => DBG_SHF_FULL, - DBG_SHF_WR_EN => DBG_SHF_WR_EN, - DBG_SHF_RD_EN => DBG_SHF_RD_EN, - DBG_DF_EMPTY => DBG_DF_EMPTY, - DBG_DF_FULL => DBG_DF_FULL, - DBG_DF_WR_EN => DBG_DF_WR_EN, - DBG_DF_RD_EN => DBG_DF_RD_EN, - DBG_ALL_CTR => DBG_ALL_CTR, - DBG_SUB_CTR => DBG_SUB_CTR, - DBG_MY_CTR => DBG_MY_CTR, - DBG_BYTES_LOADED => DBG_BYTES_LOADED, - DBG_SIZE_LEFT => DBG_SIZE_LEFT, - DBG_SUB_SIZE_TO_SAVE => DBG_SUB_SIZE_TO_SAVE, - DBG_SUB_SIZE_LOADED => DBG_SUB_SIZE_LOADED, - DBG_SUB_BYTES_LOADED => DBG_SUB_BYTES_LOADED, - DBG_QUEUE_SIZE => DBG_QUEUE_SIZE, - DBG_ACT_QUEUE_SIZE => DBG_ACT_QUEUE_SIZE, - DEBUG_OUT => DEBUG_OUT - ); - -CLK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLK_GEN; - -THE_TESTBENCH: process -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len_vec : std_logic_vector(15 downto 0); -variable test_sub_len : unsigned(15 downto 0) := x"0000"; -variable test_sub_len_vec : std_logic_vector(15 downto 0); -variable test_data : unsigned(15 downto 0) := x"ffff"; -variable test_data_vec : std_logic_vector(15 downto 0); - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; -begin - -- Set up signals - reset <= '0'; - pc_wr_en_in <= '0'; - pc_data_in <= x"00"; - pc_start_of_sub_in <= '0'; - pc_end_of_data_in <= '0'; - pc_sub_size_in <= x"0000_0000"; - pc_trig_nr_in <= x"0000_0000"; - pc_decoding_in <= x"0002_0001"; -- static - pc_event_id_in <= x"0000_00ca"; -- static - pc_queue_dec_in <= x"0003_0062"; -- static - pc_max_frame_size_in <= x"0578"; -- static - fc_h_ready_in <= '0'; - fc_ready_in <= '0'; - wait until rising_edge(clk); - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - wait until rising_edge(clk); - - -- Tests may start now - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 0; - - test_data_len := 14; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - - -- calculate the needed variables - test_loop_len := 2*(test_data_len - 1) + 1; - test_evt_len := to_unsigned( test_data_len, 16 ); - test_evt_len_vec := std_logic_vector(test_evt_len); - test_sub_len := test_evt_len + 1; - test_sub_len_vec := std_logic_vector(test_sub_len); - - -- start of subevent marker - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_trig_nr_in <= x"0000" & std_logic_vector(trigger_counter); - pc_sub_size_in <= b"0000_0000_0000_00" & test_sub_len_vec & b"00"; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_start_of_sub_in <= '1'; - wait until rising_edge(clk); - pc_start_of_sub_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_data_in <= test_evt_len_vec(15 downto 8); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_data_in <= test_evt_len_vec(7 downto 0); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_wr_en_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_data_in <= x"ff"; -- source address high byte - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_data_in <= x"22"; -- source address low byte - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_wr_en_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - test_data_vec := std_logic_vector(test_data); - wait until rising_edge(clk); - pc_data_in <= test_data_vec(15 downto 8); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_data_in <= test_data_vec(7 downto 0); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_wr_en_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); - end loop MY_DATA_LOOP; - - -- end of subevent marker --- wait until rising_edge(clk); - pc_end_of_data_in <= '1'; - wait until rising_edge(clk); - pc_end_of_data_in <= '0'; - pc_sub_size_in <= x"0000_0000"; - pc_trig_nr_in <= x"0000_0000"; - wait until rising_edge(clk); - wait until rising_edge(clk); - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait for 500 ns; - wait until rising_edge(clk); - end loop MY_TRIGGER_LOOP; - --- wait for 8 us; -------------------------------------------------------------------------------- --- end of loop -------------------------------------------------------------------------------- - - wait until rising_edge(clk); - fc_ready_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fc_h_ready_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - -- Stay a while... stay forever!!!Muahahah!!! - wait; - -end process THE_TESTBENCH; - -END; \ No newline at end of file diff --git a/gbe2_ecp3/tb_slv_mac_memory.vhd b/gbe2_ecp3/tb_slv_mac_memory.vhd deleted file mode 100755 index 00293c3..0000000 --- a/gbe2_ecp3/tb_slv_mac_memory.vhd +++ /dev/null @@ -1,114 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT slv_mac_memory - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - BUSY_IN : IN std_logic; - SLV_ADDR_IN : IN std_logic_vector(7 downto 0); - SLV_READ_IN : IN std_logic; - SLV_WRITE_IN : IN std_logic; - SLV_DATA_IN : IN std_logic_vector(31 downto 0); - MEM_CLK_IN : IN std_logic; - MEM_ADDR_IN : IN std_logic_vector(7 downto 0); - SLV_BUSY_OUT : OUT std_logic; - SLV_ACK_OUT : OUT std_logic; - SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); - MEM_DATA_OUT : OUT std_logic_vector(31 downto 0); - STAT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL BUSY_IN : std_logic; - SIGNAL SLV_ADDR_IN : std_logic_vector(7 downto 0); - SIGNAL SLV_READ_IN : std_logic; - SIGNAL SLV_WRITE_IN : std_logic; - SIGNAL SLV_BUSY_OUT : std_logic; - SIGNAL SLV_ACK_OUT : std_logic; - SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0); - SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL MEM_CLK_IN : std_logic; - SIGNAL MEM_ADDR_IN : std_logic_vector(7 downto 0); - SIGNAL MEM_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL STAT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: slv_mac_memory PORT MAP( - CLK => CLK, - RESET => RESET, - BUSY_IN => BUSY_IN, - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - MEM_CLK_IN => MEM_CLK_IN, - MEM_ADDR_IN => MEM_ADDR_IN, - MEM_DATA_OUT => MEM_DATA_OUT, - STAT => STAT - ); - -CLK_GEN_PROC: process -begin - clk <= '0'; mem_clk_in <= '0'; wait for 5.0 ns; - clk <= '1'; mem_clk_in <= '1'; wait for 5.0 ns; -end process CLK_GEN_PROC; - -THE_TESTBENCH: process -begin - -- Setup signals - reset <= '0'; - busy_in <= '0'; - slv_addr_in <= x"00"; - slv_read_in <= '0'; - slv_write_in <= '0'; - slv_data_in <= x"dead_beef"; - mem_addr_in <= x"f0"; - wait until rising_edge(clk); - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - - -- Tests may start now - wait until rising_edge(clk); - mem_addr_in <= x"00"; - wait until rising_edge(clk); - mem_addr_in <= x"01"; - wait until rising_edge(clk); - mem_addr_in <= x"02"; - wait until rising_edge(clk); - mem_addr_in <= x"03"; - wait until rising_edge(clk); - mem_addr_in <= x"04"; - wait until rising_edge(clk); - mem_addr_in <= x"05"; - wait until rising_edge(clk); - mem_addr_in <= x"06"; - wait until rising_edge(clk); - mem_addr_in <= x"07"; - wait until rising_edge(clk); - mem_addr_in <= x"08"; - - -- Stay a while... stay forever!!! Muahahaha!!!!! - wait; -end process THE_TESTBENCH; - -END; diff --git a/gbe2_ecp3/trb_net16_gbe_buf.vhd b/gbe2_ecp3/trb_net16_gbe_buf.vhd deleted file mode 100755 index 05dd9ca..0000000 --- a/gbe2_ecp3/trb_net16_gbe_buf.vhd +++ /dev/null @@ -1,1617 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; ---use work.version.all; - - -entity trb_net16_gbe_buf is -generic( - DO_SIMULATION : integer range 0 to 1 := 1; - RX_PATH_ENABLE : integer range 0 to 1 := 1; - USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1; - - FIXED_SIZE_MODE : integer range 0 to 1 := 1; - INCREMENTAL_MODE : integer range 0 to 1 := 0; - FIXED_SIZE : integer range 0 to 65535 := 10; - FIXED_DELAY_MODE : integer range 0 to 1 := 1; - UP_DOWN_MODE : integer range 0 to 1 := 0; - UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; - FIXED_DELAY : integer range 0 to 16777215 := 16777215 -); -port( - CLK : in std_logic; - TEST_CLK : in std_logic; -- only for simulation! - CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - RESET : in std_logic; - GSR_N : in std_logic; - -- Debug - STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); - STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); - -- configuration interface - IP_CFG_START_IN : in std_logic; - IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); - IP_CFG_DONE_OUT : out std_logic; - IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); - IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); - IP_CFG_MEM_CLK_OUT : out std_logic; - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_RESTART_IN : in std_logic; - -- gk 29.03.10 - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- gk 22.04.10 - -- registers setup interface - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - -- gk 23.04.10 - LED_PACKET_SENT_OUT : out std_logic; - LED_AN_DONE_N_OUT : out std_logic; - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - --SFP Connection - SFP_RXD_P_IN : in std_logic; - SFP_RXD_N_IN : in std_logic; - SFP_TXD_P_OUT : out std_logic; - SFP_TXD_N_OUT : out std_logic; - SFP_REFCLK_P_IN : in std_logic; - SFP_REFCLK_N_IN : in std_logic; - SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SFP_TXDIS_OUT : out std_logic; -- SFP disable - - -- interface between main_controller and hub logic - MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - MAKE_RESET_OUT : out std_logic; - - -- for simulation of receiving part only - MAC_RX_EOF_IN : in std_logic; - MAC_RXD_IN : in std_logic_vector(7 downto 0); - MAC_RX_EN_IN : in std_logic; - - - -- debug ports - ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end entity trb_net16_gbe_buf; - -architecture trb_net16_gbe_buf of trb_net16_gbe_buf is - --- Placer Directives ---attribute HGROUP : string; --- for whole architecture ---attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group"; - - -component tsmac35 --tsmac36 --tsmac35 -port( - --------------- clock and reset port declarations ------------------ - hclk : in std_logic; - txmac_clk : in std_logic; - rxmac_clk : in std_logic; - reset_n : in std_logic; - txmac_clk_en : in std_logic; - rxmac_clk_en : in std_logic; - ------------------- Input signals to the GMII ---------------- - rxd : in std_logic_vector(7 downto 0); - rx_dv : in std_logic; - rx_er : in std_logic; - col : in std_logic; - crs : in std_logic; - -------------------- Input signals to the CPU I/F ------------------- - haddr : in std_logic_vector(7 downto 0); - hdatain : in std_logic_vector(7 downto 0); - hcs_n : in std_logic; - hwrite_n : in std_logic; - hread_n : in std_logic; - ---------------- Input signals to the Tx MAC FIFO I/F --------------- - tx_fifodata : in std_logic_vector(7 downto 0); - tx_fifoavail : in std_logic; - tx_fifoeof : in std_logic; - tx_fifoempty : in std_logic; - tx_sndpaustim : in std_logic_vector(15 downto 0); - tx_sndpausreq : in std_logic; - tx_fifoctrl : in std_logic; - ---------------- Input signals to the Rx MAC FIFO I/F --------------- - rx_fifo_full : in std_logic; - ignore_pkt : in std_logic; - -------------------- Output signals from the GMII ----------------------- - txd : out std_logic_vector(7 downto 0); - tx_en : out std_logic; - tx_er : out std_logic; - -------------------- Output signals from the CPU I/F ------------------- - hdataout : out std_logic_vector(7 downto 0); - hdataout_en_n : out std_logic; - hready_n : out std_logic; - cpu_if_gbit_en : out std_logic; - ---------------- Output signals from the Tx MAC FIFO I/F --------------- - tx_macread : out std_logic; - tx_discfrm : out std_logic; - tx_staten : out std_logic; - tx_done : out std_logic; - tx_statvec : out std_logic_vector(30 downto 0); - ---------------- Output signals from the Rx MAC FIFO I/F --------------- - rx_fifo_error : out std_logic; - rx_stat_vector : out std_logic_vector(31 downto 0); - rx_dbout : out std_logic_vector(7 downto 0); - rx_write : out std_logic; - rx_stat_en : out std_logic; - rx_eof : out std_logic; - rx_error : out std_logic -); -end component; - -component mb_mac_sim is -port ( - -------------------------------------------------------------------------- - --------------- clock, reset, clock enable ------------------------------- - HCLK : in std_logic; - TX_MAC_CLK : in std_logic; - RX_MAC_CLK : in std_logic; - RESET_N : in std_logic; - TXMAC_CLK_EN : in std_logic; - RXMAC_CLK_EN : in std_logic; - -------------------------------------------------------------------------- - --------------- SGMII receive interface ---------------------------------- - RXD : in std_logic_vector(7 downto 0); - RX_DV : in std_logic; - RX_ER : in std_logic; - COL : in std_logic; - CRS : in std_logic; - -------------------------------------------------------------------------- - --------------- SGMII transmit interface --------------------------------- - TXD : out std_logic_vector(7 downto 0); - TX_EN : out std_logic; - TX_ER : out std_logic; - -------------------------------------------------------------------------- - --------------- CPU configuration interface ------------------------------ - HADDR : in std_logic_vector(7 downto 0); - HDATAIN : in std_logic_vector(7 downto 0); - HCS_N : in std_logic; - HWRITE_N : in std_logic; - HREAD_N : in std_logic; - HDATAOUT : out std_logic_vector(7 downto 0); - HDATAOUT_EN_N : out std_logic; - HREADY_N : out std_logic; - CPU_IF_GBIT_EN : out std_logic; - -------------------------------------------------------------------------- - --------------- Transmit FIFO interface ---------------------------------- - TX_FIFODATA : in std_logic_vector(7 downto 0); - TX_FIFOAVAIL : in std_logic; - TX_FIFOEOF : in std_logic; - TX_FIFOEMPTY : in std_logic; - TX_MACREAD : out std_logic; - TX_DONE : out std_logic; - TX_SNDPAUSTIM : in std_logic_vector(15 downto 0); - TX_SNDPAUSREQ : in std_logic; - TX_FIFOCTRL : in std_logic; - TX_DISCFRM : out std_logic; - TX_STATEN : out std_logic; - TX_STATVEC : out std_logic_vector(30 downto 0); - -------------------------------------------------------------------------- - --------------- Receive FIFO interface ----------------------------------- - RX_DBOUT : out std_logic_vector(7 downto 0); - RX_FIFO_FULL : in std_logic; - IGNORE_PKT : in std_logic; - RX_FIFO_ERROR : out std_logic; - RX_STAT_VECTOR : out std_logic_vector(31 downto 0); - RX_STAT_EN : out std_logic; - RX_WRITE : out std_logic; - RX_EOF : out std_logic; - RX_ERROR : out std_logic -); -end component; - -signal pc_decoding : std_logic_vector(31 downto 0); -signal pc_event_id : std_logic_vector(31 downto 0); -signal pc_queue_dec : std_logic_vector(31 downto 0); -signal pc_max_frame_size : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_length : std_logic_vector(15 downto 0); -signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal fc_dest_mac : std_logic_vector(47 downto 0); -signal fc_dest_ip : std_logic_vector(31 downto 0); -signal fc_dest_udp : std_logic_vector(15 downto 0); -signal fc_src_mac : std_logic_vector(47 downto 0); -signal fc_src_ip : std_logic_vector(31 downto 0); -signal fc_src_udp : std_logic_vector(15 downto 0); -signal fc_type : std_logic_vector(15 downto 0); -signal fc_ihl_version : std_logic_vector(7 downto 0); -signal fc_tos : std_logic_vector(7 downto 0); -signal fc_ttl : std_logic_vector(7 downto 0); -signal fc_protocol : std_logic_vector(7 downto 0); - -signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10 -signal ft_tx_empty : std_logic; -signal ft_start_of_packet : std_logic; -signal ft_bsm_init : std_logic_vector(3 downto 0); -signal ft_bsm_mac : std_logic_vector(3 downto 0); -signal ft_bsm_trans : std_logic_vector(3 downto 0); - -signal mac_haddr : std_logic_vector(7 downto 0); -signal mac_hdataout : std_logic_vector(7 downto 0); -signal mac_hcs : std_logic; -signal mac_hwrite : std_logic; -signal mac_hread : std_logic; -signal mac_fifoavail : std_logic; -signal mac_fifoempty : std_logic; -signal mac_fifoeof : std_logic; -signal mac_hready : std_logic; -signal mac_hdata_en : std_logic; -signal mac_tx_done : std_logic; -signal mac_tx_read : std_logic; - -signal serdes_clk_125 : std_logic; -signal mac_tx_clk_en : std_logic; -signal mac_rx_clk_en : std_logic; -signal mac_col : std_logic; -signal mac_crs : std_logic; -signal pcs_txd : std_logic_vector(7 downto 0); -signal pcs_tx_en : std_logic; -signal pcs_tx_er : std_logic; -signal pcs_an_lp_ability : std_logic_vector(15 downto 0); -signal pcs_an_complete : std_logic; -signal pcs_an_page_rx : std_logic; - -signal pcs_stat_debug : std_logic_vector(63 downto 0); - -signal stage_stat_regs : std_logic_vector(31 downto 0); -signal stage_ctrl_regs : std_logic_vector(31 downto 0); -signal use_gbe : std_logic; -signal use_trbnet : std_logic; -signal use_multievents : std_logic; --- gk 26.04.10 -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_valid : std_logic; -signal dbg_pc1 : std_logic_vector(31 downto 0); -signal dbg_fc1 : std_logic_vector(31 downto 0); -signal dbg_ft1 : std_logic_vector(31 downto 0); --- gk 08.06.10 -signal mac_tx_staten : std_logic; -signal mac_tx_statevec : std_logic_vector(30 downto 0); -signal mac_tx_discfrm : std_logic; - -signal dbg_q : std_logic_vector(15 downto 0); - --- gk 21.07.10 -signal allow_large : std_logic; - --- gk 28.07.10 -signal bytes_sent_ctr : std_logic_vector(31 downto 0); -signal monitor_dropped : std_logic_vector(31 downto 0); -signal monitor_fifos : std_logic_vector(31 downto 0); -signal monitor_fifos_q : std_logic_vector(31 downto 0); - --- gk 02.08.10 -signal discfrm_ctr : std_logic_vector(31 downto 0); - --- gk 13.02.11 -signal pcs_rxd : std_logic_vector(7 downto 0); -signal pcs_rx_en : std_logic; -signal pcs_rx_er : std_logic; -signal mac_rx_eof : std_logic; -signal mac_rx_er : std_logic; -signal mac_rxd : std_logic_vector(7 downto 0); -signal mac_rx_fifo_err : std_logic; -signal mac_rx_fifo_full : std_logic; -signal mac_rx_en : std_logic; -signal mac_rx_stat_en : std_logic; -signal mac_rx_stat_vec : std_logic_vector(31 downto 0); -signal fr_q : std_logic_vector(8 downto 0); -signal fr_rd_en : std_logic; -signal fr_frame_valid : std_logic; -signal rc_rd_en : std_logic; -signal rc_q : std_logic_vector(8 downto 0); -signal rc_frames_rec_ctr : std_logic_vector(31 downto 0); -signal mc_data : std_logic_vector(8 downto 0); -signal mc_wr_en : std_logic; -signal fc_wr_en : std_logic; -signal fc_data : std_logic_vector(7 downto 0); -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal fc_ident : std_logic_vector(15 downto 0); -signal fc_flags_offset : std_logic_vector(15 downto 0); -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_h_ready : std_logic; -signal fc_ready : std_logic; -signal rc_frame_ready : std_logic; -signal allow_rx : std_logic; -signal fr_frame_size : std_logic_vector(15 downto 0); -signal rc_frame_size : std_logic_vector(15 downto 0); -signal mc_frame_size : std_logic_vector(15 downto 0); -signal rc_bytes_rec : std_logic_vector(31 downto 0); -signal rc_debug : std_logic_vector(63 downto 0); -signal tsmac_gbit_en : std_logic; -signal mc_transmit_ctrl : std_logic; -signal rc_loading_done : std_logic; -signal fr_get_frame : std_logic; -signal mc_transmit_done : std_logic; - -signal fr_frame_proto : std_logic_vector(15 downto 0); -signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - -signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal dbg_select_rec_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal dbg_select_sent_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal dbg_select_drop_in : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal dbg_select_drop_out : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal dbg_select_gen : std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - -signal serdes_rx_clk : std_logic; - -signal mc_type : std_logic_vector(15 downto 0); -signal fr_src_mac : std_logic_vector(47 downto 0); -signal fr_dest_mac : std_logic_vector(47 downto 0); -signal fr_src_ip : std_logic_vector(31 downto 0); -signal fr_dest_ip : std_logic_vector(31 downto 0); -signal fr_src_udp : std_logic_vector(15 downto 0); -signal fr_dest_udp : std_logic_vector(15 downto 0); -signal rc_src_mac : std_logic_vector(47 downto 0); -signal rc_dest_mac : std_logic_vector(47 downto 0); -signal rc_src_ip : std_logic_vector(31 downto 0); -signal rc_dest_ip : std_logic_vector(31 downto 0); -signal rc_src_udp : std_logic_vector(15 downto 0); -signal rc_dest_udp : std_logic_vector(15 downto 0); - -signal mc_dest_mac : std_logic_vector(47 downto 0); -signal mc_dest_ip : std_logic_vector(31 downto 0); -signal mc_dest_udp : std_logic_vector(15 downto 0); -signal mc_src_mac : std_logic_vector(47 downto 0); -signal mc_src_ip : std_logic_vector(31 downto 0); -signal mc_src_udp : std_logic_vector(15 downto 0); - -signal dbg_ft : std_logic_vector(63 downto 0); - -signal fr_ip_proto : std_logic_vector(7 downto 0); -signal mc_ip_proto : std_logic_vector(7 downto 0); - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true; -attribute syn_preserve of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true; - -signal pcs_txd_q, pcs_rxd_q : std_logic_vector(7 downto 0); -signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q : std_logic; - -signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0); -signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq : std_logic; - -signal timeout_ctr : std_logic_vector(31 downto 0); -signal timeout_noticed : std_Logic; -attribute syn_keep of timeout_noticed : signal is true; -attribute syn_preserve of timeout_noticed : signal is true; - -signal make_reset : std_logic; -signal idle_too_long : std_logic; -signal mc_ident : std_logic_vector(15 downto 0); - -signal monitor_tx_packets : std_logic_vector(31 downto 0); -signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0); -signal insert_ttype, additional_hdr : std_logic; -signal dbg_hist, dbg_hist2 : hist_array; -signal mac_reset : std_logic; -signal global_reset, rst_n, ff : std_logic; - - signal gbe_cts_number : std_logic_vector(15 downto 0); - signal gbe_cts_code : std_logic_vector(7 downto 0); - signal gbe_cts_information : std_logic_vector(7 downto 0); - signal gbe_cts_start_readout : std_logic; - signal gbe_cts_readout_type : std_logic_vector(3 downto 0); - signal gbe_cts_readout_finished : std_logic; - signal gbe_cts_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_data : std_logic_vector(15 downto 0); - signal gbe_fee_dataready : std_logic; - signal gbe_fee_read : std_logic; - signal gbe_fee_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_busy : std_logic; - - signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0); - signal dhcp_done, link_ok, soft_rst : std_logic; - -signal dum_busy, dum_read, dum_dataready, dum_rd_en, dum_frame_ready : std_logic; -signal dum_data, dum_frame_size : std_logic_vector(15 downto 0); -signal dum_frame_proto : std_logic_vector(4 downto 0); -signal dum_q : std_logic_vector(8 downto 0); - -begin - -stage_ctrl_regs <= STAGE_CTRL_REGS_IN; - -reset_sync : process(GSR_N, CLK) -begin - if (GSR_N = '0') then - ff <= '0'; - rst_n <= '0'; - elsif rising_edge(CLK) then - ff <= '1'; - rst_n <= ff; - end if; -end process reset_sync; - -global_reset <= not rst_n; -- or soft_rst; - --- gk 23.04.10 -LED_PACKET_SENT_OUT <= '0'; --timeout_noticed; --pc_ready; -LED_AN_DONE_N_OUT <= dhcp_done; --not pcs_an_complete; - -fc_ihl_version <= x"45"; -fc_tos <= x"10"; -fc_ttl <= x"ff"; - ---reset_dhcp <= not GSR_N; - ---soft_gbe_reset <= '1' when soft_rst = '1' or (dhcp_done = '0' and rst_ctr(24) = '1') else '0'; - -main_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate - MAIN_CONTROL : trb_net16_gbe_main_control - generic map( - RX_PATH_ENABLE => RX_PATH_ENABLE, - DO_SIMULATION => DO_SIMULATION - ) - port map( - CLK => CLK, - CLK_125 => serdes_clk_125, - RESET => RESET, - - MC_LINK_OK_OUT => link_ok, - MC_RESET_LINK_IN => global_reset, - MC_IDLE_TOO_LONG_OUT => idle_too_long, - MC_DHCP_DONE_OUT => dhcp_done, - - -- signals to/from receive controller - RC_FRAME_WAITING_IN => rc_frame_ready, - RC_LOADING_DONE_OUT => rc_loading_done, - RC_DATA_IN => rc_q, - RC_RD_EN_OUT => rc_rd_en, - RC_FRAME_SIZE_IN => rc_frame_size, - RC_FRAME_PROTO_IN => rc_frame_proto, - - RC_SRC_MAC_ADDRESS_IN => rc_src_mac, - RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, - RC_SRC_IP_ADDRESS_IN => rc_src_ip, - RC_DEST_IP_ADDRESS_IN => rc_dest_ip, - RC_SRC_UDP_PORT_IN => rc_src_udp, - RC_DEST_UDP_PORT_IN => rc_dest_udp, - - -- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, - TC_DATA_OUT => mc_data, - TC_RD_EN_IN => mc_wr_en, - --TC_DATA_NOT_VALID_OUT => tc_data_not_valid, - TC_FRAME_SIZE_OUT => mc_frame_size, - TC_FRAME_TYPE_OUT => mc_type, - TC_IP_PROTOCOL_OUT => mc_ip_proto, - TC_IDENT_OUT => mc_ident, - - TC_DEST_MAC_OUT => mc_dest_mac, - TC_DEST_IP_OUT => mc_dest_ip, - TC_DEST_UDP_OUT => mc_dest_udp, - TC_SRC_MAC_OUT => mc_src_mac, - TC_SRC_IP_OUT => mc_src_ip, - TC_SRC_UDP_OUT => mc_src_udp, - TC_TRANSMIT_DONE_IN => mc_transmit_done, - - -- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN => pcs_an_complete, - - -- signals to/from hub - MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, - GSC_CLK_IN => GSC_CLK_IN, - GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - GSC_INIT_READ_IN => GSC_INIT_READ_IN, - GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, - GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, - GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, - GSC_BUSY_IN => GSC_BUSY_IN, - - MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT, - - -- CTS interface - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data payload interface - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- ip configurator - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - - CFG_GBE_ENABLE_IN => use_gbe, - CFG_IPU_ENABLE_IN => use_trbnet, - CFG_MULT_ENABLE_IN => use_multievents, - CFG_SUBEVENT_ID_IN => pc_event_id, - CFG_SUBEVENT_DEC_IN => pc_decoding, - CFG_QUEUE_DEC_IN => pc_queue_dec, - CFG_READOUT_CTR_IN => readout_ctr, - CFG_READOUT_CTR_VALID_IN => readout_ctr_valid, - CFG_INSERT_TTYPE_IN => insert_ttype, - CFG_MAX_SUB_IN => max_sub, - CFG_MAX_QUEUE_IN => max_queue, - CFG_MAX_SUBS_IN_QUEUE_IN => max_subs_in_queue, - CFG_MAX_SINGLE_SUB_IN => max_single_sub, - - CFG_ADDITIONAL_HDR_IN => additional_hdr, - - -- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT => mac_haddr, - TSM_HDATA_OUT => mac_hdataout, - TSM_HCS_N_OUT => mac_hcs, - TSM_HWRITE_N_OUT => mac_hwrite, - TSM_HREAD_N_OUT => mac_hread, - TSM_HREADY_N_IN => mac_hready, - TSM_HDATA_EN_N_IN => mac_hdata_en, - TSM_RX_STAT_VEC_IN => mac_rx_stat_vec, - TSM_RX_STAT_EN_IN => mac_rx_stat_en, - - MONITOR_SELECT_REC_OUT => dbg_select_rec, - MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, - MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, - MONITOR_SELECT_SENT_OUT => dbg_select_sent, - MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, - MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, - MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, - - DATA_HIST_OUT => dbg_hist, - SCTRL_HIST_OUT => dbg_hist2 - ); -end generate main_gen; - -main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate - MAIN_CONTROL : trb_net16_gbe_main_control - generic map( - RX_PATH_ENABLE => RX_PATH_ENABLE, - DO_SIMULATION => DO_SIMULATION - ) - port map( - CLK => CLK, - CLK_125 => serdes_clk_125, - RESET => RESET, - - MC_LINK_OK_OUT => link_ok, - MC_RESET_LINK_IN => global_reset, - MC_IDLE_TOO_LONG_OUT => idle_too_long, - MC_DHCP_DONE_OUT => dhcp_done, - - -- signals to/from receive controller - RC_FRAME_WAITING_IN => rc_frame_ready, - RC_LOADING_DONE_OUT => rc_loading_done, - RC_DATA_IN => rc_q, - RC_RD_EN_OUT => rc_rd_en, - RC_FRAME_SIZE_IN => rc_frame_size, - RC_FRAME_PROTO_IN => rc_frame_proto, - - RC_SRC_MAC_ADDRESS_IN => rc_src_mac, - RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, - RC_SRC_IP_ADDRESS_IN => rc_src_ip, - RC_DEST_IP_ADDRESS_IN => rc_dest_ip, - RC_SRC_UDP_PORT_IN => rc_src_udp, - RC_DEST_UDP_PORT_IN => rc_dest_udp, - - -- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, - TC_DATA_OUT => mc_data, - TC_RD_EN_IN => mc_wr_en, - --TC_DATA_NOT_VALID_OUT => tc_data_not_valid, - TC_FRAME_SIZE_OUT => mc_frame_size, - TC_FRAME_TYPE_OUT => mc_type, - TC_IP_PROTOCOL_OUT => mc_ip_proto, - TC_IDENT_OUT => mc_ident, - - TC_DEST_MAC_OUT => mc_dest_mac, - TC_DEST_IP_OUT => mc_dest_ip, - TC_DEST_UDP_OUT => mc_dest_udp, - TC_SRC_MAC_OUT => mc_src_mac, - TC_SRC_IP_OUT => mc_src_ip, - TC_SRC_UDP_OUT => mc_src_udp, - TC_TRANSMIT_DONE_IN => mc_transmit_done, - - -- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN => pcs_an_complete, - - -- signals to/from hub - MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, - GSC_CLK_IN => GSC_CLK_IN, - GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - GSC_INIT_READ_IN => '1', --GSC_INIT_READ_IN, - GSC_REPLY_DATAREADY_IN => dum_dataready, --GSC_REPLY_DATAREADY_IN, - GSC_REPLY_DATA_IN => dum_data, --GSC_REPLY_DATA_IN, - GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - GSC_REPLY_READ_OUT => dum_read, --GSC_REPLY_READ_OUT, - GSC_BUSY_IN => dum_busy, --GSC_BUSY_IN, - - MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT, - - -- CTS interface - CTS_NUMBER_IN => gbe_cts_number, - CTS_CODE_IN => gbe_cts_code, - CTS_INFORMATION_IN => gbe_cts_information, - CTS_READOUT_TYPE_IN => gbe_cts_readout_type, - CTS_START_READOUT_IN => gbe_cts_start_readout, - CTS_DATA_OUT => open, - CTS_DATAREADY_OUT => open, - CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, - CTS_READ_IN => '1', - CTS_LENGTH_OUT => open, - CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, - --Data payload interface - FEE_DATA_IN => gbe_fee_data, - FEE_DATAREADY_IN => gbe_fee_dataready, - FEE_READ_OUT => gbe_fee_read, - FEE_STATUS_BITS_IN => gbe_fee_status_bits, - FEE_BUSY_IN => gbe_fee_busy, - -- ip configurator - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - - CFG_GBE_ENABLE_IN => '1', - CFG_IPU_ENABLE_IN => '0', - CFG_MULT_ENABLE_IN => '0', - CFG_SUBEVENT_ID_IN => x"0000_00cf", - CFG_SUBEVENT_DEC_IN => x"0002_0001", - CFG_QUEUE_DEC_IN => x"0003_0062", - CFG_READOUT_CTR_IN => x"00_0000", - CFG_READOUT_CTR_VALID_IN => '0', - CFG_INSERT_TTYPE_IN => '0', - CFG_MAX_SUB_IN => x"e998", -- 59800 - CFG_MAX_QUEUE_IN => x"ea60", -- 60000 - CFG_MAX_SUBS_IN_QUEUE_IN => x"00c8", -- 200 - CFG_MAX_SINGLE_SUB_IN => x"e998", --x"7d00", -- 32000 - - CFG_ADDITIONAL_HDR_IN => '0', - - -- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT => mac_haddr, - TSM_HDATA_OUT => mac_hdataout, - TSM_HCS_N_OUT => mac_hcs, - TSM_HWRITE_N_OUT => mac_hwrite, - TSM_HREAD_N_OUT => mac_hread, - TSM_HREADY_N_IN => mac_hready, - TSM_HDATA_EN_N_IN => mac_hdata_en, - TSM_RX_STAT_VEC_IN => mac_rx_stat_vec, - TSM_RX_STAT_EN_IN => mac_rx_stat_en, - - MONITOR_SELECT_REC_OUT => dbg_select_rec, - MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, - MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, - MONITOR_SELECT_SENT_OUT => dbg_select_sent, - MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, - MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, - MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, - - DATA_HIST_OUT => dbg_hist, - SCTRL_HIST_OUT => dbg_hist2 - ); - - dummy : gbe_ipu_dummy - generic map( - DO_SIMULATION => DO_SIMULATION, - FIXED_SIZE_MODE => FIXED_SIZE_MODE, - INCREMENTAL_MODE => INCREMENTAL_MODE, - FIXED_SIZE => FIXED_SIZE, - UP_DOWN_MODE => UP_DOWN_MODE, - UP_DOWN_LIMIT => UP_DOWN_LIMIT, - FIXED_DELAY_MODE => FIXED_DELAY_MODE, - FIXED_DELAY => FIXED_DELAY - ) - port map( - clk => CLK, - rst => global_reset, - GBE_READY_IN => dhcp_done, - - CTS_NUMBER_OUT =>gbe_cts_number, - CTS_CODE_OUT =>gbe_cts_code, - CTS_INFORMATION_OUT =>gbe_cts_information, - CTS_READOUT_TYPE_OUT =>gbe_cts_readout_type, - CTS_START_READOUT_OUT =>gbe_cts_start_readout, - CTS_DATA_IN =>(others => '0'), - CTS_DATAREADY_IN =>'0', - CTS_READOUT_FINISHED_IN =>gbe_cts_readout_finished, - CTS_READ_OUT =>open, - CTS_LENGTH_IN =>(others => '0'), - CTS_ERROR_PATTERN_IN =>gbe_cts_status_bits, - -- Data payload interfac => - FEE_DATA_OUT =>gbe_fee_data, - FEE_DATAREADY_OUT =>gbe_fee_dataready, - FEE_READ_IN =>gbe_fee_read, - FEE_STATUS_BITS_OUT =>gbe_fee_status_bits, - FEE_BUSY_OUT =>gbe_fee_busy - ); - --- sctrl_dummy : gbe_sctrl_dummy --- generic map( --- DO_SIMULATION => DO_SIMULATION, --- FIXED_DELAY_MODE => 0, --- FIXED_DELAY => 4096 --- ) --- port map( --- clk => clk, --- rst => global_reset, --- --- RC_RD_EN_IN => dum_rd_en, --- RC_Q_OUT => dum_q, --- RC_FRAME_WAITING_OUT => dum_frame_ready, --- RC_LOADING_DONE_IN => '0', --- RC_FRAME_SIZE_OUT => dum_frame_size, --- RC_FRAME_PROTO_OUT => dum_frame_proto, --- --- RC_SRC_MAC_ADDRESS_OUT => open, --- RC_DEST_MAC_ADDRESS_OUT => open, --- RC_SRC_IP_ADDRESS_OUT => open, --- RC_DEST_IP_ADDRESS_OUT => open, --- RC_SRC_UDP_PORT_OUT => open, --- RC_DEST_UDP_PORT_OUT => open, --- --- GSC_REPLY_DATAREADY_OUT => dum_dataready, --- GSC_REPLY_DATA_OUT => dum_data, --- GSC_REPLY_PACKET_NUM_OUT => open, --- GSC_REPLY_READ_IN => dum_read, --- GSC_BUSY_OUT => dum_busy --- ); - - - end generate main_with_dummy_gen; - - MAKE_RESET_OUT <= make_reset; -- or idle_too_long; - -transmit_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate - - TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2 - port map( - CLK => CLK, - RESET => global_reset, --RESET, - - -- signal to/from main controller - TC_DATAREADY_IN => mc_transmit_ctrl, - TC_RD_EN_OUT => mc_wr_en, - TC_DATA_IN => mc_data(7 downto 0), - TC_FRAME_SIZE_IN => mc_frame_size, - TC_FRAME_TYPE_IN => mc_type, - TC_IP_PROTOCOL_IN => mc_ip_proto, - TC_DEST_MAC_IN => mc_dest_mac, - TC_DEST_IP_IN => mc_dest_ip, - TC_DEST_UDP_IN => mc_dest_udp, - TC_SRC_MAC_IN => mc_src_mac, - TC_SRC_IP_IN => mc_src_ip, - TC_SRC_UDP_IN => mc_src_udp, - TC_TRANSMISSION_DONE_OUT => mc_transmit_done, - TC_IDENT_IN => mc_ident, - TC_MAX_FRAME_IN => pc_max_frame_size, - - -- signal to/from frame constructor - FC_DATA_OUT => fc_data, - FC_WR_EN_OUT => fc_wr_en, - FC_READY_IN => fc_ready, - FC_H_READY_IN => fc_h_ready, - FC_FRAME_TYPE_OUT => fc_type, - FC_IP_SIZE_OUT => fc_ip_size, - FC_UDP_SIZE_OUT => fc_udp_size, - FC_IDENT_OUT => fc_ident, - FC_FLAGS_OFFSET_OUT => fc_flags_offset, - FC_SOD_OUT => fc_sod, - FC_EOD_OUT => fc_eod, - FC_IP_PROTOCOL_OUT => fc_protocol, - - DEST_MAC_ADDRESS_OUT => fc_dest_mac, - DEST_IP_ADDRESS_OUT => fc_dest_ip, - DEST_UDP_PORT_OUT => fc_dest_udp, - SRC_MAC_ADDRESS_OUT => fc_src_mac, - SRC_IP_ADDRESS_OUT => fc_src_ip, - SRC_UDP_PORT_OUT => fc_src_udp, - - MONITOR_TX_PACKETS_OUT => monitor_tx_packets - ); -end generate transmit_gen; - -transmit_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate - TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2 -port map( - CLK => CLK, - RESET => global_reset, --RESET, - --- signal to/from main controller - TC_DATAREADY_IN => mc_transmit_ctrl, - TC_RD_EN_OUT => mc_wr_en, - TC_DATA_IN => mc_data(7 downto 0), - TC_FRAME_SIZE_IN => mc_frame_size, - TC_FRAME_TYPE_IN => mc_type, - TC_IP_PROTOCOL_IN => mc_ip_proto, - TC_DEST_MAC_IN => mc_dest_mac, - TC_DEST_IP_IN => mc_dest_ip, - TC_DEST_UDP_IN => mc_dest_udp, - TC_SRC_MAC_IN => mc_src_mac, - TC_SRC_IP_IN => mc_src_ip, - TC_SRC_UDP_IN => mc_src_udp, - TC_TRANSMISSION_DONE_OUT => mc_transmit_done, - TC_IDENT_IN => mc_ident, - TC_MAX_FRAME_IN => x"0578", - --- signal to/from frame constructor - FC_DATA_OUT => fc_data, - FC_WR_EN_OUT => fc_wr_en, - FC_READY_IN => fc_ready, - FC_H_READY_IN => fc_h_ready, - FC_FRAME_TYPE_OUT => fc_type, - FC_IP_SIZE_OUT => fc_ip_size, - FC_UDP_SIZE_OUT => fc_udp_size, - FC_IDENT_OUT => fc_ident, - FC_FLAGS_OFFSET_OUT => fc_flags_offset, - FC_SOD_OUT => fc_sod, - FC_EOD_OUT => fc_eod, - FC_IP_PROTOCOL_OUT => fc_protocol, - - DEST_MAC_ADDRESS_OUT => fc_dest_mac, - DEST_IP_ADDRESS_OUT => fc_dest_ip, - DEST_UDP_PORT_OUT => fc_dest_udp, - SRC_MAC_ADDRESS_OUT => fc_src_mac, - SRC_IP_ADDRESS_OUT => fc_src_ip, - SRC_UDP_PORT_OUT => fc_src_udp, - - MONITOR_TX_PACKETS_OUT => monitor_tx_packets -); -end generate transmit_with_dummy_gen; - - -setup_imp_gen : if (DO_SIMULATION = 0) generate -SETUP : gbe_setup -port map( - CLK => CLK, - RESET => global_reset, --RESET, - - -- interface to regio bus - BUS_ADDR_IN => BUS_ADDR_IN, - BUS_DATA_IN => BUS_DATA_IN, - BUS_DATA_OUT => BUS_DATA_OUT, - BUS_WRITE_EN_IN => BUS_WRITE_EN_IN, - BUS_READ_EN_IN => BUS_READ_EN_IN, - BUS_ACK_OUT => BUS_ACK_OUT, - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT => pc_event_id, - GBE_SUBEVENT_DEC_OUT => pc_decoding, - GBE_QUEUE_DEC_OUT => pc_queue_dec, - GBE_MAX_FRAME_OUT => pc_max_frame_size, - GBE_USE_GBE_OUT => use_gbe, - GBE_USE_TRBNET_OUT => use_trbnet, - GBE_USE_MULTIEVENTS_OUT => use_multievents, - GBE_READOUT_CTR_OUT => readout_ctr, - GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, - GBE_ALLOW_RX_OUT => allow_rx, - GBE_ADDITIONAL_HDR_OUT => additional_hdr, - GBE_INSERT_TTYPE_OUT => insert_ttype, - GBE_SOFT_RESET_OUT => soft_rst, - - GBE_MAX_SUB_OUT => max_sub, - GBE_MAX_QUEUE_OUT => max_queue, - GBE_MAX_SUBS_IN_QUEUE_OUT => max_subs_in_queue, - GBE_MAX_SINGLE_SUB_OUT => max_single_sub, - - MONITOR_RX_BYTES_IN => monitor_rx_bytes, - MONITOR_RX_FRAMES_IN => monitor_rx_frames, - MONITOR_TX_BYTES_IN => monitor_tx_bytes, - MONITOR_TX_FRAMES_IN => monitor_tx_frames, - MONITOR_TX_PACKETS_IN => monitor_tx_packets, - MONITOR_DROPPED_IN => monitor_dropped, - - MONITOR_SELECT_REC_IN => dbg_select_rec, - MONITOR_SELECT_REC_BYTES_IN => dbg_select_rec_bytes, - MONITOR_SELECT_SENT_BYTES_IN => dbg_select_sent_bytes, - MONITOR_SELECT_SENT_IN => dbg_select_sent, - MONITOR_SELECT_DROP_IN_IN => dbg_select_drop_in, - MONITOR_SELECT_DROP_OUT_IN => dbg_select_drop_out, - MONITOR_SELECT_GEN_DBG_IN => dbg_select_gen, - - DATA_HIST_IN => dbg_hist, - SCTRL_HIST_IN => dbg_hist2 -); -end generate; - -setup_sim_gen : if (DO_SIMULATION = 1) generate - use_gbe <= '1'; - allow_rx <= '1'; - allow_large <= '0'; -end generate; - --- Third stage: Frame Constructor -FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr -port map( - -- ports for user logic - RESET => global_reset, --RESET, - CLK => CLK, - LINK_OK_IN => '1', --link_ok, - -- - WR_EN_IN => fc_wr_en, - DATA_IN => fc_data, - START_OF_DATA_IN => fc_sod, - END_OF_DATA_IN => fc_eod, - IP_F_SIZE_IN => fc_ip_size, - UDP_P_SIZE_IN => fc_udp_size, - HEADERS_READY_OUT => fc_h_ready, - READY_OUT => fc_ready, - DEST_MAC_ADDRESS_IN => fc_dest_mac, - DEST_IP_ADDRESS_IN => fc_dest_ip, - DEST_UDP_PORT_IN => fc_dest_udp, - SRC_MAC_ADDRESS_IN => fc_src_mac, - SRC_IP_ADDRESS_IN => fc_src_ip, - SRC_UDP_PORT_IN => fc_src_udp, - FRAME_TYPE_IN => fc_type, - IHL_VERSION_IN => fc_ihl_version, - TOS_IN => fc_tos, - IDENTIFICATION_IN => fc_ident, - FLAGS_OFFSET_IN => fc_flags_offset, - TTL_IN => fc_ttl, - PROTOCOL_IN => fc_protocol, - FRAME_DELAY_IN => (others => '0'), - - RD_CLK => serdes_clk_125, - FT_DATA_OUT => ft_data, - FT_TX_EMPTY_OUT => ft_tx_empty, - FT_TX_RD_EN_IN => mac_tx_read, - FT_START_OF_PACKET_OUT => ft_start_of_packet, - FT_TX_DONE_IN => mac_tx_done, - FT_TX_DISCFRM_IN => mac_tx_discfrm, - - MONITOR_TX_BYTES_OUT => monitor_tx_bytes, - MONITOR_TX_FRAMES_OUT => monitor_tx_frames -); - -dbg_q(15 downto 9) <= (others => '0'); - -FRAME_TRANSMITTER: trb_net16_gbe_frame_trans -port map( - CLK => CLK, - RESET => global_reset, --RESET, - LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10 - TX_MAC_CLK => serdes_clk_125, - TX_EMPTY_IN => ft_tx_empty, - START_OF_PACKET_IN => ft_start_of_packet, - DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10 - - TX_FIFOAVAIL_OUT => mac_fifoavail, - TX_FIFOEOF_OUT => mac_fifoeof, - TX_FIFOEMPTY_OUT => mac_fifoempty, - TX_DONE_IN => mac_tx_done, - TX_STAT_EN_IN => mac_tx_staten, - TX_STATVEC_IN => mac_tx_statevec, - TX_DISCFRM_IN => mac_tx_discfrm, - -- Debug - BSM_INIT_OUT => ft_bsm_init, - BSM_MAC_OUT => ft_bsm_mac, - BSM_TRANS_OUT => ft_bsm_trans, - DBG_RD_DONE_OUT => open, - DBG_INIT_DONE_OUT => open, - DBG_ENABLED_OUT => open, - DEBUG_OUT => dbg_ft - --DEBUG_OUT(31 downto 0) => open, - --DEBUG_OUT(63 downto 32) => open -); - -rx_enable_gen : if (RX_PATH_ENABLE = 1) generate - - RECEIVE_CONTROLLER : trb_net16_gbe_receive_control - port map( - CLK => CLK, - RESET => global_reset, --RESET, - - -- signals to/from frame_receiver - RC_DATA_IN => fr_q, - FR_RD_EN_OUT => fr_rd_en, - FR_FRAME_VALID_IN => fr_frame_valid, - FR_GET_FRAME_OUT => fr_get_frame, - FR_FRAME_SIZE_IN => fr_frame_size, - FR_FRAME_PROTO_IN => fr_frame_proto, - FR_IP_PROTOCOL_IN => fr_ip_proto, - - FR_SRC_MAC_ADDRESS_IN => fr_src_mac, - FR_DEST_MAC_ADDRESS_IN => fr_dest_mac, - FR_SRC_IP_ADDRESS_IN => fr_src_ip, - FR_DEST_IP_ADDRESS_IN => fr_dest_ip, - FR_SRC_UDP_PORT_IN => fr_src_udp, - FR_DEST_UDP_PORT_IN => fr_dest_udp, - - -- signals to/from main controller - RC_RD_EN_IN => rc_rd_en, - RC_Q_OUT => rc_q, - RC_FRAME_WAITING_OUT => rc_frame_ready, - RC_LOADING_DONE_IN => rc_loading_done, - RC_FRAME_SIZE_OUT => rc_frame_size, - RC_FRAME_PROTO_OUT => rc_frame_proto, - - RC_SRC_MAC_ADDRESS_OUT => rc_src_mac, - RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac, - RC_SRC_IP_ADDRESS_OUT => rc_src_ip, - RC_DEST_IP_ADDRESS_OUT => rc_dest_ip, - RC_SRC_UDP_PORT_OUT => rc_src_udp, - RC_DEST_UDP_PORT_OUT => rc_dest_udp, - - -- statistics - FRAMES_RECEIVED_OUT => rc_frames_rec_ctr, - BYTES_RECEIVED_OUT => rc_bytes_rec, - - - DEBUG_OUT => rc_debug - ); - - FRAME_RECEIVER : trb_net16_gbe_frame_receiver - port map( - CLK => CLK, - RESET => global_reset, --RESET, - LINK_OK_IN => link_ok, - ALLOW_RX_IN => allow_rx, - RX_MAC_CLK => serdes_rx_clk, --serdes_clk_125, - - -- input signals from TS_MAC - MAC_RX_EOF_IN => mac_rx_eof, - MAC_RX_ER_IN => mac_rx_er, - MAC_RXD_IN => mac_rxd, - MAC_RX_EN_IN => mac_rx_en, - MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err, - MAC_RX_FIFO_FULL_OUT => mac_rx_fifo_full, - MAC_RX_STAT_EN_IN => mac_rx_stat_en, - MAC_RX_STAT_VEC_IN => mac_rx_stat_vec, - -- output signal to control logic - FR_Q_OUT => fr_q, - FR_RD_EN_IN => fr_rd_en, - FR_FRAME_VALID_OUT => fr_frame_valid, - FR_GET_FRAME_IN => fr_get_frame, - FR_FRAME_SIZE_OUT => fr_frame_size, - FR_FRAME_PROTO_OUT => fr_frame_proto, - FR_IP_PROTOCOL_OUT => fr_ip_proto, - FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types, - FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip, - FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp, - FR_VLAN_ID_IN => (others => '0'), --vlan_id, - - FR_SRC_MAC_ADDRESS_OUT => fr_src_mac, - FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac, - FR_SRC_IP_ADDRESS_OUT => fr_src_ip, - FR_DEST_IP_ADDRESS_OUT => fr_dest_ip, - FR_SRC_UDP_PORT_OUT => fr_src_udp, - FR_DEST_UDP_PORT_OUT => fr_dest_udp, - - MONITOR_RX_BYTES_OUT => monitor_rx_bytes, - MONITOR_RX_FRAMES_OUT => monitor_rx_frames, - MONITOR_DROPPED_OUT => monitor_dropped - ); - -end generate rx_enable_gen; - -rx_disable_gen : if (RX_PATH_ENABLE = 0) generate - - - rc_q <= (others => '0'); - rc_frame_ready <= '0'; - rc_frame_size <= (others => '0'); - rc_frame_proto <= (others => '0'); - - rc_src_mac <= (others => '0'); - rc_dest_mac <= (others => '0'); - rc_src_ip <= (others => '0'); - rc_dest_ip <= (others => '0'); - rc_src_udp <= (others => '0'); - rc_dest_udp <= (others => '0'); - - rc_frames_rec_ctr <= (others => '0'); - rc_bytes_rec <= (others => '0'); - rc_debug <= (others => '0'); - - monitor_rx_bytes <= (others => '0'); - monitor_rx_frames <= (others => '0'); - monitor_dropped <= (others => '0'); - - mac_rx_fifo_full <= '0'; - -end generate rx_disable_gen; - - --- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in -imp_gen: if (DO_SIMULATION = 0) generate - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - -- Implementation - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - - - TIMEOUT_CTR_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1' or mac_tx_done = '1') then - timeout_ctr <= (others => '0'); - else - timeout_ctr <= timeout_ctr + x"1"; - end if; - end if; - end process TIMEOUT_CTR_PROC; - - TIMEOUT_NOTICED_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - timeout_noticed <= '0'; - elsif (timeout_ctr(30) = '1') then - timeout_noticed <= '1'; - end if; - end if; - end process TIMEOUT_NOTICED_PROC; - - mac_reset <= not RESET; - - -- MAC part - MAC: tsmac35 --tsmac36 --tsmac35 - port map( - ----------------- clock and reset port declarations ------------------ - hclk => CLK, - txmac_clk => serdes_clk_125, - rxmac_clk => serdes_rx_clk, --serdes_clk_125, - reset_n => GSR_N, - txmac_clk_en => mac_tx_clk_en, - rxmac_clk_en => mac_rx_clk_en, - ------------------- Input signals to the GMII ---------------- NOT USED - rxd => pcs_rxd_qq, --x"00", - rx_dv => pcs_rx_en_qq, --'0', - rx_er => pcs_rx_er_qq, --'0', - col => mac_col, - crs => mac_crs, - -------------------- Input signals to the CPU I/F ------------------- - haddr => mac_haddr, - hdatain => mac_hdataout, - hcs_n => mac_hcs, - hwrite_n => mac_hwrite, - hread_n => mac_hread, - ---------------- Input signals to the Tx MAC FIFO I/F --------------- - tx_fifodata => ft_data(7 downto 0), - tx_fifoavail => mac_fifoavail, - tx_fifoeof => mac_fifoeof, - tx_fifoempty => mac_fifoempty, - tx_sndpaustim => x"0000", - tx_sndpausreq => '0', - tx_fifoctrl => '0', -- always data frame - ---------------- Input signals to the Rx MAC FIFO I/F --------------- - rx_fifo_full => mac_rx_fifo_full, --'0', - ignore_pkt => '0', - ---------------- Output signals from the GMII ----------------------- - txd => pcs_txd, - tx_en => pcs_tx_en, - tx_er => pcs_tx_er, - ----------------- Output signals from the CPU I/F ------------------- - hdataout => open, - hdataout_en_n => mac_hdata_en, - hready_n => mac_hready, - cpu_if_gbit_en => tsmac_gbit_en, - ------------- Output signals from the Tx MAC FIFO I/F --------------- - tx_macread => mac_tx_read, - tx_discfrm => mac_tx_discfrm, - tx_staten => mac_tx_staten, -- gk 08.06.10 - tx_statvec => mac_tx_statevec, -- gk 08.06.10 - tx_done => mac_tx_done, - ------------- Output signals from the Rx MAC FIFO I/F --------------- - rx_fifo_error => mac_rx_fifo_err, --open, - rx_stat_vector => mac_rx_stat_vec, --open, - rx_dbout => mac_rxd, --open, - rx_write => mac_rx_en, --open, - rx_stat_en => mac_rx_stat_en, --open, - rx_eof => mac_rx_eof, --open, - rx_error => mac_rx_er --open - ); - - SYNC_GMII_RX_PROC : process(serdes_rx_clk) - begin - if rising_edge(serdes_rx_clk) then - pcs_rxd_q <= pcs_rxd; - pcs_rx_en_q <= pcs_rx_en; - pcs_rx_er_q <= pcs_rx_er; - - pcs_rxd_qq <= pcs_rxd_q; - pcs_rx_en_qq <= pcs_rx_en_q; - pcs_rx_er_qq <= pcs_rx_er_q; - --mac_col_q <= mac_col; - --mac_crs_q <= mac_crs; - end if; - end process SYNC_GMII_RX_PROC; - - SYNC_GMII_TX_PROC : process(serdes_clk_125) - begin - if rising_edge(serdes_clk_125) then - pcs_txd_q <= pcs_txd; - pcs_tx_en_q <= pcs_tx_en; - pcs_tx_er_q <= pcs_tx_er; - - pcs_txd_qq <= pcs_txd_q; - pcs_tx_en_qq <= pcs_tx_en_q; - pcs_tx_er_qq <= pcs_tx_er_q; - end if; - end process SYNC_GMII_TX_PROC; - - -- gk 08.06.10 - dbg_statevec_proc : process(serdes_clk_125) - begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') then - dbg_ft1 <= (others => '0'); - elsif (mac_tx_staten = '1') then - dbg_ft1(30 downto 0) <= mac_tx_statevec; - dbg_ft1(31) <= mac_tx_discfrm; - end if; - end if; - end process dbg_statevec_proc; - - serdes_intclk_gen: if (USE_125MHZ_EXTCLK = 0) generate - -- PHY part - PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b - generic map( - USE_125MHZ_EXTCLK => 0 - ) - port map( - RESET => global_reset, --soft_gbe_reset, --RESET, - GSR_N => GSR_N, - CLK_125_OUT => serdes_clk_125, - CLK_125_RX_OUT => serdes_rx_clk, --open, - CLK_125_IN => CLK_125_IN, - FT_TX_CLK_EN_OUT => mac_tx_clk_en, - FT_RX_CLK_EN_OUT => mac_rx_clk_en, - --connection to frame transmitter (tsmac) - FT_COL_OUT => mac_col, - FT_CRS_OUT => mac_crs, - FT_TXD_IN => pcs_txd_qq, - FT_TX_EN_IN => pcs_tx_en_qq, - FT_TX_ER_IN => pcs_tx_er_qq, - FT_RXD_OUT => pcs_rxd, - FT_RX_EN_OUT => pcs_rx_en, - FT_RX_ER_OUT => pcs_rx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => SFP_REFCLK_P_IN, - SD_REFCLK_N_IN => SFP_REFCLK_N_IN, - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, - -- Autonegotiation stuff - MR_ADV_ABILITY_IN => x"0020", -- full duplex only - MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, - MR_AN_PAGE_RX_OUT => pcs_an_page_rx, - MR_AN_COMPLETE_OUT => pcs_an_complete, - MR_RESET_IN => RESET, - MR_MODE_IN => '0', --MR_MODE_IN, - MR_AN_ENABLE_IN => '1', -- do autonegotiation - MR_RESTART_AN_IN => '0', --MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" - ); - end generate serdes_intclk_gen; - - serdes_extclk_gen: if (USE_125MHZ_EXTCLK = 1) generate - -- PHY part - PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b - generic map( - USE_125MHZ_EXTCLK => 1 - ) - port map( - RESET => global_reset, --soft_gbe_reset, --RESET, - GSR_N => GSR_N, - CLK_125_OUT => serdes_clk_125, - CLK_125_RX_OUT => serdes_rx_clk, - CLK_125_IN => '0', -- not used - FT_TX_CLK_EN_OUT => mac_tx_clk_en, - FT_RX_CLK_EN_OUT => mac_rx_clk_en, - --connection to frame transmitter (tsmac) - FT_COL_OUT => mac_col, - FT_CRS_OUT => mac_crs, - FT_TXD_IN => pcs_txd, - FT_TX_EN_IN => pcs_tx_en, - FT_TX_ER_IN => pcs_tx_er, - FT_RXD_OUT => pcs_rxd, - FT_RX_EN_OUT => pcs_rx_en, - FT_RX_ER_OUT => pcs_rx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => SFP_REFCLK_P_IN, - SD_REFCLK_N_IN => SFP_REFCLK_N_IN, - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, - -- Autonegotiation stuff - MR_ADV_ABILITY_IN => x"0020", -- full duplex only - MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, - MR_AN_PAGE_RX_OUT => pcs_an_page_rx, - MR_AN_COMPLETE_OUT => pcs_an_complete, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_AN_ENABLE_IN => '1', -- do autonegotiation - MR_RESTART_AN_IN => MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" - ); - end generate serdes_extclk_gen; - - stage_stat_regs(31 downto 28) <= x"e"; - stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link s-tatus - stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm - stage_stat_regs(19) <= '0'; - stage_stat_regs(18) <= link_ok; -- gk 30.09.10 - stage_stat_regs(17) <= pcs_an_complete; - stage_stat_regs(16) <= pcs_an_page_rx; - stage_stat_regs(15 downto 0) <= pcs_an_lp_ability; - -end generate imp_gen; - --- in case of simulation we include a fake MAC and no PHY/SerDes. -sim_gen: if (DO_SIMULATION = 1) generate - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - -- Simulation - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - MAC: mb_mac_sim - port map( -------------------------------------------------------------------------- - --------------- clock, reset, clock enable ------------------------------- - HCLK => CLK, - TX_MAC_CLK => serdes_clk_125, - RX_MAC_CLK => serdes_rx_clk, --serdes_clk_125, - RESET_N => GSR_N, - TXMAC_CLK_EN => mac_tx_clk_en, - RXMAC_CLK_EN => mac_rx_clk_en, - -------------------------------------------------------------------------- - --------------- SGMII receive interface ---------------------------------- - RXD => x"00", - RX_DV => '0', - RX_ER => '0', - COL => mac_col, - CRS => mac_crs, - -------------------------------------------------------------------------- - --------------- SGMII transmit interface --------------------------------- - TXD => pcs_txd, - TX_EN => pcs_tx_en, - TX_ER => pcs_tx_er, - -------------------------------------------------------------------------- - --------------- CPU configuration interface ------------------------------ - HADDR => mac_haddr, - HDATAIN => mac_hdataout, - HCS_N => mac_hcs, - HWRITE_N => mac_hwrite, - HREAD_N => mac_hread, - HDATAOUT => open, - HDATAOUT_EN_N => mac_hdata_en, - HREADY_N => mac_hready, - CPU_IF_GBIT_EN => open, - -------------------------------------------------------------------------- - --------------- Transmit FIFO interface ---------------------------------- - TX_FIFODATA => ft_data(7 downto 0), - TX_FIFOAVAIL => mac_fifoavail, - TX_FIFOEOF => mac_fifoeof, - TX_FIFOEMPTY => mac_fifoempty, - TX_MACREAD => mac_tx_read, - TX_DONE => mac_tx_done, - TX_SNDPAUSTIM => x"0000", - TX_SNDPAUSREQ => '0', - TX_FIFOCTRL => '0', - TX_DISCFRM => open, - TX_STATEN => open, - TX_STATVEC => open, - -------------------------------------------------------------------------- - --------------- Receive FIFO interface ----------------------------------- - RX_DBOUT => open, - RX_FIFO_FULL => '0', - IGNORE_PKT => '0', - RX_FIFO_ERROR => open, - RX_STAT_VECTOR => open, - RX_STAT_EN => open, - RX_WRITE => open, - RX_EOF => open, - RX_ERROR => open - ); - - -- add external test clock for the MAC part - serdes_clk_125 <= TEST_CLK; - - -- fake signals - pcs_an_lp_ability <= x"4060"; - pcs_an_page_rx <= '0'; - pcs_an_complete <= '1'; - mac_tx_clk_en <= '1'; - mac_rx_clk_en <= '1'; - - stage_stat_regs(31 downto 0) <= (others => '0'); - - pcs_stat_debug(63 downto 0) <= (others => '0'); - - SFP_TXD_P_OUT <= '1'; - SFP_TXD_N_OUT <= '0'; - SFP_TXDIS_OUT <= '0'; - - mac_rxd <= MAC_RXD_IN; - mac_rx_eof <= MAC_RX_EOF_IN; - mac_rx_en <= MAC_RX_EN_IN; - - serdes_rx_clk <= TEST_CLK; - -end generate sim_gen; - - ---*********************** --- MONITORING & DEBUG ---*********************** - - - - --- gk 04.08.10 ---MON_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0); --- if (dbg_pc1(28) = '1') then --- monitor_fifos_q(5 downto 4) <= b"11"; --- else --- monitor_fifos_q(5 downto 4) <= b"00"; --- end if; --- if (dbg_pc1(30) = '1') then --- monitor_fifos_q(7 downto 6) <= b"11"; --- else --- monitor_fifos_q(7 downto 6) <= b"00"; --- end if; --- if (dbg_fc1(28) = '1') then --- monitor_fifos_q(11 downto 8) <= b"1111"; --- else --- monitor_fifos_q(11 downto 8) <= b"0000"; --- end if; --- if (pcs_an_complete = '0') then --- monitor_fifos_q(15 downto 12) <= b"1111"; --- else --- monitor_fifos_q(15 downto 12) <= b"0000"; --- end if; --- end if; ---end process MON_PROC; - ----- gk 28.07.10 ---BYTES_SENT_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- bytes_sent_ctr <= (others => '0'); --- elsif (fc_wr_en = '1') then --- bytes_sent_ctr <= bytes_sent_ctr + x"1"; --- end if; --- end if; ---end process BYTES_SENT_CTR_PROC; --- ----- gk 02.08.10 ---DISCFRM_PROC : process(serdes_clk_125) ---begin --- if rising_edge(serdes_clk_125) then --- if (RESET = '1') then --- discfrm_ctr <= (others => '0'); --- elsif (mac_tx_discfrm = '1') then --- discfrm_ctr <= discfrm_ctr + x"1"; --- end if; --- end if; ---end process DISCFRM_PROC; --- ---discfrm_sync : signal_sync --- generic map( --- DEPTH => 2, --- WIDTH => 32 --- ) --- port map( --- RESET => RESET, --- D_IN => discfrm_ctr, --- CLK0 => serdes_clk_125, --- CLK1 => CLK, --- D_OUT => monitor_discfrm --- ); - - ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------- - ---*************** --- LOGIC ANALYZER SIGNALS ---*************** ---ANALYZER_DEBUG_OUT <= dbg_mc or dbg_tc or (dbg_fc1 & dbg_fc2) or rc_debug or dbg_ft or dbg_fr(63 downto 0) or (dbg_fr(95 downto 64) & x"00000000"); ---ANALYZER_DEBUG_OUT(3 downto 0) <= dbg_select_protos(99 downto 96); ---ANALYZER_DEBUG_OUT(63 downto 4) <= (others => '0'); - --- Outputs ---FEE_READ_OUT <= fee_read; - -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_DATA_OUT <= cts_data; -CTS_LENGTH_OUT <= cts_length; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; - -STAGE_STAT_REGS_OUT <= stage_stat_regs; - - -end architecture; diff --git a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd b/gbe2_ecp3/trb_net16_gbe_event_constr.vhd deleted file mode 100644 index 2324dc0..0000000 --- a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd +++ /dev/null @@ -1,701 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - -entity trb_net16_gbe_event_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 - PC_END_OF_QUEUE_IN : in std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_INSERT_TTYPE_IN : in std_logic; - -- FrameConstructor ports - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_SOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end entity trb_net16_gbe_event_constr; - -architecture RTL of trb_net16_gbe_event_constr is - -attribute syn_encoding : string; - -type loadStates is (IDLE, GET_Q_SIZE, START_TRANSFER, LOAD_Q_HEADERS, LOAD_DATA, LOAD_SUB, LOAD_PADDING, LOAD_TERM, CLEANUP); -signal load_current_state, load_next_state : loadStates; -attribute syn_encoding of load_current_state : signal is "onehot"; - -type saveSubHdrStates is (IDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRG_NR); -signal save_sub_hdr_current_state, save_sub_hdr_next_state : saveSubHdrStates; -attribute syn_encoding of save_sub_hdr_current_state : signal is "onehot"; - -signal df_eos, df_wr_en, df_rd_en, df_empty, df_full, load_eod : std_logic; -signal df_q, df_qq : std_logic_vector(7 downto 0); - -signal header_ctr : integer range 0 to 31; - -signal shf_data, shf_q, shf_qq : std_logic_vector(7 downto 0); -signal shf_wr_en, shf_rd_en, shf_empty, shf_full : std_logic; -signal sub_int_ctr : integer range 0 to 3; -signal sub_size_to_save : std_logic_vector(31 downto 0); - -signal qsf_data : std_logic_vector(31 downto 0); -signal qsf_q : std_logic_vector(7 downto 0); -signal qsf_wr, qsf_wr_en, qsf_wr_en_q, qsf_wr_en_qq, qsf_wr_en_qqq, qsf_rd_en, qsf_rd_en_q, qsf_empty : std_logic; - -signal queue_size : std_logic_vector(31 downto 0); - -signal termination : std_logic_vector(255 downto 0); -signal term_ctr : integer range 0 to 33; - -signal actual_q_size : std_logic_vector(15 downto 0); -signal tc_data : std_logic_vector(7 downto 0); -signal df_data : std_logic_vector(7 downto 0); -signal df_eos_q, df_eos_qq : std_logic; -signal df_wr_en_q, df_wr_en_qq : std_logic; -signal qsf_full : std_logic; - -signal padding_needed, insert_padding : std_logic; -signal load_eod_q : std_logic; -signal loaded_queue_bytes : std_logic_vector(15 downto 0); -signal shf_padding : std_logic; -signal block_shf_after_divide, previous_tc_rd : std_logic; -signal block_term_after_divide : std_logic; - -begin - ---******* --- SAVING PART ---******* - -DF_EOD_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (PC_END_OF_SUB_IN = '1') then - df_eos <= '1'; - else - df_eos <= '0'; - end if; - - df_eos_q <= df_eos; - df_eos_qq <= df_eos_q; - end if; -end process DF_EOD_PROC; - -DF_WR_EN_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (PC_WR_EN_IN = '1') then - df_wr_en <= '1'; - else - df_wr_en <= '0'; - end if; - - df_wr_en_q <= df_wr_en; - df_wr_en_qq <= df_wr_en_q; - - df_data <= PC_DATA_IN; - end if; -end process DF_WR_EN_PROC; - -DATA_FIFO : fifo_64kx9 -port map( - Data(7 downto 0) => df_data, - Data(8) => df_eos_q, - WrClock => CLK, - RdClock => CLK, - WrEn => df_wr_en_qq, - RdEn => df_rd_en, - Reset => RESET, - RPReset => RESET, - Q(7 downto 0) => df_q, - Q(8) => load_eod, - Empty => df_empty, - Full => df_full -); - -DF_QQ_PROC : process(CLK) -begin - if rising_edge(CLK) then - df_qq <= df_q; - end if; -end process DF_QQ_PROC; - -READY_PROC : process(CLK) -begin - if rising_edge(CLK) then - PC_READY_OUT <= not df_full; - end if; -end process READY_PROC; - ---***** --- subevent headers -SUBEVENT_HEADERS_FIFO : fifo_4096x9 --fifo_4kx8_ecp3 -port map( - Data(7 downto 0) => shf_data, - Data(8) => PC_SUB_SIZE_IN(2), - WrClock => CLK, - RdClock => CLK, - WrEn => shf_wr_en, - RdEn => shf_rd_en, - Reset => RESET, - RPReset => RESET, - Q(7 downto 0) => shf_q, - Q(8) => shf_padding, - Empty => shf_empty, - Full => shf_full -); - -SHF_WR_EN_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (save_sub_hdr_current_state = IDLE) then - shf_wr_en <= '0'; - else - shf_wr_en <= '1'; - end if; - end if; -end process SHF_WR_EN_PROC; - -VARIOUS_SYNC : process(CLK) -begin - if rising_edge(CLK) then - shf_qq <= shf_q; - end if; -end process VARIOUS_SYNC; - -SAVE_SUB_HDR_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - save_sub_hdr_current_state <= IDLE; - elsif rising_edge(CLK) then - save_sub_hdr_current_state <= save_sub_hdr_next_state; - end if; -end process SAVE_SUB_HDR_MACHINE_PROC; - -SAVE_SUB_HDR_MACHINE : process(save_sub_hdr_current_state, PC_START_OF_SUB_IN, sub_int_ctr) -begin - case (save_sub_hdr_current_state) is - - when IDLE => - if (PC_START_OF_SUB_IN = '1') then - save_sub_hdr_next_state <= SAVE_SIZE; - else - save_sub_hdr_next_state <= IDLE; - end if; - - when SAVE_SIZE => - if (sub_int_ctr = 0) then - save_sub_hdr_next_state <= SAVE_DECODING; - else - save_sub_hdr_next_state <= SAVE_SIZE; - end if; - - when SAVE_DECODING => - if (sub_int_ctr = 0) then - save_sub_hdr_next_state <= SAVE_ID; - else - save_sub_hdr_next_state <= SAVE_DECODING; - end if; - - when SAVE_ID => - if (sub_int_ctr = 0) then - save_sub_hdr_next_state <= SAVE_TRG_NR; - else - save_sub_hdr_next_state <= SAVE_ID; - end if; - - when SAVE_TRG_NR => - if (sub_int_ctr = 0) then - save_sub_hdr_next_state <= IDLE; - else - save_sub_hdr_next_state <= SAVE_TRG_NR; - end if; - - when others => save_sub_hdr_next_state <= IDLE; - - end case; -end process SAVE_SUB_HDR_MACHINE; - -SUB_INT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (save_sub_hdr_current_state = IDLE) then - sub_int_ctr <= 3; - else - if (sub_int_ctr = 0) then - sub_int_ctr <= 3; - else - sub_int_ctr <= sub_int_ctr - 1; - end if; - end if; - end if; -end process SUB_INT_CTR_PROC; - -SUB_SIZE_TO_SAVE_PROC : process (CLK) -begin - if rising_edge(CLK) then - sub_size_to_save <= PC_SUB_SIZE_IN + x"10" + x"8"; -- addition for subevent headers and subsubevent - end if; -end process SUB_SIZE_TO_SAVE_PROC; - -SHF_DATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - case (save_sub_hdr_current_state) is - - when IDLE => - shf_data <= x"ac"; - - when SAVE_SIZE => - shf_data <= sub_size_to_save(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); - - when SAVE_DECODING => - if (PC_INSERT_TTYPE_IN = '0') then - shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); - else - if (sub_int_ctr = 0) then - shf_data(3 downto 0) <= PC_DECODING_IN(3 downto 0); - shf_data(7 downto 4) <= PC_TRIGGER_TYPE_IN; - else - shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); - end if; - end if; - - when SAVE_ID => - shf_data <= PC_EVENT_ID_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); - - when SAVE_TRG_NR => - shf_data <= PC_TRIG_NR_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8); - - when others => shf_data <= x"00"; - - end case; - end if; -end process SHF_DATA_PROC; - ---******* --- queue sizes - -QUEUE_SIZE_FIFO : fifo_512x32x8 -port map( - Data => qsf_data, - WrClock => CLK, - RdClock => CLK, - WrEn => qsf_wr, - RdEn => qsf_rd_en, - Reset => RESET, - RPReset => RESET, - Q => qsf_q, - Empty => qsf_empty, - Full => qsf_full -); - -qsf_wr <= qsf_wr_en_qqq or qsf_wr_en_qq or qsf_wr_en_q; - -QSF_DATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - -- queue size is saved twice in a row to facilitate readout and packet construction - if (qsf_wr_en = '1' or qsf_wr_en_q = '1') then - if (qsf_wr_en = '1' and qsf_wr_en_q = '0') then - qsf_data(7) <= padding_needed; - qsf_data(6 downto 0) <= (others => '0'); - else - qsf_data(7 downto 0) <= queue_size(31 downto 24); - end if; - qsf_data(15 downto 8) <= queue_size(23 downto 16); - qsf_data(23 downto 16) <= queue_size(15 downto 8); - qsf_data(31 downto 24) <= queue_size(7 downto 0); - elsif (qsf_wr_en_qq = '1') then - qsf_data(7 downto 0) <= PC_QUEUE_DEC_IN(31 downto 24); - qsf_data(15 downto 8) <= PC_QUEUE_DEC_IN(23 downto 16); - qsf_data(23 downto 16) <= PC_QUEUE_DEC_IN(15 downto 8); - qsf_data(31 downto 24) <= PC_QUEUE_DEC_IN(7 downto 0); - else - qsf_data <= (others => '1'); - end if; - end if; -end process QSF_DATA_PROC; - -QSF_WR_PROC : process(CLK) -begin - if rising_edge(CLK) then - qsf_wr_en_q <= qsf_wr_en; - qsf_wr_en_qq <= qsf_wr_en_q; - qsf_wr_en_qqq <= qsf_wr_en_qq; - - qsf_wr_en <= PC_END_OF_QUEUE_IN; - end if; -end process QSF_WR_PROC; - -QUEUE_SIZE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - queue_size <= x"0000_0008"; -- queue headers - elsif rising_edge(CLK) then - if (qsf_wr_en_qqq = '1') then - queue_size <= x"0000_0008"; - elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then - if (PC_SUB_SIZE_IN(2) = '1') then - queue_size <= queue_size + PC_SUB_SIZE_IN + x"4" + x"10" + x"8"; -- subevent data size + padding + subevent headers + subsubevent - else - queue_size <= queue_size + PC_SUB_SIZE_IN + x"10" + x"8"; -- subevent data size + subevent headers + subsubevent - end if; - else - queue_size <= queue_size; - end if; - end if; -end process QUEUE_SIZE_PROC; - -process(CLK) -begin - if rising_edge(CLK) then - if (PC_START_OF_SUB_IN = '1') then - padding_needed <= '0'; - elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then - if (PC_SUB_SIZE_IN(2) = '1') then - padding_needed <= '1'; - else - padding_needed <= '0'; - end if; - else - padding_needed <= padding_needed; - end if; - end if; -end process; - ---******* --- LOADING PART ---******* - -LOAD_MACHINE_PROC : process(RESET, CLK) is -begin - if RESET = '1' then - load_current_state <= IDLE; - elsif rising_edge(CLK) then - load_current_state <= load_next_state; - end if; -end process LOAD_MACHINE_PROC; - -LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod_q, term_ctr, insert_padding, loaded_queue_bytes, actual_q_size) -begin - case (load_current_state) is - - when IDLE => - if (qsf_empty = '0') then -- something in queue sizes fifo means entire queue is waiting - load_next_state <= GET_Q_SIZE; - else - load_next_state <= IDLE; - end if; - - when GET_Q_SIZE => - if (header_ctr = 0) then - load_next_state <= START_TRANSFER; - else - load_next_state <= GET_Q_SIZE; - end if; - - when START_TRANSFER => - load_next_state <= LOAD_Q_HEADERS; - - when LOAD_Q_HEADERS => - if (header_ctr = 0) then - load_next_state <= LOAD_SUB; - else - load_next_state <= LOAD_Q_HEADERS; - end if; - - when LOAD_SUB => - if (header_ctr = 0) then - load_next_state <= LOAD_DATA; - else - load_next_state <= LOAD_SUB; - end if; - - when LOAD_DATA => - if (load_eod_q = '1' and term_ctr = 33) then - if (insert_padding = '1') then - load_next_state <= LOAD_PADDING; - else - if (loaded_queue_bytes = actual_q_size) then - load_next_state <= LOAD_TERM; - else - load_next_state <= LOAD_SUB; - end if; - end if; - else - load_next_state <= LOAD_DATA; - end if; - - when LOAD_PADDING => - if (header_ctr = 0) then - if (loaded_queue_bytes = actual_q_size) then - load_next_state <= LOAD_TERM; - else - load_next_state <= LOAD_SUB; - end if; - else - load_next_state <= LOAD_PADDING; - end if; - - when LOAD_TERM => - if (header_ctr = 0) then - load_next_state <= CLEANUP; - else - load_next_state <= LOAD_TERM; - end if; - - when CLEANUP => - load_next_state <= IDLE; - - end case; -end process LOAD_MACHINE; - -process(CLK) -begin - if rising_edge(CLK) then - load_eod_q <= load_eod; - end if; -end process; - -HEADER_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = IDLE) then - header_ctr <= 3; - elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then - header_ctr <= 8; - elsif (load_current_state = LOAD_Q_HEADERS and header_ctr = 0) then - header_ctr <= 15; - elsif (load_current_state = LOAD_SUB and header_ctr = 0) then - if (insert_padding = '1') then - header_ctr <= 3; - else - header_ctr <= 31; - end if; - elsif (load_current_state = LOAD_PADDING and header_ctr = 0) then - if (loaded_queue_bytes = actual_q_size) then - header_ctr <= 31; - else - header_ctr <= 15; - end if; - elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes = actual_q_size and insert_padding = '0') then - header_ctr <= 31; - elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '0') then - header_ctr <= 15; - elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '1') then - header_ctr <= 3; - elsif (load_current_state = LOAD_TERM and header_ctr = 0) then - header_ctr <= 3; - elsif (TC_RD_EN_IN = '1') then - if (load_current_state = LOAD_Q_HEADERS or load_current_state = LOAD_TERM or load_current_state = LOAD_PADDING) then - if (load_current_state = LOAD_TERM) then - if (block_term_after_divide = '1') then - header_ctr <= 31; - else - header_ctr <= header_ctr - 1; - end if; - else - header_ctr <= header_ctr - 1; - end if; - elsif (load_current_state = LOAD_SUB and block_shf_after_divide = '0') then - header_ctr <= header_ctr - 1; - else - header_ctr <= header_ctr; - end if; - elsif (load_current_state = GET_Q_SIZE) then - header_ctr <= header_ctr - 1; - else - header_ctr <= header_ctr; - end if; - end if; -end process HEADER_CTR_PROC; - -SIZE_FOR_PADDING_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = IDLE) then - insert_padding <= '0'; - elsif (load_current_state = LOAD_SUB and header_ctr = 12) then - insert_padding <= shf_padding; - else - insert_padding <= insert_padding; - end if; - end if; -end process SIZE_FOR_PADDING_PROC; - -TC_SOD_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = START_TRANSFER) then - TC_SOD_OUT <= '1'; - else - TC_SOD_OUT <= '0'; - end if; - end if; -end process TC_SOD_PROC; - -process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = IDLE) then - loaded_queue_bytes <= (others => '0'); - elsif (TC_RD_EN_IN = '1') then - loaded_queue_bytes <= loaded_queue_bytes + x"1"; - else - loaded_queue_bytes <= loaded_queue_bytes; - end if; - end if; -end process; - ---***** --- read from fifos - -df_rd_en <= '1' when (load_current_state = LOAD_DATA and TC_RD_EN_IN = '1' and load_eod_q = '0') or - (load_current_state = LOAD_SUB and header_ctr = 0 and TC_RD_EN_IN = '1') - else '0'; - -shf_rd_en <= '1' when (load_current_state = LOAD_SUB and TC_RD_EN_IN = '1' and header_ctr /= 0 and block_shf_after_divide = '0') or - (load_current_state = LOAD_Q_HEADERS and header_ctr = 0 and TC_RD_EN_IN = '1') or - (load_current_state = LOAD_DATA and load_eod_q = '1' and (loaded_queue_bytes /= actual_q_size) and (loaded_queue_bytes + x"4" /= actual_q_size)) - else '0'; - - --- nasty workaround for the case when the packet is divided on LOAD_SUB state -process(CLK) -begin - if rising_edge(CLK) then - previous_tc_rd <= TC_RD_EN_IN; - end if; -end process; -block_shf_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 15 else '0'; -block_term_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 31 else '0'; - -QUEUE_FIFO_RD_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = GET_Q_SIZE and header_ctr /= 0) then - qsf_rd_en_q <= '1'; - elsif (load_current_state = IDLE and qsf_empty = '0') then - qsf_rd_en_q <= '1'; - else - qsf_rd_en_q <= '0'; - end if; - end if; -end process QUEUE_FIFO_RD_PROC; - -qsf_rd_en <= '1' when load_current_state = LOAD_Q_HEADERS and TC_RD_EN_IN = '1' and header_ctr /= 0 else qsf_rd_en_q; - -ACTUAL_Q_SIZE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = START_TRANSFER) then - actual_q_size(7 downto 0) <= qsf_q; - elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then - actual_q_size(15 downto 8) <= qsf_q; - end if; - end if; -end process ACTUAL_Q_SIZE_PROC; - -TC_EVENT_SIZE_OUT <= actual_q_size; -- queue size without termination - -TERMINATION_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = IDLE) then - termination(255 downto 8) <= (others => '0'); - elsif (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then - termination(255 downto 8) <= termination(247 downto 0); - else - termination(255 downto 8) <= termination(255 downto 8); - end if; - end if; -end process TERMINATION_PROC; - -term_bits_gen : for I in 0 to 7 generate - process(CLK) - begin - if rising_edge(CLK) then - if (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then - case (load_current_state) is - when LOAD_Q_HEADERS => termination(I) <= qsf_q(I); - when LOAD_SUB => termination(I) <= shf_q(I); - when LOAD_DATA => termination(I) <= df_q(I); - when others => termination(I) <= '0'; - end case; - else - termination(I) <= termination(I); - end if; - end if; - end process; -end generate term_bits_gen; - -TERM_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = IDLE) then - term_ctr <= 0; - elsif (TC_RD_EN_IN = '1' and term_ctr /= 33) then - term_ctr <= term_ctr + 1; - end if; - end if; -end process TERM_CTR_PROC; - -TC_DATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - case (load_current_state) is - when LOAD_Q_HEADERS => tc_data <= qsf_q; - when LOAD_SUB => tc_data <= shf_q; - when LOAD_DATA => tc_data <= df_q; - when LOAD_PADDING => tc_data <= x"aa"; - when LOAD_TERM => tc_data <= termination((header_ctr + 1) * 8 - 1 downto header_ctr * 8); - when others => tc_data <= x"cc"; - end case; - end if; -end process TC_DATA_PROC; - -TC_DATA_OUT(7 downto 0) <= tc_data; -TC_DATA_8_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = LOAD_TERM and header_ctr = 0) then - TC_DATA_OUT(8) <= '1'; - else - TC_DATA_OUT(8) <= '0'; - end if; - end if; -end process TC_DATA_8_PROC; - ---***** --- outputs - - - -DEBUG_OUT <= (others => '0'); - -end architecture RTL; diff --git a/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd b/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd deleted file mode 100755 index 9120ba0..0000000 --- a/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd +++ /dev/null @@ -1,630 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_frame_constr is -port( - -- ports for user logic - RESET : in std_logic; - CLK : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - -- - WR_EN_IN : in std_logic; - DATA_IN : in std_logic_vector(7 downto 0); - START_OF_DATA_IN : in std_logic; - END_OF_DATA_IN : in std_logic; - IP_F_SIZE_IN : in std_logic_vector(15 downto 0); - UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation - HEADERS_READY_OUT : out std_logic; - READY_OUT : out std_logic; - DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - IHL_VERSION_IN : in std_logic_vector(7 downto 0); - TOS_IN : in std_logic_vector(7 downto 0); - IDENTIFICATION_IN : in std_logic_vector(15 downto 0); - FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); - TTL_IN : in std_logic_vector(7 downto 0); - PROTOCOL_IN : in std_logic_vector(7 downto 0); - FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10 - -- ports for packetTransmitter - RD_CLK : in std_logic; -- 125MHz clock!!! - FT_DATA_OUT : out std_logic_vector(8 downto 0); - FT_TX_EMPTY_OUT : out std_logic; - FT_TX_RD_EN_IN : in std_logic; - FT_START_OF_PACKET_OUT : out std_logic; - FT_TX_DONE_IN : in std_logic; - FT_TX_DISCFRM_IN : in std_logic; - - MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_frame_constr; - -architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_LINK_group"; - -component fifo_4096x9 is -port( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -attribute syn_encoding : string; - -type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION, - TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS, - SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH, - UDP_CS, SAVE_DATA, CLEANUP, DELAY); -signal constructCurrentState, constructNextState : constructStates; -signal bsm_constr : std_logic_vector(7 downto 0); -attribute syn_encoding of constructCurrentState: signal is "onehot"; - -type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP); -signal transmitCurrentState, transmitNextState : transmitStates; -attribute syn_encoding of transmitCurrentState : signal is "onehot"; - -signal bsm_trans : std_logic_vector(3 downto 0); - -signal headers_int_counter : integer range 0 to 6; -signal fpf_data : std_logic_vector(7 downto 0); -signal fpf_empty : std_logic; -signal fpf_full : std_logic; -signal fpf_wr_en : std_logic; -signal fpf_rd_en : std_logic; -signal fpf_q : std_logic_vector(8 downto 0); -signal ip_size : std_logic_vector(15 downto 0); -signal ip_checksum : std_logic_vector(31 downto 0); -signal udp_size : std_logic_vector(15 downto 0); -signal udp_checksum : std_logic_vector(15 downto 0); -signal ft_sop : std_logic; -signal put_udp_headers : std_logic; -signal ready_frames_ctr : std_logic_vector(15 downto 0); -signal sent_frames_ctr : std_logic_vector(15 downto 0); -signal debug : std_logic_vector(63 downto 0); -signal ready : std_logic; -signal headers_ready : std_logic; - -signal cur_max : integer range 0 to 10; - -signal ready_frames_ctr_q : std_logic_vector(15 downto 0); -signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10 - -signal fpf_reset : std_logic; -- gk 01.01.01 -signal link_ok_125, link_ok_q : std_logic; - --- gk 09.12.10 -signal delay_ctr : std_logic_vector(31 downto 0); -signal frame_delay_reg : std_logic_vector(31 downto 0); -signal fpf_data_q : std_logic_vector(7 downto 0); -signal fpf_wr_en_q, fpf_eod : std_logic; - -signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0); - -begin - --- Fakes -udp_checksum <= x"0000"; -- no checksum test needed ---debug <= (others => '0'); - -process(CLK) -begin - if rising_edge(CLK) then - if constructCurrentState = IDLE then - ready <= '1'; - else - ready <= '0'; - end if; - - if (constructCurrentState = SAVE_DATA) then - headers_ready <= '1'; - else - headers_ready <= '0'; - end if; - end if; -end process; ---ready <= '1' when (constructCurrentState = IDLE) --- else '0'; ---headers_ready <= '1' when (constructCurrentState = SAVE_DATA) --- else '0'; - -sizeProc: process(CLK) -- put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN) -begin - if rising_edge(CLK) then - if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then - ip_size <= IP_F_SIZE_IN + x"14" + x"8"; - udp_size <= UDP_P_SIZE_IN + x"8"; - else - ip_size <= IP_F_SIZE_IN + x"14"; - udp_size <= UDP_P_SIZE_IN; - end if; - end if; -end process sizeProc; - -ipCsProc : process(CLK) -begin - if rising_edge(CLK) then - if (constructCurrentState = IDLE) then - ip_checksum <= x"00000000"; - else - case constructCurrentState is - when DEST_MAC_ADDR => - case headers_int_counter is - when 0 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(7 downto 0); - when 1 => - ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(15 downto 8); - when 2 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(23 downto 16); - when 3 => - ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(31 downto 24); - when 4 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(7 downto 0); - when 5 => - ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(15 downto 8); - when others => null; - end case; - when SRC_MAC_ADDR => - case headers_int_counter is - when 0 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(23 downto 16); - when 1 => - ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(31 downto 24); - when 2 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IHL_VERSION_IN; - when 3 => - ip_checksum <= ip_checksum + TOS_IN; - when 4 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + ip_size(15 downto 8); - when 5 => - ip_checksum <= ip_checksum + ip_size(7 downto 0); - when others => null; - end case; - when VERSION => - if headers_int_counter = 0 then - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IDENTIFICATION_IN(7 downto 0); - end if; - when TOS_S => - if headers_int_counter = 0 then - ip_checksum <= ip_checksum + IDENTIFICATION_IN(15 downto 8); - end if; - when IP_LENGTH => - if headers_int_counter = 0 then - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + FLAGS_OFFSET_IN(15 downto 8); - elsif headers_int_counter = 1 then - ip_checksum <= ip_checksum + FLAGS_OFFSET_IN(7 downto 0); - end if; - when IDENT => - if headers_int_counter = 0 then - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + TTL_IN; - elsif headers_int_counter = 1 then - ip_checksum <= ip_checksum + PROTOCOL_IN; - end if; - -- gk 29.03.10 corrected the bug with bad checksums when sum larger than 16b - when FLAGS => - if headers_int_counter = 0 then - ip_cs_temp_right <= ip_checksum(31 downto 16); - elsif headers_int_counter = 1 then - ip_checksum(31 downto 16) <= (others => '0'); - end if; - when TTL_S => - if headers_int_counter = 0 then - ip_checksum <= ip_checksum + ip_cs_temp_right; - end if; - when PROTO => - if headers_int_counter = 0 then - ip_checksum(15 downto 0) <= ip_checksum(15 downto 0) + ip_checksum(31 downto 16); - end if; - when others => null; - end case; - end if; - end if; -end process ipCsProc; - - -constructMachineProc: process(RESET, CLK ) -begin - if RESET = '1' then - constructCurrentState <= IDLE; - elsif( rising_edge(CLK) ) then - constructCurrentState <= constructNextState; - end if; -end process constructMachineProc; - ---find next state of construct machine -constructMachine: process( constructCurrentState, delay_ctr, FRAME_DELAY_IN, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, FRAME_TYPE_IN, DEST_UDP_PORT_IN) -begin - constructNextState <= constructCurrentState; - if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0 - case constructCurrentState is - when IDLE => - if( START_OF_DATA_IN = '1' ) then - constructNextState <= DEST_MAC_ADDR; - end if; - when DEST_MAC_ADDR => - constructNextState <= SRC_MAC_ADDR; - when SRC_MAC_ADDR => - constructNextState <= FRAME_TYPE_S; - when FRAME_TYPE_S => - --if (DEST_IP_ADDRESS_IN /= x"0000_0000") then -- in case of ip frame continue with ip/udp headers - if (FRAME_TYPE_IN = x"0008") then - constructNextState <= VERSION; - else -- otherwise transmit data as pure ethernet frame - constructNextState <= SAVE_DATA; - end if; - when VERSION => - constructNextState <= TOS_S; - when TOS_S => - constructNextState <= IP_LENGTH; - when IP_LENGTH => - constructNextState <= IDENT; - when IDENT => - constructNextState <= FLAGS; - when FLAGS => - constructNextState <= TTL_S; - when TTL_S => - constructNextState <= PROTO; - when PROTO => - constructNextState <= HEADER_CS; - when HEADER_CS => - constructNextState <= SRC_IP_ADDR; - when SRC_IP_ADDR => - constructNextState <= DEST_IP_ADDR; - when DEST_IP_ADDR => - if (put_udp_headers = '1') and (DEST_UDP_PORT_IN /= x"0000") then - constructNextState <= SRC_PORT; - else - constructNextState <= SAVE_DATA; - end if; - when SRC_PORT => - constructNextState <= DEST_PORT; - when DEST_PORT => - constructNextState <= UDP_LENGTH; - when UDP_LENGTH => - constructNextState <= UDP_CS; - when UDP_CS => - constructNextState <= SAVE_DATA; - when SAVE_DATA => - if (END_OF_DATA_IN = '1') then - constructNextState <= CLEANUP; - end if; - when CLEANUP => - --constructNextState <= IDLE; - constructNextState <= DELAY; -- gk 10.12.10 IDLE; - -- gk 09.12.10 - when DELAY => - if (delay_ctr = FRAME_DELAY_IN) then - constructNextState <= IDLE; - else - constructNextState <= DELAY; - end if; - - when others => - constructNextState <= IDLE; - end case; - end if; -end process constructMachine; - --- gk 09.12.10 -delayCtrProc : process(CLK) -begin - if rising_edge(CLK) then - if (constructCurrentState = IDLE) or (constructCurrentState = CLEANUP) then - delay_ctr <= (others => '0'); - elsif (constructCurrentState = DELAY) then - delay_ctr <= delay_ctr + x"1"; - end if; - - frame_delay_reg <= FRAME_DELAY_IN; - end if; -end process delayCtrProc; - - -bsmConstrProc : process(constructCurrentState) -begin ---find maximum time in each state & set state bits - case constructCurrentState is - when IDLE => cur_max <= 0; bsm_constr <= x"01"; - when DEST_MAC_ADDR => cur_max <= 5; bsm_constr <= x"02"; - when SRC_MAC_ADDR => cur_max <= 5; bsm_constr <= x"03"; - when FRAME_TYPE_S => cur_max <= 1; bsm_constr <= x"04"; - when VERSION => cur_max <= 0; bsm_constr <= x"05"; - when TOS_S => cur_max <= 0; bsm_constr <= x"06"; - when IP_LENGTH => cur_max <= 1; bsm_constr <= x"07"; - when IDENT => cur_max <= 1; bsm_constr <= x"08"; - when FLAGS => cur_max <= 1; bsm_constr <= x"09"; - when TTL_S => cur_max <= 0; bsm_constr <= x"0a"; - when PROTO => cur_max <= 0; bsm_constr <= x"0b"; - when HEADER_CS => cur_max <= 1; bsm_constr <= x"0c"; - when SRC_IP_ADDR => cur_max <= 3; bsm_constr <= x"0d"; - when DEST_IP_ADDR => cur_max <= 3; bsm_constr <= x"0e"; - when SRC_PORT => cur_max <= 1; bsm_constr <= x"0f"; - when DEST_PORT => cur_max <= 1; bsm_constr <= x"10"; - when UDP_LENGTH => cur_max <= 1; bsm_constr <= x"11"; - when UDP_CS => cur_max <= 1; bsm_constr <= x"12"; - when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13"; - when CLEANUP => cur_max <= 0; bsm_constr <= x"14"; - when DELAY => cur_max <= 0; bsm_constr <= x"15"; - when others => cur_max <= 0; bsm_constr <= x"1f"; - end case; -end process; - - -headersIntProc : process(CLK) -begin - if rising_edge(CLK) then - if (constructCurrentState = IDLE) then - headers_int_counter <= 0; - else - if (headers_int_counter = cur_max) then - headers_int_counter <= 0; - else - headers_int_counter <= headers_int_counter + 1; - end if; - end if; - end if; -end process headersIntProc; - - - -putUdpHeadersProc : process(CLK) -begin - if rising_edge(CLK) then - if (FLAGS_OFFSET_IN(12 downto 0) = "0000000000000") then - put_udp_headers <= '1'; - else - put_udp_headers <= '0'; - end if; - end if; -end process putUdpHeadersProc; - -fpfWrEnProc : process(constructCurrentState, WR_EN_IN, LINK_OK_IN) -begin - if (LINK_OK_IN = '0') then -- gk 01.10.10 - fpf_wr_en <= '0'; - elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) and (constructCurrentState /= DELAY) then - fpf_wr_en <= '1'; - elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then - fpf_wr_en <= '1'; - else - fpf_wr_en <= '0'; - end if; -end process fpfWrEnProc; - -fpfDataProc : process(constructCurrentState, DEST_MAC_ADDRESS_IN, SRC_MAC_ADDRESS_IN, FRAME_TYPE_IN, IHL_VERSION_IN, - TOS_IN, ip_size, IDENTIFICATION_IN, FLAGS_OFFSET_IN, TTL_IN, PROTOCOL_IN, - ip_checksum, SRC_IP_ADDRESS_IN, DEST_IP_ADDRESS_IN, - SRC_UDP_PORT_IN, DEST_UDP_PORT_IN, udp_size, udp_checksum, headers_int_counter, DATA_IN) -begin - case constructCurrentState is - when IDLE => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when DEST_MAC_ADDR => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when SRC_MAC_ADDR => fpf_data <= SRC_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when FRAME_TYPE_S => fpf_data <= FRAME_TYPE_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when VERSION => fpf_data <= IHL_VERSION_IN; - when TOS_S => fpf_data <= TOS_IN; - when IP_LENGTH => fpf_data <= ip_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when IDENT => fpf_data <= IDENTIFICATION_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when FLAGS => fpf_data <= FLAGS_OFFSET_IN(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when TTL_S => fpf_data <= TTL_IN; - when PROTO => fpf_data <= PROTOCOL_IN; - when HEADER_CS => fpf_data <= x"ff" - ip_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when SRC_IP_ADDR => fpf_data <= SRC_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when DEST_IP_ADDR => fpf_data <= DEST_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when SRC_PORT => fpf_data <= SRC_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when DEST_PORT => fpf_data <= DEST_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when UDP_LENGTH => fpf_data <= udp_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when SAVE_DATA => fpf_data <= DATA_IN; - when CLEANUP => fpf_data <= x"ab"; - when DELAY => fpf_data <= x"ac"; - when others => fpf_data <= x"00"; - end case; -end process fpfDataProc; - -syncProc : process(CLK) -begin - if rising_edge(CLK) then - fpf_data_q <= fpf_data; - fpf_wr_en_q <= fpf_wr_en; - fpf_eod <= END_OF_DATA_IN; - end if; -end process syncProc; - - - -readyFramesCtrProc: process( CLK ) -begin - if rising_edge(CLK) then - if (LINK_OK_IN = '0') then -- gk 01.10.10 - ready_frames_ctr <= (others => '0'); - elsif (constructCurrentState = CLEANUP) then - ready_frames_ctr <= ready_frames_ctr + 1; - else - ready_frames_ctr <= ready_frames_ctr; - end if; - end if; -end process readyFramesCtrProc; - -fpfResetProc : process(CLK) -begin - if rising_edge(CLK) then - if (LINK_OK_IN = '0') then - fpf_reset <= '1'; - else - fpf_reset <= '0'; - end if; - end if; -end process fpfResetProc; ---fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10 - -FINAL_PACKET_FIFO: fifo_4096x9 -port map( - Data(7 downto 0) => fpf_data_q, - Data(8) => fpf_eod, --END_OF_DATA_IN, - WrClock => CLK, - RdClock => RD_CLK, - WrEn => fpf_wr_en_q, - RdEn => fpf_rd_en, --FT_TX_RD_EN_IN, - Reset => fpf_reset, - RPReset => fpf_reset, - Q => fpf_q, - Empty => fpf_empty, - Full => fpf_full -); - ---fpf_rd_en <= FT_TX_RD_EN_IN; -fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1')) - or (link_ok_125 = '0') -- clear the fifo if link is down - else '0'; - -transferToRdClock : signal_sync - generic map( - DEPTH => 2, - WIDTH => 16 - ) - port map( - RESET => RESET, - D_IN => ready_frames_ctr, - CLK0 => RD_CLK, --CLK, - CLK1 => RD_CLK, - D_OUT => ready_frames_ctr_q - ); - -process(RD_CLK) -begin - if rising_edge(RD_CLK) then - link_ok_q <= LINK_OK_IN; - link_ok_125 <= link_ok_q; - end if; -end process; - -transmitMachineProc: process( RD_CLK ) -begin - if RESET = '1' then - transmitCurrentState <= T_IDLE; - elsif( rising_edge(RD_CLK) ) then - if (link_ok_125 = '0') then -- gk 01.10.10 - transmitCurrentState <= T_IDLE; - else - transmitCurrentState <= transmitNextState; - end if; - end if; -end process transmitMachineProc; - -transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, link_ok_125, ready_frames_ctr_q, FT_TX_DISCFRM_IN ) -begin - case transmitCurrentState is - when T_IDLE => - bsm_trans <= x"0"; - if( (sent_frames_ctr /= ready_frames_ctr_q) ) then - transmitNextState <= T_LOAD; - else - transmitNextState <= T_IDLE; - end if; - when T_LOAD => - bsm_trans <= x"1"; - if( fpf_q(8) = '1' ) then - transmitNextState <= T_TRANSMIT; - else - transmitNextState <= T_LOAD; - end if; - when T_TRANSMIT => - bsm_trans <= x"2"; - -- gk 03.08.10 - if ((link_ok_125 = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then - transmitNextState <= T_CLEANUP; - elsif (link_ok_125 = '0') then - transmitNextState <= T_PAUSE; - else - transmitNextState <= T_TRANSMIT; - end if; - when T_PAUSE => - transmitNextState <= T_CLEANUP; - when T_CLEANUP => - bsm_trans <= x"3"; - transmitNextState <= T_IDLE; - when others => - bsm_trans <= x"f"; - transmitNextState <= T_IDLE; - end case; -end process transmitMachine; - - - -sopProc: process( RD_CLK ) -begin - if rising_edge(RD_CLK) then - if (link_ok_125 = '0') then -- gk 01.10.10 - ft_sop <= '0'; - elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then - ft_sop <= '1'; - else - ft_sop <= '0'; - end if; - end if; -end process sopProc; - -sentFramesCtrProc: process( RD_CLK ) -begin - if rising_edge(RD_CLK) then - if (LINK_OK_IN = '0') then -- gk 01.10.10 - sent_frames_ctr <= (others => '0'); - mon_sent_frames <= (others => '0'); - elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then - sent_frames_ctr <= sent_frames_ctr + 1; - mon_sent_frames <= mon_sent_frames + x"1"; - else - sent_frames_ctr <= sent_frames_ctr; - mon_sent_frames <= mon_sent_frames; - end if; - end if; -end process sentFramesCtrProc; - - - -FT_DATA_OUT <= fpf_q; -FT_TX_EMPTY_OUT <= fpf_empty; -FT_START_OF_PACKET_OUT <= ft_sop; -READY_OUT <= ready; -HEADERS_READY_OUT <= headers_ready; - - -MONITOR_TX_BYTES_OUT <= mon_sent_bytes; -MONITOR_TX_FRAMES_OUT <= mon_sent_frames; - -process(RD_CLK) -begin - if rising_edge(RD_CLK) then - if (LINK_OK_IN = '0') then - mon_sent_bytes <= (others => '0'); - elsif (fpf_rd_en = '1') then - mon_sent_bytes <= mon_sent_bytes + x"1"; - else - mon_sent_bytes <= mon_sent_bytes; - end if; - end if; -end process; - -end trb_net16_gbe_frame_constr; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd b/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd deleted file mode 100644 index 7a0c2d4..0000000 --- a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd +++ /dev/null @@ -1,756 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- here all frame checking has to be done, if the frame fits into protocol standards --- if so FR_FRAME_VALID_OUT is asserted after having received all bytes of a frame --- otherwise, after receiving all bytes, FR_FRAME_VALID_OUT keeps low and the fifo is cleared --- also a part of addresses assignemt has to be done here - -entity trb_net16_gbe_frame_receiver is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - LINK_OK_IN : in std_logic; - ALLOW_RX_IN : in std_logic; - RX_MAC_CLK : in std_logic; -- receiver serdes clock - --- input signals from TS_MAC - MAC_RX_EOF_IN : in std_logic; - MAC_RX_ER_IN : in std_logic; - MAC_RXD_IN : in std_logic_vector(7 downto 0); - MAC_RX_EN_IN : in std_logic; - MAC_RX_FIFO_ERR_IN : in std_logic; - MAC_RX_FIFO_FULL_OUT : out std_logic; - MAC_RX_STAT_EN_IN : in std_logic; - MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); - --- output signal to control logic - FR_Q_OUT : out std_logic_vector(8 downto 0); - FR_RD_EN_IN : in std_logic; - FR_FRAME_VALID_OUT : out std_logic; - FR_GET_FRAME_IN : in std_logic; - FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); - FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); - FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0); - FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0); - FR_VLAN_ID_IN : in std_logic_vector(31 downto 0); - - FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - - MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); - MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_frame_receiver; - - -architecture trb_net16_gbe_frame_receiver of trb_net16_gbe_frame_receiver is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_frame_receiver : architecture is "GBE_LINK_group"; - -attribute syn_encoding : string; -type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME, REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP); -signal filter_current_state, filter_next_state : filter_states; -attribute syn_encoding of filter_current_state : signal is "onehot"; - -signal fifo_wr_en : std_logic; -signal rx_bytes_ctr : std_logic_vector(15 downto 0); -signal frame_valid_q : std_logic; -signal delayed_frame_valid : std_logic; -signal delayed_frame_valid_q : std_logic; - -signal rec_fifo_empty : std_logic; -signal rec_fifo_full : std_logic; -signal sizes_fifo_full : std_logic; -signal sizes_fifo_empty : std_logic; - -signal remove_ctr : std_logic_vector(7 downto 0); -signal new_frame : std_logic; -signal new_frame_lock : std_logic := '0'; -signal saved_frame_type : std_logic_vector(15 downto 0); -signal saved_vid : std_logic_vector(15 downto 0) := (others => '0'); -signal saved_src_mac : std_logic_vector(47 downto 0); -signal saved_dest_mac : std_logic_vector(47 downto 0); -signal frame_type_valid : std_logic; -signal saved_proto : std_logic_vector(7 downto 0); -signal saved_src_ip : std_logic_vector(31 downto 0); -signal saved_dest_ip : std_logic_vector(31 downto 0); -signal saved_src_udp : std_logic_vector(15 downto 0); -signal saved_dest_udp : std_logic_vector(15 downto 0); - -signal dump : std_logic_vector(7 downto 0); -signal dump2 : std_logic_vector(7 downto 0); - -signal error_frames_ctr : std_logic_vector(15 downto 0); - --- debug signals -signal dbg_rec_frames : std_logic_vector(31 downto 0); -signal dbg_drp_frames : std_logic_vector(31 downto 0); -signal state : std_logic_vector(3 downto 0); - -signal rx_data, fr_q : std_logic_vector(8 downto 0); - -signal fr_src_ip, fr_dest_ip : std_logic_vector(31 downto 0); -signal fr_dest_udp, fr_src_udp, fr_frame_size, fr_frame_proto : std_logic_vector(15 downto 0); -signal fr_dest_mac, fr_src_mac : std_logic_vector(47 downto 0); -signal fr_ip_proto : std_logic_vector(7 downto 0); -signal mon_rec_bytes : std_logic_vector(31 downto 0); - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true; -attribute syn_preserve of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true; - -begin - --- new_frame is asserted when first byte of the frame arrives -NEW_FRAME_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (LINK_OK_IN = '0' or MAC_RX_EOF_IN = '1') then - new_frame <= '0'; - new_frame_lock <= '0'; - elsif (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') then - new_frame <= '1'; - new_frame_lock <= '1'; - else - new_frame <= '0'; - new_frame_lock <= new_frame_lock; - end if; - end if; -end process NEW_FRAME_PROC; - - -FILTER_MACHINE_PROC : process(RX_MAC_CLK, RESET) -begin - if RESET = '1' then - filter_current_state <= IDLE; - elsif rising_edge(RX_MAC_CLK) then --- if (RESET = '1') then --- filter_current_state <= IDLE; --- else - filter_current_state <= filter_next_state; --- end if; - end if; -end process FILTER_MACHINE_PROC; - -FILTER_MACHINE : process(filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, g_MY_MAC, saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN) -begin - - case filter_current_state is - - when IDLE => - state <= x"1"; - if (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') then - filter_next_state <= REMOVE_DEST; - else - filter_next_state <= IDLE; - end if; - - -- frames arrive without preamble! - when REMOVE_DEST => - state <= x"3"; - if (remove_ctr = x"03") then -- counter starts with a delay that's why only 3 - -- destination MAC address filtering here - if (saved_dest_mac = g_MY_MAC) or (saved_dest_mac = x"ffffffffffff") then -- must accept broadcasts for ARP - filter_next_state <= REMOVE_SRC; - else - filter_next_state <= DECIDE; - end if; - else - filter_next_state <= REMOVE_DEST; - end if; - - when REMOVE_SRC => - state <= x"4"; - if (remove_ctr = x"09") then - filter_next_state <= REMOVE_TYPE; - else - filter_next_state <= REMOVE_SRC; - end if; - - when REMOVE_TYPE => - state <= x"5"; - if (remove_ctr = x"0b") then - if (saved_frame_type = x"8100") then -- VLAN tagged frame - filter_next_state <= REMOVE_VID; - else -- no VLAN tag - if (saved_frame_type = x"0800") then -- in case of IP continue removing headers - filter_next_state <= REMOVE_IP; - else - filter_next_state <= DECIDE; - end if; - end if; - else - filter_next_state <= REMOVE_TYPE; - end if; - - when REMOVE_VID => - state <= x"a"; - if (remove_ctr = x"0d") then - filter_next_state <= REMOVE_VTYPE; - else - filter_next_state <= REMOVE_VID; - end if; - - when REMOVE_VTYPE => - state <= x"b"; - if (remove_ctr = x"0f") then - if (saved_frame_type = x"0800") then -- in case of IP continue removing headers - filter_next_state <= REMOVE_IP; - else - filter_next_state <= DECIDE; - end if; - else - filter_next_state <= REMOVE_VTYPE; - end if; - - when REMOVE_IP => - state <= x"c"; - if (remove_ctr = x"11") then - if (saved_proto = x"11") then -- forced to recognize udp only, TODO check all protocols - filter_next_state <= REMOVE_UDP; - else - filter_next_state <= DECIDE; -- changed from drop - end if; - else - filter_next_state <= REMOVE_IP; - end if; - - when REMOVE_UDP => - state <= x"d"; - if (remove_ctr = x"19") then - filter_next_state <= DECIDE; - else - filter_next_state <= REMOVE_UDP; - end if; - - when DECIDE => - state <= x"6"; - if (frame_type_valid = '1') then - filter_next_state <= SAVE_FRAME; - elsif (saved_frame_type = x"0806") then - filter_next_state <= SAVE_FRAME; - else - filter_next_state <= DROP_FRAME; - end if; - - when SAVE_FRAME => - state <= x"7"; - if (MAC_RX_EOF_IN = '1') then - filter_next_state <= CLEANUP; - else - filter_next_state <= SAVE_FRAME; - end if; - - when DROP_FRAME => - state <= x"8"; - if (MAC_RX_EOF_IN = '1') then - filter_next_state <= CLEANUP; - else - filter_next_state <= DROP_FRAME; - end if; - - when CLEANUP => - state <= x"9"; - filter_next_state <= IDLE; - - when others => null; - - end case; -end process; - --- counts the bytes to be removed from the ethernet headers fields -REMOVE_CTR_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = IDLE) or - (filter_current_state = REMOVE_VTYPE and remove_ctr = x"0f") or - (filter_current_state = REMOVE_TYPE and remove_ctr = x"0b") then - - remove_ctr <= (others => '1'); - elsif (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) then --and (filter_current_state /= CLEANUP) then - remove_ctr <= remove_ctr + x"1"; - else - remove_ctr <= remove_ctr; - end if; - end if; -end process REMOVE_CTR_PROC; - -SAVED_PROTO_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_proto <= (others => '0'); - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") then - saved_proto <= MAC_RXD_IN; - else - saved_proto <= saved_proto; - end if; - end if; -end process SAVED_PROTO_PROC; - -SAVED_SRC_IP_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_src_ip <= (others => '0'); - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") then - saved_src_ip(7 downto 0) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") then - saved_src_ip(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") then - saved_src_ip(23 downto 16) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") then - saved_src_ip(31 downto 24) <= MAC_RXD_IN; - else - saved_src_ip <= saved_src_ip; - end if; - end if; -end process SAVED_SRC_IP_PROC; - -SAVED_DEST_IP_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_dest_ip <= (others => '0'); - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") then - saved_dest_ip(7 downto 0) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") then - saved_dest_ip(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") then - saved_dest_ip(23 downto 16) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") then - saved_dest_ip(31 downto 24) <= MAC_RXD_IN; - else - saved_dest_ip <= saved_dest_ip; - end if; - end if; -end process SAVED_DEST_IP_PROC; - -SAVED_SRC_UDP_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_src_udp <= (others => '0'); - elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") then - saved_src_udp(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") then - saved_src_udp(7 downto 0) <= MAC_RXD_IN; - else - saved_src_udp <= saved_src_udp; - end if; - end if; -end process SAVED_SRC_UDP_PROC; - -SAVED_DEST_UDP_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_dest_udp <= (others => '0'); - elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") then - saved_dest_udp(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") then - saved_dest_udp(7 downto 0) <= MAC_RXD_IN; - else - saved_dest_udp <= saved_dest_udp; - end if; - end if; -end process SAVED_DEST_UDP_PROC; - --- saves the destination mac address of the incoming frame -SAVED_DEST_MAC_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_dest_mac <= (others => '0'); - elsif (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') then - saved_dest_mac(7 downto 0) <= MAC_RXD_IN; - elsif (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') then - saved_dest_mac(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") then - saved_dest_mac(23 downto 16) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") then - saved_dest_mac(31 downto 24) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") then - saved_dest_mac(39 downto 32) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") then - saved_dest_mac(47 downto 40) <= MAC_RXD_IN; - else - saved_dest_mac <= saved_dest_mac; - end if; - end if; -end process SAVED_DEST_MAC_PROC; - --- saves the source mac address of the incoming frame -SAVED_SRC_MAC_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_src_mac <= (others => '0'); - elsif (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") then - saved_src_mac(7 downto 0) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") then - saved_src_mac(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") then - saved_src_mac(23 downto 16) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") then - saved_src_mac(31 downto 24) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") then - saved_src_mac(39 downto 32) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") then - saved_src_mac(47 downto 40) <= MAC_RXD_IN; - else - saved_src_mac <= saved_src_mac; - end if; - end if; -end process SAVED_SRC_MAC_PROC; - --- saves the frame type of the incoming frame for futher check -SAVED_FRAME_TYPE_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_frame_type <= (others => '0'); - elsif (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") then - saved_frame_type(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") then - saved_frame_type(7 downto 0) <= MAC_RXD_IN; - -- two more cases for VLAN tagged frame - elsif (filter_current_state = REMOVE_VID) and (remove_ctr = x"0d") then - saved_frame_type(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0e") then - saved_frame_type(7 downto 0) <= MAC_RXD_IN; - else - saved_frame_type <= saved_frame_type; - end if; - end if; -end process SAVED_FRAME_TYPE_PROC; - --- saves VLAN id when tagged frame spotted -SAVED_VID_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (filter_current_state = CLEANUP) then - saved_vid <= (others => '0'); - elsif (filter_current_state = REMOVE_TYPE and remove_ctr = x"0b" and saved_frame_type = x"8100") then - saved_vid(15 downto 8) <= MAC_RXD_IN; - elsif (filter_current_state = REMOVE_VID and remove_ctr = x"0c") then - saved_vid(7 downto 0) <= MAC_RXD_IN; - else - saved_vid <= saved_vid; - end if; - end if; -end process SAVED_VID_PROC; - -type_validator : trb_net16_gbe_type_validator -port map( - CLK => RX_MAC_CLK, - RESET => RESET, - FRAME_TYPE_IN => saved_frame_type, - SAVED_VLAN_ID_IN => saved_vid, - ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN, - VLAN_ID_IN => FR_VLAN_ID_IN, - - -- IP level - IP_PROTOCOLS_IN => saved_proto, - ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN, - - -- UDP level - UDP_PROTOCOL_IN => saved_dest_udp, - ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN, - - VALID_OUT => frame_type_valid -); - -receive_fifo : fifo_4096x9 -port map( --- Data(7 downto 0) => MAC_RXD_IN, --- Data(8) => MAC_RX_EOF_IN, - Data => rx_data, - WrClock => RX_MAC_CLK, - RdClock => CLK, - WrEn => fifo_wr_en, - RdEn => FR_RD_EN_IN, - Reset => RESET, - RPReset => RESET, - Q => fr_q, --FR_Q_OUT, - Empty => rec_fifo_empty, - Full => rec_fifo_full -); - --- BUG HERE, probably more lost bytes in the fifo in other conditions ---fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or --- --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or --- ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or --- (filter_current_state = DECIDE and frame_type_valid = '1'))) --- else '0'; - -RX_FIFO_SYNC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - - rx_data(8) <= MAC_RX_EOF_IN; - rx_data(7 downto 0) <= MAC_RXD_IN; - - if (MAC_RX_EN_IN = '1') then - if (filter_current_state = SAVE_FRAME) then - fifo_wr_en <= '1'; - elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then - fifo_wr_en <= '1'; - elsif (filter_current_state = DECIDE and frame_type_valid = '1') then - fifo_wr_en <= '1'; - else - fifo_wr_en <= '0'; - end if; - else - fifo_wr_en <= '0'; - end if; - - MAC_RX_FIFO_FULL_OUT <= rec_fifo_full; - end if; -end process RX_FIFO_SYNC; - - - -sizes_fifo : fifo_512x32 -port map( - Data(15 downto 0) => rx_bytes_ctr, - Data(31 downto 16) => saved_frame_type, - WrClock => RX_MAC_CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(15 downto 0) => fr_frame_size, --FR_FRAME_SIZE_OUT, - Q(31 downto 16) => fr_frame_proto, --FR_FRAME_PROTO_OUT, - Empty => sizes_fifo_empty, - Full => sizes_fifo_full -); - -macs_fifo : fifo_512x72 -port map( - Data(47 downto 0) => saved_src_mac, - Data(63 downto 48) => saved_src_udp, - Data(71 downto 64) => (others => '0'), - WrClock => RX_MAC_CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(47 downto 0) => fr_src_mac, --FR_SRC_MAC_ADDRESS_OUT, - Q(63 downto 48) => fr_src_udp, --FR_SRC_UDP_PORT_OUT, - Q(71 downto 64) => dump2, - Empty => open, - Full => open -); - -macd_fifo : fifo_512x72 -port map( - Data(47 downto 0) => saved_dest_mac, - Data(63 downto 48) => saved_dest_udp, - Data(71 downto 64) => (others => '0'), - WrClock => RX_MAC_CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(47 downto 0) => fr_dest_mac, --FR_DEST_MAC_ADDRESS_OUT, - Q(63 downto 48) => fr_dest_udp, --FR_DEST_UDP_PORT_OUT, - Q(71 downto 64) => dump, - Empty => open, - Full => open -); - -ip_fifo : fifo_512x72 -port map( - Data(31 downto 0) => saved_src_ip, - Data(63 downto 32) => saved_dest_ip, - Data(71 downto 64) => saved_proto, - WrClock => RX_MAC_CLK, - RdClock => CLK, - WrEn => frame_valid_q, - RdEn => FR_GET_FRAME_IN, - Reset => RESET, - RPReset => RESET, - Q(31 downto 0) => fr_src_ip, --FR_SRC_IP_ADDRESS_OUT, - Q(63 downto 32) => fr_dest_ip, --FR_DEST_IP_ADDRESS_OUT, - Q(71 downto 64) => fr_ip_proto, --FR_IP_PROTOCOL_OUT, - Empty => open, - Full => open -); - -process(CLK) -begin - if rising_edge(CLK) then - FR_SRC_IP_ADDRESS_OUT <= fr_src_ip; - FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip; - FR_IP_PROTOCOL_OUT <= fr_ip_proto; - FR_DEST_UDP_PORT_OUT <= fr_dest_udp; - FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac; - FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac; - FR_SRC_UDP_PORT_OUT <= fr_src_udp; - FR_FRAME_PROTO_OUT <= fr_frame_proto; - FR_FRAME_SIZE_OUT <= fr_frame_size; - FR_Q_OUT <= fr_q; - end if; -end process; - -FRAME_VALID_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (MAC_RX_EOF_IN = '1' and ALLOW_RX_IN = '1' and frame_type_valid = '1') then - frame_valid_q <= '1'; - else - frame_valid_q <= '0'; - end if; - end if; -end process FRAME_VALID_PROC; - -RX_BYTES_CTR_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (RESET = '1') or (delayed_frame_valid_q = '1') then - rx_bytes_ctr <= x"0001"; - elsif (fifo_wr_en = '1') then - rx_bytes_ctr <= rx_bytes_ctr + x"1"; - end if; - end if; -end process; - -ERROR_FRAMES_CTR_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (RESET = '1') then - error_frames_ctr <= (others => '0'); - elsif (MAC_RX_ER_IN = '1') then - error_frames_ctr <= error_frames_ctr + x"1"; - end if; - end if; -end process ERROR_FRAMES_CTR_PROC; - - -SYNC_PROC : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - delayed_frame_valid <= MAC_RX_EOF_IN; - delayed_frame_valid_q <= delayed_frame_valid; - end if; -end process SYNC_PROC; - ---***************** --- synchronization between 125MHz receive clock and 100MHz system clock -FRAME_VALID_SYNC : pulse_sync -port map( - CLK_A_IN => RX_MAC_CLK, - RESET_A_IN => RESET, - PULSE_A_IN => frame_valid_q, - CLK_B_IN => CLK, - RESET_B_IN => RESET, - PULSE_B_OUT => FR_FRAME_VALID_OUT -); - - --- **** --- debug counters, to be removed later -RECEIVED_FRAMES_CTR : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (RESET = '1') then - dbg_rec_frames <= (others => '0'); - elsif (MAC_RX_EOF_IN = '1') then - dbg_rec_frames <= dbg_rec_frames + x"1"; - end if; - end if; -end process RECEIVED_FRAMES_CTR; - -DROPPED_FRAMES_CTR : process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (RESET = '1') then - dbg_drp_frames <= (others => '0'); - elsif (filter_current_state = DECIDE and frame_type_valid = '0') then - dbg_drp_frames <= dbg_drp_frames + x"1"; - end if; - end if; -end process DROPPED_FRAMES_CTR; - -sync1 : signal_sync -generic map ( - WIDTH => 32, - DEPTH => 2 -) -port map ( - RESET => RESET, - CLK0 => CLK, - CLK1 => CLK, - D_IN => dbg_drp_frames, - D_OUT => MONITOR_DROPPED_OUT -); - -sync3 : signal_sync -generic map ( - WIDTH => 32, - DEPTH => 2 -) -port map ( - RESET => RESET, - CLK0 => CLK, - CLK1 => CLK, - D_IN => dbg_rec_frames, - D_OUT => MONITOR_RX_FRAMES_OUT -); - -sync4 : signal_sync -generic map ( - WIDTH => 32, - DEPTH => 2 -) -port map ( - RESET => RESET, - CLK0 => CLK, - CLK1 => CLK, - D_IN => mon_rec_bytes, - D_OUT => MONITOR_RX_BYTES_OUT -); - -process(RX_MAC_CLK) -begin - if rising_edge(RX_MAC_CLK) then - if (RESET = '1') then - mon_rec_bytes <= (others => '0'); - elsif (fifo_wr_en = '1') then - mon_rec_bytes <= mon_rec_bytes + x"1"; - else - mon_rec_bytes <= mon_rec_bytes; - end if; - end if; -end process; - --- end of debug counters --- **** - -end trb_net16_gbe_frame_receiver; - - diff --git a/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd b/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd deleted file mode 100755 index 41db165..0000000 --- a/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd +++ /dev/null @@ -1,226 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_frame_trans is -port ( - CLK : in std_logic; - RESET : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - TX_MAC_CLK : in std_logic; - TX_EMPTY_IN : in std_logic; - START_OF_PACKET_IN : in std_logic; - DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC - - TX_FIFOAVAIL_OUT : out std_logic; - TX_FIFOEOF_OUT : out std_logic; - TX_FIFOEMPTY_OUT : out std_logic; - TX_DONE_IN : in std_logic; - TX_STAT_EN_IN : in std_logic; - TX_STATVEC_IN : in std_logic_vector(30 downto 0); - TX_DISCFRM_IN : in std_logic; - -- Debug - BSM_INIT_OUT : out std_logic_vector(3 downto 0); - BSM_MAC_OUT : out std_logic_vector(3 downto 0); - BSM_TRANS_OUT : out std_logic_vector(3 downto 0); - DBG_RD_DONE_OUT : out std_logic; - DBG_INIT_DONE_OUT : out std_logic; - DBG_ENABLED_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_frame_trans; - --- FifoRd ?!? - -architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_frame_trans : architecture is "GBE_BUF_group"; - -component mac_init_mem is -port ( - Address : in std_logic_vector(5 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0) -); -end component; - -attribute syn_encoding : string; - -type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED); -signal macInitState, macInitNextState : macInitStates; -attribute syn_encoding of macInitState: signal is "onehot"; -signal bsm_init : std_logic_vector(3 downto 0); - -type macStates is (M_RESETING, M_IDLE, M_INIT); -signal macCurrentState, macNextState : macStates; -attribute syn_encoding of macCurrentState : signal is "onehot"; -signal bsm_mac : std_logic_vector(3 downto 0); - -type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO); -signal transmitCurrentState, transmitNextState : transmitStates; -attribute syn_encoding of transmitCurrentState: signal is "onehot"; -signal bsm_trans : std_logic_vector(3 downto 0); - -signal tx_fifoavail_i : std_logic; -signal tx_fifoeof_i : std_logic; - --- host interface signals -signal hcs_n_i : std_logic; -signal hwrite_n_i : std_logic; -signal hread_n_i : std_logic; - --- MAC INITIALIZATION signals -signal macInitMemAddr : std_logic_vector(5 downto 0); -signal macInitMemQ : std_logic_vector(7 downto 0); -signal macInitMemEn : std_logic; -signal reading_done : std_logic; -signal init_done : std_logic; -signal enabled : std_logic; -signal addrSig : std_logic_vector(5 downto 0); -signal addr2 : std_logic_vector(5 downto 0); -signal resetAddr : std_logic; - -signal FifoEmpty : std_logic; -signal debug : std_logic_vector(63 downto 0); -signal sent_ctr : std_logic_vector(31 downto 0); -signal link_ok_125 : std_logic; - -begin - -linkOkSync : pulse_sync -port map( - CLK_A_IN => CLK, - RESET_A_IN => RESET, - PULSE_A_IN => LINK_OK_IN, - CLK_B_IN => TX_MAC_CLK, - RESET_B_IN => RESET, - PULSE_B_OUT => link_ok_125 -); - --- Fakes -debug(63 downto 32) <= (others => '0'); ---debug(31 downto 0) <= sent_ctr; - - -TransmitStateMachineProc : process (TX_MAC_CLK) -begin - if RESET = '1' then - transmitCurrentState <= T_IDLE; - elsif rising_edge(TX_MAC_CLK) then - if (LINK_OK_IN = '0') then -- gk 01.10.10 - transmitCurrentState <= T_IDLE; - else - transmitCurrentState <= transmitNextState; - end if; - end if; -end process TransmitStatemachineProc; - -TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN) -begin - case transmitCurrentState is - when T_IDLE => - bsm_trans <= x"0"; - if (START_OF_PACKET_IN = '1') then - transmitNextState <= T_TRANSMIT; - else - transmitNextState <= T_IDLE; - end if; - when T_TRANSMIT => - bsm_trans <= x"1"; - if (DATA_ENDFLAG_IN = '1') then - transmitNextState <= T_WAITFORFIFO; - else - transmitNextState <= T_TRANSMIT; - end if; - when T_WAITFORFIFO => - bsm_trans <= x"2"; - if (TX_DONE_IN = '1') then - transmitNextState <= T_IDLE; - else - transmitNextState <= T_WAITFORFIFO; - end if; - when others => - bsm_trans <= x"f"; - transmitNextState <= T_IDLE; - end case; -end process TransmitStateMachine; - -FifoAvailProc : process (TX_MAC_CLK) -begin - if rising_edge(TX_MAC_CLK) then - if (LINK_OK_IN = '0') then -- gk 01.10.10 - tx_fifoavail_i <= '0'; - elsif (transmitCurrentState = T_TRANSMIT) then - tx_fifoavail_i <= '1'; - else - tx_fifoavail_i <= '0'; - end if; - end if; -end process FifoAvailProc; - -FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, RESET) -begin - if (LINK_OK_IN = '0') then -- gk 01.10.10 - FifoEmpty <= '1'; - elsif (transmitCurrentState = T_WAITFORFIFO) then - FifoEmpty <= '1'; - elsif (transmitCurrentState = T_TRANSMIT) then - FifoEmpty <= TX_EMPTY_IN; - elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then - FifoEmpty <= '0'; - else - FifoEmpty <= '1'; - end if; -end process FifoEmptyProc; - -tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) - else '0'; - -SENT_CTR_PROC : process(TX_MAC_CLK) -begin - if (RESET = '1') then - sent_ctr <= (others => '0'); - elsif rising_edge(TX_MAC_CLK) then - if (TX_DONE_IN = '1') and (TX_STAT_EN_IN = '1') and (TX_STATVEC_IN(0) = '1') then - sent_ctr <= sent_ctr + x"1"; - else - sent_ctr <= sent_ctr; - end if; - end if; -end process SENT_CTR_PROC; - -sync1 : signal_sync -generic map( - WIDTH => 32, - DEPTH => 2 -) -port map ( - RESET => RESET, - CLK0 => CLK, - CLK1 => CLK, - D_IN => sent_ctr, - D_OUT => debug(31 downto 0) -); - -TX_FIFOAVAIL_OUT <= tx_fifoavail_i; -TX_FIFOEOF_OUT <= tx_fifoeof_i; -TX_FIFOEMPTY_OUT <= FifoEmpty; - -BSM_INIT_OUT <= bsm_init; -BSM_MAC_OUT <= bsm_mac; -BSM_TRANS_OUT <= bsm_trans; -DBG_RD_DONE_OUT <= reading_done; -DBG_INIT_DONE_OUT <= init_done; -DBG_ENABLED_OUT <= enabled; -DEBUG_OUT <= debug; - -end trb_net16_gbe_frame_trans; diff --git a/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd b/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd deleted file mode 100644 index 040737b..0000000 --- a/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd +++ /dev/null @@ -1,1508 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity trb_net16_ipu2gbe is -port( - CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 - MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - - SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0); - SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0); - - -- PacketConstructor interface - ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; -- gk 07.10.10 - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) -); -end entity; - -architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is - --- attribute HGROUP : string; --- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe"; - -component fifo_32kx16x8_mb2 -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - AlmostEmpty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic -); -end component; - -type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE, RESET_FIFO); -signal saveCurrentState, saveNextState : saveStates; -signal state : std_logic_vector(3 downto 0); -signal data_req_comb : std_logic; -signal data_req : std_logic; -- request data signal, will be used for fee_read generation -signal rst_saved_ctr_comb : std_logic; -signal rst_saved_ctr : std_logic; - -signal fee_read_comb : std_logic; -signal fee_read : std_logic; -- fee_read signal -signal saved_ctr : std_logic_vector(16 downto 0); -signal ce_saved_ctr : std_logic; - --- header data -signal cts_rnd : std_logic_vector(15 downto 0); -signal cts_rnd_saved : std_logic; -signal cts_trg : std_logic_vector(15 downto 0); -signal cts_trg_saved : std_logic; -signal cts_len : std_logic_vector(16 downto 0); -signal cts_len_saved : std_logic; - --- CTS interface -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal cts_length : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_data : std_logic_vector(31 downto 0); - --- Split FIFO signals -signal sf_data : std_logic_vector(15 downto 0); -signal sf_wr_en_comb : std_logic; -signal sf_wr_en : std_logic; -- write signal for FIFO -signal sf_rd_en_comb : std_logic; -signal sf_rd_en : std_logic; -- read signal for FIFO -signal sf_wcnt : std_logic_vector(15 downto 0); -signal sf_rcnt : std_logic_vector(16 downto 0); -signal sf_empty : std_logic; -signal sf_aempty : std_logic; -signal sf_full : std_logic; -signal sf_afull : std_logic; - -------------------------------------------------------------------- -type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2); -signal loadCurrentState, loadNextState : loadStates; -signal state2 : std_logic_vector(3 downto 0); - -signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data -signal rst_rem_ctr_comb : std_logic; -signal rst_rem_ctr : std_logic; -- reset the remove counter -signal rst_regs_comb : std_logic; -signal rst_regs : std_logic; -- reset storage registers -signal rem_phase_comb : std_logic; -signal rem_phase : std_logic; -- header remove phase -signal data_phase_comb : std_logic; -signal data_phase : std_logic; -- data transport phase from split fifo to PC -signal pad_phase_comb : std_logic; -signal pad_phase : std_logic; -- padding phase -signal calc_pad_comb : std_logic; -signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE -signal pad_data_comb : std_logic; -signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value - -signal pc_sos_comb : std_logic; -signal pc_sos : std_logic; -- start of data signal -signal pc_eod_comb : std_logic; -signal pc_eod : std_logic; -- end of data signal - -signal ce_rem_ctr_comb : std_logic; -signal ce_rem_ctr : std_logic; -- count enable for remove counter -signal remove_done_comb : std_logic; -signal remove_done : std_logic; -- end of header stripping process -signal read_done_comb : std_logic; -signal read_done : std_logic; -- end of data phase (read phase from SF) - -signal pc_data : std_logic_vector(7 downto 0); -signal pc_data_q : std_logic_vector(7 downto 0); -signal pc_trig_nr : std_logic_vector(15 downto 0); -signal pc_sub_size : std_logic_vector(17 downto 0); -signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo -signal padding_needed : std_logic; -signal pc_wr_en_comb : std_logic; -signal pc_wr_en_q : std_logic; -signal pc_wr_en_qq : std_logic; -signal pc_wr_en_qqq : std_logic; -signal pc_eod_q : std_logic; - -signal debug : std_logic_vector(383 downto 0); - --- gk -signal bank_select : std_logic_vector(3 downto 0); -signal save_addr_comb : std_logic; -signal save_addr : std_logic; -signal addr_saved_comb : std_logic; -signal addr_saved : std_logic; -signal start_config : std_logic; -signal config_done : std_logic; -signal add_sub_state : std_logic; -signal add_sub_state_comb : std_logic; -signal add_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub : std_logic; -signal load_sub_comb : std_logic; -signal load_sub_done : std_logic; -signal load_sub_done_comb : std_logic; -signal load_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub_ctr_comb : std_logic; -signal actual_message_size : std_logic_vector(31 downto 0); -signal more_subevents : std_logic; -signal trig_random : std_logic_vector(7 downto 0); -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_lock : std_logic; -signal pc_trig_nr_q : std_logic_vector(31 downto 0); - --- gk 20.07.10 -signal inc_data_ctr : std_logic_vector(31 downto 0); -signal dropped_sm_events_ctr : std_logic_vector(31 downto 0); -signal dropped_lr_events_ctr : std_logic_vector(31 downto 0); -signal dropped_ctr : std_logic_vector(31 downto 0); --- gk 22.07.10 -signal headers_invalid : std_logic; -signal headers_invalid_ctr : std_logic_vector(31 downto 0); -signal cts_len_q : std_logic_vector(15 downto 0); -signal cts_trg_q : std_logic_vector(15 downto 0); -signal cts_rnd_q : std_logic_vector(15 downto 0); -signal first_run_trg : std_logic_vector(15 downto 0); -signal first_run_addr : std_logic_vector(15 downto 0); -signal first_run_lock : std_logic; -signal cts_addr : std_logic_vector(15 downto 0); -signal cts_addr_q : std_logic_vector(15 downto 0); -signal cts_addr_saved : std_logic; - --- gk 24.07.10 -signal save_eod : std_logic; -signal save_eod_comb : std_logic; - -signal load_eod : std_logic; -signal endpoint_addr : std_logic_vector(15 downto 0); -signal endp_addr_lock : std_logic; - -signal saved_events_ctr : std_logic_vector(15 downto 0); -signal loaded_events_ctr : std_logic_vector(15 downto 0); -signal constr_events_ctr : std_logic_vector(31 downto 0); -signal event_waiting : std_logic; - -signal drop_sub : std_logic; -signal drop_sub_comb : std_logic; -signal drop_event : std_logic; -signal drop_event_comb : std_logic; -signal drop_small : std_logic; -signal drop_large : std_logic; -signal drop_headers : std_logic; -signal drop_small_comb : std_logic; -signal drop_large_comb : std_logic; -signal drop_headers_comb : std_logic; -signal inc_trg_ctr : std_logic; -signal inc_trg_ctr_comb : std_logic; - -signal invalid_hsize_ctr : std_logic_vector(15 downto 0); -signal invalid_hsize_lock : std_logic; - -signal load_eod_q : std_logic; -signal read_size_q : std_logic_vector(17 downto 0); - --- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked -signal sf_real_wr_en : std_logic; - --- gk 01.10.10 -signal found_empty_evt : std_logic; -signal found_empty_evt_comb : std_logic; -signal found_empty_evt_ctr : std_logic_vector(31 downto 0); - --- gk 06.10.10 -signal message_size : std_logic_vector(31 downto 0); - --- gk 07.12.10 -signal prev_bank_select : std_logic_vector(3 downto 0); -signal first_event : std_logic; - -signal reset_split_fifo : std_logic; - -signal input_data_ctr : std_logic_vector(31 downto 0); - --- SIMPLE SENDER STUFF -type gen_states is (IDLE, WAIT_FOR_PC, GENERATE_DATA, CLEANUP); -signal gen_current_state, gen_next_state : gen_states; - -signal gen_data_ctr : std_logic_vector(15 downto 0); - -begin - -BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 -START_CONFIG_OUT <= start_config; -- gk 27.03.10 -config_done <= CONFIG_DONE_IN; -- gk 29.03.10 - --- CTS interface signals -cts_error_pattern <= (others => '0'); -- FAKE - -cts_length <= x"0000"; -- length of data payload is always 0 -cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' - -cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; - -cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) - else '0'; - --- Byte swapping... done here. TAKE CARE! --- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes --- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port. --- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped --- for GbE inside the packet constructor. --- --- Long live the Endianess! - --- Sync all critical pathes -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below - sf_wr_en <= sf_wr_en_comb; - ce_rem_ctr <= ce_rem_ctr_comb; - sf_rd_en <= sf_rd_en_comb; - fee_read <= fee_read_comb; - read_done <= read_done_comb; - pc_eod_q <= pc_eod; - pc_wr_en_qqq <= pc_wr_en_qq; - pc_wr_en_qq <= pc_wr_en_q; - pc_wr_en_q <= pc_wr_en_comb; - end if; -end process THE_SYNC_PROC; - --- gk 27.03.10 data selector for sf to write the evt builder address on top of data -SF_DATA_PROC : process( CLK ) -begin - if( rising_edge(CLK) ) then - if (RESET = '1') then -- gk 31.05.10 - sf_data <= (others => '0'); - elsif( save_addr = '1' ) then - sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address - sf_data(15 downto 4) <= x"abc"; - -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent - elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then - sf_data <= x"0001"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then - sf_data <= x"5555"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then - sf_data <= FEE_STATUS_BITS_IN(31 downto 16); - elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then - sf_data <= FEE_STATUS_BITS_IN(15 downto 0); - else - sf_data <= FEE_DATA_IN; - end if; - end if; -end process SF_DATA_PROC; - --- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY -fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled - else '0'; - --- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY -sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled - (save_addr = '1') or - (add_sub_state = '1') -- gk 29.03.10 save the subsubevent - else '0'; - --- gk 06.08.10 -sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0'; - --- gk 27.03.10 do not count evt builder address as saved ipu bytes ---ce_saved_ctr <= sf_wr_en; -ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en; - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -saveMachineProc: process( CLK ) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saveCurrentState <= SIDLE; - data_req <= '0'; - rst_saved_ctr <= '0'; - save_addr <= '0'; -- gk 27.03.10 - addr_saved <= '0'; -- gk 27.03.10 - add_sub_state <= '0'; -- gk 29.03.10 - save_eod <= '0'; -- gk 25.07.10 - else - saveCurrentState <= saveNextState; - data_req <= data_req_comb; - rst_saved_ctr <= rst_saved_ctr_comb; - save_addr <= save_addr_comb; -- gk 27.03.10 - addr_saved <= addr_saved_comb; -- gk 27.03.10 - add_sub_state <= add_sub_state_comb; -- gk 29.03.10 - save_eod <= save_eod_comb; -- gk 25.07.10 - end if; - end if; -end process saveMachineProc; - -saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, input_data_ctr, MAX_MESSAGE_SIZE_IN) -begin - saveNextState <= SIDLE; - data_req_comb <= '0'; - rst_saved_ctr_comb <= '0'; - save_addr_comb <= '0'; -- gk 27.03.10 - addr_saved_comb <= '0'; -- gk 27.03.10 - add_sub_state_comb <= '0'; -- gk 29.03.10 - save_eod_comb <= '0'; -- gk 25.07.10 - case saveCurrentState is - when SIDLE => - state <= x"0"; - if (CTS_START_READOUT_IN = '1') then - saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10 - data_req_comb <= '1'; - rst_saved_ctr_comb <= '1'; - else - saveNextState <= SIDLE; - end if; - -- gk 27.03.10 - when SAVE_EVT_ADDR => - state <= x"5"; - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - save_addr_comb <= '1'; - when WAIT_FOR_DATA => - state <= x"1"; - if (FEE_BUSY_IN = '1') then - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - else - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - end if; - addr_saved_comb <= '1'; -- gk 27.03.10 - when SAVE_DATA => - state <= x"2"; - if (FEE_BUSY_IN = '0') then - saveNextState <= TERMINATE; - else - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - end if; - when TERMINATE => - state <= x"3"; - if (CTS_READ_IN = '1') then - saveNextState <= SCLOSE; - else - saveNextState <= TERMINATE; - end if; - when SCLOSE => - state <= x"4"; - if (CTS_START_READOUT_IN = '0') then - if (input_data_ctr > MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012 - saveNextState <= RESET_FIFO; - else - saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10 - end if; - else - saveNextState <= SCLOSE; - end if; - -- gk 06.11.2012 - when RESET_FIFO => - saveNextState <= SIDLE; - state <= x"E"; - -- gk 29.03.10 new states during which the subsub bytes are saved - when ADD_SUBSUB1 => - state <= x"6"; - saveNextState <= ADD_SUBSUB2; - add_sub_state_comb <= '1'; - when ADD_SUBSUB2 => - state<= x"7"; - saveNextState <= ADD_SUBSUB3; - add_sub_state_comb <= '1'; - save_eod_comb <= '1'; - when ADD_SUBSUB3 => - state<= x"8"; - saveNextState <= ADD_SUBSUB4; - add_sub_state_comb <= '1'; - when ADD_SUBSUB4 => - state<= x"9"; - saveNextState <= SIDLE; - add_sub_state_comb <= '1'; - when others => - state <= x"f"; - saveNextState <= SIDLE; - end case; -end process saveMachine; - --- gk 06.11.2012 -INPUT_DATA_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1' or rst_saved_ctr = '1') then - input_data_ctr <= (others => '0'); - elsif (saveCurrentState = SAVE_DATA and sf_real_wr_en = '1') then - input_data_ctr(31 downto 1) <= input_data_ctr(31 downto 1) + x"1"; - end if; - end if; -end process INPUT_DATA_CTR_PROC; - --- gk 29.03.10 -ADD_SUB_CTR_PROC : process( CLK ) -begin - if( rising_edge( CLK ) ) then - if( (RESET = '1') or (rst_saved_ctr = '1') ) then - add_sub_ctr <= (others => '0'); - elsif( add_sub_state = '1' ) then - add_sub_ctr <= add_sub_ctr + 1; - end if; - end if; -end process ADD_SUB_CTR_PROC; - ---******** --- SAVE INCOMING EVENT HEADERS ---******** - --- Counter for header word storage -THE_CTS_SAVED_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - saved_ctr <= (others => '0'); - elsif( ce_saved_ctr = '1' ) then - saved_ctr <= saved_ctr + 1; - end if; - end if; -end process THE_CTS_SAVED_CTR; - --- save triggerRnd from incoming data for cts response -CTS_RND_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_rnd <= (others => '0'); - cts_rnd_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then - cts_rnd <= sf_data; - cts_rnd_saved <= '1'; - end if; - end if; -end process CTS_RND_PROC; - --- save triggerNr from incoming data for cts response -CTS_TRG_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_trg <= (others => '0'); - cts_trg_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then - cts_trg <= sf_data; - cts_trg_saved <= '1'; - end if; - end if; -end process CTS_TRG_PROC; - --- save size from incoming data for cts response (future) and to get rid of padding ---CTS_SIZE_PROC: process( CLK ) ---begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then --- cts_len <= (others => '0'); --- cts_len_saved <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then --- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words --- cts_len(0) <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then --- cts_len <= cts_len + x"4"; --- cts_len_saved <= '1'; --- end if; --- end if; ---end process CTS_SIZE_PROC; - --- gk 22.07.10 ---CTS_ADDR_PROC : process(CLK) ---begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then --- cts_addr <= (others => '0'); --- cts_addr_saved <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then --- cts_addr <= sf_data; --- cts_addr_saved <= '1'; --- end if; --- end if; ---end process CTS_ADDR_PROC; - ---****** --- SAVE FIRST EVENT HEADER VALUES ---****** - --- gk 22.07.10 ---FIRST_RUN_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- first_run_trg <= (others => '0'); --- first_run_addr <= (others => '0'); --- first_run_lock <= '0'; --- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then --- first_run_trg <= cts_trg; --- first_run_addr <= cts_addr; --- first_run_lock <= '1'; --- -- important: value saved by saveMachine but incremented by loadMachine --- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then --- first_run_trg <= first_run_trg + x"1"; --- end if; --- end if; ---end process FIRST_RUN_PROC; - --- gk 25.07.10 -SAVED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saved_events_ctr <= (others => '0'); - elsif (save_eod = '1') and (input_data_ctr < MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012 - saved_events_ctr <= saved_events_ctr + x"1"; - end if; - end if; -end process SAVED_EVT_CTR_PROC; - - ----- gk 20.07.10 ---INC_DATA_CTR_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') or (rst_saved_ctr = '1') then --- inc_data_ctr <= (others => '0'); --- elsif (sf_wr_en = '1') and (data_req = '1') then --- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1"; --- end if; --- end if; ---end process INC_DATA_CTR_proc; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Split FIFO ---THE_SPLIT_FIFO: fifo_32kx16x8_mb2 ---port map( --- -- Byte swapping for correct byte order on readout side of FIFO --- Data(7 downto 0) => sf_data(15 downto 8), --- Data(8) => '0', --- Data(16 downto 9) => sf_data(7 downto 0), --- Data(17) => save_eod, --- WrClock => CLK, --- RdClock => CLK, --- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en, --- RdEn => sf_rd_en, --- Reset => reset_split_fifo, --RESET, -- gk 06.11.2012 --- RPReset => reset_split_fifo, --RESET, -- gk 06.11.2012 --- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead --- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 --- Q(7 downto 0) => pc_data, --- Q(8) => load_eod, --- WCNT => sf_wcnt, --- RCNT => sf_rcnt, --- Empty => sf_empty, --- AlmostEmpty => open, --sf_aempty, --- Full => sf_full, --- AlmostFull => sf_afull ---); - -sf_aempty <= '0'; - -reset_split_fifo <= '1' when (saveCurrentState = RESET_FIFO or RESET = '1') else '0'; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- gk 25.07.10 -EVENT_WAITING_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - event_waiting <= '0'; - elsif (loaded_events_ctr /= saved_events_ctr) then - event_waiting <= '1'; - else - event_waiting <= '0'; - end if; - end if; -end process EVENT_WAITING_PROC; - --- write signal for PC data -pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or - (pad_phase = '1') or - ((load_sub = '1') and (sf_rd_en = '1')) or - ((drop_sub = '1') and (sf_rd_en = '1')) or - ((drop_event = '1') and (sf_rd_en = '1')) - else '0'; - -sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or - --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or - ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10 - ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10 - ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or - ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') ) - else '0'; - -ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') ) - else '0'; - --- FIFO data delay process (also forces padding bytes to known value) -THE_DATA_DELAY_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( pad_data = '1' ) then - pc_data_q <= x"aa"; -- padding for 64bit - -- gk 21.07.10 - -- set the error flag if a broken packet is sent - elsif (drop_sub = '1') and (load_sub_ctr = x"3") then - pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0); - else - pc_data_q <= pc_data; - end if; - end if; -end process THE_DATA_DELAY_PROC; - --- Statemachine for reading the data payload from the SPLIT_FIFO and feeding --- it into the packet constructor -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loadCurrentState <= LIDLE; - rst_rem_ctr <= '0'; - rem_phase <= '0'; - calc_pad <= '0'; - data_phase <= '0'; - pad_phase <= '0'; - pc_sos <= '0'; - pc_eod <= '0'; - rst_regs <= '0'; - pad_data <= '0'; - load_sub <= '0'; -- gk 30.03.10 - drop_sub <= '0'; -- gk 25.07.10 - drop_event <= '0'; -- gk 25.07.10 - drop_small <= '0'; -- gk 25.07.10 - drop_large <= '0'; -- gk 25.07.10 - drop_headers <= '0'; -- gk 25.07.10 - inc_trg_ctr <= '0'; -- gk 26.07.10 - found_empty_evt <= '0'; -- gk 01.10.10 - else - loadCurrentState <= loadNextState; - rst_rem_ctr <= rst_rem_ctr_comb; - rem_phase <= rem_phase_comb; - calc_pad <= calc_pad_comb; - data_phase <= data_phase_comb; - pad_phase <= pad_phase_comb; - pc_sos <= pc_sos_comb; - pc_eod <= pc_eod_comb; - rst_regs <= rst_regs_comb; - pad_data <= pad_data_comb; - load_sub <= load_sub_comb; -- gk 30.03.1 - drop_sub <= drop_sub_comb; -- gk 25.07.10 - drop_event <= drop_event_comb; -- gk 25.07.10 - drop_small <= drop_small_comb; -- gk 25.07.10 - drop_large <= drop_large_comb; -- gk 25.07.10 - drop_headers <= drop_headers_comb; -- gk 25.07.10 - inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10 - found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10 - end if; - end if; -end process loadMachineProc; - -loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, - PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, - MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, - first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size, DATA_GBE_ENABLE_IN, first_event, - prev_bank_select, bank_select) -begin - loadNextState <= LIDLE; - rst_rem_ctr_comb <= '0'; - rem_phase_comb <= '0'; - calc_pad_comb <= '0'; - data_phase_comb <= '0'; - pad_phase_comb <= '0'; - pc_sos_comb <= '0'; - pc_eod_comb <= '0'; - rst_regs_comb <= '0'; - pad_data_comb <= '0'; - load_sub_comb <= '0'; -- gk 30.03.10 - drop_sub_comb <= '0'; -- gk 25.07.10 - drop_event_comb <= '0'; -- gk 25.07.10 - drop_small_comb <= '0'; -- gk 25.07.10 - drop_large_comb <= '0'; -- gk 25.07.10 - drop_headers_comb <= '0'; -- gk 25.07.10 - inc_trg_ctr_comb <= '0'; -- gk 26.07.10 - found_empty_evt_comb <= '0'; -- gk 01.10.10 - case loadCurrentState is - when LIDLE => - state2 <= x"0"; - -- gk 23.07.10 - if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 -- and (PC_READY_IN = '1') - loadNextState <= INIT; - rst_rem_ctr_comb <= '1'; - rst_regs_comb <= '1'; - else - loadNextState <= LIDLE; - end if; - when INIT => - state2 <= x"1"; - loadNextState <= REMOVE; - rem_phase_comb <= '1'; - when REMOVE => - state2 <= x"2"; - if( remove_done = '1' ) then - -- gk 06.10.10 - if (MULT_EVT_ENABLE_IN = '1') then - if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then - --loadNextState <= WAIT_TO_REMOVE; - -- gk 07.12.10 - if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet - loadNextState <= WAIT_PC; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - - else - loadNextState <= WAIT_PC; - end if; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - inc_trg_ctr_comb <= '1'; - else - loadNextState <= REMOVE; - rem_phase_comb <= '1'; - end if; - when WAIT_TO_REMOVE => - if (rem_ctr = x"a") then - loadNextState <= DECIDE; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - when DECIDE => --- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_large_comb <= '1'; --- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10 --- loadNextState <= CALCA; --- found_empty_evt_comb <= '1'; --- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_small_comb <= '1'; --- elsif (pc_trig_nr + x"1" /= first_run_trg) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_headers_comb <= '1'; --- elsif (endpoint_addr /= first_run_addr) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_headers_comb <= '1'; --- else - loadNextState <= CALCA; --- end if; - calc_pad_comb <= '1'; - when CALCA => - state2 <= x"3"; - loadNextState <= CALCB; - pc_sos_comb <= '1'; - when CALCB => - -- we need a branch in case of length "0"!!!! - state2 <= x"4"; - loadNextState <= LOAD; - data_phase_comb <= '1'; - when LOAD => - state2 <= x"5"; - if (load_eod = '1') then - loadNextState <= LOAD_SUBSUB; - else - loadNextState <= LOAD; - data_phase_comb <= '1'; - end if; - -- gk 31.03.10 - when LOAD_SUBSUB => - state2 <= x"d"; - if( load_sub_done = '1' ) then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= LOAD_SUBSUB; - load_sub_comb <= '1'; - end if; - when PAD0 => - state2 <= x"6"; - loadNextState <= PAD1; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD1 => - state2 <= x"7"; - loadNextState <= PAD2; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD2 => - state2 <= x"8"; - loadNextState <= PAD3; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD3 => - state2 <= x"9"; - loadNextState <= CALCC; - pad_data_comb <= '1'; - when CALCC => - state2 <= x"a"; - if (MULT_EVT_ENABLE_IN = '1') then - loadNextState <= LIDLE; - else - loadNextState <= CLOSE; - end if; - pc_eod_comb <= '1'; - when CLOSE => - state2 <= x"b"; - loadNextState <= WAIT_PC; - --rst_regs_comb <= '1'; -- gk 07.10.10 - when WAIT_PC => - state2 <= x"c"; - if( PC_READY_IN = '1' ) then - -- gk 06.10.10 - if (MULT_EVT_ENABLE_IN = '1') then - loadNextState <= WAIT_TO_REMOVE; - else - loadNextState <= LIDLE; - end if; - else - loadNextState <= WAIT_PC; - end if; - when PAUSE_BEFORE_DROP1 => - loadNextState <= PAUSE_BEFORE_DROP2; - pc_sos_comb <= '1'; - when PAUSE_BEFORE_DROP2 => - loadNextState <= DROP; - drop_event_comb <= '1'; - -- gk 23.07.10 - when DROP => - state2 <= x"e"; - -- when data is dropped the eod marker stands as its end - if (load_eod = '1') then - loadNextState <= DROP_SUBSUB; - else - loadNextState <= DROP; - drop_event_comb <= '1'; - end if; - -- gk 25.07.10 - when DROP_SUBSUB => - if (load_sub_done = '1') then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= DROP_SUBSUB; - drop_sub_comb <= '1'; - end if; - when others => - state2 <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- gk 25.07.10 ---INVALID_STATS_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- dropped_lr_events_ctr <= (others => '0'); --- dropped_sm_events_ctr <= (others => '0'); --- headers_invalid_ctr <= (others => '0'); --- dropped_ctr <= (others => '0'); --- invalid_hsize_ctr <= (others => '0'); --- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10 --- elsif (rst_regs = '1') then --- invalid_hsize_lock <= '0'; --- elsif (drop_small = '1') then --- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (drop_large = '1') then --- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (drop_headers = '1') then --- headers_invalid_ctr <= headers_invalid_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ?? --- invalid_hsize_ctr <= invalid_hsize_ctr + x"1"; --- invalid_hsize_lock <= '1'; --- -- gk 01.10.10 --- elsif (found_empty_evt = '1') then --- found_empty_evt_ctr <= found_empty_evt_ctr + x"1"; --- end if; --- end if; ---end process INVALID_STATS_PROC; - --- gk 05.08.10 -INVALID_H_PROC : process(CLK) -begin - if rising_edge(CLK) then - load_eod_q <= load_eod; - read_size_q <= read_size; - end if; -end process INVALID_H_PROC; - --- gk 26.04.10 -READOUT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then - readout_ctr <= READOUT_CTR_IN; - readout_ctr_lock <= '0'; - elsif (pc_sos = '1') then - readout_ctr <= readout_ctr + x"1"; - end if; - end if; -end process READOUT_CTR_PROC; - ---****** --- SELECTION OF EVENT BUILDER ---****** - --- gk 27.03.10 -bank_select_proc : process( CLK ) -begin - if rising_edge( CLK ) then - -- gk 29.03.10 - if( (RESET = '1') or (rst_regs = '1') ) then - bank_select <= "0000"; - -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then - bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0); - end if; - end if; -end process bank_select_proc; - --- gk 07.12.10 -first_event_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - first_event <= '1'; - elsif (remove_done = '1') then - first_event <= '0'; - end if; - end if; -end process first_event_proc; - --- gk 07.12.10 -prev_bank_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - prev_bank_select <= "0000"; - elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then - prev_bank_select <= bank_select; - end if; - end if; -end process prev_bank_proc; - - --- gk 29.03.10 -start_config_proc : process( CLK ) -begin - if rising_edge( CLK ) then - if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then - start_config <= '0'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1') ) then -- gk 01.06.10 - start_config <= '1'; - end if; - end if; -end process start_config_proc; - - ---****** --- LOAD SUBSUBEVENT ---****** - --- gk 30.03.10 -load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') ) - else '0'; - --- gk 30.03.10 -LOAD_SUB_CTR_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_ctr <= (others => '0'); - elsif( (load_sub_ctr_comb = '1') ) then - load_sub_ctr <= load_sub_ctr + 1; - end if; - end if; -end process LOAD_SUB_CTR_PROC; - --- gk 30.03.10 --- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or --- ((load_sub_ctr = x"4") and (drop_sub = '1')) --- else '0'; -load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0'; - --- gk 30.03.10 -LOAD_SUB_DONE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_done <= '0'; - else - load_sub_done <= load_sub_done_comb; - end if; - end if; -end process LOAD_SUB_DONE_PROC; - ---****** --- EXTRACT EVENT HEADERS FROM SPLITFIFO ---****** - --- Counter for stripping the unneeded parts of the data stream, and saving the important parts -THE_REMOVE_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - rem_ctr <= (others => '0'); - elsif( (ce_rem_ctr = '1') ) then - rem_ctr <= rem_ctr + 1; - end if; - end if; -end process THE_REMOVE_CTR; - -remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address - -THE_REM_DONE_SYNC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - remove_done <= '0'; - else - remove_done <= remove_done_comb; - end if; - end if; -end process THE_REM_DONE_SYNC; - --- gk 26.04.10 -TRIG_RANDOM_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (rst_regs = '1')) then - trig_random <= (others => '0'); - elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then - trig_random <= pc_data; - end if; - end if; -end process TRIG_RANDOM_PROC; - --- extract the trigger number from splitfifo data -THE_TRG_NR_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_trig_nr <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10 - pc_trig_nr(7 downto 0) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10 - pc_trig_nr(15 downto 8) <= pc_data; - end if; - end if; -end process THE_TRG_NR_PROC; - --- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, --- and in case of padding needed increase it accordingly -THE_SUB_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_sub_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - pc_sub_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - pc_sub_size(17 downto 10) <= pc_data; - -- gk 20.07.10 - -- gk 30.03.10 bug fixed in the way that is written below - -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save - elsif( (calc_pad = '1') and (padding_needed = '1') ) then - pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!! - elsif( (calc_pad = '1') and (padding_needed = '0') ) then - pc_sub_size <= pc_sub_size + x"8"; - end if; - end if; -end process THE_SUB_SIZE_PROC; - --- gk 06.10.10 -MESSAGE_SIZE_PROC : process(CLK) -begin - if rising_edge(CLK) then --- if (RESET = '1') then --- message_size <= (others => '0'); --- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then --- message_size <= (others => '0'); --- elsif (pc_sos = '1') then --- message_size <= message_size + pc_sub_size; --- end if; - if (RESET = '1') then - message_size <= x"0000_0028"; - elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then - message_size <= x"0000_0028"; - elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then - message_size <= x"0000_0028"; - elsif (pc_sos = '1') then - message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers - end if; - end if; -end process MESSAGE_SIZE_PROC; - - --- gk 25.07.10 -ENDP_ADDRESS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_regs = '1') then - endpoint_addr <= (others => '0'); - endp_addr_lock <= '0'; - elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then - endpoint_addr(7 downto 0) <= pc_data; - endp_addr_lock <= '1'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then - endpoint_addr(15 downto 8) <= pc_data; - endp_addr_lock <= '0'; - end if; - end if; -end process ENDP_ADDRESS_PROC; - - - --- check for padding -THE_PADDING_NEEDED_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - padding_needed <= '0'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then - padding_needed <= '1'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then - padding_needed <= '0'; - end if; - end if; -end process THE_PADDING_NEEDED_PROC; - --- number of bytes to read from split fifo -THE_READ_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then - read_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - read_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - read_size(17 downto 10) <= pc_data; - elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then - read_size <= read_size - 1; - -- gk 25.07.10 - elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then - read_size <= read_size - 1; - end if; - end if; -end process THE_READ_SIZE_PROC; - -read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2" - ---****** --- EVENTS COUNTERS ---****** - --- gk 25.07.10 -LOADED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loaded_events_ctr <= (others => '0'); - elsif (remove_done = '1') then - loaded_events_ctr <= loaded_events_ctr + x"1"; - end if; - end if; -end process LOADED_EVT_CTR_PROC; - ----- gk 25.07.10 ---CONSTR_EVENTS_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- constr_events_ctr <= (others => '0'); --- elsif (pc_eod = '1') then --- constr_events_ctr <= constr_events_ctr + x"1"; --- end if; --- end if; ---end process CONSTR_EVENTS_CTR_PROC; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Debug signals ---debug(0) <= sf_full; ---debug(1) <= sf_empty; ---debug(2) <= sf_afull; ---debug(3) <= sf_aempty; --- ---debug(7 downto 4) <= state2; --- ---debug(11 downto 8) <= state; --- ---dbg_bs_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(15 downto 12) <= (others => '0'); --- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then --- debug(15 downto 12) <= bank_select; --- end if; --- end if; ---end process dbg_bs_proc; --- ---debug(16) <= config_done; ---debug(17) <= '0'; --remove_done; ---debug(18) <= read_done; ---debug(19) <= padding_needed; --- ---debug(20) <= load_sub_done; --- ---dbg_cts_inf_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(39 downto 32) <= (others => '0'); --- elsif ( save_addr = '1' ) then --- debug(39 downto 32) <= CTS_INFORMATION_IN; --- end if; --- end if; ---end process dbg_cts_inf_proc; --- ---debug(47 downto 40) <= (others => '0'); --- --- ---debug(63 downto 48) <= actual_message_size(15 downto 0); --- ---dbg_pc_sub_size_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(81 downto 64) <= (others => '0'); --- elsif (loadCurrentState = DECIDE) then --- debug(81 downto 64) <= pc_sub_size; --- end if; --- end if; ---end process dbg_pc_sub_size_proc; --- ---dbg_empty_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') or (rst_regs = '1') then --- debug(84 downto 82) <= (others => '0'); --- elsif (read_size = 2) then --- debug(82) <= sf_empty; --- elsif (read_size = 1) then --- debug(83) <= sf_empty; --- elsif (read_size = 0) then --- debug(84) <= sf_empty; --- end if; --- end if; ---end process dbg_empty_proc; --- ---debug(95 downto 85) <= (others => '0'); --- ---dbg_inc_ctr_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(127 downto 96) <= (others => '1'); --- elsif (saveCurrentState = SCLOSE) then --- debug(127 downto 96) <= inc_data_ctr; --- end if; --- end if; ---end process dbg_inc_ctr_proc; --- ---debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0); ---debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0); --- ---debug(175 downto 160) <= headers_invalid_ctr(15 downto 0); ---debug(191 downto 176) <= (others => '0'); --- ---dbg_cts_q_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- cts_len_q <= (others => '0'); --- cts_rnd_q <= (others => '0'); --- cts_trg_q <= (others => '0'); --- cts_addr_q <= (others => '0'); --- elsif (cts_len_saved = '1') then --- cts_len_q <= cts_len(16 downto 1); --- cts_addr_q <= cts_addr; --- cts_rnd_q <= cts_rnd; --- cts_trg_q <= cts_trg; --- end if; --- end if; ---end process dbg_cts_q_proc; --- ---debug(207 downto 192) <= cts_trg_q; ---debug(223 downto 208) <= cts_rnd_q; ---debug(239 downto 224) <= cts_addr_q; ---debug(255 downto 240) <= cts_len_q; ---debug(271 downto 256) <= first_run_trg; ---debug(287 downto 272) <= first_run_addr; --- ---debug(303 downto 288) <= saved_events_ctr; ---debug(319 downto 304) <= loaded_events_ctr; --- ---debug(335 downto 320) <= constr_events_ctr(15 downto 0); ---debug(351 downto 336) <= dropped_ctr(15 downto 0); --- ---debug(367 downto 352) <= invalid_hsize_ctr; ---debug(383 downto 368) <= (others => '0'); --- ---MONITOR_OUT(31 downto 0) <= constr_events_ctr; ---MONITOR_OUT(63 downto 32) <= dropped_ctr; ---MONITOR_OUT(95 downto 64) <= headers_invalid_ctr; ---MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr; ---MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr; ---MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000"; ---MONITOR_OUT(191 downto 164) <= (others => '0'); ---MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10 - --- Outputs -FEE_READ_OUT <= fee_read; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; -CTS_DATA_OUT <= cts_data; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_LENGTH_OUT <= cts_length; - ---PC_SOS_OUT <= pc_sos; ---PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1')) --- or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) --- -- gk 07.12.10 --- or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) --- else '0'; -- gk 07.10.10 ---PC_DATA_OUT <= pc_data_q; ---PC_WR_EN_OUT <= pc_wr_en_qq; - -PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random; - ---PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; ---PC_PADDING_OUT <= padding_needed; --- gk 07.10.10 ---PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0'; - -DEBUG_OUT <= debug; - --- SIMPLE SENDER STUFF - - - -PC_SOS_OUT <= '0'; --'1' when gen_current_state = WAIT_FOR_PC and PC_READY_IN = '1' else '0'; -PC_EOS_OUT <= '0'; -PC_EOD_OUT <= '0'; --'1' when gen_current_state = GENERATE_DATA and gen_data_ctr = SCTRL_DUMMY_SIZE_IN else '0'; -PC_DATA_OUT <= gen_data_ctr(7 downto 0); -PC_WR_EN_OUT <= '0'; --'1' when gen_current_state = GENERATE_DATA else '0'; -PC_SUB_SIZE_OUT <= x"0000" & SCTRL_DUMMY_SIZE_IN + x"1"; -PC_PADDING_OUT <= '0'; - -GEN_MACHINE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - gen_current_state <= IDLE; - else - gen_current_state <= gen_next_state; - end if; - end if; -end process GEN_MACHINE_PROC; - -GEN_MACHINE : process(gen_current_state, gen_data_ctr, event_waiting, DATA_GBE_ENABLE_IN, SCTRL_DUMMY_SIZE_IN, PC_READY_IN) -begin - case (gen_current_state) is - - when IDLE => - if (event_waiting = '1' and DATA_GBE_ENABLE_IN = '1') then - gen_next_state <= WAIT_FOR_PC; - else - gen_next_state <= IDLE; - end if; - - when WAIT_FOR_PC => - if (PC_READY_IN = '1') then - gen_next_state <= GENERATE_DATA; - else - gen_next_state <= WAIT_FOR_PC; - end if; - - when GENERATE_DATA => - if (gen_data_ctr = SCTRL_DUMMY_SIZE_IN) then - gen_next_state <= CLEANUP; - else - gen_next_state <= GENERATE_DATA; - end if; - - when CLEANUP => - gen_next_state <= IDLE; - - end case; -end process GEN_MACHINE; - -GEN_DATA_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (gen_current_state = IDLE) then - gen_data_ctr <= (others => '0'); - elsif (gen_current_state = GENERATE_DATA) then - gen_data_ctr <= gen_data_ctr + x"1"; - end if; - end if; -end process GEN_DATA_CTR_PROC; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd deleted file mode 100644 index 3e77ecd..0000000 --- a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd +++ /dev/null @@ -1,878 +0,0 @@ -LIBRARY ieee; - -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - - -entity trb_net16_gbe_ipu_interface is -port ( - CLK_IPU : in std_logic; - CLK_GBE : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_SUBEVENT_SIZE_IN : in std_logic_vector(15 downto 0); - MAX_QUEUE_SIZE_IN : in std_logic_vector(15 downto 0); - MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - MAX_SINGLE_SUB_SIZE_IN : in std_logic_vector(15 downto 0); - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - -- PacketConstructor interface - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; - PC_EOQ_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0); - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) - ); -end entity trb_net16_gbe_ipu_interface; - -architecture RTL of trb_net16_gbe_ipu_interface is - -attribute syn_encoding : string; - -type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, FINISH_4_WORDS, CLEANUP); -signal save_current_state, save_next_state : saveStates; -attribute syn_encoding of save_current_state : signal is "onehot"; - -type loadStates is (IDLE, WAIT_FOR_SUBS, REMOVE, WAIT_ONE, WAIT_TWO, DECIDE, PREPARE_TO_LOAD_SUB, WAIT_FOR_LOAD, LOAD, CLOSE_PACKET, CLOSE_SUB, CLOSE_QUEUE, CLOSE_QUEUE_IMMEDIATELY); -signal load_current_state, load_next_state : loadStates; -attribute syn_encoding of load_current_state : signal is "onehot"; - -signal sf_data : std_Logic_vector(15 downto 0); -signal save_eod, sf_wr_en, sf_rd_en, sf_reset, sf_empty, sf_full, sf_afull, sf_eos : std_logic; -signal sf_q, pc_data : std_logic_vector(7 downto 0); - -signal cts_rnd, cts_trg : std_logic_vector(15 downto 0); -signal save_ctr : std_logic_vector(15 downto 0); - -signal saved_events_ctr, loaded_events_ctr, saved_events_ctr_gbe : std_logic_vector(7 downto 0); -signal loaded_bytes_ctr : std_Logic_vector(15 downto 0); - -signal trigger_random : std_logic_vector(7 downto 0); -signal trigger_number : std_logic_vector(15 downto 0); -signal subevent_size : std_logic_vector(17 downto 0); -signal trigger_type : std_logic_vector(3 downto 0); - -signal bank_select : std_logic_vector(3 downto 0); -signal readout_ctr : std_logic_vector(23 downto 0) := x"000000"; -signal pc_ready_q : std_logic; -signal sf_afull_q : std_logic; -signal sf_aempty : std_logic; -signal rec_state, load_state : std_logic_vector(3 downto 0); -signal queue_size : std_logic_vector(17 downto 0); -signal number_of_subs : std_logic_vector(15 downto 0); -signal size_check_ctr : integer range 0 to 7; -signal sf_data_q, sf_data_qq, sf_data_qqq, sf_data_qqqq, sf_data_qqqqq : std_logic_vector(15 downto 0); -signal sf_wr_q, sf_wr_lock : std_logic; -signal save_eod_q, save_eod_qq, save_eod_qqq, save_eod_qqqq, save_eod_qqqqq : std_logic; -signal too_large_dropped : std_logic_vector(31 downto 0); -signal previous_ttype, previous_bank : std_logic_vector(3 downto 0); - -begin - ---********* --- RECEIVING PART ---********* - -SAVE_MACHINE_PROC : process(RESET, CLK_IPU) -begin - if RESET = '1' then - save_current_state <= IDLE; - elsif rising_edge(CLK_IPU) then - save_current_state <= save_next_state; - end if; -end process SAVE_MACHINE_PROC; - -SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, size_check_ctr) -begin - case (save_current_state) is - - when IDLE => - rec_state <= x"1"; - if (CTS_START_READOUT_IN = '1') then - save_next_state <= SAVE_EVT_ADDR; - else - save_next_state <= IDLE; - end if; - - when SAVE_EVT_ADDR => - rec_state <= x"2"; - save_next_state <= WAIT_FOR_DATA; - - when WAIT_FOR_DATA => - rec_state <= x"3"; - if (FEE_BUSY_IN = '1') then - save_next_state <= SAVE_DATA; - else - save_next_state <= WAIT_FOR_DATA; - end if; - - when SAVE_DATA => - rec_state <= x"4"; - if (FEE_BUSY_IN = '0') then - save_next_state <= TERMINATE; - else - save_next_state <= SAVE_DATA; - end if; - - when TERMINATE => - rec_state <= x"5"; - if (CTS_READ_IN = '1') then - save_next_state <= CLOSE; - else - save_next_state <= TERMINATE; - end if; - - when CLOSE => - rec_state <= x"6"; - if (CTS_START_READOUT_IN = '0') then - save_next_state <= ADD_SUBSUB1; - else - save_next_state <= CLOSE; - end if; - - when ADD_SUBSUB1 => - rec_state <= x"7"; - save_next_state <= ADD_SUBSUB2; - - when ADD_SUBSUB2 => - rec_state <= x"8"; - save_next_state <= ADD_SUBSUB3; - - when ADD_SUBSUB3 => - rec_state <= x"9"; - save_next_state <= ADD_SUBSUB4; - - when ADD_SUBSUB4 => - rec_state <= x"a"; - save_next_state <= FINISH_4_WORDS; - - when FINISH_4_WORDS => - rec_state <= x"b"; - if (size_check_ctr = 1) then - save_next_state <= CLEANUP; - else - save_next_state <= FINISH_4_WORDS; - end if; - - when CLEANUP => - rec_state <= x"c"; - save_next_state <= IDLE; - - end case; -end process SAVE_MACHINE; - -SF_WR_EN_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - sf_afull_q <= sf_afull; - - if (sf_afull_q = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then - sf_wr_en <= '1'; - elsif (save_current_state = SAVE_EVT_ADDR) then - sf_wr_en <= '1'; - elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then - sf_wr_en <= '1'; - elsif (save_current_state = FINISH_4_WORDS) then - sf_wr_en <= '1'; - else - sf_wr_en <= '0'; - end if; - end if; -end process SF_WR_EN_PROC; - -SF_DATA_EOD_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - case (save_current_state) is - - when SAVE_EVT_ADDR => - sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); - sf_data(7 downto 4) <= CTS_READOUT_TYPE_IN; - sf_data(15 downto 8) <= x"ab"; - save_eod <= '0'; - - when SAVE_DATA => - sf_data <= FEE_DATA_IN; - save_eod <= '0'; - - when ADD_SUBSUB1 => - sf_data <= x"0001"; - save_eod <= '0'; - - when ADD_SUBSUB2 => - sf_data <= x"5555"; - save_eod <= '0'; - - when ADD_SUBSUB3 => - sf_data <= FEE_STATUS_BITS_IN(31 downto 16); - save_eod <= '1'; - - when ADD_SUBSUB4 => - sf_data <= FEE_STATUS_BITS_IN(15 downto 0); - save_eod <= '0'; - - when others => sf_data <= (others => '0'); save_eod <= '0'; - - end case; - end if; -end process SF_DATA_EOD_PROC; - -process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - if (sf_wr_en = '1') then - sf_data_q <= sf_data; - sf_data_qq <= sf_data_q; - sf_data_qqq <= sf_data_qq; - sf_data_qqqq <= sf_data_qqq; - sf_data_qqqqq <= sf_data_qqqq; - - save_eod_q <= save_eod; - save_eod_qq <= save_eod_q; - save_eod_qqq <= save_eod_qq; - save_eod_qqqq <= save_eod_qqq; - save_eod_qqqqq <= save_eod_qqqq; - else - sf_data_q <= sf_data_q; - sf_data_qq <= sf_data_qq; - sf_data_qqq <= sf_data_qqq; - sf_data_qqqq <= sf_data_qqqq; - sf_data_qqqqq <= sf_data_qqqqq; - - save_eod_q <= save_eod_q; - save_eod_qq <= save_eod_qq; - save_eod_qqq <= save_eod_qqq; - save_eod_qqqq <= save_eod_qqqq; - save_eod_qqqqq <= save_eod_qqqq; - end if; - -sf_wr_q <= sf_wr_en and not sf_wr_lock; - - end if; -end process; - -process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - if (save_current_state = IDLE) then - size_check_ctr <= 0; - elsif (save_current_state = SAVE_DATA and sf_wr_en = '1' and size_check_ctr /= 4) then - size_check_ctr <= size_check_ctr + 1; - elsif (save_current_state = FINISH_4_WORDS and size_check_ctr /= 0) then - size_check_ctr <= size_check_ctr - 1; - else - size_check_ctr <= size_check_ctr; - end if; - - if (save_current_state = IDLE) then - sf_wr_lock <= '1'; - elsif (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") < ("00" & MAX_SUBEVENT_SIZE_IN)) then -- condition to ALLOW an event to be passed forward - sf_wr_lock <= '0'; - else - sf_wr_lock <= sf_wr_lock; - end if; - - end if; -end process; - -process(RESET, CLK_IPU) -begin - if (RESET = '1') then - too_large_dropped <= (others => '0'); - elsif rising_edge(CLK_IPU) then - if (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") >= ("00" & MAX_SUBEVENT_SIZE_IN)) then - too_large_dropped <= too_large_dropped + x"1"; - else - too_large_dropped <= too_large_dropped; - end if; - end if; -end process; - - -SAVED_EVENTS_CTR_PROC : process(RESET, CLK_IPU) -begin - if (RESET = '1') then - saved_events_ctr <= (others => '0'); - elsif rising_edge(CLK_IPU) then - if (save_current_state = ADD_SUBSUB4 and sf_wr_lock = '0') then - saved_events_ctr <= saved_events_ctr + x"1"; - else - saved_events_ctr <= saved_events_ctr; - end if; - end if; -end process SAVED_EVENTS_CTR_PROC; - -CTS_DATAREADY_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then - CTS_DATAREADY_OUT <= '1'; - elsif (save_current_state = TERMINATE) then - CTS_DATAREADY_OUT <= '1'; - else - CTS_DATAREADY_OUT <= '0'; - end if; - end if; -end process CTS_DATAREADY_PROC; - -CTS_READOUT_FINISHED_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - if (save_current_state = CLOSE) then - CTS_READOUT_FINISHED_OUT <= '1'; - else - CTS_READOUT_FINISHED_OUT <= '0'; - end if; - end if; -end process CTS_READOUT_FINISHED_PROC; - -CTS_LENGTH_OUT <= (others => '0'); -CTS_ERROR_PATTERN_OUT <= (others => '0'); - -CTS_DATA_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg; - end if; -end process CTS_DATA_PROC; - -CTS_RND_TRG_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - if (save_current_state = SAVE_DATA and save_ctr = x"0000") then - cts_rnd <= sf_data; - cts_trg <= cts_trg; - elsif (save_current_state = SAVE_DATA and save_ctr = x"0001") then - cts_rnd <= cts_rnd; - cts_trg <= sf_data; - else - cts_rnd <= cts_rnd; - cts_trg <= cts_trg; - end if; - end if; -end process CTS_RND_TRG_PROC; - -SAVE_CTR_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - if (save_current_state = IDLE) then - save_ctr <= (others => '0'); - elsif (save_current_state = SAVE_DATA and sf_wr_en = '1') then - save_ctr <= save_ctr + x"1"; - else - save_ctr <= save_ctr; - end if; - end if; -end process SAVE_CTR_PROC; - -FEE_READ_PROC : process(CLK_IPU) -begin - if rising_edge(CLK_IPU) then - if (sf_afull = '0') then - if (save_current_state = IDLE or save_current_state = SAVE_EVT_ADDR or save_current_state = WAIT_FOR_DATA or save_current_state = SAVE_DATA) then - FEE_READ_OUT <= '1'; - else - FEE_READ_OUT <= '0'; - end if; - else - FEE_READ_OUT <= '0'; - end if; - end if; -end process FEE_READ_PROC; - - -THE_SPLIT_FIFO: fifo_32kx16x8_mb2 --fifo_16kx18x9 -port map( - -- Byte swapping for correct byte order on readout side of FIFO - Data(7 downto 0) => sf_data_qqqqq(15 downto 8), - Data(8) => '0', - Data(16 downto 9) => sf_data_qqqqq(7 downto 0), - Data(17) => save_eod_qqqqq, - WrClock => CLK_IPU, - RdClock => CLK_GBE, - WrEn => sf_wr_q, -- sf_wr_en - RdEn => sf_rd_en, - Reset => sf_reset, - RPReset => sf_reset, - AmEmptyThresh => b"0000_0000_0000_0010", --b"0000_0000_0000_0010", -- one byte ahead - AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 -- b"001_0011_1000_1000" - Q(7 downto 0) => sf_q, - Q(8) => sf_eos, - --WCNT => open, - --RCNT => open, - Empty => sf_empty, - AlmostEmpty => sf_aempty, - Full => sf_full, -- WARNING, JUST FOR DEBUG - AlmostFull => sf_afull -); - -sf_reset <= RESET; - ---********* --- LOADING PART ---********* - -PC_DATA_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - pc_data <= sf_q; - end if; -end process PC_DATA_PROC; - -LOAD_MACHINE_PROC : process(RESET, CLK_GBE) -begin - if RESET = '1' then - load_current_state <= IDLE; - elsif rising_edge(CLK_GBE) then - load_current_state <= load_next_state; - end if; -end process LOAD_MACHINE_PROC; - -LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, PC_READY_IN, sf_eos, queue_size, number_of_subs, - subevent_size, MAX_QUEUE_SIZE_IN, MAX_SUBS_IN_QUEUE_IN, MAX_SINGLE_SUB_SIZE_IN, previous_bank, previous_ttype, trigger_type, - bank_select, MULT_EVT_ENABLE_IN -) -begin - case (load_current_state) is - - when IDLE => - load_state <= x"1"; - load_next_state <= WAIT_FOR_SUBS; - - when WAIT_FOR_SUBS => - load_state <= x"2"; - if (saved_events_ctr_gbe /= loaded_events_ctr) then - load_next_state <= REMOVE; - else - load_next_state <= WAIT_FOR_SUBS; - end if; - - when REMOVE => - load_state <= x"3"; - if (loaded_bytes_ctr = x"0008") then - load_next_state <= WAIT_ONE; - else - load_next_state <= REMOVE; - end if; - - when WAIT_ONE => - load_state <= x"4"; - load_next_state <= WAIT_TWO; - - when WAIT_TWO => - load_state <= x"4"; - load_next_state <= DECIDE; - - --TODO: all queue split conditions here and also in the size process - when DECIDE => - load_state <= x"5"; - if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then -- max udp packet exceeded - load_next_state <= CLOSE_QUEUE; - elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then - load_next_state <= CLOSE_QUEUE; - elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then - load_next_state <= CLOSE_QUEUE; - elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then - load_next_state <= CLOSE_QUEUE; - elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then - load_next_state <= CLOSE_QUEUE; - else - load_next_state <= PREPARE_TO_LOAD_SUB; - end if; - - when PREPARE_TO_LOAD_SUB => - load_state <= x"6"; - load_next_state <= WAIT_FOR_LOAD; - - when WAIT_FOR_LOAD => - load_state <= x"7"; - if (PC_READY_IN = '1') then - load_next_state <= LOAD; - else - load_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD => - load_state <= x"8"; - if (sf_eos = '1') then - load_next_state <= CLOSE_SUB; - else - load_next_state <= LOAD; - end if; - - when CLOSE_SUB => - load_state <= x"9"; - if (subevent_size > ("00" & MAX_SINGLE_SUB_SIZE_IN) and queue_size = (subevent_size + x"10" + x"8" + x"4")) then - load_next_state <= CLOSE_QUEUE_IMMEDIATELY; - else - load_next_state <= WAIT_FOR_SUBS; - end if; - - when CLOSE_QUEUE => - load_state <= x"a"; - load_next_state <= PREPARE_TO_LOAD_SUB; - - when CLOSE_QUEUE_IMMEDIATELY => - load_state <= x"b"; - load_next_state <= WAIT_FOR_SUBS; - - - when others => load_next_state <= IDLE; - - end case; -end process LOAD_MACHINE; - -saved_ctr_sync : signal_sync -generic map( - WIDTH => 8, - DEPTH => 2 -) -port map( - RESET => RESET, - CLK0 => CLK_GBE, - CLK1 => CLK_GBE, - D_IN => saved_events_ctr, - D_OUT => saved_events_ctr_gbe -); - - ---TODO: all queue split conditions here --- the queue size counter used only for closing current queue --- sums up all subevent sizes with their headers and stuff -process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE) then - queue_size <= (others => '0'); - elsif (load_current_state = CLOSE_QUEUE_IMMEDIATELY) then - queue_size <= (others => '0'); - elsif (load_current_state = WAIT_TWO) then - queue_size <= queue_size + subevent_size + x"10" + x"8" + x"4"; - elsif (load_current_state = DECIDE) then - if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then - queue_size <= subevent_size + x"10" + x"8" + x"4"; - elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then - queue_size <= subevent_size + x"10" + x"8" + x"4"; - elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then - queue_size <= subevent_size + x"10" + x"8" + x"4"; - elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then - queue_size <= subevent_size + x"10" + x"8" + x"4"; - elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then - queue_size <= subevent_size + x"10" + x"8" + x"4"; - else - queue_size <= queue_size; - end if; - else - queue_size <= queue_size; - end if; - end if; -end process; - -process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE or load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then - number_of_subs <= (others => '0'); - elsif (load_current_state = PREPARE_TO_LOAD_SUB) then - number_of_subs <= number_of_subs + x"1"; - else - number_of_subs <= number_of_subs; - end if; - end if; -end process; - - -SF_RD_EN_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (PC_READY_IN = '1') then - if (load_current_state = REMOVE) then - sf_rd_en <= '1'; - elsif (load_current_state = LOAD) then - sf_rd_en <= '1'; - else - sf_rd_en <= '0'; - end if; - else - sf_rd_en <= '0'; - end if; - end if; -end process SF_RD_EN_PROC; - ---***** --- information extraction - -process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE) then - previous_bank <= x"0"; - previous_ttype <= x"0"; - elsif (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY or load_current_state = CLOSE_SUB) then - previous_bank <= bank_select; - previous_ttype <= trigger_type; - else - previous_bank <= previous_bank; - previous_ttype <= previous_ttype; - end if; - end if; -end process; - -TRIGGER_RANDOM_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE) then - trigger_random <= (others => '0'); - elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0005") then - trigger_random <= pc_data; - else - trigger_random <= trigger_random; - end if; - end if; -end process TRIGGER_RANDOM_PROC; - -TRIGGER_NUMBER_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE) then - trigger_number <= (others => '0'); - elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0007") then - trigger_number(7 downto 0) <= pc_data; - elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0006") then - trigger_number(15 downto 8) <= pc_data; - else - trigger_number <= trigger_number; - end if; - end if; -end process TRIGGER_NUMBER_PROC; - -SUBEVENT_SIZE_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE) then - subevent_size <= (others => '0'); - elsif (load_current_state = WAIT_ONE and sf_rd_en = '1' and loaded_bytes_ctr = x"0009") then - subevent_size(9 downto 2) <= pc_data; - elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0008") then - subevent_size(17 downto 10) <= pc_data; - else - subevent_size <= subevent_size; - end if; - end if; -end process SUBEVENT_SIZE_PROC; - -TRIGGER_TYPE_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE) then - trigger_type <= x"0"; - elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then - trigger_type <= pc_data(7 downto 4); - else - trigger_type <= trigger_type; - end if; - end if; -end process TRIGGER_TYPE_PROC; - --- end of extraction ---***** - ---***** --- counters - -LOADED_EVENTS_CTR_PROC : process(RESET, CLK_GBE) -begin - if (RESET = '1') then - loaded_events_ctr <= (others => '0'); - elsif rising_edge(CLK_GBE) then - if (load_current_state = CLOSE_SUB) then - loaded_events_ctr <= loaded_events_ctr + x"1"; - else - loaded_events_ctr <= loaded_events_ctr; - end if; - end if; -end process LOADED_EVENTS_CTR_PROC; - -LOADED_BYTES_CTR_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = WAIT_FOR_SUBS) then - loaded_bytes_ctr <= (others => '0'); - elsif (sf_rd_en = '1') then - if (load_current_state = REMOVE) then - loaded_bytes_ctr <= loaded_bytes_ctr + x"1"; - else - loaded_bytes_ctr <= loaded_bytes_ctr; - end if; - else - loaded_bytes_ctr <= loaded_bytes_ctr; - end if; - end if; -end process LOADED_BYTES_CTR_PROC; - -READOUT_CTR_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (READOUT_CTR_VALID_IN = '1') then - readout_ctr <= READOUT_CTR_IN; - elsif (load_current_state = DECIDE) then - readout_ctr <= readout_ctr + x"1"; - else - readout_ctr <= readout_ctr; - end if; - end if; -end process READOUT_CTR_PROC; - --- end of counters ---***** - ---***** --- event builder selection - - -BANK_SELECT_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = IDLE) then - bank_select <= x"0"; - elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then - bank_select <= pc_data(3 downto 0); - else - bank_select <= bank_select; - end if; - end if; -end process BANK_SELECT_PROC; - -BANK_SELECT_OUT <= bank_select; - -START_CONFIG_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then - START_CONFIG_OUT <= '1'; - elsif (CONFIG_DONE_IN = '1') then - START_CONFIG_OUT <= '0'; - else - START_CONFIG_OUT <= '0'; - end if; - end if; -end process START_CONFIG_PROC; - --- end of event builder selection ---***** - - -PC_WR_EN_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - pc_ready_q <= PC_READY_IN; - if (pc_ready_q = '1') then - if (load_current_state = LOAD) then - PC_WR_EN_OUT <= '1'; - else - PC_WR_EN_OUT <= '0'; - end if; - else - PC_WR_EN_OUT <= '0'; - end if; - end if; -end process PC_WR_EN_PROC; - -PC_SOS_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = PREPARE_TO_LOAD_SUB) then - PC_SOS_OUT <= '1'; - else - PC_SOS_OUT <= '0'; - end if; - end if; -end process PC_SOS_PROC; - -PC_EOD_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - PC_EOS_OUT <= sf_eos; - end if; -end process PC_EOD_PROC; - -PC_EOQ_PROC : process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - if (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then - PC_EOQ_OUT <= '1'; - else - PC_EOQ_OUT <= '0'; - end if; - end if; -end process PC_EOQ_PROC; - ---******* --- outputs - -PC_DATA_OUT <= pc_data; - -PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & subevent_size; - -PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & trigger_number & trigger_random; - -PC_TRIGGER_TYPE_OUT <= trigger_type; - - -process(CLK_GBE) -begin - if rising_edge(CLK_GBE) then - DEBUG_OUT(3 downto 0) <= rec_state; - DEBUG_OUT(7 downto 4) <= load_state; - DEBUG_OUT(8) <= sf_empty; - DEBUG_OUT(9) <= sf_aempty; - DEBUG_OUT(10) <= sf_full; - DEBUG_OUT(11) <= sf_afull; - end if; -end process; - -DEBUG_OUT(383 downto 12) <= (others => '0'); -MONITOR_OUT(31 downto 0) <= too_large_dropped; -MONITOR_OUT(223 downto 32) <= (others => '0'); - -end architecture RTL; diff --git a/gbe2_ecp3/trb_net16_gbe_mac_control.vhd b/gbe2_ecp3/trb_net16_gbe_mac_control.vhd deleted file mode 100644 index 5a9a607..0000000 --- a/gbe2_ecp3/trb_net16_gbe_mac_control.vhd +++ /dev/null @@ -1,223 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - ---******** --- configures TriSpeed MAC and signalizes when it's ready --- used also to filter out frames with different addresses --- after main configuration (by setting TsMAC filtering accordingly) - - - -entity trb_net16_gbe_mac_control is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- signals to/from main controller - MC_TSMAC_READY_OUT : out std_logic; - MC_RECONF_IN : in std_logic; - MC_GBE_EN_IN : in std_logic; - MC_RX_DISCARD_FCS : in std_logic; - MC_PROMISC_IN : in std_logic; - MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0); - --- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT : out std_logic_vector(7 downto 0); - TSM_HDATA_OUT : out std_logic_vector(7 downto 0); - TSM_HCS_N_OUT : out std_logic; - TSM_HWRITE_N_OUT : out std_logic; - TSM_HREAD_N_OUT : out std_logic; - TSM_HREADY_N_IN : in std_logic; - TSM_HDATA_EN_N_IN : in std_logic; - - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_mac_control; - - -architecture trb_net16_gbe_mac_control of trb_net16_gbe_mac_control is - -attribute syn_encoding : string; - -type mac_conf_states is (IDLE, DISABLE, WRITE_TX_RX_CTRL1, WRITE_TX_RX_CTRL2, ENABLE, READY); -signal mac_conf_current_state, mac_conf_next_state : mac_conf_states; -attribute syn_encoding of mac_conf_current_state : signal is "onehot"; - -signal tsmac_ready : std_logic; -signal reg_mode : std_logic_vector(7 downto 0); -signal reg_tx_rx_ctrl1, reg_tx_rx_ctrl2 : std_logic_vector(7 downto 0); -signal reg_max_pkt_size : std_logic_vector(15 downto 0); -signal reg_ipg : std_logic_vector(15 downto 0); -signal reg_mac0 : std_logic_vector(15 downto 0); -signal reg_mac1 : std_logic_vector(15 downto 0); -signal reg_mac2 : std_logic_vector(15 downto 0); - -signal haddr : std_logic_vector(7 downto 0); -signal hcs_n : std_logic; -signal hwrite_n : std_logic; -signal hdata_pointer : integer range 0 to 1; -signal state : std_logic_vector(3 downto 0); -signal hready_n_q : std_logic; - -begin - -reg_mode(7 downto 4) <= x"0"; -reg_mode(3) <= '1'; -- tx_en -reg_mode(2) <= '1'; -- rx_en -reg_mode(1) <= '1'; -- flow_control en -reg_mode(0) <= MC_GBE_EN_IN; -- gbe en - -reg_tx_rx_ctrl2(7 downto 1) <= (others => '0'); -- reserved -reg_tx_rx_ctrl2(0) <= '1'; -- receive short -reg_tx_rx_ctrl1(7) <= '1'; -- receive broadcast -reg_tx_rx_ctrl1(6) <= '1'; -- drop control -reg_tx_rx_ctrl1(5) <= '0'; -- half_duplex en -reg_tx_rx_ctrl1(4) <= '1'; -- receive multicast -reg_tx_rx_ctrl1(3) <= '1'; -- receive pause -reg_tx_rx_ctrl1(2) <= '0'; -- transmit disable FCS -reg_tx_rx_ctrl1(1) <= '1'; -- receive discard FCS and padding -reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode - - -MAC_CONF_MACHINE_PROC : process(CLK) -begin - if RESET = '1' then - mac_conf_current_state <= IDLE; - elsif rising_edge(CLK) then --- if (RESET = '1') then --- mac_conf_current_state <= IDLE; --- else - mac_conf_current_state <= mac_conf_next_state; --- end if; - end if; -end process MAC_CONF_MACHINE_PROC; - -MAC_CONF_MACHINE : process(mac_conf_current_state, MC_RECONF_IN, TSM_HREADY_N_IN) -begin - - case mac_conf_current_state is - - when IDLE => - if (MC_RECONF_IN = '1') then - mac_conf_next_state <= DISABLE; - else - mac_conf_next_state <= IDLE; - end if; - - when DISABLE => - if (TSM_HREADY_N_IN = '0') then - mac_conf_next_state <= WRITE_TX_RX_CTRL1; - else - mac_conf_next_state <= DISABLE; - end if; - - when WRITE_TX_RX_CTRL1 => - if (TSM_HREADY_N_IN = '0') then - mac_conf_next_state <= WRITE_TX_RX_CTRL2; - else - mac_conf_next_state <= WRITE_TX_RX_CTRL1; - end if; - - when WRITE_TX_RX_CTRL2 => - if (TSM_HREADY_N_IN = '0') then - mac_conf_next_state <= ENABLE; - else - mac_conf_next_state <= WRITE_TX_RX_CTRL2; - end if; - - when ENABLE => - if (TSM_HREADY_N_IN = '0') then - mac_conf_next_state <= READY; - else - mac_conf_next_state <= ENABLE; - end if; - - when READY => - if (MC_RECONF_IN = '1') then - mac_conf_next_state <= DISABLE; - else - mac_conf_next_state <= READY; - end if; - - end case; - -end process MAC_CONF_MACHINE; - -HADDR_PROC : process(CLK) -begin - if rising_edge(CLK) then - case mac_conf_current_state is - when IDLE => - TSM_HADDR_OUT <= x"00"; - when DISABLE => - TSM_HADDR_OUT <= x"00"; - when WRITE_TX_RX_CTRL1 => - TSM_HADDR_OUT <= x"02"; - when WRITE_TX_RX_CTRL2 => - TSM_HADDR_OUT <= x"03"; - when ENABLE => - TSM_HADDR_OUT <= x"00"; - when READY => - TSM_HADDR_OUT <= x"00"; - end case; - end if; -end process HADDR_PROC; - -HDATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - case mac_conf_current_state is - when IDLE => - TSM_HDATA_OUT <= x"00"; - when DISABLE => - TSM_HDATA_OUT <= x"00"; - when WRITE_TX_RX_CTRL1 => - TSM_HDATA_OUT <= reg_tx_rx_ctrl1; - when WRITE_TX_RX_CTRL2 => - TSM_HDATA_OUT <= reg_tx_rx_ctrl2; - when ENABLE => - TSM_HDATA_OUT <= reg_mode; - when READY => - TSM_HDATA_OUT <= x"00"; - end case; - end if; -end process HDATA_PROC; - -process(CLK) -begin - if rising_edge(CLK) then - if (mac_conf_current_state = IDLE or mac_conf_current_state = READY) then - hcs_n <= '1'; - hwrite_n <= '1'; - elsif (TSM_HREADY_N_IN = '1') then - hcs_n <= '0'; - hwrite_n <= '0'; - else - hcs_n <= '1'; - hwrite_n <= '1'; - end if; - - if (mac_conf_current_state = READY) then - tsmac_ready <= '1'; - else - tsmac_ready <= '0'; - end if; - end if; -end process; - -TSM_HCS_N_OUT <= hcs_n; -TSM_HWRITE_N_OUT <= hwrite_n; -TSM_HREAD_N_OUT <= '1'; -MC_TSMAC_READY_OUT <= tsmac_ready; - - -end trb_net16_gbe_mac_control; - - diff --git a/gbe2_ecp3/trb_net16_gbe_main_control.vhd b/gbe2_ecp3/trb_net16_gbe_main_control.vhd deleted file mode 100644 index c430dc8..0000000 --- a/gbe2_ecp3/trb_net16_gbe_main_control.vhd +++ /dev/null @@ -1,957 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- controls the work of the whole gbe in both directions --- multiplexes the output between data stream and output slow control packets based on priority --- reacts to incoming gbe slow control commands --- - - -entity trb_net16_gbe_main_control is - generic( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0 - ); -port ( - CLK : in std_logic; -- system clock - CLK_125 : in std_logic; - RESET : in std_logic; - - MC_LINK_OK_OUT : out std_logic; - MC_RESET_LINK_IN : in std_logic; - MC_IDLE_TOO_LONG_OUT : out std_logic; - MC_DHCP_DONE_OUT : out std_logic; - --- signals to/from receive controller - RC_FRAME_WAITING_IN : in std_logic; - RC_LOADING_DONE_OUT : out std_logic; - RC_DATA_IN : in std_logic_vector(8 downto 0); - RC_RD_EN_OUT : out std_logic; - RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - - RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - --- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_RD_EN_IN : in std_logic; - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_TRANSMIT_DONE_IN : in std_logic; - --- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN : in std_logic; - --- signals to/from hub - MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); - - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - -- signal for data readout - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - CFG_ADDITIONAL_HDR_IN : in std_logic; - - MAKE_RESET_OUT : out std_logic; - --- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT : out std_logic_vector(7 downto 0); - TSM_HDATA_OUT : out std_logic_vector(7 downto 0); - TSM_HCS_N_OUT : out std_logic; - TSM_HWRITE_N_OUT : out std_logic; - TSM_HREAD_N_OUT : out std_logic; - TSM_HREADY_N_IN : in std_logic; - TSM_HDATA_EN_N_IN : in std_logic; - TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); - TSM_RX_STAT_EN_IN : in std_logic; - - - MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_OUT : out hist_array; - SCTRL_HIST_OUT : out hist_array -); -end trb_net16_gbe_main_control; - - -architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -signal tsm_ready : std_logic; -signal tsm_reconf : std_logic; -signal tsm_haddr : std_logic_vector(7 downto 0); -signal tsm_hdata : std_logic_vector(7 downto 0); -signal tsm_hcs_n : std_logic; -signal tsm_hwrite_n : std_logic; -signal tsm_hread_n : std_logic; - -type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS); -signal link_current_state, link_next_state : link_states; -attribute syn_encoding of link_current_state : signal is "onehot"; - -signal link_down_ctr : std_logic_vector(15 downto 0); -signal link_down_ctr_lock : std_logic; -signal link_ok : std_logic; -signal link_ok_timeout_ctr : std_logic_vector(15 downto 0); - -signal mac_control_debug : std_logic_vector(63 downto 0); - -type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP); -signal flow_current_state, flow_next_state : flow_states; -attribute syn_encoding of flow_current_state : signal is "onehot"; - -signal state : std_logic_vector(3 downto 0); -signal link_state : std_logic_vector(3 downto 0); -signal redirect_state : std_logic_vector(3 downto 0); - -signal ps_wr_en : std_logic; -signal ps_response_ready : std_logic; -signal ps_busy : std_logic_vector(c_MAX_PROTOCOLS -1 downto 0); -signal rc_rd_en : std_logic; -signal first_byte : std_logic; -signal first_byte_q : std_logic; -signal first_byte_qq : std_logic; -signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal loaded_bytes_ctr : std_Logic_vector(15 downto 0); - -signal dhcp_start : std_logic; -signal dhcp_done : std_logic; -signal wait_ctr : std_logic_vector(31 downto 0); - -signal rc_data_local : std_logic_vector(8 downto 0); - --- debug -signal frame_waiting_ctr : std_logic_vector(15 downto 0); -signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - -type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP); -signal redirect_current_state, redirect_next_state : redirect_states; -attribute syn_encoding of redirect_current_state : signal is "onehot"; - -signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic; - -type stats_states is (IDLE, LOAD_VECTOR, CLEANUP); -signal stats_current_state, stats_next_state : stats_states; - -signal stat_rdy, stat_ack : std_logic; -signal rx_stat_en_q : std_logic; -signal rx_stat_vec_q : std_logic_vector(31 downto 0); - -type array_of_ctrs is array(15 downto 0) of std_logic_vector(31 downto 0); -signal arr : array_of_ctrs; -signal stats_ctr : integer range 0 to 15; -signal stat_data : std_logic_vector(31 downto 0); -signal stat_addr : std_logic_vector(7 downto 0); - -signal unique_id : std_logic_vector(63 downto 0); - - -signal nothing_sent : std_logic; -signal nothing_sent_ctr : std_logic_vector(31 downto 0); - -signal dbg_ps : std_Logic_vector(63 downto 0); - -signal tc_data : std_logic_vector(8 downto 0); - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; -attribute syn_preserve of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; - -signal mc_busy : std_logic; - -begin - -unique_id <= MC_UNIQUE_ID_IN; - -protocol_selector : trb_net16_gbe_protocol_selector -generic map( - RX_PATH_ENABLE => RX_PATH_ENABLE, - DO_SIMULATION => DO_SIMULATION - ) -port map( - CLK => CLK, - RESET => RESET, - RESET_FOR_DHCP => MC_RESET_LINK_IN, - - PS_DATA_IN => rc_data_local, -- RC_DATA_IN, - PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en, - PS_PROTO_SELECT_IN => proto_select, - PS_BUSY_OUT => ps_busy, - PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN, - PS_RESPONSE_READY_OUT => ps_response_ready, - - PS_SRC_MAC_ADDRESS_IN => RC_SRC_MAC_ADDRESS_IN, - PS_DEST_MAC_ADDRESS_IN => RC_DEST_MAC_ADDRESS_IN, - PS_SRC_IP_ADDRESS_IN => RC_SRC_IP_ADDRESS_IN, - PS_DEST_IP_ADDRESS_IN => RC_DEST_IP_ADDRESS_IN, - PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN, - PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN, - - TC_DATA_OUT => tc_data, - TC_RD_EN_IN => TC_RD_EN_IN, - TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT, - TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT, - TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT, - TC_IDENT_OUT => TC_IDENT_OUT, - TC_DEST_MAC_OUT => TC_DEST_MAC_OUT, - TC_DEST_IP_OUT => TC_DEST_IP_OUT, - TC_DEST_UDP_OUT => TC_DEST_UDP_OUT, - TC_SRC_MAC_OUT => TC_SRC_MAC_OUT, - TC_SRC_IP_OUT => TC_SRC_IP_OUT, - TC_SRC_UDP_OUT => TC_SRC_UDP_OUT, - - MC_BUSY_IN => mc_busy, - - DHCP_START_IN => dhcp_start, - DHCP_DONE_OUT => dhcp_done, - - GSC_CLK_IN => GSC_CLK_IN, - GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - GSC_INIT_READ_IN => GSC_INIT_READ_IN, - GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, - GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, - GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, - GSC_BUSY_IN => GSC_BUSY_IN, - - MAKE_RESET_OUT => MAKE_RESET_OUT, - - -- CTS interface - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data payload interface - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- ip configurator - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - - CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, - CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, - CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, - CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, - CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, - CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, - CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, - CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, - CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, - CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, - CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, - CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, - CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, - - CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, - - -- input for statistics from outside - STAT_DATA_IN => stat_data, - STAT_ADDR_IN => stat_addr, - STAT_DATA_RDY_IN => stat_rdy, - STAT_DATA_ACK_OUT => stat_ack, - - MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT, - MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT, - MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT, - MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT, - MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT, - MONITOR_SELECT_DROP_IN_OUT => MONITOR_SELECT_DROP_IN_OUT, - MONITOR_SELECT_GEN_DBG_OUT => MONITOR_SELECT_GEN_DBG_OUT, - - DATA_HIST_OUT => DATA_HIST_OUT, - SCTRL_HIST_OUT => SCTRL_HIST_OUT -); - -TC_DATA_OUT <= tc_data; - --- gk 07.11.11 --- do not select any response constructors when dropping a frame -proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0'); - --- gk 07.11.11 -DISABLE_REDIRECT_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - disable_redirect <= '0'; - elsif (redirect_current_state = CHECK_TYPE) then - if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then - disable_redirect <= '1'; - elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then - disable_redirect <= '1'; - else - disable_redirect <= '0'; - end if; - else - disable_redirect <= disable_redirect; - end if; - end if; -end process DISABLE_REDIRECT_PROC; - --- warning -SYNC_PROC : process(CLK) -begin - if rising_edge(CLK) then - rc_data_local <= RC_DATA_IN; - end if; -end process SYNC_PROC; - -REDIRECT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - redirect_current_state <= IDLE; - elsif rising_edge(CLK) then - if RX_PATH_ENABLE = 1 then - redirect_current_state <= redirect_next_state; - else - redirect_current_state <= IDLE; - end if; - end if; -end process REDIRECT_MACHINE_PROC; - -REDIRECT_MACHINE : process(redirect_current_state, link_current_state, RC_FRAME_WAITING_IN, ps_busy, RC_FRAME_PROTO_IN, loaded_bytes_ctr, RC_FRAME_SIZE_IN) -begin - case redirect_current_state is - - when IDLE => - redirect_state <= x"1"; - if (RC_FRAME_WAITING_IN = '1') then - redirect_next_state <= CHECK_TYPE; - else - redirect_next_state <= IDLE; - end if; - - when CHECK_TYPE => - if (link_current_state = ACTIVE) then - redirect_next_state <= CHECK_BUSY; - elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then - redirect_next_state <= CHECK_BUSY; - else - redirect_next_state <= DROP; - end if; - - when DROP => - redirect_state <= x"7"; - if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then - redirect_next_state <= WAIT_ONE; - else - redirect_next_state <= DROP; - end if; - - when CHECK_BUSY => - redirect_state <= x"6"; - if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then - redirect_next_state <= LOAD; - else - redirect_next_state <= BUSY; - end if; - - when LOAD => - redirect_state <= x"2"; - if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then - redirect_next_state <= WAIT_ONE; - else - redirect_next_state <= LOAD; - end if; - - when BUSY => - redirect_state <= x"3"; - if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then - redirect_next_state <= LOAD; - else - redirect_next_state <= BUSY; - end if; - - when WAIT_ONE => - redirect_state <= x"f"; - redirect_next_state <= FINISH; - - when FINISH => - redirect_state <= x"4"; - redirect_next_state <= CLEANUP; - - when CLEANUP => - redirect_state <= x"5"; - redirect_next_state <= IDLE; - - end case; -end process REDIRECT_MACHINE; - -rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0'; -RC_RD_EN_OUT <= rc_rd_en; - -LOADING_DONE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then - RC_LOADING_DONE_OUT <= '1'; - else - RC_LOADING_DONE_OUT <= '0'; - end if; - end if; -end process LOADING_DONE_PROC; - -PS_WR_EN_PROC : process(CLK) -begin - if rising_edge(CLK) then - ps_wr_en <= rc_rd_en; - ps_wr_en_q <= ps_wr_en; - ps_wr_en_qq <= ps_wr_en_q; - end if; -end process PS_WR_EN_PROC; - -LOADED_BYTES_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (redirect_current_state = IDLE) then - loaded_bytes_ctr <= (others => '0'); - elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then - loaded_bytes_ctr <= loaded_bytes_ctr + x"1"; - else - loaded_bytes_ctr <= loaded_bytes_ctr; - end if; - end if; -end process LOADED_BYTES_CTR_PROC; - -FIRST_BYTE_PROC : process(CLK) -begin - if rising_edge(CLK) then - first_byte_q <= first_byte; - first_byte_qq <= first_byte_q; - - if (redirect_current_state = IDLE) then - first_byte <= '1'; - else - first_byte <= '0'; - end if; - end if; -end process FIRST_BYTE_PROC; - ---********************* --- DATA FLOW CONTROL - -FLOW_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - flow_current_state <= IDLE; - elsif rising_edge(CLK) then - flow_current_state <= flow_next_state; - end if; -end process FLOW_MACHINE_PROC; - -FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data) -begin - case flow_current_state is - - when IDLE => - if (ps_response_ready = '1') then - flow_next_state <= TRANSMIT_CTRL; - else - flow_next_state <= IDLE; - end if; - - when TRANSMIT_CTRL => - if (tc_data(8) = '1') then - flow_next_state <= WAIT_FOR_FC; - else - flow_next_state <= TRANSMIT_CTRL; - end if; - - when WAIT_FOR_FC => - if (TC_TRANSMIT_DONE_IN = '1') then - flow_next_state <= CLEANUP; - else - flow_next_state <= WAIT_FOR_FC; - end if; - - when CLEANUP => - flow_next_state <= IDLE; - - end case; -end process FLOW_MACHINE; - -process(CLK) -begin - if rising_edge(CLK) then - if (flow_current_state = IDLE and ps_response_ready = '1') then - TC_TRANSMIT_CTRL_OUT <= '1'; - else - TC_TRANSMIT_CTRL_OUT <= '0'; - end if; - - if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then - mc_busy <= '1'; - else - mc_busy <= '0'; - end if; - end if; -end process; - ---*********************** --- LINK STATE CONTROL - -lsm_impl_gen : if DO_SIMULATION = 0 generate - LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) - begin - if MC_RESET_LINK_IN = '1' then - link_current_state <= INACTIVE; - elsif rising_edge(CLK) then - if RX_PATH_ENABLE = 1 then - link_current_state <= link_next_state; - else - link_current_state <= INACTIVE; - end if; - end if; - end process; -end generate lsm_impl_gen; - -lsm_sim_gen : if DO_SIMULATION = 1 generate - LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) - begin - if MC_RESET_LINK_IN = '1' then - link_current_state <= GET_ADDRESS; - elsif rising_edge(CLK) then - if RX_PATH_ENABLE = 1 then - link_current_state <= link_next_state; - else - link_current_state <= ACTIVE; - end if; - end if; - end process; -end generate lsm_sim_gen; - -LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, tsm_ready, link_ok_timeout_ctr) -begin - case link_current_state is - - when INACTIVE => - link_state <= x"2"; - if (PCS_AN_COMPLETE_IN = '1') then - link_next_state <= TIMEOUT; - else - link_next_state <= INACTIVE; - end if; - - when TIMEOUT => - link_state <= x"3"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - if (link_ok_timeout_ctr = x"ffff") then - link_next_state <= ENABLE_MAC; --FINALIZE; - else - link_next_state <= TIMEOUT; - end if; - end if; - - when ENABLE_MAC => - link_state <= x"4"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - elsif (tsm_ready = '1') then - link_next_state <= FINALIZE; --INACTIVE; - else - link_next_state <= ENABLE_MAC; - end if; - - when FINALIZE => - link_state <= x"5"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - link_next_state <= WAIT_FOR_BOOT; --ACTIVE; - end if; - - when WAIT_FOR_BOOT => - link_state <= x"6"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - if (wait_ctr = x"0000_1000") then - link_next_state <= GET_ADDRESS; - else - link_next_state <= WAIT_FOR_BOOT; - end if; - end if; - - when GET_ADDRESS => - link_state <= x"7"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - if (dhcp_done = '1') then - link_next_state <= ACTIVE; - else - link_next_state <= GET_ADDRESS; - end if; - end if; - - when ACTIVE => - link_state <= x"1"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - link_next_state <= ACTIVE; - end if; - - end case; -end process LINK_STATE_MACHINE; - -MC_DHCP_DONE_OUT <= '1' when link_current_state = ACTIVE else '0'; - -LINK_OK_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - --if (RESET = '1') or (link_current_state /= TIMEOUT) then - if (link_current_state /= TIMEOUT) then - link_ok_timeout_ctr <= (others => '0'); - elsif (link_current_state = TIMEOUT) then - link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1"; - end if; - - if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then - link_ok <= '1'; - else - link_ok <= '0'; - end if; - - if (link_current_state = GET_ADDRESS) then - dhcp_start <= '1'; - else - dhcp_start <= '0'; - end if; - end if; -end process LINK_OK_CTR_PROC; - ---link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0'; - -WAIT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (link_current_state = WAIT_FOR_BOOT) then - wait_ctr <= wait_ctr + x"1"; - else - wait_ctr <= (others => '0'); - end if; - end if; -end process WAIT_CTR_PROC; - ---dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0'; - ---LINK_DOWN_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- link_down_ctr <= (others => '0'); --- link_down_ctr_lock <= '0'; --- elsif (PCS_AN_COMPLETE_IN = '1') then --- link_down_ctr_lock <= '0'; --- elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then --- link_down_ctr <= link_down_ctr + x"1"; --- link_down_ctr_lock <= '1'; --- end if; --- end if; ---end process LINK_DOWN_CTR_PROC; - -MC_LINK_OK_OUT <= link_ok; -- or nothing_sent; - --- END OF LINK STATE CONTROL ---************* - ---************* --- GENERATE MAC_ADDRESS -g_MY_MAC <= unique_id(31 downto 8) & x"be0002"; - ---************* - ---**************** --- TRI SPEED MAC CONTROLLER - -TSMAC_CONTROLLER : trb_net16_gbe_mac_control -port map( - CLK => CLK, - RESET => MC_RESET_LINK_IN, - --- signals to/from main controller - MC_TSMAC_READY_OUT => tsm_ready, - MC_RECONF_IN => tsm_reconf, - MC_GBE_EN_IN => '1', - MC_RX_DISCARD_FCS => '0', - MC_PROMISC_IN => '1', - MC_MAC_ADDR_IN => g_MY_MAC, --x"001122334455", - --- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT => tsm_haddr, - TSM_HDATA_OUT => tsm_hdata, - TSM_HCS_N_OUT => tsm_hcs_n, - TSM_HWRITE_N_OUT => tsm_hwrite_n, - TSM_HREAD_N_OUT => tsm_hread_n, - TSM_HREADY_N_IN => TSM_HREADY_N_IN, - TSM_HDATA_EN_N_IN => TSM_HDATA_EN_N_IN, - - DEBUG_OUT => open -); - ---DEBUG_OUT <= mac_control_debug; -process(CLK) -begin - if rising_edge(CLK) then - if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then - tsm_reconf <= '1'; - else - tsm_reconf <= '0'; - end if; - end if; -end process; ---tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0'; - -TSM_HADDR_OUT <= tsm_haddr; -TSM_HCS_N_OUT <= tsm_hcs_n; -TSM_HDATA_OUT <= tsm_hdata; -TSM_HREAD_N_OUT <= tsm_hread_n; -TSM_HWRITE_N_OUT <= tsm_hwrite_n; - --- END OF TRI SPEED MAC CONTROLLER ---*************** - - --- ***** --- STATISTICS --- ***** - --- ---CTRS_GEN : for n in 0 to 15 generate --- --- CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- arr(n) <= (others => '0'); --- elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then --- arr(n) <= arr(n) + x"1"; --- end if; --- end if; --- end process CTR_PROC; --- ---end generate CTRS_GEN; --- ---STAT_VEC_SYNC : signal_sync ---generic map ( --- WIDTH => 32, --- DEPTH => 2 ---) ---port map ( --- RESET => RESET, --- CLK0 => CLK, --- CLK1 => CLK, --- D_IN => TSM_RX_STAT_VEC_IN, --- D_OUT => rx_stat_vec_q ---); --- --- ---STAT_VEC_EN_SYNC : pulse_sync ---port map( --- CLK_A_IN => CLK_125, --- RESET_A_IN => RESET, --- PULSE_A_IN => TSM_RX_STAT_EN_IN, --- CLK_B_IN => CLK, --- RESET_B_IN => RESET, --- PULSE_B_OUT => rx_stat_en_q ---); --- --- ---STATS_MACHINE_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- stats_current_state <= IDLE; --- else --- stats_current_state <= stats_next_state; --- end if; --- end if; ---end process STATS_MACHINE_PROC; --- ---STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr) ---begin --- --- case (stats_current_state) is --- --- when IDLE => --- if (rx_stat_en_q = '1') then --- stats_next_state <= LOAD_VECTOR; --- else --- stats_next_state <= IDLE; --- end if; --- --- when LOAD_VECTOR => --- --if (stat_ack = '1') then --- if (stats_ctr = 15) then --- stats_next_state <= CLEANUP; --- else --- stats_next_state <= LOAD_VECTOR; --- end if; --- --- when CLEANUP => --- stats_next_state <= IDLE; --- --- end case; --- ---end process STATS_MACHINE; --- ---STATS_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') or (stats_current_state = IDLE) then --- stats_ctr <= 0; --- elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then --- stats_ctr <= stats_ctr + 1; --- end if; --- end if; ---end process STATS_CTR_PROC; --- -----stat_data <= arr(stats_ctr); --- ---stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8)); --- ---stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; --- ---stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24); ---stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16); ---stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8); ---stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0); - - --- **** debug ---FRAME_WAITING_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- frame_waiting_ctr <= (others => '0'); --- elsif (RC_FRAME_WAITING_IN = '1') then --- frame_waiting_ctr <= frame_waiting_ctr + x"1"; --- end if; --- end if; ---end process FRAME_WAITING_CTR_PROC; --- ---SAVE_VALUES_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- ps_busy_q <= (others => '0'); --- rc_frame_proto_q <= (others => '0'); --- elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then --- ps_busy_q <= ps_busy; --- rc_frame_proto_q <= RC_FRAME_PROTO_IN; --- end if; --- end if; ---end process SAVE_VALUES_PROC; - - --- **** - - - -end trb_net16_gbe_main_control; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd b/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd deleted file mode 100755 index 5e68bad..0000000 --- a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd +++ /dev/null @@ -1,1088 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; -use work.trb_net_gbe_components.all; - -entity trb_net16_gbe_packet_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10 - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 - PC_END_OF_DATA_IN : in std_logic; - PC_TRANSMIT_ON_OUT : out std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_PADDING_IN : in std_logic; -- gk 29.03.10 - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP - PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 - -- FrameConstructor ports - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(7 downto 0); - TC_H_READY_IN : in std_logic; - TC_READY_IN : in std_logic; - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_SOD_OUT : out std_logic; - TC_EOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_packet_constr; - -architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_GBE_group"; - -component fifo_64kx9 -port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - --- FIFO for SubEventHeader information -component fifo_16kx8 is -port ( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -signal df_wr_en : std_logic; -signal df_rd_en : std_logic; -signal df_q : std_logic_vector(7 downto 0); -signal df_q_reg : std_logic_vector(7 downto 0); -signal df_empty : std_logic; -signal df_full : std_logic; - -signal fc_data : std_logic_vector(7 downto 0); -signal fc_wr_en : std_logic; -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter! -signal fc_flags_offset : std_logic_vector(15 downto 0); - -signal shf_data : std_logic_vector(7 downto 0); -signal shf_wr_en : std_logic; -signal shf_rd_en : std_logic; -signal shf_q : std_logic_vector(7 downto 0); -signal shf_empty : std_logic; -signal shf_full : std_logic; - -type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD); -signal constructCurrentState, constructNextState : constructStates; -signal constr_state : std_logic_vector(3 downto 0); -signal all_int_ctr : integer range 0 to 31; -signal all_ctr : std_logic_vector(4 downto 0); - -type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM); -signal saveSubCurrentState, saveSubNextState : saveSubStates; -signal save_state : std_logic_vector(3 downto 0); -signal sub_int_ctr : integer range 0 to 31; -signal sub_ctr : std_logic_vector(4 downto 0); -signal my_int_ctr : integer range 0 to 3; -signal my_ctr : std_logic_vector(1 downto 0); - -type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY); -signal loadCurrentState, loadNextState: loadStates; -signal load_state : std_logic_vector(3 downto 0); - -signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination -signal queue_size_temp : std_logic_vector(31 downto 0); -signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid -signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame -signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf -signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted -signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent -signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet -signal size_left : std_logic_vector(31 downto 0); -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal max_frame_size : std_logic_vector(15 downto 0); -signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term -signal debug : std_logic_vector(63 downto 0); -signal pc_ready : std_logic; - -signal pc_sub_size : std_logic_vector(31 downto 0); -signal pc_trig_nr : std_logic_vector(31 downto 0); -signal rst_after_sub_comb : std_logic; -- gk 08.04.10 -signal rst_after_sub : std_logic; -- gk 08.04.10 -signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10 -signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10 -signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10 - --- gk 26.07.10 -signal load_eod : std_logic; -signal load_eod_q : std_logic; - --- gk 07.10.10 -signal df_eod : std_logic; - --- gk 04.12.10 -signal first_sub_in_multi : std_logic; -signal from_divide_state : std_logic; -signal disable_prep : std_logic; - -begin - - -PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0'; - -my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order -load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10 - -all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging -sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging -my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging - -max_frame_size <= PC_MAX_FRAME_SIZE_IN; - --- Ready signal for PacketConstructor -pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0'; - --- store event information on Start_of_Subevent -THE_EVT_INFO_STORE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( PC_START_OF_SUB_IN = '1' ) then - pc_sub_size <= PC_SUB_SIZE_IN; - pc_trig_nr <= PC_TRIG_NR_IN; - else - pc_sub_size <= pc_sub_size; - pc_trig_nr <= pc_trig_nr; - end if; - end if; -end process; - --- gk 07.10.10 -df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1')) - or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1')) - else '0'; - --- Data FIFO for incoming packet data from IPU buffer --- gk 26.07.10 -DATA_FIFO : fifo_64kx9 -port map( - Data(7 downto 0) => PC_DATA_IN, - Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10 - WrClock => CLK, - RdClock => CLK, - WrEn => df_wr_en, - RdEn => df_rd_en, - Reset => RESET, - RPReset => RESET, - Q(7 downto 0) => df_q, - Q(8) => load_eod, - Empty => df_empty, - Full => df_full -); - -LOAD_EOD_PROC : process(CLK) -begin - if rising_edge(CLK) then - load_eod_q <= load_eod; - end if; -end process LOAD_EOD_PROC; - --- Write enable for the data FIFO --- !!!combinatorial signal!!! --- could be avoided as IPU2GBE does only send data in case of PC_READY. -df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) - else '0'; - --- Output register for data FIFO -dfQProc : process(CLK) -begin - if rising_edge(CLK) then - df_q_reg <= df_q; - end if; -end process dfQProc; - --- Construction state machine -constructMachineProc : process(RESET, CLK) -begin - if RESET = '1' then - constructCurrentState <= CIDLE; - elsif rising_edge(CLK) then --- if (RESET = '1') then --- constructCurrentState <= CIDLE; --- else - constructCurrentState <= constructNextState; --- end if; - end if; -end process constructMachineProc; - -constructMachine : process(constructCurrentState, df_empty, PC_START_OF_SUB_IN, PC_END_OF_DATA_IN, loadCurrentState) -begin - case constructCurrentState is - when CIDLE => - constr_state <= x"1"; - --if( PC_WR_EN_IN = '1' ) then - -- gk 04.12.10 - if (PC_START_OF_SUB_IN = '1') then - - constructNextState <= SAVE_DATA; - else - constructNextState <= CIDLE; - end if; - when SAVE_DATA => - constr_state <= x"2"; - if( PC_END_OF_DATA_IN = '1') then - constructNextState <= WAIT_FOR_LOAD; - else - constructNextState <= SAVE_DATA; - end if; - when WAIT_FOR_LOAD => - constr_state <= x"3"; - if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted - constructNextState <= CIDLE; - else - constructNextState <= WAIT_FOR_LOAD; - end if; - when others => - constr_state <= x"f"; - constructNextState <= CIDLE; - end case; -end process constructMachine; - ---*********************** --- SIZE COUNTERS FOR SAVING SIDE ---*********************** - --- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size --- that's why they are removed if pc_padding flag is asserted -sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0') - else (x"c" + pc_sub_size); -- subevent headers + data - --- BUG HERE BUG HERE BUG HERE BUG HERE --- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents -queueSizeProc : process(RESET, CLK) -begin - if (RESET = '1') then - queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination - elsif rising_edge(CLK) then - --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then - if (loadCurrentState = CLEANUP) then - queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination - elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then - queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers - else - queue_size <= queue_size; - end if; - end if; -end process queueSizeProc; - - ---*********************** --- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION ---*********************** - -loadMachineProc : process(RESET, CLK) -begin - if RESET = '1' then - loadCurrentState <= LIDLE; - elsif rising_edge(CLK) then --- if (RESET = '1') then --- loadCurrentState <= LIDLE; --- else - loadCurrentState <= loadNextState; --- end if; - end if; -end process loadMachineProc; - -loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty, - size_left, TC_H_READY_IN, - max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN, - delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN) -begin - case loadCurrentState is - when LIDLE => - load_state <= x"1"; - if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then - loadNextState <= WAIT_FOR_FC; - else - loadNextState <= LIDLE; - end if; - when WAIT_FOR_FC => - load_state <= x"2"; - if (TC_H_READY_IN = '1') then - loadNextState <= PUT_Q_LEN; - else - loadNextState <= WAIT_FOR_FC; - end if; - when PUT_Q_LEN => - load_state <= x"3"; - if (all_int_ctr = 3) then - loadNextState <= PUT_Q_DEC; - else - loadNextState <= PUT_Q_LEN; - end if; - when PUT_Q_DEC => - load_state <= x"4"; - if (all_int_ctr = 3) then - loadNextState <= LOAD_SUB; - else - loadNextState <= PUT_Q_DEC; - end if; - when LOAD_SUB => - load_state <= x"5"; - if (bytes_loaded = max_frame_size - 1) then - loadNextState <= DIVIDE; - elsif (all_int_ctr = 15) then - loadNextState <= PREP_DATA; - else - loadNextState <= LOAD_SUB; - end if; - when PREP_DATA => - load_state <= x"6"; - loadNextState <= LOAD_DATA; - when LOAD_DATA => - load_state <= x"7"; --- if (bytes_loaded = max_frame_size - 1) then --- loadNextState <= DIVIDE; --- -- gk 07.10.10 --- elsif (MULT_EVT_ENABLE_IN = '1') then --- if (size_left = x"0000_0023") then --- loadNextState <= LOAD_TERM; --- elsif (load_eod_q = '1') then --- loadNextState <= LOAD_SUB; --- else --- loadNextState <= LOAD_DATA; --- end if; --- else --- if (load_eod_q = '1') then --- loadNextState <= LOAD_TERM; --- else --- loadNextState <= LOAD_DATA; --- end if; --- end if; - if (bytes_loaded = max_frame_size - 1) then - loadNextState <= DIVIDE; - -- gk 07.10.10 - elsif (load_eod_q = '1') then - if (MULT_EVT_ENABLE_IN = '1') then - if (size_left < x"0000_0030") then - loadNextState <= LOAD_TERM; - else - loadNextState <= LOAD_SUB; - end if; - else - loadNextState <= LOAD_TERM; - end if; - else - loadNextState <= LOAD_DATA; - end if; - when DIVIDE => - load_state <= x"8"; - if (TC_H_READY_IN = '1') then - if (divide_position = "00") then - loadNextState <= PREP_DATA; - elsif (divide_position = "01") then - loadNextState <= LOAD_SUB; - else - loadNextState <= LOAD_TERM; - end if; - else - loadNextState <= DIVIDE; - end if; - when LOAD_TERM => - load_state <= x"9"; - if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then - loadNextState <= DIVIDE; - elsif (all_int_ctr = 31) then - loadNextState <= CLEANUP; - else - loadNextState <= LOAD_TERM; - end if; - -- gk 28.04.10 - when CLEANUP => - load_state <= x"a"; - if (PC_DELAY_IN = x"0000_0000") then - loadNextState <= LIDLE; - else - loadNextState <= DELAY; - end if; - -- gk 28.04.10 - when DELAY => - load_state <= x"b"; - if (delay_ctr = x"0000_0000") then - loadNextState <= LIDLE; - else - loadNextState <= DELAY; - end if; - when others => - load_state <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- gk 04.12.10 -firstSubInMultiProc : process(RESET, CLK) -begin - if (RESET = '1') then - first_sub_in_multi <= '1'; - elsif rising_edge(CLK) then - if (loadCurrentState = LOAD_TERM) then - first_sub_in_multi <= '1'; - elsif (loadCurrentState = LOAD_DATA) then - first_sub_in_multi <= '0'; - else - first_sub_in_multi <= first_sub_in_multi; - end if; - end if; -end process; - --- gk 04.12.10 -fromDivideStateProc : process(RESET, CLK) -begin - if (RESET = '1') then - from_divide_state <= '0'; - elsif rising_edge(CLK) then - if (loadCurrentState = DIVIDE) then - from_divide_state <= '1'; - elsif (loadCurrentState = PREP_DATA) then - from_divide_state <= '0'; - else - from_divide_state <= from_divide_state; - end if; - end if; -end process fromDivideStateProc; - - -dividePositionProc : process(RESET, CLK) -begin - if (RESET = '1') then - divide_position <= "00"; - disable_prep <= '0'; - elsif rising_edge(CLK) then - if (bytes_loaded = max_frame_size - 1) then - if (loadCurrentState = LIDLE) then - divide_position <= "00"; - disable_prep <= '0'; -- gk 05.12.10 - elsif (loadCurrentState = LOAD_DATA) then - -- gk 05.12.10 - -- gk 26.07.10 - if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term - divide_position <= "11"; - disable_prep <= '0'; -- gk 05.12.10 - elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then - if (size_left > x"0000_0028") then - divide_position <= "01"; - disable_prep <= '0'; -- gk 05.12.10 - else - divide_position <= "11"; - disable_prep <= '0'; -- gk 05.12.10 - end if; - else - divide_position <= "00"; -- still data loaded divide on data - disable_prep <= '1'; -- gk 05.12.10 - end if; - elsif (loadCurrentState = LOAD_SUB) then - if (all_int_ctr = 15) then - divide_position <= "00"; - disable_prep <= '1'; -- gk 05.12.10 - else - divide_position <= "01"; - disable_prep <= '0'; -- gk 05.12.10 - end if; - elsif (loadCurrentState = LOAD_TERM) then - divide_position <= "11"; - disable_prep <= '0'; -- gk 05.12.10 - else - divide_position <= divide_position; - disable_prep <= disable_prep; - end if; - elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep - disable_prep <= '0'; - divide_position <= divide_position; - else - divide_position <= divide_position; - disable_prep <= disable_prep; - end if; - - end if; -end process dividePositionProc; - -allIntCtrProc : process(CLK) -begin - if rising_edge(CLK) then - case loadCurrentState is - - when LIDLE => all_int_ctr <= 0; - - when WAIT_FOR_FC => all_int_ctr <= 0; - - when PUT_Q_LEN => - if (all_int_ctr = 3) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when PUT_Q_DEC => - if (all_int_ctr = 3) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when LOAD_SUB => - if (all_int_ctr = 15) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when LOAD_DATA => all_int_ctr <= 0; - - when LOAD_TERM => - if (all_int_ctr = 31) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when DIVIDE => null; - - when CLEANUP => all_int_ctr <= 0; - - when PREP_DATA => all_int_ctr <= 0; - - when DELAY => all_int_ctr <= 0; - end case; - end if; -end process allIntCtrProc; - -dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, all_int_ctr, load_eod_q) -begin - if (loadCurrentState = LOAD_DATA) then --- if (bytes_loaded = max_frame_size - x"1") then --- df_rd_en <= '0'; --- -- gk 07.10.10 --- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then --- df_rd_en <= '0'; --- -- gk 07.10.10 --- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then --- df_rd_en <= '0'; --- else --- df_rd_en <= '1'; --- end if; - if (bytes_loaded = max_frame_size - x"1") then - df_rd_en <= '0'; - -- gk 26.07.10 - --elsif (load_eod = '1') or (load_eod_q = '1') then - elsif (load_eod_q = '1') then - df_rd_en <= '0'; --- elsif (sub_bytes_loaded = sub_size_loaded) then --- df_rd_en <= '0'; - else - df_rd_en <= '1'; - end if; - - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then - df_rd_en <= '1'; - elsif (loadCurrentState = PREP_DATA) then - df_rd_en <= '1'; - else - df_rd_en <= '0'; - end if; -end process dfRdEnProc; - -shfRdEnProc : process(loadCurrentState, all_int_ctr) -begin - if (loadCurrentState = LOAD_SUB) then - shf_rd_en <= '1'; - elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then - shf_rd_en <= '1'; - elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then - shf_rd_en <= '1'; - else - shf_rd_en <= '0'; - end if; -end process shfRdEnProc; - - -fcWrEnProc : process(loadCurrentState, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep) -begin - if (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then - fc_wr_en <= '1'; - elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then - fc_wr_en <= '1'; - -- gk 04.12.10 - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then - fc_wr_en <= '1'; - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then - fc_wr_en <= '1'; - else - fc_wr_en <= '0'; - end if; -end process fcWrEnProc; - - --- was all_int_ctr -fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr) -begin - case loadCurrentState is - when LIDLE => fc_data <= x"af"; - when WAIT_FOR_FC => fc_data <= x"bf"; - -- gk 08.04.10 my_int_ctr changed to load_int_ctr - when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8); - when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8); - when LOAD_SUB => fc_data <= shf_q; - when PREP_DATA => fc_data <= df_q_reg; - when LOAD_DATA => fc_data <= df_q_reg; - when LOAD_TERM => fc_data <= shf_q; - when DIVIDE => fc_data <= x"cf"; - when CLEANUP => fc_data <= x"df"; - when others => fc_data <= x"00"; - end case; -end process fcDataProc; - --- delay counters --- gk 28.04.10 -DELAY_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LIDLE) then - delay_ctr <= PC_DELAY_IN; - elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then - delay_ctr <= delay_ctr - x"1"; - else - delay_ctr <= delay_ctr; - end if; - end if; -end process DELAY_CTR_PROC; - --- gk 28.04.10 -TICKS_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then - ticks_ctr <= x"00"; - elsif (loadCurrentState = DELAY) then - ticks_ctr <= ticks_ctr + x"1"; - else - ticks_ctr <= ticks_ctr; - end if; - end if; -end process TICKS_CTR_PROC; - - ---*********************** --- SIZE COUNTERS FOR LOADING SIDE ---*********************** - -queue_size_temp <= queue_size - x"20"; -- size of data without termination - --- gk 08.04.10 -rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or - ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) - else '0'; - --- gk 08.04.10 -RST_AFTER_SUB_PROC : process(CLK) -begin - if(rising_edge(CLK)) then - rst_after_sub <= rst_after_sub_comb; - end if; -end process RST_AFTER_SUB_PROC; - --- counts all bytes loaded to divide data into frames -bytesLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then - bytes_loaded <= x"0000"; - elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then - bytes_loaded <= bytes_loaded + x"1"; - -- gk 05.12.10 --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then --- bytes_loaded <= bytes_loaded + x"1"; - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then - bytes_loaded <= bytes_loaded + x"1"; - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then - bytes_loaded <= bytes_loaded + x"1"; - else - bytes_loaded <= bytes_loaded; - end if; - end if; -end process bytesLoadedProc; - --- size of subevent loaded from memory -subSizeLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10 - sub_size_loaded <= x"00000000"; - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then - -- was all_int_ctr - -- gk 08.04.10 my_int_ctr changed to load_int_ctr - sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q; - -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then - sub_size_loaded <= sub_size_loaded + x"4"; - else - sub_size_loaded <= sub_size_loaded; - end if; - end if; -end process subSizeLoadedProc; - --- counts only raw data bytes being loaded -subBytesLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10 - sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count - elsif (loadCurrentState = LOAD_DATA) then - sub_bytes_loaded <= sub_bytes_loaded + x"1"; - else - sub_bytes_loaded <= sub_bytes_loaded; - end if; - end if; -end process subBytesLoadedProc; - --- counts the size of the large udp packet -actualPacketProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - actual_packet_size <= x"0008"; - elsif (fc_wr_en = '1') then - actual_packet_size <= actual_packet_size + x"1"; - else - actual_packet_size <= actual_packet_size; - end if; - end if; -end process actualPacketProc; - -actualQueueSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = CLEANUP) then - actual_queue_size <= (others => '0'); - elsif (loadCurrentState = LIDLE) then - actual_queue_size <= queue_size; - else - actual_queue_size <= actual_queue_size; - end if; - end if; -end process actualQueueSizeProc; - --- amount of bytes left to send in current packet -sizeLeftProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = CLEANUP) then - size_left <= (others => '0'); - elsif (loadCurrentState = LIDLE) then - size_left <= queue_size; - elsif (fc_wr_en = '1') then - size_left <= size_left - 1; - else - size_left <= size_left; - end if; - end if; -end process sizeLeftProc; - --- HOT FIX: don't rely on CTS information, count the packets on your own. --- In this case, we increment the fragmented packet ID with EOD from ipu2gbe. -THE_FC_IDENT_COUNTER_PROC: process(RESET, CLK) -begin - if (RESET = '1') then - fc_ident <= (others => '0'); - elsif rising_edge(CLK) then - if (PC_END_OF_DATA_IN = '1') then - fc_ident <= fc_ident + 1; - else - fc_ident <= fc_ident; - end if; - end if; -end process THE_FC_IDENT_COUNTER_PROC; - -fc_flags_offset(15 downto 14) <= "00"; - -moreFragmentsProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - fc_flags_offset(13) <= '0'; - elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then - if ((actual_queue_size - actual_packet_size) < max_frame_size) then - fc_flags_offset(13) <= '0'; -- no more fragments - else - fc_flags_offset(13) <= '1'; -- more fragments - end if; - else - fc_flags_offset(13) <= fc_flags_offset(13); - end if; - end if; -end process moreFragmentsProc; - -eodProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then - fc_eod <= '1'; - elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then - fc_eod <= '1'; - elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then - fc_eod <= '1'; - else - fc_eod <= '0'; - end if; - end if; -end process eodProc; - -sodProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then - fc_sod <= '1'; - elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then - fc_sod <= '1'; - else - fc_sod <= '0'; - end if; - end if; -end process sodProc; - -offsetProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - fc_flags_offset(12 downto 0) <= (others => '0'); - elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then - fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3); - else - fc_flags_offset(12 downto 0) <= fc_flags_offset(12 downto 0); - end if; - end if; -end process offsetProc; - -fcIPSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then - if (size_left >= max_frame_size) then - fc_ip_size <= max_frame_size; - else - fc_ip_size <= size_left(15 downto 0); - end if; - else - fc_ip_size <= fc_ip_size; - end if; - end if; -end process fcIPSizeProc; - -fcUDPSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then - fc_udp_size <= queue_size(15 downto 0); - else - fc_udp_size <= fc_udp_size; - end if; - end if; -end process fcUDPSizeProc; - - ---*********************** --- SUBEVENT HEADERS WRITE AND READ ---*********************** - -SUBEVENT_HEADERS_FIFO : fifo_4kx8_ecp3 --fifo_16kx8 -port map( - Data => shf_data, - WrClock => CLK, - RdClock => CLK, - WrEn => shf_wr_en, - RdEn => shf_rd_en, - Reset => RESET, - RPReset => RESET, - Q => shf_q, - Empty => shf_empty, - Full => shf_full -); - --- write enable for SHF -shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA)) - else '0'; - --- data multiplexing for SHF (convert 32bit LWs to 8bit) --- CHANGED. --- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC. -shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, - pc_trig_nr, my_int_ctr, fc_data) -begin - case saveSubCurrentState is - when SIDLE => shf_data <= x"ac"; - when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_TERM => shf_data <= fc_data; - when others => shf_data <= x"00"; - end case; -end process shfDataProc; - -saveSubMachineProc : process(RESET, CLK) -begin - if RESET = '1' then - saveSubCurrentState <= SIDLE; - elsif rising_edge(CLK) then --- if (RESET = '1') then --- saveSubCurrentState <= SIDLE; --- else - saveSubCurrentState <= saveSubNextState; --- end if; - end if; -end process saveSubMachineProc; - -saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN) -begin - case saveSubCurrentState is - when SIDLE => - save_state <= x"1"; - if (PC_START_OF_SUB_IN = '1') then - saveSubNextState <= SAVE_SIZE; - -- this branch is dangerous! - elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len - saveSubNextState <= SAVE_TERM; - else - saveSubNextState <= SIDLE; - end if; - when SAVE_SIZE => - save_state <= x"2"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_DECODING; - else - saveSubNextState <= SAVE_SIZE; - end if; - when SAVE_DECODING => - save_state <= x"3"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_ID; - else - saveSubNextState <= SAVE_DECODING; - end if; - when SAVE_ID => - save_state <= x"4"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_TRIG_NR; - else - saveSubNextState <= SAVE_ID; - end if; - when SAVE_TRIG_NR => - save_state <= x"5"; - if (sub_int_ctr = 3) then - saveSubNextState <= SIDLE; - else - saveSubNextState <= SAVE_TRIG_NR; - end if; - when SAVE_TERM => - save_state <= x"6"; - if (sub_int_ctr = 31) then - saveSubNextState <= SIDLE; - else - saveSubNextState <= SAVE_TERM; - end if; - when others => - save_state <= x"f"; - saveSubNextState <= SIDLE; - end case; -end process; - --- This counter is used for breaking down 32bit information words into 8bit bytes for --- storing them in the SHF. --- It is also used for the termination 32byte sequence. -subIntProc: process( CLK ) -begin - if rising_edge(CLK) then - if (saveSubCurrentState = SIDLE) then - sub_int_ctr <= 0; - elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then - sub_int_ctr <= 0; - elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then - sub_int_ctr <= 0; - elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then - sub_int_ctr <= sub_int_ctr + 1; - else - sub_int_ctr <= sub_int_ctr; - end if; - end if; -end process subIntProc; - ---debug(3 downto 0) <= constr_state; ---debug(7 downto 4) <= save_state; ---debug(11 downto 8) <= load_state; ---debug(27 downto 12) <= queue_size(15 downto 0); ---debug(28) <= df_full; ---debug(29) <= df_empty; ---debug(30) <= shf_full; ---debug(31) <= shf_empty; --- ---debug(47 downto 32) <= size_left(15 downto 0); ---debug(52 downto 48) <= all_ctr; ---debug(53) <= pc_ready; - --- outputs -PC_READY_OUT <= pc_ready; -TC_WR_EN_OUT <= fc_wr_en; -TC_DATA_OUT <= fc_data; -TC_IP_SIZE_OUT <= fc_ip_size; -TC_UDP_SIZE_OUT <= fc_udp_size; --- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); --- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); -TC_FLAGS_OFFSET_OUT <= fc_flags_offset; -TC_SOD_OUT <= fc_sod; -TC_EOD_OUT <= fc_eod; - -process(CLK) -begin - if rising_edge(CLK) then - DEBUG_OUT(3 downto 0) <= constr_state; - DEBUG_OUT(7 downto 4) <= load_state; - DEBUG_OUT(11 downto 8) <= save_state; - DEBUG_OUT(12) <= df_full; - DEBUG_OUT(13) <= df_empty; - DEBUG_OUT(14) <= shf_full; - DEBUG_OUT(15) <= shf_empty; - end if; -end process; -DEBUG_OUT(63 downto 16) <= (others => '0'); - -end trb_net16_gbe_packet_constr; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_packet_constr_20101006.vhd b/gbe2_ecp3/trb_net16_gbe_packet_constr_20101006.vhd deleted file mode 100644 index 1102f44..0000000 --- a/gbe2_ecp3/trb_net16_gbe_packet_constr_20101006.vhd +++ /dev/null @@ -1,958 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_packet_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_DATA_IN : in std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_PADDING_IN : in std_logic; -- gk 29.03.10 - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP - PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 - -- FrameConstructor ports - FC_WR_EN_OUT : out std_logic; - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_H_READY_IN : in std_logic; - FC_READY_IN : in std_logic; - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_packet_constr; - -architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr_group"; - -component fifo_64kx9 -port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - --- FIFO for SubEventHeader information -component fifo_2048x8 is -port ( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -signal df_wr_en : std_logic; -signal df_rd_en : std_logic; -signal df_q : std_logic_vector(7 downto 0); -signal df_q_reg : std_logic_vector(7 downto 0); -signal df_empty : std_logic; -signal df_full : std_logic; - -signal fc_data : std_logic_vector(7 downto 0); -signal fc_wr_en : std_logic; -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter! -signal fc_flags_offset : std_logic_vector(15 downto 0); - -signal shf_data : std_logic_vector(7 downto 0); -signal shf_wr_en : std_logic; -signal shf_rd_en : std_logic; -signal shf_q : std_logic_vector(7 downto 0); -signal shf_empty : std_logic; -signal shf_full : std_logic; - -type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD); -signal constructCurrentState, constructNextState : constructStates; -signal constr_state : std_logic_vector(3 downto 0); -signal all_int_ctr : integer range 0 to 31; -signal all_ctr : std_logic_vector(4 downto 0); - -type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM); -signal saveSubCurrentState, saveSubNextState : saveSubStates; -signal save_state : std_logic_vector(3 downto 0); -signal sub_int_ctr : integer range 0 to 31; -signal sub_ctr : std_logic_vector(4 downto 0); -signal my_int_ctr : integer range 0 to 3; -signal my_ctr : std_logic_vector(1 downto 0); - -type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY); -signal loadCurrentState, loadNextState: loadStates; -signal load_state : std_logic_vector(3 downto 0); - -signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination -signal queue_size_temp : std_logic_vector(31 downto 0); -signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid -signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame -signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf -signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted -signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent -signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet -signal size_left : std_logic_vector(31 downto 0); -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal max_frame_size : std_logic_vector(15 downto 0); -signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term -signal debug : std_logic_vector(63 downto 0); -signal pc_ready : std_logic; - -signal pc_sub_size : std_logic_vector(31 downto 0); -signal pc_trig_nr : std_logic_vector(31 downto 0); -signal rst_after_sub_comb : std_logic; -- gk 08.04.10 -signal rst_after_sub : std_logic; -- gk 08.04.10 -signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10 -signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10 -signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10 - --- gk 26.07.10 -signal load_eod : std_logic; -signal load_eod_q : std_logic; - -begin - --- Fakes ---debug <= (others => '0'); - -my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order -load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10 - -all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging -sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging -my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging - -max_frame_size <= PC_MAX_FRAME_SIZE_IN; - --- Ready signal for PacketConstructor -pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0'; - --- store event information on Start_of_Subevent -THE_EVT_INFO_STORE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if (RESET = '1') then -- gk 31.05.10 - pc_sub_size <= (others => '0'); - pc_trig_nr <= (others => '0'); - elsif( PC_START_OF_SUB_IN = '1' ) then - pc_sub_size <= PC_SUB_SIZE_IN; - pc_trig_nr <= PC_TRIG_NR_IN; - end if; - end if; -end process; - --- Data FIFO for incoming packet data from IPU buffer --- gk 26.07.10 -DATA_FIFO : fifo_64kx9 -port map( - Data(7 downto 0) => PC_DATA_IN, - Data(8) => PC_END_OF_DATA_IN, - WrClock => CLK, - RdClock => CLK, - WrEn => df_wr_en, - RdEn => df_rd_en, - Reset => RESET, - RPReset => RESET, - Q(7 downto 0) => df_q, - Q(8) => load_eod, - Empty => df_empty, - Full => df_full -); - -LOAD_EOD_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - load_eod_q <= '0'; - else - load_eod_q <= load_eod; - end if; - end if; -end process LOAD_EOD_PROC; - --- Write enable for the data FIFO --- !!!combinatorial signal!!! --- could be avoided as IPU2GBE does only send data in case of PC_READY. -df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) - else '0'; - --- Output register for data FIFO -dfQProc : process(CLK) -begin - if rising_edge(CLK) then - df_q_reg <= df_q; - end if; -end process dfQProc; - --- Construction state machine -constructMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - constructCurrentState <= CIDLE; - else - constructCurrentState <= constructNextState; - end if; - end if; -end process constructMachineProc; - -constructMachine : process(constructCurrentState, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr) -begin - case constructCurrentState is - when CIDLE => - constr_state <= x"0"; - if( PC_WR_EN_IN = '1' ) then - constructNextState <= SAVE_DATA; - else - constructNextState <= CIDLE; - end if; - when SAVE_DATA => - constr_state <= x"1"; - if( PC_END_OF_DATA_IN = '1' ) then - constructNextState <= WAIT_FOR_LOAD; - else - constructNextState <= SAVE_DATA; - end if; - when WAIT_FOR_LOAD => - constr_state <= x"2"; - if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted - constructNextState <= CIDLE; - else - constructNextState <= WAIT_FOR_LOAD; - end if; - when others => - constr_state <= x"f"; - constructNextState <= CIDLE; - end case; -end process constructMachine; - ---*********************** --- SIZE COUNTERS FOR SAVING SIDE ---*********************** - --- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size --- that's why they are removed if pc_padding flag is asserted -sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0') - else (x"c" + pc_sub_size); -- subevent headers + data - --- BUG HERE BUG HERE BUG HERE BUG HERE --- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents -queueSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = CLEANUP) then - queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination - elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then - queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers - end if; - end if; -end process queueSizeProc; - - ---*********************** --- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION ---*********************** - -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loadCurrentState <= LIDLE; - else - loadCurrentState <= loadNextState; - end if; - end if; -end process loadMachineProc; - -loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty, - sub_bytes_loaded, sub_size_loaded, size_left, FC_H_READY_IN, max_frame_size, - bytes_loaded, divide_position, PC_DELAY_IN, delay_ctr, load_eod_q) -begin - case loadCurrentState is - when LIDLE => - load_state <= x"0"; - if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then - loadNextState <= WAIT_FOR_FC; - else - loadNextState <= LIDLE; - end if; - when WAIT_FOR_FC => - load_state <= x"1"; - if (FC_H_READY_IN = '1') then - loadNextState <= PUT_Q_LEN; - else - loadNextState <= WAIT_FOR_FC; - end if; - when PUT_Q_LEN => - load_state <= x"2"; - if (all_int_ctr = 3) then - loadNextState <= PUT_Q_DEC; - else - loadNextState <= PUT_Q_LEN; - end if; - when PUT_Q_DEC => - load_state <= x"3"; - if (all_int_ctr = 3) then - loadNextState <= LOAD_SUB; - else - loadNextState <= PUT_Q_DEC; - end if; - when LOAD_SUB => - load_state <= x"4"; - if (bytes_loaded = max_frame_size - 1) then - loadNextState <= DIVIDE; - elsif (all_int_ctr = 15) then - loadNextState <= PREP_DATA; - else - loadNextState <= LOAD_SUB; - end if; - when PREP_DATA => - load_state <= x"5"; - loadNextState <= LOAD_DATA; - when LOAD_DATA => - load_state <= x"6"; - if (bytes_loaded = max_frame_size - 1) then - loadNextState <= DIVIDE; - -- gk 26.07.10 - -- close packet after one event loaded - elsif (load_eod_q = '1') then - loadNextState <= LOAD_TERM; --- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded --- if (size_left = x"00000021") then -- and there is no more data, only termination left --- -- gk 21.07.10 --- if (PC_SKIP_TERM_IN = '0') then --- loadNextState <= LOAD_TERM; -- add termination and close packet --- else --- loadNextState <= CLEANUP; --- end if; --- else -- there is more data in fifo --- loadNextState <= LOAD_SUB; -- add another subevent --- end if; - else - loadNextState <= LOAD_DATA; - end if; - when DIVIDE => - load_state <= x"7"; - if (FC_H_READY_IN = '1') then - if (divide_position = "00") then - loadNextState <= PREP_DATA; - elsif (divide_position = "01") then - loadNextState <= LOAD_SUB; - else - loadNextState <= LOAD_TERM; - end if; - else - loadNextState <= DIVIDE; - end if; - when LOAD_TERM => - load_state <= x"8"; - if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then - loadNextState <= DIVIDE; - elsif (all_int_ctr = 31) then - loadNextState <= CLEANUP; - else - loadNextState <= LOAD_TERM; - end if; - -- gk 28.04.10 - when CLEANUP => - load_state <= x"9"; - if (PC_DELAY_IN = x"0000_0000") then - loadNextState <= LIDLE; - else - loadNextState <= DELAY; - end if; - -- gk 28.04.10 - when DELAY => - load_state <= x"a"; - if (delay_ctr = x"0000_0000") then - loadNextState <= LIDLE; - else - loadNextState <= DELAY; - end if; - when others => - load_state <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - -dividePositionProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - divide_position <= "00"; - elsif (bytes_loaded = max_frame_size - 1) then - if (loadCurrentState = LIDLE) then - divide_position <= "00"; - elsif (loadCurrentState = LOAD_DATA) then - -- gk 26.07.10 - if (load_eod_q = '1') then -- if termination is about to be loaded divide on term - divide_position <= "11"; - else - divide_position <= "00"; -- still data loaded divide on data --- if (sub_bytes_loaded = sub_size_loaded) and (size_left = x"00000021") then --- divide_position <= "11"; --- elsif (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021") then --- divide_position <= "01"; --- else --- divide_position <= "00"; - end if; - elsif (loadCurrentState = LOAD_SUB) then - if (all_int_ctr = 15) then - divide_position <= "00"; - else - divide_position <= "01"; - end if; - elsif (loadCurrentState = LOAD_TERM) then - divide_position <= "11"; - end if; - end if; - end if; -end process dividePositionProc; - -allIntCtrProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then -- gk 31.05.10 - all_int_ctr <= 0; - else - case loadCurrentState is - - when LIDLE => all_int_ctr <= 0; - - when WAIT_FOR_FC => all_int_ctr <= 0; - - when PUT_Q_LEN => - if (all_int_ctr = 3) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when PUT_Q_DEC => - if (all_int_ctr = 3) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when LOAD_SUB => - if (all_int_ctr = 15) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when LOAD_DATA => all_int_ctr <= 0; - - when LOAD_TERM => - if (all_int_ctr = 31) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when DIVIDE => null; --all_int_ctr <= all_int_ctr; - - when CLEANUP => all_int_ctr <= 0; - - when PREP_DATA => all_int_ctr <= 0; - - when DELAY => all_int_ctr <= 0; - end case; - end if; - end if; -end process allIntCtrProc; - -dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, - sub_size_loaded, all_int_ctr, RESET, load_eod, load_eod_q) -begin - if (RESET = '1') then -- gk 31.05.10 - df_rd_en <= '0'; - elsif (loadCurrentState = LOAD_DATA) then --- if (bytes_loaded >= max_frame_size - x"1") then --- df_rd_en <= '0'; --- elsif (sub_bytes_loaded >= sub_size_loaded) then --- df_rd_en <= '0'; - if (bytes_loaded = max_frame_size - x"1") then - df_rd_en <= '0'; - -- gk 26.07.10 - --elsif (load_eod = '1') or (load_eod_q = '1') then - elsif (load_eod_q = '1') then - df_rd_en <= '0'; --- elsif (sub_bytes_loaded = sub_size_loaded) then --- df_rd_en <= '0'; - else - df_rd_en <= '1'; - end if; - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then - df_rd_en <= '1'; - elsif (loadCurrentState = PREP_DATA) then - df_rd_en <= '1'; - else - df_rd_en <= '0'; - end if; -end process dfRdEnProc; - -shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET) -begin - if (RESET = '1') then -- gk 31.05.10 - shf_rd_en <= '0'; - elsif (loadCurrentState = LOAD_SUB) then - shf_rd_en <= '1'; - elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then - shf_rd_en <= '1'; - elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then - shf_rd_en <= '1'; - else - shf_rd_en <= '0'; - end if; -end process shfRdEnProc; - - -fcWrEnProc : process(loadCurrentState, RESET) -begin - if (RESET = '1') then -- gk 31.05.10 - fc_wr_en <= '0'; - elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then - fc_wr_en <= '1'; - elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then - fc_wr_en <= '1'; - else - fc_wr_en <= '0'; - end if; -end process fcWrEnProc; - --- was all_int_ctr -fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr) -begin - case loadCurrentState is - when LIDLE => fc_data <= x"af"; - when WAIT_FOR_FC => fc_data <= x"bf"; - -- gk 08.04.10 my_int_ctr changed to load_int_ctr - when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8); - when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8); - when LOAD_SUB => fc_data <= shf_q; - when PREP_DATA => fc_data <= df_q_reg; - when LOAD_DATA => fc_data <= df_q_reg; - when LOAD_TERM => fc_data <= shf_q; - when DIVIDE => fc_data <= x"cf"; - when CLEANUP => fc_data <= x"df"; - when others => fc_data <= x"00"; - end case; -end process fcDataProc; - --- delay counters --- gk 28.04.10 -DELAY_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (loadCurrentState = LIDLE)) then - delay_ctr <= PC_DELAY_IN; - elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then - delay_ctr <= delay_ctr - x"1"; - end if; - end if; -end process DELAY_CTR_PROC; - --- gk 28.04.10 -TICKS_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then - ticks_ctr <= x"00"; - elsif (loadCurrentState = DELAY) then - ticks_ctr <= ticks_ctr + x"1"; - end if; - end if; -end process TICKS_CTR_PROC; - - ---*********************** --- SIZE COUNTERS FOR LOADING SIDE ---*********************** - -queue_size_temp <= queue_size - x"20"; -- size of data without termination - --- gk 08.04.10 -rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or - ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) - else '0'; - --- gk 08.04.10 -RST_AFTER_SUB_PROC : process(CLK) -begin - if(rising_edge(CLK)) then - if(RESET = '1') then - rst_after_sub <= '0'; - else - rst_after_sub <= rst_after_sub_comb; - end if; - end if; -end process RST_AFTER_SUB_PROC; - --- counts all bytes loaded to divide data into frames -bytesLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then - bytes_loaded <= x"0000"; - elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then - bytes_loaded <= bytes_loaded + x"1"; - end if; - end if; -end process bytesLoadedProc; - --- size of subevent loaded from memory -subSizeLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10 - sub_size_loaded <= x"00000000"; - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then - -- was all_int_ctr - -- gk 08.04.10 my_int_ctr changed to load_int_ctr - sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q; - -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then - sub_size_loaded <= sub_size_loaded + x"4"; - end if; - end if; -end process subSizeLoadedProc; - --- counts only raw data bytes being loaded -subBytesLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10 - sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count - elsif (loadCurrentState = LOAD_DATA) then - sub_bytes_loaded <= sub_bytes_loaded + x"1"; - end if; - end if; -end process subBytesLoadedProc; - --- counts the size of the large udp packet -actualPacketProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - actual_packet_size <= x"0008"; - elsif (fc_wr_en = '1') then - actual_packet_size <= actual_packet_size + x"1"; - end if; - end if; -end process actualPacketProc; - -actualQueueSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = CLEANUP) then - actual_queue_size <= (others => '0'); - elsif (loadCurrentState = LIDLE) then - actual_queue_size <= queue_size; - end if; - end if; -end process actualQueueSizeProc; - --- amount of bytes left to send in current packet -sizeLeftProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = CLEANUP) then - size_left <= (others => '0'); - elsif (loadCurrentState = LIDLE) then - size_left <= queue_size; - elsif (fc_wr_en = '1') then - size_left <= size_left - 1; - end if; - end if; -end process sizeLeftProc; - --- HOT FIX: don't rely on CTS information, count the packets on your own. --- In this case, we increment the fragmented packet ID with EOD from ipu2gbe. -THE_FC_IDENT_COUNTER_PROC: process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_ident <= (others => '0'); - elsif (PC_END_OF_DATA_IN = '1') then - fc_ident <= fc_ident + 1; - end if; - end if; -end process THE_FC_IDENT_COUNTER_PROC; - -fc_flags_offset(15 downto 14) <= "00"; - -moreFragmentsProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - fc_flags_offset(13) <= '0'; - elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then - if ((actual_queue_size - actual_packet_size) < max_frame_size) then - fc_flags_offset(13) <= '0'; -- no more fragments - else - fc_flags_offset(13) <= '1'; -- more fragments - end if; - end if; - end if; -end process moreFragmentsProc; - -eodProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_eod <= '0'; - elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then - fc_eod <= '1'; - elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then - fc_eod <= '1'; - elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then - fc_eod <= '1'; - else - fc_eod <= '0'; - end if; - end if; -end process eodProc; - -sodProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_sod <= '0'; - elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then - fc_sod <= '1'; - elsif (loadCurrentState = DIVIDE) and (FC_READY_IN = '1') then - fc_sod <= '1'; - else - fc_sod <= '0'; - end if; - end if; -end process sodProc; - -offsetProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - fc_flags_offset(12 downto 0) <= (others => '0'); - elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) then - fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3); - end if; - end if; -end process offsetProc; - -fcIPSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET= '1') then - fc_ip_size <= (others => '0'); - elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then - if (size_left >= max_frame_size) then - fc_ip_size <= max_frame_size; - else - fc_ip_size <= size_left(15 downto 0); - end if; - end if; - end if; -end process fcIPSizeProc; - -fcUDPSizeProc : process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_udp_size <= (others => '0'); - elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then - fc_udp_size <= queue_size(15 downto 0); - end if; - end if; -end process fcUDPSizeProc; - - ---*********************** --- SUBEVENT HEADERS WRITE AND READ ---*********************** - -SUBEVENT_HEADERS_FIFO : fifo_2048x8 -port map( - Data => shf_data, - WrClock => CLK, - RdClock => CLK, - WrEn => shf_wr_en, - RdEn => shf_rd_en, - Reset => RESET, - RPReset => RESET, - Q => shf_q, - Empty => shf_empty, - Full => shf_full -); - --- write enable for SHF -shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA)) - else '0'; - --- data multiplexing for SHF (convert 32bit LWs to 8bit) --- CHANGED. --- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC. -shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, - pc_trig_nr, my_int_ctr, fc_data) -begin - case saveSubCurrentState is - when SIDLE => shf_data <= x"ac"; - when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_TERM => shf_data <= fc_data; - when others => shf_data <= x"00"; - end case; -end process shfDataProc; - -saveSubMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saveSubCurrentState <= SIDLE; - else - saveSubCurrentState <= saveSubNextState; - end if; - end if; -end process saveSubMachineProc; - -saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, FC_H_READY_IN) -begin - case saveSubCurrentState is - when SIDLE => - save_state <= x"0"; - if (PC_START_OF_SUB_IN = '1') then - saveSubNextState <= SAVE_SIZE; - -- this branch is dangerous! - elsif (loadCurrentState = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len - saveSubNextState <= SAVE_TERM; - else - saveSubNextState <= SIDLE; - end if; - when SAVE_SIZE => - save_state <= x"1"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_DECODING; - else - saveSubNextState <= SAVE_SIZE; - end if; - when SAVE_DECODING => - save_state <= x"2"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_ID; - else - saveSubNextState <= SAVE_DECODING; - end if; - when SAVE_ID => - save_state <= x"3"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_TRIG_NR; - else - saveSubNextState <= SAVE_ID; - end if; - when SAVE_TRIG_NR => - save_state <= x"4"; - if (sub_int_ctr = 3) then - saveSubNextState <= SIDLE; - else - saveSubNextState <= SAVE_TRIG_NR; - end if; - when SAVE_TERM => - save_state <= x"5"; - if (sub_int_ctr = 31) then - saveSubNextState <= SIDLE; - else - saveSubNextState <= SAVE_TERM; - end if; - when others => - save_state <= x"f"; - saveSubNextState <= SIDLE; - end case; -end process; - --- This counter is used for breaking down 32bit information words into 8bit bytes for --- storing them in the SHF. --- It is also used for the termination 32byte sequence. -subIntProc: process( CLK ) -begin - if rising_edge(CLK) then - if (RESET = '1') or (saveSubCurrentState = SIDLE) then - sub_int_ctr <= 0; - elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then - sub_int_ctr <= 0; - elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then - sub_int_ctr <= 0; - elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then - sub_int_ctr <= sub_int_ctr + 1; - end if; - end if; -end process subIntProc; - -debug(3 downto 0) <= constr_state; -debug(7 downto 4) <= save_state; -debug(11 downto 8) <= load_state; -debug(27 downto 12) <= queue_size(15 downto 0); -debug(28) <= df_full; -debug(29) <= df_empty; -debug(30) <= shf_full; -debug(31) <= shf_empty; - -debug(47 downto 32) <= size_left(15 downto 0); -debug(52 downto 48) <= all_ctr; -debug(53) <= pc_ready; - --- outputs -PC_READY_OUT <= pc_ready; -FC_WR_EN_OUT <= fc_wr_en; -FC_DATA_OUT <= fc_data; -FC_IP_SIZE_OUT <= fc_ip_size; -FC_UDP_SIZE_OUT <= fc_udp_size; -FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); -FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); -FC_FLAGS_OFFSET_OUT <= fc_flags_offset; -FC_SOD_OUT <= fc_sod; -FC_EOD_OUT <= fc_eod; - -DEBUG_OUT <= debug; - -end trb_net16_gbe_packet_constr; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd b/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd deleted file mode 100644 index 41ab0b1..0000000 --- a/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd +++ /dev/null @@ -1,1099 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_packet_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10 - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 - PC_END_OF_DATA_IN : in std_logic; - PC_TRANSMIT_ON_OUT : out std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_PADDING_IN : in std_logic; -- gk 29.03.10 - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP - PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 - -- FrameConstructor ports - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(7 downto 0); - TC_H_READY_IN : in std_logic; - TC_READY_IN : in std_logic; - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_SOD_OUT : out std_logic; - TC_EOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_packet_constr; - -architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is - --- attribute HGROUP : string; --- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr"; - -component fifo_64kx9 -port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - --- FIFO for SubEventHeader information -component fifo_16kx8 is -port ( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -signal df_wr_en : std_logic; -signal df_rd_en : std_logic; -signal df_q : std_logic_vector(7 downto 0); -signal df_q_reg : std_logic_vector(7 downto 0); -signal df_empty : std_logic; -signal df_full : std_logic; - -signal fc_data : std_logic_vector(7 downto 0); -signal fc_wr_en : std_logic; -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter! -signal fc_flags_offset : std_logic_vector(15 downto 0); - -signal shf_data : std_logic_vector(7 downto 0); -signal shf_wr_en : std_logic; -signal shf_rd_en : std_logic; -signal shf_q : std_logic_vector(7 downto 0); -signal shf_empty : std_logic; -signal shf_full : std_logic; - -type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD); -signal constructCurrentState, constructNextState : constructStates; -signal constr_state : std_logic_vector(3 downto 0); -signal all_int_ctr : integer range 0 to 31; -signal all_ctr : std_logic_vector(4 downto 0); - -type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM); -signal saveSubCurrentState, saveSubNextState : saveSubStates; -signal save_state : std_logic_vector(3 downto 0); -signal sub_int_ctr : integer range 0 to 31; -signal sub_ctr : std_logic_vector(4 downto 0); -signal my_int_ctr : integer range 0 to 3; -signal my_ctr : std_logic_vector(1 downto 0); - -type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY); -signal loadCurrentState, loadNextState: loadStates; -signal load_state : std_logic_vector(3 downto 0); - -signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination -signal queue_size_temp : std_logic_vector(31 downto 0); -signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid -signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame -signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf -signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted -signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent -signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet -signal size_left : std_logic_vector(31 downto 0); -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal max_frame_size : std_logic_vector(15 downto 0); -signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term -signal debug : std_logic_vector(63 downto 0); -signal pc_ready : std_logic; - -signal pc_sub_size : std_logic_vector(31 downto 0); -signal pc_trig_nr : std_logic_vector(31 downto 0); -signal rst_after_sub_comb : std_logic; -- gk 08.04.10 -signal rst_after_sub : std_logic; -- gk 08.04.10 -signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10 -signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10 -signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10 - --- gk 26.07.10 -signal load_eod : std_logic; -signal load_eod_q : std_logic; - --- gk 07.10.10 -signal df_eod : std_logic; - --- gk 04.12.10 -signal first_sub_in_multi : std_logic; -signal from_divide_state : std_logic; -signal disable_prep : std_logic; - -begin - - ---PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0'; -PC_TRANSMIT_ON_OUT <= '0'; - --- my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order --- load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10 --- --- all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging --- sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging --- my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging --- --- max_frame_size <= PC_MAX_FRAME_SIZE_IN; --- --- -- Ready signal for PacketConstructor --- pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0'; -pc_ready <= '0'; - --- store event information on Start_of_Subevent --- THE_EVT_INFO_STORE_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if (RESET = '1') then -- gk 31.05.10 --- pc_sub_size <= (others => '0'); --- pc_trig_nr <= (others => '0'); --- elsif( PC_START_OF_SUB_IN = '1' ) then --- pc_sub_size <= PC_SUB_SIZE_IN; --- pc_trig_nr <= PC_TRIG_NR_IN; --- end if; --- end if; --- end process; --- --- -- gk 07.10.10 --- df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1')) --- or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1')) --- else '0'; - --- Data FIFO for incoming packet data from IPU buffer --- gk 26.07.10 --- DATA_FIFO : fifo_64kx9 --- port map( --- Data(7 downto 0) => PC_DATA_IN, --- Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10 --- WrClock => CLK, --- RdClock => CLK, --- WrEn => df_wr_en, --- RdEn => df_rd_en, --- Reset => RESET, --- RPReset => RESET, --- Q(7 downto 0) => df_q, --- Q(8) => load_eod, --- Empty => df_empty, --- Full => df_full --- ); - --- LOAD_EOD_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- load_eod_q <= '0'; --- else --- load_eod_q <= load_eod; --- end if; --- end if; --- end process LOAD_EOD_PROC; --- --- -- Write enable for the data FIFO --- -- !!!combinatorial signal!!! --- -- could be avoided as IPU2GBE does only send data in case of PC_READY. --- df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) --- else '0'; --- --- -- Output register for data FIFO --- dfQProc : process(CLK) --- begin --- if rising_edge(CLK) then --- df_q_reg <= df_q; --- end if; --- end process dfQProc; --- --- -- Construction state machine --- constructMachineProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- constructCurrentState <= CIDLE; --- else --- constructCurrentState <= constructNextState; --- end if; --- end if; --- end process constructMachineProc; --- --- constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr) --- begin --- case constructCurrentState is --- when CIDLE => --- constr_state <= x"0"; --- --if( PC_WR_EN_IN = '1' ) then --- -- gk 04.12.10 --- if (PC_START_OF_SUB_IN = '1') then --- --- constructNextState <= SAVE_DATA; --- else --- constructNextState <= CIDLE; --- end if; --- when SAVE_DATA => --- constr_state <= x"1"; --- if( PC_END_OF_DATA_IN = '1' ) then --- constructNextState <= WAIT_FOR_LOAD; --- else --- constructNextState <= SAVE_DATA; --- end if; --- when WAIT_FOR_LOAD => --- constr_state <= x"2"; --- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted --- constructNextState <= CIDLE; --- else --- constructNextState <= WAIT_FOR_LOAD; --- end if; --- when others => --- constr_state <= x"f"; --- constructNextState <= CIDLE; --- end case; --- end process constructMachine; - ---*********************** --- SIZE COUNTERS FOR SAVING SIDE ---*********************** - --- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size --- that's why they are removed if pc_padding flag is asserted --- sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0') --- else (x"c" + pc_sub_size); -- subevent headers + data --- --- -- BUG HERE BUG HERE BUG HERE BUG HERE --- -- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents --- queueSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then --- if (RESET = '1') or (loadCurrentState = CLEANUP) then --- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination --- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then --- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers --- end if; --- end if; --- end process queueSizeProc; - - ---*********************** --- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION ---*********************** - --- loadMachineProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- loadCurrentState <= LIDLE; --- else --- loadCurrentState <= loadNextState; --- end if; --- end if; --- end process loadMachineProc; --- --- loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty, --- sub_bytes_loaded, sub_size_loaded, size_left, TC_H_READY_IN, --- max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN, --- delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN) --- begin --- case loadCurrentState is --- when LIDLE => --- load_state <= x"0"; --- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then --- loadNextState <= WAIT_FOR_FC; --- else --- loadNextState <= LIDLE; --- end if; --- when WAIT_FOR_FC => --- load_state <= x"1"; --- if (TC_H_READY_IN = '1') then --- loadNextState <= PUT_Q_LEN; --- else --- loadNextState <= WAIT_FOR_FC; --- end if; --- when PUT_Q_LEN => --- load_state <= x"2"; --- if (all_int_ctr = 3) then --- loadNextState <= PUT_Q_DEC; --- else --- loadNextState <= PUT_Q_LEN; --- end if; --- when PUT_Q_DEC => --- load_state <= x"3"; --- if (all_int_ctr = 3) then --- loadNextState <= LOAD_SUB; --- else --- loadNextState <= PUT_Q_DEC; --- end if; --- when LOAD_SUB => --- load_state <= x"4"; --- if (bytes_loaded = max_frame_size - 1) then --- loadNextState <= DIVIDE; --- elsif (all_int_ctr = 15) then --- loadNextState <= PREP_DATA; --- else --- loadNextState <= LOAD_SUB; --- end if; --- when PREP_DATA => --- load_state <= x"5"; --- loadNextState <= LOAD_DATA; --- when LOAD_DATA => --- load_state <= x"6"; --- -- if (bytes_loaded = max_frame_size - 1) then --- -- loadNextState <= DIVIDE; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') then --- -- if (size_left = x"0000_0023") then --- -- loadNextState <= LOAD_TERM; --- -- elsif (load_eod_q = '1') then --- -- loadNextState <= LOAD_SUB; --- -- else --- -- loadNextState <= LOAD_DATA; --- -- end if; --- -- else --- -- if (load_eod_q = '1') then --- -- loadNextState <= LOAD_TERM; --- -- else --- -- loadNextState <= LOAD_DATA; --- -- end if; --- -- end if; --- if (bytes_loaded = max_frame_size - 1) then --- loadNextState <= DIVIDE; --- -- gk 07.10.10 --- elsif (load_eod_q = '1') then --- if (MULT_EVT_ENABLE_IN = '1') then --- if (size_left < x"0000_0030") then --- loadNextState <= LOAD_TERM; --- else --- loadNextState <= LOAD_SUB; --- end if; --- else --- loadNextState <= LOAD_TERM; --- end if; --- else --- loadNextState <= LOAD_DATA; --- end if; --- when DIVIDE => --- load_state <= x"7"; --- if (TC_H_READY_IN = '1') then --- if (divide_position = "00") then --- loadNextState <= PREP_DATA; --- elsif (divide_position = "01") then --- loadNextState <= LOAD_SUB; --- else --- loadNextState <= LOAD_TERM; --- end if; --- else --- loadNextState <= DIVIDE; --- end if; --- when LOAD_TERM => --- load_state <= x"8"; --- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then --- loadNextState <= DIVIDE; --- elsif (all_int_ctr = 31) then --- loadNextState <= CLEANUP; --- else --- loadNextState <= LOAD_TERM; --- end if; --- -- gk 28.04.10 --- when CLEANUP => --- load_state <= x"9"; --- if (PC_DELAY_IN = x"0000_0000") then --- loadNextState <= LIDLE; --- else --- loadNextState <= DELAY; --- end if; --- -- gk 28.04.10 --- when DELAY => --- load_state <= x"a"; --- if (delay_ctr = x"0000_0000") then --- loadNextState <= LIDLE; --- else --- loadNextState <= DELAY; --- end if; --- when others => --- load_state <= x"f"; --- loadNextState <= LIDLE; --- end case; --- end process loadMachine; --- --- -- gk 04.12.10 --- firstSubInMultiProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LOAD_TERM) then --- first_sub_in_multi <= '1'; --- elsif (loadCurrentState = LOAD_DATA) then --- first_sub_in_multi <= '0'; --- end if; --- end if; --- end process; --- --- -- gk 04.12.10 --- fromDivideStateProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- from_divide_state <= '0'; --- elsif (loadCurrentState = DIVIDE) then --- from_divide_state <= '1'; --- elsif (loadCurrentState = PREP_DATA) then --- from_divide_state <= '0'; --- end if; --- end if; --- end process fromDivideStateProc; --- --- --- dividePositionProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- divide_position <= "00"; --- -- elsif (bytes_loaded = max_frame_size - 1) then --- -- if (loadCurrentState = LIDLE) then --- -- divide_position <= "00"; --- -- elsif (loadCurrentState = LOAD_DATA) then --- -- -- gk 07.10.10 --- -- if (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then --- -- divide_position <= "11"; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then --- -- divide_position <= "01"; --- -- -- gk 26.07.10 --- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term --- -- divide_position <= "11"; --- -- else --- -- divide_position <= "00"; -- still data loaded divide on data --- -- end if; --- -- elsif (loadCurrentState = LOAD_SUB) then --- -- if (all_int_ctr = 15) then --- -- divide_position <= "00"; --- -- else --- -- divide_position <= "01"; --- -- end if; --- -- elsif (loadCurrentState = LOAD_TERM) then --- -- divide_position <= "11"; --- -- end if; --- -- end if; --- elsif (bytes_loaded = max_frame_size - 1) then --- if (loadCurrentState = LIDLE) then --- divide_position <= "00"; --- disable_prep <= '0'; -- gk 05.12.10 --- elsif (loadCurrentState = LOAD_DATA) then --- -- gk 05.12.10 --- -- gk 26.07.10 --- if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term --- divide_position <= "11"; --- disable_prep <= '0'; -- gk 05.12.10 --- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then --- if (size_left > x"0000_0028") then --- divide_position <= "01"; --- disable_prep <= '0'; -- gk 05.12.10 --- else --- divide_position <= "11"; --- disable_prep <= '0'; -- gk 05.12.10 --- end if; --- else --- divide_position <= "00"; -- still data loaded divide on data --- disable_prep <= '1'; -- gk 05.12.10 --- end if; --- elsif (loadCurrentState = LOAD_SUB) then --- if (all_int_ctr = 15) then --- divide_position <= "00"; --- disable_prep <= '1'; -- gk 05.12.10 --- else --- divide_position <= "01"; --- disable_prep <= '0'; -- gk 05.12.10 --- end if; --- elsif (loadCurrentState = LOAD_TERM) then --- divide_position <= "11"; --- disable_prep <= '0'; -- gk 05.12.10 --- end if; --- elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep --- disable_prep <= '0'; --- end if; --- --- end if; --- end process dividePositionProc; --- --- allIntCtrProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then -- gk 31.05.10 --- all_int_ctr <= 0; --- else --- case loadCurrentState is --- --- when LIDLE => all_int_ctr <= 0; --- --- when WAIT_FOR_FC => all_int_ctr <= 0; --- --- when PUT_Q_LEN => --- if (all_int_ctr = 3) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when PUT_Q_DEC => --- if (all_int_ctr = 3) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when LOAD_SUB => --- if (all_int_ctr = 15) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when LOAD_DATA => all_int_ctr <= 0; --- --- when LOAD_TERM => --- if (all_int_ctr = 31) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when DIVIDE => null; --- --- when CLEANUP => all_int_ctr <= 0; --- --- when PREP_DATA => all_int_ctr <= 0; --- --- when DELAY => all_int_ctr <= 0; --- end case; --- end if; --- end if; --- end process allIntCtrProc; --- --- dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, --- sub_size_loaded, all_int_ctr, RESET, size_left, load_eod_q) --- begin --- if (RESET = '1') then --- df_rd_en <= '0'; --- elsif (loadCurrentState = LOAD_DATA) then --- -- if (bytes_loaded = max_frame_size - x"1") then --- -- df_rd_en <= '0'; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then --- -- df_rd_en <= '0'; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then --- -- df_rd_en <= '0'; --- -- else --- -- df_rd_en <= '1'; --- -- end if; --- if (bytes_loaded = max_frame_size - x"1") then --- df_rd_en <= '0'; --- -- gk 26.07.10 --- --elsif (load_eod = '1') or (load_eod_q = '1') then --- elsif (load_eod_q = '1') then --- df_rd_en <= '0'; --- -- elsif (sub_bytes_loaded = sub_size_loaded) then --- -- df_rd_en <= '0'; --- else --- df_rd_en <= '1'; --- end if; --- --- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then --- df_rd_en <= '1'; --- elsif (loadCurrentState = PREP_DATA) then --- df_rd_en <= '1'; --- else --- df_rd_en <= '0'; --- end if; --- end process dfRdEnProc; --- --- shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET) --- begin --- if (RESET = '1') then -- gk 31.05.10 --- shf_rd_en <= '0'; --- elsif (loadCurrentState = LOAD_SUB) then --- shf_rd_en <= '1'; --- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then --- shf_rd_en <= '1'; --- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then --- shf_rd_en <= '1'; --- else --- shf_rd_en <= '0'; --- end if; --- end process shfRdEnProc; --- --- --- -- fcWrEnProc : process(loadCurrentState, RESET) --- -- begin --- -- if (RESET = '1') then -- gk 31.05.10 --- -- fc_wr_en <= '0'; --- -- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then --- -- fc_wr_en <= '1'; --- -- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then --- -- fc_wr_en <= '1'; --- -- else --- -- fc_wr_en <= '0'; --- -- end if; --- -- end process fcWrEnProc; --- fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep) --- begin --- if (RESET = '1') then -- gk 31.05.10 --- fc_wr_en <= '0'; --- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then --- fc_wr_en <= '1'; --- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then --- fc_wr_en <= '1'; --- -- gk 04.12.10 --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then --- fc_wr_en <= '1'; --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then --- fc_wr_en <= '1'; --- else --- fc_wr_en <= '0'; --- end if; --- end process fcWrEnProc; --- --- --- -- was all_int_ctr --- fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr) --- begin --- case loadCurrentState is --- when LIDLE => fc_data <= x"af"; --- when WAIT_FOR_FC => fc_data <= x"bf"; --- -- gk 08.04.10 my_int_ctr changed to load_int_ctr --- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8); --- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8); --- when LOAD_SUB => fc_data <= shf_q; --- when PREP_DATA => fc_data <= df_q_reg; --- when LOAD_DATA => fc_data <= df_q_reg; --- when LOAD_TERM => fc_data <= shf_q; --- when DIVIDE => fc_data <= x"cf"; --- when CLEANUP => fc_data <= x"df"; --- when others => fc_data <= x"00"; --- end case; --- end process fcDataProc; --- --- -- delay counters --- -- gk 28.04.10 --- DELAY_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if ((RESET = '1') or (loadCurrentState = LIDLE)) then --- delay_ctr <= PC_DELAY_IN; --- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then --- delay_ctr <= delay_ctr - x"1"; --- end if; --- end if; --- end process DELAY_CTR_PROC; --- --- -- gk 28.04.10 --- TICKS_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then --- ticks_ctr <= x"00"; --- elsif (loadCurrentState = DELAY) then --- ticks_ctr <= ticks_ctr + x"1"; --- end if; --- end if; --- end process TICKS_CTR_PROC; - - ---*********************** --- SIZE COUNTERS FOR LOADING SIDE ---*********************** - --- queue_size_temp <= queue_size - x"20"; -- size of data without termination --- --- -- gk 08.04.10 --- rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or --- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) --- else '0'; --- --- -- gk 08.04.10 --- RST_AFTER_SUB_PROC : process(CLK) --- begin --- if(rising_edge(CLK)) then --- if(RESET = '1') then --- rst_after_sub <= '0'; --- else --- rst_after_sub <= rst_after_sub_comb; --- end if; --- end if; --- end process RST_AFTER_SUB_PROC; --- --- -- counts all bytes loaded to divide data into frames --- bytesLoadedProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then --- bytes_loaded <= x"0000"; --- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then --- bytes_loaded <= bytes_loaded + x"1"; --- -- gk 05.12.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then --- -- bytes_loaded <= bytes_loaded + x"1"; --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then --- bytes_loaded <= bytes_loaded + x"1"; --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then --- bytes_loaded <= bytes_loaded + x"1"; --- end if; --- end if; --- end process bytesLoadedProc; --- --- -- size of subevent loaded from memory --- subSizeLoadedProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10 --- sub_size_loaded <= x"00000000"; --- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then --- -- was all_int_ctr --- -- gk 08.04.10 my_int_ctr changed to load_int_ctr --- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q; --- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo --- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then --- sub_size_loaded <= sub_size_loaded + x"4"; --- end if; --- end if; --- end process subSizeLoadedProc; --- --- -- counts only raw data bytes being loaded --- subBytesLoadedProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10 --- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count --- elsif (loadCurrentState = LOAD_DATA) then --- sub_bytes_loaded <= sub_bytes_loaded + x"1"; --- end if; --- end if; --- end process subBytesLoadedProc; --- --- -- counts the size of the large udp packet --- actualPacketProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then --- actual_packet_size <= x"0008"; --- elsif (fc_wr_en = '1') then --- actual_packet_size <= actual_packet_size + x"1"; --- end if; --- end if; --- end process actualPacketProc; --- --- actualQueueSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = CLEANUP) then --- actual_queue_size <= (others => '0'); --- elsif (loadCurrentState = LIDLE) then --- actual_queue_size <= queue_size; --- end if; --- end if; --- end process actualQueueSizeProc; --- --- -- amount of bytes left to send in current packet --- sizeLeftProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = CLEANUP) then --- size_left <= (others => '0'); --- elsif (loadCurrentState = LIDLE) then --- size_left <= queue_size; --- elsif (fc_wr_en = '1') then --- size_left <= size_left - 1; --- end if; --- end if; --- end process sizeLeftProc; --- --- -- HOT FIX: don't rely on CTS information, count the packets on your own. --- -- In this case, we increment the fragmented packet ID with EOD from ipu2gbe. --- THE_FC_IDENT_COUNTER_PROC: process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_ident <= (others => '0'); --- elsif (PC_END_OF_DATA_IN = '1') then --- fc_ident <= fc_ident + 1; --- end if; --- end if; --- end process THE_FC_IDENT_COUNTER_PROC; --- --- fc_flags_offset(15 downto 14) <= "00"; --- --- moreFragmentsProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then --- fc_flags_offset(13) <= '0'; --- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then --- if ((actual_queue_size - actual_packet_size) < max_frame_size) then --- fc_flags_offset(13) <= '0'; -- no more fragments --- else --- fc_flags_offset(13) <= '1'; -- more fragments --- end if; --- end if; --- end if; --- end process moreFragmentsProc; --- --- eodProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_eod <= '0'; --- elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then --- fc_eod <= '1'; --- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then --- fc_eod <= '1'; --- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then --- fc_eod <= '1'; --- else --- fc_eod <= '0'; --- end if; --- end if; --- end process eodProc; --- --- sodProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_sod <= '0'; --- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then --- fc_sod <= '1'; --- elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then --- fc_sod <= '1'; --- else --- fc_sod <= '0'; --- end if; --- end if; --- end process sodProc; --- --- offsetProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then --- fc_flags_offset(12 downto 0) <= (others => '0'); --- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then --- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3); --- end if; --- end if; --- end process offsetProc; --- --- fcIPSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET= '1') then --- fc_ip_size <= (others => '0'); --- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then --- if (size_left >= max_frame_size) then --- fc_ip_size <= max_frame_size; --- else --- fc_ip_size <= size_left(15 downto 0); --- end if; --- end if; --- end if; --- end process fcIPSizeProc; --- --- fcUDPSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_udp_size <= (others => '0'); --- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then --- fc_udp_size <= queue_size(15 downto 0); --- end if; --- end if; --- end process fcUDPSizeProc; - - ---*********************** --- SUBEVENT HEADERS WRITE AND READ ---*********************** - --- SUBEVENT_HEADERS_FIFO : fifo_16kx8 --- port map( --- Data => shf_data, --- WrClock => CLK, --- RdClock => CLK, --- WrEn => shf_wr_en, --- RdEn => shf_rd_en, --- Reset => RESET, --- RPReset => RESET, --- Q => shf_q, --- Empty => shf_empty, --- Full => shf_full --- ); --- --- -- write enable for SHF --- shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA)) --- else '0'; --- --- -- data multiplexing for SHF (convert 32bit LWs to 8bit) --- -- CHANGED. --- -- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC. --- shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, --- pc_trig_nr, my_int_ctr, fc_data) --- begin --- case saveSubCurrentState is --- when SIDLE => shf_data <= x"ac"; --- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_TERM => shf_data <= fc_data; --- when others => shf_data <= x"00"; --- end case; --- end process shfDataProc; --- --- saveSubMachineProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- saveSubCurrentState <= SIDLE; --- else --- saveSubCurrentState <= saveSubNextState; --- end if; --- end if; --- end process saveSubMachineProc; --- --- saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN) --- begin --- case saveSubCurrentState is --- when SIDLE => --- save_state <= x"0"; --- if (PC_START_OF_SUB_IN = '1') then --- saveSubNextState <= SAVE_SIZE; --- -- this branch is dangerous! --- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len --- saveSubNextState <= SAVE_TERM; --- else --- saveSubNextState <= SIDLE; --- end if; --- when SAVE_SIZE => --- save_state <= x"1"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SAVE_DECODING; --- else --- saveSubNextState <= SAVE_SIZE; --- end if; --- when SAVE_DECODING => --- save_state <= x"2"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SAVE_ID; --- else --- saveSubNextState <= SAVE_DECODING; --- end if; --- when SAVE_ID => --- save_state <= x"3"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SAVE_TRIG_NR; --- else --- saveSubNextState <= SAVE_ID; --- end if; --- when SAVE_TRIG_NR => --- save_state <= x"4"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SIDLE; --- else --- saveSubNextState <= SAVE_TRIG_NR; --- end if; --- when SAVE_TERM => --- save_state <= x"5"; --- if (sub_int_ctr = 31) then --- saveSubNextState <= SIDLE; --- else --- saveSubNextState <= SAVE_TERM; --- end if; --- when others => --- save_state <= x"f"; --- saveSubNextState <= SIDLE; --- end case; --- end process; --- --- -- This counter is used for breaking down 32bit information words into 8bit bytes for --- -- storing them in the SHF. --- -- It is also used for the termination 32byte sequence. --- subIntProc: process( CLK ) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (saveSubCurrentState = SIDLE) then --- sub_int_ctr <= 0; --- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then --- sub_int_ctr <= 0; --- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then --- sub_int_ctr <= 0; --- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then --- sub_int_ctr <= sub_int_ctr + 1; --- end if; --- end if; --- end process subIntProc; --- --- debug(3 downto 0) <= constr_state; --- debug(7 downto 4) <= save_state; --- debug(11 downto 8) <= load_state; --- debug(27 downto 12) <= queue_size(15 downto 0); --- debug(28) <= df_full; --- debug(29) <= df_empty; --- debug(30) <= shf_full; --- debug(31) <= shf_empty; --- --- debug(47 downto 32) <= size_left(15 downto 0); --- debug(52 downto 48) <= all_ctr; --- debug(53) <= pc_ready; - --- outputs --- PC_READY_OUT <= pc_ready; --- TC_WR_EN_OUT <= fc_wr_en; --- TC_DATA_OUT <= fc_data; --- TC_IP_SIZE_OUT <= fc_ip_size; --- TC_UDP_SIZE_OUT <= fc_udp_size; --- -- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); --- -- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); --- TC_FLAGS_OFFSET_OUT <= fc_flags_offset; --- TC_SOD_OUT <= fc_sod; --- TC_EOD_OUT <= fc_eod; - -PC_READY_OUT <= '1'; -TC_IP_SIZE_OUT <= (others => '0'); -TC_UDP_SIZE_OUT <= (others => '0'); --- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); --- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); --- TC_FLAGS_OFFSET_OUT <= fc_flags_offset; --- TC_SOD_OUT <= fc_sod; --- TC_EOD_OUT <= fc_eod; - -DEBUG_OUT <= debug; - -end trb_net16_gbe_packet_constr; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd b/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd deleted file mode 100644 index 67a8e6c..0000000 --- a/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd +++ /dev/null @@ -1,1182 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_packet_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10 - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; -- CHANGED TO SLOW CONTROL PULSE - PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 - PC_END_OF_DATA_IN : in std_logic; - PC_TRANSMIT_ON_OUT : out std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_PADDING_IN : in std_logic; -- gk 29.03.10 - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP - PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 - -- FrameConstructor ports - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(7 downto 0); - TC_H_READY_IN : in std_logic; - TC_READY_IN : in std_logic; - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_SOD_OUT : out std_logic; - TC_EOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_packet_constr; - -architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is - --- attribute HGROUP : string; --- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr"; - -component fifo_64kx9 -port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - --- FIFO for SubEventHeader information -component fifo_16kx8 is -port ( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -signal df_wr_en : std_logic; -signal df_rd_en : std_logic; -signal df_q : std_logic_vector(7 downto 0); -signal df_q_reg : std_logic_vector(7 downto 0); -signal df_empty : std_logic; -signal df_full : std_logic; - -signal fc_data : std_logic_vector(7 downto 0); -signal fc_wr_en : std_logic; -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter! -signal fc_flags_offset : std_logic_vector(15 downto 0); - -signal shf_data : std_logic_vector(7 downto 0); -signal shf_wr_en : std_logic; -signal shf_rd_en : std_logic; -signal shf_q : std_logic_vector(7 downto 0); -signal shf_empty : std_logic; -signal shf_full : std_logic; - -type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD); -signal constructCurrentState, constructNextState : constructStates; -signal constr_state : std_logic_vector(3 downto 0); -signal all_int_ctr : integer range 0 to 31; -signal all_ctr : std_logic_vector(4 downto 0); - -type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM); -signal saveSubCurrentState, saveSubNextState : saveSubStates; -signal save_state : std_logic_vector(3 downto 0); -signal sub_int_ctr : integer range 0 to 31; -signal sub_ctr : std_logic_vector(4 downto 0); -signal my_int_ctr : integer range 0 to 3; -signal my_ctr : std_logic_vector(1 downto 0); - -type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY); -signal loadCurrentState, loadNextState: loadStates; -signal load_state : std_logic_vector(3 downto 0); - -signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination -signal queue_size_temp : std_logic_vector(31 downto 0); -signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid -signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame -signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf -signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted -signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent -signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet -signal size_left : std_logic_vector(31 downto 0); -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal max_frame_size : std_logic_vector(15 downto 0); -signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term -signal debug : std_logic_vector(63 downto 0); -signal pc_ready : std_logic; - -signal pc_sub_size : std_logic_vector(31 downto 0); -signal pc_trig_nr : std_logic_vector(31 downto 0); -signal rst_after_sub_comb : std_logic; -- gk 08.04.10 -signal rst_after_sub : std_logic; -- gk 08.04.10 -signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10 -signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10 -signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10 - --- gk 26.07.10 -signal load_eod : std_logic; -signal load_eod_q : std_logic; - --- gk 07.10.10 -signal df_eod : std_logic; - --- gk 04.12.10 -signal first_sub_in_multi : std_logic; -signal from_divide_state : std_logic; -signal disable_prep : std_logic; - --- gk 02.08.11 -type constructSimpleFrameStates is (IDLE, WAIT_FOR_HEADERS, PUT_DATA, FINISH); -signal constrSimpleFrameCurrentState, constrSimpleFrameNextState : constructSimpleFrameStates; - -signal gen_data_ctr : std_logic_vector(15 downto 0); - -signal state : std_logic_vector(3 downto 0); - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of state : signal is true; -attribute syn_preserve of state : signal is true; - -begin - -costrSimpleFrameMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - constrSimpleFrameCurrentState <= IDLE; - else - constrSimpleFrameCurrentState <= constrSimpleFrameNextState; - end if; - end if; -end process costrSimpleFrameMachineProc; - -constrSimpleFrameMachine : process(constrSimpleFrameCurrentState, PC_START_OF_SUB_IN, TC_H_READY_IN, gen_data_ctr, TC_READY_IN) -begin - case constrSimpleFrameCurrentState is - - when IDLE => - state <= x"1"; - if (PC_START_OF_SUB_IN = '1') then - constrSimpleFrameNextState <= WAIT_FOR_HEADERS; - else - constrSimpleFrameNextState <= IDLE; - end if; - - when WAIT_FOR_HEADERS => - state <= x"2"; - if (TC_H_READY_IN = '1') then - constrSimpleFrameNextState <= PUT_DATA; - else - constrSimpleFrameNextState <= WAIT_FOR_HEADERS; - end if; - - when PUT_DATA => - state <= x"3"; - if (gen_data_ctr = x"0100") then - constrSimpleFrameNextState <= FINISH; - else - constrSimpleFrameNextState <= PUT_DATA; - end if; - - when FINISH => - state <= x"4"; - if (TC_READY_IN = '1') then - constrSimpleFrameNextState <= IDLE; - else - constrSimpleFrameNextState <= FINISH; - end if; - - end case; -end process constrSimpleFrameMachine; - -GEN_DATA_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (constrSimpleFrameCurrentState = IDLE) then - gen_data_ctr <= (others => '0'); - elsif (constrSimpleFrameCurrentState = PUT_DATA) then - gen_data_ctr <= gen_data_ctr + x"1"; - end if; - end if; -end process; - -TC_DATA_OUT <= gen_data_ctr(7 downto 0); -TC_WR_EN_OUT <= '1' when constrSimpleFrameCurrentState = PUT_DATA else '0'; -TC_SOD_OUT <= '1' when (constrSimpleFrameCurrentState = IDLE and PC_START_OF_SUB_IN = '1') or (constrSimpleFrameCurrentState = WAIT_FOR_HEADERS and TC_H_READY_IN = '0') else '0'; -TC_EOD_OUT <= '1' when constrSimpleFrameCurrentState = PUT_DATA and gen_data_ctr = x"0100" else '0'; -PC_READY_OUT <= '1' when constrSimpleFrameCurrentState = IDLE else '0'; -PC_TRANSMIT_ON_OUT <= '0' when constrSimpleFrameCurrentState = IDLE and PC_START_OF_SUB_IN = '0' else '1'; -TC_IP_SIZE_OUT <= x"0100"; -TC_UDP_SIZE_OUT <= x"0100"; -TC_FLAGS_OFFSET_OUT <= (others => '0'); - ---PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0'; ---PC_TRANSMIT_ON_OUT <= '0'; - --- my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order --- load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10 --- --- all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging --- sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging --- my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging --- --- max_frame_size <= PC_MAX_FRAME_SIZE_IN; --- --- -- Ready signal for PacketConstructor - --pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0'; ---pc_ready <= '0'; - --- store event information on Start_of_Subevent --- THE_EVT_INFO_STORE_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if (RESET = '1') then -- gk 31.05.10 --- pc_sub_size <= (others => '0'); --- pc_trig_nr <= (others => '0'); --- elsif( PC_START_OF_SUB_IN = '1' ) then --- pc_sub_size <= PC_SUB_SIZE_IN; --- pc_trig_nr <= PC_TRIG_NR_IN; --- end if; --- end if; --- end process; --- --- -- gk 07.10.10 --- df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1')) --- or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1')) --- else '0'; - --- Data FIFO for incoming packet data from IPU buffer --- gk 26.07.10 --- DATA_FIFO : fifo_64kx9 --- port map( --- Data(7 downto 0) => PC_DATA_IN, --- Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10 --- WrClock => CLK, --- RdClock => CLK, --- WrEn => df_wr_en, --- RdEn => df_rd_en, --- Reset => RESET, --- RPReset => RESET, --- Q(7 downto 0) => df_q, --- Q(8) => load_eod, --- Empty => df_empty, --- Full => df_full --- ); - --- LOAD_EOD_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- load_eod_q <= '0'; --- else --- load_eod_q <= load_eod; --- end if; --- end if; --- end process LOAD_EOD_PROC; --- --- -- Write enable for the data FIFO --- -- !!!combinatorial signal!!! --- -- could be avoided as IPU2GBE does only send data in case of PC_READY. --- df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) --- else '0'; --- --- -- Output register for data FIFO --- dfQProc : process(CLK) --- begin --- if rising_edge(CLK) then --- df_q_reg <= df_q; --- end if; --- end process dfQProc; --- --- -- Construction state machine --- constructMachineProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- constructCurrentState <= CIDLE; --- else --- constructCurrentState <= constructNextState; --- end if; --- end if; --- end process constructMachineProc; --- --- constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr) --- begin --- case constructCurrentState is --- when CIDLE => --- constr_state <= x"0"; --- --if( PC_WR_EN_IN = '1' ) then --- -- gk 04.12.10 --- if (PC_START_OF_SUB_IN = '1') then --- --- constructNextState <= SAVE_DATA; --- else --- constructNextState <= CIDLE; --- end if; --- when SAVE_DATA => --- constr_state <= x"1"; --- if( PC_END_OF_DATA_IN = '1' ) then --- constructNextState <= WAIT_FOR_LOAD; --- else --- constructNextState <= SAVE_DATA; --- end if; --- when WAIT_FOR_LOAD => --- constr_state <= x"2"; --- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted --- constructNextState <= CIDLE; --- else --- constructNextState <= WAIT_FOR_LOAD; --- end if; --- when others => --- constr_state <= x"f"; --- constructNextState <= CIDLE; --- end case; --- end process constructMachine; - ---*********************** --- SIZE COUNTERS FOR SAVING SIDE ---*********************** - --- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size --- that's why they are removed if pc_padding flag is asserted --- sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0') --- else (x"c" + pc_sub_size); -- subevent headers + data --- --- -- BUG HERE BUG HERE BUG HERE BUG HERE --- -- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents --- queueSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then --- if (RESET = '1') or (loadCurrentState = CLEANUP) then --- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination --- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then --- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers --- end if; --- end if; --- end process queueSizeProc; - - ---*********************** --- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION ---*********************** - --- loadMachineProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- loadCurrentState <= LIDLE; --- else --- loadCurrentState <= loadNextState; --- end if; --- end if; --- end process loadMachineProc; --- --- loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty, --- sub_bytes_loaded, sub_size_loaded, size_left, TC_H_READY_IN, --- max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN, --- delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN) --- begin --- case loadCurrentState is --- when LIDLE => --- load_state <= x"0"; --- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then --- loadNextState <= WAIT_FOR_FC; --- else --- loadNextState <= LIDLE; --- end if; --- when WAIT_FOR_FC => --- load_state <= x"1"; --- if (TC_H_READY_IN = '1') then --- loadNextState <= PUT_Q_LEN; --- else --- loadNextState <= WAIT_FOR_FC; --- end if; --- when PUT_Q_LEN => --- load_state <= x"2"; --- if (all_int_ctr = 3) then --- loadNextState <= PUT_Q_DEC; --- else --- loadNextState <= PUT_Q_LEN; --- end if; --- when PUT_Q_DEC => --- load_state <= x"3"; --- if (all_int_ctr = 3) then --- loadNextState <= LOAD_SUB; --- else --- loadNextState <= PUT_Q_DEC; --- end if; --- when LOAD_SUB => --- load_state <= x"4"; --- if (bytes_loaded = max_frame_size - 1) then --- loadNextState <= DIVIDE; --- elsif (all_int_ctr = 15) then --- loadNextState <= PREP_DATA; --- else --- loadNextState <= LOAD_SUB; --- end if; --- when PREP_DATA => --- load_state <= x"5"; --- loadNextState <= LOAD_DATA; --- when LOAD_DATA => --- load_state <= x"6"; --- -- if (bytes_loaded = max_frame_size - 1) then --- -- loadNextState <= DIVIDE; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') then --- -- if (size_left = x"0000_0023") then --- -- loadNextState <= LOAD_TERM; --- -- elsif (load_eod_q = '1') then --- -- loadNextState <= LOAD_SUB; --- -- else --- -- loadNextState <= LOAD_DATA; --- -- end if; --- -- else --- -- if (load_eod_q = '1') then --- -- loadNextState <= LOAD_TERM; --- -- else --- -- loadNextState <= LOAD_DATA; --- -- end if; --- -- end if; --- if (bytes_loaded = max_frame_size - 1) then --- loadNextState <= DIVIDE; --- -- gk 07.10.10 --- elsif (load_eod_q = '1') then --- if (MULT_EVT_ENABLE_IN = '1') then --- if (size_left < x"0000_0030") then --- loadNextState <= LOAD_TERM; --- else --- loadNextState <= LOAD_SUB; --- end if; --- else --- loadNextState <= LOAD_TERM; --- end if; --- else --- loadNextState <= LOAD_DATA; --- end if; --- when DIVIDE => --- load_state <= x"7"; --- if (TC_H_READY_IN = '1') then --- if (divide_position = "00") then --- loadNextState <= PREP_DATA; --- elsif (divide_position = "01") then --- loadNextState <= LOAD_SUB; --- else --- loadNextState <= LOAD_TERM; --- end if; --- else --- loadNextState <= DIVIDE; --- end if; --- when LOAD_TERM => --- load_state <= x"8"; --- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then --- loadNextState <= DIVIDE; --- elsif (all_int_ctr = 31) then --- loadNextState <= CLEANUP; --- else --- loadNextState <= LOAD_TERM; --- end if; --- -- gk 28.04.10 --- when CLEANUP => --- load_state <= x"9"; --- if (PC_DELAY_IN = x"0000_0000") then --- loadNextState <= LIDLE; --- else --- loadNextState <= DELAY; --- end if; --- -- gk 28.04.10 --- when DELAY => --- load_state <= x"a"; --- if (delay_ctr = x"0000_0000") then --- loadNextState <= LIDLE; --- else --- loadNextState <= DELAY; --- end if; --- when others => --- load_state <= x"f"; --- loadNextState <= LIDLE; --- end case; --- end process loadMachine; --- --- -- gk 04.12.10 --- firstSubInMultiProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LOAD_TERM) then --- first_sub_in_multi <= '1'; --- elsif (loadCurrentState = LOAD_DATA) then --- first_sub_in_multi <= '0'; --- end if; --- end if; --- end process; --- --- -- gk 04.12.10 --- fromDivideStateProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- from_divide_state <= '0'; --- elsif (loadCurrentState = DIVIDE) then --- from_divide_state <= '1'; --- elsif (loadCurrentState = PREP_DATA) then --- from_divide_state <= '0'; --- end if; --- end if; --- end process fromDivideStateProc; --- --- --- dividePositionProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- divide_position <= "00"; --- -- elsif (bytes_loaded = max_frame_size - 1) then --- -- if (loadCurrentState = LIDLE) then --- -- divide_position <= "00"; --- -- elsif (loadCurrentState = LOAD_DATA) then --- -- -- gk 07.10.10 --- -- if (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then --- -- divide_position <= "11"; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then --- -- divide_position <= "01"; --- -- -- gk 26.07.10 --- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term --- -- divide_position <= "11"; --- -- else --- -- divide_position <= "00"; -- still data loaded divide on data --- -- end if; --- -- elsif (loadCurrentState = LOAD_SUB) then --- -- if (all_int_ctr = 15) then --- -- divide_position <= "00"; --- -- else --- -- divide_position <= "01"; --- -- end if; --- -- elsif (loadCurrentState = LOAD_TERM) then --- -- divide_position <= "11"; --- -- end if; --- -- end if; --- elsif (bytes_loaded = max_frame_size - 1) then --- if (loadCurrentState = LIDLE) then --- divide_position <= "00"; --- disable_prep <= '0'; -- gk 05.12.10 --- elsif (loadCurrentState = LOAD_DATA) then --- -- gk 05.12.10 --- -- gk 26.07.10 --- if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term --- divide_position <= "11"; --- disable_prep <= '0'; -- gk 05.12.10 --- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then --- if (size_left > x"0000_0028") then --- divide_position <= "01"; --- disable_prep <= '0'; -- gk 05.12.10 --- else --- divide_position <= "11"; --- disable_prep <= '0'; -- gk 05.12.10 --- end if; --- else --- divide_position <= "00"; -- still data loaded divide on data --- disable_prep <= '1'; -- gk 05.12.10 --- end if; --- elsif (loadCurrentState = LOAD_SUB) then --- if (all_int_ctr = 15) then --- divide_position <= "00"; --- disable_prep <= '1'; -- gk 05.12.10 --- else --- divide_position <= "01"; --- disable_prep <= '0'; -- gk 05.12.10 --- end if; --- elsif (loadCurrentState = LOAD_TERM) then --- divide_position <= "11"; --- disable_prep <= '0'; -- gk 05.12.10 --- end if; --- elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep --- disable_prep <= '0'; --- end if; --- --- end if; --- end process dividePositionProc; --- --- allIntCtrProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then -- gk 31.05.10 --- all_int_ctr <= 0; --- else --- case loadCurrentState is --- --- when LIDLE => all_int_ctr <= 0; --- --- when WAIT_FOR_FC => all_int_ctr <= 0; --- --- when PUT_Q_LEN => --- if (all_int_ctr = 3) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when PUT_Q_DEC => --- if (all_int_ctr = 3) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when LOAD_SUB => --- if (all_int_ctr = 15) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when LOAD_DATA => all_int_ctr <= 0; --- --- when LOAD_TERM => --- if (all_int_ctr = 31) then --- all_int_ctr <= 0; --- else --- all_int_ctr <= all_int_ctr + 1; --- end if; --- --- when DIVIDE => null; --- --- when CLEANUP => all_int_ctr <= 0; --- --- when PREP_DATA => all_int_ctr <= 0; --- --- when DELAY => all_int_ctr <= 0; --- end case; --- end if; --- end if; --- end process allIntCtrProc; --- --- dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, --- sub_size_loaded, all_int_ctr, RESET, size_left, load_eod_q) --- begin --- if (RESET = '1') then --- df_rd_en <= '0'; --- elsif (loadCurrentState = LOAD_DATA) then --- -- if (bytes_loaded = max_frame_size - x"1") then --- -- df_rd_en <= '0'; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then --- -- df_rd_en <= '0'; --- -- -- gk 07.10.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then --- -- df_rd_en <= '0'; --- -- else --- -- df_rd_en <= '1'; --- -- end if; --- if (bytes_loaded = max_frame_size - x"1") then --- df_rd_en <= '0'; --- -- gk 26.07.10 --- --elsif (load_eod = '1') or (load_eod_q = '1') then --- elsif (load_eod_q = '1') then --- df_rd_en <= '0'; --- -- elsif (sub_bytes_loaded = sub_size_loaded) then --- -- df_rd_en <= '0'; --- else --- df_rd_en <= '1'; --- end if; --- --- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then --- df_rd_en <= '1'; --- elsif (loadCurrentState = PREP_DATA) then --- df_rd_en <= '1'; --- else --- df_rd_en <= '0'; --- end if; --- end process dfRdEnProc; --- --- shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET) --- begin --- if (RESET = '1') then -- gk 31.05.10 --- shf_rd_en <= '0'; --- elsif (loadCurrentState = LOAD_SUB) then --- shf_rd_en <= '1'; --- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then --- shf_rd_en <= '1'; --- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then --- shf_rd_en <= '1'; --- else --- shf_rd_en <= '0'; --- end if; --- end process shfRdEnProc; --- --- --- -- fcWrEnProc : process(loadCurrentState, RESET) --- -- begin --- -- if (RESET = '1') then -- gk 31.05.10 --- -- fc_wr_en <= '0'; --- -- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then --- -- fc_wr_en <= '1'; --- -- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then --- -- fc_wr_en <= '1'; --- -- else --- -- fc_wr_en <= '0'; --- -- end if; --- -- end process fcWrEnProc; --- fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep) --- begin --- if (RESET = '1') then -- gk 31.05.10 --- fc_wr_en <= '0'; --- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then --- fc_wr_en <= '1'; --- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then --- fc_wr_en <= '1'; --- -- gk 04.12.10 --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then --- fc_wr_en <= '1'; --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then --- fc_wr_en <= '1'; --- else --- fc_wr_en <= '0'; --- end if; --- end process fcWrEnProc; --- --- --- -- was all_int_ctr --- fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr) --- begin --- case loadCurrentState is --- when LIDLE => fc_data <= x"af"; --- when WAIT_FOR_FC => fc_data <= x"bf"; --- -- gk 08.04.10 my_int_ctr changed to load_int_ctr --- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8); --- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8); --- when LOAD_SUB => fc_data <= shf_q; --- when PREP_DATA => fc_data <= df_q_reg; --- when LOAD_DATA => fc_data <= df_q_reg; --- when LOAD_TERM => fc_data <= shf_q; --- when DIVIDE => fc_data <= x"cf"; --- when CLEANUP => fc_data <= x"df"; --- when others => fc_data <= x"00"; --- end case; --- end process fcDataProc; --- --- -- delay counters --- -- gk 28.04.10 --- DELAY_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if ((RESET = '1') or (loadCurrentState = LIDLE)) then --- delay_ctr <= PC_DELAY_IN; --- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then --- delay_ctr <= delay_ctr - x"1"; --- end if; --- end if; --- end process DELAY_CTR_PROC; --- --- -- gk 28.04.10 --- TICKS_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then --- ticks_ctr <= x"00"; --- elsif (loadCurrentState = DELAY) then --- ticks_ctr <= ticks_ctr + x"1"; --- end if; --- end if; --- end process TICKS_CTR_PROC; - - ---*********************** --- SIZE COUNTERS FOR LOADING SIDE ---*********************** - --- queue_size_temp <= queue_size - x"20"; -- size of data without termination --- --- -- gk 08.04.10 --- rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or --- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) --- else '0'; --- --- -- gk 08.04.10 --- RST_AFTER_SUB_PROC : process(CLK) --- begin --- if(rising_edge(CLK)) then --- if(RESET = '1') then --- rst_after_sub <= '0'; --- else --- rst_after_sub <= rst_after_sub_comb; --- end if; --- end if; --- end process RST_AFTER_SUB_PROC; --- --- -- counts all bytes loaded to divide data into frames --- bytesLoadedProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then --- bytes_loaded <= x"0000"; --- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then --- bytes_loaded <= bytes_loaded + x"1"; --- -- gk 05.12.10 --- -- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then --- -- bytes_loaded <= bytes_loaded + x"1"; --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then --- bytes_loaded <= bytes_loaded + x"1"; --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then --- bytes_loaded <= bytes_loaded + x"1"; --- end if; --- end if; --- end process bytesLoadedProc; --- --- -- size of subevent loaded from memory --- subSizeLoadedProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10 --- sub_size_loaded <= x"00000000"; --- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then --- -- was all_int_ctr --- -- gk 08.04.10 my_int_ctr changed to load_int_ctr --- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q; --- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo --- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then --- sub_size_loaded <= sub_size_loaded + x"4"; --- end if; --- end if; --- end process subSizeLoadedProc; --- --- -- counts only raw data bytes being loaded --- subBytesLoadedProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10 --- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count --- elsif (loadCurrentState = LOAD_DATA) then --- sub_bytes_loaded <= sub_bytes_loaded + x"1"; --- end if; --- end if; --- end process subBytesLoadedProc; --- --- -- counts the size of the large udp packet --- actualPacketProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then --- actual_packet_size <= x"0008"; --- elsif (fc_wr_en = '1') then --- actual_packet_size <= actual_packet_size + x"1"; --- end if; --- end if; --- end process actualPacketProc; --- --- actualQueueSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = CLEANUP) then --- actual_queue_size <= (others => '0'); --- elsif (loadCurrentState = LIDLE) then --- actual_queue_size <= queue_size; --- end if; --- end if; --- end process actualQueueSizeProc; --- --- -- amount of bytes left to send in current packet --- sizeLeftProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = CLEANUP) then --- size_left <= (others => '0'); --- elsif (loadCurrentState = LIDLE) then --- size_left <= queue_size; --- elsif (fc_wr_en = '1') then --- size_left <= size_left - 1; --- end if; --- end if; --- end process sizeLeftProc; --- --- -- HOT FIX: don't rely on CTS information, count the packets on your own. --- -- In this case, we increment the fragmented packet ID with EOD from ipu2gbe. --- THE_FC_IDENT_COUNTER_PROC: process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_ident <= (others => '0'); --- elsif (PC_END_OF_DATA_IN = '1') then --- fc_ident <= fc_ident + 1; --- end if; --- end if; --- end process THE_FC_IDENT_COUNTER_PROC; --- --- fc_flags_offset(15 downto 14) <= "00"; --- --- moreFragmentsProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then --- fc_flags_offset(13) <= '0'; --- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then --- if ((actual_queue_size - actual_packet_size) < max_frame_size) then --- fc_flags_offset(13) <= '0'; -- no more fragments --- else --- fc_flags_offset(13) <= '1'; -- more fragments --- end if; --- end if; --- end if; --- end process moreFragmentsProc; --- --- eodProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_eod <= '0'; --- elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then --- fc_eod <= '1'; --- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then --- fc_eod <= '1'; --- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then --- fc_eod <= '1'; --- else --- fc_eod <= '0'; --- end if; --- end if; --- end process eodProc; --- --- sodProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_sod <= '0'; --- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then --- fc_sod <= '1'; --- elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then --- fc_sod <= '1'; --- else --- fc_sod <= '0'; --- end if; --- end if; --- end process sodProc; --- --- offsetProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then --- fc_flags_offset(12 downto 0) <= (others => '0'); --- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then --- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3); --- end if; --- end if; --- end process offsetProc; --- --- fcIPSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET= '1') then --- fc_ip_size <= (others => '0'); --- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then --- if (size_left >= max_frame_size) then --- fc_ip_size <= max_frame_size; --- else --- fc_ip_size <= size_left(15 downto 0); --- end if; --- end if; --- end if; --- end process fcIPSizeProc; --- --- fcUDPSizeProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- fc_udp_size <= (others => '0'); --- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then --- fc_udp_size <= queue_size(15 downto 0); --- end if; --- end if; --- end process fcUDPSizeProc; - - ---*********************** --- SUBEVENT HEADERS WRITE AND READ ---*********************** - --- SUBEVENT_HEADERS_FIFO : fifo_16kx8 --- port map( --- Data => shf_data, --- WrClock => CLK, --- RdClock => CLK, --- WrEn => shf_wr_en, --- RdEn => shf_rd_en, --- Reset => RESET, --- RPReset => RESET, --- Q => shf_q, --- Empty => shf_empty, --- Full => shf_full --- ); --- --- -- write enable for SHF --- shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA)) --- else '0'; --- --- -- data multiplexing for SHF (convert 32bit LWs to 8bit) --- -- CHANGED. --- -- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC. --- shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, --- pc_trig_nr, my_int_ctr, fc_data) --- begin --- case saveSubCurrentState is --- when SIDLE => shf_data <= x"ac"; --- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8); --- when SAVE_TERM => shf_data <= fc_data; --- when others => shf_data <= x"00"; --- end case; --- end process shfDataProc; --- --- saveSubMachineProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- saveSubCurrentState <= SIDLE; --- else --- saveSubCurrentState <= saveSubNextState; --- end if; --- end if; --- end process saveSubMachineProc; --- --- saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN) --- begin --- case saveSubCurrentState is --- when SIDLE => --- save_state <= x"0"; --- if (PC_START_OF_SUB_IN = '1') then --- saveSubNextState <= SAVE_SIZE; --- -- this branch is dangerous! --- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len --- saveSubNextState <= SAVE_TERM; --- else --- saveSubNextState <= SIDLE; --- end if; --- when SAVE_SIZE => --- save_state <= x"1"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SAVE_DECODING; --- else --- saveSubNextState <= SAVE_SIZE; --- end if; --- when SAVE_DECODING => --- save_state <= x"2"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SAVE_ID; --- else --- saveSubNextState <= SAVE_DECODING; --- end if; --- when SAVE_ID => --- save_state <= x"3"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SAVE_TRIG_NR; --- else --- saveSubNextState <= SAVE_ID; --- end if; --- when SAVE_TRIG_NR => --- save_state <= x"4"; --- if (sub_int_ctr = 3) then --- saveSubNextState <= SIDLE; --- else --- saveSubNextState <= SAVE_TRIG_NR; --- end if; --- when SAVE_TERM => --- save_state <= x"5"; --- if (sub_int_ctr = 31) then --- saveSubNextState <= SIDLE; --- else --- saveSubNextState <= SAVE_TERM; --- end if; --- when others => --- save_state <= x"f"; --- saveSubNextState <= SIDLE; --- end case; --- end process; --- --- -- This counter is used for breaking down 32bit information words into 8bit bytes for --- -- storing them in the SHF. --- -- It is also used for the termination 32byte sequence. --- subIntProc: process( CLK ) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (saveSubCurrentState = SIDLE) then --- sub_int_ctr <= 0; --- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then --- sub_int_ctr <= 0; --- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then --- sub_int_ctr <= 0; --- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then --- sub_int_ctr <= sub_int_ctr + 1; --- end if; --- end if; --- end process subIntProc; --- --- debug(3 downto 0) <= constr_state; --- debug(7 downto 4) <= save_state; --- debug(11 downto 8) <= load_state; --- debug(27 downto 12) <= queue_size(15 downto 0); --- debug(28) <= df_full; --- debug(29) <= df_empty; --- debug(30) <= shf_full; --- debug(31) <= shf_empty; --- --- debug(47 downto 32) <= size_left(15 downto 0); --- debug(52 downto 48) <= all_ctr; --- debug(53) <= pc_ready; - --- outputs --- PC_READY_OUT <= pc_ready; --- TC_WR_EN_OUT <= fc_wr_en; --- TC_DATA_OUT <= fc_data; --- TC_IP_SIZE_OUT <= fc_ip_size; --- TC_UDP_SIZE_OUT <= fc_udp_size; --- -- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); --- -- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); --- TC_FLAGS_OFFSET_OUT <= fc_flags_offset; --- TC_SOD_OUT <= fc_sod; --- TC_EOD_OUT <= fc_eod; - ---PC_READY_OUT <= '1'; ---TC_IP_SIZE_OUT <= (others => '0'); ---TC_UDP_SIZE_OUT <= (others => '0'); --- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); --- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); --- TC_FLAGS_OFFSET_OUT <= fc_flags_offset; --- TC_SOD_OUT <= fc_sod; --- TC_EOD_OUT <= fc_eod; - -DEBUG_OUT <= debug; - -end trb_net16_gbe_packet_constr; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd b/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd deleted file mode 100644 index d7dd176..0000000 --- a/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd +++ /dev/null @@ -1,87 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- maps the frame type and protocol code into internal value which sets the priority - -entity trb_net16_gbe_protocol_prioritizer is -port ( - CLK : in std_logic; - RESET : in std_logic; - - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type - PROTOCOL_CODE_IN : in std_logic_vector(7 downto 0); -- ip protocol - UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); - - CODE_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0) -); -end trb_net16_gbe_protocol_prioritizer; - - -architecture trb_net16_gbe_protocol_prioritizer of trb_net16_gbe_protocol_prioritizer is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_protocol_prioritizer : architecture is "GBE_MAIN_group"; - -begin - -PRIORITIZE : process(RESET, CLK) -begin - if RESET = '1' then - CODE_OUT <= (others => '0'); - elsif rising_edge(CLK) then - - CODE_OUT <= (others => '0'); - - --**** HERE ADD YOU PROTOCOL RECOGNITION AT WANTED PRIORITY LEVEL - -- priority level is the bit position in the CODE_OUT vector - -- less significant bit has the higher priority - case FRAME_TYPE_IN is - - -- IPv4 - when x"0800" => - if (PROTOCOL_CODE_IN = x"11") then -- UDP - -- No. 2 = DHCP - if (UDP_PROTOCOL_IN = x"0044") then -- DHCP Client - CODE_OUT(1) <= '1'; - -- No. 4 = SCTRL - elsif (UDP_PROTOCOL_IN = x"6590") then -- SCTRL module - CODE_OUT(2) <= '1'; - else - -- branch for pure IPv4 - CODE_OUT <= (others => '0'); - end if; - -- No. 3 = ICMP - elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP - CODE_OUT(4) <= '1'; - else - CODE_OUT <= (others => '0'); - end if; - - -- No. 1 = ARP - when x"0806" => - CODE_OUT(0) <= '1'; - - -- last slot is reserved for Trash - when others => - CODE_OUT <= (others => '0'); - - end case; - - end if; - -end process PRIORITIZE; - -end trb_net16_gbe_protocol_prioritizer; - - diff --git a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd deleted file mode 100644 index a6122ba..0000000 --- a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd +++ /dev/null @@ -1,690 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- multiplexes between different protocols and manages the responses --- --- - - -entity trb_net16_gbe_protocol_selector is - generic( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0 - ); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - RESET_FOR_DHCP : in std_logic; - --- signals to/from main controller - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - PS_RESPONSE_READY_OUT : out std_logic; - - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - --- singals to/from transmit controller with constructed response - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_RD_EN_IN : in std_logic; - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - MC_BUSY_IN : in std_logic; - - -- misc signals for response constructors - DHCP_START_IN : in std_logic; - DHCP_DONE_OUT : out std_logic; - - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - MAKE_RESET_OUT : out std_logic; - - -- signal for data readout - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - CFG_ADDITIONAL_HDR_IN : in std_logic; - - -- input for statistics from outside - STAT_DATA_IN : in std_logic_vector(31 downto 0); - STAT_ADDR_IN : in std_logic_vector(7 downto 0); - STAT_DATA_RDY_IN : in std_logic; - STAT_DATA_ACK_OUT : out std_logic; - - MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_OUT : out hist_array; - SCTRL_HIST_OUT : out hist_array -); -end trb_net16_gbe_protocol_selector; - - -architecture trb_net16_gbe_protocol_selector of trb_net16_gbe_protocol_selector is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal tc_data : std_logic_vector(c_MAX_PROTOCOLS * 9 - 1 downto 0); -signal tc_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal tc_type : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal selected : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal tc_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0); -signal tc_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal tc_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal tc_src_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0); -signal tc_src_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal tc_src_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0); - --- plus 1 is for the outside -signal stat_data : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); -signal stat_addr : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0); -signal stat_rdy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal stat_ack : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal tc_ip_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal tc_udp_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal tc_size_left : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal tc_flags_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); - -signal tc_data_not_valid : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - -type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP); -signal select_current_state, select_next_state : select_states; -attribute syn_encoding of select_current_state : signal is "onehot"; - -signal state : std_logic_vector(3 downto 0); -signal index : integer range 0 to c_MAX_PROTOCOLS - 1; - -signal mult : std_logic; - -signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); -signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of state, mult : signal is true; -attribute syn_preserve of state, mult : signal is true; - - -begin - -zeros <= (others => '0'); - --- protocol Nr. 1 ARP -ARP : trb_net16_gbe_response_constructor_ARP -generic map( STAT_ADDRESS_BASE => 6 -) -port map ( - CLK => CLK, - RESET => RESET, - --- INTERFACE - PS_DATA_IN => PS_DATA_IN, - PS_WR_EN_IN => PS_WR_EN_IN, - PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0), - PS_RESPONSE_READY_OUT => resp_ready(0), - PS_BUSY_OUT => busy(0), - PS_SELECTED_IN => selected(0), - - PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, - PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, - PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, - PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, - PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, - PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, - - TC_RD_EN_IN => TC_RD_EN_IN, - TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9), - TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16), - TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16), - TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8), - TC_IDENT_OUT => tc_ident(1 * 16 - 1 downto 0 * 16), - - TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48), - TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32), - TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16), - TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48), - TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32), - TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16), - - STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32), - STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8), - STAT_DATA_RDY_OUT => stat_rdy(0), - STAT_DATA_ACK_IN => stat_ack(0), - RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16), - SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16), - DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32) --- END OF INTERFACE -); - --- protocol No. 2 DHCP -DHCP : trb_net16_gbe_response_constructor_DHCP -generic map( STAT_ADDRESS_BASE => 0 -) -port map ( - CLK => CLK, - RESET => RESET_FOR_DHCP, --RESET, - --- INTERFACE - PS_DATA_IN => PS_DATA_IN, - PS_WR_EN_IN => PS_WR_EN_IN, - PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1), - PS_RESPONSE_READY_OUT => resp_ready(1), - PS_BUSY_OUT => busy(1), - PS_SELECTED_IN => selected(1), - - PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, - PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, - PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, - PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, - PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, - PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, - - TC_RD_EN_IN => TC_RD_EN_IN, - TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9), - TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16), - TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16), - TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8), - TC_IDENT_OUT => tc_ident(2 * 16 - 1 downto 1 * 16), - - TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48), - TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32), - TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16), - TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48), - TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32), - TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16), - - STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32), - STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8), - STAT_DATA_RDY_OUT => stat_rdy(1), - STAT_DATA_ACK_IN => stat_ack(1), - RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16), - SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16), --- END OF INTERFACE - - DHCP_START_IN => DHCP_START_IN, - DHCP_DONE_OUT => DHCP_DONE_OUT, - - DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32) - ); - - --protocol No. 3 Ping -Ping : trb_net16_gbe_response_constructor_Ping -generic map( STAT_ADDRESS_BASE => 3 -) -port map ( - CLK => CLK, - RESET => RESET, - ----- INTERFACE - PS_DATA_IN => PS_DATA_IN, - PS_WR_EN_IN => PS_WR_EN_IN, - PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4), - PS_RESPONSE_READY_OUT => resp_ready(4), - PS_BUSY_OUT => busy(4), - PS_SELECTED_IN => selected(4), - - PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, - PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, - PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, - PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, - PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, - PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, - - TC_RD_EN_IN => TC_RD_EN_IN, - TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9), - TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16), - TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16), - TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8), - TC_IDENT_OUT => tc_ident(5 * 16 - 1 downto 4 * 16), - - TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48), - TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32), - TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16), - TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48), - TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32), - TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16), - - STAT_DATA_OUT => open, - STAT_ADDR_OUT => open, - STAT_DATA_RDY_OUT => open, - STAT_DATA_ACK_IN => '0', - RECEIVED_FRAMES_OUT => open, - SENT_FRAMES_OUT => open, - DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(5 * 64 - 1 downto 4 * 64) --- END OF INTERFACE -); - -SCTRL : trb_net16_gbe_response_constructor_SCTRL -generic map( STAT_ADDRESS_BASE => 8 -) -port map ( - CLK => CLK, - RESET => RESET, - --- INTERFACE - PS_DATA_IN => PS_DATA_IN, - PS_WR_EN_IN => PS_WR_EN_IN, - PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2), - PS_RESPONSE_READY_OUT => resp_ready(2), - PS_BUSY_OUT => busy(2), - PS_SELECTED_IN => selected(2), - - PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, - PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, - PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, - PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, - PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, - PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, - - TC_RD_EN_IN => TC_RD_EN_IN, - TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9), - TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16), - TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16), - TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8), - TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16), - - TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48), - TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32), - TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16), - TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48), - TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32), - TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16), - - STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32), - STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8), - STAT_DATA_RDY_OUT => stat_rdy(2), - STAT_DATA_ACK_IN => stat_ack(2), - - DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(3 * 64 - 1 downto 2 * 64), - -- END OF INTERFACE - - GSC_CLK_IN => GSC_CLK_IN, - GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - GSC_INIT_READ_IN => GSC_INIT_READ_IN, - GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, - GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, - GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, - GSC_BUSY_IN => GSC_BUSY_IN, - CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, - MAKE_RESET_OUT => MAKE_RESET_OUT, - - MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(3 * 32 - 1 downto 2 * 32), - MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(3 * 32 - 1 downto 2 * 32), - MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(3 * 32 - 1 downto 2 * 32), - MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(3 * 32 - 1 downto 2 * 32), - - DATA_HIST_OUT => SCTRL_HIST_OUT -); - -TrbNetData : trb_net16_gbe_response_constructor_TrbNetData -generic map( - RX_PATH_ENABLE => RX_PATH_ENABLE, - DO_SIMULATION => DO_SIMULATION - ) -port map ( - CLK => CLK, - RESET => RESET, - --- INTERFACE - PS_DATA_IN => PS_DATA_IN, - PS_WR_EN_IN => PS_WR_EN_IN, - PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3), - PS_RESPONSE_READY_OUT => resp_ready(3), - PS_BUSY_OUT => busy(3), - PS_SELECTED_IN => selected(3), - - PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, - PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, - PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, - PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, - PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, - PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, - - TC_RD_EN_IN => TC_RD_EN_IN, - TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9), - TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16), - TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16), - TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8), - TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16), - - TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48), - TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32), - TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16), - TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48), - TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32), - TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16), - - STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32), - STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8), - STAT_DATA_RDY_OUT => stat_rdy(3), - STAT_DATA_ACK_IN => stat_ack(3), - - DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64), --- END OF INTERFACE - - -- CTS interface - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data payload interface - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- ip configurator - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - - CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, - CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, - CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, - CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, - CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, - CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, - CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, - CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, - CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, - CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, - CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, - CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, - CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, - - MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32), - MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32), - MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32), - MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32), - MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32), - MONITOR_SELECT_DROP_IN_OUT => open, - - DATA_HIST_OUT => DATA_HIST_OUT -); - ---stat_gen : if g_SIMULATE = 0 generate ---Stat : trb_net16_gbe_response_constructor_Stat ---generic map( STAT_ADDRESS_BASE => 10 ---) ---port map ( --- CLK => CLK, --- RESET => RESET, --- ----- INTERFACE --- PS_DATA_IN => PS_DATA_IN, --- PS_WR_EN_IN => PS_WR_EN_IN, --- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4), --- PS_RESPONSE_READY_OUT => resp_ready(4), --- PS_BUSY_OUT => busy(4), --- PS_SELECTED_IN => selected(4), --- --- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, --- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN, --- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, --- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN, --- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, --- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN, --- --- TC_WR_EN_OUT => TC_WR_EN_OUT, --- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9), --- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16), --- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16), --- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8), --- --- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48), --- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32), --- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16), --- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48), --- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32), --- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16), --- --- TC_IP_SIZE_OUT => tc_ip_size(5 * 16 - 1 downto 4 * 16), --- TC_UDP_SIZE_OUT => tc_udp_size(5 * 16 - 1 downto 4 * 16), --- TC_FLAGS_OFFSET_OUT => tc_flags_size(5 * 16 - 1 downto 4 * 16), --- --- TC_BUSY_IN => TC_BUSY_IN, --- --- STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32), --- STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8), --- STAT_DATA_RDY_OUT => stat_rdy(4), --- STAT_DATA_ACK_IN => stat_ack(4), --- --- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16), --- SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16), --- DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32), --- --- STAT_DATA_IN => stat_data, --- STAT_ADDR_IN => stat_addr, --- STAT_DATA_RDY_IN => stat_rdy, --- STAT_DATA_ACK_OUT => stat_ack ---); ---end generate; - ---*************** --- DO NOT TOUCH, response selection logic - ---stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN; ---stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN; ---stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN; ---STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS); - ---mult <= or_all(resp_ready(2 downto 0)); --or_all(resp_ready(2 downto 0)) and or_all(resp_ready(4 downto 3)); - -PS_BUSY_OUT <= busy; - -SELECT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - select_current_state <= IDLE; - elsif rising_edge(CLK) then --- if (RESET = '1') then --- select_current_state <= IDLE; --- else - select_current_state <= select_next_state; --- end if; - end if; -end process SELECT_MACHINE_PROC; - -SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros, busy) -begin - - case (select_current_state) is - - when IDLE => - if (MC_BUSY_IN = '0') then - select_next_state <= LOOP_OVER; - else - select_next_state <= IDLE; - end if; - - when LOOP_OVER => - if (resp_ready /= zeros) then - if (resp_ready(index) = '1') then - select_next_state <= SELECT_ONE; - elsif (index = c_MAX_PROTOCOLS) then - select_next_state <= CLEANUP; - else - select_next_state <= LOOP_OVER; - end if; - else - select_next_state <= CLEANUP; - end if; - - when SELECT_ONE => - if (MC_BUSY_IN = '1') then - select_next_state <= PROCESS_REQUEST; - else - select_next_state <= SELECT_ONE; - end if; - - when PROCESS_REQUEST => - if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then - select_next_state <= CLEANUP; - else - select_next_state <= PROCESS_REQUEST; - end if; - - when CLEANUP => - select_next_state <= IDLE; - - end case; - -end process SELECT_MACHINE; - -INDEX_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (select_current_state = IDLE) then - index <= 0; - elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0') then - index <= index + 1; - else - index <= index; - end if; - end if; -end process INDEX_PROC; - -SELECTOR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST) then - TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9); - TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16); - TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16); - TC_DEST_MAC_OUT <= tc_mac((index + 1) * 48 - 1 downto index * 48); - TC_DEST_IP_OUT <= tc_ip((index + 1) * 32 - 1 downto index * 32); - TC_DEST_UDP_OUT <= tc_udp((index + 1) * 16 - 1 downto index * 16); - TC_SRC_MAC_OUT <= tc_src_mac((index + 1) * 48 - 1 downto index * 48); - TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32); - TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16); - TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8); - TC_IDENT_OUT <= tc_ident((index + 1) * 16 - 1 downto index * 16); - if (select_current_state = SELECT_ONE) then - PS_RESPONSE_READY_OUT <= '1'; - selected(index) <= '0'; - else - PS_RESPONSE_READY_OUT <= '0'; - selected(index) <= '1'; - end if; - else - TC_DATA_OUT <= (others => '0'); - TC_FRAME_SIZE_OUT <= (others => '0'); - TC_FRAME_TYPE_OUT <= (others => '0'); - TC_DEST_MAC_OUT <= (others => '0'); - TC_DEST_IP_OUT <= (others => '0'); - TC_DEST_UDP_OUT <= (others => '0'); - TC_SRC_MAC_OUT <= (others => '0'); - TC_SRC_IP_OUT <= (others => '0'); - TC_SRC_UDP_OUT <= (others => '0'); - TC_IP_PROTOCOL_OUT <= (others => '0'); - TC_IDENT_OUT <= (others => '0'); - PS_RESPONSE_READY_OUT <= '0'; - selected <= (others => '0'); - end if; - end if; -end process SELECTOR_PROC; - -end trb_net16_gbe_protocol_selector; - - diff --git a/gbe2_ecp3/trb_net16_gbe_receive_control.vhd b/gbe2_ecp3/trb_net16_gbe_receive_control.vhd deleted file mode 100644 index 4a7bc6f..0000000 --- a/gbe2_ecp3/trb_net16_gbe_receive_control.vhd +++ /dev/null @@ -1,256 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- controller has to control the rest of the logic (TX part, TS_MAC, HUB) accordingly to --- the message received from receiver, frame checking is already done --- - - -entity trb_net16_gbe_receive_control is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- signals to/from frame_receiver - RC_DATA_IN : in std_logic_vector(8 downto 0); - FR_RD_EN_OUT : out std_logic; - FR_FRAME_VALID_IN : in std_logic; - FR_GET_FRAME_OUT : out std_logic; - FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0); - FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - - FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - --- signals to/from main controller - RC_RD_EN_IN : in std_logic; - RC_Q_OUT : out std_logic_vector(8 downto 0); - RC_FRAME_WAITING_OUT : out std_logic; - RC_LOADING_DONE_IN : in std_logic; - RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - - RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - --- statistics - FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_receive_control; - - -architecture trb_net16_gbe_receive_control of trb_net16_gbe_receive_control is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_receive_control : architecture is "GBE_MAIN_group"; -attribute syn_encoding : string; - -type load_states is (IDLE, PREPARE, WAIT_ONE, READY); -signal load_current_state, load_next_state : load_states; -attribute syn_encoding of load_current_state : signal is "onehot"; - -signal frames_received_ctr : std_logic_vector(31 downto 0); -signal frames_readout_ctr : std_logic_vector(31 downto 0); -signal bytes_rec_ctr : std_logic_vector(31 downto 0); - -signal state : std_logic_vector(3 downto 0); -signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal reset_prioritizer : std_logic; -signal frame_waiting : std_logic; - --- debug only -signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - -begin - -FR_RD_EN_OUT <= RC_RD_EN_IN; -RC_Q_OUT <= RC_DATA_IN; -RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN; -RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN; -RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN; -RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN; -RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN; -RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN; -RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN; - -protocol_prioritizer : trb_net16_gbe_protocol_prioritizer -port map( - CLK => CLK, - RESET => reset_prioritizer, - - FRAME_TYPE_IN => FR_FRAME_PROTO_IN, - PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN, - UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN, - - CODE_OUT => proto_code -); - -reset_prioritizer <= '1' when load_current_state = IDLE else '0'; - ---RC_FRAME_PROTO_OUT <= proto_code when (and_all(proto_code) = '0') else (others => '0'); -RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash - ---DEBUG_OUT(3 downto 0) <= state; ---DEBUG_OUT(11 downto 4) <= frames_received_ctr(7 downto 0); ---DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0); ---DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0); - -LOAD_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - load_current_state <= IDLE; - elsif rising_edge(CLK) then - load_current_state <= load_next_state; - end if; -end process LOAD_MACHINE_PROC; - -LOAD_MACHINE : process(load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN) -begin - case load_current_state is - - when IDLE => - state <= x"1"; - if (frames_readout_ctr /= frames_received_ctr) then -- frame is still waiting in frame_receiver - load_next_state <= PREPARE; - else - load_next_state <= IDLE; - end if; - - when PREPARE => -- prepare frame size - state <= x"2"; - load_next_state <= WAIT_ONE; --READY; - - when WAIT_ONE => - load_next_state <= READY; - - when READY => -- wait for reading out the whole frame - state <= x"3"; - if (RC_LOADING_DONE_IN = '1') then - load_next_state <= IDLE; - else - load_next_state <= READY; - end if; - - end case; -end process LOAD_MACHINE; - -process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = PREPARE) then - FR_GET_FRAME_OUT <= '1'; - else - FR_GET_FRAME_OUT <= '0'; - end if; - - if (load_current_state = READY and RC_LOADING_DONE_IN = '0') then - RC_FRAME_WAITING_OUT <= '1'; - else - RC_FRAME_WAITING_OUT <= '0'; - end if; - - --RC_FRAME_WAITING_OUT <= frame_waiting; - end if; -end process; - ---FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE) --- else '0'; --- ---RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY) --- else '0'; - ---SYNC_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- FRAMES_RECEIVED_OUT <= frames_received_ctr; --- --BYTES_RECEIVED_OUT <= bytes_rec_ctr; --- BYTES_RECEIVED_OUT(15 downto 0) <= bytes_rec_ctr(15 downto 0); --- BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto; --- BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0'); --- end if; ---end process SYNC_PROC; - -FRAMES_REC_CTR_PROC : process(RESET, CLK) -begin - if (RESET = '1') then - frames_received_ctr <= (others => '0'); - elsif rising_edge(CLK) then - if (FR_FRAME_VALID_IN = '1') then - frames_received_ctr <= frames_received_ctr + x"1"; - else - frames_received_ctr <= frames_received_ctr; - end if; - end if; -end process FRAMES_REC_CTR_PROC; - -FRAMES_READOUT_CTR_PROC : process(RESET, CLK) -begin - if (RESET = '1') then - frames_readout_ctr <= (others => '0'); - elsif rising_edge(CLK) then - if (RC_LOADING_DONE_IN = '1') then - frames_readout_ctr <= frames_readout_ctr + x"1"; - else - frames_readout_ctr <= frames_readout_ctr; - end if; - end if; -end process FRAMES_READOUT_CTR_PROC; - --- debug only -BYTES_REC_CTR_PROC : process(RESET, CLK) -begin - if (RESET = '1') then - bytes_rec_ctr <= (others => '0'); - elsif rising_edge(CLK) then - if (FR_FRAME_VALID_IN = '1') then - bytes_rec_ctr <= bytes_rec_ctr + FR_FRAME_SIZE_IN; - else - bytes_rec_ctr <= bytes_rec_ctr; - end if; - end if; -end process BYTES_REC_CTR_PROC; - -SAVED_PROTO_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (load_current_state = READY) then - if (and_all(proto_code) = '0') then - saved_proto <= proto_code; - else - saved_proto <= (others => '0'); - end if; - else - saved_proto <= saved_proto; - end if; - end if; -end process SAVED_PROTO_PROC; --- end of debug - - -end trb_net16_gbe_receive_control; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd deleted file mode 100644 index 8154f9f..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd +++ /dev/null @@ -1,418 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- creates a reply for an incoming ARP request - -entity trb_net16_gbe_response_constructor_ARP is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_response_constructor_ARP; - - -architecture trb_net16_gbe_response_constructor_ARP of trb_net16_gbe_response_constructor_ARP is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_response_constructor_ARP : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -type dissect_states is (IDLE, READ_FRAME, DECIDE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state: signal is "onehot"; - -type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP); -signal stats_current_state, stats_next_state : stats_states; -attribute syn_encoding of stats_current_state : signal is "onehot"; - -signal saved_opcode : std_logic_vector(15 downto 0); -signal saved_sender_ip : std_logic_vector(31 downto 0); -signal saved_target_ip : std_logic_vector(31 downto 0); -signal data_ctr : integer range 0 to 30; -signal values : std_logic_vector(223 downto 0); -signal tc_data : std_logic_vector(8 downto 0); - -signal state : std_logic_vector(3 downto 0); -signal rec_frames : std_logic_vector(15 downto 0); -signal sent_frames : std_logic_vector(15 downto 0); -signal stat_data_temp : std_logic_vector(31 downto 0); - -signal tc_wr : std_logic; - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of state : signal is true; -attribute syn_preserve of state : signal is true; - -begin - -values(15 downto 0) <= x"0100"; -- hardware type -values(31 downto 16) <= x"0008"; -- protocol type -values(39 downto 32) <= x"06"; -- hardware size -values(47 downto 40) <= x"04"; -- protocol size -values(63 downto 48) <= x"0200"; --opcode (reply) -values(111 downto 64) <= g_MY_MAC; -- sender (my) mac -values(143 downto 112) <= g_MY_IP; -values(191 downto 144) <= PS_SRC_MAC_ADDRESS_IN; -- target mac -values(223 downto 192) <= saved_sender_ip; -- target ip - -DISSECT_MACHINE_PROC : process(CLK) -begin - if RESET = '1' then - dissect_current_state <= IDLE; - elsif rising_edge(CLK) then --- if (RESET = '1') then --- dissect_current_state <= IDLE; --- else - dissect_current_state <= dissect_next_state; --- end if; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, g_MY_IP, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, PS_SELECTED_IN, saved_target_ip) -begin - case dissect_current_state is - - when IDLE => - state <= x"1"; - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - dissect_next_state <= READ_FRAME; - else - dissect_next_state <= IDLE; - end if; - - when READ_FRAME => - state <= x"2"; - if (PS_DATA_IN(8) = '1') then - dissect_next_state <= DECIDE; - else - dissect_next_state <= READ_FRAME; - end if; - - when DECIDE => - state <= x"3"; - if (saved_target_ip = g_MY_IP or g_SIMULATE = 1) then - dissect_next_state <= WAIT_FOR_LOAD; - -- in case the request is not for me, drop it - else - dissect_next_state <= IDLE; - end if; - - when WAIT_FOR_LOAD => - state <= x"4"; - if (PS_SELECTED_IN = '1') then - dissect_next_state <= LOAD_FRAME; - else - dissect_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD_FRAME => - state <= x"5"; - if (data_ctr = 28) then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= LOAD_FRAME; - end if; - - when CLEANUP => - state <= x"e"; - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - -DATA_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (dissect_current_state = IDLE and PS_WR_EN_IN = '0') then - data_ctr <= 1; - elsif (dissect_current_state = WAIT_FOR_LOAD) then - data_ctr <= 1; - elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - data_ctr <= data_ctr + 1; - elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame - data_ctr <= data_ctr + 1; - elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response - data_ctr <= data_ctr + 1; - end if; - end if; -end process DATA_CTR_PROC; - ---TC_WR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1') then --- tc_wr <= '1'; --- else --- tc_wr <= '0'; --- end if; --- end if; ---end process TC_WR_PROC; - -SAVE_VALUES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saved_opcode <= (others => '0'); - saved_sender_ip <= (others => '0'); - saved_target_ip <= (others => '0'); - elsif (dissect_current_state = READ_FRAME) then - case (data_ctr) is - - when 6 => - saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0); - when 7 => - saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0); - - - when 13 => - saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); - when 14 => - saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); - when 15 => - saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); - when 16 => - saved_sender_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); - - when 23 => - saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); - when 24 => - saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); - when 25 => - saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); - when 26 => - saved_target_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); - - when others => null; - end case; - end if; - end if; -end process SAVE_VALUES_PROC; - -TC_DATA_PROC : process(dissect_current_state, data_ctr, values) -begin - if rising_edge(CLK) then - tc_data(8) <= '0'; - - if (dissect_current_state = LOAD_FRAME) then - for i in 0 to 7 loop - tc_data(i) <= values((data_ctr - 1) * 8 + i); - end loop; - -- mark the last byte - if (data_ctr = 28) then - tc_data(8) <= '1'; - end if; - else - tc_data(7 downto 0) <= (others => '0'); - end if; - - TC_DATA_OUT <= tc_data; - - end if; -end process TC_DATA_PROC; - ---TC_WR_EN_OUT <= tc_wr; - -PS_RESPONSE_SYNC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then - PS_RESPONSE_READY_OUT <= '1'; - else - PS_RESPONSE_READY_OUT <= '0'; - end if; - - if (dissect_current_state = IDLE) then - PS_BUSY_OUT <= '0'; - else - PS_BUSY_OUT <= '1'; - end if; - end if; -end process PS_RESPONSE_SYNC; - - - -TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size - -TC_FRAME_TYPE_OUT <= x"0608"; -TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; -TC_DEST_IP_OUT <= x"00000000"; -- doesnt matter -TC_DEST_UDP_OUT <= x"0000"; -- doesnt matter -TC_SRC_MAC_OUT <= g_MY_MAC; -TC_SRC_IP_OUT <= x"00000000"; -- doesnt matter -TC_SRC_UDP_OUT <= x"0000"; -- doesnt matter -TC_IP_PROTOCOL_OUT <= x"00"; -- doesnt matter -TC_IDENT_OUT <= (others => '0'); -- doesn't matter - - --- **** statistice ---REC_FRAMES_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- rec_frames <= (others => '0'); --- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then --- rec_frames <= rec_frames + x"1"; --- end if; --- end if; ---end process REC_FRAMES_PROC; --- ---SENT_FRAMES_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- sent_frames <= (others => '0'); --- elsif (dissect_current_state = CLEANUP) then --- sent_frames <= sent_frames + x"1"; --- end if; --- end if; ---end process SENT_FRAMES_PROC; --- ---RECEIVED_FRAMES_OUT <= rec_frames; ---SENT_FRAMES_OUT <= sent_frames; ---STATS_MACHINE_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- stats_current_state <= IDLE; --- else --- stats_current_state <= stats_next_state; --- end if; --- end if; ---end process STATS_MACHINE_PROC; --- ---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state) ---begin --- --- case (stats_current_state) is --- --- when IDLE => --- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then --- stats_next_state <= LOAD_SENT; --- else --- stats_next_state <= IDLE; --- end if; --- --- when LOAD_SENT => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= LOAD_RECEIVED; --- else --- stats_next_state <= LOAD_SENT; --- end if; --- --- when LOAD_RECEIVED => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= CLEANUP; --- else --- stats_next_state <= LOAD_RECEIVED; --- end if; --- --- when CLEANUP => --- stats_next_state <= IDLE; --- --- end case; --- ---end process STATS_MACHINE; --- ---SELECTOR : process(CLK) ---begin --- if rising_edge(CLK) then --- case(stats_current_state) is --- --- when LOAD_SENT => --- stat_data_temp <= x"0601" & sent_frames; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); --- --- when LOAD_RECEIVED => --- stat_data_temp <= x"0602" & rec_frames; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); --- --- when others => --- stat_data_temp <= (others => '0'); --- STAT_ADDR_OUT <= (others => '0'); --- --- end case; --- end if; ---end process SELECTOR; --- ---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); ---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); ---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); ---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); --- ---STAT_SYNC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then --- STAT_DATA_RDY_OUT <= '1'; --- else --- STAT_DATA_RDY_OUT <= '0'; --- end if; --- end if; ---end process STAT_SYNC; -----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; --- ----- **** debug ---DEBUG_OUT(3 downto 0) <= state; ---DEBUG_OUT(4) <= '0'; ---DEBUG_OUT(7 downto 5) <= "000"; ---DEBUG_OUT(8) <= '0'; ---DEBUG_OUT(11 downto 9) <= "000"; ---DEBUG_OUT(31 downto 12) <= (others => '0'); ----- **** - -end trb_net16_gbe_response_constructor_ARP; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd deleted file mode 100644 index d4d301b..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd +++ /dev/null @@ -1,818 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- - -entity trb_net16_gbe_response_constructor_DHCP is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - - DHCP_START_IN : in std_logic; - DHCP_DONE_OUT : out std_logic; - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_response_constructor_DHCP; - - -architecture trb_net16_gbe_response_constructor_DHCP of trb_net16_gbe_response_constructor_DHCP is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_response_constructor_DHCP : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -type main_states is (BOOTING, DELAY, SENDING_DISCOVER, WAITING_FOR_OFFER, SENDING_REQUEST, WAITING_FOR_ACK, ESTABLISHED); -signal main_current_state, main_next_state : main_states; -attribute syn_encoding of main_current_state: signal is "onehot"; - -type receive_states is (IDLE, DISCARD, CLEANUP, SAVE_VALUES); -signal receive_current_state, receive_next_state : receive_states; -attribute syn_encoding of receive_current_state: signal is "onehot"; - -type discover_states is (IDLE, WAIT_FOR_LOAD, BOOTP_HEADERS, CLIENT_IP, YOUR_IP, ZEROS1, MY_MAC, ZEROS2, VENDOR_VALS, VENDOR_VALS2, TERMINATION, CLEANUP); -signal construct_current_state, construct_next_state : discover_states; -attribute syn_encoding of construct_current_state: signal is "onehot"; - - -type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, LOAD_DISCARDED, CLEANUP); -signal stats_current_state, stats_next_state : stats_states; -attribute syn_encoding of stats_current_state : signal is "onehot"; - -signal state : std_logic_vector(3 downto 0); -signal rec_frames : std_logic_vector(15 downto 0); -signal sent_frames : std_logic_vector(15 downto 0); - -signal wait_ctr : std_logic_vector(31 downto 0); -- wait for 5 sec before sending request -signal load_ctr : integer range 0 to 600 := 0; - -signal bootp_hdr : std_logic_vector(95 downto 0); - -signal tc_data : std_logic_vector(8 downto 0); -signal vendor_values : std_logic_vector(175 downto 0); -signal save_ctr : integer range 0 to 600 := 0; -signal saved_transaction_id : std_logic_vector(31 downto 0); -signal saved_proposed_ip : std_logic_vector(31 downto 0); -signal saved_dhcp_type : std_logic_vector(23 downto 0); -signal saved_true_ip : std_logic_vector(31 downto 0); -signal transaction_id : std_logic_vector(31 downto 0); -signal client_ip_reg : std_logic_vector(31 downto 0); -signal your_ip_reg : std_logic_vector(31 downto 0); -signal saved_server_mac : std_logic_vector(47 downto 0); -signal saved_server_ip : std_logic_vector(31 downto 0); -signal state2 : std_logic_vector(3 downto 0); -signal state3 : std_logic_vector(3 downto 0); -signal vendor_values2 : std_logic_vector(47 downto 0); - -signal discarded_ctr : std_logic_vector(15 downto 0); - -signal stat_data_temp : std_logic_vector(31 downto 0); - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of state, state2 : signal is true; -attribute syn_preserve of state, state2 : signal is true; - -begin - - --- **** --- fixing the constant values for DHCP request headers -TC_DEST_MAC_OUT <= x"ffffffffffff" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_server_mac; -TC_DEST_IP_OUT <= x"ffffffff" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_server_ip; -TC_DEST_UDP_OUT <= x"4300"; -TC_SRC_MAC_OUT <= g_MY_MAC; -TC_SRC_IP_OUT <= x"00000000" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else saved_proposed_ip; -TC_SRC_UDP_OUT <= x"4400"; -TC_IP_PROTOCOL_OUT <= x"11"; -- udp -bootp_hdr(7 downto 0) <= x"01"; -- message type(request) -bootp_hdr(15 downto 8) <= x"01"; -- hardware type (eth) -bootp_hdr(23 downto 16) <= x"06"; -- hardware address length -bootp_hdr(31 downto 24) <= x"00"; -- hops -bootp_hdr(63 downto 32) <= transaction_id; -- transaction id; -bootp_hdr(95 downto 64) <= x"0000_0000"; -- seconds elapsed/flags -transaction_id <= x"cefa" & g_MY_MAC(47 downto 32); -vendor_values(31 downto 0) <= x"63538263"; -- magic cookie (dhcp message) -vendor_values(55 downto 32) <= x"010135" when (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER) else x"030135"; -- dhcp discover, then dhcp request -vendor_values(79 downto 56) <= x"01073d"; -- client identifier -vendor_values(127 downto 80) <= g_MY_MAC; -- client identifier -vendor_values(143 downto 128) <= x"040c"; -- client name -vendor_values(175 downto 144) <= x"33425254"; -- client name (TRB3) -vendor_values2(15 downto 0) <= x"0436"; -- server identifier -vendor_values2(47 downto 16) <= saved_server_ip; - ---***************** --- setting of global variable for IP address -g_MY_IP <= saved_true_ip when main_current_state = ESTABLISHED else (others => '0'); --- ---***************** - -SAVE_SERVER_ADDR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (main_current_state = BOOTING) then - saved_server_mac <= (others => '0'); - saved_server_ip <= (others => '0'); - elsif (main_current_state = WAITING_FOR_OFFER) and (receive_current_state = SAVE_VALUES and save_ctr = 1) then - saved_server_mac <= PS_SRC_MAC_ADDRESS_IN; - saved_server_ip <= PS_SRC_IP_ADDRESS_IN; - else - saved_server_mac <= saved_server_mac; - saved_server_ip <= saved_server_ip; - end if; - end if; -end process SAVE_SERVER_ADDR_PROC; - - --- **** MAIN MACHINE PART - -MAIN_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - main_current_state <= BOOTING; - elsif rising_edge(CLK) then - main_current_state <= main_next_state; - end if; -end process MAIN_MACHINE_PROC; - -MAIN_MACHINE : process(main_current_state, DHCP_START_IN, construct_current_state, wait_ctr, receive_current_state, PS_DATA_IN) -begin - - case (main_current_state) is - - when BOOTING => - state2 <= x"1"; - if (DHCP_START_IN = '1') then - main_next_state <= DELAY; - else - main_next_state <= BOOTING; - end if; - - when DELAY => - if (wait_ctr = x"2000_0000") then - main_next_state <= SENDING_DISCOVER; - else - main_next_state <= DELAY; - end if; - - when SENDING_DISCOVER => - state2 <= x"2"; - if (construct_current_state = CLEANUP) then - main_next_state <= WAITING_FOR_OFFER; - else - main_next_state <= SENDING_DISCOVER; - end if; - - when WAITING_FOR_OFFER => - state2 <= x"3"; - if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then - main_next_state <= SENDING_REQUEST; - elsif (wait_ctr = x"2000_0000") then - main_next_state <= BOOTING; - else - main_next_state <= WAITING_FOR_OFFER; - end if; - - when SENDING_REQUEST => - state2 <= x"4"; - if (construct_current_state = CLEANUP) then - main_next_state <= WAITING_FOR_ACK; - else - main_next_state <= SENDING_REQUEST; - end if; - - when WAITING_FOR_ACK => - state2 <= x"5"; - if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then - main_next_state <= ESTABLISHED; - elsif (wait_ctr = x"2000_0000") then - main_next_state <= BOOTING; - else - main_next_state <= WAITING_FOR_ACK; - end if; - - when ESTABLISHED => - state2 <= x"6"; - main_next_state <= ESTABLISHED; - - end case; - -end process MAIN_MACHINE; - -WAIT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (main_current_state = SENDING_DISCOVER or main_current_state = SENDING_REQUEST or main_current_state = BOOTING) then - wait_ctr <= (others => '0'); - elsif (main_current_state = WAITING_FOR_ACK or main_current_state = WAITING_FOR_OFFER or main_current_state = DELAY) then - wait_ctr <= wait_ctr + x"1"; - else - wait_ctr <= wait_ctr; - end if; - end if; -end process WAIT_CTR_PROC; - -DHCP_DONE_OUT <= '1' when main_current_state = ESTABLISHED else '0'; - - --- **** MESSAGES RECEIVING PART - -RECEIVE_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - receive_current_state <= IDLE; - elsif rising_edge(CLK) then - receive_current_state <= receive_next_state; - end if; -end process RECEIVE_MACHINE_PROC; - -RECEIVE_MACHINE : process(receive_current_state, main_current_state, bootp_hdr, saved_dhcp_type, saved_transaction_id, PS_DATA_IN, PS_DEST_MAC_ADDRESS_IN, g_MY_MAC, PS_ACTIVATE_IN, PS_WR_EN_IN, save_ctr) -begin - case receive_current_state is - - when IDLE => - state3 <= x"1"; - if (PS_ACTIVATE_IN = '1' and PS_WR_EN_IN = '1') then - if (main_current_state = WAITING_FOR_OFFER or main_current_state = WAITING_FOR_ACK) then -- ready to receive dhcp frame - if (PS_DEST_MAC_ADDRESS_IN = g_MY_MAC) then -- check if i'm the addressee (discards broadcasts also) - receive_next_state <= SAVE_VALUES; - else - receive_next_state <= DISCARD; -- discard if the frame is not for me - end if; - else - receive_next_state <= DISCARD; -- discard if the frame arrived at wrong time - end if; - else - receive_next_state <= IDLE; - end if; - - when SAVE_VALUES => - state3 <= x"2"; - if (PS_DATA_IN(8) = '1') then - receive_next_state <= CLEANUP; - -- check if the same transaction - elsif (save_ctr = 9) and (saved_transaction_id /= bootp_hdr(63 downto 32)) then - receive_next_state <= DISCARD; - -- if the wrong message at the wrong time - elsif (main_current_state = WAITING_FOR_OFFER) and (save_ctr = 242) and (saved_dhcp_type /= x"020135") then - receive_next_state <= DISCARD; - -- if the wrong message at the wrong time - elsif (main_current_state = WAITING_FOR_ACK) and (save_ctr = 242) and (saved_dhcp_type /= x"050135") then - receive_next_state <= DISCARD; - else - receive_next_state <= SAVE_VALUES; - end if; - - when DISCARD => - state3 <= x"3"; - if (PS_DATA_IN(8) = '1') then - receive_next_state <= CLEANUP; - else - receive_next_state <= DISCARD; - end if; - - when CLEANUP => - state3 <= x"4"; - receive_next_state <= IDLE; - - end case; - -end process RECEIVE_MACHINE; - -SAVE_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (receive_current_state = IDLE) then - save_ctr <= 0; - elsif (receive_current_state = SAVE_VALUES and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - save_ctr <= save_ctr + 1; - else - save_ctr <= save_ctr; - end if; - end if; -end process SAVE_CTR_PROC; - -SAVE_VALUES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (main_current_state = BOOTING) then - saved_transaction_id <= (others => '0'); - saved_proposed_ip <= (others => '0'); - saved_true_ip <= (others => '0'); - saved_dhcp_type <= (others => '0'); - -- dissection of DHCP Offer message - elsif (main_current_state = WAITING_FOR_OFFER and receive_current_state = SAVE_VALUES) then - - saved_true_ip <= saved_true_ip; - - case save_ctr is - - when 3 => - saved_transaction_id(7 downto 0) <= PS_DATA_IN(7 downto 0); - - when 4 => - saved_transaction_id(15 downto 8) <= PS_DATA_IN(7 downto 0); - - when 5 => - saved_transaction_id(23 downto 16) <= PS_DATA_IN(7 downto 0); - - when 6 => - saved_transaction_id(31 downto 24) <= PS_DATA_IN(7 downto 0); - - - when 15 => - saved_proposed_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); - - when 16 => - saved_proposed_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); - - when 17 => - saved_proposed_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); - - when 18 => - saved_proposed_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); - - - when 239 => - saved_dhcp_type(7 downto 0) <= PS_DATA_IN(7 downto 0); - - when 240 => - saved_dhcp_type(15 downto 8) <= PS_DATA_IN(7 downto 0); - - when 241 => - saved_dhcp_type(23 downto 16) <= PS_DATA_IN(7 downto 0); - - when others => null; - - end case; - -- dissection on DHCP Ack message - elsif (main_current_state = WAITING_FOR_ACK and receive_current_state = SAVE_VALUES) then - - saved_proposed_ip <= saved_proposed_ip; - - case save_ctr is - - when 3 => - saved_transaction_id(7 downto 0) <= PS_DATA_IN(7 downto 0); - - when 4 => - saved_transaction_id(15 downto 8) <= PS_DATA_IN(7 downto 0); - - when 5 => - saved_transaction_id(23 downto 16) <= PS_DATA_IN(7 downto 0); - - when 6 => - saved_transaction_id(31 downto 24) <= PS_DATA_IN(7 downto 0); - - - when 15 => - saved_true_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); - - when 16 => - saved_true_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); - - when 17 => - saved_true_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); - - when 18 => - saved_true_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); - - - when 239 => - saved_dhcp_type(7 downto 0) <= PS_DATA_IN(7 downto 0); - - when 240 => - saved_dhcp_type(15 downto 8) <= PS_DATA_IN(7 downto 0); - - when 241 => - saved_dhcp_type(23 downto 16) <= PS_DATA_IN(7 downto 0); - - when others => null; - - end case; - else - saved_transaction_id <= saved_transaction_id; - saved_proposed_ip <= saved_proposed_ip; - saved_true_ip <= saved_true_ip; - saved_dhcp_type <= saved_dhcp_type; - end if; - end if; -end process SAVE_VALUES_PROC; - - --- **** MESSAGES CONSTRUCTING PART - -CONSTRUCT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - construct_current_state <= IDLE; - elsif rising_edge(CLK) then - if (main_current_state = BOOTING) then - construct_current_state <= IDLE; - else - construct_current_state <= construct_next_state; - end if; - end if; -end process CONSTRUCT_MACHINE_PROC; - -CONSTRUCT_MACHINE : process(construct_current_state, main_current_state, load_ctr, PS_SELECTED_IN) -begin - case construct_current_state is - - when IDLE => - state <= x"1"; - if (main_current_state = SENDING_DISCOVER) or (main_current_state = SENDING_REQUEST) then - construct_next_state <= WAIT_FOR_LOAD; - else - construct_next_state <= IDLE; - end if; - - when WAIT_FOR_LOAD => - state <= x"2"; - if (PS_SELECTED_IN = '1') then - construct_next_state <= BOOTP_HEADERS; - else - construct_next_state <= WAIT_FOR_LOAD; - end if; - - - when BOOTP_HEADERS => - state <= x"3"; - if (load_ctr = 11) then - construct_next_state <= CLIENT_IP; - else - construct_next_state <= BOOTP_HEADERS; - end if; - - when CLIENT_IP => - state <= x"5"; - if (load_ctr = 15) then - construct_next_state <= YOUR_IP; - else - construct_next_state <= CLIENT_IP; - end if; - - when YOUR_IP => - state <= x"b"; - if (load_ctr = 19) then - construct_next_state <= ZEROS1; - else - construct_next_state <= YOUR_IP; - end if; - - when ZEROS1 => - state <= x"c"; - if (load_ctr = 27) then - construct_next_state <= MY_MAC; - else - construct_next_state <= ZEROS1; - end if; - - when MY_MAC => - state <= x"6"; - if (load_ctr = 33) then - construct_next_state <= ZEROS2; - else - construct_next_state <= MY_MAC; - end if; - - when ZEROS2 => - state <= x"7"; - if (load_ctr = 235) then - construct_next_state <= VENDOR_VALS; - else - construct_next_state <= ZEROS2; - end if; - - when VENDOR_VALS => - state <= x"8"; - if (load_ctr = 257) then - -- for discover it's enough of values - if (main_current_state = SENDING_DISCOVER) then - construct_next_state <= TERMINATION; - -- for request there is some more values needed - else - construct_next_state <= VENDOR_VALS2; - end if; - else - construct_next_state <= VENDOR_VALS; - end if; - - when VENDOR_VALS2 => - state <= x"d"; - if (load_ctr = 263) then - construct_next_state <= TERMINATION; - else - construct_next_state <= VENDOR_VALS2; - end if; - - when TERMINATION => - state <= x"e"; - construct_next_state <= CLEANUP; - - when CLEANUP => - state <= x"9"; - construct_next_state <= IDLE; - - end case; -end process CONSTRUCT_MACHINE; - -LOAD_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (construct_current_state = IDLE) then - load_ctr <= 0; - elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then - load_ctr <= load_ctr + 1; - else - load_ctr <= load_ctr; - end if; - end if; -end process LOAD_CTR_PROC; - -TC_DATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - case (construct_current_state) is - - when BOOTP_HEADERS => - for i in 0 to 7 loop - tc_data(i) <= bootp_hdr(load_ctr * 8 + i); - end loop; - tc_data(8) <= '0'; - - when CLIENT_IP => - if (main_current_state = SENDING_DISCOVER) then - tc_data(7 downto 0) <= x"00"; - elsif (main_current_state = SENDING_REQUEST) then - for i in 0 to 7 loop - tc_data(i) <= saved_proposed_ip((load_ctr - 12) * 8 + i); - end loop; - end if; - tc_data(8) <= '0'; - - when YOUR_IP => - tc_data(7 downto 0) <= x"00"; - tc_data(8) <= '0'; - - when ZEROS1 => - tc_data(7 downto 0) <= x"00"; - tc_data(8) <= '0'; - - when MY_MAC => - for i in 0 to 7 loop - tc_data(i) <= g_MY_MAC((load_ctr - 28) * 8 + i); - end loop; - tc_data(8) <= '0'; - - when ZEROS2 => - tc_data(7 downto 0) <= x"00"; - tc_data(8) <= '0'; - - when VENDOR_VALS => - for i in 0 to 7 loop - tc_data(i) <= vendor_values((load_ctr - 236) * 8 + i); - end loop; - tc_data(8) <= '0'; - - -- needed only for DHCP Request message - when VENDOR_VALS2 => - for i in 0 to 7 loop - tc_data(i) <= vendor_values2((load_ctr - 258) * 8 + i); - end loop; - tc_data(8) <= '0'; - - when TERMINATION => - tc_data(7 downto 0) <= x"ff"; - tc_data(8) <= '1'; - - when others => - tc_data(7 downto 0) <= x"00"; - tc_data(8) <= '0'; - - end case; - - TC_DATA_OUT <= tc_data; - - end if; -end process; - -PS_RESPONSE_SYNC : process(CLK) -begin - if rising_edge(CLK) then - if (construct_current_state = IDLE or construct_current_state = CLEANUP) then - PS_RESPONSE_READY_OUT <= '0'; - else - PS_RESPONSE_READY_OUT <= '1'; - end if; - - if (construct_current_state = IDLE) then - PS_BUSY_OUT <= '0'; - else - PS_BUSY_OUT <= '1'; - end if; - end if; -end process PS_RESPONSE_SYNC; - --- fixed sizes for discover and request messages -TC_FRAME_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109"; - -TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip - -TC_IDENT_OUT <= x"1" & sent_frames(11 downto 0); - - --- **** statistics ---REC_FRAMES_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- rec_frames <= (others => '0'); --- elsif (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') then --- rec_frames <= rec_frames + x"1"; --- end if; --- end if; ---end process REC_FRAMES_PROC; --- --- needed for identification -SENT_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - sent_frames <= (others => '0'); - elsif (construct_current_state = CLEANUP) then - sent_frames <= sent_frames + x"1"; - end if; - end if; -end process SENT_FRAMES_PROC; --- ---RECEIVED_FRAMES_OUT <= rec_frames; ---SENT_FRAMES_OUT <= sent_frames; --- ---STATS_MACHINE_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- stats_current_state <= IDLE; --- else --- stats_current_state <= stats_next_state; --- end if; --- end if; ---end process STATS_MACHINE_PROC; --- ---STATS_MACHINE : process(stats_current_state, STAT_DATA_ACK_IN, PS_DATA_IN, construct_current_state, receive_current_state) ---begin --- --- case (stats_current_state) is --- --- when IDLE => --- if (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') or (construct_current_state = CLEANUP) or (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then --- stats_next_state <= LOAD_SENT; --- else --- stats_next_state <= IDLE; --- end if; --- --- when LOAD_SENT => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= LOAD_RECEIVED; --- else --- stats_next_state <= LOAD_SENT; --- end if; --- --- when LOAD_RECEIVED => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= LOAD_DISCARDED; --- else --- stats_next_state <= LOAD_RECEIVED; --- end if; --- --- when LOAD_DISCARDED => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= CLEANUP; --- else --- stats_next_state <= LOAD_DISCARDED; --- end if; --- --- when CLEANUP => --- stats_next_state <= IDLE; --- --- end case; --- ---end process STATS_MACHINE; --- ---SELECTOR : process(CLK) ---begin --- if rising_edge(CLK) then --- case(stats_current_state) is --- --- when LOAD_SENT => --- stat_data_temp <= x"0101" & sent_frames; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); --- --- when LOAD_RECEIVED => --- stat_data_temp <= x"0102" & rec_frames; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); --- --- when LOAD_DISCARDED => --- stat_data_temp <= x"0103" & discarded_ctr; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8)); --- --- when others => --- stat_data_temp <= (others => '0'); --- STAT_ADDR_OUT <= (others => '0'); --- --- end case; --- end if; --- ---end process SELECTOR; --- ---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); ---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); ---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); ---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); --- ---STAT_SYNC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then --- STAT_DATA_RDY_OUT <= '1'; --- else --- STAT_DATA_RDY_OUT <= '0'; --- end if; --- end if; ---end process STAT_SYNC; --- **** - - --- **** debug ---DEBUG_OUT(3 downto 0) <= state; ---DEBUG_OUT(7 downto 4) <= state2; ---DEBUG_OUT(11 downto 8) <= state3; ---DEBUG_OUT(15 downto 12) <= (others => '0'); ---DEBUG_OUT(31 downto 16) <= discarded_ctr; --- ---DISCARDED_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- discarded_ctr <= (others => '0'); --- elsif (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then --- discarded_ctr <= discarded_ctr + x"1"; --- end if; --- end if; ---end process DISCARDED_CTR_PROC; --- **** - -end trb_net16_gbe_response_constructor_DHCP; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd deleted file mode 100644 index 813efee..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd +++ /dev/null @@ -1,235 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; - ---******** --- Response Constructor which forwards received frame back ceating a loopback --- - -entity trb_net16_gbe_response_constructor_Forward is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - TC_BUSY_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_response_constructor_Forward; - - -architecture trb_net16_gbe_response_constructor_Forward of trb_net16_gbe_response_constructor_Forward is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_response_constructor_Forward : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -type dissect_states is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state: signal is "safe,gray"; - -signal ff_wr_en : std_logic; -signal ff_rd_en : std_logic; -signal resp_bytes_ctr : std_logic_vector(15 downto 0); -signal ff_empty : std_logic; -signal ff_full : std_logic; -signal ff_q : std_logic_vector(8 downto 0); -signal ff_rd_lock : std_logic; - -signal state : std_logic_vector(3 downto 0); -signal rec_frames : std_logic_vector(15 downto 0); -signal sent_frames : std_logic_vector(15 downto 0); - -begin - -DISSECT_MACHINE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - dissect_current_state <= IDLE; - else - dissect_current_state <= dissect_next_state; - end if; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, ff_q, ff_rd_lock, TC_BUSY_IN) -begin - case dissect_current_state is - - when IDLE => - state <= x"1"; - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - dissect_next_state <= SAVE; - else - dissect_next_state <= IDLE; - end if; - - when SAVE => - state <= x"2"; - if (PS_DATA_IN(8) = '1') then - dissect_next_state <= WAIT_FOR_LOAD; - else - dissect_next_state <= SAVE; - end if; - - when WAIT_FOR_LOAD => - state <= x"3"; - if (TC_BUSY_IN = '0') then - dissect_next_state <= LOAD; - else - dissect_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD => - state <= x"4"; - if (ff_q(8) = '1') and (ff_rd_lock = '0') then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= LOAD; - end if; - - when CLEANUP => - state <= x"5"; - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - ---PS_BUSY_OUT <= '1' when ff_wr_en = '1' else '0'; -PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; - -ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0'; - -FF_RD_LOCK_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - ff_rd_lock <= '1'; - elsif (dissect_current_state = LOAD and ff_rd_en = '1') then - ff_rd_lock <= '0'; - else - ff_rd_lock <= '1'; - end if; - end if; -end process FF_RD_LOCK_PROC; - -FRAME_FIFO: fifo_4096x9 -port map( - Data => PS_DATA_IN, - WrClock => CLK, - RdClock => CLK, - WrEn => ff_wr_en, - RdEn => ff_rd_en, - Reset => RESET, - RPReset => RESET, - Q => ff_q, - Empty => ff_empty, - Full => ff_full -); - -ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0'; - -TC_DATA_OUT <= ff_q; - -PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0'; - -TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1"; - -TC_FRAME_TYPE_OUT <= x"0008"; -TC_DEST_MAC_OUT <= x"9a680f201300"; -TC_DEST_IP_OUT <= x"0100a8c0"; -TC_DEST_UDP_OUT <= x"50c3"; -TC_SRC_MAC_OUT <= x"efbeefbe0000"; -TC_SRC_IP_OUT <= x"0b00a8c0"; -TC_SRC_UDP_OUT <= x"50c3"; -TC_IP_PROTOCOL_OUT <= x"11"; - -RESP_BYTES_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (dissect_current_state = IDLE) then - resp_bytes_ctr <= (others => '0'); - elsif (dissect_current_state = SAVE) then - resp_bytes_ctr <= resp_bytes_ctr + x"1"; - end if; - end if; -end process RESP_BYTES_CTR_PROC; - -REC_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - rec_frames <= (others => '0'); - elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - rec_frames <= rec_frames + x"1"; - end if; - end if; -end process REC_FRAMES_PROC; - -SENT_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - sent_frames <= (others => '0'); - elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then - sent_frames <= sent_frames + x"1"; - end if; - end if; -end process SENT_FRAMES_PROC; - -RECEIVED_FRAMES_OUT <= rec_frames; -SENT_FRAMES_OUT <= sent_frames; - --- **** debug -DEBUG_OUT(3 downto 0) <= state; -DEBUG_OUT(4) <= ff_empty; -DEBUG_OUT(7 downto 5) <= "000"; -DEBUG_OUT(8) <= ff_full; -DEBUG_OUT(11 downto 9) <= "000"; -DEBUG_OUT(31 downto 12) <= (others => '0'); --- **** - -end trb_net16_gbe_response_constructor_Forward; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd deleted file mode 100644 index b96eef0..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd +++ /dev/null @@ -1,424 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - ---******** --- Response Constructor which responds to Ping messages --- - -entity trb_net16_gbe_response_constructor_Ping is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_response_constructor_Ping; - - -architecture trb_net16_gbe_response_constructor_Ping of trb_net16_gbe_response_constructor_Ping is - -attribute syn_encoding : string; - -type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state: signal is "onehot"; - -type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP); -signal stats_current_state, stats_next_state : stats_states; -attribute syn_encoding of stats_current_state : signal is "onehot"; - -signal sent_frames : std_logic_vector(15 downto 0); - -signal saved_data : std_logic_vector(447 downto 0); -signal saved_headers : std_logic_vector(63 downto 0); - -signal data_ctr : integer range 1 to 1500; -signal data_length : integer range 1 to 1500; -signal tc_data : std_logic_vector(8 downto 0); - -signal checksum : std_logic_vector(15 downto 0); - -signal checksum_l, checksum_r : std_logic_vector(19 downto 0); -signal checksum_ll, checksum_rr : std_logic_vector(15 downto 0); -signal checksum_lll, checksum_rrr : std_logic_vector(15 downto 0); - -begin - -DISSECT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - dissect_current_state <= IDLE; - elsif rising_edge(CLK) then - dissect_current_state <= dissect_next_state; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_SELECTED_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length) -begin - case dissect_current_state is - - when IDLE => - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - dissect_next_state <= READ_FRAME; - else - dissect_next_state <= IDLE; - end if; - - when READ_FRAME => - if (PS_DATA_IN(8) = '1') then - dissect_next_state <= WAIT_FOR_LOAD; - else - dissect_next_state <= READ_FRAME; - end if; - - when WAIT_FOR_LOAD => - if (PS_SELECTED_IN = '1') then - dissect_next_state <= LOAD_FRAME; - else - dissect_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD_FRAME => - if (data_ctr = data_length + 1) then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= LOAD_FRAME; - end if; - - when CLEANUP => - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - -DATA_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = WAIT_FOR_LOAD) then - data_ctr <= 2; - elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame - data_ctr <= data_ctr + 1; - elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response - data_ctr <= data_ctr + 1; - end if; - end if; -end process DATA_CTR_PROC; - -DATA_LENGTH_PROC: process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - data_length <= 1; - elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then - data_length <= data_ctr; - end if; - end if; -end process DATA_LENGTH_PROC; - -SAVE_VALUES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (dissect_current_state = IDLE) then - saved_headers <= (others => '0'); - saved_data <= (others => '0'); - elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - saved_headers(7 downto 0) <= PS_DATA_IN(7 downto 0); - elsif (dissect_current_state = READ_FRAME) then - if (data_ctr < 9) then -- headers - saved_headers(data_ctr * 8 - 1 downto (data_ctr - 1) * 8) <= PS_DATA_IN(7 downto 0); - elsif (data_ctr > 8) then -- data - saved_data((data_ctr - 8) * 8 - 1 downto (data_ctr - 8 - 1) * 8) <= PS_DATA_IN(7 downto 0); - end if; - elsif (dissect_current_state = LOAD_FRAME) then - saved_headers(7 downto 0) <= x"00"; - saved_headers(23 downto 16) <= checksum(7 downto 0); - saved_headers(31 downto 24) <= checksum(15 downto 8); - end if; - end if; -end process SAVE_VALUES_PROC; - -CS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (dissect_current_state = IDLE) then - checksum_l(19 downto 0) <= (others => '0'); - checksum_r(19 downto 0) <= (others => '0'); - checksum_ll(15 downto 0) <= (others => '0'); - checksum_rr(15 downto 0) <= (others => '0'); - checksum_lll(15 downto 0) <= (others => '0'); - checksum_rrr(15 downto 0) <= (others => '0'); - elsif (dissect_current_state = READ_FRAME and data_ctr > 4) then - if (std_logic_vector(to_unsigned(data_ctr, 1)) = "0") then - checksum_l <= checksum_l + PS_DATA_IN(7 downto 0); - else - checksum_r <= checksum_r + PS_DATA_IN(7 downto 0); - end if; - checksum_ll <= checksum_ll; - checksum_lll <= checksum_lll; - checksum_rr <= checksum_rr; - checksum_rrr <= checksum_rrr; - elsif (dissect_current_state = WAIT_FOR_LOAD) then - checksum_ll <= x"0000" + checksum_l(7 downto 0) + checksum_r(19 downto 8); - checksum_rr <= x"0000" + checksum_r(7 downto 0) + checksum_l(19 downto 8); - checksum_l <= checksum_l; - checksum_lll <= checksum_lll; - checksum_r <= checksum_r; - checksum_rrr <= checksum_rrr; - elsif (dissect_current_state = LOAD_FRAME and data_ctr = 2) then - checksum_lll <= x"0000" + checksum_ll(7 downto 0) + checksum_rr(15 downto 8); - checksum_rrr <= x"0000" + checksum_rr(7 downto 0) + checksum_ll(15 downto 8); - checksum_l <= checksum_l; - checksum_ll <= checksum_ll; - checksum_r <= checksum_r; - checksum_rr <= checksum_rr; - else - checksum_l <= checksum_l; - checksum_ll <= checksum_ll; - checksum_lll <= checksum_lll; - checksum_r <= checksum_r; - checksum_rr <= checksum_rr; - checksum_rrr <= checksum_rrr; - end if; - end if; -end process CS_PROC; -checksum(7 downto 0) <= not (checksum_rrr(7 downto 0) + checksum_lll(15 downto 8)); -checksum(15 downto 8) <= not (checksum_lll(7 downto 0) + checksum_rrr(15 downto 8)); - -TC_DATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - tc_data(8) <= '0'; - - if (dissect_current_state = LOAD_FRAME) then - if (data_ctr < 10) then -- headers - for i in 0 to 7 loop - tc_data(i) <= saved_headers((data_ctr - 2) * 8 + i); - end loop; - else -- data - for i in 0 to 7 loop - tc_data(i) <= saved_data((data_ctr - 8 - 2) * 8 + i); - end loop; - - -- mark the last byte - if (data_ctr = data_length + 1) then - tc_data(8) <= '1'; - end if; - end if; - else - tc_data(7 downto 0) <= (others => '0'); - end if; - - TC_DATA_OUT <= tc_data; - - end if; -end process TC_DATA_PROC; - -PS_RESPONSE_SYNC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then - PS_RESPONSE_READY_OUT <= '1'; - else - PS_RESPONSE_READY_OUT <= '0'; - end if; - - if (dissect_current_state = IDLE) then - PS_BUSY_OUT <= '0'; - else - PS_BUSY_OUT <= '1'; - end if; - end if; -end process PS_RESPONSE_SYNC; - -TC_FRAME_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16)); -TC_FRAME_TYPE_OUT <= x"0008"; -TC_DEST_UDP_OUT <= x"0000"; -- not used -TC_SRC_MAC_OUT <= g_MY_MAC; -TC_SRC_IP_OUT <= g_MY_IP; -TC_SRC_UDP_OUT <= x"0000"; -- not used -TC_IP_PROTOCOL_OUT <= X"01"; -- ICMP -TC_IDENT_OUT <= x"2" & sent_frames(11 downto 0); - -ADDR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = READ_FRAME) then - TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; - TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; - end if; - end if; -end process ADDR_PROC; - --- statistics --- ---REC_FRAMES_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- rec_frames <= (others => '0'); --- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then --- rec_frames <= rec_frames + x"1"; --- end if; --- end if; ---end process REC_FRAMES_PROC; --- --- needed for identification -SENT_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - sent_frames <= (others => '0'); - elsif (dissect_current_state = CLEANUP) then - sent_frames <= sent_frames + x"1"; - end if; - end if; -end process SENT_FRAMES_PROC; --- ---RECEIVED_FRAMES_OUT <= rec_frames; ---SENT_FRAMES_OUT <= sent_frames; ---RECEIVED_FRAMES_OUT <= rec_frames; ---SENT_FRAMES_OUT <= sent_frames; --- ---STATS_MACHINE_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- stats_current_state <= IDLE; --- else --- stats_current_state <= stats_next_state; --- end if; --- end if; ---end process STATS_MACHINE_PROC; --- ---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN, dissect_current_state) ---begin --- --- case (stats_current_state) is --- --- when IDLE => --- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then --- stats_next_state <= LOAD_SENT; --- else --- stats_next_state <= IDLE; --- end if; --- --- when LOAD_SENT => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= LOAD_RECEIVED; --- else --- stats_next_state <= LOAD_SENT; --- end if; --- --- when LOAD_RECEIVED => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= CLEANUP; --- else --- stats_next_state <= LOAD_RECEIVED; --- end if; --- --- when CLEANUP => --- stats_next_state <= IDLE; --- --- end case; --- ---end process STATS_MACHINE; --- ---SELECTOR : process(CLK) ---begin --- if rising_edge(CLK) then --- case(stats_current_state) is --- --- when LOAD_SENT => --- stat_data_temp <= x"0401" & sent_frames; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); --- --- when LOAD_RECEIVED => --- stat_data_temp <= x"0402" & rec_frames; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); --- --- when others => --- stat_data_temp <= (others => '0'); --- STAT_ADDR_OUT <= (others => '0'); --- --- end case; --- end if; ---end process SELECTOR; --- ---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); ---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); ---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); ---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); --- ---STAT_SYNC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then --- STAT_DATA_RDY_OUT <= '1'; --- else --- STAT_DATA_RDY_OUT <= '0'; --- end if; --- end if; ---end process STAT_SYNC; ---STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; - --- **** debug ---DEBUG_OUT(3 downto 0) <= state; ---DEBUG_OUT(4) <= '0'; ---DEBUG_OUT(7 downto 5) <= "000"; ---DEBUG_OUT(8) <= '0'; ---DEBUG_OUT(11 downto 9) <= "000"; ---DEBUG_OUT(31 downto 12) <= (others => '0'); --- **** - -end trb_net16_gbe_response_constructor_Ping; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd deleted file mode 100644 index 06c5c84..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd +++ /dev/null @@ -1,820 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - - -entity trb_net16_gbe_response_constructor_SCTRL is -generic ( STAT_ADDRESS_BASE : integer := 0 -); - port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - - -- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - DEBUG_OUT : out std_logic_vector(63 downto 0); - -- END OF INTERFACE - - -- protocol specific ports - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - MAKE_RESET_OUT : out std_logic; - CFG_ADDITIONAL_HDR_IN : in std_logic; - -- end of protocol specific ports - - MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); - - DATA_HIST_OUT : out hist_array - ); -end entity trb_net16_gbe_response_constructor_SCTRL; - -architecture RTL of trb_net16_gbe_response_constructor_SCTRL is - -attribute syn_encoding : string; - ---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP); -type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); ---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_A_WORD, WAIT_ONE, WAIT_TWO, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP); ---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state: signal is "onehot"; - -type stats_states is (IDLE, LOAD_RECEIVED, LOAD_REPLY, CLEANUP); -signal stats_current_state, stats_next_state : stats_states; -attribute syn_encoding of stats_current_state : signal is "onehot"; - -signal saved_target_ip : std_logic_vector(31 downto 0); -signal data_ctr : integer range 0 to 30; - - -signal stat_data_temp : std_logic_vector(31 downto 0); -signal rec_frames : std_logic_vector(15 downto 0); - -signal rx_fifo_q : std_logic_vector(17 downto 0); -signal rx_fifo_qq : std_logic_vector(17 downto 0); -signal rx_fifo_wr, rx_fifo_rd : std_logic; -signal tx_eod, rx_eod : std_logic; - -signal tx_fifo_q : std_logic_vector(8 downto 0); -signal tx_fifo_wr, tx_fifo_rd : std_logic; -signal tx_fifo_reset : std_logic; -signal gsc_reply_read : std_logic; -signal gsc_init_dataready : std_logic; -signal gsc_init_dataready_q : std_logic; - -signal tx_data_ctr : std_logic_vector(15 downto 0); -signal tx_loaded_ctr : std_logic_vector(15 downto 0); -signal tx_frame_loaded : std_logic_vector(15 downto 0); - -signal packet_num : std_logic_vector(2 downto 0); - -signal init_ctr, reply_ctr : std_logic_vector(15 downto 0); -signal rx_empty, tx_empty : std_logic; - -signal rx_full, tx_full : std_logic; - -signal size_left : std_logic_vector(15 downto 0); - -signal reset_detected : std_logic := '0'; -signal make_reset : std_logic := '0'; - - -signal fifo_rd_q : std_logic; - -signal too_much_data : std_logic; - -signal rx_fifo_data : std_logic_vector(8 downto 0); -signal tx_fifo_data : std_logic_vector(17 downto 0); - -signal tc_wr : std_logic; -signal state : std_logic_vector(3 downto 0); -signal saved_hdr_1 : std_logic_vector(7 downto 0) := x"ab"; -signal saved_hdr_2 : std_logic_vector(7 downto 0) := x"cd"; -signal saved_hdr_ctr : std_logic_vector(3 downto 0); - -signal mon_rec_frames, mon_rec_bytes, mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0); - -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true; -attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true; - -signal hist_inst : hist_array; -signal reset_all_hist : std_logic_vector(31 downto 0); - -begin - -MAKE_RESET_OUT <= make_reset; - -receive_fifo : fifo_2048x8x16 - PORT map( - Reset => RESET, - RPReset => RESET, - WrClock => CLK, - RdClock => CLK, - Data => rx_fifo_data, - WrEn => rx_fifo_wr, - RdEn => rx_fifo_rd, - Q => rx_fifo_q, - Full => rx_full, - Empty => rx_empty - ); - ---TODO: change to synchronous -rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or - (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or - (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') - else '0'; -- preload first word - -RX_FIFO_WR_SYNC : process(CLK) -begin - if rising_edge(CLK) then - - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and (saved_hdr_ctr = "0100" or saved_hdr_ctr = "1000")) then - rx_fifo_wr <= '1'; - else - rx_fifo_wr <= '0'; - end if; - - rx_fifo_data <= PS_DATA_IN; - end if; -end process RX_FIFO_WR_SYNC; - -SAVED_HDR_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = IDLE and PS_WR_EN_IN = '0' and PS_ACTIVATE_IN = '0') then - saved_hdr_ctr <= "0001"; - elsif (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr /= "1000") then - saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0'; - else - saved_hdr_ctr <= saved_hdr_ctr; - end if; - end if; -end process SAVED_HDR_CTR_PROC; - -SAVED_HDR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - if (saved_hdr_ctr = "0001") then - saved_hdr_1 <= PS_DATA_IN(7 downto 0); - saved_hdr_2 <= saved_hdr_2; - elsif (saved_hdr_ctr = "0010") then - saved_hdr_2 <= PS_DATA_IN(7 downto 0); - saved_hdr_1 <= saved_hdr_1; - else - saved_hdr_1 <= saved_hdr_1; - saved_hdr_2 <= saved_hdr_2; - end if; - else - saved_hdr_1 <= saved_hdr_1; - saved_hdr_2 <= saved_hdr_2; - end if; - end if; -end process SAVED_HDR_PROC; - ---RX_FIFO_RD_SYNC : process(CLK) ---begin --- if rising_edge(CLK) then --- --- if (dissect_current_state = LOAD_A_WORD) then --- rx_fifo_rd <= '1'; --- else --- rx_fifo_rd <= '0'; --- end if; --- ----- if (dissect_current_state = WAIT_ONE) then ----- gsc_init_dataready <= '1'; ----- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '0') then ----- gsc_init_dataready <= '1'; ----- else ----- gsc_init_dataready <= '0'; ----- end if; --- ----- if (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then -- preload the first byte ----- rx_fifo_rd <= '1'; ----- elsif (dissect_current_state = LOAD_TO_HUB) then ----- rx_fifo_rd <= '1'; ----- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') then ----- rx_fifo_rd <= '1'; ----- else ----- rx_fifo_rd <= '0'; ----- end if; ----- ----- if (dissect_current_state = WAIT_FOR_HUB) then ----- gsc_init_dataready <= '1'; ----- elsif (dissect_current_state = LOAD_TO_HUB and GSC_INIT_READ_IN = '1') then ----- gsc_init_dataready <= '1'; ----- else ----- gsc_init_dataready <= '0'; ----- end if; ----- ----- if (dissect_current_state = WAIT_FOR_HUB) then ----- packet_num <= "100"; ----- elsif (dissect_current_state = LOAD_TO_HUB) then ----- if (gsc_init_dataready = '1' and packet_num = "100") then ----- packet_num <= "000"; ----- elsif (gsc_init_dataready = '1' and packet_num /= "100") then ----- packet_num <= packet_num + "1"; ----- else ----- packet_num <= packet_num; ----- end if; ----- else ----- packet_num <= packet_num; ----- end if; --- --- if (dissect_current_state = READ_FRAME) then --- packet_num <= "011"; --- elsif (dissect_current_state = LOAD_A_WORD) then --- if (packet_num = "100") then --- packet_num <= "000"; --- else --- packet_num <= packet_num + "1"; --- end if; --- else --- packet_num <= packet_num; --- end if; --- --- GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9); --- GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0); --- --- --GSC_INIT_DATAREADY_OUT <= gsc_init_dataready; --- ----- GSC_INIT_PACKET_NUM_OUT <= packet_num; --- --- end if; ---end process RX_FIFO_RD_SYNC; --- ---GSC_INIT_DATAREADY_OUT <= '1' when dissect_current_state = WAIT_FOR_HUB else '0'; - -----TODO: add a register -GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9); -GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0); - ------- TODO: change it to synchronous -GSC_INIT_PACKET_NUM_OUT <= packet_num; -GSC_INIT_DATAREADY_OUT <= gsc_init_dataready; -gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or - (dissect_current_state = WAIT_FOR_HUB) else '0'; - -PACKET_NUM_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = IDLE) then - packet_num <= "100"; - elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100") then - packet_num <= "000"; - elsif (rx_fifo_rd = '1' and packet_num /= "100") then - packet_num <= packet_num + "1"; - end if; - end if; -end process PACKET_NUM_PROC; - ---temporairly changed to a smaller fifo -transmit_fifo : fifo_65536x18x9 --fifo_4kx18x9 --fifo_65536x18x9 - PORT map( - Reset => tx_fifo_reset, - RPReset => tx_fifo_reset, - WrClock => CLK, - RdClock => CLK, - Data => tx_fifo_data, - WrEn => tx_fifo_wr, - RdEn => tx_fifo_rd, - Q => tx_fifo_q, - Full => tx_full, - Empty => tx_empty - ); - -TX_FIFO_WR_SYNC : process(CLK) -begin - if rising_edge(CLK) then - if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then - tx_fifo_wr <= '1'; - elsif (saved_hdr_ctr = "0010") then - tx_fifo_wr <= '1'; - else - tx_fifo_wr <= '0'; - end if; - - if (saved_hdr_ctr = "010") then - tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02"; - else - tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8); - tx_fifo_data(8) <= '0'; - tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0); - tx_fifo_data(17) <= '0'; - end if; - end if; -end process TX_FIFO_WR_SYNC; - ---TX_FIFO_RD_SYNC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and tx_frame_loaded /= g_MAX_FRAME_SIZE) then --- tx_fifo_rd <= '1'; --- else --- tx_fifo_rd <= '0'; --- end if; --- end if; ---end process TX_FIFO_RD_SYNC; -tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0'; - -TX_FIFO_SYNC_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) then - tx_fifo_reset <= '1'; - else - tx_fifo_reset <= '0'; - end if; - end if; -end process TX_FIFO_SYNC_PROC; - -TC_DATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - - TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0); - - --if (tx_loaded_ctr = tx_data_ctr + x"1" or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then - if (tx_loaded_ctr = tx_data_ctr) then - TC_DATA_OUT(8) <= '1'; - else - TC_DATA_OUT(8) <= '0'; - end if; - end if; -end process TC_DATA_PROC; - -GSC_REPLY_READ_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE) then - gsc_reply_read <= '1'; - else - gsc_reply_read <= '0'; - end if; - end if; -end process GSC_REPLY_READ_PROC; -GSC_REPLY_READ_OUT <= gsc_reply_read; - --- counter of data received from TRBNet hub -TX_DATA_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = IDLE) then - tx_data_ctr <= (others => '0'); - elsif (tx_fifo_wr = '1') then - tx_data_ctr <= tx_data_ctr + x"2"; - end if; - end if; -end process TX_DATA_CTR_PROC; - -TOO_MUCH_DATA_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = IDLE) then - too_much_data <= '0'; - elsif (dissect_current_state = SAVE_RESPONSE) and (tx_data_ctr = x"fa00") then - too_much_data <= '1'; - end if; - end if; -end process TOO_MUCH_DATA_PROC; - --- total counter of data transported to frame constructor -TX_LOADED_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (dissect_current_state = IDLE) then - tx_loaded_ctr <= x"0000"; - elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then - tx_loaded_ctr <= tx_loaded_ctr + x"1"; - end if; - end if; -end process TX_LOADED_CTR_PROC; - -PS_RESPONSE_SYNC : process(CLK) -begin - if rising_edge(CLK) then - if (too_much_data = '0') then - if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then - PS_RESPONSE_READY_OUT <= '1'; - else - PS_RESPONSE_READY_OUT <= '0'; - end if; - end if; - - if (dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE) then - PS_BUSY_OUT <= '0'; - else - PS_BUSY_OUT <= '1'; - end if; - end if; -end process PS_RESPONSE_SYNC; - -TC_FRAME_TYPE_OUT <= x"0008"; -TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; -TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; -TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8); -TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0); -TC_SRC_MAC_OUT <= g_MY_MAC; -TC_SRC_IP_OUT <= g_MY_IP; -TC_SRC_UDP_OUT <= x"9065"; --x"a861"; -TC_IP_PROTOCOL_OUT <= x"11"; -TC_IDENT_OUT <= x"3" & reply_ctr(11 downto 0); - -TC_FRAME_SIZE_OUT <= tx_data_ctr; - -DISSECT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - dissect_current_state <= IDLE; - elsif rising_edge(CLK) then --- if (RESET = '1') then --- if (g_SIMULATE = 0) then --- dissect_current_state <= IDLE; --- else --- dissect_current_state <= WAIT_FOR_RESPONSE; --- end if; --- else - dissect_current_state <= dissect_next_state; --- end if; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN) -begin - case dissect_current_state is - - when IDLE => - state <= x"0"; - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - dissect_next_state <= READ_FRAME; - else - dissect_next_state <= IDLE; - end if; - - when READ_FRAME => - state <= x"1"; - if (PS_DATA_IN(8) = '1') then - dissect_next_state <= WAIT_FOR_HUB; - else - dissect_next_state <= READ_FRAME; - end if; - - when WAIT_FOR_HUB => - state <= x"2"; - if (GSC_INIT_READ_IN = '1') then - dissect_next_state <= LOAD_TO_HUB; - else - dissect_next_state <= WAIT_FOR_HUB; - end if; - - when LOAD_TO_HUB => - state <= x"3"; - if (rx_fifo_q(17) = '1') then - if (reset_detected = '1') then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= WAIT_FOR_RESPONSE; - end if; - else - dissect_next_state <= LOAD_TO_HUB; - end if; - - when WAIT_FOR_RESPONSE => - state <= x"4"; - if (GSC_REPLY_DATAREADY_IN = '1') then - dissect_next_state <= SAVE_RESPONSE; - else - dissect_next_state <= WAIT_FOR_RESPONSE; - end if; - - when SAVE_RESPONSE => - state <= x"5"; - if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then - if (too_much_data = '0') then - dissect_next_state <= WAIT_FOR_LOAD; - else - dissect_next_state <= CLEANUP; - end if; - else - dissect_next_state <= SAVE_RESPONSE; - end if; - - when WAIT_FOR_LOAD => - state <= x"6"; - if (PS_SELECTED_IN = '1') then - dissect_next_state <= LOAD_FRAME; - else - dissect_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD_FRAME => - state <= x"7"; - if (tx_loaded_ctr = tx_data_ctr) then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= LOAD_FRAME; - end if; - - when CLEANUP => - state <= x"8"; - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - --- reset request packet detection - RESET_DETECTED_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (dissect_current_state = IDLE) then - reset_detected <= '0'; - elsif (PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100") then - reset_detected <= '1'; - else - reset_detected <= reset_detected; - end if; - end if; - end process RESET_DETECTED_PROC; - - MAKE_RESET_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (dissect_current_state = IDLE) then - make_reset <= '0'; - elsif (dissect_current_state = CLEANUP and reset_detected = '1') then - make_reset <= '1'; - else - make_reset <= make_reset; - end if; - end if; - end process MAKE_RESET_PROC; - - --- monitoring - -hist_ctrs_gen : for i in 0 to 31 generate - - process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - reset_all_hist(i) <= '1'; - elsif (hist_inst(i) = x"ffff_ffff") then - reset_all_hist(i) <= '1'; - else - reset_all_hist(i) <= '0'; - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if (reset_all_hist /= x"0000_0000") then - hist_inst(i) <= (others => '0'); - elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr and i = to_integer(unsigned(tx_data_ctr(15 downto 11)))) then - hist_inst(i) <= hist_inst(i) + x"1"; - else - hist_inst(i) <= hist_inst(i); - end if; - end if; - end process; - -end generate hist_ctrs_gen; - -DATA_HIST_OUT <= hist_inst; - - -process(CLK) -begin - if rising_edge(CLK) then - DEBUG_OUT(0) <= rx_full; - DEBUG_OUT(1) <= rx_empty; - DEBUG_OUT(2) <= tx_full; - DEBUG_OUT(3) <= tx_empty; - DEBUG_OUT(7 downto 4) <= state; - end if; -end process; - -DEBUG_OUT(63 downto 8) <= (others => '0'); - -process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_rec_frames <= (others => '0'); - elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then - mon_rec_frames <= mon_rec_frames + x"1"; - else - mon_rec_frames <= mon_rec_frames; - end if; - end if; -end process; -MONITOR_SELECT_REC_OUT <= mon_rec_frames; - -process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_rec_bytes <= (others => '0'); - elsif (rx_fifo_wr = '1') then - mon_rec_bytes <= mon_rec_bytes + x"1"; - else - mon_rec_bytes <= mon_rec_bytes; - end if; - end if; -end process; -MONITOR_SELECT_REC_BYTES_OUT <= mon_rec_bytes; - -process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_sent_frames <= (others => '0'); - elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then - mon_sent_frames <= mon_sent_frames + x"1"; - else - mon_sent_frames <= mon_sent_frames; - end if; - end if; -end process; -MONITOR_SELECT_SENT_OUT <= mon_sent_frames; - -process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_sent_bytes <= (others => '0'); - elsif (tx_fifo_rd = '1') then - mon_sent_bytes <= mon_sent_bytes + x"1"; - else - mon_sent_bytes <= mon_sent_bytes; - end if; - end if; -end process; -MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes; - --- statistics ---REC_FRAMES_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- rec_frames <= (others => '0'); --- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then --- rec_frames <= rec_frames + x"1"; --- end if; --- end if; ---end process REC_FRAMES_PROC; --- --- needed for identification -REPLY_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - reply_ctr <= (others => '0'); - elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then - reply_ctr <= reply_ctr + x"1"; - end if; - end if; -end process REPLY_CTR_PROC; --- --- ---STATS_MACHINE_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- stats_current_state <= IDLE; --- else --- stats_current_state <= stats_next_state; --- end if; --- end if; ---end process STATS_MACHINE_PROC; --- ---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state, tx_loaded_ctr, tx_data_ctr) ---begin --- --- case (stats_current_state) is --- --- when IDLE => --- if ((dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr)) then --- stats_next_state <= LOAD_RECEIVED; --- else --- stats_next_state <= IDLE; --- end if; --- --- when LOAD_RECEIVED => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= LOAD_REPLY; --- else --- stats_next_state <= LOAD_RECEIVED; --- end if; --- --- when LOAD_REPLY => --- if (STAT_DATA_ACK_IN = '1') then --- stats_next_state <= CLEANUP; --- else --- stats_next_state <= LOAD_REPLY; --- end if; --- --- when CLEANUP => --- stats_next_state <= IDLE; --- --- end case; --- ---end process STATS_MACHINE; --- ---SELECTOR : process(CLK) ---begin --- if rising_edge(CLK) then --- case(stats_current_state) is --- --- when LOAD_RECEIVED => --- stat_data_temp <= x"0502" & rec_frames; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); --- --- when LOAD_REPLY => --- stat_data_temp <= x"0503" & reply_ctr; --- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); --- --- when others => --- stat_data_temp <= (others => '0'); --- STAT_ADDR_OUT <= (others => '0'); --- --- end case; --- end if; ---end process SELECTOR; --- ---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); ---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); ---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); ---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); --- ---STAT_SYNC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then --- STAT_DATA_RDY_OUT <= '1'; --- else --- STAT_DATA_RDY_OUT <= '0'; --- end if; --- end if; ---end process STAT_SYNC; -----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; --- ----- end of statistics - - -end architecture RTL; diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd deleted file mode 100644 index 3f1cf11..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd +++ /dev/null @@ -1,336 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:10:12 11/18/2011 --- Design Name: --- Module Name: trb_net16_gbe_response_constructor_Stat - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - -entity trb_net16_gbe_response_constructor_Stat is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - - TC_BUSY_IN : in std_logic; - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - - STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0); - STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0); - STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); - STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); - --- debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_response_constructor_Stat; - -architecture Behavioral of trb_net16_gbe_response_constructor_Stat is - -attribute syn_encoding : string; - -type construct_states is (IDLE, WAIT_FOR_LOAD, LOAD_DATA, TERMINATION, CLEANUP); -signal construct_current_state, construct_next_state : construct_states; -attribute syn_encoding of construct_current_state: signal is "safe,gray"; - -signal timer : unsigned(28 downto 0); -signal state : std_logic_vector(3 downto 0); -signal load_ctr : integer range 0 to 255; -signal tc_data : std_logic_vector(8 downto 0); -signal tc_data_t : std_logic_vector(7 downto 0); -signal timer_lock : std_logic; - -signal mem_din : std_logic_vector(31 downto 0); -signal mem_dout, mem_wr_addr : std_logic_vector(7 downto 0); -signal mem_rd_addr : std_logic_vector(9 downto 0); -signal mem_wr_en : std_logic; -signal selected : std_logic_vector(c_MAX_PROTOCOLS downto 0); - -signal pause : integer range 0 to 28; - -signal stat_data_temp : std_logic_vector(31 downto 0); - -begin -pause <= 10 when g_SIMULATE = 1 else 28; - - -mem : statts_mem - PORT map( - WrClock => CLK, - Reset => RESET, - WrClockEn => '1', - WE => mem_wr_en, - WrAddress => mem_wr_addr, - Data => mem_din, - RdClock => CLK, - RdAddress => mem_rd_addr, - Q => mem_dout, - RdClockEn => '1' - ); - -mem_wr_en <= or_all(selected); -STAT_DATA_ACK_OUT <= selected; - -SELECTOR_PROC : process(CLK) - variable found : boolean := false; -begin - if rising_edge(CLK) then - - selected <= (others => '0'); - - if (RESET = '1') then - mem_wr_addr <= (others => '0'); - mem_din <= (others => '0'); - found := false; - else - if (or_all(STAT_DATA_RDY_IN) = '1') then - for i in 0 to c_MAX_PROTOCOLS loop - if (STAT_DATA_RDY_IN(i) = '1') then - mem_wr_addr <= STAT_ADDR_IN((i + 1) * 8 - 1 downto i * 8); - mem_din <= STAT_DATA_IN((i + 1) * 32 - 1 downto i * 32); - selected(i) <= '1'; - found := true; - elsif (i = c_MAX_PROTOCOLS) and (STAT_DATA_RDY_IN(i) = '0') and (found = false) then - found := false; - end if; - end loop; - else - mem_wr_addr <= (others => '0'); - mem_din <= (others => '0'); - found := false; - end if; - end if; - - end if; -end process SELECTOR_PROC; - - - - - -TIMER_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - timer <= (others => '0'); - timer_lock <= '0'; - elsif (timer(pause) = '0') then - timer_lock <= '0'; - timer <= timer + 1; - elsif (timer(pause) = '1') then - timer_lock <= '1'; - timer <= timer + 1; - else - timer <= timer + 1; - end if; - end if; -end process TIMER_PROC; - --- **** MESSAGES CONSTRUCTING PART - -CONSTRUCT_MACHINE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - construct_current_state <= IDLE; - else - if (g_SIMULATE = 1) then - construct_current_state <= IDLE; - else - construct_current_state <= construct_next_state; - end if; - end if; - end if; -end process CONSTRUCT_MACHINE_PROC; - -CONSTRUCT_MACHINE : process(construct_current_state, timer_lock, TC_BUSY_IN, PS_SELECTED_IN, timer, load_ctr) -begin - case construct_current_state is - - when IDLE => - state <= x"1"; - if (timer(pause) = '1' and timer_lock = '0') then - construct_next_state <= WAIT_FOR_LOAD; - else - construct_next_state <= IDLE; - end if; - - when WAIT_FOR_LOAD => - state <= x"4"; - if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then - construct_next_state <= LOAD_DATA; - else - construct_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD_DATA => - state <= x"2"; - if (load_ctr = 255) then - construct_next_state <= TERMINATION; - else - construct_next_state <= LOAD_DATA; - end if; - - when TERMINATION => - state <= x"e"; - construct_next_state <= CLEANUP; - - when CLEANUP => - state <= x"9"; - construct_next_state <= IDLE; - - end case; -end process CONSTRUCT_MACHINE; - -LOAD_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (construct_current_state = IDLE) then - load_ctr <= 1; - elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then - load_ctr <= load_ctr + 1; - end if; - end if; -end process LOAD_CTR_PROC; - -mem_rd_addr <= std_logic_vector(to_unsigned(load_ctr, 10)); - -TC_DATA_PROC : process(construct_current_state, tc_data_t) -begin - - tc_data(8) <= '0'; - - case (construct_current_state) is - - when LOAD_DATA => - for i in 0 to 7 loop - tc_data(i) <= mem_dout(i); - end loop; - - when TERMINATION => - tc_data(7 downto 0) <= x"ff"; - tc_data(8) <= '1'; - - when others => tc_data(7 downto 0) <= x"00"; - - end case; - -end process; - -TC_DATA_SYNC : process(CLK) -begin - if rising_edge(CLK) then - TC_DATA_OUT <= tc_data; - end if; -end process TC_DATA_SYNC; - - ---PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1'; ---PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1'; - -PS_RESPONSE_SYNC : process(CLK) -begin - if rising_edge(CLK) then - if (construct_current_state = IDLE) then - PS_RESPONSE_READY_OUT <= '0'; - else - PS_RESPONSE_READY_OUT <= '1'; - end if; - - if (construct_current_state = IDLE) then - PS_BUSY_OUT <= '0'; - else - PS_BUSY_OUT <= '1'; - end if; - end if; -end process PS_RESPONSE_SYNC; - -TC_FRAME_SIZE_OUT <= x"0100"; -TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip - -TC_DEST_MAC_OUT <= x"ffffffffffff"; -TC_DEST_IP_OUT <= x"ff" & g_MY_IP(23 downto 0); --x"ff00a8c0"; -TC_DEST_UDP_OUT <= x"51c3"; -TC_SRC_MAC_OUT <= g_MY_MAC; -TC_SRC_IP_OUT <= g_MY_IP; -TC_SRC_UDP_OUT <= x"51c3"; -TC_IP_PROTOCOL_OUT <= x"11"; -- udp - -TC_IP_SIZE_OUT <= x"0100"; -TC_UDP_SIZE_OUT <= x"0100"; -TC_FLAGS_OFFSET_OUT <= (others => '0'); - --- **** debug -DEBUG_OUT(3 downto 0) <= state; -DEBUG_OUT(4) <= '0'; -DEBUG_OUT(7 downto 5) <= "000"; -DEBUG_OUT(8) <= '0'; -DEBUG_OUT(11 downto 9) <= "000"; -DEBUG_OUT(31 downto 12) <= (others => '0'); --- **** - -end Behavioral; - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd deleted file mode 100644 index cf8005d..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd +++ /dev/null @@ -1,235 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; - ---******** --- Response Constructor which forwards received frame back ceating a loopback --- - -entity trb_net16_gbe_response_constructor_Test is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - TC_BUSY_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_response_constructor_Test; - - -architecture trb_net16_gbe_response_constructor_Test of trb_net16_gbe_response_constructor_Test is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_response_constructor_Test: architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -type dissect_states is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state: signal is "safe,gray"; - -signal ff_wr_en : std_logic; -signal ff_rd_en : std_logic; -signal resp_bytes_ctr : std_logic_vector(15 downto 0); -signal ff_empty : std_logic; -signal ff_full : std_logic; -signal ff_q : std_logic_vector(8 downto 0); -signal ff_rd_lock : std_logic; - -signal state : std_logic_vector(3 downto 0); -signal rec_frames : std_logic_vector(15 downto 0); -signal sent_frames : std_logic_vector(15 downto 0); - -begin - -DISSECT_MACHINE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - dissect_current_state <= IDLE; - else - dissect_current_state <= dissect_next_state; - end if; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, ff_q, ff_rd_lock, TC_BUSY_IN) -begin - case dissect_current_state is - - when IDLE => - state <= x"1"; - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - dissect_next_state <= SAVE; - else - dissect_next_state <= IDLE; - end if; - - when SAVE => - state <= x"2"; - if (PS_DATA_IN(8) = '1') then - dissect_next_state <= WAIT_FOR_LOAD; - else - dissect_next_state <= SAVE; - end if; - - when WAIT_FOR_LOAD => - state <= x"3"; - if (TC_BUSY_IN = '0') then - dissect_next_state <= LOAD; - else - dissect_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD => - state <= x"4"; - if (ff_q(8) = '1') and (ff_rd_lock = '0') then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= LOAD; - end if; - - when CLEANUP => - state <= x"5"; - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - -PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; - -ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0'; - -FF_RD_LOCK_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - ff_rd_lock <= '1'; - elsif (dissect_current_state = LOAD and ff_rd_en = '1') then - ff_rd_lock <= '0'; - else - ff_rd_lock <= '1'; - end if; - end if; -end process FF_RD_LOCK_PROC; - --- TODO: put a smaller fifo here -FRAME_FIFO: fifo_4096x9 -port map( - Data => PS_DATA_IN, - WrClock => CLK, - RdClock => CLK, - WrEn => ff_wr_en, - RdEn => ff_rd_en, - Reset => RESET, - RPReset => RESET, - Q => ff_q, - Empty => ff_empty, - Full => ff_full -); - -ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0'; - -TC_DATA_OUT <= ff_q; - -PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0'; - -TC_FRAME_SIZE_OUT <= resp_bytes_ctr + x"1"; - -TC_FRAME_TYPE_OUT <= x"aa08"; -TC_DEST_MAC_OUT <= x"9a680f201300"; -TC_DEST_IP_OUT <= x"0100a8c0"; -TC_DEST_UDP_OUT <= x"51c3"; -TC_SRC_MAC_OUT <= x"efbeefbe0000"; -TC_SRC_IP_OUT <= x"0b00a8c0"; -TC_SRC_UDP_OUT <= x"51c3"; -TC_IP_PROTOCOL_OUT <= x"11"; - -RESP_BYTES_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (dissect_current_state = IDLE) then - resp_bytes_ctr <= (others => '0'); - elsif (dissect_current_state = SAVE) then - resp_bytes_ctr <= resp_bytes_ctr + x"1"; - end if; - end if; -end process RESP_BYTES_CTR_PROC; - -REC_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - rec_frames <= (others => '0'); - elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - rec_frames <= rec_frames + x"1"; - end if; - end if; -end process REC_FRAMES_PROC; - -SENT_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - sent_frames <= (others => '0'); - elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then - sent_frames <= sent_frames + x"1"; - end if; - end if; -end process SENT_FRAMES_PROC; - -RECEIVED_FRAMES_OUT <= rec_frames; -SENT_FRAMES_OUT <= sent_frames; - --- **** debug -DEBUG_OUT(3 downto 0) <= state; -DEBUG_OUT(4) <= ff_empty; -DEBUG_OUT(7 downto 5) <= "000"; -DEBUG_OUT(8) <= ff_full; -DEBUG_OUT(11 downto 9) <= "000"; -DEBUG_OUT(31 downto 12) <= (others => '0'); --- **** - -end trb_net16_gbe_response_constructor_Test; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd deleted file mode 100644 index 8a1b618..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd +++ /dev/null @@ -1,160 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; - ---******** --- Response Constructor which recevies data and does nothing except counting incoming packets --- - -entity trb_net16_gbe_response_constructor_Test1 is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - TC_BUSY_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_response_constructor_Test1; - - -architecture trb_net16_gbe_response_constructor_Test1 of trb_net16_gbe_response_constructor_Test1 is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_response_constructor_Forward : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -type dissect_states is (IDLE, SAVE, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state: signal is "safe,gray"; - -signal ff_wr_en : std_logic; -signal ff_rd_en : std_logic; -signal resp_bytes_ctr : std_logic_vector(15 downto 0); -signal ff_empty : std_logic; -signal ff_full : std_logic; -signal ff_q : std_logic_vector(8 downto 0); -signal ff_rd_lock : std_logic; - -signal state : std_logic_vector(3 downto 0); -signal rec_frames : std_logic_vector(15 downto 0); -signal sent_frames : std_logic_vector(15 downto 0); - -begin - -DISSECT_MACHINE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - dissect_current_state <= IDLE; - else - dissect_current_state <= dissect_next_state; - end if; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN) -begin - case dissect_current_state is - - when IDLE => - state <= x"1"; - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - dissect_next_state <= SAVE; - else - dissect_next_state <= IDLE; - end if; - - when SAVE => - state <= x"2"; - if (PS_DATA_IN(8) = '1') then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= SAVE; - end if; - - when CLEANUP => - state <= x"5"; - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - -PS_BUSY_OUT <= '0'; - -TC_DATA_OUT <= (others => '0'); - -PS_RESPONSE_READY_OUT <= '0'; - -TC_FRAME_SIZE_OUT <= (others => '0'); - -TC_FRAME_TYPE_OUT <= x"0008"; -TC_DEST_MAC_OUT <= x"9a680f201300"; -TC_DEST_IP_OUT <= x"0100a8c0"; -TC_DEST_UDP_OUT <= x"50c3"; -TC_SRC_MAC_OUT <= x"efbeefbe0000"; -TC_SRC_IP_OUT <= x"0b00a8c0"; -TC_SRC_UDP_OUT <= x"50c3"; -TC_IP_PROTOCOL_OUT <= x"11"; - -REC_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - rec_frames <= (others => '0'); - elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - rec_frames <= rec_frames + x"1"; - end if; - end if; -end process REC_FRAMES_PROC; - -RECEIVED_FRAMES_OUT <= rec_frames; -SENT_FRAMES_OUT <= (others => '0'); - --- **** debug -DEBUG_OUT(31 downto 0) <= (others => '0'); --- **** - -end trb_net16_gbe_response_constructor_Test1; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd deleted file mode 100644 index 4845606..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd +++ /dev/null @@ -1,163 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; - ---******** --- gets all the data which is not supposed to be received by other protocols --- simply clears the fifo from garbage - -entity trb_net16_gbe_response_constructor_Trash is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_BUSY_IN : in std_logic; - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_response_constructor_Trash; - - -architecture trb_net16_gbe_response_constructor_Trash of trb_net16_gbe_response_constructor_Trash is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_response_constructor_Trash : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; - -type dissect_states is (IDLE, SAVE, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state: signal is "safe,gray"; - -signal state : std_logic_vector(3 downto 0); -signal rec_frames : std_logic_vector(15 downto 0); -signal sent_frames : std_logic_vector(15 downto 0); - -begin - -DISSECT_MACHINE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - dissect_current_state <= IDLE; - else - dissect_current_state <= dissect_next_state; - end if; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN) -begin - case dissect_current_state is - - when IDLE => - state <= x"1"; - if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - dissect_next_state <= SAVE; - else - dissect_next_state <= IDLE; - end if; - - when SAVE => - state <= x"2"; - if (PS_DATA_IN(8) = '1') then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= SAVE; - end if; - - when CLEANUP => - state <= x"5"; - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - -PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; - -TC_DATA_OUT <= '0' & x"ab"; - -PS_RESPONSE_READY_OUT <= '0'; - -TC_FRAME_SIZE_OUT <= (others => '0'); - -TC_FRAME_TYPE_OUT <= (others => '0'); -TC_DEST_MAC_OUT <= (others => '0'); -TC_DEST_IP_OUT <= (others => '0'); -TC_DEST_UDP_OUT <= (others => '0'); -TC_SRC_MAC_OUT <= (others => '0'); -TC_SRC_IP_OUT <= (others => '0'); -TC_SRC_UDP_OUT <= (others => '0'); -TC_IP_PROTOCOL_OUT <= (others => '0'); - -REC_FRAMES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - rec_frames <= (others => '0'); - elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then - rec_frames <= rec_frames + x"1"; - end if; - end if; -end process REC_FRAMES_PROC; - -RECEIVED_FRAMES_OUT <= rec_frames; -SENT_FRAMES_OUT <= (others => '0'); - --- **** debug -DEBUG_OUT(3 downto 0) <= state; -DEBUG_OUT(31 downto 4) <= (others => '0'); --- **** - -end trb_net16_gbe_response_constructor_Trash; - - diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd deleted file mode 100644 index ff7546a..0000000 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd +++ /dev/null @@ -1,600 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - -entity trb_net16_gbe_response_constructor_TrbNetData is -generic ( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0 - ); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - DEBUG_OUT : out std_logic_vector(63 downto 0); --- END OF INTERFACE - - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0); - - DATA_HIST_OUT : out hist_array -); -end trb_net16_gbe_response_constructor_TrbNetData; - - -architecture trb_net16_gbe_response_constructor_TrbNetData of trb_net16_gbe_response_constructor_TrbNetData is - -attribute syn_encoding : string; - -signal ip_cfg_start : std_logic; -signal ip_cfg_bank : std_logic_vector(3 downto 0); -signal ip_cfg_done : std_logic; -signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); -signal ip_cfg_mem_data : std_logic_vector(31 downto 0); -signal ip_cfg_mem_clk : std_logic; - -signal ic_dest_mac, ic_dest_mac_shift : std_logic_vector(47 downto 0); -signal ic_dest_ip, ic_dest_ip_shift : std_logic_vector(31 downto 0); -signal ic_dest_udp, ic_dest_udp_shift : std_logic_vector(15 downto 0); -signal ic_src_mac, ic_src_mac_shift : std_logic_vector(47 downto 0); -signal ic_src_ip, ic_src_ip_shift : std_logic_vector(31 downto 0); -signal ic_src_udp, ic_src_udp_shift : std_logic_vector(15 downto 0); - -signal pc_wr_en : std_logic; -signal pc_data : std_logic_vector(7 downto 0); -signal pc_eoq : std_logic; -signal pc_sos : std_logic; -signal pc_ready : std_logic; -signal pc_sub_size : std_logic_vector(31 downto 0); -signal pc_trig_nr : std_logic_vector(31 downto 0); -signal pc_eos : std_logic; - -signal tc_rd_en : std_logic; -signal tc_data : std_logic_vector(8 downto 0); -signal tc_size : std_logic_vector(15 downto 0); -signal tc_sod : std_logic; -signal pc_trig_type, pc_trig_type_shift : std_logic_vector(3 downto 0); - -type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP); -signal dissect_current_state, dissect_next_state : dissect_states; -attribute syn_encoding of dissect_current_state : signal is "onehot"; - -signal event_bytes : std_logic_vector(15 downto 0); -signal loaded_bytes : std_logic_vector(15 downto 0); -signal sent_packets : std_logic_vector(15 downto 0); - -signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0); -signal ipu_dbg : std_logic_vector(383 downto 0); -signal constr_dbg : std_logic_vector(63 downto 0); - -signal hist_inst : hist_array; -signal tc_sod_flag : std_logic; -signal reset_all_hist : std_logic_vector(31 downto 0); -signal ipu_monitor : std_logic_vector(223 downto 0); - --- JUST FOR DEBUGING PURPOSE -type sim_check_states is (IDLE, SAVE_HDR, GO_OVER_DATA, SAVE_TLR, GET_ONE_MORE, GET_SECOND_MORE, CLEANUP); -signal sim_check_current, sim_check_next : sim_check_states; - -signal hdr, tlr : std_logic_vector(255 downto 0); - - - -begin - - -sim_check_gen : if DO_SIMULATION = 1 generate - - process(RESET, CLK) - begin - if RESET = '1' then - sim_check_current <= IDLE; - elsif rising_edge(CLK) then - sim_check_current <= sim_check_next; - end if; - end process; - - process(sim_check_current, tc_sod, loaded_bytes, tc_size, hdr, tlr, event_bytes) - begin - case (sim_check_current) is - - when IDLE => - if (tc_sod = '1') then - sim_check_next <= SAVE_HDR; - else - sim_check_next <= IDLE; - end if; - - when SAVE_HDR => - if (loaded_bytes = x"001f" + x"0002") then - sim_check_next <= GO_OVER_DATA; - else - sim_check_next <= SAVE_HDR; - end if; - - when GO_OVER_DATA => - if (loaded_bytes = tc_size + x"0001") then - sim_check_next <= SAVE_TLR; - else - sim_check_next <= GO_OVER_DATA; - end if; - - when SAVE_TLR => - if (loaded_bytes = event_bytes) then - sim_check_next <= GET_ONE_MORE; - else - sim_check_next <= SAVE_TLR; - end if; - - when GET_ONE_MORE => - sim_check_next <= GET_SECOND_MORE; - - when GET_SECOND_MORE => - sim_check_next <= CLEANUP; - - when CLEANUP => - - --assert (hdr = tlr) report "--------- >>>> Header Trailer mismatch" severity failure; - - sim_check_next <= IDLE; - - end case; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if (sim_check_current = SAVE_HDR and loaded_bytes > x"0001") then - hdr((to_integer(unsigned(loaded_bytes - x"0002") * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - x"0002")) * 8)) <= tc_data(7 downto 0); - else - hdr <= hdr; - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if (sim_check_current = SAVE_TLR) then - tlr((to_integer(unsigned(loaded_bytes - tc_size - 2) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 2)) * 8)) <= tc_data(7 downto 0); - elsif (sim_check_current = GET_ONE_MORE) then - tlr((to_integer(unsigned(loaded_bytes - tc_size - 1) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 1)) * 8)) <= tc_data(7 downto 0); - elsif (sim_check_current = GET_ONE_MORE) then - tlr((to_integer(unsigned(loaded_bytes - tc_size) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size)) * 8)) <= tc_data(7 downto 0); - else - tlr <= tlr; - end if; - end if; - end process; - - -end generate sim_check_gen; - - - - -THE_IP_CONFIGURATOR: ip_configurator -port map( - CLK => CLK, - RESET => RESET, - -- configuration interface - START_CONFIG_IN => ip_cfg_start, - BANK_SELECT_IN => ip_cfg_bank, - CONFIG_DONE_OUT => ip_cfg_done, - MEM_ADDR_OUT => ip_cfg_mem_addr, - MEM_DATA_IN => ip_cfg_mem_data, - MEM_CLK_OUT => ip_cfg_mem_clk, - -- information for IP cores - DEST_MAC_OUT => ic_dest_mac, - DEST_IP_OUT => ic_dest_ip, - DEST_UDP_OUT => ic_dest_udp, - SRC_MAC_OUT => ic_src_mac, - SRC_IP_OUT => ic_src_ip, - SRC_UDP_OUT => ic_src_udp, - MTU_OUT => open, - -- Debug - DEBUG_OUT => open -); - -MB_IP_CONFIG: slv_mac_memory -port map( - CLK => CLK, - RESET => RESET, - BUSY_IN => '0', - -- Slave bus - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - -- I/O to the backend - MEM_CLK_IN => ip_cfg_mem_clk, - MEM_ADDR_IN => ip_cfg_mem_addr, - MEM_DATA_OUT => ip_cfg_mem_data, - -- Status lines - STAT => open -); - -THE_IPU_INTERFACE: trb_net16_gbe_ipu_interface --ipu2gbe -port map( - CLK_IPU => CLK, - CLK_GBE => CLK, - RESET => RESET, - --Event information coming from CTS - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data from Frontends - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- slow control interface - START_CONFIG_OUT => ip_cfg_start, - BANK_SELECT_OUT => ip_cfg_bank, - CONFIG_DONE_IN => ip_cfg_done, - DATA_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, - DATA_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, - MULT_EVT_ENABLE_IN => CFG_MULT_ENABLE_IN, - MAX_SUBEVENT_SIZE_IN => CFG_MAX_SUB_IN, - MAX_QUEUE_SIZE_IN => CFG_MAX_QUEUE_IN, - MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, - MAX_SINGLE_SUB_SIZE_IN => CFG_MAX_SINGLE_SUB_IN, - READOUT_CTR_IN => CFG_READOUT_CTR_IN, - READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, - -- PacketConstructor interface - PC_WR_EN_OUT => pc_wr_en, - PC_DATA_OUT => pc_data, - PC_READY_IN => pc_ready, - PC_SOS_OUT => pc_sos, - PC_EOS_OUT => pc_eos, - PC_EOQ_OUT => pc_eoq, - PC_SUB_SIZE_OUT => pc_sub_size, - PC_TRIG_NR_OUT => pc_trig_nr, - PC_TRIGGER_TYPE_OUT => pc_trig_type, - MONITOR_OUT => ipu_monitor, - DEBUG_OUT => ipu_dbg -); - -MONITOR_SELECT_DROP_OUT_OUT <= ipu_monitor(31 downto 0); - -PACKET_CONSTRUCTOR : trb_net16_gbe_event_constr -port map( - CLK => CLK, - RESET => RESET, - PC_WR_EN_IN => pc_wr_en, - PC_DATA_IN => pc_data, - PC_READY_OUT => pc_ready, - PC_START_OF_SUB_IN => pc_sos, - PC_END_OF_SUB_IN => pc_eos, - PC_END_OF_QUEUE_IN => pc_eoq, - PC_SUB_SIZE_IN => pc_sub_size, - PC_DECODING_IN => CFG_SUBEVENT_DEC_IN, - PC_EVENT_ID_IN => CFG_SUBEVENT_ID_IN, - PC_TRIG_NR_IN => pc_trig_nr, - PC_TRIGGER_TYPE_IN => pc_trig_type_shift, - PC_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, - PC_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, - TC_RD_EN_IN => tc_rd_en, - TC_DATA_OUT => tc_data, - TC_EVENT_SIZE_OUT => tc_size, - TC_SOD_OUT => tc_sod, - DEBUG_OUT => constr_dbg -); - -tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0'; - -DISSECT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - dissect_current_state <= IDLE; - elsif rising_edge(CLK) then - dissect_current_state <= dissect_next_state; - end if; -end process DISSECT_MACHINE_PROC; - -DISSECT_MACHINE : process(dissect_current_state, tc_sod, event_bytes, loaded_bytes, PS_SELECTED_IN) -begin - case dissect_current_state is - - when IDLE => - if (tc_sod = '1') then - dissect_next_state <= WAIT_FOR_LOAD; - else - dissect_next_state <= IDLE; - end if; - - when WAIT_FOR_LOAD => - if (PS_SELECTED_IN = '1') then - dissect_next_state <= LOAD; - else - dissect_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD => - if (event_bytes = loaded_bytes) then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= LOAD; - end if; - - when CLEANUP => - dissect_next_state <= IDLE; - - end case; -end process DISSECT_MACHINE; - -PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; -PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) or (dissect_current_state = WAIT_FOR_LOAD) else '0'; - -TC_DATA_OUT <= tc_data; - -EVENT_BYTES_PROC : process (clk) is -begin - if rising_edge(clk) then - if dissect_current_state = IDLE and tc_sod = '1' then - event_bytes <= tc_size + x"20"; -- adding termination bytes - else - event_bytes <= event_bytes; - end if; - end if; -end process EVENT_BYTES_PROC; - -LOADED_BYTES_PROC : process (clk) is -begin - if rising_edge(clk) then - if (dissect_current_state = IDLE) then - loaded_bytes <= (others => '0'); - elsif (dissect_current_state = LOAD and TC_RD_EN_IN = '1') then - loaded_bytes <= loaded_bytes + x"1"; - else - loaded_bytes <= loaded_bytes; - end if; - end if; -end process LOADED_BYTES_PROC; - -TC_FRAME_SIZE_OUT <= event_bytes; -TC_FRAME_TYPE_OUT <= x"0008"; - -TC_DEST_MAC_OUT <= ic_dest_mac_shift; --x"c4e870211b00"; --ic_dest_mac; -TC_DEST_IP_OUT <= ic_dest_ip_shift; --x"0300a8c0"; --ic_dest_ip; -TC_DEST_UDP_OUT <= ic_dest_udp_shift; --x"c35c"; --ic_dest_udp; - ---TC_DEST_MAC_OUT <= x"87883c290c00"; --ic_dest_mac; ---TC_DEST_IP_OUT <= x"0188a8c0"; --ic_dest_ip; ---TC_DEST_UDP_OUT <= x"c35b"; --ic_dest_udp; - -process(CLK) -begin - if rising_edge(CLK) then - if (ip_cfg_start = '1') then - ic_dest_mac_shift <= ic_dest_mac; - ic_dest_ip_shift <= ic_dest_ip; - ic_dest_udp_shift <= ic_dest_udp; - pc_trig_type_shift <= pc_trig_type; - else - ic_dest_mac_shift <= ic_dest_mac_shift; - ic_dest_ip_shift <= ic_dest_ip_shift; - ic_dest_udp_shift <= ic_dest_udp_shift; - pc_trig_type_shift <= pc_trig_type_shift; - end if; - end if; -end process; - - - -rx_enable_gen : if (RX_PATH_ENABLE = 1) generate - TC_SRC_MAC_OUT <= g_MY_MAC; - TC_SRC_IP_OUT <= g_MY_IP; -end generate rx_enable_gen; - -rx_disable_gen : if (RX_PATH_ENABLE = 0) generate - TC_SRC_MAC_OUT <= g_MY_MAC; - TC_SRC_IP_OUT <= ic_src_ip; -end generate rx_disable_gen; - ---TC_SRC_MAC_OUT <= x"99883c290c00"; ---TC_SRC_IP_OUT <= x"0288a8c0"; - -TC_SRC_UDP_OUT <= ic_src_udp; -TC_IP_PROTOCOL_OUT <= x"11"; -TC_IDENT_OUT <= x"4" & sent_packets(11 downto 0); - -SENT_PACKETS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - sent_packets <= (others => '0'); - elsif (dissect_current_state = IDLE and tc_sod = '1') then - sent_packets <= sent_packets + x"1"; - end if; - end if; -end process SENT_PACKETS_PROC; - --- monitoring - - -process(CLK) -begin - if rising_edge(CLK) then - if (tc_sod = '1' and tc_sod_flag = '0') then - tc_sod_flag <= '1'; - elsif (tc_sod = '0') then - tc_sod_flag <= '0'; - else - tc_sod_flag <= tc_sod_flag; - end if; - end if; -end process; - -hist_ctrs_gen : for i in 0 to 31 generate - - process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - reset_all_hist(i) <= '1'; - elsif (hist_inst(i) = x"ffff_ffff") then - reset_all_hist(i) <= '1'; - else - reset_all_hist(i) <= '0'; - end if; - end if; - end process; - - HIST_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') or (reset_all_hist /= x"0000_0000") then - hist_inst(i) <= (others => '0'); - elsif (tc_sod = '1' and tc_sod_flag = '0' and i = to_integer(unsigned(event_bytes(15 downto 11)))) then - hist_inst(i) <= hist_inst(i) + x"1"; - else - hist_inst(i) <= hist_inst(i); - end if; - end if; - end process; -end generate hist_ctrs_gen; - -DATA_HIST_OUT <= hist_inst; - -process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_sent_frames <= (others => '0'); - elsif (dissect_current_state = LOAD and event_bytes = loaded_bytes) then - mon_sent_frames <= mon_sent_frames + x"1"; - else - mon_sent_frames <= mon_sent_frames; - end if; - end if; -end process; -MONITOR_SELECT_SENT_OUT <= mon_sent_frames; - -process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_sent_bytes <= (others => '0'); - elsif (tc_rd_en = '1') then - mon_sent_bytes <= mon_sent_bytes + x"1"; - else - mon_sent_bytes <= mon_sent_bytes; - end if; - end if; -end process; - -MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes; - - -MONITOR_SELECT_REC_BYTES_OUT <= (others => '0'); -MONITOR_SELECT_REC_OUT <= (others => '0'); - -DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0); -DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0); - - - -end trb_net16_gbe_response_constructor_TrbNetData; - - diff --git a/gbe2_ecp3/trb_net16_gbe_setup.vhd b/gbe2_ecp3/trb_net16_gbe_setup.vhd deleted file mode 100644 index c9bf2f3..0000000 --- a/gbe2_ecp3/trb_net16_gbe_setup.vhd +++ /dev/null @@ -1,403 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; ---use work.version.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - -entity gbe_setup is -port( - CLK : in std_logic; - RESET : in std_logic; - - -- interface to regio bus - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - BUS_WRITE_EN_IN : in std_logic; - BUS_READ_EN_IN : in std_logic; - BUS_ACK_OUT : out std_logic; - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); - GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); - GBE_USE_GBE_OUT : out std_logic; - GBE_USE_TRBNET_OUT : out std_logic; - GBE_USE_MULTIEVENTS_OUT : out std_logic; - GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); - GBE_READOUT_CTR_VALID_OUT : out std_logic; - GBE_ALLOW_RX_OUT : out std_logic; - GBE_ADDITIONAL_HDR_OUT : out std_logic; - GBE_INSERT_TTYPE_OUT : out std_logic; - GBE_SOFT_RESET_OUT : out std_logic; - - GBE_MAX_SUB_OUT : out std_logic_vector(15 downto 0); - GBE_MAX_QUEUE_OUT : out std_logic_vector(15 downto 0); - GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0); - GBE_MAX_SINGLE_SUB_OUT : out std_logic_vector(15 downto 0); - - MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0); - MONITOR_TX_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_TX_FRAMES_IN : in std_logic_vector(31 downto 0); - MONITOR_TX_PACKETS_IN : in std_logic_vector(31 downto 0); - MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0); - - MONITOR_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_IN : in std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_IN : in hist_array; - SCTRL_HIST_IN : in hist_array -); -end entity; - -architecture gbe_setup of gbe_setup is - -signal reset_values : std_logic; -signal subevent_id : std_logic_vector(31 downto 0); -signal subevent_dec : std_logic_vector(31 downto 0); -signal queue_dec : std_logic_vector(31 downto 0); -signal max_frame : std_logic_vector(15 downto 0); -signal use_gbe : std_logic; -signal use_trbnet : std_logic; -signal use_multievents : std_logic; -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_valid : std_logic; -signal ack : std_logic; -signal ack_q : std_logic; -signal data_out : std_logic_vector(31 downto 0); -signal allow_rx : std_logic; -signal additional_hdr : std_logic; -signal insert_ttype : std_logic; - signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0); - -begin - -OUT_PROC : process(CLK) -begin - if rising_edge(CLK) then - GBE_SUBEVENT_ID_OUT <= subevent_id; - GBE_SUBEVENT_DEC_OUT <= subevent_dec; - GBE_QUEUE_DEC_OUT <= queue_dec; - GBE_MAX_FRAME_OUT <= max_frame; - GBE_USE_GBE_OUT <= use_gbe; - GBE_USE_TRBNET_OUT <= use_trbnet; - GBE_USE_MULTIEVENTS_OUT <= use_multievents; - GBE_READOUT_CTR_OUT <= readout_ctr; - GBE_READOUT_CTR_VALID_OUT <= readout_ctr_valid; - BUS_ACK_OUT <= ack_q; - ack_q <= ack; - BUS_DATA_OUT <= data_out; - GBE_ALLOW_RX_OUT <= '1'; --allow_rx; - GBE_INSERT_TTYPE_OUT <= insert_ttype; - GBE_ADDITIONAL_HDR_OUT <= additional_hdr; - GBE_MAX_SUB_OUT <= max_sub; - GBE_MAX_QUEUE_OUT <= max_queue; - GBE_MAX_SUBS_IN_QUEUE_OUT <= max_subs_in_queue; - GBE_MAX_SINGLE_SUB_OUT <= max_single_sub; - end if; -end process OUT_PROC; - -ACK_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - ack <= '0'; - elsif ((BUS_WRITE_EN_IN = '1') or (BUS_READ_EN_IN = '1')) then - ack <= '1'; - else - ack <= '0'; - end if; - end if; -end process ACK_PROC; - -WRITE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (reset_values = '1') ) then - subevent_id <= x"0000_00cf"; - subevent_dec <= x"0002_0001"; - queue_dec <= x"0003_0062"; - max_frame <= x"0578"; - use_gbe <= '0'; - use_trbnet <= '0'; - use_multievents <= '0'; - reset_values <= '0'; - readout_ctr <= x"00_0000"; - readout_ctr_valid <= '0'; - allow_rx <= '1'; - insert_ttype <= '0'; - additional_hdr <= '1'; - GBE_SOFT_RESET_OUT <= '0'; - max_sub <= x"e998"; -- 59800 - max_queue <= x"ea60"; -- 60000 - max_subs_in_queue <= x"00c8"; -- 200 - max_single_sub <= x"7d00"; -- 32000 - - elsif (BUS_WRITE_EN_IN = '1') then - - GBE_SOFT_RESET_OUT <= '0'; - - case BUS_ADDR_IN is - - when x"00" => - subevent_id <= BUS_DATA_IN; - - when x"01" => - subevent_dec <= BUS_DATA_IN; - - when x"02" => - queue_dec <= BUS_DATA_IN; - - when x"04" => - max_frame <= BUS_DATA_IN(15 downto 0); - - when x"05" => - if (BUS_DATA_IN = x"0000_0000") then - use_gbe <= '0'; - else - use_gbe <= '1'; - end if; - - when x"06" => - if (BUS_DATA_IN = x"0000_0000") then - use_trbnet <= '0'; - else - use_trbnet <= '1'; - end if; - - when x"07" => - if (BUS_DATA_IN = x"0000_0000") then - use_multievents <= '0'; - else - use_multievents <= '1'; - end if; - - when x"08" => - readout_ctr <= BUS_DATA_IN(23 downto 0); - readout_ctr_valid <= '1'; - - when x"09" => - allow_rx <= BUS_DATA_IN(0); - - when x"0a" => - additional_hdr <= BUS_DATA_IN(0); - - when x"0b" => - insert_ttype <= BUS_DATA_IN(0); - - when x"0c" => - max_sub <= BUS_DATA_IN(15 downto 0); - - when x"10" => - max_queue <= BUS_DATA_IN(15 downto 0); - - when x"0e" => - max_subs_in_queue <= BUS_DATA_IN(15 downto 0); - - when x"0f" => - max_single_sub <= BUS_DATA_IN(15 downto 0); - - - when x"ff" => - if (BUS_DATA_IN = x"ffff_ffff") then - reset_values <= '0'; - GBE_SOFT_RESET_OUT <= '1'; - else - reset_values <= '0'; - GBE_SOFT_RESET_OUT <= '0'; - end if; - - when others => - subevent_id <= subevent_id; - subevent_dec <= subevent_dec; - queue_dec <= queue_dec; - max_frame <= max_frame; - use_gbe <= use_gbe; - use_trbnet <= use_trbnet; - use_multievents <= use_multievents; - reset_values <= reset_values; - readout_ctr <= readout_ctr; - readout_ctr_valid <= readout_ctr_valid; - allow_rx <= allow_rx; - additional_hdr <= additional_hdr; - insert_ttype <= insert_ttype; - max_sub <= max_sub; - max_queue <= max_queue; - max_subs_in_queue <= max_subs_in_queue; - max_single_sub <= max_single_sub; - end case; - else - reset_values <= '0'; - readout_ctr_valid <= '0'; - GBE_SOFT_RESET_OUT <= '0'; - end if; - end if; -end process WRITE_PROC; - -READ_PROC : process(CLK) - variable address : integer range 0 to 255; -begin - if rising_edge(CLK) then - if (RESET = '1') then - data_out <= (others => '0'); - elsif (BUS_READ_EN_IN = '1') then - - address := to_integer(unsigned(BUS_ADDR_IN)); - - case address is - - when 0 => - data_out <= subevent_id; - - when 1 => - data_out <= subevent_dec; - - when 2 => - data_out <= queue_dec; - - when 4 => - data_out(15 downto 0) <= max_frame; - data_out(31 downto 16) <= (others => '0'); - - when 5 => - if (use_gbe = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when 6 => - if (use_trbnet = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when 7 => - if (use_multievents = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when 9 => - data_out(0) <= allow_rx; - data_out(31 downto 1) <= (others => '0'); - - when 10 => - data_out(0) <= additional_hdr; - data_out(31 downto 1) <= (others => '0'); - - when 11 => - data_out(0) <= insert_ttype; - data_out(31 downto 1) <= (others => '0'); - - when 12 => - data_out(15 downto 0) <= max_sub; - data_out(31 downto 16) <= (others => '0'); - - when 14 => - data_out(15 downto 0) <= max_subs_in_queue; - data_out(31 downto 16) <= (others => '0'); - - when 15 => - data_out(15 downto 0) <= max_single_sub; - data_out(31 downto 16) <= (others => '0'); - - when 16 => - data_out(15 downto 0) <= max_queue; - data_out(31 downto 16) <= (others => '0'); - - -- Histogram of sctrl data sizes - when 96 to 127 => - data_out <= SCTRL_HIST_IN(address - 96); - - -- Histogram of TrbNetData data sizes - when 128 to 159 => - data_out <= DATA_HIST_IN(address - 128); - - -- General statistics - when 224 => - data_out <= MONITOR_RX_BYTES_IN; - - when 225 => - data_out <= MONITOR_RX_FRAMES_IN; - - when 226 => - data_out <= MONITOR_TX_BYTES_IN; - - when 227 => - data_out <= MONITOR_TX_FRAMES_IN; - - when 228 => - data_out <= MONITOR_TX_PACKETS_IN; - - when 229 => - data_out <= MONITOR_DROPPED_IN; - - -- Sctrl - when 160 => - data_out <= MONITOR_SELECT_REC_IN(3 * 32 - 1 downto 2 * 32); - when 161 => - data_out <= MONITOR_SELECT_REC_BYTES_IN(3 * 32 - 1 downto 2 * 32); - when 162 => - data_out <= MONITOR_SELECT_SENT_IN(3 * 32 - 1 downto 2 * 32); - when 163 => - data_out <= MONITOR_SELECT_SENT_BYTES_IN(3 * 32 - 1 downto 2 * 32); - when 164 => - data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 - 32 downto 2 * 64); - when 165 => - data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 downto 2 * 64 + 32); - when 166 => - data_out <= MONITOR_SELECT_DROP_IN_IN(3 * 32 - 1 downto 2 * 32); - when 167 => - data_out <= MONITOR_SELECT_DROP_OUT_IN(3 * 32 - 1 downto 2 * 32); - - -- TrbnetData - when 176 => - data_out <= MONITOR_SELECT_REC_IN(4 * 32 - 1 downto 3 * 32); - when 177 => - data_out <= MONITOR_SELECT_REC_BYTES_IN(4 * 32 - 1 downto 3 * 32); - when 178 => - data_out <= MONITOR_SELECT_SENT_IN(4 * 32 - 1 downto 3 * 32); - when 179 => - data_out <= MONITOR_SELECT_SENT_BYTES_IN(4 * 32 - 1 downto 3 * 32); - when 180 => - data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 - 32 downto 3 * 64); - when 181 => - data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 downto 3 * 64 + 32); - when 182 => - data_out <= MONITOR_SELECT_DROP_IN_IN(4 * 32 - 1 downto 3 * 32); - when 183 => - data_out <= MONITOR_SELECT_DROP_OUT_IN(4 * 32 - 1 downto 3 * 32); - - -- for older network monitors - when 243 => - data_out <= MONITOR_TX_BYTES_IN; - - when 244 => - data_out <= MONITOR_TX_FRAMES_IN; - - when others => - data_out <= (others => '0'); - end case; - end if; - end if; -end process READ_PROC; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd b/gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd deleted file mode 100644 index 282b036..0000000 --- a/gbe2_ecp3/trb_net16_gbe_setup_simplified.vhd +++ /dev/null @@ -1,597 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; ---use work.version.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - -entity gbe_setup is -port( - CLK : in std_logic; - RESET : in std_logic; - - -- interface to regio bus - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - - -- gk 26.04.10 - -- input from gbe_buf (only to return the whole trigger number via regio) - GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0); - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); - GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0); - GBE_MIN_PACKET_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); - GBE_USE_GBE_OUT : out std_logic; - GBE_USE_TRBNET_OUT : out std_logic; - GBE_USE_MULTIEVENTS_OUT : out std_logic; - GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10 - GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 - GBE_DELAY_OUT : out std_logic_vector(31 downto 0); - GBE_ALLOW_LARGE_OUT : out std_logic; - GBE_ALLOW_RX_OUT : out std_logic; - GBE_ALLOW_BRDCST_ETH_OUT : out std_logic; - GBE_ALLOW_BRDCST_IP_OUT : out std_logic; - GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10 - GBE_ALLOWED_TYPES_OUT : out std_logic_vector(31 downto 0); - GBE_ALLOWED_IP_OUT : out std_logic_vector(31 downto 0); - GBE_ALLOWED_UDP_OUT : out std_logic_vector(31 downto 0); - GBE_VLAN_ID_OUT : out std_logic_vector(31 downto 0); - -- gk 28.07.10 - MONITOR_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_SENT_IN : in std_logic_vector(31 downto 0); - MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0); - MONITOR_SM_IN : in std_logic_vector(31 downto 0); - MONITOR_LR_IN : in std_logic_vector(31 downto 0); - MONITOR_HDR_IN : in std_logic_vector(31 downto 0); - MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0); - MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0); - MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10 - MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10 - MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0); - MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_RX_BYTES_R_IN : in std_logic_vector(31 downto 0); - -- gk 01.06.10 - DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE3_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE4_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE5_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE6_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE7_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE8_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE9_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE10_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE11_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE12_IN : in std_logic_vector(31 downto 0); - DBG_PC1_IN : in std_logic_vector(31 downto 0); - DBG_PC2_IN : in std_logic_vector(31 downto 0); - DBG_FC1_IN : in std_logic_vector(31 downto 0); - DBG_FC2_IN : in std_logic_vector(31 downto 0); - DBG_FT1_IN : in std_logic_vector(31 downto 0); - DBG_FT2_IN : in std_logic_vector(31 downto 0); - DBG_FR_IN : in std_logic_vector(95 downto 0); - DBG_RC_IN : in std_logic_vector(63 downto 0); - DBG_MC_IN : in std_logic_vector(63 downto 0); - DBG_TC_IN : in std_logic_vector(31 downto 0); - DBG_FIFO_RD_EN_OUT : out std_logic; - - DBG_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); - DBG_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0); - DBG_SELECT_PROTOS_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0) - --DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10 -); -end entity; - -architecture gbe_setup of gbe_setup is - --- attribute HGROUP : string; --- attribute HGROUP of gbe_setup : architecture is "GBE_conf"; - -signal reset_values : std_logic; - -signal subevent_id : std_logic_vector(31 downto 0); -signal subevent_dec : std_logic_vector(31 downto 0); -signal queue_dec : std_logic_vector(31 downto 0); -signal max_packet : std_logic_vector(31 downto 0); -signal min_packet : std_logic_vector(31 downto 0); -- gk 07.20.10 -signal max_frame : std_logic_vector(15 downto 0); -signal use_gbe : std_logic; -signal use_trbnet : std_logic; -signal use_multievents : std_logic; -signal readout_ctr : std_logic_vector(23 downto 0); -- gk 26.04.10 -signal readout_ctr_valid : std_logic; -- gk 26.04.10 -signal ack : std_logic; -- gk 26.04.10 -signal ack_q : std_logic; -- gk 26.04.10 -signal data_out : std_logic_vector(31 downto 0); -- gk 26.04.10 -signal delay : std_logic_vector(31 downto 0); -- gk 28.04.10 -signal allow_large : std_logic; -- gk 21.07.10 -signal reset_fifo : std_logic; -- gk 28.09.10 -signal allow_rx : std_logic; -signal frame_delay : std_logic_vector(31 downto 0); -- gk 09.12.10 -signal allowed_types : std_logic_vector(31 downto 0); -signal allowed_ip : std_logic_vector(31 downto 0); -signal allowed_udp : std_logic_vector(31 downto 0); -signal vlan_id : std_logic_vector(31 downto 0); - -begin - -OUT_PROC : process(CLK) -begin - if rising_edge(CLK) then - GBE_SUBEVENT_ID_OUT <= subevent_id; - GBE_SUBEVENT_DEC_OUT <= subevent_dec; - GBE_QUEUE_DEC_OUT <= queue_dec; - GBE_MAX_PACKET_OUT <= max_packet; - GBE_MIN_PACKET_OUT <= min_packet; - GBE_MAX_FRAME_OUT <= max_frame; - GBE_USE_GBE_OUT <= use_gbe; - GBE_USE_TRBNET_OUT <= use_trbnet; - GBE_USE_MULTIEVENTS_OUT <= use_multievents; - GBE_READOUT_CTR_OUT <= readout_ctr; -- gk 26.04.10 - GBE_READOUT_CTR_VALID_OUT <= readout_ctr_valid; -- gk 26.04.10 - BUS_ACK_OUT <= ack_q; -- gk 26.04.10 - ack_q <= ack; -- gk 26.04.10 - BUS_DATA_OUT <= data_out; -- gk 26.04.10 - GBE_DELAY_OUT <= delay; -- gk 28.04.10 - GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10 - GBE_ALLOW_RX_OUT <= allow_rx; - --DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10 - GBE_FRAME_DELAY_OUT <= frame_delay; -- gk 09.12.10 - GBE_ALLOWED_TYPES_OUT <= allowed_types; - GBE_ALLOWED_IP_OUT <= allowed_ip; - GBE_ALLOWED_UDP_OUT <= allowed_udp; - GBE_VLAN_ID_OUT <= vlan_id; - end if; -end process OUT_PROC; - --- gk 26.04.10 -ACK_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - ack <= '0'; - elsif ((BUS_WRITE_EN_IN = '1') or (BUS_READ_EN_IN = '1')) then - ack <= '1'; - else - ack <= '0'; - end if; - end if; -end process ACK_PROC; - -WRITE_PROC : process(CLK) -begin - DBG_FIFO_RD_EN_OUT <= '0'; - - if rising_edge(CLK) then - if ( (RESET = '1') or (reset_values = '1') ) then - subevent_id <= x"0000_00cf"; - subevent_dec <= x"0002_0001"; - queue_dec <= x"0003_0062"; - max_packet <= x"0000_0fd0"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester - min_packet <= x"0000_0007"; -- gk 20.07.10 - max_frame <= x"0578"; - use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured - use_trbnet <= '0'; - use_multievents <= '0'; - reset_values <= '0'; - readout_ctr <= x"00_0000"; -- gk 26.04.10 -- gk 07.06.10 corrected bug found by Sergey - readout_ctr_valid <= '0'; -- gk 26.04.10 - delay <= x"0000_0000"; -- gk 28.04.10 - DBG_FIFO_RD_EN_OUT <= '0'; - allow_large <= '0'; -- gk 21.07.10 - reset_fifo <= '0'; -- gk 28.09.10 - allow_rx <= '1'; - frame_delay <= x"0000_0000"; -- gk 09.12.10 - allowed_types <= x"0000_00ff"; -- only test protocol allowed - allowed_ip <= x"0000_00ff"; - allowed_udp <= x"0000_00ff"; - vlan_id <= x"0000_0000"; -- no vlan id by default - - elsif (BUS_WRITE_EN_IN = '1') then - case BUS_ADDR_IN is - - when x"00" => - subevent_id <= BUS_DATA_IN; - - when x"01" => - subevent_dec <= BUS_DATA_IN; - - when x"02" => - queue_dec <= BUS_DATA_IN; - - when x"03" => - max_packet <= BUS_DATA_IN; - - when x"04" => - max_frame <= BUS_DATA_IN(15 downto 0); - - when x"05" => - if (BUS_DATA_IN = x"0000_0000") then - use_gbe <= '0'; - else - use_gbe <= '1'; - end if; - - when x"06" => - if (BUS_DATA_IN = x"0000_0000") then - use_trbnet <= '0'; - else - use_trbnet <= '1'; - end if; - - when x"07" => - if (BUS_DATA_IN = x"0000_0000") then - use_multievents <= '0'; - else - use_multievents <= '1'; - end if; - - -- gk 26.04.10 - when x"08" => - readout_ctr <= BUS_DATA_IN(23 downto 0); - readout_ctr_valid <= '1'; - - -- gk 28.04.10 - when x"09" => - delay <= BUS_DATA_IN; - - when x"0a" => - DBG_FIFO_RD_EN_OUT <= '1'; - - -- gk 20.07.10 - when x"0b" => - min_packet <= BUS_DATA_IN; - - -- gk 21.07.10 - when x"0c" => - if (BUS_DATA_IN = x"0000_0000") then - allow_large <= '0'; - else - allow_large <= '1'; - end if; - - -- gk 09.12.10 - when x"0d" => - frame_delay <= BUS_DATA_IN; - - when x"0e" => - allow_rx <= BUS_DATA_IN(0); - - when x"0f" => - allowed_types <= BUS_DATA_IN; - - when x"10" => - vlan_id <= BUS_DATA_IN; - - when x"11" => - allowed_ip <= BUS_DATA_IN; - - when x"12" => - allowed_udp <= BUS_DATA_IN; - - -- gk 28.09.10 - when x"fe" => - if (BUS_DATA_IN = x"ffff_ffff") then - reset_fifo <= '1'; - else - reset_fifo <= '0'; - end if; - - when x"ff" => - if (BUS_DATA_IN = x"ffff_ffff") then - reset_values <= '1'; - else - reset_values <= '0'; - end if; - - when others => - subevent_id <= subevent_id; - subevent_dec <= subevent_dec; - queue_dec <= queue_dec; - max_packet <= max_packet; - min_packet <= min_packet; - max_frame <= max_frame; - use_gbe <= use_gbe; - use_trbnet <= use_trbnet; - use_multievents <= use_multievents; - reset_values <= reset_values; - readout_ctr <= readout_ctr; -- gk 26.04.10 - readout_ctr_valid <= readout_ctr_valid; -- gk 26.04.10 - delay <= delay; -- gk 28.04.10 - DBG_FIFO_RD_EN_OUT <= '0'; - allow_large <= allow_large; - reset_fifo <= reset_fifo; -- gk 28.09.10 - allow_rx <= allow_rx; - frame_delay <= frame_delay; - allowed_types <= allowed_types; - vlan_id <= vlan_id; - allowed_ip <= allowed_ip; - allowed_udp <= allowed_udp; - - end case; - else - reset_values <= '0'; - readout_ctr_valid <= '0'; -- gk 26.04.10 - --reset_fifo <= '0'; -- gk 28.09.10 - end if; - end if; -end process WRITE_PROC; - --- gk 26.04.10 -READ_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - data_out <= (others => '0'); - elsif (BUS_READ_EN_IN = '1') then - case BUS_ADDR_IN is - - when x"00" => - data_out <= subevent_id; - - when x"01" => - data_out <= subevent_dec; - - when x"02" => - data_out <= queue_dec; - - when x"03" => - data_out <= max_packet; - - when x"04" => - data_out(15 downto 0) <= max_frame; - data_out(31 downto 16) <= (others => '0'); - - when x"05" => - if (use_gbe = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when x"06" => - if (use_trbnet = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when x"07" => - if (use_multievents = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when x"08" => - data_out <= GBE_TRIG_NR_IN; - - when x"09" => - data_out <= delay; - - when x"0b" => - data_out <= min_packet; - - -- gk 21.07.10 - when x"0c" => - if (allow_large = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - -- gk 09.12.10 - when x"0d" => - data_out <= frame_delay; - - - when x"0e" => - data_out(0) <= allow_rx; - data_out(31 downto 1) <= (others => '0'); - - when x"0f" => - data_out <= allowed_types; - - when x"10" => - data_out <= vlan_id; - - when x"11" => - data_out <= allowed_ip; - - when x"12" => - data_out <= allowed_udp; - - -- gk 01.06.10 - --when x"e0" => - -- data_out <= DBG_IPU2GBE1_IN; - - --when x"e1" => - -- data_out <= DBG_IPU2GBE2_IN; - - --when x"e2" => - -- data_out <= DBG_PC1_IN; - - --when x"e3" => - -- data_out <= DBG_PC2_IN; - - --when x"e4" => - -- data_out <= DBG_FC1_IN; - - --when x"e5" => - -- data_out <= DBG_FC2_IN; - - --when x"e6" => - -- data_out <= DBG_FT1_IN; - - --when x"e7" => - -- data_out <= DBG_FT2_IN; - - --when x"e8" => - -- data_out(15 downto 0) <= DBG_FIFO_Q_IN; - -- data_out(31 downto 16) <= (others => '0'); - - --when x"e9" => - -- data_out <= DBG_IPU2GBE3_IN; - - --when x"ea" => - -- data_out <= DBG_IPU2GBE4_IN; - - --when x"eb" => - -- data_out <= DBG_IPU2GBE5_IN; - - --when x"ec" => - -- data_out <= DBG_IPU2GBE6_IN; - - --when x"ed" => - -- data_out <= DBG_IPU2GBE7_IN; - - --when x"ee" => - -- data_out <= DBG_IPU2GBE8_IN; - - --when x"ef" => - -- data_out <= DBG_IPU2GBE9_IN; - - --when x"f0" => - -- data_out <= DBG_IPU2GBE10_IN; - - --when x"f1" => - -- data_out <= DBG_IPU2GBE11_IN; - - --when x"f2" => - -- data_out <= DBG_IPU2GBE12_IN; - - --when x"f3" => - -- data_out <= MONITOR_BYTES_IN; - - --when x"f4" => - -- data_out <= MONITOR_SENT_IN; - - --when x"f5" => - -- data_out <= MONITOR_DROPPED_IN; - - --when x"f6" => - -- data_out <= MONITOR_SM_IN; - - --when x"f7" => - -- data_out <= MONITOR_LR_IN; - - --when x"f8" => - -- data_out <= MONITOR_HDR_IN; - - --when x"f9" => - -- data_out <= MONITOR_FIFOS_IN; - - --when x"fa" => - -- data_out <= MONITOR_DISCFRM_IN; - - --when x"fb" => - -- data_out <= MONITOR_LINK_DWN_IN; - - --when x"fc" => - -- data_out <= MONITOR_EMPTY_IN; - - --when x"d1" => - -- data_out <= DBG_FR_IN; - - --when x"d2" => - -- data_out <= DBG_RC_IN; - - --when x"d4" => - -- data_out <= DBG_TC_IN; - - -- **** transmit section - - when x"90" => - data_out <= DBG_FT2_IN; - - -- **** receive debug section - - when x"a0" => - data_out <= DBG_FR_IN(31 downto 0); -- received frames from tsmac | state machine | fifos status - - when x"a1" => - data_out <= DBG_FR_IN(63 downto 32); -- dropped | accepted frames - - when x"a2" => - data_out <= MONITOR_RX_FRAMES_IN; - - when x"a3" => - data_out <= MONITOR_RX_BYTES_IN; - - when x"a4" => - data_out <= MONITOR_RX_BYTES_R_IN; - - when x"a5" => - data_out <= DBG_MC_IN(31 downto 0); - - when x"a6" => - data_out <= g_MY_IP; - - when x"a7" => - data_out <= DBG_FR_IN(95 downto 64); -- ok | error frames - - - -- *** debug of response constructors - - -- ARP - when x"b0" => - data_out(15 downto 0) <= DBG_SELECT_REC_IN(1 * 16 - 1 downto 0 * 16); - data_out(31 downto 16) <= DBG_SELECT_SENT_IN(1 * 16 - 1 downto 0 * 16); - when x"b1" => - data_out <= DBG_SELECT_PROTOS_IN(1 * 32 - 1 downto 0 * 32); - - -- DHCP - when x"b2" => - data_out(15 downto 0) <= DBG_SELECT_REC_IN(2 * 16 - 1 downto 1 * 16); - data_out(31 downto 16) <= DBG_SELECT_SENT_IN(2 * 16 - 1 downto 1 * 16); - when x"b3" => - data_out <= DBG_SELECT_PROTOS_IN(1 * 32 - 1 downto 0 * 32); - - -- PING - when x"b4" => - data_out(15 downto 0) <= DBG_SELECT_REC_IN(3 * 16 - 1 downto 2 * 16); - data_out(31 downto 16) <= DBG_SELECT_SENT_IN(3 * 16 - 1 downto 2 * 16); - when x"b5" => - data_out <= DBG_SELECT_PROTOS_IN(3 * 32 - 1 downto 2 * 32); - - -- Test1a - when x"b6" => - data_out(15 downto 0) <= DBG_SELECT_REC_IN(4 * 16 - 1 downto 3 * 16); - data_out(31 downto 16) <= DBG_SELECT_SENT_IN(4 * 16 - 1 downto 3 * 16); - when x"b7" => - data_out <= DBG_SELECT_PROTOS_IN(4 * 32 - 1 downto 3 * 32); - - -- Test1b - when x"b8" => - data_out(15 downto 0) <= DBG_SELECT_REC_IN(5 * 16 - 1 downto 4 * 16); - data_out(31 downto 16) <= DBG_SELECT_SENT_IN(5 * 16 - 1 downto 4 * 16); - when x"b9" => - data_out <= DBG_SELECT_PROTOS_IN(5 * 32 - 1 downto 4 * 32); - - -- **** end of received debug section - - when others => - data_out <= (others => '0'); - end case; - end if; - end if; -end process READ_PROC; - -end architecture; diff --git a/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd b/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd deleted file mode 100644 index 825ee80..0000000 --- a/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd +++ /dev/null @@ -1,135 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_protocols.all; - ---******** --- doing shit right now - -entity trb_net16_gbe_transmit_control is -port ( - CLK : in std_logic; - RESET : in std_logic; - --- signal to/from main controller - MC_TRANSMIT_CTRL_IN : in std_logic; - MC_DATA_IN : in std_logic_vector(8 downto 0); - MC_WR_EN_IN : in std_logic; - MC_DATA_NOT_VALID_IN : in std_logic; - MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - - MC_DEST_MAC_IN : in std_logic_vector(47 downto 0); - MC_DEST_IP_IN : in std_logic_vector(31 downto 0); - MC_DEST_UDP_IN : in std_logic_vector(15 downto 0); - MC_SRC_MAC_IN : in std_logic_vector(47 downto 0); - MC_SRC_IP_IN : in std_logic_vector(31 downto 0); - MC_SRC_UDP_IN : in std_logic_vector(15 downto 0); - - MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - MC_IDENT_IN : in std_logic_vector(15 downto 0); - - MC_IP_SIZE_IN : in std_logic_vector(15 downto 0); - MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0); - MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); - - MC_FC_H_READY_OUT : out std_logic; - MC_FC_READY_OUT : out std_logic; - MC_FC_WR_EN_IN : in std_logic; - - MC_BUSY_OUT : out std_logic; - MC_TRANSMIT_DONE_OUT : out std_logic; - --- signal to/from frame constructor - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_WR_EN_OUT : out std_logic; - FC_READY_IN : in std_logic; - FC_H_READY_IN : in std_logic; - FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - - DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_transmit_control; - - -architecture trb_net16_gbe_transmit_control of trb_net16_gbe_transmit_control is - -begin - -SYNC_PROC : process(CLK) -begin - if rising_edge(CLK) then - - MC_FC_H_READY_OUT <= FC_H_READY_IN; - MC_FC_READY_OUT <= FC_READY_IN; - - FC_FRAME_TYPE_OUT <= MC_FRAME_TYPE_IN; - - FC_DATA_OUT <= MC_DATA_IN(7 downto 0); - FC_IP_PROTOCOL_OUT <= MC_IP_PROTOCOL_IN; - - if (MC_TRANSMIT_CTRL_IN = '1') then - FC_SOD_OUT <= '1'; - else - FC_SOD_OUT <= '0'; - end if; - - if (MC_DATA_IN(8) = '1') then - FC_EOD_OUT <= '1'; - else - FC_EOD_OUT <= '0'; - end if; - - if (MC_FRAME_TYPE_IN = x"0008") then - FC_IP_SIZE_OUT <= MC_IP_SIZE_IN; - FC_UDP_SIZE_OUT <= MC_UDP_SIZE_IN; - else - FC_IP_SIZE_OUT <= MC_FRAME_SIZE_IN; - FC_UDP_SIZE_OUT <= MC_FRAME_SIZE_IN; - end if; - - - if (MC_DATA_NOT_VALID_IN = '0' and MC_WR_EN_IN = '1') then - FC_WR_EN_OUT <= '1'; - else - FC_WR_EN_OUT <= '0'; - end if; - - FC_FLAGS_OFFSET_OUT <= MC_FLAGS_OFFSET_IN; - - DEST_MAC_ADDRESS_OUT <= MC_DEST_MAC_IN; - DEST_IP_ADDRESS_OUT <= MC_DEST_IP_IN; - DEST_UDP_PORT_OUT <= MC_DEST_UDP_IN; - SRC_MAC_ADDRESS_OUT <= MC_SRC_MAC_IN; - SRC_IP_ADDRESS_OUT <= MC_SRC_IP_IN; - SRC_UDP_PORT_OUT <= MC_SRC_UDP_IN; - - FC_IDENT_OUT <= MC_IDENT_IN; - end if; -end process SYNC_PROC; - -end trb_net16_gbe_transmit_control; - - diff --git a/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd b/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd deleted file mode 100644 index d2a4963..0000000 --- a/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd +++ /dev/null @@ -1,311 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_protocols.all; - ---******** --- performs response constructors readout and splitting into frames - -entity trb_net16_gbe_transmit_control2 is -port ( - CLK : in std_logic; - RESET : in std_logic; - --- signal to/from main controller - TC_DATAREADY_IN : in std_logic; - TC_RD_EN_OUT : out std_logic; - TC_DATA_IN : in std_logic_vector(7 downto 0); - TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - TC_DEST_MAC_IN : in std_logic_vector(47 downto 0); - TC_DEST_IP_IN : in std_logic_vector(31 downto 0); - TC_DEST_UDP_IN : in std_logic_vector(15 downto 0); - TC_SRC_MAC_IN : in std_logic_vector(47 downto 0); - TC_SRC_IP_IN : in std_logic_vector(31 downto 0); - TC_SRC_UDP_IN : in std_logic_vector(15 downto 0); - TC_TRANSMISSION_DONE_OUT : out std_logic; - TC_IDENT_IN : in std_logic_vector(15 downto 0); - TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0); - --- signal to/from frame constructor - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_WR_EN_OUT : out std_logic; - FC_READY_IN : in std_logic; - FC_H_READY_IN : in std_logic; - FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - - DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - - MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0) -); -end trb_net16_gbe_transmit_control2; - - -architecture trb_net16_gbe_transmit_control2 of trb_net16_gbe_transmit_control2 is - -attribute syn_encoding : string; - -type transmit_states is (IDLE, PREPARE_HEADERS, WAIT_FOR_H, TRANSMIT, SEND_ONE, SEND_TWO, CLOSE, WAIT_FOR_TRANS, DIVIDE, CLEANUP); -signal transmit_current_state, transmit_next_state : transmit_states; -attribute syn_encoding of transmit_current_state : signal is "onehot"; - -signal tc_rd, tc_rd_q, tc_rd_qq : std_logic; -signal local_end : std_logic_vector(15 downto 0); - -signal actual_frame_bytes, full_packet_size, ip_size, packet_loaded_bytes : std_logic_vector(15 downto 0); -signal go_to_divide, more_fragments : std_logic; -signal first_frame : std_logic; -signal mon_packets_sent_ctr : std_logic_vector(31 downto 0); - -begin - -TRANSMIT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - transmit_current_state <= IDLE; - elsif rising_edge(CLK) then - transmit_current_state <= transmit_next_state; - end if; -end process TRANSMIT_MACHINE_PROC; - -TRANSMIT_MACHINE : process(transmit_current_state, FC_H_READY_IN, TC_DATAREADY_IN, FC_READY_IN, local_end, TC_MAX_FRAME_IN, actual_frame_bytes, go_to_divide) -begin - case transmit_current_state is - - when IDLE => - if (TC_DATAREADY_IN = '1') then - transmit_next_state <= PREPARE_HEADERS; - else - transmit_next_state <= IDLE; - end if; - - when PREPARE_HEADERS => - transmit_next_state<= WAIT_FOR_H; - - when WAIT_FOR_H => - if (FC_H_READY_IN = '1') then - transmit_next_state <= TRANSMIT; - else - transmit_next_state <= WAIT_FOR_H; - end if; - - when TRANSMIT => - if (local_end = x"0000") then - transmit_next_state <= SEND_ONE; - else - if (actual_frame_bytes = TC_MAX_FRAME_IN - x"1") then - transmit_next_state <= SEND_ONE; - else - transmit_next_state <= TRANSMIT; - end if; - end if; - - when SEND_ONE => - transmit_next_state <= SEND_TWO; - - when SEND_TWO => - transmit_next_state <= CLOSE; - - when CLOSE => - transmit_next_state <= WAIT_FOR_TRANS; - - when WAIT_FOR_TRANS => - if (FC_READY_IN = '1') then - if (go_to_divide = '1') then - transmit_next_state <= DIVIDE; - else - transmit_next_state <= CLEANUP; - end if; - else - transmit_next_state <= WAIT_FOR_TRANS; - end if; - - when DIVIDE => - transmit_next_state <= PREPARE_HEADERS; - - when CLEANUP => - transmit_next_state <= IDLE; - - end case; -end process TRANSMIT_MACHINE; - -tc_rd <= '1' when transmit_current_state = TRANSMIT else '0'; -TC_RD_EN_OUT <= tc_rd; - -SYNC_PROC : process(CLK) -begin - if rising_edge(CLK) then - tc_rd_q <= tc_rd; - tc_rd_qq <= tc_rd_q; - FC_WR_EN_OUT <= tc_rd_qq; - end if; -end process SYNC_PROC; - -ACTUAL_FRAME_BYTES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then - actual_frame_bytes <= (others => '0'); - elsif (transmit_current_state = TRANSMIT) then - actual_frame_bytes <= actual_frame_bytes + x"1"; - else - actual_frame_bytes <= actual_frame_bytes; - end if; - end if; -end process ACTUAL_FRAME_BYTES_PROC; - -GO_TO_DIVIDE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then - go_to_divide <= '0'; - elsif (transmit_current_state = TRANSMIT and actual_frame_bytes = TC_MAX_FRAME_IN - x"1") then - go_to_divide <= '1'; --- elsif (transmit_current_state = SEND_ONE and full_packet_size < packet_loaded_bytes - x"1") then --- go_to_divide <= '1'; --- elsif (transmit_current_state = SEND_TWO and full_packet_size < packet_loaded_bytes - x"1") then --- go_to_divide <= '1'; - elsif (transmit_current_state = SEND_ONE and full_packet_size = packet_loaded_bytes) then - go_to_divide <= '0'; - else - go_to_divide <= go_to_divide; - end if; - end if; -end process GO_TO_DIVIDE_PROC; - -LOCAL_END_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (transmit_current_state = IDLE and TC_DATAREADY_IN = '1') then - local_end <= TC_FRAME_SIZE_IN - x"1"; - full_packet_size <= TC_FRAME_SIZE_IN; - elsif (transmit_current_state = TRANSMIT) then - local_end <= local_end - x"1"; - full_packet_size <= full_packet_size; - else - local_end <= local_end; - full_packet_size <= full_packet_size; - end if; - end if; -end process LOCAL_END_PROC; - -FC_DATA_OUT <= TC_DATA_IN; -FC_SOD_OUT <= '1' when transmit_current_state = WAIT_FOR_H else '0'; -FC_EOD_OUT <= '1' when transmit_current_state = CLOSE else '0'; - -process(CLK) -begin - if rising_edge(CLK) then - if (transmit_current_state = PREPARE_HEADERS) then - if (local_end >= TC_MAX_FRAME_IN) then - ip_size <= TC_MAX_FRAME_IN; - else - ip_size <= local_end + x"1"; - end if; - else - ip_size <= ip_size; - end if; - end if; -end process; -FC_IP_SIZE_OUT <= ip_size; -FC_UDP_SIZE_OUT <= full_packet_size; --TC_FRAME_SIZE_IN; - -FC_FLAGS_OFFSET_OUT(15 downto 14) <= "00"; -FC_FLAGS_OFFSET_OUT(13) <= more_fragments; -MORE_FRAGMENTS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (transmit_current_state = PREPARE_HEADERS) then - if (local_end >= TC_MAX_FRAME_IN) then - more_fragments <= '1'; - else - more_fragments <= '0'; - end if; - else - more_fragments <= more_fragments; - end if; - end if; -end process MORE_FRAGMENTS_PROC; -FC_FLAGS_OFFSET_OUT(12 downto 0) <= ('0' & x"000") when first_frame = '1' else (packet_loaded_bytes(15 downto 3) + x"1"); - -PACKET_LOADED_BYTES_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (transmit_current_state = IDLE) then - packet_loaded_bytes <= x"0000"; - elsif (transmit_current_state = TRANSMIT) then - packet_loaded_bytes <= packet_loaded_bytes + x"1"; --- elsif (transmit_current_state = DIVIDE and first_frame = '1') then --- packet_loaded_bytes <= packet_loaded_bytes + x"8"; -- 8bytes for udp headers added for the first offset - else - packet_loaded_bytes <= packet_loaded_bytes; - end if; - end if; -end process PACKET_LOADED_BYTES_PROC; - -FIRST_FRAME_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (transmit_current_state = IDLE) then - first_frame <= '1'; - elsif (transmit_current_state = DIVIDE) then - first_frame <= '0'; - else - first_frame <= first_frame; - end if; - end if; -end process FIRST_FRAME_PROC; - - -TC_TRANSMISSION_DONE_OUT <= '1' when transmit_current_state = CLEANUP else '0'; - -FC_FRAME_TYPE_OUT <= TC_FRAME_TYPE_IN; -FC_IP_PROTOCOL_OUT <= TC_IP_PROTOCOL_IN; -DEST_MAC_ADDRESS_OUT <= TC_DEST_MAC_IN; -DEST_IP_ADDRESS_OUT <= TC_DEST_IP_IN; -DEST_UDP_PORT_OUT <= TC_DEST_UDP_IN; -SRC_MAC_ADDRESS_OUT <= TC_SRC_MAC_IN; -SRC_IP_ADDRESS_OUT <= TC_SRC_IP_IN; -SRC_UDP_PORT_OUT <= TC_SRC_UDP_IN; -FC_IDENT_OUT <= TC_IDENT_IN; - --- monitoring - -process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_packets_sent_ctr <= (others => '0'); - elsif (transmit_current_state = CLEANUP) then - mon_packets_sent_ctr <= mon_packets_sent_ctr + x"1"; - else - mon_packets_sent_ctr <= mon_packets_sent_ctr; - end if; - end if; -end process; - -MONITOR_TX_PACKETS_OUT <= mon_packets_sent_ctr; - -end trb_net16_gbe_transmit_control2; - - diff --git a/gbe2_ecp3/trb_net16_gbe_type_validator.vhd b/gbe2_ecp3/trb_net16_gbe_type_validator.vhd deleted file mode 100644 index 23bab0d..0000000 --- a/gbe2_ecp3/trb_net16_gbe_type_validator.vhd +++ /dev/null @@ -1,141 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - - ---******** --- contains valid frame types codes and performs checking of type and vlan id --- by default there is place for 32 frame type which is hardcoded value --- due to allow register which is set by slow control - -entity trb_net16_gbe_type_validator is -port ( - CLK : in std_logic; -- 125MHz clock input - RESET : in std_logic; - -- ethernet level - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type - SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id - ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup - VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup - - -- IP level - IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0); - ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); - - -- UDP level - UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); - ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); - - VALID_OUT : out std_logic -); -end trb_net16_gbe_type_validator; - - -architecture trb_net16_gbe_type_validator of trb_net16_gbe_type_validator is - ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_type_validator : architecture is "GBE_MAIN_group"; - -signal result : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0); -signal ip_result : std_logic_vector(c_MAX_IP_PROTOCOLS - 1 downto 0); -signal udp_result : std_logic_vector(c_MAX_UDP_PROTOCOLS - 1 downto 0); -signal partially_valid : std_logic; -- only protocols, vlan to be checked -signal zeros : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0); - -begin - - zeros <= (others => '0'); - --- DO NOT TOUCH -IP_RESULTS_GEN : for i in 0 to c_MAX_IP_PROTOCOLS - 1 generate -process(CLK) -begin - if rising_edge(CLK) then - if IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and ALLOWED_IP_PROTOCOLS_IN(i) = '1' then - ip_result(i) <= '1'; - else - ip_result(i) <= '0'; - end if; - end if; -end process; -end generate IP_RESULTS_GEN; - -UDP_RESULTS_GEN : for i in 0 to c_MAX_UDP_PROTOCOLS - 1 generate -process(CLK) -begin - if rising_edge(CLK) then - if UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and ALLOWED_UDP_PROTOCOLS_IN(i) = '1' then - udp_result(i) <= '1'; - else - udp_result(i) <= '0'; - end if; - end if; -end process; -end generate UDP_RESULTS_GEN; - - -RESULT_GEN : for i in 0 to c_MAX_FRAME_TYPES - 1 generate -process(CLK) -begin - if rising_edge(CLK) then - if FRAME_TYPES(i) = FRAME_TYPE_IN and ALLOWED_TYPES_IN(i) = '1' then - result(i) <= '1'; - else - result(i) <= '0'; - end if; - end if; -end process; -end generate RESULT_GEN; - -PARTIALLY_VALID_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - partially_valid <= '0'; - elsif (FRAME_TYPE_IN = x"0800") then -- ip frame - if (IP_PROTOCOLS_IN = x"11") then -- in case of udp inside ip - partially_valid <= or_all(udp_result); - elsif (IP_PROTOCOLS_IN = x"01" or IP_PROTOCOLS_IN = x"dd" or IP_PROTOCOLS_IN = x"ee") then -- in case of ICMP - partially_valid <= '1'; - else -- do not accept other protocols than udp and icmp inside ip - partially_valid <= '0'; - end if; - elsif (result /= zeros) then-- other frame - partially_valid <= '1'; - else - partially_valid <= '0'; - end if; - end if; -end process PARTIALLY_VALID_PROC; - -VALID_OUT_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (partially_valid = '1') then - if (SAVED_VLAN_ID_IN = x"0000") then - VALID_OUT <= '1'; - elsif (VLAN_ID_IN = x"0000_0000") then - VALID_OUT <= '0'; - elsif (SAVED_VLAN_ID_IN = VLAN_ID_IN(15 downto 0) or SAVED_VLAN_ID_IN = VLAN_ID_IN(31 downto 16)) then - VALID_OUT <= '1'; - else - VALID_OUT <= '0'; - end if; - else - VALID_OUT <= '0'; - end if; - end if; -end process VALID_OUT_PROC; - -end trb_net16_gbe_type_validator; - - diff --git a/gbe2_ecp3/trb_net16_ipu2gbe.vhd b/gbe2_ecp3/trb_net16_ipu2gbe.vhd deleted file mode 100755 index 471956c..0000000 --- a/gbe2_ecp3/trb_net16_ipu2gbe.vhd +++ /dev/null @@ -1,1430 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity trb_net16_ipu2gbe is -port( - CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 - MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - -- PacketConstructor interface - ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; -- gk 07.10.10 - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) -); -end entity; - -architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is - --- attribute HGROUP : string; --- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe"; - -component fifo_32kx16x8_mb2 -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - AlmostEmpty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic -); -end component; - -type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE, RESET_FIFO); -signal saveCurrentState, saveNextState : saveStates; -signal state : std_logic_vector(3 downto 0); -signal data_req_comb : std_logic; -signal data_req : std_logic; -- request data signal, will be used for fee_read generation -signal rst_saved_ctr_comb : std_logic; -signal rst_saved_ctr : std_logic; - -signal fee_read_comb : std_logic; -signal fee_read : std_logic; -- fee_read signal -signal saved_ctr : std_logic_vector(16 downto 0); -signal ce_saved_ctr : std_logic; - --- header data -signal cts_rnd : std_logic_vector(15 downto 0); -signal cts_rnd_saved : std_logic; -signal cts_trg : std_logic_vector(15 downto 0); -signal cts_trg_saved : std_logic; -signal cts_len : std_logic_vector(16 downto 0); -signal cts_len_saved : std_logic; - --- CTS interface -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal cts_length : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_data : std_logic_vector(31 downto 0); - --- Split FIFO signals -signal sf_data : std_logic_vector(15 downto 0); -signal sf_wr_en_comb : std_logic; -signal sf_wr_en : std_logic; -- write signal for FIFO -signal sf_rd_en_comb : std_logic; -signal sf_rd_en : std_logic; -- read signal for FIFO -signal sf_wcnt : std_logic_vector(15 downto 0); -signal sf_rcnt : std_logic_vector(16 downto 0); -signal sf_empty : std_logic; -signal sf_aempty : std_logic; -signal sf_full : std_logic; -signal sf_afull : std_logic; - -------------------------------------------------------------------- -type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2); -signal loadCurrentState, loadNextState : loadStates; -signal state2 : std_logic_vector(3 downto 0); - -signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data -signal rst_rem_ctr_comb : std_logic; -signal rst_rem_ctr : std_logic; -- reset the remove counter -signal rst_regs_comb : std_logic; -signal rst_regs : std_logic; -- reset storage registers -signal rem_phase_comb : std_logic; -signal rem_phase : std_logic; -- header remove phase -signal data_phase_comb : std_logic; -signal data_phase : std_logic; -- data transport phase from split fifo to PC -signal pad_phase_comb : std_logic; -signal pad_phase : std_logic; -- padding phase -signal calc_pad_comb : std_logic; -signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE -signal pad_data_comb : std_logic; -signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value - -signal pc_sos_comb : std_logic; -signal pc_sos : std_logic; -- start of data signal -signal pc_eod_comb : std_logic; -signal pc_eod : std_logic; -- end of data signal - -signal ce_rem_ctr_comb : std_logic; -signal ce_rem_ctr : std_logic; -- count enable for remove counter -signal remove_done_comb : std_logic; -signal remove_done : std_logic; -- end of header stripping process -signal read_done_comb : std_logic; -signal read_done : std_logic; -- end of data phase (read phase from SF) - -signal pc_data : std_logic_vector(7 downto 0); -signal pc_data_q : std_logic_vector(7 downto 0); -signal pc_trig_nr : std_logic_vector(15 downto 0); -signal pc_sub_size : std_logic_vector(17 downto 0); -signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo -signal padding_needed : std_logic; -signal pc_wr_en_comb : std_logic; -signal pc_wr_en_q : std_logic; -signal pc_wr_en_qq : std_logic; -signal pc_wr_en_qqq : std_logic; -signal pc_eod_q : std_logic; - -signal debug : std_logic_vector(383 downto 0); - --- gk -signal bank_select : std_logic_vector(3 downto 0); -signal save_addr_comb : std_logic; -signal save_addr : std_logic; -signal addr_saved_comb : std_logic; -signal addr_saved : std_logic; -signal start_config : std_logic; -signal config_done : std_logic; -signal add_sub_state : std_logic; -signal add_sub_state_comb : std_logic; -signal add_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub : std_logic; -signal load_sub_comb : std_logic; -signal load_sub_done : std_logic; -signal load_sub_done_comb : std_logic; -signal load_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub_ctr_comb : std_logic; -signal actual_message_size : std_logic_vector(31 downto 0); -signal more_subevents : std_logic; -signal trig_random : std_logic_vector(7 downto 0); -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_lock : std_logic; -signal pc_trig_nr_q : std_logic_vector(31 downto 0); - --- gk 20.07.10 -signal inc_data_ctr : std_logic_vector(31 downto 0); -signal dropped_sm_events_ctr : std_logic_vector(31 downto 0); -signal dropped_lr_events_ctr : std_logic_vector(31 downto 0); -signal dropped_ctr : std_logic_vector(31 downto 0); --- gk 22.07.10 -signal headers_invalid : std_logic; -signal headers_invalid_ctr : std_logic_vector(31 downto 0); -signal cts_len_q : std_logic_vector(15 downto 0); -signal cts_trg_q : std_logic_vector(15 downto 0); -signal cts_rnd_q : std_logic_vector(15 downto 0); -signal first_run_trg : std_logic_vector(15 downto 0); -signal first_run_addr : std_logic_vector(15 downto 0); -signal first_run_lock : std_logic; -signal cts_addr : std_logic_vector(15 downto 0); -signal cts_addr_q : std_logic_vector(15 downto 0); -signal cts_addr_saved : std_logic; - --- gk 24.07.10 -signal save_eod : std_logic; -signal save_eod_comb : std_logic; - -signal load_eod : std_logic; -signal endpoint_addr : std_logic_vector(15 downto 0); -signal endp_addr_lock : std_logic; - -signal saved_events_ctr : std_logic_vector(15 downto 0); -signal loaded_events_ctr : std_logic_vector(15 downto 0); -signal constr_events_ctr : std_logic_vector(31 downto 0); -signal event_waiting : std_logic; - -signal drop_sub : std_logic; -signal drop_sub_comb : std_logic; -signal drop_event : std_logic; -signal drop_event_comb : std_logic; -signal drop_small : std_logic; -signal drop_large : std_logic; -signal drop_headers : std_logic; -signal drop_small_comb : std_logic; -signal drop_large_comb : std_logic; -signal drop_headers_comb : std_logic; -signal inc_trg_ctr : std_logic; -signal inc_trg_ctr_comb : std_logic; - -signal invalid_hsize_ctr : std_logic_vector(15 downto 0); -signal invalid_hsize_lock : std_logic; - -signal load_eod_q : std_logic; -signal read_size_q : std_logic_vector(17 downto 0); - --- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked -signal sf_real_wr_en : std_logic; - --- gk 01.10.10 -signal found_empty_evt : std_logic; -signal found_empty_evt_comb : std_logic; -signal found_empty_evt_ctr : std_logic_vector(31 downto 0); - --- gk 06.10.10 -signal message_size : std_logic_vector(31 downto 0); - --- gk 07.12.10 -signal prev_bank_select : std_logic_vector(3 downto 0); -signal first_event : std_logic; - -signal reset_split_fifo : std_logic; - -signal input_data_ctr : std_logic_vector(31 downto 0); - -begin - -BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 -START_CONFIG_OUT <= start_config; -- gk 27.03.10 -config_done <= CONFIG_DONE_IN; -- gk 29.03.10 - --- CTS interface signals -cts_error_pattern <= (others => '0'); -- FAKE - -cts_length <= x"0000"; -- length of data payload is always 0 -cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' - -cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; - -cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) - else '0'; - --- Byte swapping... done here. TAKE CARE! --- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes --- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port. --- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped --- for GbE inside the packet constructor. --- --- Long live the Endianess! - --- Sync all critical pathes -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below - sf_wr_en <= sf_wr_en_comb; - ce_rem_ctr <= ce_rem_ctr_comb; - sf_rd_en <= sf_rd_en_comb; - fee_read <= fee_read_comb; - read_done <= read_done_comb; - pc_eod_q <= pc_eod; - pc_wr_en_qqq <= pc_wr_en_qq; - pc_wr_en_qq <= pc_wr_en_q; - pc_wr_en_q <= pc_wr_en_comb; - end if; -end process THE_SYNC_PROC; - --- gk 27.03.10 data selector for sf to write the evt builder address on top of data -SF_DATA_PROC : process( CLK ) -begin - if( rising_edge(CLK) ) then - if (RESET = '1') then -- gk 31.05.10 - sf_data <= (others => '0'); - elsif( save_addr = '1' ) then - sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address - sf_data(15 downto 4) <= x"abc"; - -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent - elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then - sf_data <= x"0001"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then - sf_data <= x"5555"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then - sf_data <= FEE_STATUS_BITS_IN(31 downto 16); - elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then - sf_data <= FEE_STATUS_BITS_IN(15 downto 0); - else - sf_data <= FEE_DATA_IN; - end if; - end if; -end process SF_DATA_PROC; - --- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY -fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled - else '0'; - --- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY -sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled - (save_addr = '1') or - (add_sub_state = '1') -- gk 29.03.10 save the subsubevent - else '0'; - --- gk 06.08.10 -sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0'; - --- gk 27.03.10 do not count evt builder address as saved ipu bytes ---ce_saved_ctr <= sf_wr_en; -ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en; - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -saveMachineProc: process( CLK ) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saveCurrentState <= SIDLE; - data_req <= '0'; - rst_saved_ctr <= '0'; - save_addr <= '0'; -- gk 27.03.10 - addr_saved <= '0'; -- gk 27.03.10 - add_sub_state <= '0'; -- gk 29.03.10 - save_eod <= '0'; -- gk 25.07.10 - else - saveCurrentState <= saveNextState; - data_req <= data_req_comb; - rst_saved_ctr <= rst_saved_ctr_comb; - save_addr <= save_addr_comb; -- gk 27.03.10 - addr_saved <= addr_saved_comb; -- gk 27.03.10 - add_sub_state <= add_sub_state_comb; -- gk 29.03.10 - save_eod <= save_eod_comb; -- gk 25.07.10 - end if; - end if; -end process saveMachineProc; - -saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, input_data_ctr, MAX_MESSAGE_SIZE_IN) -begin - saveNextState <= SIDLE; - data_req_comb <= '0'; - rst_saved_ctr_comb <= '0'; - save_addr_comb <= '0'; -- gk 27.03.10 - addr_saved_comb <= '0'; -- gk 27.03.10 - add_sub_state_comb <= '0'; -- gk 29.03.10 - save_eod_comb <= '0'; -- gk 25.07.10 - case saveCurrentState is - when SIDLE => - state <= x"0"; - if (CTS_START_READOUT_IN = '1') then - saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10 - data_req_comb <= '1'; - rst_saved_ctr_comb <= '1'; - else - saveNextState <= SIDLE; - end if; - -- gk 27.03.10 - when SAVE_EVT_ADDR => - state <= x"5"; - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - save_addr_comb <= '1'; - when WAIT_FOR_DATA => - state <= x"1"; - if (FEE_BUSY_IN = '1') then - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - else - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - end if; - addr_saved_comb <= '1'; -- gk 27.03.10 - when SAVE_DATA => - state <= x"2"; - if (FEE_BUSY_IN = '0') then - saveNextState <= TERMINATE; - else - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - end if; - when TERMINATE => - state <= x"3"; - if (CTS_READ_IN = '1') then - saveNextState <= SCLOSE; - else - saveNextState <= TERMINATE; - end if; - when SCLOSE => - state <= x"4"; - if (CTS_START_READOUT_IN = '0') then - if (input_data_ctr > MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012 - saveNextState <= RESET_FIFO; - else - saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10 - end if; - else - saveNextState <= SCLOSE; - end if; - -- gk 06.11.2012 - when RESET_FIFO => - saveNextState <= SIDLE; - state <= x"E"; - -- gk 29.03.10 new states during which the subsub bytes are saved - when ADD_SUBSUB1 => - state <= x"6"; - saveNextState <= ADD_SUBSUB2; - add_sub_state_comb <= '1'; - when ADD_SUBSUB2 => - state<= x"7"; - saveNextState <= ADD_SUBSUB3; - add_sub_state_comb <= '1'; - save_eod_comb <= '1'; - when ADD_SUBSUB3 => - state<= x"8"; - saveNextState <= ADD_SUBSUB4; - add_sub_state_comb <= '1'; - when ADD_SUBSUB4 => - state<= x"9"; - saveNextState <= SIDLE; - add_sub_state_comb <= '1'; - when others => - state <= x"f"; - saveNextState <= SIDLE; - end case; -end process saveMachine; - --- gk 06.11.2012 -INPUT_DATA_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1' or rst_saved_ctr = '1') then - input_data_ctr <= (others => '0'); - elsif (saveCurrentState = SAVE_DATA and sf_real_wr_en = '1') then - input_data_ctr(31 downto 1) <= input_data_ctr(31 downto 1) + x"1"; - end if; - end if; -end process INPUT_DATA_CTR_PROC; - --- gk 29.03.10 -ADD_SUB_CTR_PROC : process( CLK ) -begin - if( rising_edge( CLK ) ) then - if( (RESET = '1') or (rst_saved_ctr = '1') ) then - add_sub_ctr <= (others => '0'); - elsif( add_sub_state = '1' ) then - add_sub_ctr <= add_sub_ctr + 1; - end if; - end if; -end process ADD_SUB_CTR_PROC; - ---******** --- SAVE INCOMING EVENT HEADERS ---******** - --- Counter for header word storage -THE_CTS_SAVED_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - saved_ctr <= (others => '0'); - elsif( ce_saved_ctr = '1' ) then - saved_ctr <= saved_ctr + 1; - end if; - end if; -end process THE_CTS_SAVED_CTR; - --- save triggerRnd from incoming data for cts response -CTS_RND_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_rnd <= (others => '0'); - cts_rnd_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then - cts_rnd <= sf_data; - cts_rnd_saved <= '1'; - end if; - end if; -end process CTS_RND_PROC; - --- save triggerNr from incoming data for cts response -CTS_TRG_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_trg <= (others => '0'); - cts_trg_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then - cts_trg <= sf_data; - cts_trg_saved <= '1'; - end if; - end if; -end process CTS_TRG_PROC; - --- save size from incoming data for cts response (future) and to get rid of padding -CTS_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_len <= (others => '0'); - cts_len_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then - cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words - cts_len(0) <= '0'; - elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then - cts_len <= cts_len + x"4"; - cts_len_saved <= '1'; - end if; - end if; -end process CTS_SIZE_PROC; - --- gk 22.07.10 -CTS_ADDR_PROC : process(CLK) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_addr <= (others => '0'); - cts_addr_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then - cts_addr <= sf_data; - cts_addr_saved <= '1'; - end if; - end if; -end process CTS_ADDR_PROC; - ---****** --- SAVE FIRST EVENT HEADER VALUES ---****** - --- gk 22.07.10 -FIRST_RUN_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - first_run_trg <= (others => '0'); - first_run_addr <= (others => '0'); - first_run_lock <= '0'; - elsif (first_run_lock = '0') and (cts_addr_saved = '1') then - first_run_trg <= cts_trg; - first_run_addr <= cts_addr; - first_run_lock <= '1'; - -- important: value saved by saveMachine but incremented by loadMachine - elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then - first_run_trg <= first_run_trg + x"1"; - end if; - end if; -end process FIRST_RUN_PROC; - --- gk 25.07.10 -SAVED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saved_events_ctr <= (others => '0'); - elsif (save_eod = '1') and (input_data_ctr < MAX_MESSAGE_SIZE_IN) then -- gk 06.11.2012 - saved_events_ctr <= saved_events_ctr + x"1"; - end if; - end if; -end process SAVED_EVT_CTR_PROC; - - --- gk 20.07.10 ---INC_DATA_CTR_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') or (rst_saved_ctr = '1') then --- inc_data_ctr <= (others => '0'); --- elsif (sf_wr_en = '1') and (data_req = '1') then --- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1"; --- end if; --- end if; ---end process INC_DATA_CTR_proc; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Split FIFO -THE_SPLIT_FIFO: fifo_32kx16x8_mb2 -port map( - -- Byte swapping for correct byte order on readout side of FIFO - Data(7 downto 0) => sf_data(15 downto 8), - Data(8) => '0', - Data(16 downto 9) => sf_data(7 downto 0), - Data(17) => save_eod, - WrClock => CLK, - RdClock => CLK, - WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en, - RdEn => sf_rd_en, - Reset => reset_split_fifo, --RESET, -- gk 06.11.2012 - RPReset => reset_split_fifo, --RESET, -- gk 06.11.2012 - AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead - AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 - Q(7 downto 0) => pc_data, - Q(8) => load_eod, - WCNT => sf_wcnt, - RCNT => sf_rcnt, - Empty => sf_empty, - AlmostEmpty => sf_aempty, - Full => sf_full, - AlmostFull => sf_afull -); - -reset_split_fifo <= '1' when (saveCurrentState = RESET_FIFO or RESET = '1') else '0'; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- gk 25.07.10 -EVENT_WAITING_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - event_waiting <= '0'; - elsif (loaded_events_ctr /= saved_events_ctr) then - event_waiting <= '1'; - else - event_waiting <= '0'; - end if; - end if; -end process EVENT_WAITING_PROC; - --- write signal for PC data -pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or - (pad_phase = '1') or - ((load_sub = '1') and (sf_rd_en = '1')) or - ((drop_sub = '1') and (sf_rd_en = '1')) or - ((drop_event = '1') and (sf_rd_en = '1')) - else '0'; - -sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or - --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or - ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10 - ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10 - ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or - ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') ) - else '0'; - -ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') ) - else '0'; - --- FIFO data delay process (also forces padding bytes to known value) -THE_DATA_DELAY_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( pad_data = '1' ) then - pc_data_q <= x"aa"; -- padding for 64bit - -- gk 21.07.10 - -- set the error flag if a broken packet is sent - elsif (drop_sub = '1') and (load_sub_ctr = x"3") then - pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0); - else - pc_data_q <= pc_data; - end if; - end if; -end process THE_DATA_DELAY_PROC; - --- Statemachine for reading the data payload from the SPLIT_FIFO and feeding --- it into the packet constructor -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loadCurrentState <= LIDLE; - rst_rem_ctr <= '0'; - rem_phase <= '0'; - calc_pad <= '0'; - data_phase <= '0'; - pad_phase <= '0'; - pc_sos <= '0'; - pc_eod <= '0'; - rst_regs <= '0'; - pad_data <= '0'; - load_sub <= '0'; -- gk 30.03.10 - drop_sub <= '0'; -- gk 25.07.10 - drop_event <= '0'; -- gk 25.07.10 - drop_small <= '0'; -- gk 25.07.10 - drop_large <= '0'; -- gk 25.07.10 - drop_headers <= '0'; -- gk 25.07.10 - inc_trg_ctr <= '0'; -- gk 26.07.10 - found_empty_evt <= '0'; -- gk 01.10.10 - else - loadCurrentState <= loadNextState; - rst_rem_ctr <= rst_rem_ctr_comb; - rem_phase <= rem_phase_comb; - calc_pad <= calc_pad_comb; - data_phase <= data_phase_comb; - pad_phase <= pad_phase_comb; - pc_sos <= pc_sos_comb; - pc_eod <= pc_eod_comb; - rst_regs <= rst_regs_comb; - pad_data <= pad_data_comb; - load_sub <= load_sub_comb; -- gk 30.03.1 - drop_sub <= drop_sub_comb; -- gk 25.07.10 - drop_event <= drop_event_comb; -- gk 25.07.10 - drop_small <= drop_small_comb; -- gk 25.07.10 - drop_large <= drop_large_comb; -- gk 25.07.10 - drop_headers <= drop_headers_comb; -- gk 25.07.10 - inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10 - found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10 - end if; - end if; -end process loadMachineProc; - -loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, - PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, - MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, - first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size, DATA_GBE_ENABLE_IN, first_event, - prev_bank_select, bank_select) -begin - loadNextState <= LIDLE; - rst_rem_ctr_comb <= '0'; - rem_phase_comb <= '0'; - calc_pad_comb <= '0'; - data_phase_comb <= '0'; - pad_phase_comb <= '0'; - pc_sos_comb <= '0'; - pc_eod_comb <= '0'; - rst_regs_comb <= '0'; - pad_data_comb <= '0'; - load_sub_comb <= '0'; -- gk 30.03.10 - drop_sub_comb <= '0'; -- gk 25.07.10 - drop_event_comb <= '0'; -- gk 25.07.10 - drop_small_comb <= '0'; -- gk 25.07.10 - drop_large_comb <= '0'; -- gk 25.07.10 - drop_headers_comb <= '0'; -- gk 25.07.10 - inc_trg_ctr_comb <= '0'; -- gk 26.07.10 - found_empty_evt_comb <= '0'; -- gk 01.10.10 - case loadCurrentState is - when LIDLE => - state2 <= x"0"; - -- gk 23.07.10 - if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 -- and (PC_READY_IN = '1') - loadNextState <= INIT; - rst_rem_ctr_comb <= '1'; - rst_regs_comb <= '1'; - else - loadNextState <= LIDLE; - end if; - when INIT => - state2 <= x"1"; - loadNextState <= REMOVE; - rem_phase_comb <= '1'; - when REMOVE => - state2 <= x"2"; - if( remove_done = '1' ) then - -- gk 06.10.10 - if (MULT_EVT_ENABLE_IN = '1') then - if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then - --loadNextState <= WAIT_TO_REMOVE; - -- gk 07.12.10 - if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet - loadNextState <= WAIT_PC; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - - else - loadNextState <= WAIT_PC; - end if; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - inc_trg_ctr_comb <= '1'; - else - loadNextState <= REMOVE; - rem_phase_comb <= '1'; - end if; - when WAIT_TO_REMOVE => - if (rem_ctr = x"a") then - loadNextState <= DECIDE; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - when DECIDE => - if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_large_comb <= '1'; - elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10 - loadNextState <= CALCA; - found_empty_evt_comb <= '1'; - elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_small_comb <= '1'; - elsif (pc_trig_nr + x"1" /= first_run_trg) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_headers_comb <= '1'; - elsif (endpoint_addr /= first_run_addr) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_headers_comb <= '1'; - else - loadNextState <= CALCA; - end if; - calc_pad_comb <= '1'; - when CALCA => - state2 <= x"3"; - loadNextState <= CALCB; - pc_sos_comb <= '1'; - when CALCB => - -- we need a branch in case of length "0"!!!! - state2 <= x"4"; - loadNextState <= LOAD; - data_phase_comb <= '1'; - when LOAD => - state2 <= x"5"; - if (load_eod = '1') then - loadNextState <= LOAD_SUBSUB; - else - loadNextState <= LOAD; - data_phase_comb <= '1'; - end if; - -- gk 31.03.10 - when LOAD_SUBSUB => - state2 <= x"d"; - if( load_sub_done = '1' ) then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= LOAD_SUBSUB; - load_sub_comb <= '1'; - end if; - when PAD0 => - state2 <= x"6"; - loadNextState <= PAD1; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD1 => - state2 <= x"7"; - loadNextState <= PAD2; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD2 => - state2 <= x"8"; - loadNextState <= PAD3; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD3 => - state2 <= x"9"; - loadNextState <= CALCC; - pad_data_comb <= '1'; - when CALCC => - state2 <= x"a"; - if (MULT_EVT_ENABLE_IN = '1') then - loadNextState <= LIDLE; - else - loadNextState <= CLOSE; - end if; - pc_eod_comb <= '1'; - when CLOSE => - state2 <= x"b"; - loadNextState <= WAIT_PC; - --rst_regs_comb <= '1'; -- gk 07.10.10 - when WAIT_PC => - state2 <= x"c"; - if( PC_READY_IN = '1' ) then - -- gk 06.10.10 - if (MULT_EVT_ENABLE_IN = '1') then - loadNextState <= WAIT_TO_REMOVE; - else - loadNextState <= LIDLE; - end if; - else - loadNextState <= WAIT_PC; - end if; - when PAUSE_BEFORE_DROP1 => - loadNextState <= PAUSE_BEFORE_DROP2; - pc_sos_comb <= '1'; - when PAUSE_BEFORE_DROP2 => - loadNextState <= DROP; - drop_event_comb <= '1'; - -- gk 23.07.10 - when DROP => - state2 <= x"e"; - -- when data is dropped the eod marker stands as its end - if (load_eod = '1') then - loadNextState <= DROP_SUBSUB; - else - loadNextState <= DROP; - drop_event_comb <= '1'; - end if; - -- gk 25.07.10 - when DROP_SUBSUB => - if (load_sub_done = '1') then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= DROP_SUBSUB; - drop_sub_comb <= '1'; - end if; - when others => - state2 <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- gk 07.10.10 -PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0'; - --- gk 25.07.10 ---INVALID_STATS_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- dropped_lr_events_ctr <= (others => '0'); --- dropped_sm_events_ctr <= (others => '0'); --- headers_invalid_ctr <= (others => '0'); --- dropped_ctr <= (others => '0'); --- invalid_hsize_ctr <= (others => '0'); --- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10 --- elsif (rst_regs = '1') then --- invalid_hsize_lock <= '0'; --- elsif (drop_small = '1') then --- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (drop_large = '1') then --- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (drop_headers = '1') then --- headers_invalid_ctr <= headers_invalid_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ?? --- invalid_hsize_ctr <= invalid_hsize_ctr + x"1"; --- invalid_hsize_lock <= '1'; --- -- gk 01.10.10 --- elsif (found_empty_evt = '1') then --- found_empty_evt_ctr <= found_empty_evt_ctr + x"1"; --- end if; --- end if; ---end process INVALID_STATS_PROC; - --- gk 05.08.10 -INVALID_H_PROC : process(CLK) -begin - if rising_edge(CLK) then - load_eod_q <= load_eod; - read_size_q <= read_size; - end if; -end process INVALID_H_PROC; - --- gk 26.04.10 -READOUT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then - readout_ctr <= READOUT_CTR_IN; - readout_ctr_lock <= '0'; - elsif (pc_sos = '1') then - readout_ctr <= readout_ctr + x"1"; - end if; - end if; -end process READOUT_CTR_PROC; - ---****** --- SELECTION OF EVENT BUILDER ---****** - --- gk 27.03.10 -bank_select_proc : process( CLK ) -begin - if rising_edge( CLK ) then - -- gk 29.03.10 - if( (RESET = '1') or (rst_regs = '1') ) then - bank_select <= "0000"; - -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then - bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0); - end if; - end if; -end process bank_select_proc; - --- gk 07.12.10 -first_event_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - first_event <= '1'; - elsif (remove_done = '1') then - first_event <= '0'; - end if; - end if; -end process first_event_proc; - --- gk 07.12.10 -prev_bank_proc : process(CLK) -begin - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - prev_bank_select <= "0000"; - elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then - prev_bank_select <= bank_select; - end if; -end process prev_bank_proc; - - --- gk 29.03.10 -start_config_proc : process( CLK ) -begin - if rising_edge( CLK ) then - if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then - start_config <= '0'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1') ) then -- gk 01.06.10 - start_config <= '1'; - end if; - end if; -end process start_config_proc; - - ---****** --- LOAD SUBSUBEVENT ---****** - --- gk 30.03.10 -load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') ) - else '0'; - --- gk 30.03.10 -LOAD_SUB_CTR_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_ctr <= (others => '0'); - elsif( (load_sub_ctr_comb = '1') ) then - load_sub_ctr <= load_sub_ctr + 1; - end if; - end if; -end process LOAD_SUB_CTR_PROC; - --- gk 30.03.10 --- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or --- ((load_sub_ctr = x"4") and (drop_sub = '1')) --- else '0'; -load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0'; - --- gk 30.03.10 -LOAD_SUB_DONE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_done <= '0'; - else - load_sub_done <= load_sub_done_comb; - end if; - end if; -end process LOAD_SUB_DONE_PROC; - ---****** --- EXTRACT EVENT HEADERS FROM SPLITFIFO ---****** - --- Counter for stripping the unneeded parts of the data stream, and saving the important parts -THE_REMOVE_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - rem_ctr <= (others => '0'); - elsif( (ce_rem_ctr = '1') ) then - rem_ctr <= rem_ctr + 1; - end if; - end if; -end process THE_REMOVE_CTR; - -remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address - -THE_REM_DONE_SYNC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - remove_done <= '0'; - else - remove_done <= remove_done_comb; - end if; - end if; -end process THE_REM_DONE_SYNC; - --- gk 26.04.10 -TRIG_RANDOM_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (rst_regs = '1')) then - trig_random <= (others => '0'); - elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then - trig_random <= pc_data; - end if; - end if; -end process TRIG_RANDOM_PROC; - --- extract the trigger number from splitfifo data -THE_TRG_NR_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_trig_nr <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10 - pc_trig_nr(7 downto 0) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10 - pc_trig_nr(15 downto 8) <= pc_data; - end if; - end if; -end process THE_TRG_NR_PROC; - --- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, --- and in case of padding needed increase it accordingly -THE_SUB_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_sub_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - pc_sub_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - pc_sub_size(17 downto 10) <= pc_data; - -- gk 20.07.10 - -- gk 30.03.10 bug fixed in the way that is written below - -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save - elsif( (calc_pad = '1') and (padding_needed = '1') ) then - pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!! - elsif( (calc_pad = '1') and (padding_needed = '0') ) then - pc_sub_size <= pc_sub_size + x"8"; - end if; - end if; -end process THE_SUB_SIZE_PROC; - --- gk 06.10.10 -MESSAGE_SIZE_PROC : process(CLK) -begin - if rising_edge(CLK) then --- if (RESET = '1') then --- message_size <= (others => '0'); --- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then --- message_size <= (others => '0'); --- elsif (pc_sos = '1') then --- message_size <= message_size + pc_sub_size; --- end if; - if (RESET = '1') then - message_size <= x"0000_0028"; - elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then - message_size <= x"0000_0028"; - elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then - message_size <= x"0000_0028"; - elsif (pc_sos = '1') then - message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers - end if; - end if; -end process MESSAGE_SIZE_PROC; - - --- gk 25.07.10 -ENDP_ADDRESS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_regs = '1') then - endpoint_addr <= (others => '0'); - endp_addr_lock <= '0'; - elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then - endpoint_addr(7 downto 0) <= pc_data; - endp_addr_lock <= '1'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then - endpoint_addr(15 downto 8) <= pc_data; - endp_addr_lock <= '0'; - end if; - end if; -end process ENDP_ADDRESS_PROC; - - - --- check for padding -THE_PADDING_NEEDED_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - padding_needed <= '0'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then - padding_needed <= '1'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then - padding_needed <= '0'; - end if; - end if; -end process THE_PADDING_NEEDED_PROC; - --- number of bytes to read from split fifo -THE_READ_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then - read_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - read_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - read_size(17 downto 10) <= pc_data; - elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then - read_size <= read_size - 1; - -- gk 25.07.10 - elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then - read_size <= read_size - 1; - end if; - end if; -end process THE_READ_SIZE_PROC; - -read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2" - ---****** --- EVENTS COUNTERS ---****** - --- gk 25.07.10 -LOADED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loaded_events_ctr <= (others => '0'); - elsif (remove_done = '1') then - loaded_events_ctr <= loaded_events_ctr + x"1"; - end if; - end if; -end process LOADED_EVT_CTR_PROC; - --- gk 25.07.10 -CONSTR_EVENTS_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - constr_events_ctr <= (others => '0'); - elsif (pc_eod = '1') then - constr_events_ctr <= constr_events_ctr + x"1"; - end if; - end if; -end process CONSTR_EVENTS_CTR_PROC; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Debug signals ---debug(0) <= sf_full; ---debug(1) <= sf_empty; ---debug(2) <= sf_afull; ---debug(3) <= sf_aempty; --- ---debug(7 downto 4) <= state2; --- ---debug(11 downto 8) <= state; --- ---dbg_bs_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(15 downto 12) <= (others => '0'); --- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then --- debug(15 downto 12) <= bank_select; --- end if; --- end if; ---end process dbg_bs_proc; --- ---debug(16) <= config_done; ---debug(17) <= '0'; --remove_done; ---debug(18) <= read_done; ---debug(19) <= padding_needed; --- ---debug(20) <= load_sub_done; --- ---dbg_cts_inf_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(39 downto 32) <= (others => '0'); --- elsif ( save_addr = '1' ) then --- debug(39 downto 32) <= CTS_INFORMATION_IN; --- end if; --- end if; ---end process dbg_cts_inf_proc; --- ---debug(47 downto 40) <= (others => '0'); --- --- ---debug(63 downto 48) <= actual_message_size(15 downto 0); --- ---dbg_pc_sub_size_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(81 downto 64) <= (others => '0'); --- elsif (loadCurrentState = DECIDE) then --- debug(81 downto 64) <= pc_sub_size; --- end if; --- end if; ---end process dbg_pc_sub_size_proc; --- ---dbg_empty_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') or (rst_regs = '1') then --- debug(84 downto 82) <= (others => '0'); --- elsif (read_size = 2) then --- debug(82) <= sf_empty; --- elsif (read_size = 1) then --- debug(83) <= sf_empty; --- elsif (read_size = 0) then --- debug(84) <= sf_empty; --- end if; --- end if; ---end process dbg_empty_proc; --- ---debug(95 downto 85) <= (others => '0'); --- ---dbg_inc_ctr_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(127 downto 96) <= (others => '1'); --- elsif (saveCurrentState = SCLOSE) then --- debug(127 downto 96) <= inc_data_ctr; --- end if; --- end if; ---end process dbg_inc_ctr_proc; --- ---debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0); ---debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0); --- ---debug(175 downto 160) <= headers_invalid_ctr(15 downto 0); ---debug(191 downto 176) <= (others => '0'); --- ---dbg_cts_q_proc : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- cts_len_q <= (others => '0'); --- cts_rnd_q <= (others => '0'); --- cts_trg_q <= (others => '0'); --- cts_addr_q <= (others => '0'); --- elsif (cts_len_saved = '1') then --- cts_len_q <= cts_len(16 downto 1); --- cts_addr_q <= cts_addr; --- cts_rnd_q <= cts_rnd; --- cts_trg_q <= cts_trg; --- end if; --- end if; ---end process dbg_cts_q_proc; - ---debug(207 downto 192) <= cts_trg_q; ---debug(223 downto 208) <= cts_rnd_q; ---debug(239 downto 224) <= cts_addr_q; ---debug(255 downto 240) <= cts_len_q; ---debug(271 downto 256) <= first_run_trg; ---debug(287 downto 272) <= first_run_addr; --- ---debug(303 downto 288) <= saved_events_ctr; ---debug(319 downto 304) <= loaded_events_ctr; --- ---debug(335 downto 320) <= constr_events_ctr(15 downto 0); ---debug(351 downto 336) <= dropped_ctr(15 downto 0); --- ---debug(367 downto 352) <= invalid_hsize_ctr; ---debug(383 downto 368) <= (others => '0'); --- ---MONITOR_OUT(31 downto 0) <= constr_events_ctr; ---MONITOR_OUT(63 downto 32) <= dropped_ctr; ---MONITOR_OUT(95 downto 64) <= headers_invalid_ctr; ---MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr; ---MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr; ---MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000"; ---MONITOR_OUT(191 downto 164) <= (others => '0'); ---MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10 - --- Outputs -FEE_READ_OUT <= fee_read; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; -CTS_DATA_OUT <= cts_data; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_LENGTH_OUT <= cts_length; - -PC_SOS_OUT <= pc_sos; -PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1')) - or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) - -- gk 07.12.10 - or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) - else '0'; -- gk 07.10.10 -PC_DATA_OUT <= pc_data_q; -PC_WR_EN_OUT <= pc_wr_en_qq; - -PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random; - -PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; -PC_PADDING_OUT <= padding_needed; - ---DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_ipu2gbe_20101006.vhd b/gbe2_ecp3/trb_net16_ipu2gbe_20101006.vhd deleted file mode 100644 index 73c8d7a..0000000 --- a/gbe2_ecp3/trb_net16_ipu2gbe_20101006.vhd +++ /dev/null @@ -1,1316 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity trb_net16_ipu2gbe is -port( - CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 - MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - -- PacketConstructor interface - ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) -); -end entity; - -architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe_group"; - -component fifo_32kx16x8_mb2 -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - AlmostEmpty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic -); -end component; - -type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE); -signal saveCurrentState, saveNextState : saveStates; -signal state : std_logic_vector(3 downto 0); -signal data_req_comb : std_logic; -signal data_req : std_logic; -- request data signal, will be used for fee_read generation -signal rst_saved_ctr_comb : std_logic; -signal rst_saved_ctr : std_logic; - -signal fee_read_comb : std_logic; -signal fee_read : std_logic; -- fee_read signal -signal saved_ctr : std_logic_vector(16 downto 0); -signal ce_saved_ctr : std_logic; - --- header data -signal cts_rnd : std_logic_vector(15 downto 0); -signal cts_rnd_saved : std_logic; -signal cts_trg : std_logic_vector(15 downto 0); -signal cts_trg_saved : std_logic; -signal cts_len : std_logic_vector(16 downto 0); -signal cts_len_saved : std_logic; - --- CTS interface -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal cts_length : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_data : std_logic_vector(31 downto 0); - --- Split FIFO signals -signal sf_data : std_logic_vector(15 downto 0); -signal sf_wr_en_comb : std_logic; -signal sf_wr_en : std_logic; -- write signal for FIFO -signal sf_rd_en_comb : std_logic; -signal sf_rd_en : std_logic; -- read signal for FIFO -signal sf_wcnt : std_logic_vector(15 downto 0); -signal sf_rcnt : std_logic_vector(16 downto 0); -signal sf_empty : std_logic; -signal sf_aempty : std_logic; -signal sf_full : std_logic; -signal sf_afull : std_logic; - -------------------------------------------------------------------- -type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2); -signal loadCurrentState, loadNextState : loadStates; -signal state2 : std_logic_vector(3 downto 0); - -signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data -signal rst_rem_ctr_comb : std_logic; -signal rst_rem_ctr : std_logic; -- reset the remove counter -signal rst_regs_comb : std_logic; -signal rst_regs : std_logic; -- reset storage registers -signal rem_phase_comb : std_logic; -signal rem_phase : std_logic; -- header remove phase -signal data_phase_comb : std_logic; -signal data_phase : std_logic; -- data transport phase from split fifo to PC -signal pad_phase_comb : std_logic; -signal pad_phase : std_logic; -- padding phase -signal calc_pad_comb : std_logic; -signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE -signal pad_data_comb : std_logic; -signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value - -signal pc_sos_comb : std_logic; -signal pc_sos : std_logic; -- start of data signal -signal pc_eod_comb : std_logic; -signal pc_eod : std_logic; -- end of data signal - -signal ce_rem_ctr_comb : std_logic; -signal ce_rem_ctr : std_logic; -- count enable for remove counter -signal remove_done_comb : std_logic; -signal remove_done : std_logic; -- end of header stripping process -signal read_done_comb : std_logic; -signal read_done : std_logic; -- end of data phase (read phase from SF) - -signal pc_data : std_logic_vector(7 downto 0); -signal pc_data_q : std_logic_vector(7 downto 0); -signal pc_trig_nr : std_logic_vector(15 downto 0); -signal pc_sub_size : std_logic_vector(17 downto 0); -signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo -signal padding_needed : std_logic; -signal pc_wr_en_comb : std_logic; -signal pc_wr_en_q : std_logic; -signal pc_wr_en_qq : std_logic; -signal pc_wr_en_qqq : std_logic; -signal pc_eod_q : std_logic; - -signal debug : std_logic_vector(383 downto 0); - --- gk -signal bank_select : std_logic_vector(3 downto 0); -signal save_addr_comb : std_logic; -signal save_addr : std_logic; -signal addr_saved_comb : std_logic; -signal addr_saved : std_logic; -signal start_config : std_logic; -signal config_done : std_logic; -signal add_sub_state : std_logic; -signal add_sub_state_comb : std_logic; -signal add_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub : std_logic; -signal load_sub_comb : std_logic; -signal load_sub_done : std_logic; -signal load_sub_done_comb : std_logic; -signal load_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub_ctr_comb : std_logic; -signal actual_message_size : std_logic_vector(31 downto 0); -signal more_subevents : std_logic; -signal trig_random : std_logic_vector(7 downto 0); -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_lock : std_logic; -signal pc_trig_nr_q : std_logic_vector(31 downto 0); - --- gk 20.07.10 -signal inc_data_ctr : std_logic_vector(31 downto 0); -signal dropped_sm_events_ctr : std_logic_vector(31 downto 0); -signal dropped_lr_events_ctr : std_logic_vector(31 downto 0); -signal dropped_ctr : std_logic_vector(31 downto 0); --- gk 22.07.10 -signal headers_invalid : std_logic; -signal headers_invalid_ctr : std_logic_vector(31 downto 0); -signal cts_len_q : std_logic_vector(15 downto 0); -signal cts_trg_q : std_logic_vector(15 downto 0); -signal cts_rnd_q : std_logic_vector(15 downto 0); -signal first_run_trg : std_logic_vector(15 downto 0); -signal first_run_addr : std_logic_vector(15 downto 0); -signal first_run_lock : std_logic; -signal cts_addr : std_logic_vector(15 downto 0); -signal cts_addr_q : std_logic_vector(15 downto 0); -signal cts_addr_saved : std_logic; - --- gk 24.07.10 -signal save_eod : std_logic; -signal save_eod_comb : std_logic; - -signal load_eod : std_logic; -signal endpoint_addr : std_logic_vector(15 downto 0); -signal endp_addr_lock : std_logic; - -signal saved_events_ctr : std_logic_vector(15 downto 0); -signal loaded_events_ctr : std_logic_vector(15 downto 0); -signal constr_events_ctr : std_logic_vector(31 downto 0); -signal event_waiting : std_logic; - -signal drop_sub : std_logic; -signal drop_sub_comb : std_logic; -signal drop_event : std_logic; -signal drop_event_comb : std_logic; -signal drop_small : std_logic; -signal drop_large : std_logic; -signal drop_headers : std_logic; -signal drop_small_comb : std_logic; -signal drop_large_comb : std_logic; -signal drop_headers_comb : std_logic; -signal inc_trg_ctr : std_logic; -signal inc_trg_ctr_comb : std_logic; - -signal invalid_hsize_ctr : std_logic_vector(15 downto 0); -signal invalid_hsize_lock : std_logic; - -signal load_eod_q : std_logic; -signal read_size_q : std_logic_vector(17 downto 0); - --- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked -signal sf_real_wr_en : std_logic; - --- gk 01.10.10 -signal found_empty_evt : std_logic; -signal found_empty_evt_comb : std_logic; -signal found_empty_evt_ctr : std_logic_vector(31 downto 0); - -begin - -BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 -START_CONFIG_OUT <= start_config; -- gk 27.03.10 -config_done <= CONFIG_DONE_IN; -- gk 29.03.10 - --- CTS interface signals -cts_error_pattern <= (others => '0'); -- FAKE - -cts_length <= x"0000"; -- length of data payload is always 0 -cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' - -cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; - -cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) - else '0'; - --- Byte swapping... done here. TAKE CARE! --- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes --- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port. --- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped --- for GbE inside the packet constructor. --- --- Long live the Endianess! - --- Sync all critical pathes -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below - sf_wr_en <= sf_wr_en_comb; - ce_rem_ctr <= ce_rem_ctr_comb; - sf_rd_en <= sf_rd_en_comb; - fee_read <= fee_read_comb; - read_done <= read_done_comb; - pc_eod_q <= pc_eod; - pc_wr_en_qqq <= pc_wr_en_qq; - pc_wr_en_qq <= pc_wr_en_q; - pc_wr_en_q <= pc_wr_en_comb; - end if; -end process THE_SYNC_PROC; - --- gk 27.03.10 data selector for sf to write the evt builder address on top of data -SF_DATA_PROC : process( CLK ) -begin - if( rising_edge(CLK) ) then - if (RESET = '1') then -- gk 31.05.10 - sf_data <= (others => '0'); - elsif( save_addr = '1' ) then - sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address - sf_data(15 downto 4) <= x"abc"; - -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent - elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then - sf_data <= x"0001"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then - sf_data <= x"5555"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then - sf_data <= FEE_STATUS_BITS_IN(31 downto 16); - elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then - sf_data <= FEE_STATUS_BITS_IN(15 downto 0); - else - sf_data <= FEE_DATA_IN; - end if; - end if; -end process SF_DATA_PROC; - --- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY -fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled - else '0'; - --- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY -sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled - (save_addr = '1') or - (add_sub_state = '1') -- gk 29.03.10 save the subsubevent - else '0'; - --- gk 06.08.10 -sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0'; - --- gk 27.03.10 do not count evt builder address as saved ipu bytes ---ce_saved_ctr <= sf_wr_en; -ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en; - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -saveMachineProc: process( CLK ) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saveCurrentState <= SIDLE; - data_req <= '0'; - rst_saved_ctr <= '0'; - save_addr <= '0'; -- gk 27.03.10 - addr_saved <= '0'; -- gk 27.03.10 - add_sub_state <= '0'; -- gk 29.03.10 - save_eod <= '0'; -- gk 25.07.10 - else - saveCurrentState <= saveNextState; - data_req <= data_req_comb; - rst_saved_ctr <= rst_saved_ctr_comb; - save_addr <= save_addr_comb; -- gk 27.03.10 - addr_saved <= addr_saved_comb; -- gk 27.03.10 - add_sub_state <= add_sub_state_comb; -- gk 29.03.10 - save_eod <= save_eod_comb; -- gk 25.07.10 - end if; - end if; -end process saveMachineProc; - -saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN) -begin - saveNextState <= SIDLE; - data_req_comb <= '0'; - rst_saved_ctr_comb <= '0'; - save_addr_comb <= '0'; -- gk 27.03.10 - addr_saved_comb <= '0'; -- gk 27.03.10 - add_sub_state_comb <= '0'; -- gk 29.03.10 - save_eod_comb <= '0'; -- gk 25.07.10 - case saveCurrentState is - when SIDLE => - state <= x"0"; - if (CTS_START_READOUT_IN = '1') then - saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10 - data_req_comb <= '1'; - rst_saved_ctr_comb <= '1'; - else - saveNextState <= SIDLE; - end if; - -- gk 27.03.10 - when SAVE_EVT_ADDR => - state <= x"5"; - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - save_addr_comb <= '1'; - when WAIT_FOR_DATA => - state <= x"1"; - if (FEE_BUSY_IN = '1') then - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - else - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - end if; - addr_saved_comb <= '1'; -- gk 27.03.10 - when SAVE_DATA => - state <= x"2"; - if (FEE_BUSY_IN = '0') then - saveNextState <= TERMINATE; - else - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - end if; - when TERMINATE => - state <= x"3"; - if (CTS_READ_IN = '1') then - saveNextState <= SCLOSE; - else - saveNextState <= TERMINATE; - end if; - when SCLOSE => - state <= x"4"; - if (CTS_START_READOUT_IN = '0') then - saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10 - else - saveNextState <= SCLOSE; - end if; - -- gk 29.03.10 new states during which the subsub bytes are saved - when ADD_SUBSUB1 => - state <= x"6"; - saveNextState <= ADD_SUBSUB2; - add_sub_state_comb <= '1'; - when ADD_SUBSUB2 => - state<= x"7"; - saveNextState <= ADD_SUBSUB3; - add_sub_state_comb <= '1'; - save_eod_comb <= '1'; - when ADD_SUBSUB3 => - state<= x"8"; - saveNextState <= ADD_SUBSUB4; - add_sub_state_comb <= '1'; - when ADD_SUBSUB4 => - state<= x"9"; - saveNextState <= SIDLE; - add_sub_state_comb <= '1'; - when others => - state <= x"f"; - saveNextState <= SIDLE; - end case; -end process saveMachine; - --- gk 29.03.10 -ADD_SUB_CTR_PROC : process( CLK ) -begin - if( rising_edge( CLK ) ) then - if( (RESET = '1') or (rst_saved_ctr = '1') ) then - add_sub_ctr <= (others => '0'); - elsif( add_sub_state = '1' ) then - add_sub_ctr <= add_sub_ctr + 1; - end if; - end if; -end process ADD_SUB_CTR_PROC; - ---******** --- SAVE INCOMING EVENT HEADERS ---******** - --- Counter for header word storage -THE_CTS_SAVED_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - saved_ctr <= (others => '0'); - elsif( ce_saved_ctr = '1' ) then - saved_ctr <= saved_ctr + 1; - end if; - end if; -end process THE_CTS_SAVED_CTR; - --- save triggerRnd from incoming data for cts response -CTS_RND_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_rnd <= (others => '0'); - cts_rnd_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then - cts_rnd <= sf_data; - cts_rnd_saved <= '1'; - end if; - end if; -end process CTS_RND_PROC; - --- save triggerNr from incoming data for cts response -CTS_TRG_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_trg <= (others => '0'); - cts_trg_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then - cts_trg <= sf_data; - cts_trg_saved <= '1'; - end if; - end if; -end process CTS_TRG_PROC; - --- save size from incoming data for cts response (future) and to get rid of padding -CTS_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_len <= (others => '0'); - cts_len_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then - cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words - cts_len(0) <= '0'; - elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then - cts_len <= cts_len + x"4"; - cts_len_saved <= '1'; - end if; - end if; -end process CTS_SIZE_PROC; - --- gk 22.07.10 -CTS_ADDR_PROC : process(CLK) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_addr <= (others => '0'); - cts_addr_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then - cts_addr <= sf_data; - cts_addr_saved <= '1'; - end if; - end if; -end process CTS_ADDR_PROC; - ---****** --- SAVE FIRST EVENT HEADER VALUES ---****** - --- gk 22.07.10 -FIRST_RUN_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - first_run_trg <= (others => '0'); - first_run_addr <= (others => '0'); - first_run_lock <= '0'; - elsif (first_run_lock = '0') and (cts_addr_saved = '1') then - first_run_trg <= cts_trg; - first_run_addr <= cts_addr; - first_run_lock <= '1'; - -- important: value saved by saveMachine but incremented by loadMachine - elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then - first_run_trg <= first_run_trg + x"1"; - end if; - end if; -end process FIRST_RUN_PROC; - --- gk 25.07.10 -SAVED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saved_events_ctr <= (others => '0'); - elsif (save_eod = '1') then - saved_events_ctr <= saved_events_ctr + x"1"; - end if; - end if; -end process SAVED_EVT_CTR_PROC; - - --- gk 20.07.10 -INC_DATA_CTR_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_saved_ctr = '1') then - inc_data_ctr <= (others => '0'); - elsif (sf_wr_en = '1') and (data_req = '1') then - inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1"; - end if; - end if; -end process INC_DATA_CTR_proc; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Split FIFO -THE_SPLIT_FIFO: fifo_32kx16x8_mb2 -port map( - -- Byte swapping for correct byte order on readout side of FIFO - Data(7 downto 0) => sf_data(15 downto 8), - Data(8) => '0', - Data(16 downto 9) => sf_data(7 downto 0), - Data(17) => save_eod, - WrClock => CLK, - RdClock => CLK, - WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en, - RdEn => sf_rd_en, - Reset => RESET, - RPReset => RESET, - AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead - AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 - Q(7 downto 0) => pc_data, - Q(8) => load_eod, - WCNT => sf_wcnt, - RCNT => sf_rcnt, - Empty => sf_empty, - AlmostEmpty => sf_aempty, - Full => sf_full, - AlmostFull => sf_afull -); - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- gk 25.07.10 -EVENT_WAITING_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - event_waiting <= '0'; - elsif (loaded_events_ctr /= saved_events_ctr) then - event_waiting <= '1'; - else - event_waiting <= '0'; - end if; - end if; -end process EVENT_WAITING_PROC; - --- write signal for PC data -pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or - (pad_phase = '1') or - ((load_sub = '1') and (sf_rd_en = '1')) or - ((drop_sub = '1') and (sf_rd_en = '1')) or - ((drop_event = '1') and (sf_rd_en = '1')) - else '0'; - -sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or - --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or - ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10 - ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10 - ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or - ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') ) - else '0'; - -ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') ) - else '0'; - --- FIFO data delay process (also forces padding bytes to known value) -THE_DATA_DELAY_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( pad_data = '1' ) then - pc_data_q <= x"aa"; -- padding for 64bit - -- gk 21.07.10 - -- set the error flag if a broken packet is sent - elsif (drop_sub = '1') and (load_sub_ctr = x"3") then - pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0); - else - pc_data_q <= pc_data; - end if; - end if; -end process THE_DATA_DELAY_PROC; - --- Statemachine for reading the data payload from the SPLIT_FIFO and feeding --- it into the packet constructor -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loadCurrentState <= LIDLE; - rst_rem_ctr <= '0'; - rem_phase <= '0'; - calc_pad <= '0'; - data_phase <= '0'; - pad_phase <= '0'; - pc_sos <= '0'; - pc_eod <= '0'; - rst_regs <= '0'; - pad_data <= '0'; - load_sub <= '0'; -- gk 30.03.10 - drop_sub <= '0'; -- gk 25.07.10 - drop_event <= '0'; -- gk 25.07.10 - drop_small <= '0'; -- gk 25.07.10 - drop_large <= '0'; -- gk 25.07.10 - drop_headers <= '0'; -- gk 25.07.10 - inc_trg_ctr <= '0'; -- gk 26.07.10 - found_empty_evt <= '0'; -- gk 01.10.10 - else - loadCurrentState <= loadNextState; - rst_rem_ctr <= rst_rem_ctr_comb; - rem_phase <= rem_phase_comb; - calc_pad <= calc_pad_comb; - data_phase <= data_phase_comb; - pad_phase <= pad_phase_comb; - pc_sos <= pc_sos_comb; - pc_eod <= pc_eod_comb; - rst_regs <= rst_regs_comb; - pad_data <= pad_data_comb; - load_sub <= load_sub_comb; -- gk 30.03.1 - drop_sub <= drop_sub_comb; -- gk 25.07.10 - drop_event <= drop_event_comb; -- gk 25.07.10 - drop_small <= drop_small_comb; -- gk 25.07.10 - drop_large <= drop_large_comb; -- gk 25.07.10 - drop_headers <= drop_headers_comb; -- gk 25.07.10 - inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10 - found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10 - end if; - end if; -end process loadMachineProc; - -loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting) -begin - loadNextState <= LIDLE; - rst_rem_ctr_comb <= '0'; - rem_phase_comb <= '0'; - calc_pad_comb <= '0'; - data_phase_comb <= '0'; - pad_phase_comb <= '0'; - pc_sos_comb <= '0'; - pc_eod_comb <= '0'; - rst_regs_comb <= '0'; - pad_data_comb <= '0'; - load_sub_comb <= '0'; -- gk 30.03.10 - drop_sub_comb <= '0'; -- gk 25.07.10 - drop_event_comb <= '0'; -- gk 25.07.10 - drop_small_comb <= '0'; -- gk 25.07.10 - drop_large_comb <= '0'; -- gk 25.07.10 - drop_headers_comb <= '0'; -- gk 25.07.10 - inc_trg_ctr_comb <= '0'; -- gk 26.07.10 - found_empty_evt_comb <= '0'; -- gk 01.10.10 - case loadCurrentState is - when LIDLE => - state2 <= x"0"; - -- gk 23.07.10 - if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 - loadNextState <= INIT; - rst_rem_ctr_comb <= '1'; - rst_regs_comb <= '1'; - else - loadNextState <= LIDLE; - end if; - when INIT => - state2 <= x"1"; - loadNextState <= REMOVE; - rem_phase_comb <= '1'; - when REMOVE => - state2 <= x"2"; - if( remove_done = '1' ) then - loadNextState <= WAIT_TO_REMOVE; - inc_trg_ctr_comb <= '1'; - else - loadNextState <= REMOVE; - rem_phase_comb <= '1'; - end if; - when WAIT_TO_REMOVE => - if (rem_ctr = x"a") then - loadNextState <= DECIDE; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - when DECIDE => - if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_large_comb <= '1'; - elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10 - loadNextState <= CALCA; - found_empty_evt_comb <= '1'; - elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_small_comb <= '1'; - elsif (pc_trig_nr + x"1" /= first_run_trg) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_headers_comb <= '1'; - elsif (endpoint_addr /= first_run_addr) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_headers_comb <= '1'; - else - loadNextState <= CALCA; - end if; - calc_pad_comb <= '1'; - when CALCA => - state2 <= x"3"; - loadNextState <= CALCB; - pc_sos_comb <= '1'; - when CALCB => - -- we need a branch in case of length "0"!!!! - state2 <= x"4"; - loadNextState <= LOAD; - data_phase_comb <= '1'; - when LOAD => - state2 <= x"5"; - -- gk 31.03.10 after loading subevent data read the subsubevent from sf - if (load_eod = '1') then - loadNextState <= LOAD_SUBSUB; - else - loadNextState <= LOAD; - data_phase_comb <= '1'; - end if; - -- gk 31.03.10 - when LOAD_SUBSUB => - state2 <= x"d"; - if( load_sub_done = '1' ) then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= LOAD_SUBSUB; - load_sub_comb <= '1'; - end if; - when PAD0 => - state2 <= x"6"; - loadNextState <= PAD1; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD1 => - state2 <= x"7"; - loadNextState <= PAD2; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD2 => - state2 <= x"8"; - loadNextState <= PAD3; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD3 => - state2 <= x"9"; - loadNextState <= CALCC; - pad_data_comb <= '1'; - when CALCC => - state2 <= x"a"; - loadNextState <= CLOSE; - pc_eod_comb <= '1'; - when CLOSE => - state2 <= x"b"; - loadNextState <= WAIT_PC; - rst_regs_comb <= '1'; - when WAIT_PC => - state2 <= x"c"; - if( PC_READY_IN = '1' ) then - loadNextState <= LIDLE; - else - loadNextState <= WAIT_PC; - end if; - when PAUSE_BEFORE_DROP1 => - loadNextState <= PAUSE_BEFORE_DROP2; - pc_sos_comb <= '1'; - when PAUSE_BEFORE_DROP2 => - loadNextState <= DROP; - drop_event_comb <= '1'; - -- gk 23.07.10 - when DROP => - state2 <= x"e"; - -- when data is dropped the eod marker stands as its end - if (load_eod = '1') then - loadNextState <= DROP_SUBSUB; - else - loadNextState <= DROP; - drop_event_comb <= '1'; - end if; - -- gk 25.07.10 - when DROP_SUBSUB => - if (load_sub_done = '1') then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= DROP_SUBSUB; - drop_sub_comb <= '1'; - end if; - when others => - state2 <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- gk 25.07.10 -INVALID_STATS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - dropped_lr_events_ctr <= (others => '0'); - dropped_sm_events_ctr <= (others => '0'); - headers_invalid_ctr <= (others => '0'); - dropped_ctr <= (others => '0'); - invalid_hsize_ctr <= (others => '0'); - found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10 - elsif (rst_regs = '1') then - invalid_hsize_lock <= '0'; - elsif (drop_small = '1') then - dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1"; - dropped_ctr <= dropped_ctr + x"1"; - elsif (drop_large = '1') then - dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1"; - dropped_ctr <= dropped_ctr + x"1"; - elsif (drop_headers = '1') then - headers_invalid_ctr <= headers_invalid_ctr + x"1"; - dropped_ctr <= dropped_ctr + x"1"; - elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ?? - invalid_hsize_ctr <= invalid_hsize_ctr + x"1"; - invalid_hsize_lock <= '1'; - -- gk 01.10.10 - elsif (found_empty_evt = '1') then - found_empty_evt_ctr <= found_empty_evt_ctr + x"1"; - end if; - end if; -end process INVALID_STATS_PROC; - --- gk 05.08.10 -INVALID_H_PROC : process(CLK) -begin - if rising_edge(CLK) then - load_eod_q <= load_eod; - read_size_q <= read_size; - end if; -end process INVALID_H_PROC; - --- gk 26.04.10 -READOUT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then - readout_ctr <= READOUT_CTR_IN; - readout_ctr_lock <= '0'; - elsif (pc_sos = '1') then - readout_ctr <= readout_ctr + x"1"; - end if; - end if; -end process READOUT_CTR_PROC; - ---****** --- SELECTION OF EVENT BUILDER ---****** - --- gk 27.03.10 -bank_select_proc : process( CLK ) -begin - if rising_edge( CLK ) then - -- gk 29.03.10 - if( (RESET = '1') or (rst_regs = '1') ) then - bank_select <= "0000"; - -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then - bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0); - end if; - end if; -end process bank_select_proc; - --- gk 29.03.10 -start_config_proc : process( CLK ) -begin - if rising_edge( CLK ) then - if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then - start_config <= '0'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then -- gk 01.06.10 - start_config <= '1'; - end if; - end if; -end process start_config_proc; - - ---****** --- LOAD SUBSUBEVENT ---****** - --- gk 30.03.10 -load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') ) - else '0'; - --- gk 30.03.10 -LOAD_SUB_CTR_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_ctr <= (others => '0'); - elsif( (load_sub_ctr_comb = '1') ) then - load_sub_ctr <= load_sub_ctr + 1; - end if; - end if; -end process LOAD_SUB_CTR_PROC; - --- gk 30.03.10 --- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or --- ((load_sub_ctr = x"4") and (drop_sub = '1')) --- else '0'; -load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0'; - --- gk 30.03.10 -LOAD_SUB_DONE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_done <= '0'; - else - load_sub_done <= load_sub_done_comb; - end if; - end if; -end process LOAD_SUB_DONE_PROC; - ---****** --- EXTRACT EVENT HEADERS FROM SPLITFIFO ---****** - --- Counter for stripping the unneeded parts of the data stream, and saving the important parts -THE_REMOVE_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - rem_ctr <= (others => '0'); - elsif( (ce_rem_ctr = '1') ) then - rem_ctr <= rem_ctr + 1; - end if; - end if; -end process THE_REMOVE_CTR; - -remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address - -THE_REM_DONE_SYNC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - remove_done <= '0'; - else - remove_done <= remove_done_comb; - end if; - end if; -end process THE_REM_DONE_SYNC; - --- gk 26.04.10 -TRIG_RANDOM_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (rst_regs = '1')) then - trig_random <= (others => '0'); - elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then - trig_random <= pc_data; - end if; - end if; -end process TRIG_RANDOM_PROC; - --- extract the trigger number from splitfifo data -THE_TRG_NR_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_trig_nr <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10 - pc_trig_nr(7 downto 0) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10 - pc_trig_nr(15 downto 8) <= pc_data; - end if; - end if; -end process THE_TRG_NR_PROC; - --- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, --- and in case of padding needed increase it accordingly -THE_SUB_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_sub_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - pc_sub_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - pc_sub_size(17 downto 10) <= pc_data; - -- gk 20.07.10 - -- gk 30.03.10 bug fixed in the way that is written below - -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save - elsif( (calc_pad = '1') and (padding_needed = '1') ) then - pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!! - elsif( (calc_pad = '1') and (padding_needed = '0') ) then - pc_sub_size <= pc_sub_size + x"8"; - end if; - end if; -end process THE_SUB_SIZE_PROC; - --- gk 25.07.10 -ENDP_ADDRESS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_regs = '1') then - endpoint_addr <= (others => '0'); - endp_addr_lock <= '0'; - elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then - endpoint_addr(7 downto 0) <= pc_data; - endp_addr_lock <= '1'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then - endpoint_addr(15 downto 8) <= pc_data; - endp_addr_lock <= '0'; - end if; - end if; -end process ENDP_ADDRESS_PROC; - - - --- check for padding -THE_PADDING_NEEDED_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - padding_needed <= '0'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then - padding_needed <= '1'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then - padding_needed <= '0'; - end if; - end if; -end process THE_PADDING_NEEDED_PROC; - --- number of bytes to read from split fifo -THE_READ_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then - read_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - read_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - read_size(17 downto 10) <= pc_data; - elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then - read_size <= read_size - 1; - -- gk 25.07.10 - elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then - read_size <= read_size - 1; - end if; - end if; -end process THE_READ_SIZE_PROC; - -read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2" - ---****** --- EVENTS COUNTERS ---****** - --- gk 25.07.10 -LOADED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loaded_events_ctr <= (others => '0'); - elsif (remove_done = '1') then - loaded_events_ctr <= loaded_events_ctr + x"1"; - end if; - end if; -end process LOADED_EVT_CTR_PROC; - --- gk 25.07.10 -CONSTR_EVENTS_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - constr_events_ctr <= (others => '0'); - elsif (pc_eod = '1') then - constr_events_ctr <= constr_events_ctr + x"1"; - end if; - end if; -end process CONSTR_EVENTS_CTR_PROC; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Debug signals -debug(0) <= sf_full; -debug(1) <= sf_empty; -debug(2) <= sf_afull; -debug(3) <= sf_aempty; - -debug(7 downto 4) <= state2; - -debug(11 downto 8) <= state; - -dbg_bs_proc : process(CLK) -begin - if rising_edge(CLK) then - if RESET = '1' then - debug(15 downto 12) <= (others => '0'); - elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then - debug(15 downto 12) <= bank_select; - end if; - end if; -end process dbg_bs_proc; - -debug(16) <= config_done; -debug(17) <= remove_done; -debug(18) <= read_done; -debug(19) <= padding_needed; - -debug(20) <= load_sub_done; - -dbg_cts_inf_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - debug(39 downto 32) <= (others => '0'); - elsif ( save_addr = '1' ) then - debug(39 downto 32) <= CTS_INFORMATION_IN; - end if; - end if; -end process dbg_cts_inf_proc; - -debug(47 downto 40) <= (others => '0'); - - -debug(63 downto 48) <= actual_message_size(15 downto 0); - -dbg_pc_sub_size_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - debug(81 downto 64) <= (others => '0'); - elsif (loadCurrentState = DECIDE) then - debug(81 downto 64) <= pc_sub_size; - end if; - end if; -end process dbg_pc_sub_size_proc; - -dbg_empty_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_regs = '1') then - debug(84 downto 82) <= (others => '0'); - elsif (read_size = 2) then - debug(82) <= sf_empty; - elsif (read_size = 1) then - debug(83) <= sf_empty; - elsif (read_size = 0) then - debug(84) <= sf_empty; - end if; - end if; -end process dbg_empty_proc; - -debug(95 downto 85) <= (others => '0'); - -dbg_inc_ctr_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - debug(127 downto 96) <= (others => '1'); - elsif (saveCurrentState = SCLOSE) then - debug(127 downto 96) <= inc_data_ctr; - end if; - end if; -end process dbg_inc_ctr_proc; - -debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0); -debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0); - -debug(175 downto 160) <= headers_invalid_ctr(15 downto 0); -debug(191 downto 176) <= (others => '0'); - -dbg_cts_q_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - cts_len_q <= (others => '0'); - cts_rnd_q <= (others => '0'); - cts_trg_q <= (others => '0'); - cts_addr_q <= (others => '0'); - elsif (cts_len_saved = '1') then - cts_len_q <= cts_len(16 downto 1); - cts_addr_q <= cts_addr; - cts_rnd_q <= cts_rnd; - cts_trg_q <= cts_trg; - end if; - end if; -end process dbg_cts_q_proc; - -debug(207 downto 192) <= cts_trg_q; -debug(223 downto 208) <= cts_rnd_q; -debug(239 downto 224) <= cts_addr_q; -debug(255 downto 240) <= cts_len_q; -debug(271 downto 256) <= first_run_trg; -debug(287 downto 272) <= first_run_addr; - -debug(303 downto 288) <= saved_events_ctr; -debug(319 downto 304) <= loaded_events_ctr; - -debug(335 downto 320) <= constr_events_ctr(15 downto 0); -debug(351 downto 336) <= dropped_ctr(15 downto 0); - -debug(367 downto 352) <= invalid_hsize_ctr; -debug(383 downto 368) <= (others => '0'); - -MONITOR_OUT(31 downto 0) <= constr_events_ctr; -MONITOR_OUT(63 downto 32) <= dropped_ctr; -MONITOR_OUT(95 downto 64) <= headers_invalid_ctr; -MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr; -MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr; -MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000"; -MONITOR_OUT(191 downto 164) <= (others => '0'); -MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10 - --- Outputs -FEE_READ_OUT <= fee_read; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; -CTS_DATA_OUT <= cts_data; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_LENGTH_OUT <= cts_length; - -PC_SOS_OUT <= pc_sos; -PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q; -PC_DATA_OUT <= pc_data_q; -PC_WR_EN_OUT <= pc_wr_en_qq; - -PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random; - -PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; -PC_PADDING_OUT <= padding_needed; - -DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd b/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd deleted file mode 100644 index 29b1529..0000000 --- a/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd +++ /dev/null @@ -1,1403 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity trb_net16_ipu2gbe is -port( - CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 - MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - -- PacketConstructor interface - ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; -- gk 07.10.10 - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) -); -end entity; - -architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is - --- attribute HGROUP : string; --- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe"; - -component fifo_32kx16x8_mb2 -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - AlmostEmpty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic -); -end component; - -type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE); -signal saveCurrentState, saveNextState : saveStates; -signal state : std_logic_vector(3 downto 0); -signal data_req_comb : std_logic; -signal data_req : std_logic; -- request data signal, will be used for fee_read generation -signal rst_saved_ctr_comb : std_logic; -signal rst_saved_ctr : std_logic; - -signal fee_read_comb : std_logic; -signal fee_read : std_logic; -- fee_read signal -signal saved_ctr : std_logic_vector(16 downto 0); -signal ce_saved_ctr : std_logic; - --- header data -signal cts_rnd : std_logic_vector(15 downto 0); -signal cts_rnd_saved : std_logic; -signal cts_trg : std_logic_vector(15 downto 0); -signal cts_trg_saved : std_logic; -signal cts_len : std_logic_vector(16 downto 0); -signal cts_len_saved : std_logic; - --- CTS interface -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal cts_length : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_data : std_logic_vector(31 downto 0); - --- Split FIFO signals -signal sf_data : std_logic_vector(15 downto 0); -signal sf_wr_en_comb : std_logic; -signal sf_wr_en : std_logic; -- write signal for FIFO -signal sf_rd_en_comb : std_logic; -signal sf_rd_en : std_logic; -- read signal for FIFO -signal sf_wcnt : std_logic_vector(15 downto 0); -signal sf_rcnt : std_logic_vector(16 downto 0); -signal sf_empty : std_logic; -signal sf_aempty : std_logic; -signal sf_full : std_logic; -signal sf_afull : std_logic; - -------------------------------------------------------------------- -type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2); -signal loadCurrentState, loadNextState : loadStates; -signal state2 : std_logic_vector(3 downto 0); - -signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data -signal rst_rem_ctr_comb : std_logic; -signal rst_rem_ctr : std_logic; -- reset the remove counter -signal rst_regs_comb : std_logic; -signal rst_regs : std_logic; -- reset storage registers -signal rem_phase_comb : std_logic; -signal rem_phase : std_logic; -- header remove phase -signal data_phase_comb : std_logic; -signal data_phase : std_logic; -- data transport phase from split fifo to PC -signal pad_phase_comb : std_logic; -signal pad_phase : std_logic; -- padding phase -signal calc_pad_comb : std_logic; -signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE -signal pad_data_comb : std_logic; -signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value - -signal pc_sos_comb : std_logic; -signal pc_sos : std_logic; -- start of data signal -signal pc_eod_comb : std_logic; -signal pc_eod : std_logic; -- end of data signal - -signal ce_rem_ctr_comb : std_logic; -signal ce_rem_ctr : std_logic; -- count enable for remove counter -signal remove_done_comb : std_logic; -signal remove_done : std_logic; -- end of header stripping process -signal read_done_comb : std_logic; -signal read_done : std_logic; -- end of data phase (read phase from SF) - -signal pc_data : std_logic_vector(7 downto 0); -signal pc_data_q : std_logic_vector(7 downto 0); -signal pc_trig_nr : std_logic_vector(15 downto 0); -signal pc_sub_size : std_logic_vector(17 downto 0); -signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo -signal padding_needed : std_logic; -signal pc_wr_en_comb : std_logic; -signal pc_wr_en_q : std_logic; -signal pc_wr_en_qq : std_logic; -signal pc_wr_en_qqq : std_logic; -signal pc_eod_q : std_logic; - -signal debug : std_logic_vector(383 downto 0); - --- gk -signal bank_select : std_logic_vector(3 downto 0); -signal save_addr_comb : std_logic; -signal save_addr : std_logic; -signal addr_saved_comb : std_logic; -signal addr_saved : std_logic; -signal start_config : std_logic; -signal config_done : std_logic; -signal add_sub_state : std_logic; -signal add_sub_state_comb : std_logic; -signal add_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub : std_logic; -signal load_sub_comb : std_logic; -signal load_sub_done : std_logic; -signal load_sub_done_comb : std_logic; -signal load_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub_ctr_comb : std_logic; -signal actual_message_size : std_logic_vector(31 downto 0); -signal more_subevents : std_logic; -signal trig_random : std_logic_vector(7 downto 0); -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_lock : std_logic; -signal pc_trig_nr_q : std_logic_vector(31 downto 0); - --- gk 20.07.10 -signal inc_data_ctr : std_logic_vector(31 downto 0); -signal dropped_sm_events_ctr : std_logic_vector(31 downto 0); -signal dropped_lr_events_ctr : std_logic_vector(31 downto 0); -signal dropped_ctr : std_logic_vector(31 downto 0); --- gk 22.07.10 -signal headers_invalid : std_logic; -signal headers_invalid_ctr : std_logic_vector(31 downto 0); -signal cts_len_q : std_logic_vector(15 downto 0); -signal cts_trg_q : std_logic_vector(15 downto 0); -signal cts_rnd_q : std_logic_vector(15 downto 0); -signal first_run_trg : std_logic_vector(15 downto 0); -signal first_run_addr : std_logic_vector(15 downto 0); -signal first_run_lock : std_logic; -signal cts_addr : std_logic_vector(15 downto 0); -signal cts_addr_q : std_logic_vector(15 downto 0); -signal cts_addr_saved : std_logic; - --- gk 24.07.10 -signal save_eod : std_logic; -signal save_eod_comb : std_logic; - -signal load_eod : std_logic; -signal endpoint_addr : std_logic_vector(15 downto 0); -signal endp_addr_lock : std_logic; - -signal saved_events_ctr : std_logic_vector(15 downto 0); -signal loaded_events_ctr : std_logic_vector(15 downto 0); -signal constr_events_ctr : std_logic_vector(31 downto 0); -signal event_waiting : std_logic; - -signal drop_sub : std_logic; -signal drop_sub_comb : std_logic; -signal drop_event : std_logic; -signal drop_event_comb : std_logic; -signal drop_small : std_logic; -signal drop_large : std_logic; -signal drop_headers : std_logic; -signal drop_small_comb : std_logic; -signal drop_large_comb : std_logic; -signal drop_headers_comb : std_logic; -signal inc_trg_ctr : std_logic; -signal inc_trg_ctr_comb : std_logic; - -signal invalid_hsize_ctr : std_logic_vector(15 downto 0); -signal invalid_hsize_lock : std_logic; - -signal load_eod_q : std_logic; -signal read_size_q : std_logic_vector(17 downto 0); - --- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked -signal sf_real_wr_en : std_logic; - --- gk 01.10.10 -signal found_empty_evt : std_logic; -signal found_empty_evt_comb : std_logic; -signal found_empty_evt_ctr : std_logic_vector(31 downto 0); - --- gk 06.10.10 -signal message_size : std_logic_vector(31 downto 0); - --- gk 07.12.10 -signal prev_bank_select : std_logic_vector(3 downto 0); -signal first_event : std_logic; - -begin - -BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 -START_CONFIG_OUT <= start_config; -- gk 27.03.10 -config_done <= CONFIG_DONE_IN; -- gk 29.03.10 - --- CTS interface signals -cts_error_pattern <= (others => '0'); -- FAKE - -cts_length <= x"0000"; -- length of data payload is always 0 -cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' - -cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; - -cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) - else '0'; - --- Byte swapping... done here. TAKE CARE! --- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes --- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port. --- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped --- for GbE inside the packet constructor. --- --- Long live the Endianess! - --- Sync all critical pathes -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below - sf_wr_en <= sf_wr_en_comb; - ce_rem_ctr <= ce_rem_ctr_comb; - sf_rd_en <= sf_rd_en_comb; - fee_read <= fee_read_comb; - read_done <= read_done_comb; - pc_eod_q <= pc_eod; - pc_wr_en_qqq <= pc_wr_en_qq; - pc_wr_en_qq <= pc_wr_en_q; - pc_wr_en_q <= pc_wr_en_comb; - end if; -end process THE_SYNC_PROC; - --- -- gk 27.03.10 data selector for sf to write the evt builder address on top of data --- SF_DATA_PROC : process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if (RESET = '1') then -- gk 31.05.10 --- sf_data <= (others => '0'); --- elsif( save_addr = '1' ) then --- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address --- sf_data(15 downto 4) <= x"abc"; --- -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent --- elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then --- sf_data <= x"0001"; -- gk 11.06.10 --- elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then --- sf_data <= x"5555"; -- gk 11.06.10 --- elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then --- sf_data <= FEE_STATUS_BITS_IN(31 downto 16); --- elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then --- sf_data <= FEE_STATUS_BITS_IN(15 downto 0); --- else --- sf_data <= FEE_DATA_IN; --- end if; --- end if; --- end process SF_DATA_PROC; - --- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY -fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled - else '0'; - --- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY -sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled - (save_addr = '1') or - (add_sub_state = '1') -- gk 29.03.10 save the subsubevent - else '0'; - --- gk 06.08.10 -sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0'; - --- gk 27.03.10 do not count evt builder address as saved ipu bytes ---ce_saved_ctr <= sf_wr_en; -ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en; - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO --- saveMachineProc: process( CLK ) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- saveCurrentState <= SIDLE; --- data_req <= '0'; --- rst_saved_ctr <= '0'; --- save_addr <= '0'; -- gk 27.03.10 --- addr_saved <= '0'; -- gk 27.03.10 --- add_sub_state <= '0'; -- gk 29.03.10 --- save_eod <= '0'; -- gk 25.07.10 --- else --- saveCurrentState <= saveNextState; --- data_req <= data_req_comb; --- rst_saved_ctr <= rst_saved_ctr_comb; --- save_addr <= save_addr_comb; -- gk 27.03.10 --- addr_saved <= addr_saved_comb; -- gk 27.03.10 --- add_sub_state <= add_sub_state_comb; -- gk 29.03.10 --- save_eod <= save_eod_comb; -- gk 25.07.10 --- end if; --- end if; --- end process saveMachineProc; --- --- saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN) --- begin --- saveNextState <= SIDLE; --- data_req_comb <= '0'; --- rst_saved_ctr_comb <= '0'; --- save_addr_comb <= '0'; -- gk 27.03.10 --- addr_saved_comb <= '0'; -- gk 27.03.10 --- add_sub_state_comb <= '0'; -- gk 29.03.10 --- save_eod_comb <= '0'; -- gk 25.07.10 --- case saveCurrentState is --- when SIDLE => --- state <= x"0"; --- if (CTS_START_READOUT_IN = '1') then --- saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10 --- data_req_comb <= '1'; --- rst_saved_ctr_comb <= '1'; --- else --- saveNextState <= SIDLE; --- end if; --- -- gk 27.03.10 --- when SAVE_EVT_ADDR => --- state <= x"5"; --- saveNextState <= WAIT_FOR_DATA; --- data_req_comb <= '1'; --- save_addr_comb <= '1'; --- when WAIT_FOR_DATA => --- state <= x"1"; --- if (FEE_BUSY_IN = '1') then --- saveNextState <= SAVE_DATA; --- data_req_comb <= '1'; --- else --- saveNextState <= WAIT_FOR_DATA; --- data_req_comb <= '1'; --- end if; --- addr_saved_comb <= '1'; -- gk 27.03.10 --- when SAVE_DATA => --- state <= x"2"; --- if (FEE_BUSY_IN = '0') then --- saveNextState <= TERMINATE; --- else --- saveNextState <= SAVE_DATA; --- data_req_comb <= '1'; --- end if; --- when TERMINATE => --- state <= x"3"; --- if (CTS_READ_IN = '1') then --- saveNextState <= SCLOSE; --- else --- saveNextState <= TERMINATE; --- end if; --- when SCLOSE => --- state <= x"4"; --- if (CTS_START_READOUT_IN = '0') then --- saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10 --- else --- saveNextState <= SCLOSE; --- end if; --- -- gk 29.03.10 new states during which the subsub bytes are saved --- when ADD_SUBSUB1 => --- state <= x"6"; --- saveNextState <= ADD_SUBSUB2; --- add_sub_state_comb <= '1'; --- when ADD_SUBSUB2 => --- state<= x"7"; --- saveNextState <= ADD_SUBSUB3; --- add_sub_state_comb <= '1'; --- save_eod_comb <= '1'; --- when ADD_SUBSUB3 => --- state<= x"8"; --- saveNextState <= ADD_SUBSUB4; --- add_sub_state_comb <= '1'; --- when ADD_SUBSUB4 => --- state<= x"9"; --- saveNextState <= SIDLE; --- add_sub_state_comb <= '1'; --- when others => --- state <= x"f"; --- saveNextState <= SIDLE; --- end case; --- end process saveMachine; --- --- -- gk 29.03.10 --- ADD_SUB_CTR_PROC : process( CLK ) --- begin --- if( rising_edge( CLK ) ) then --- if( (RESET = '1') or (rst_saved_ctr = '1') ) then --- add_sub_ctr <= (others => '0'); --- elsif( add_sub_state = '1' ) then --- add_sub_ctr <= add_sub_ctr + 1; --- end if; --- end if; --- end process ADD_SUB_CTR_PROC; --- --- --******** --- -- SAVE INCOMING EVENT HEADERS --- --******** --- --- -- Counter for header word storage --- THE_CTS_SAVED_CTR: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then --- saved_ctr <= (others => '0'); --- elsif( ce_saved_ctr = '1' ) then --- saved_ctr <= saved_ctr + 1; --- end if; --- end if; --- end process THE_CTS_SAVED_CTR; --- --- -- save triggerRnd from incoming data for cts response --- CTS_RND_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then --- cts_rnd <= (others => '0'); --- cts_rnd_saved <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then --- cts_rnd <= sf_data; --- cts_rnd_saved <= '1'; --- end if; --- end if; --- end process CTS_RND_PROC; --- --- -- save triggerNr from incoming data for cts response --- CTS_TRG_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then --- cts_trg <= (others => '0'); --- cts_trg_saved <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then --- cts_trg <= sf_data; --- cts_trg_saved <= '1'; --- end if; --- end if; --- end process CTS_TRG_PROC; --- --- -- save size from incoming data for cts response (future) and to get rid of padding --- CTS_SIZE_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then --- cts_len <= (others => '0'); --- cts_len_saved <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then --- cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words --- cts_len(0) <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then --- cts_len <= cts_len + x"4"; --- cts_len_saved <= '1'; --- end if; --- end if; --- end process CTS_SIZE_PROC; --- --- -- gk 22.07.10 --- CTS_ADDR_PROC : process(CLK) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_saved_ctr = '1') ) then --- cts_addr <= (others => '0'); --- cts_addr_saved <= '0'; --- elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then --- cts_addr <= sf_data; --- cts_addr_saved <= '1'; --- end if; --- end if; --- end process CTS_ADDR_PROC; --- --- --****** --- -- SAVE FIRST EVENT HEADER VALUES --- --****** --- --- -- gk 22.07.10 --- FIRST_RUN_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- first_run_trg <= (others => '0'); --- first_run_addr <= (others => '0'); --- first_run_lock <= '0'; --- elsif (first_run_lock = '0') and (cts_addr_saved = '1') then --- first_run_trg <= cts_trg; --- first_run_addr <= cts_addr; --- first_run_lock <= '1'; --- -- important: value saved by saveMachine but incremented by loadMachine --- elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then --- first_run_trg <= first_run_trg + x"1"; --- end if; --- end if; --- end process FIRST_RUN_PROC; --- --- -- gk 25.07.10 --- SAVED_EVT_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- saved_events_ctr <= (others => '0'); --- elsif (save_eod = '1') then --- saved_events_ctr <= saved_events_ctr + x"1"; --- end if; --- end if; --- end process SAVED_EVT_CTR_PROC; --- --- --- -- gk 20.07.10 --- INC_DATA_CTR_proc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (rst_saved_ctr = '1') then --- inc_data_ctr <= (others => '0'); --- elsif (sf_wr_en = '1') and (data_req = '1') then --- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1"; --- end if; --- end if; --- end process INC_DATA_CTR_proc; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Split FIFO --- THE_SPLIT_FIFO: fifo_32kx16x8_mb2 --- port map( --- -- Byte swapping for correct byte order on readout side of FIFO --- Data(7 downto 0) => sf_data(15 downto 8), --- Data(8) => '0', --- Data(16 downto 9) => sf_data(7 downto 0), --- Data(17) => save_eod, --- WrClock => CLK, --- RdClock => CLK, --- WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en, --- RdEn => sf_rd_en, --- Reset => RESET, --- RPReset => RESET, --- AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead --- AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 --- Q(7 downto 0) => pc_data, --- Q(8) => load_eod, --- WCNT => sf_wcnt, --- RCNT => sf_rcnt, --- Empty => sf_empty, --- AlmostEmpty => sf_aempty, --- Full => sf_full, --- AlmostFull => sf_afull --- ); - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- gk 25.07.10 --- EVENT_WAITING_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- event_waiting <= '0'; --- elsif (loaded_events_ctr /= saved_events_ctr) then --- event_waiting <= '1'; --- else --- event_waiting <= '0'; --- end if; --- end if; --- end process EVENT_WAITING_PROC; --- --- -- write signal for PC data --- pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or --- (pad_phase = '1') or --- ((load_sub = '1') and (sf_rd_en = '1')) or --- ((drop_sub = '1') and (sf_rd_en = '1')) or --- ((drop_event = '1') and (sf_rd_en = '1')) --- else '0'; --- --- sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or --- --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or --- ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10 --- ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10 --- ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or --- ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') ) --- else '0'; --- --- ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') ) --- else '0'; --- --- -- FIFO data delay process (also forces padding bytes to known value) --- THE_DATA_DELAY_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if( pad_data = '1' ) then --- pc_data_q <= x"aa"; -- padding for 64bit --- -- gk 21.07.10 --- -- set the error flag if a broken packet is sent --- elsif (drop_sub = '1') and (load_sub_ctr = x"3") then --- pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0); --- else --- pc_data_q <= pc_data; --- end if; --- end if; --- end process THE_DATA_DELAY_PROC; --- --- -- Statemachine for reading the data payload from the SPLIT_FIFO and feeding --- -- it into the packet constructor --- loadMachineProc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- loadCurrentState <= LIDLE; --- rst_rem_ctr <= '0'; --- rem_phase <= '0'; --- calc_pad <= '0'; --- data_phase <= '0'; --- pad_phase <= '0'; --- pc_sos <= '0'; --- pc_eod <= '0'; --- rst_regs <= '0'; --- pad_data <= '0'; --- load_sub <= '0'; -- gk 30.03.10 --- drop_sub <= '0'; -- gk 25.07.10 --- drop_event <= '0'; -- gk 25.07.10 --- drop_small <= '0'; -- gk 25.07.10 --- drop_large <= '0'; -- gk 25.07.10 --- drop_headers <= '0'; -- gk 25.07.10 --- inc_trg_ctr <= '0'; -- gk 26.07.10 --- found_empty_evt <= '0'; -- gk 01.10.10 --- else --- loadCurrentState <= loadNextState; --- rst_rem_ctr <= rst_rem_ctr_comb; --- rem_phase <= rem_phase_comb; --- calc_pad <= calc_pad_comb; --- data_phase <= data_phase_comb; --- pad_phase <= pad_phase_comb; --- pc_sos <= pc_sos_comb; --- pc_eod <= pc_eod_comb; --- rst_regs <= rst_regs_comb; --- pad_data <= pad_data_comb; --- load_sub <= load_sub_comb; -- gk 30.03.1 --- drop_sub <= drop_sub_comb; -- gk 25.07.10 --- drop_event <= drop_event_comb; -- gk 25.07.10 --- drop_small <= drop_small_comb; -- gk 25.07.10 --- drop_large <= drop_large_comb; -- gk 25.07.10 --- drop_headers <= drop_headers_comb; -- gk 25.07.10 --- inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10 --- found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10 --- end if; --- end if; --- end process loadMachineProc; --- --- loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, --- PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, --- MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, --- first_run_addr, load_eod, event_waiting, MULT_EVT_ENABLE_IN, message_size) --- begin --- loadNextState <= LIDLE; --- rst_rem_ctr_comb <= '0'; --- rem_phase_comb <= '0'; --- calc_pad_comb <= '0'; --- data_phase_comb <= '0'; --- pad_phase_comb <= '0'; --- pc_sos_comb <= '0'; --- pc_eod_comb <= '0'; --- rst_regs_comb <= '0'; --- pad_data_comb <= '0'; --- load_sub_comb <= '0'; -- gk 30.03.10 --- drop_sub_comb <= '0'; -- gk 25.07.10 --- drop_event_comb <= '0'; -- gk 25.07.10 --- drop_small_comb <= '0'; -- gk 25.07.10 --- drop_large_comb <= '0'; -- gk 25.07.10 --- drop_headers_comb <= '0'; -- gk 25.07.10 --- inc_trg_ctr_comb <= '0'; -- gk 26.07.10 --- found_empty_evt_comb <= '0'; -- gk 01.10.10 --- case loadCurrentState is --- when LIDLE => --- state2 <= x"0"; --- -- gk 23.07.10 --- if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 -- and (PC_READY_IN = '1') --- loadNextState <= INIT; --- rst_rem_ctr_comb <= '1'; --- rst_regs_comb <= '1'; --- else --- loadNextState <= LIDLE; --- end if; --- when INIT => --- state2 <= x"1"; --- loadNextState <= REMOVE; --- rem_phase_comb <= '1'; --- when REMOVE => --- state2 <= x"2"; --- if( remove_done = '1' ) then --- -- gk 06.10.10 --- if (MULT_EVT_ENABLE_IN = '1') then --- if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then --- --loadNextState <= WAIT_TO_REMOVE; --- -- gk 07.12.10 --- if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet --- loadNextState <= WAIT_PC; --- else --- loadNextState <= WAIT_TO_REMOVE; --- end if; --- --- else --- loadNextState <= WAIT_PC; --- end if; --- else --- loadNextState <= WAIT_TO_REMOVE; --- end if; --- inc_trg_ctr_comb <= '1'; --- else --- loadNextState <= REMOVE; --- rem_phase_comb <= '1'; --- end if; --- when WAIT_TO_REMOVE => --- if (rem_ctr = x"a") then --- loadNextState <= DECIDE; --- else --- loadNextState <= WAIT_TO_REMOVE; --- end if; --- when DECIDE => --- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_large_comb <= '1'; --- elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10 --- loadNextState <= CALCA; --- found_empty_evt_comb <= '1'; --- elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_small_comb <= '1'; --- elsif (pc_trig_nr + x"1" /= first_run_trg) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_headers_comb <= '1'; --- elsif (endpoint_addr /= first_run_addr) then --- loadNextState <= PAUSE_BEFORE_DROP1; --- drop_headers_comb <= '1'; --- else --- loadNextState <= CALCA; --- end if; --- calc_pad_comb <= '1'; --- when CALCA => --- state2 <= x"3"; --- loadNextState <= CALCB; --- pc_sos_comb <= '1'; --- when CALCB => --- -- we need a branch in case of length "0"!!!! --- state2 <= x"4"; --- loadNextState <= LOAD; --- data_phase_comb <= '1'; --- when LOAD => --- state2 <= x"5"; --- if (load_eod = '1') then --- loadNextState <= LOAD_SUBSUB; --- else --- loadNextState <= LOAD; --- data_phase_comb <= '1'; --- end if; --- -- gk 31.03.10 --- when LOAD_SUBSUB => --- state2 <= x"d"; --- if( load_sub_done = '1' ) then --- if( padding_needed = '0' ) then --- loadNextState <= CALCC; --- else --- loadNextState <= PAD0; --- pad_phase_comb <= '1'; --- end if; --- else --- loadNextState <= LOAD_SUBSUB; --- load_sub_comb <= '1'; --- end if; --- when PAD0 => --- state2 <= x"6"; --- loadNextState <= PAD1; --- pad_phase_comb <= '1'; --- pad_data_comb <= '1'; --- when PAD1 => --- state2 <= x"7"; --- loadNextState <= PAD2; --- pad_phase_comb <= '1'; --- pad_data_comb <= '1'; --- when PAD2 => --- state2 <= x"8"; --- loadNextState <= PAD3; --- pad_phase_comb <= '1'; --- pad_data_comb <= '1'; --- when PAD3 => --- state2 <= x"9"; --- loadNextState <= CALCC; --- pad_data_comb <= '1'; --- when CALCC => --- state2 <= x"a"; --- if (MULT_EVT_ENABLE_IN = '1') then --- loadNextState <= LIDLE; --- else --- loadNextState <= CLOSE; --- end if; --- pc_eod_comb <= '1'; --- when CLOSE => --- state2 <= x"b"; --- loadNextState <= WAIT_PC; --- --rst_regs_comb <= '1'; -- gk 07.10.10 --- when WAIT_PC => --- state2 <= x"c"; --- if( PC_READY_IN = '1' ) then --- -- gk 06.10.10 --- if (MULT_EVT_ENABLE_IN = '1') then --- loadNextState <= WAIT_TO_REMOVE; --- else --- loadNextState <= LIDLE; --- end if; --- else --- loadNextState <= WAIT_PC; --- end if; --- when PAUSE_BEFORE_DROP1 => --- loadNextState <= PAUSE_BEFORE_DROP2; --- pc_sos_comb <= '1'; --- when PAUSE_BEFORE_DROP2 => --- loadNextState <= DROP; --- drop_event_comb <= '1'; --- -- gk 23.07.10 --- when DROP => --- state2 <= x"e"; --- -- when data is dropped the eod marker stands as its end --- if (load_eod = '1') then --- loadNextState <= DROP_SUBSUB; --- else --- loadNextState <= DROP; --- drop_event_comb <= '1'; --- end if; --- -- gk 25.07.10 --- when DROP_SUBSUB => --- if (load_sub_done = '1') then --- if( padding_needed = '0' ) then --- loadNextState <= CALCC; --- else --- loadNextState <= PAD0; --- pad_phase_comb <= '1'; --- end if; --- else --- loadNextState <= DROP_SUBSUB; --- drop_sub_comb <= '1'; --- end if; --- when others => --- state2 <= x"f"; --- loadNextState <= LIDLE; --- end case; --- end process loadMachine; --- --- -- gk 07.10.10 --- PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0'; --- --- -- gk 25.07.10 --- INVALID_STATS_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- dropped_lr_events_ctr <= (others => '0'); --- dropped_sm_events_ctr <= (others => '0'); --- headers_invalid_ctr <= (others => '0'); --- dropped_ctr <= (others => '0'); --- invalid_hsize_ctr <= (others => '0'); --- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10 --- elsif (rst_regs = '1') then --- invalid_hsize_lock <= '0'; --- elsif (drop_small = '1') then --- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (drop_large = '1') then --- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (drop_headers = '1') then --- headers_invalid_ctr <= headers_invalid_ctr + x"1"; --- dropped_ctr <= dropped_ctr + x"1"; --- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ?? --- invalid_hsize_ctr <= invalid_hsize_ctr + x"1"; --- invalid_hsize_lock <= '1'; --- -- gk 01.10.10 --- elsif (found_empty_evt = '1') then --- found_empty_evt_ctr <= found_empty_evt_ctr + x"1"; --- end if; --- end if; --- end process INVALID_STATS_PROC; --- --- -- gk 05.08.10 --- INVALID_H_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- load_eod_q <= load_eod; --- read_size_q <= read_size; --- end if; --- end process INVALID_H_PROC; --- --- -- gk 26.04.10 --- READOUT_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then --- readout_ctr <= READOUT_CTR_IN; --- readout_ctr_lock <= '0'; --- elsif (pc_sos = '1') then --- readout_ctr <= readout_ctr + x"1"; --- end if; --- end if; --- end process READOUT_CTR_PROC; - ---****** --- SELECTION OF EVENT BUILDER ---****** - --- gk 27.03.10 -bank_select_proc : process( CLK ) -begin - if rising_edge( CLK ) then - -- gk 29.03.10 - if( (RESET = '1') or (rst_regs = '1') ) then - bank_select <= "0000"; - -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then - bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0); - end if; - end if; -end process bank_select_proc; - --- gk 07.12.10 -first_event_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - first_event <= '1'; - elsif (remove_done = '1') then - first_event <= '0'; - end if; - end if; -end process first_event_proc; - --- gk 07.12.10 -prev_bank_proc : process(CLK) -begin - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - prev_bank_select <= "0000"; - elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then - prev_bank_select <= bank_select; - end if; -end process prev_bank_proc; - - --- gk 29.03.10 -start_config_proc : process( CLK ) -begin - if rising_edge( CLK ) then - if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then - start_config <= '0'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1') ) then -- gk 01.06.10 - start_config <= '1'; - end if; - end if; -end process start_config_proc; - - ---****** --- LOAD SUBSUBEVENT ---****** - --- gk 30.03.10 --- load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') ) --- else '0'; --- --- -- gk 30.03.10 --- LOAD_SUB_CTR_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 --- load_sub_ctr <= (others => '0'); --- elsif( (load_sub_ctr_comb = '1') ) then --- load_sub_ctr <= load_sub_ctr + 1; --- end if; --- end if; --- end process LOAD_SUB_CTR_PROC; --- --- -- gk 30.03.10 --- -- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or --- -- ((load_sub_ctr = x"4") and (drop_sub = '1')) --- -- else '0'; --- load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0'; --- --- -- gk 30.03.10 --- LOAD_SUB_DONE_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 --- load_sub_done <= '0'; --- else --- load_sub_done <= load_sub_done_comb; --- end if; --- end if; --- end process LOAD_SUB_DONE_PROC; --- --- --****** --- -- EXTRACT EVENT HEADERS FROM SPLITFIFO --- --****** --- --- -- Counter for stripping the unneeded parts of the data stream, and saving the important parts --- THE_REMOVE_CTR: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then --- rem_ctr <= (others => '0'); --- elsif( (ce_rem_ctr = '1') ) then --- rem_ctr <= rem_ctr + 1; --- end if; --- end if; --- end process THE_REMOVE_CTR; --- --- remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address --- --- THE_REM_DONE_SYNC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_rem_ctr = '1') ) then --- remove_done <= '0'; --- else --- remove_done <= remove_done_comb; --- end if; --- end if; --- end process THE_REM_DONE_SYNC; --- --- -- gk 26.04.10 --- TRIG_RANDOM_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if ((RESET = '1') or (rst_regs = '1')) then --- trig_random <= (others => '0'); --- elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then --- trig_random <= pc_data; --- end if; --- end if; --- end process TRIG_RANDOM_PROC; --- --- -- extract the trigger number from splitfifo data --- THE_TRG_NR_PROC: process( CLK ) --- begin --- if rising_edge(CLK) then --- if ( (RESET = '1') or (rst_regs = '1') ) then --- pc_trig_nr <= (others => '0'); --- elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10 --- pc_trig_nr(7 downto 0) <= pc_data; --- elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10 --- pc_trig_nr(15 downto 8) <= pc_data; --- end if; --- end if; --- end process THE_TRG_NR_PROC; --- --- -- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, --- -- and in case of padding needed increase it accordingly --- THE_SUB_SIZE_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_regs = '1') ) then --- pc_sub_size <= (others => '0'); --- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 --- pc_sub_size(9 downto 2) <= pc_data; --- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 --- pc_sub_size(17 downto 10) <= pc_data; --- -- gk 20.07.10 --- -- gk 30.03.10 bug fixed in the way that is written below --- -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save --- elsif( (calc_pad = '1') and (padding_needed = '1') ) then --- pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!! --- elsif( (calc_pad = '1') and (padding_needed = '0') ) then --- pc_sub_size <= pc_sub_size + x"8"; --- end if; --- end if; --- end process THE_SUB_SIZE_PROC; --- --- -- gk 06.10.10 --- MESSAGE_SIZE_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- -- if (RESET = '1') then --- -- message_size <= (others => '0'); --- -- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then --- -- message_size <= (others => '0'); --- -- elsif (pc_sos = '1') then --- -- message_size <= message_size + pc_sub_size; --- -- end if; --- if (RESET = '1') then --- message_size <= x"0000_0028"; --- elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then --- message_size <= x"0000_0028"; --- elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then --- message_size <= x"0000_0028"; --- elsif (pc_sos = '1') then --- message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers --- end if; --- end if; --- end process MESSAGE_SIZE_PROC; --- --- --- -- gk 25.07.10 --- ENDP_ADDRESS_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (rst_regs = '1') then --- endpoint_addr <= (others => '0'); --- endp_addr_lock <= '0'; --- elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then --- endpoint_addr(7 downto 0) <= pc_data; --- endp_addr_lock <= '1'; --- elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then --- endpoint_addr(15 downto 8) <= pc_data; --- endp_addr_lock <= '0'; --- end if; --- end if; --- end process ENDP_ADDRESS_PROC; --- --- --- --- -- check for padding --- THE_PADDING_NEEDED_PROC: process( CLK ) --- begin --- if rising_edge(CLK) then --- if ( (RESET = '1') or (rst_regs = '1') ) then --- padding_needed <= '0'; --- elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then --- padding_needed <= '1'; --- elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then --- padding_needed <= '0'; --- end if; --- end if; --- end process THE_PADDING_NEEDED_PROC; --- --- -- number of bytes to read from split fifo --- THE_READ_SIZE_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then --- read_size <= (others => '0'); --- elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 --- read_size(9 downto 2) <= pc_data; --- elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 --- read_size(17 downto 10) <= pc_data; --- elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then --- read_size <= read_size - 1; --- -- gk 25.07.10 --- elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then --- read_size <= read_size - 1; --- end if; --- end if; --- end process THE_READ_SIZE_PROC; --- --- read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2" --- --- --****** --- -- EVENTS COUNTERS --- --****** --- --- -- gk 25.07.10 --- LOADED_EVT_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- loaded_events_ctr <= (others => '0'); --- elsif (remove_done = '1') then --- loaded_events_ctr <= loaded_events_ctr + x"1"; --- end if; --- end if; --- end process LOADED_EVT_CTR_PROC; --- --- -- gk 25.07.10 --- CONSTR_EVENTS_CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- constr_events_ctr <= (others => '0'); --- elsif (pc_eod = '1') then --- constr_events_ctr <= constr_events_ctr + x"1"; --- end if; --- end if; --- end process CONSTR_EVENTS_CTR_PROC; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Debug signals --- debug(0) <= sf_full; --- debug(1) <= sf_empty; --- debug(2) <= sf_afull; --- debug(3) <= sf_aempty; --- --- debug(7 downto 4) <= state2; --- --- debug(11 downto 8) <= state; --- --- dbg_bs_proc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(15 downto 12) <= (others => '0'); --- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then --- debug(15 downto 12) <= bank_select; --- end if; --- end if; --- end process dbg_bs_proc; --- --- debug(16) <= config_done; --- debug(17) <= '0'; --remove_done; --- debug(18) <= read_done; --- debug(19) <= padding_needed; --- --- debug(20) <= load_sub_done; --- --- dbg_cts_inf_proc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(39 downto 32) <= (others => '0'); --- elsif ( save_addr = '1' ) then --- debug(39 downto 32) <= CTS_INFORMATION_IN; --- end if; --- end if; --- end process dbg_cts_inf_proc; --- --- debug(47 downto 40) <= (others => '0'); --- --- --- debug(63 downto 48) <= actual_message_size(15 downto 0); --- --- dbg_pc_sub_size_proc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(81 downto 64) <= (others => '0'); --- elsif (loadCurrentState = DECIDE) then --- debug(81 downto 64) <= pc_sub_size; --- end if; --- end if; --- end process dbg_pc_sub_size_proc; --- --- dbg_empty_proc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') or (rst_regs = '1') then --- debug(84 downto 82) <= (others => '0'); --- elsif (read_size = 2) then --- debug(82) <= sf_empty; --- elsif (read_size = 1) then --- debug(83) <= sf_empty; --- elsif (read_size = 0) then --- debug(84) <= sf_empty; --- end if; --- end if; --- end process dbg_empty_proc; --- --- debug(95 downto 85) <= (others => '0'); --- --- dbg_inc_ctr_proc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- debug(127 downto 96) <= (others => '1'); --- elsif (saveCurrentState = SCLOSE) then --- debug(127 downto 96) <= inc_data_ctr; --- end if; --- end if; --- end process dbg_inc_ctr_proc; --- --- debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0); --- debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0); --- --- debug(175 downto 160) <= headers_invalid_ctr(15 downto 0); --- debug(191 downto 176) <= (others => '0'); --- --- dbg_cts_q_proc : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- cts_len_q <= (others => '0'); --- cts_rnd_q <= (others => '0'); --- cts_trg_q <= (others => '0'); --- cts_addr_q <= (others => '0'); --- elsif (cts_len_saved = '1') then --- cts_len_q <= cts_len(16 downto 1); --- cts_addr_q <= cts_addr; --- cts_rnd_q <= cts_rnd; --- cts_trg_q <= cts_trg; --- end if; --- end if; --- end process dbg_cts_q_proc; --- --- debug(207 downto 192) <= cts_trg_q; --- debug(223 downto 208) <= cts_rnd_q; --- debug(239 downto 224) <= cts_addr_q; --- debug(255 downto 240) <= cts_len_q; --- debug(271 downto 256) <= first_run_trg; --- debug(287 downto 272) <= first_run_addr; --- --- debug(303 downto 288) <= saved_events_ctr; --- debug(319 downto 304) <= loaded_events_ctr; --- --- debug(335 downto 320) <= constr_events_ctr(15 downto 0); --- debug(351 downto 336) <= dropped_ctr(15 downto 0); --- --- debug(367 downto 352) <= invalid_hsize_ctr; --- debug(383 downto 368) <= (others => '0'); --- --- MONITOR_OUT(31 downto 0) <= constr_events_ctr; --- MONITOR_OUT(63 downto 32) <= dropped_ctr; --- MONITOR_OUT(95 downto 64) <= headers_invalid_ctr; --- MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr; --- MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr; --- MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000"; --- MONITOR_OUT(191 downto 164) <= (others => '0'); --- MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10 - --- Outputs -FEE_READ_OUT <= fee_read; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; -CTS_DATA_OUT <= cts_data; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_LENGTH_OUT <= cts_length; - -PC_SOS_OUT <= pc_sos; -PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1')) - or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) - -- gk 07.12.10 - or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) - else '0'; -- gk 07.10.10 -PC_DATA_OUT <= pc_data_q; -PC_WR_EN_OUT <= pc_wr_en_qq; - -PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random; - -PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; -PC_PADDING_OUT <= padding_needed; - -DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd b/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd deleted file mode 100755 index 7624a16..0000000 --- a/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd +++ /dev/null @@ -1,236 +0,0 @@ --- LinkStateMachine for SFPs (GigE) - --- Still missing: link reset features, fifo full error handling, signals on stat_op --- Take care: all input signals must be synchronous to SYSCLK, --- all output signals are synchronous to SYSCLK. --- Clock Domain Crossing is in your responsibility! - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; ---use work.trb_net_std.all; - -entity trb_net16_lsm_sfp_gbe is -port( SYSCLK : in std_logic; -- fabric clock (100MHz) - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available - -- status signals - SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) - SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) - SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) - SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) - -- control signals - FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset - LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset - USER_RESET_OUT : out std_logic; -- FPGA reset for user logic - -- debug signals - TIMING_CTR_OUT : out std_logic_vector(18 downto 0); - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture lsm_sfp_gbe of trb_net16_lsm_sfp_gbe is - --- state machine signals -type STATES is ( QRST, SLEEP, DELAY, USERRST, LINK ); -signal CURRENT_STATE, NEXT_STATE: STATES; - -signal state_bits : std_logic_vector(3 downto 0); -signal next_ce_tctr : std_logic; -signal ce_tctr : std_logic; -signal next_rst_tctr : std_logic; -signal rst_tctr : std_logic; -signal next_quad_rst : std_logic; -signal quad_rst : std_logic; -signal next_lane_rst : std_logic; -signal lane_rst : std_logic; -signal next_user_rst : std_logic; -signal user_rst : std_logic; -signal sfp_missing_q : std_logic; -signal sfp_missing_qq : std_logic; -signal sfp_los_q : std_logic; -signal sfp_los_qq : std_logic; -signal sd_rxclk_bad_q : std_logic; -signal sd_rxclk_bad_qq : std_logic; -signal sd_rxclk_bad_qqq : std_logic; -signal sd_txclk_bad_q : std_logic; -signal sd_txclk_bad_qq : std_logic; -signal sd_txclk_bad_qqq : std_logic; -signal sd_rxclk_warn_comb : std_logic; -signal sd_rxclk_warn : std_logic; -- rising edge on rlol detected -signal sd_txclk_warn_comb : std_logic; -signal sd_txclk_warn : std_logic; -- rising edge on plol detected -signal timing_ctr : std_logic_vector(18 downto 0); -signal debug : std_logic_vector(31 downto 0); - -begin - --- Debug signals -debug(31 downto 4) <= (others => '0'); -debug(3) <= sd_txclk_warn; -debug(2) <= sd_rxclk_warn; -debug(1) <= rst_tctr; -debug(0) <= ce_tctr; - --- synchronize external signals from SFP -THE_SYNC_PROC: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - -- SFP input signals - sfp_missing_qq <= sfp_missing_q; - sfp_missing_q <= sfp_missing_in; - sfp_los_qq <= sfp_los_q; - sfp_los_q <= sfp_los_in; - -- SerDes input signals - sd_rxclk_bad_qqq <= sd_rxclk_bad_qq; - sd_rxclk_bad_qq <= sd_rxclk_bad_q; - sd_rxclk_bad_q <= sd_rxclk_bad_in; - sd_txclk_bad_qqq <= sd_txclk_bad_q; - sd_txclk_bad_qq <= sd_txclk_bad_q; - sd_txclk_bad_q <= sd_txclk_bad_in; - -- edge detectors - sd_rxclk_warn <= sd_rxclk_warn_comb; - sd_txclk_warn <= sd_txclk_warn_comb; - end if; -end process THE_SYNC_PROC; - --- combinatorial part of edge detectors (rlol, see remark on page 8-63 in HB1003.pdf) -sd_rxclk_warn_comb <= '1' when ( (sd_rxclk_bad_qqq = '0') and (sd_rxclk_bad_qq = '1') ) else '0'; -sd_txclk_warn_comb <= '1' when ( (sd_txclk_bad_qqq = '0') and (sd_txclk_bad_qq = '1') ) else '0'; - --------------------------------------------------------------------------- --- Main control state machine, startup control for SFP --------------------------------------------------------------------------- - --- Timing counter for reset sequencing -THE_TIMING_COUNTER_PROC: process( sysclk, clear ) -begin - if( clear = '1' ) then - timing_ctr <= (others => '0'); - elsif( rising_edge(sysclk) ) then - if ( (rst_tctr = '1') or (sd_rxclk_warn = '1') or (sd_txclk_warn = '1') ) then - timing_ctr <= (others => '0'); - elsif( ce_tctr = '1' ) then - timing_ctr <= timing_ctr + 1; - end if; - end if; -end process THE_TIMING_COUNTER_PROC; - --- State machine --- state registers -STATE_MEM: process( sysclk, clear ) -begin - if( clear = '1' ) then - CURRENT_STATE <= QRST; - ce_tctr <= '0'; - rst_tctr <= '0'; - quad_rst <= '1'; - lane_rst <= '1'; - user_rst <= '1'; - elsif( rising_edge(sysclk) ) then - CURRENT_STATE <= NEXT_STATE; - ce_tctr <= next_ce_tctr; - rst_tctr <= next_rst_tctr; - quad_rst <= next_quad_rst; - lane_rst <= next_lane_rst; - user_rst <= next_user_rst; - end if; -end process STATE_MEM; - --- state transitions -PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_missing_qq, sfp_los_qq, sd_txclk_bad_qqq, sd_rxclk_bad_qqq, - timing_ctr(8), timing_ctr(18), timing_ctr(17), - reset ) -begin - NEXT_STATE <= QRST; -- avoid latches - next_ce_tctr <= '0'; - next_rst_tctr <= '0'; - next_quad_rst <= '0'; - next_lane_rst <= '0'; - next_user_rst <= '0'; - case CURRENT_STATE is - when QRST => -- initial state, we stay there unless CLEAR is deasserted. - state_bits <= x"0"; - if( (timing_ctr(8) = '1') ) then - NEXT_STATE <= SLEEP; -- release QUAD_RST, wait for lock of RxClock and TxClock - next_lane_rst <= '1'; - next_user_rst <= '1'; - next_rst_tctr <= '1'; - else - NEXT_STATE <= QRST; -- count delay - next_ce_tctr <= '1'; - next_quad_rst <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; - when SLEEP => -- we check for SFP presence and signal - state_bits <= x"1"; - if( (sfp_missing_qq = '0') and (sfp_los_qq = '0') ) then - NEXT_STATE <= DELAY; -- do a correctly timed QUAD reset (about 150ns) - next_ce_tctr <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - else - NEXT_STATE <= SLEEP; -- wait for SFP present signal - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; - when DELAY => -- we wait approx. 4ms and check for PLL lock in the SerDes - state_bits <= x"2"; - if( (timing_ctr(18) = '1') and (timing_ctr(17) = '1') and (sd_rxclk_bad_qqq = '0') and (sd_txclk_bad_qqq = '0') ) then - NEXT_STATE <= USERRST; -- we release lane reset - next_ce_tctr <= '1'; - next_user_rst <= '1'; - else - NEXT_STATE <= DELAY; - next_ce_tctr <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; - when USERRST => -- short delay for user reset - state_bits <= x"3"; - if( (timing_ctr(18) = '0') and (timing_ctr(17) = '0') ) then - NEXT_STATE <= LINK; - next_rst_tctr <= '1'; - else - NEXT_STATE <= USERRST; - next_ce_tctr <= '1'; - next_user_rst <= '1'; - end if; - when LINK => -- operational - state_bits <= x"4"; - NEXT_STATE <= LINK; - when others => - NEXT_STATE <= QRST; - end case; - - -- emergency jumps in case of SFP problems - if( ((sfp_missing_qq = '1') or (sfp_los_qq = '1') or (RESET = '1')) and CURRENT_STATE /= QRST ) then - NEXT_STATE <= SLEEP; -- wait for SFP present signal - next_rst_tctr <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; -end process; - --------------------------------------------------------------------------- --- Output signals --------------------------------------------------------------------------- -full_reset_out <= quad_rst; -lane_reset_out <= lane_rst; -user_reset_out <= user_rst; - --------------------------------------------------------------------------- --- Debug output --------------------------------------------------------------------------- -timing_ctr_out <= timing_ctr; -bsm_out <= state_bits; -debug_out <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd b/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd deleted file mode 100755 index 13141e6..0000000 --- a/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd +++ /dev/null @@ -1,890 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; - -use work.trb_net_gbe_components.all; - -entity trb_net16_med_ecp_sfp_gbe_8b is --- gk 28.04.10 -generic ( - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 -); -port( - RESET : in std_logic; - GSR_N : in std_logic; - CLK_125_OUT : out std_logic; - CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk - CLK_125_RX_OUT : out std_logic; - --SGMII connection to frame transmitter (tsmac) - FT_TX_CLK_EN_OUT : out std_logic; - FT_RX_CLK_EN_OUT : out std_logic; - FT_COL_OUT : out std_logic; - FT_CRS_OUT : out std_logic; - FT_TXD_IN : in std_logic_vector(7 downto 0); - FT_TX_EN_IN : in std_logic; - FT_TX_ER_IN : in std_logic; - - FT_RXD_OUT : out std_logic_vector(7 downto 0); - FT_RX_EN_OUT : out std_logic; - FT_RX_ER_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable - -- Autonegotiation stuff - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); -- should be x"0020 - MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); -- advert page from link partner - MR_AN_PAGE_RX_OUT : out std_logic; - MR_AN_COMPLETE_OUT : out std_logic; - MR_AN_ENABLE_IN : in std_logic; - MR_RESTART_AN_IN : in std_logic; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) -); -end entity; - -architecture trb_net16_med_ecp_sfp_gbe_8b of trb_net16_med_ecp_sfp_gbe_8b is - --- Placer Directives ---attribute HGROUP : string; --- for whole architecture ---attribute HGROUP of trb_net16_med_ecp_sfp_gbe_8b : architecture is "media_interface_group"; -attribute syn_sharing : string; -attribute syn_sharing of trb_net16_med_ecp_sfp_gbe_8b : architecture is "off"; - ---component serdes_gbe_0ch is -component serdes_ch4 is - --GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0ch.txt"); -GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (7 downto 0); - tx_k_ch3 : in std_logic; - xmit_ch3 : in std_logic; - tx_disp_correct_ch3 : in std_logic; - rxdata_ch3 : out std_logic_vector (7 downto 0); - rx_k_ch3 : out std_logic; - rx_disp_err_ch3 : out std_logic; - rx_cv_err_ch3 : out std_logic; - rx_serdes_rst_ch3_c : in std_logic; - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pcs_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pcs_rst_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - -component serdes_gbe_0_extclock_8b is -GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"); -port( refclkp : in std_logic; - refclkn : in std_logic; - hdinp0 : in std_logic; - hdinn0 : in std_logic; - hdoutp0 : out std_logic; - hdoutn0 : out std_logic; - ff_rxiclk_ch0 : in std_logic; - ff_txiclk_ch0 : in std_logic; - ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0 : out std_logic; - ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - refck2core : out std_logic; - ffs_plol : out std_logic - ); -end component; - -component serdes_gbe_0_intclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); - port ( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - ffs_plol : out std_logic); - -end component; - --- component sgmii_gbe_pcs34 --- port( rst_n : in std_logic; --- signal_detect : in std_logic; --- gbe_mode : in std_logic; --- sgmii_mode : in std_logic; --- operational_rate : in std_logic_vector(1 downto 0); --- debug_link_timer_short : in std_logic; --- rx_compensation_err : out std_logic; --- tx_clk_125 : in std_logic; --- tx_clock_enable_source : out std_logic; --- tx_clock_enable_sink : in std_logic; --- tx_d : in std_logic_vector(7 downto 0); --- tx_en : in std_logic; --- tx_er : in std_logic; --- rx_clk_125 : in std_logic; --- rx_clock_enable_source : out std_logic; --- rx_clock_enable_sink : in std_logic; --- rx_d : out std_logic_vector(7 downto 0); --- rx_dv : out std_logic; --- rx_er : out std_logic; --- col : out std_logic; --- crs : out std_logic; --- tx_data : out std_logic_vector(7 downto 0); --- tx_kcntl : out std_logic; --- tx_disparity_cntl : out std_logic; --- serdes_recovered_clk : in std_logic; --- rx_data : in std_logic_vector(7 downto 0); --- rx_even : in std_logic; --- rx_kcntl : in std_logic; --- rx_disp_err : in std_logic; --- rx_cv_err : in std_logic; --- rx_err_decode_mode : in std_logic; --- mr_an_complete : out std_logic; --- mr_page_rx : out std_logic; --- mr_lp_adv_ability : out std_logic_vector(15 downto 0); --- mr_main_reset : in std_logic; --- mr_an_enable : in std_logic; --- mr_restart_an : in std_logic; --- mr_adv_ability : in std_logic_vector(15 downto 0) --- ); --- end component; - -component sgmii_gbe_pcs35 --sgmii_gbe_pcs36 -- sgmii_gbe_pcs35 -port( rst_n : in std_logic; - signal_detect : in std_logic; - gbe_mode : in std_logic; - sgmii_mode : in std_logic; - operational_rate : in std_logic_vector(1 downto 0); - debug_link_timer_short : in std_logic; - - force_isolate : in std_logic; - force_loopback : in std_logic; - force_unidir : in std_logic; - - rx_compensation_err : out std_logic; - - ctc_drop_flag : out std_logic; - ctc_add_flag : out std_logic; - an_link_ok : out std_logic; - - tx_clk_125 : in std_logic; - tx_clock_enable_source : out std_logic; - tx_clock_enable_sink : in std_logic; - tx_d : in std_logic_vector(7 downto 0); - tx_en : in std_logic; - tx_er : in std_logic; - rx_clk_125 : in std_logic; - rx_clock_enable_source : out std_logic; - rx_clock_enable_sink : in std_logic; - rx_d : out std_logic_vector(7 downto 0); - rx_dv : out std_logic; - rx_er : out std_logic; - col : out std_logic; - crs : out std_logic; - tx_data : out std_logic_vector(7 downto 0); - tx_kcntl : out std_logic; - tx_disparity_cntl : out std_logic; - - xmit_autoneg : out std_logic; - - serdes_recovered_clk : in std_logic; - rx_data : in std_logic_vector(7 downto 0); - rx_even : in std_logic; - rx_kcntl : in std_logic; - rx_disp_err : in std_logic; - rx_cv_err : in std_logic; - rx_err_decode_mode : in std_logic; - mr_an_complete : out std_logic; - mr_page_rx : out std_logic; - mr_lp_adv_ability : out std_logic_vector(15 downto 0); - mr_main_reset : in std_logic; - mr_an_enable : in std_logic; - mr_restart_an : in std_logic; - mr_adv_ability : in std_logic_vector(15 downto 0) - ); -end component; - -component trb_net16_lsm_sfp_gbe is -port( SYSCLK : in std_logic; -- fabric clock (100MHz) - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available - -- status signals - SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) - SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) - SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) - SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) - -- control signals - FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset - LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset - USER_RESET_OUT : out std_logic; -- FPGA reset for user logic - -- debug signals - TIMING_CTR_OUT : out std_logic_vector(18 downto 0); - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); -end component; - -component reset_controller_pcs port ( - rst_n : in std_logic; - clk : in std_logic; - tx_plol : in std_logic; - rx_cdr_lol : in std_logic; - quad_rst_out : out std_logic; - tx_pcs_rst_out : out std_logic; - rx_pcs_rst_out : out std_logic - ); -end component; -component reset_controller_cdr port ( - rst_n : in std_logic; - clk : in std_logic; - cdr_lol : in std_logic; - cdr_rst_out : out std_logic - ); -end component; - -component rate_resolution port ( - gbe_mode : in std_logic; - sgmii_mode : in std_logic; - an_enable : in std_logic; - advertised_rate : in std_logic_vector(1 downto 0); - link_partner_rate : in std_logic_vector(1 downto 0); - non_an_rate : in std_logic_vector(1 downto 0); - operational_rate : out std_logic_vector(1 downto 0) - ); -end component; - -component register_interface_hb port ( - rst_n : in std_logic; - hclk : in std_logic; - gbe_mode : in std_logic; - sgmii_mode : in std_logic; - hcs_n : in std_logic; - hwrite_n : in std_logic; - haddr : in std_logic_vector(3 downto 0); - hdatain : in std_logic_vector(7 downto 0); - hdataout : out std_logic_vector(7 downto 0); - hready_n : out std_logic; - mr_an_complete : in std_logic; - mr_page_rx : in std_logic; - mr_lp_adv_ability : in std_logic_vector(15 downto 0); - mr_main_reset : out std_logic; - mr_an_enable : out std_logic; - mr_restart_an : out std_logic; - mr_adv_ability : out std_logic_vector(15 downto 0) - ); -end component; - -component sgmii33 port ( - rst_n : in std_logic; - signal_detect : in std_logic; - gbe_mode : in std_logic; - sgmii_mode : in std_logic; - --force_isolate : in std_logic; - --force_loopback : in std_logic; - --force_unidir : in std_logic; - operational_rate : in std_logic_vector(1 downto 0); - debug_link_timer_short : in std_logic; - rx_compensation_err : out std_logic; - --ctc_drop_flag : out std_logic; - --ctc_add_flag : out std_logic; - --an_link_ok : out std_logic; - tx_clk_125 : in std_logic; - tx_clock_enable_source : out std_logic; - tx_clock_enable_sink : in std_logic; - tx_d : in std_logic_vector(7 downto 0); - tx_en : in std_logic; - tx_er : in std_logic; - rx_clk_125 : in std_logic; - rx_clock_enable_source : out std_logic; - rx_clock_enable_sink : in std_logic; - rx_d : out std_logic_vector(7 downto 0); - rx_dv : out std_logic; - rx_er : out std_logic; - col : out std_logic; - crs : out std_logic; - tx_data : out std_logic_vector(7 downto 0); - tx_kcntl : out std_logic; - tx_disparity_cntl : out std_logic; - --xmit_autoneg : out std_logic; - serdes_recovered_clk : in std_logic; - rx_data : in std_logic_vector(7 downto 0); - rx_even : in std_logic; - rx_kcntl : in std_logic; - rx_disp_err : in std_logic; - rx_cv_err : in std_logic; - rx_err_decode_mode : in std_logic; - mr_an_complete : out std_logic; - mr_page_rx : out std_logic; - mr_lp_adv_ability : out std_logic_vector(15 downto 0); - mr_main_reset : in std_logic; - mr_an_enable : in std_logic; - mr_restart_an : in std_logic; - mr_adv_ability : in std_logic_vector(15 downto 0) - ); -end component; - - -signal refclkcore : std_logic; - -signal sd_link_ok : std_logic; -signal sd_link_error : std_logic_vector(2 downto 0); - -signal sd_tx_data : std_logic_vector(7 downto 0); -signal sd_tx_kcntl : std_logic; -signal sd_tx_correct_disp : std_logic; -signal sd_tx_clk : std_logic; - -signal sd_rx_data : std_logic_vector(7 downto 0); -signal sd_rx_even : std_logic; -signal sd_rx_kcntl : std_logic; -signal sd_rx_disp_error : std_logic; -signal sd_rx_cv_error : std_logic; -signal sd_rx_clk : std_logic; - -signal sd_tx_data_q : std_logic_vector(7 downto 0); -signal sd_tx_kcntl_q : std_logic; -signal sd_tx_correct_disp_q : std_logic; - -signal sd_rx_data_q : std_logic_vector(7 downto 0); -signal sd_rx_kcntl_q : std_logic; -signal sd_rx_disp_error_q : std_logic; -signal sd_rx_cv_error_q : std_logic; - -signal pcs_mr_an_complete : std_logic; -signal pcs_mr_ability : std_logic_vector(15 downto 0); -signal pcs_mr_page_rx : std_logic; -signal pcs_mr_reset : std_logic; - -signal pcs_tx_clk_en : std_logic; -signal pcs_rx_clk_en : std_logic; -signal pcs_rx_comp_err : std_logic; - -signal pcs_rx_d : std_logic_vector(7 downto 0); -signal pcs_rx_dv : std_logic; -signal pcs_rx_er : std_logic; - -signal sd_rx_debug : std_logic_vector(15 downto 0); -signal sd_tx_debug : std_logic_vector(15 downto 0); - -signal buf_stat_debug : std_logic_vector(63 downto 0); - -signal quad_rst : std_logic; -signal lane_rst : std_logic; -signal user_rst : std_logic; - -signal reset_bsm : std_logic_vector(3 downto 0); -signal reset_debug : std_logic_vector(31 downto 0); -signal test_clk : std_logic; - -signal xmit : std_logic; -signal signal_detected, compensation_err, tx_clk_en, rx_clk_en, rst_n, an_complete : std_logic; -signal tx_pll_lol, rx_cdr_lol, los, tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic; - -signal operational_rate : std_logic_vector(1 downto 0); - -signal mr_an_enable, mr_restart_an, mr_main_reset, mr_page_rx : std_logic; -signal mr_lp_adv_ability, mr_adv_ability : std_logic_vector(15 downto 0); - - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - --attribute syn_keep of sd_tx_clk : signal is true; - --attribute syn_preserve of sd_tx_clk : signal is true; - attribute syn_keep of sd_rx_clk : signal is true; - attribute syn_preserve of sd_rx_clk : signal is true; - - attribute syn_keep of sd_tx_correct_disp_q, sd_tx_kcntl_q, sd_tx_data_q, sd_rx_data_q, sd_rx_cv_error_q, sd_rx_disp_error_q, sd_rx_kcntl_q : signal is true; - attribute syn_preserve of sd_tx_correct_disp_q, sd_tx_kcntl_q, sd_tx_data_q, sd_rx_data_q, sd_rx_cv_error_q, sd_rx_disp_error_q, sd_rx_kcntl_q : signal is true; - -begin - --- Reset state machine for SerDes --- THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe --- port map( --- SYSCLK => CLK_125_IN, --- RESET => '0', -- really? --- CLEAR => RESET, -- from 100MHz PLL, includes async part --- -- status signals --- SFP_MISSING_IN => SD_PRSNT_N_IN, --- SFP_LOS_IN => SD_LOS_IN, --- SD_LINK_OK_IN => '1', -- not used --- SD_LOS_IN => '0', -- not used --- SD_TXCLK_BAD_IN => sd_link_error(2), -- plol --- SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol --- -- control signals --- FULL_RESET_OUT => quad_rst, --- LANE_RESET_OUT => lane_rst, --- USER_RESET_OUT => user_rst, --- -- debug signals --- TIMING_CTR_OUT => open, --- BSM_OUT => reset_bsm, --- DEBUG_OUT => reset_debug --- ); - --- gk 28.04.10 --- SerDes for GbE -clk_int : if (USE_125MHZ_EXTCLK = 0) generate - - refclkcore <= CLK_125_IN; --sd_tx_clk; --CLK_125_IN; - --- SERDES_GBE : serdes_gbe_0_intclock_8b --- port map( --- core_txrefclk => CLK_125_IN, --- core_rxrefclk => CLK_125_IN, --- hdinp0 => SD_RXD_P_IN, --- hdinn0 => SD_RXD_N_IN, --- hdoutp0 => SD_TXD_P_OUT, --- hdoutn0 => SD_TXD_N_OUT, --- ff_rxiclk_ch0 => sd_rx_clk, --- ff_txiclk_ch0 => sd_tx_clk, --- ff_ebrd_clk_0 => sd_rx_clk, --- ff_txdata_ch0 => sd_tx_data, --- ff_rxdata_ch0 => sd_rx_data, --- ff_tx_k_cntrl_ch0 => sd_tx_kcntl, --- ff_rx_k_cntrl_ch0 => sd_rx_kcntl, --- ff_rxfullclk_ch0 => sd_rx_clk, --- ff_xmit_ch0 => '0', --- ff_correct_disp_ch0 => sd_tx_correct_disp, --- ff_disp_err_ch0 => sd_rx_disp_error, --- ff_cv_ch0 => sd_rx_cv_error, --- ff_rx_even_ch0 => sd_rx_even, --- ffc_rrst_ch0 => '0', --- ffc_lane_tx_rst_ch0 => lane_rst, --- ffc_lane_rx_rst_ch0 => lane_rst, --- ffc_txpwdnb_ch0 => '1', --- ffc_rxpwdnb_ch0 => '1', --- ffs_rlos_lo_ch0 => sd_link_error(0), --- ffs_ls_sync_status_ch0 => sd_link_ok, --- ffs_rlol_ch0 => sd_link_error(1), --- oob_out_ch0 => open, --- ffc_macro_rst => '0', --- ffc_quad_rst => quad_rst, --- ffc_trst => '0', --- ff_txfullclk => sd_tx_clk, --- ff_txhalfclk => open, --- ffs_plol => sd_link_error(2) --- ); - - --SERDES_GBE : serdes_gbe_0ch - SERDES_GBE : serdes_ch4 - port map( - ------------------ - -- CH0 -- - hdinp_ch3 => SD_RXD_P_IN, - hdinn_ch3 => SD_RXD_N_IN, - hdoutp_ch3 => SD_TXD_P_OUT, - hdoutn_ch3 => SD_TXD_N_OUT, - rxiclk_ch3 => sd_rx_clk, - txiclk_ch3 => CLK_125_IN, --sd_tx_clk, - rx_full_clk_ch3 => sd_rx_clk, - rx_half_clk_ch3 => open, - tx_full_clk_ch3 => open, --sd_tx_clk, - tx_half_clk_ch3 => open, - fpga_rxrefclk_ch3 => CLK_125_IN, - txdata_ch3 => sd_tx_data_q, - tx_k_ch3 => sd_tx_kcntl_q, - xmit_ch3 => xmit, --'0', - tx_disp_correct_ch3 => sd_tx_correct_disp_q, - rxdata_ch3 => sd_rx_data, - rx_k_ch3 => sd_rx_kcntl, - rx_disp_err_ch3 => sd_rx_disp_error, - rx_cv_err_ch3 => sd_rx_cv_error, - rx_serdes_rst_ch3_c => rx_serdes_rst, - sb_felb_ch3_c => '0', - sb_felb_rst_ch3_c => '0', - tx_pcs_rst_ch3_c => tx_pcs_rst, - tx_pwrup_ch3_c => '1', - rx_pcs_rst_ch3_c => rx_pcs_rst, - rx_pwrup_ch3_c => '1', - rx_los_low_ch3_s => los, - lsm_status_ch3_s => signal_detected, - rx_cdr_lol_ch3_s => rx_cdr_lol, - -- CH1 -- - -- CH2 -- - -- CH3 -- - ---- Miscillaneous ports - fpga_txrefclk => CLK_125_IN, - tx_serdes_rst_c => '0', - tx_pll_lol_qd_s => tx_pll_lol, - rst_qd_c => quad_rst, - serdes_rst_qd_c => '0' - ); - - -end generate clk_int; - -clk_ext : if (USE_125MHZ_EXTCLK = 1) generate - --SERDES_GBE : serdes_gbe_0_extclock_8b - SERDES_GBE : serdes_gbe_0_extclock_8b - port map( -- SerDes connection to outside world - refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input - refclkn => SD_REFCLK_N_IN, - hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input - hdinn0 => SD_RXD_N_IN, - hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output - hdoutn0 => SD_TXD_N_OUT, - refck2core => refclkcore, -- reference clock from input - -- RX part - ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output - ff_rxiclk_ch0 => sd_rx_clk, - ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice - ff_rxdata_ch0 => sd_rx_data, -- RX data output - ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output - ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output) - ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error - ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error - -- TX part - ff_txfullclk => sd_tx_clk, -- TX full clock output - ff_txiclk_ch0 => sd_tx_clk, - ff_txhalfclk => open, - ff_txdata_ch0 => sd_tx_data, -- TX data input - ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input - ff_xmit_ch0 => '0', -- for autonegotiation (input) - ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input) - -- Resets and power down - ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high) - ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel - ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel - ffc_rrst_ch0 => '0', -- '0' for normal operation - ffc_macro_rst => '0', -- '0' for normal operation - ffc_trst => '0', -- '0' for normal operation - ffc_txpwdnb_ch0 => '1', -- must be '1' - ffc_rxpwdnb_ch0 => '1', -- must be '1' - -- Status outputs - ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas? - ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel - ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL - ffs_plol => sd_link_error(2), -- loss of lock in TX PLL - oob_out_ch0 => open -- not needed - ); -end generate clk_ext; - ---SD_RX_DATA_PROC: process( sd_rx_clk ) ---begin --- if( rising_edge(sd_rx_clk) ) then --- sd_rx_debug(15 downto 12) <= (others => '0'); --- sd_rx_debug(11) <= sd_rx_disp_error; --- sd_rx_debug(10) <= sd_rx_even; --- sd_rx_debug(9) <= sd_rx_cv_error; --- sd_rx_debug(8) <= sd_rx_kcntl; --- sd_rx_debug(7 downto 0) <= sd_rx_data; --- end if; ---end process SD_RX_DATA_PROC; --- ---SD_TX_DATA_PROC: process( CLK_125_IN) --sd_tx_clk ) ---begin --- if( rising_edge(CLK_125_IN)) then --sd_tx_clk) ) then --- sd_tx_debug(15 downto 10) <= (others => '0'); --- sd_tx_debug(9) <= sd_tx_correct_disp; --- sd_tx_debug(8) <= sd_tx_kcntl; --- sd_tx_debug(7 downto 0) <= sd_tx_data; --- end if; ---end process SD_TX_DATA_PROC; - -buf_stat_debug(63 downto 40) <= (others => '0'); -buf_stat_debug(39 downto 36) <= reset_debug(3 downto 0); -buf_stat_debug(35 downto 32) <= reset_bsm; --- logic analyzer signals -buf_stat_debug(31) <= pcs_mr_page_rx; -buf_stat_debug(30) <= pcs_mr_reset; --pcs_mr_an_complete; -buf_stat_debug(28 downto 26) <= reset_bsm(2 downto 0); -buf_stat_debug(25 downto 23) <= sd_link_error(2 downto 0); -buf_stat_debug(22) <= sd_link_ok; -buf_stat_debug(21 downto 12) <= sd_tx_debug(9 downto 0); -buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0); - - ---SGMII_GBE_PCS : sgmii33 port map ( --- rst_n => GSR_N, --- signal_detect => signal_detected, --- gbe_mode => '1', --- sgmii_mode => '0', --- operational_rate => operational_rate, --- debug_link_timer_short => '0', --- rx_compensation_err => compensation_err, --- tx_clk_125 => CLK_125_IN, --- tx_clock_enable_source => tx_clk_en, --- tx_clock_enable_sink => tx_clk_en, --- tx_d => FT_TXD_IN, --pcs_rxd, --pcs_txd, --- tx_en => FT_TX_EN_IN, --pcs_rx_dv, --pcs_tx_en, --- tx_er => FT_TX_ER_IN, --pcs_rx_er, --pcs_tx_er, --- rx_clk_125 => CLK_125_IN, --- rx_clock_enable_source => rx_clk_en, --- rx_clock_enable_sink => rx_clk_en, --- rx_d => pcs_rx_d, --- rx_dv => pcs_rx_dv, --- rx_er => pcs_rx_er, --- col => FT_COL_OUT, --- crs => FT_CRS_OUT, --- tx_data => sd_tx_data, --- tx_kcntl => sd_tx_kcntl, --- tx_disparity_cntl => sd_tx_correct_disp, --- serdes_recovered_clk => sd_rx_clk, --- rx_data => sd_rx_data_q, --- rx_even => '0', --- rx_kcntl => sd_rx_kcntl_q, --- rx_disp_err => sd_rx_disp_error_q, --- rx_cv_err => sd_rx_cv_error_q, --- rx_err_decode_mode => '0', --- mr_an_complete => an_complete, --- mr_page_rx => mr_page_rx, --- mr_lp_adv_ability => mr_lp_adv_ability, --- mr_main_reset => mr_main_reset, --reset_i, --- mr_an_enable => '1', --'1', --- mr_restart_an => mr_restart_an, --- mr_adv_ability => mr_adv_ability --x"0020" --- ); - - SYNC_TX_PROC : process(CLK_125_IN) - begin - if rising_edge(CLK_125_IN) then - sd_tx_data_q <= sd_tx_data; - sd_tx_kcntl_q <= sd_tx_kcntl; - sd_tx_correct_disp_q <= sd_tx_correct_disp; - end if; - end process SYNC_TX_PROC; - - SYNC_RX_PROC : process(sd_rx_clk) - begin - if rising_edge(sd_rx_clk) then - sd_rx_data_q <= sd_rx_data; - sd_rx_kcntl_q <= sd_rx_kcntl; - sd_rx_disp_error_q <= sd_rx_disp_error; - sd_rx_cv_error_q <= sd_rx_cv_error; - end if; - end process SYNC_RX_PROC; - - - - - SGMII_GBE_PCS : sgmii_gbe_pcs35 --sgmii_gbe_pcs36 --sgmii_gbe_pcs35 - port map( - rst_n => rst_n, --GSR_N, - signal_detect => signal_detected, - gbe_mode => '1', - sgmii_mode => '0', - operational_rate => operational_rate, - debug_link_timer_short => '0', - - force_isolate => '0', - force_loopback => '0', - force_unidir => '0', - - rx_compensation_err => compensation_err, - - ctc_drop_flag => open, - ctc_add_flag => open, - an_link_ok => open, - - -- MAC interface - tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes - tx_clock_enable_source => tx_clk_en, - tx_clock_enable_sink => tx_clk_en, - tx_d => FT_TXD_IN, -- TX data from MAC - tx_en => FT_TX_EN_IN, -- TX data enable from MAC - tx_er => FT_TX_ER_IN, -- TX error from MAC - rx_clk_125 => sd_rx_clk, --CLK_125_IN, --refclkcore, -- original clock from SerDes - rx_clock_enable_source => rx_clk_en, - rx_clock_enable_sink => rx_clk_en, - rx_d => pcs_rx_d, -- RX data to MAC - rx_dv => pcs_rx_dv, -- RX data enable to MAC - rx_er => pcs_rx_er, -- RX error to MAC - col => FT_COL_OUT, - crs => FT_CRS_OUT, - -- SerDes interface - tx_data => sd_tx_data, -- TX data to SerDes - tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes - tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes) - - xmit_autoneg => xmit, - - serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream - rx_data => sd_rx_data_q, -- RX data from SerDes - rx_kcntl => sd_rx_kcntl_q, -- RX komma control from SerDes - rx_err_decode_mode => '0', -- receive error control mode fixed to normal - rx_even => '0', -- unused (receive error control mode = normal, tie to GND) - rx_disp_err => sd_rx_disp_error_q, -- RX disparity error from SerDes - rx_cv_err => sd_rx_cv_error_q, -- RX code violation error from SerDes - -- Autonegotiation stuff - mr_an_complete => an_complete, - mr_page_rx => mr_page_rx, - mr_lp_adv_ability => mr_lp_adv_ability, - mr_main_reset => mr_main_reset, - mr_an_enable => '1', - mr_restart_an => mr_restart_an, - mr_adv_ability => mr_adv_ability - ); - -rst_n <= not RESET; - ---SYNC_RX_PROC : process(sd_rx_clk) ---begin --- if rising_edge(sd_rx_clk) then - FT_RXD_OUT <= pcs_rx_d; - FT_RX_EN_OUT <= pcs_rx_dv; - FT_RX_ER_OUT <= pcs_rx_er; --- end if; ---end process SYNC_RX_PROC; - -u0_reset_controller_pcs : reset_controller_pcs port map( - rst_n => rst_n, - clk => CLK_125_IN, - tx_plol => tx_pll_lol, - rx_cdr_lol => rx_cdr_lol, - quad_rst_out => quad_rst, - tx_pcs_rst_out => tx_pcs_rst, - rx_pcs_rst_out => rx_pcs_rst -); - -u0_reset_controller_cdr : reset_controller_cdr port map( - rst_n => rst_n, - clk => CLK_125_IN, - cdr_lol => rx_cdr_lol, - cdr_rst_out => rx_serdes_rst -); - -u0_rate_resolution : rate_resolution port map( - gbe_mode => '1', - sgmii_mode => '0', - an_enable => '1', - advertised_rate => mr_adv_ability(11 downto 10), - link_partner_rate => mr_lp_adv_ability(11 downto 10), - non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled - - operational_rate => operational_rate -); - -u0_ri : register_interface_hb port map( - -- Control Signals - rst_n => rst_n, - hclk => CLK_125_IN, - gbe_mode => '1', - sgmii_mode => '0', - - -- Host Bus - hcs_n => '1', - hwrite_n => '1', - haddr => (others => '0'), - hdatain => (others => '0'), - - hdataout => open, - hready_n => open, - - -- Register Outputs - mr_an_enable => mr_an_enable, - mr_restart_an => mr_restart_an, - mr_main_reset => mr_main_reset, - mr_adv_ability => mr_adv_ability, - - -- Register Inputs - mr_an_complete => an_complete, - mr_page_rx => mr_page_rx, - mr_lp_adv_ability => mr_lp_adv_ability - ); - - - -pcs_mr_reset <= MR_RESET_IN or RESET or user_rst; - -FT_TX_CLK_EN_OUT <= tx_clk_en; -- to MAC -FT_RX_CLK_EN_OUT <= rx_clk_en; -- to MAC - -MR_AN_LP_ABILITY_OUT <= pcs_mr_ability; -MR_AN_COMPLETE_OUT <= an_complete; -MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx; - --- Clock games -CLK_125_OUT <= CLK_125_IN; --sd_tx_clk; -CLK_125_RX_OUT <= sd_rx_clk; - --- Fakes -STAT_OP <= (others => '0'); -SD_TXDIS_OUT <= '0'; -- enable -STAT_DEBUG <= buf_stat_debug; - -end architecture; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net_gbe_components.vhd b/gbe2_ecp3/trb_net_gbe_components.vhd deleted file mode 100644 index 42e2667..0000000 --- a/gbe2_ecp3/trb_net_gbe_components.vhd +++ /dev/null @@ -1,1360 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -library work; -use work.trb_net_std.all; - -use work.trb_net_gbe_protocols.all; - -package trb_net_gbe_components is - - - -component trb_net16_gbe_transmit_control2 is -port ( - CLK : in std_logic; - RESET : in std_logic; - --- signal to/from main controller - TC_DATAREADY_IN : in std_logic; - TC_RD_EN_OUT : out std_logic; - TC_DATA_IN : in std_logic_vector(7 downto 0); - TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - TC_DEST_MAC_IN : in std_logic_vector(47 downto 0); - TC_DEST_IP_IN : in std_logic_vector(31 downto 0); - TC_DEST_UDP_IN : in std_logic_vector(15 downto 0); - TC_SRC_MAC_IN : in std_logic_vector(47 downto 0); - TC_SRC_IP_IN : in std_logic_vector(31 downto 0); - TC_SRC_UDP_IN : in std_logic_vector(15 downto 0); - TC_IDENT_IN : in std_logic_vector(15 downto 0); - TC_TRANSMISSION_DONE_OUT : out std_logic; - TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0); - --- signal to/from frame constructor - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_WR_EN_OUT : out std_logic; - FC_READY_IN : in std_logic; - FC_H_READY_IN : in std_logic; - FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - - DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - - MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0) -); -end component; - -component trb_net16_gbe_event_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 - PC_END_OF_QUEUE_IN : in std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_INSERT_TTYPE_IN : in std_logic; - -- FrameConstructor ports - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_SOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_ipu_interface is - port ( - CLK_IPU : in std_logic; - CLK_GBE : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_SUBEVENT_SIZE_IN : in std_logic_vector(15 downto 0); - MAX_QUEUE_SIZE_IN : in std_logic_vector(15 downto 0); - MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - MAX_SINGLE_SUB_SIZE_IN : in std_logic_vector(15 downto 0); - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - -- PacketConstructor interface - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; - PC_EOQ_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0); - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) - ); -end component; - -component gbe_ipu_dummy is - generic ( - DO_SIMULATION : integer range 0 to 1 := 0; - FIXED_SIZE_MODE : integer range 0 to 1 := 1; - INCREMENTAL_MODE : integer range 0 to 1 := 0; - FIXED_SIZE : integer range 0 to 65535 := 10; - FIXED_DELAY_MODE : integer range 0 to 1 := 1; - UP_DOWN_MODE : integer range 0 to 1 := 0; - UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; - FIXED_DELAY : integer range 0 to 16777215 := 16777215 - ); - port ( - clk : in std_logic; - rst : in std_logic; - GBE_READY_IN : in std_logic; - - CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); - CTS_CODE_OUT : out std_logic_vector (7 downto 0); - CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - CTS_START_READOUT_OUT : out std_logic; - CTS_DATA_IN : in std_logic_vector (31 downto 0); - CTS_DATAREADY_IN : in std_logic; - CTS_READOUT_FINISHED_IN : in std_logic; - CTS_READ_OUT : out std_logic; - CTS_LENGTH_IN : in std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_OUT : out std_logic_vector (15 downto 0); - FEE_DATAREADY_OUT : out std_logic; - FEE_READ_IN : in std_logic; - FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - FEE_BUSY_OUT : out std_logic - ); -end component; - -component gbe_sctrl_dummy is - generic ( - DO_SIMULATION : integer range 0 to 1 := 0; - FIXED_DELAY_MODE : integer range 0 to 1 := 1; - FIXED_DELAY : integer range 0 to 65535 := 4096 - ); - port ( - clk : in std_logic; - rst : in std_logic; - - RC_RD_EN_IN : in std_logic; - RC_Q_OUT : out std_logic_vector(8 downto 0); - RC_FRAME_WAITING_OUT : out std_logic; - RC_LOADING_DONE_IN : in std_logic; - RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - - RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - - GSC_REPLY_DATAREADY_OUT : out std_logic; - GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_REPLY_READ_IN : in std_logic; - GSC_BUSY_OUT : out std_logic - ); -end component; - -component trb_net16_gbe_buf is -generic( - DO_SIMULATION : integer range 0 to 1 := 1; - RX_PATH_ENABLE : integer range 0 to 1 := 1; - USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1; - - FIXED_SIZE_MODE : integer range 0 to 1 := 1; - INCREMENTAL_MODE : integer range 0 to 1 := 0; - FIXED_SIZE : integer range 0 to 65535 := 10; - UP_DOWN_MODE : integer range 0 to 1 := 0; - UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; - FIXED_DELAY_MODE : integer range 0 to 1 := 1; - FIXED_DELAY : integer range 0 to 16777215 := 16777215 -); -port( - CLK : in std_logic; - TEST_CLK : in std_logic; -- only for simulation! - CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - RESET : in std_logic; - GSR_N : in std_logic; - -- Debug - STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); - STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); - -- configuration interface - IP_CFG_START_IN : in std_logic; - IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); - IP_CFG_DONE_OUT : out std_logic; - IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); - IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); - IP_CFG_MEM_CLK_OUT : out std_logic; - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_RESTART_IN : in std_logic; - -- gk 29.03.10 - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- gk 22.04.10 - -- registers setup interface - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - -- gk 23.04.10 - LED_PACKET_SENT_OUT : out std_logic; - LED_AN_DONE_N_OUT : out std_logic; - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - --SFP Connection - SFP_RXD_P_IN : in std_logic; - SFP_RXD_N_IN : in std_logic; - SFP_TXD_P_OUT : out std_logic; - SFP_TXD_N_OUT : out std_logic; - SFP_REFCLK_P_IN : in std_logic; - SFP_REFCLK_N_IN : in std_logic; - SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SFP_TXDIS_OUT : out std_logic; -- SFP disable - - -- interface between main_controller and hub logic - MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - MAKE_RESET_OUT : out std_logic; - - -- for simulation of receiving part only - MAC_RX_EOF_IN : in std_logic; - MAC_RXD_IN : in std_logic_vector(7 downto 0); - MAC_RX_EN_IN : in std_logic; - - - -- debug ports - ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - - -component trb_net16_gbe_protocol_prioritizer is -port ( - CLK : in std_logic; - RESET : in std_logic; - - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type - PROTOCOL_CODE_IN : in std_logic_vector(7 downto 0); -- ip protocol - UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); - - CODE_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0) -); -end component; - -component trb_net16_gbe_type_validator is -port ( - CLK : in std_logic; - RESET : in std_logic; - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); -- recovered frame type - SAVED_VLAN_ID_IN : in std_logic_vector(15 downto 0); -- recovered vlan id - ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); -- signal from gbe_setup - VLAN_ID_IN : in std_logic_vector(31 downto 0); -- two values from gbe setup - - -- IP level - IP_PROTOCOLS_IN : in std_logic_vector(7 downto 0); - ALLOWED_IP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); - - -- UDP level - UDP_PROTOCOL_IN : in std_logic_vector(15 downto 0); - ALLOWED_UDP_PROTOCOLS_IN : in std_logic_vector(31 downto 0); - - VALID_OUT : out std_logic -); -end component; - -component trb_net16_gbe_protocol_selector is -generic( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0 - ); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - RESET_FOR_DHCP : in std_logic; - --- signals to/from main controller - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - PS_RESPONSE_READY_OUT : out std_logic; - - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - --- singals to/from transmi controller with constructed response - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_RD_EN_IN : in std_logic; - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - MC_BUSY_IN : in std_logic; - - -- misc signals for response constructors - DHCP_START_IN : in std_logic; - DHCP_DONE_OUT : out std_logic; - - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - MAKE_RESET_OUT : out std_logic; - - -- signal for data readout - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - CFG_ADDITIONAL_HDR_IN : in std_logic; - - -- input for statistics from outside - STAT_DATA_IN : in std_logic_vector(31 downto 0); - STAT_ADDR_IN : in std_logic_vector(7 downto 0); - STAT_DATA_RDY_IN : in std_logic; - STAT_DATA_ACK_OUT : out std_logic; - - MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_OUT : out hist_array; - SCTRL_HIST_OUT : out hist_array -); -end component; - -component trb_net16_gbe_mac_control is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- signals to/from main controller - MC_TSMAC_READY_OUT : out std_logic; - MC_RECONF_IN : in std_logic; - MC_GBE_EN_IN : in std_logic; - MC_RX_DISCARD_FCS : in std_logic; - MC_PROMISC_IN : in std_logic; - MC_MAC_ADDR_IN : in std_logic_vector(47 downto 0); - --- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT : out std_logic_vector(7 downto 0); - TSM_HDATA_OUT : out std_logic_vector(7 downto 0); - TSM_HCS_N_OUT : out std_logic; - TSM_HWRITE_N_OUT : out std_logic; - TSM_HREAD_N_OUT : out std_logic; - TSM_HREADY_N_IN : in std_logic; - TSM_HDATA_EN_N_IN : in std_logic; - - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_main_control is -generic( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0 - ); -port ( - CLK : in std_logic; -- system clock - CLK_125 : in std_logic; - RESET : in std_logic; - - MC_LINK_OK_OUT : out std_logic; - MC_RESET_LINK_IN : in std_logic; - MC_IDLE_TOO_LONG_OUT : out std_logic; - MC_DHCP_DONE_OUT : out std_logic; - --- signals to/from receive controller - RC_FRAME_WAITING_IN : in std_logic; - RC_LOADING_DONE_OUT : out std_logic; - RC_DATA_IN : in std_logic_vector(8 downto 0); - RC_RD_EN_OUT : out std_logic; - RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - - RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - --- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_RD_EN_IN : in std_logic; - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_TRANSMIT_DONE_IN : in std_logic; - --- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN : in std_logic; - --- signals to/from hub - MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); - - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - -- signal for data readout - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - CFG_ADDITIONAL_HDR_IN : in std_logic; - - MAKE_RESET_OUT : out std_logic; - --- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT : out std_logic_vector(7 downto 0); - TSM_HDATA_OUT : out std_logic_vector(7 downto 0); - TSM_HCS_N_OUT : out std_logic; - TSM_HWRITE_N_OUT : out std_logic; - TSM_HREAD_N_OUT : out std_logic; - TSM_HREADY_N_IN : in std_logic; - TSM_HDATA_EN_N_IN : in std_logic; - TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); - TSM_RX_STAT_EN_IN : in std_logic; - - - MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_OUT : out hist_array; - SCTRL_HIST_OUT : out hist_array -); -end component; - -component trb_net16_gbe_transmit_control is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- signal to/from main controller - MC_TRANSMIT_CTRL_IN : in std_logic; -- slow control frame is waiting to be built and sent - MC_DATA_IN : in std_logic_vector(8 downto 0); - MC_DATA_NOT_VALID_IN : in std_logic; - MC_WR_EN_IN : in std_logic; - MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - - MC_DEST_MAC_IN : in std_logic_vector(47 downto 0); - MC_DEST_IP_IN : in std_logic_vector(31 downto 0); - MC_DEST_UDP_IN : in std_logic_vector(15 downto 0); - MC_SRC_MAC_IN : in std_logic_vector(47 downto 0); - MC_SRC_IP_IN : in std_logic_vector(31 downto 0); - MC_SRC_UDP_IN : in std_logic_vector(15 downto 0); - - MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - MC_IDENT_IN : in std_logic_vector(15 downto 0); - - MC_IP_SIZE_IN : in std_logic_vector(15 downto 0); - MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0); - MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); - - MC_FC_H_READY_OUT : out std_logic; - MC_FC_READY_OUT : out std_logic; - MC_FC_WR_EN_IN : in std_logic; - - MC_BUSY_OUT : out std_logic; - MC_TRANSMIT_DONE_OUT : out std_logic; - --- signal to/from frame constructor - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_WR_EN_OUT : out std_logic; - FC_READY_IN : in std_logic; - FC_H_READY_IN : in std_logic; - FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - - DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_receive_control is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- signals to/from frame_receiver - RC_DATA_IN : in std_logic_vector(8 downto 0); - FR_RD_EN_OUT : out std_logic; - FR_FRAME_VALID_IN : in std_logic; - FR_GET_FRAME_OUT : out std_logic; - FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0); - FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - - FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - --- signals to the rest of the logic - RC_RD_EN_IN : in std_logic; - RC_Q_OUT : out std_logic_vector(8 downto 0); - RC_FRAME_WAITING_OUT : out std_logic; - RC_LOADING_DONE_IN : in std_logic; - RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - - RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - --- statistics - FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0); - - - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_frame_receiver is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - LINK_OK_IN : in std_logic; - ALLOW_RX_IN : in std_logic; - RX_MAC_CLK : in std_logic; -- receiver serdes clock - --- input signals from TS_MAC - MAC_RX_EOF_IN : in std_logic; - MAC_RX_ER_IN : in std_logic; - MAC_RXD_IN : in std_logic_vector(7 downto 0); - MAC_RX_EN_IN : in std_logic; - MAC_RX_FIFO_ERR_IN : in std_logic; - MAC_RX_FIFO_FULL_OUT : out std_logic; - MAC_RX_STAT_EN_IN : in std_logic; - MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); --- output signal to control logic - FR_Q_OUT : out std_logic_vector(8 downto 0); - FR_RD_EN_IN : in std_logic; - FR_FRAME_VALID_OUT : out std_logic; - FR_GET_FRAME_IN : in std_logic; - FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); - FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0); - FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0); - FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0); - FR_VLAN_ID_IN : in std_logic_vector(31 downto 0); - - FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - - MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); - MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0) -); -end component; - --- gk 01.07.10 -component trb_net16_ipu2gbe is -port( - CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 - MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - --- SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0); --- SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0); - - -- PacketConstructor interface - ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; -- gk 07.10.10 - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) -); -end component; - -component trb_net16_gbe_packet_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10 - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 - PC_END_OF_DATA_IN : in std_logic; - PC_TRANSMIT_ON_OUT : out std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_PADDING_IN : in std_logic; -- gk 29.03.10 - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP - PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 - -- FrameConstructor ports - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(7 downto 0); - TC_H_READY_IN : in std_logic; - TC_READY_IN : in std_logic; - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_SOD_OUT : out std_logic; - TC_EOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_frame_constr is -port( - -- ports for user logic - RESET : in std_logic; - CLK : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - -- - WR_EN_IN : in std_logic; - DATA_IN : in std_logic_vector(7 downto 0); - START_OF_DATA_IN : in std_logic; - END_OF_DATA_IN : in std_logic; - IP_F_SIZE_IN : in std_logic_vector(15 downto 0); - UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation - HEADERS_READY_OUT : out std_logic; - READY_OUT : out std_logic; - DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - IHL_VERSION_IN : in std_logic_vector(7 downto 0); - TOS_IN : in std_logic_vector(7 downto 0); - IDENTIFICATION_IN : in std_logic_vector(15 downto 0); - FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); - TTL_IN : in std_logic_vector(7 downto 0); - PROTOCOL_IN : in std_logic_vector(7 downto 0); - FRAME_DELAY_IN : in std_logic_vector(31 downto 0); - -- ports for packetTransmitter - RD_CLK : in std_logic; -- 125MHz clock!!! - FT_DATA_OUT : out std_logic_vector(8 downto 0); - FT_TX_EMPTY_OUT : out std_logic; - FT_TX_RD_EN_IN : in std_logic; - FT_START_OF_PACKET_OUT : out std_logic; - FT_TX_DONE_IN : in std_logic; - FT_TX_DISCFRM_IN : in std_logic; - - MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0) -); -end component; - -component trb_net16_gbe_frame_trans is -port ( - CLK : in std_logic; - RESET : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - TX_MAC_CLK : in std_logic; - TX_EMPTY_IN : in std_logic; - START_OF_PACKET_IN : in std_logic; - DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC - -- NEW PORTS --- HADDR_OUT : out std_logic_vector(7 downto 0); --- HDATA_OUT : out std_logic_vector(7 downto 0); --- HCS_OUT : out std_logic; --- HWRITE_OUT : out std_logic; --- HREAD_OUT : out std_logic; --- HREADY_IN : in std_logic; --- HDATA_EN_IN : in std_logic; - TX_FIFOAVAIL_OUT : out std_logic; - TX_FIFOEOF_OUT : out std_logic; - TX_FIFOEMPTY_OUT : out std_logic; - TX_DONE_IN : in std_logic; - TX_STAT_EN_IN : in std_logic; - TX_STATVEC_IN : in std_logic_vector(30 downto 0); - TX_DISCFRM_IN : in std_logic; - -- Debug - BSM_INIT_OUT : out std_logic_vector(3 downto 0); - BSM_MAC_OUT : out std_logic_vector(3 downto 0); - BSM_TRANS_OUT : out std_logic_vector(3 downto 0); - DBG_RD_DONE_OUT : out std_logic; - DBG_INIT_DONE_OUT : out std_logic; - DBG_ENABLED_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_med_ecp_sfp_gbe_8b is --- gk 28.04.10 -generic ( - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 -); -port( - RESET : in std_logic; - GSR_N : in std_logic; - CLK_125_OUT : out std_logic; - CLK_125_RX_OUT : out std_logic; - CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk - --SGMII connection to frame transmitter (tsmac) - FT_TX_CLK_EN_OUT : out std_logic; - FT_RX_CLK_EN_OUT : out std_logic; - FT_COL_OUT : out std_logic; - FT_CRS_OUT : out std_logic; - FT_TXD_IN : in std_logic_vector(7 downto 0); - FT_TX_EN_IN : in std_logic; - FT_TX_ER_IN : in std_logic; - FT_RXD_OUT : out std_logic_vector(7 downto 0); - FT_RX_EN_OUT : out std_logic; - FT_RX_ER_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable - -- Autonegotiation stuff - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); - MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); - MR_AN_PAGE_RX_OUT : out std_logic; - MR_AN_COMPLETE_OUT : out std_logic; - MR_AN_ENABLE_IN : in std_logic; - MR_RESTART_AN_IN : in std_logic; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) -); -end component; - -component gbe_setup is -port( - CLK : in std_logic; - RESET : in std_logic; - - -- interface to regio bus - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - BUS_WRITE_EN_IN : in std_logic; - BUS_READ_EN_IN : in std_logic; - BUS_ACK_OUT : out std_logic; - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); - GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); - GBE_USE_GBE_OUT : out std_logic; - GBE_USE_TRBNET_OUT : out std_logic; - GBE_USE_MULTIEVENTS_OUT : out std_logic; - GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); - GBE_READOUT_CTR_VALID_OUT : out std_logic; - GBE_ALLOW_RX_OUT : out std_logic; - GBE_ADDITIONAL_HDR_OUT : out std_logic; - GBE_INSERT_TTYPE_OUT : out std_logic; - GBE_SOFT_RESET_OUT : out std_logic; - - GBE_MAX_SUB_OUT : out std_logic_vector(15 downto 0); - GBE_MAX_QUEUE_OUT : out std_logic_vector(15 downto 0); - GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0); - GBE_MAX_SINGLE_SUB_OUT : out std_logic_vector(15 downto 0); - - MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0); - MONITOR_TX_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_TX_FRAMES_IN : in std_logic_vector(31 downto 0); - MONITOR_TX_PACKETS_IN : in std_logic_vector(31 downto 0); - MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0); - - MONITOR_SELECT_REC_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_IN : in std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_IN : in hist_array; - SCTRL_HIST_IN : in hist_array -); -end component; - - -component ip_configurator is -port( - CLK : in std_logic; - RESET : in std_logic; - -- configuration interface - START_CONFIG_IN : in std_logic; -- start configuration run - BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank - CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used - MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for - MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory - MEM_CLK_OUT : out std_logic; -- clock for BlockRAM - -- information for IP cores - DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address - DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address - DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port - SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address - SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address - SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port - MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) - -- Debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end component; - -component fifo_4096x9 is -port( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_2048x8 is -port( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_4096x32 is -port( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_512x32 is -port( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_512x72 is -port( - Data : in std_logic_vector(71 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(71 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_1024x16x8 is -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_65536x18x9 is -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_4kx18x9 is -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - - -component fifo_2048x8x16 is -port( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(17 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_4kx8_ecp3 is -port( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component statts_mem is - port ( - WrAddress: in std_logic_vector(7 downto 0); - RdAddress: in std_logic_vector(9 downto 0); - Data: in std_logic_vector(31 downto 0); - WE: in std_logic; - RdClock: in std_logic; - RdClockEn: in std_logic; - Reset: in std_logic; - WrClock: in std_logic; - WrClockEn: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end component; - ---component slv_mac_memory is ---port( --- CLK : in std_logic; --- RESET : in std_logic; --- BUSY_IN : in std_logic; --- -- Slave bus --- SLV_ADDR_IN : in std_logic_vector(7 downto 0); --- SLV_READ_IN : in std_logic; --- SLV_WRITE_IN : in std_logic; --- SLV_BUSY_OUT : out std_logic; --- SLV_ACK_OUT : out std_logic; --- SLV_DATA_IN : in std_logic_vector(31 downto 0); --- SLV_DATA_OUT : out std_logic_vector(31 downto 0); --- -- I/O to the backend --- MEM_CLK_IN : in std_logic; --- MEM_ADDR_IN : in std_logic_vector(7 downto 0); --- MEM_DATA_OUT : out std_logic_vector(31 downto 0); --- -- Status lines --- STAT : out std_logic_vector(31 downto 0) -- DEBUG ---); ---end component; - -component fifo_32kx16x8_mb2 -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - AlmostEmpty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic -); -end component; - -component fifo_64kx9 -port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_16kx18x9 is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(14 downto 0); - AmFullThresh: in std_logic_vector(13 downto 0); - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end component; - -component fifo_32kx9_flags is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostFull : out std_logic); -end component; - - -component fifo_512x32x8 -port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component fifo_512x8 -port ( - Data : in std_logic_vector(7 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -end package; \ No newline at end of file diff --git a/gbe2_ecp3/trb_net_gbe_protocols.vhd b/gbe2_ecp3/trb_net_gbe_protocols.vhd deleted file mode 100644 index 8d0dc4c..0000000 --- a/gbe2_ecp3/trb_net_gbe_protocols.vhd +++ /dev/null @@ -1,627 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -library work; -use work.trb_net_std.all; - -package trb_net_gbe_protocols is - -type hist_array is array(31 downto 0) of std_logic_vector(31 downto 0); - -signal g_SIMULATE : integer range 0 to 1 := 0; - --- g_MY_IP is being set by DHCP Response Constructor -signal g_MY_IP : std_logic_vector(31 downto 0); --- g_MY_MAC is being set by Main Controller -signal g_MY_MAC : std_logic_vector(47 downto 0); - -constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2; -constant c_MAX_PROTOCOLS : integer range 1 to 16 := 5; --5; --4; --5; -constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2; -constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4; - -type frame_types_a is array(c_MAX_FRAME_TYPES - 1 downto 0) of std_logic_vector(15 downto 0); -constant FRAME_TYPES : frame_types_a := (x"0800", x"0806"); --- IPv4, ARP - -type ip_protos_a is array(c_MAX_IP_PROTOCOLS - 1 downto 0) of std_logic_vector(7 downto 0); -constant IP_PROTOCOLS : ip_protos_a := (x"11", x"01"); --- UDP, ICMP - --- this are the destination ports of the incoming packet -type udp_protos_a is array(c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0); -constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531"); --x"6590", x"7530", x"7531"); --x"61a8", x"7530", x"7531"); --- DHCP client, SCTRL, STATs - -component trb_net16_gbe_response_constructor_Forward is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_BUSY_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_ARP is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_Test is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_BUSY_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_Trash is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_BUSY_IN : in std_logic; - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_DHCP is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - - DHCP_START_IN : in std_logic; - DHCP_DONE_OUT : out std_logic; --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_Ping is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_PseudoPing is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_Test1 is -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - TC_BUSY_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_SCTRL is -generic ( STAT_ADDRESS_BASE : integer := 0 -); - port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - - -- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - DEBUG_OUT : out std_logic_vector(63 downto 0); - -- END OF INTERFACE - - -- protocol specific ports - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - MAKE_RESET_OUT : out std_logic; - CFG_ADDITIONAL_HDR_IN : in std_logic; - -- end of protocol specific ports - - MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); - - DATA_HIST_OUT : out hist_array - ); -end component; - -component trb_net16_gbe_response_constructor_Stat is -generic ( STAT_ADDRESS_BASE : integer := 0 -); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_WR_EN_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_BUSY_IN : in std_logic; - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0); - SENT_FRAMES_OUT : out std_logic_vector(15 downto 0); --- END OF INTERFACE - - STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0); - STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0); - STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); - STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0); - --- debug - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_response_constructor_TrbNetData is -generic ( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0 - ); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - --- INTERFACE - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - - DEBUG_OUT : out std_logic_vector(63 downto 0); - --- END OF INTERFACE - - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0); - - DATA_HIST_OUT : out hist_array -); -end component; - -end package; diff --git a/gbe_ecp2m/feeder.vhd b/gbe_ecp2m/feeder.vhd deleted file mode 100755 index 57fb2c2..0000000 --- a/gbe_ecp2m/feeder.vhd +++ /dev/null @@ -1,620 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity feeder is -port( CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- PacketConstructor interface - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - -- Debug - BSM_SAVE_OUT : out std_logic_vector(3 downto 0); - BSM_LOAD_OUT : out std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : out std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : out std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : out std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : out std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : out std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : out std_logic; - DBG_SF_WR_EN_OUT : out std_logic; - DBG_SF_EMPTY_OUT : out std_logic; - DBG_SF_FULL_OUT : out std_logic; - DBG_SF_AFULL_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end entity; - -architecture feeder of feeder is - -component fifo_32kx16x8_mb -port( Data : in std_logic_vector(15 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic - ); -end component; - -type saveStates is (SIDLE, WAIT_FOR_DATA, SAVE_DATA, TERMINATE, SCLOSE); -signal saveCurrentState, saveNextState : saveStates; -signal state : std_logic_vector(3 downto 0); -signal data_req_comb : std_logic; -signal data_req : std_logic; -- request data signal, will be used for fee_read generation -signal rst_saved_ctr_comb : std_logic; -signal rst_saved_ctr : std_logic; - -signal fee_read_comb : std_logic; -signal fee_read : std_logic; -- fee_read signal -signal saved_ctr : std_logic_vector(16 downto 0); -signal ce_saved_ctr : std_logic; - --- header data -signal cts_rnd : std_logic_vector(15 downto 0); -signal cts_rnd_saved : std_logic; -signal cts_trg : std_logic_vector(15 downto 0); -signal cts_trg_saved : std_logic; -signal cts_len : std_logic_vector(16 downto 0); -signal cts_len_saved : std_logic; - --- CTS interface -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal cts_length : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_data : std_logic_vector(31 downto 0); - --- Split FIFO signals -signal sf_data : std_logic_vector(15 downto 0); -signal sf_wr_en_comb : std_logic; -signal sf_wr_en : std_logic; -- write signal for FIFO -signal sf_rd_en : std_logic; -signal sf_wcnt : std_logic_vector(15 downto 0); -signal sf_rcnt : std_logic_vector(16 downto 0); -signal sf_empty : std_logic; -signal sf_full : std_logic; -signal sf_afull : std_logic; - -------------------------------------------------------------------- -type loadStates is (LIDLE, INIT, REMOVE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, WAIT_PC, CLOSE); -signal loadCurrentState, loadNextState : loadStates; -signal state2 : std_logic_vector(3 downto 0); - -signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data -signal rst_rem_ctr_comb : std_logic; -signal rst_rem_ctr : std_logic; -signal rst_regs_comb : std_logic; -signal rst_regs : std_logic; -signal ce_rem_ctr_comb : std_logic; -signal ce_rem_ctr : std_logic; -signal remove_done_comb : std_logic; -signal remove_done : std_logic; -- end of header stripping process -signal load_done_comb : std_logic; -signal load_done : std_logic; -- end of data transfer into PC -signal calc_pad_comb : std_logic; -signal calc_pad : std_logic; -- add padding bytes, if needed -signal read_data_comb : std_logic; -signal read_data : std_logic; -- fetch data from split fifo -signal data_phase_comb : std_logic; -signal data_phase : std_logic; -- data transport phase from split fifo to PC -signal pc_sos_comb : std_logic; -signal pc_sos : std_logic; -- start of data signal -signal pc_eod_comb : std_logic; -signal pc_eod : std_logic; -- end of data signal -signal pad_data_comb : std_logic; -signal pad_data : std_logic; -- insert padding bytes - -signal pc_data : std_logic_vector(7 downto 0); -signal pc_data_q : std_logic_vector(7 downto 0); -signal pc_trig_nr : std_logic_vector(15 downto 0); -signal pc_sub_size : std_logic_vector(17 downto 0); -signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo -signal padding_needed : std_logic; -signal pc_wr_en_q : std_logic; -signal pc_wr_en_qq : std_logic; -signal pc_eod_q : std_logic; - -signal debug : std_logic_vector(31 downto 0); - -begin - --- CTS interface signals -cts_error_pattern <= (others => '0'); -- FAKE -cts_dataready <= '1'; -- FAKE - -cts_length <= x"0000"; -- length of data payload is always 0 -cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' - -cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; - - --- Sync all critical pathes -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - sf_data <= FEE_DATA_IN; - sf_wr_en <= sf_wr_en_comb; - fee_read <= fee_read_comb; - load_done <= load_done_comb; - pc_eod_q <= pc_eod; - pc_wr_en_qq <= pc_wr_en_q; - pc_wr_en_q <= data_phase; - end if; -end process THE_SYNC_PROC; - --- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY -fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) - else '0'; - --- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY -sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) - else '0'; - --- Counter for header word storage -THE_CTS_SAVED_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - saved_ctr <= (others => '0'); - elsif( ce_saved_ctr = '1' ) then - saved_ctr <= saved_ctr + 1; - end if; - end if; -end process THE_CTS_SAVED_CTR; - -ce_saved_ctr <= sf_wr_en; - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -saveMachineProc: process( CLK ) -begin - if rising_edge(CLK) then - if RESET = '1' then - saveCurrentState <= SIDLE; - data_req <= '0'; - rst_saved_ctr <= '0'; - else - saveCurrentState <= saveNextState; - data_req <= data_req_comb; - rst_saved_ctr <= rst_saved_ctr_comb; - end if; - end if; -end process saveMachineProc; - -saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN ) -begin - saveNextState <= SIDLE; - data_req_comb <= '0'; - rst_saved_ctr_comb <= '0'; - case saveCurrentState is - when SIDLE => - state <= x"0"; - if (CTS_START_READOUT_IN = '1') then - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - rst_saved_ctr_comb <= '1'; - else - saveNextState <= SIDLE; - end if; - when WAIT_FOR_DATA => - state <= x"1"; - if (FEE_BUSY_IN = '1') then - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - else - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - end if; - when SAVE_DATA => - state <= x"2"; - if (FEE_BUSY_IN = '0') then - saveNextState <= TERMINATE; - else - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - end if; - when TERMINATE => - state <= x"3"; - if (CTS_READ_IN = '1') then - saveNextState <= SCLOSE; - else - saveNextState <= TERMINATE; - end if; - when SCLOSE => - state <= x"4"; - if (CTS_START_READOUT_IN = '0') then - saveNextState <= SIDLE; - else - saveNextState <= SCLOSE; - end if; - when others => - state <= x"f"; - saveNextState <= SIDLE; - end case; -end process saveMachine; - --- save triggerRnd from incoming data for cts response -CTS_RND_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_rnd <= (others => '0'); - cts_rnd_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then - cts_rnd <= sf_data; - cts_rnd_saved <= '1'; - end if; - end if; -end process CTS_RND_PROC; - --- save triggerNr from incoming data for cts response -CTS_TRG_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_trg <= (others => '0'); - cts_trg_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then - cts_trg <= sf_data; - cts_trg_saved <= '1'; - end if; - end if; -end process CTS_TRG_PROC; - --- save size from incoming data for cts response (future) and to get rid of padding -CTS_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_len <= (others => '0'); - cts_len_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then - cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words - elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then - cts_len <= cts_len + x"4"; - cts_len_saved <= '1'; - end if; - end if; -end process CTS_SIZE_PROC; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Split FIFO -THE_SPLIT_FIFO: fifo_32kx16x8_mb -port map( Data => sf_data, - WrClock => CLK, - RdClock => CLK, - WrEn => sf_wr_en, - RdEn => sf_rd_en, - Reset => RESET, - RPReset => RESET, - AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 - Q => pc_data, --open, - WCNT => sf_wcnt, - RCNT => sf_rcnt, - Empty => sf_empty, - Full => sf_full, - AlmostFull => sf_afull - ); - -sf_rd_en <= read_data; ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- FIFO data delay process (also forces padding bytes to known value) -THE_DATA_DELAY_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( pad_data = '1' ) then - pc_data_q <= x"ee"; - else - pc_data_q <= pc_data; - end if; - end if; -end process THE_DATA_DELAY_PROC; - --- Statemachine for reading the data payload from the SPLIT_FIFO and feeding --- it into the packet constructor -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if RESET = '1' then - loadCurrentState <= LIDLE; - rst_regs <= '0'; - rst_rem_ctr <= '0'; - ce_rem_ctr <= '0'; - calc_pad <= '0'; - read_data <= '0'; - data_phase <= '0'; - pc_sos <= '0'; - pc_eod <= '0'; - pad_data <= '0'; - else - loadCurrentState <= loadNextState; - rst_regs <= rst_regs_comb; - rst_rem_ctr <= rst_rem_ctr_comb; - ce_rem_ctr <= ce_rem_ctr_comb; - calc_pad <= calc_pad_comb; - read_data <= read_data_comb; - data_phase <= data_phase_comb; - pc_sos <= pc_sos_comb; - pc_eod <= pc_eod_comb; - pad_data <= pad_data_comb; - end if; - end if; -end process loadMachineProc; - -loadMachine : process( loadCurrentState, sf_empty, remove_done, load_done, padding_needed, PC_READY_IN ) -begin - loadNextState <= LIDLE; - rst_regs_comb <= '0'; - rst_rem_ctr_comb <= '0'; - ce_rem_ctr_comb <= '0'; - calc_pad_comb <= '0'; - read_data_comb <= '0'; - data_phase_comb <= '0'; - pc_sos_comb <= '0'; - pc_eod_comb <= '0'; - pad_data_comb <= '0'; - case loadCurrentState is - when LIDLE => - state2 <= x"0"; - if( (sf_empty = '0') and (PC_READY_IN = '1') ) then - loadNextState <= INIT; - rst_regs_comb <= '1'; - rst_rem_ctr_comb <= '1'; - else - loadNextState <= LIDLE; - end if; - when INIT => - state2 <= x"1"; - loadNextState <= REMOVE; - ce_rem_ctr_comb <= '1'; - read_data_comb <= '1'; - when REMOVE => - state2 <= x"2"; - if( remove_done = '1' ) then - loadNextState <= CALCA; - calc_pad_comb <= '1'; - else - loadNextState <= REMOVE; - ce_rem_ctr_comb <= '1'; - read_data_comb <= '1'; - end if; - when CALCA => - state2 <= x"3"; - loadNextState <= CALCB; - when CALCB => - -- we need a branch in case of length "0"!!!! - state2 <= x"4"; - loadNextState <= LOAD; - read_data_comb <= '1'; - data_phase_comb <= '1'; - pc_sos_comb <= '1'; - when LOAD => - state2 <= x"5"; - if ( (load_done = '1') and (padding_needed = '0') ) then - loadNextState <= CLOSE; - elsif( (load_done = '1') and (padding_needed = '1') ) then - loadNextState <= PAD0; - data_phase_comb <= '1'; - else - loadNextState <= LOAD; - read_data_comb <= '1'; - data_phase_comb <= '1'; - end if; - when PAD0 => - state2 <= x"5"; - loadNextState <= PAD1; - data_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD1 => - state2 <= x"6"; - loadNextState <= PAD2; - data_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD2 => - state2 <= x"7"; - loadNextState <= PAD3; - data_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD3 => - state2 <= x"8"; - loadNextState <= CLOSE; - pad_data_comb <= '1'; - when CLOSE => - state2 <= x"9"; - loadNextState <= WAIT_PC; - pc_eod_comb <= '1'; - when WAIT_PC => - state2 <= x"a"; - if( PC_READY_IN = '1' ) then - loadNextState <= LIDLE; - rst_rem_ctr_comb <= '1'; - rst_regs_comb <= '1'; - else - loadNextState <= WAIT_PC; - end if; - when others => - state2 <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- Counter for stripping the unneeded parts of the data stream, and saving the important parts -THE_REMOVE_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - rem_ctr <= (others => '0'); - elsif( ce_rem_ctr = '1' ) then - rem_ctr <= rem_ctr + 1; - end if; - end if; -end process THE_REMOVE_CTR; - -remove_done_comb <= '1' when ( rem_ctr = x"6" ) else '0'; - -THE_REM_DONE_SYNC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - remove_done <= '0'; - else - remove_done <= remove_done_comb; - end if; - end if; -end process THE_REM_DONE_SYNC; - --- extract the trigger number from splitfifo data -THE_TRG_NR_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_trig_nr <= (others => '0'); - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"3") ) then - pc_trig_nr(7 downto 0) <= pc_data; - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"4") ) then - pc_trig_nr(15 downto 8) <= pc_data; - end if; - end if; -end process THE_TRG_NR_PROC; - --- check for padding -THE_PADDING_NEEDED_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - padding_needed <= '0'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then - padding_needed <= '1'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then - padding_needed <= '0'; - end if; - end if; -end process THE_PADDING_NEEDED_PROC; - --- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, --- and in case of padding needed increase it accordingly -THE_SUB_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_sub_size <= (others => '0'); - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then - pc_sub_size(9 downto 2) <= pc_data; - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then - pc_sub_size(17 downto 10) <= pc_data; - elsif( (calc_pad = '1') and (padding_needed = '1') ) then - pc_sub_size <= pc_sub_size + 4; - end if; - end if; -end process THE_SUB_SIZE_PROC; - --- number of bytes to read from split fifo -THE_READ_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - read_size <= (others => '0'); - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"5") ) then - read_size(9 downto 2) <= pc_data; - elsif( (ce_rem_ctr = '1') and (rem_ctr = x"6") ) then - read_size(17 downto 10) <= pc_data; - elsif( ((calc_pad = '1') and (load_done = '0')) ) then - read_size <= read_size - 2; - elsif( ((read_data = '1') and (data_phase = '1')) ) then - read_size <= read_size - 1; - end if; - end if; -end process THE_READ_SIZE_PROC; - -load_done_comb <= '1' when (read_size = 0) else '0'; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Debug signals -debug(31) <= remove_done; -debug(30) <= load_done; -debug(29) <= ce_rem_ctr; -debug(28) <= rst_rem_ctr; -debug(27) <= rst_regs; -debug(26) <= data_phase; -debug(25) <= read_data; -debug(24) <= pad_data; -debug(23 downto 18) <= (others => '0'); -debug(17 downto 0) <= read_size; - --- Outputs -FEE_READ_OUT <= fee_read; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; -CTS_DATA_OUT <= cts_data; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_LENGTH_OUT <= cts_length; - -PC_SOS_OUT <= pc_sos; -PC_EOD_OUT <= pc_eod_q; -PC_DATA_OUT <= pc_data_q; -PC_WR_EN_OUT <= pc_wr_en_qq; -PC_TRIG_NR_OUT <= x"0000" & pc_trig_nr; -PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; -PC_PADDING_OUT <= padding_needed; - -BSM_SAVE_OUT <= state; -BSM_LOAD_OUT <= state2; -DBG_CTS_CTR_OUT <= saved_ctr(2 downto 0); -DBG_REM_CTR_OUT <= rem_ctr; -DBG_SF_DATA_OUT <= sf_data; -DBG_SF_WCNT_OUT <= sf_wcnt; -DBG_SF_RCNT_OUT <= sf_rcnt; -DBG_SF_RD_EN_OUT <= sf_rd_en; -DBG_SF_WR_EN_OUT <= sf_wr_en; -DBG_SF_EMPTY_OUT <= sf_empty; -DBG_SF_FULL_OUT <= sf_full; -DBG_SF_AFULL_OUT <= sf_afull; - -DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/ip_configurator.vhd b/gbe_ecp2m/ip_configurator.vhd deleted file mode 100755 index d6b0778..0000000 --- a/gbe_ecp2m/ip_configurator.vhd +++ /dev/null @@ -1,342 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity ip_configurator is -port( - CLK : in std_logic; - RESET : in std_logic; - -- configuration interface - START_CONFIG_IN : in std_logic; -- start configuration run - BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank - CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used - MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for - MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory - MEM_CLK_OUT : out std_logic; -- clock for BlockRAM - -- information for IP cores - DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address - DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address - DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port - SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address - SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address - SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port - MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) - -- Debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end entity; - -architecture ip_configurator of ip_configurator is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of ip_configurator : architecture is "GBE_conf_group"; - -type STATES is (IDLE, LOAD_REG, DELAY0, DELAY1, DELAY2, LOAD_DONE); -signal CURRENT_STATE, NEXT_STATE : STATES; -signal bsm : std_logic_vector(3 downto 0); -signal ce_ctr_comb : std_logic; -signal ce_ctr : std_logic; -signal rst_ctr_comb : std_logic; -signal rst_ctr : std_logic; -signal cfg_done_comb : std_logic; -signal cfg_done : std_logic; - -signal ctr_done_comb : std_logic; -signal ctr_done : std_logic; - -signal wr_select_comb : std_logic_vector(15 downto 0); -signal wr_select : std_logic_vector(15 downto 0); -signal wr_select_q : std_logic_vector(15 downto 0); - -signal addr_ctr : std_logic_vector(3 downto 0); -signal dest_mac : std_logic_vector(47 downto 0); -signal dest_ip : std_logic_vector(31 downto 0); -signal dest_udp : std_logic_vector(15 downto 0); -signal src_mac : std_logic_vector(47 downto 0); -signal src_ip : std_logic_vector(31 downto 0); -signal src_udp : std_logic_vector(15 downto 0); -signal mtu : std_logic_vector(15 downto 0); - -signal debug : std_logic_vector(31 downto 0); - -begin - - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -STATE_MACHINE_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if RESET = '1' then - CURRENT_STATE <= IDLE; - ce_ctr <= '0'; - rst_ctr <= '0'; - cfg_done <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - ce_ctr <= ce_ctr_comb; - rst_ctr <= rst_ctr_comb; - cfg_done <= cfg_done_comb; - end if; - end if; -end process STATE_MACHINE_PROC; - -STATE_MACHINE_TRANS: process( CURRENT_STATE, START_CONFIG_IN, ctr_done ) -begin - NEXT_STATE <= IDLE; - ce_ctr_comb <= '0'; - rst_ctr_comb <= '0'; - cfg_done_comb <= '0'; - case CURRENT_STATE is - when IDLE => - bsm <= x"0"; - if( START_CONFIG_IN = '1' ) then - NEXT_STATE <= LOAD_REG; - ce_ctr_comb <= '1'; - else - NEXT_STATE <= IDLE; - end if; - when LOAD_REG => - bsm <= x"1"; - if( ctr_done = '1' ) then - NEXT_STATE <= DELAY0; - rst_ctr_comb <= '1'; - else - NEXT_STATE <= LOAD_REG; - ce_ctr_comb <= '1'; - end if; - when DELAY0 => - bsm <= x"2"; - NEXT_STATE <= DELAY1; - when DELAY1 => - bsm <= x"3"; - NEXT_STATE <= DELAY2; - when DELAY2 => - bsm <= x"4"; - NEXT_STATE <= LOAD_DONE; - cfg_done_comb <= '1'; - when LOAD_DONE => - bsm <= x"2"; - if( START_CONFIG_IN = '0' ) then - NEXT_STATE <= IDLE; - else - NEXT_STATE <= LOAD_DONE; - cfg_done_comb <= '1'; - end if; - when others => - bsm <= x"f"; - NEXT_STATE <= IDLE; - end case; -end process STATE_MACHINE_TRANS; - --- address counter -THE_ADDR_CTR_PROC: process( CLK ) -begin - if ( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_ctr = '1') ) then - addr_ctr <= (others => '0'); - elsif( ce_ctr = '1' ) then - addr_ctr <= addr_ctr + 1; - end if; - end if; -end process THE_ADDR_CTR_PROC; - -ctr_done_comb <= '1' when (addr_ctr = x"e") else '0'; - -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - ctr_done <= ctr_done_comb; - wr_select_q <= wr_select; - wr_select <= wr_select_comb; - end if; -end process THE_SYNC_PROC; - --- generate combinatorial write select signals, register and delay the (output registers in EBR!) -wr_select_comb(0) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"0") ) else '0'; -- dest MAC low -wr_select_comb(1) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"1") ) else '0'; -- dest MAC high -wr_select_comb(2) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"2") ) else '0'; -- dest IP -wr_select_comb(3) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"3") ) else '0'; -- dest port -wr_select_comb(4) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"4") ) else '0'; -- src MAC low -wr_select_comb(5) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"5") ) else '0'; -- src MAC high -wr_select_comb(6) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"6") ) else '0'; -- src IP -wr_select_comb(7) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"7") ) else '0'; -- src port -wr_select_comb(8) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"8") ) else '0'; -- MTU -wr_select_comb(9) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"9") ) else '0'; -wr_select_comb(10) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"a") ) else '0'; -wr_select_comb(11) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"b") ) else '0'; -wr_select_comb(12) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"c") ) else '0'; -wr_select_comb(13) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"d") ) else '0'; -wr_select_comb(14) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"e") ) else '0'; -wr_select_comb(15) <= '1' when ( (ce_ctr = '1') and (addr_ctr = x"f") ) else '0'; - --- destination MAC low register -THE_D_MAC_LOW_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_mac(31 downto 0) <= (others => '0'); - elsif( wr_select_q(0) = '1') then - dest_mac(31 downto 0) <= mem_data_in; - end if; - end if; -end process THE_D_MAC_LOW_PROC; - --- destination MAC high register -THE_D_MAC_HIGH_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_mac(47 downto 32) <= (others => '0'); - elsif( wr_select_q(1) = '1') then - dest_mac(47 downto 32) <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_D_MAC_HIGH_PROC; - --- destination IP register -THE_D_IP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_ip <= (others => '0'); - elsif( wr_select_q(2) = '1') then - dest_ip <= mem_data_in; - end if; - end if; -end process THE_D_IP_PROC; - --- destination PORT register -THE_D_PORT_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - dest_udp <= (others => '0'); - elsif( wr_select_q(3) = '1') then - dest_udp <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_D_PORT_PROC; - --- source MAC low register -THE_S_MAC_LOW_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_mac(31 downto 0) <= (others => '0'); - elsif( wr_select_q(4) = '1') then - src_mac(31 downto 0) <= mem_data_in; - end if; - end if; -end process THE_S_MAC_LOW_PROC; - --- source MAC high register -THE_S_MAC_HIGH_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_mac(47 downto 32) <= (others => '0'); - elsif( wr_select_q(5) = '1') then - src_mac(47 downto 32) <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_S_MAC_HIGH_PROC; - --- source IP register -THE_S_IP_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_ip <= (others => '0'); - elsif( wr_select_q(6) = '1') then - src_ip <= mem_data_in; - end if; - end if; -end process THE_S_IP_PROC; - --- source PORT register -THE_S_PORT_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - src_udp <= (others => '0'); - elsif( wr_select_q(7) = '1') then - src_udp <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_S_PORT_PROC; - --- MTU size register -THE_MTU_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - mtu <= (others => '0'); - elsif( wr_select_q(8) = '1') then - mtu <= mem_data_in(15 downto 0); - end if; - end if; -end process THE_MTU_PROC; - - --- Debug signals -debug(31 downto 12) <= (others => '0'); -debug(11 downto 8) <= addr_ctr; -debug(7) <= '0'; -debug(6) <= ctr_done; -debug(5) <= ce_ctr; -debug(4) <= rst_ctr; -debug(3 downto 0) <= bsm; --- Outputs -MEM_ADDR_OUT(7 downto 4) <= BANK_SELECT_IN; -MEM_ADDR_OUT(3 downto 0) <= addr_ctr; -MEM_CLK_OUT <= CLK; -CONFIG_DONE_OUT <= cfg_done; - --- destination MAC address - swap for user convinience -DEST_MAC_OUT(47 downto 40) <= dest_mac(7 downto 0); -DEST_MAC_OUT(39 downto 32) <= dest_mac(15 downto 8); -DEST_MAC_OUT(31 downto 24) <= dest_mac(23 downto 16); -DEST_MAC_OUT(23 downto 16) <= dest_mac(31 downto 24); -DEST_MAC_OUT(15 downto 8) <= dest_mac(39 downto 32); -DEST_MAC_OUT(7 downto 0) <= dest_mac(47 downto 40); - --- destination IP address - swap for user convinience -DEST_IP_OUT(31 downto 24) <= dest_ip(7 downto 0); -DEST_IP_OUT(23 downto 16) <= dest_ip(15 downto 8); -DEST_IP_OUT(15 downto 8) <= dest_ip(23 downto 16); -DEST_IP_OUT(7 downto 0) <= dest_ip(31 downto 24); - --- destination port address - swap for user convinience -DEST_UDP_OUT(15 downto 8) <= dest_udp(7 downto 0); -DEST_UDP_OUT(7 downto 0) <= dest_udp(15 downto 8); - --- source MAC address - swap for user convinience -SRC_MAC_OUT(47 downto 40) <= src_mac(7 downto 0); -SRC_MAC_OUT(39 downto 32) <= src_mac(15 downto 8); -SRC_MAC_OUT(31 downto 24) <= src_mac(23 downto 16); -SRC_MAC_OUT(23 downto 16) <= src_mac(31 downto 24); -SRC_MAC_OUT(15 downto 8) <= src_mac(39 downto 32); -SRC_MAC_OUT(7 downto 0) <= src_mac(47 downto 40); - --- source IP address - swap for user convinience -SRC_IP_OUT(31 downto 24) <= src_ip(7 downto 0); -SRC_IP_OUT(23 downto 16) <= src_ip(15 downto 8); -SRC_IP_OUT(15 downto 8) <= src_ip(23 downto 16); -SRC_IP_OUT(7 downto 0) <= src_ip(31 downto 24); - --- source port address - swap for user convinience -SRC_UDP_OUT(15 downto 8) <= src_udp(7 downto 0); -SRC_UDP_OUT(7 downto 0) <= src_udp(15 downto 8); - --- DO NOT SWAP! -MTU_OUT <= mtu; - -DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/ipcores/.cvsignore b/gbe_ecp2m/ipcores/.cvsignore deleted file mode 100644 index 25a5568..0000000 --- a/gbe_ecp2m/ipcores/.cvsignore +++ /dev/null @@ -1,6 +0,0 @@ -*.jhd -*.naf -*.srp -*.sym -*.log -*tmpl.vhd diff --git a/gbe_ecp2m/ipcores/debug_fifo_2kx16.vhd b/gbe_ecp2m/ipcores/debug_fifo_2kx16.vhd deleted file mode 100644 index e10ee86..0000000 --- a/gbe_ecp2m/ipcores/debug_fifo_2kx16.vhd +++ /dev/null @@ -1,1965 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 16 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e - --- Wed Jul 21 14:35:10 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity debug_fifo_2kx16 is - port ( - Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(15 downto 0); - Empty: out std_logic; - Full: out std_logic); -end debug_fifo_2kx16; - -architecture Structure of debug_fifo_2kx16 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "debug_fifo_2kx16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "debug_fifo_2kx16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_1_0 : label is "9"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t24: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t23: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t22: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t21: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t20: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t19: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t18: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t17: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t16: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t15: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t14: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t13: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t12: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t11: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), - DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_0_1_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), - DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), - DIA6=>Data(15), DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, - ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, - ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, - ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, - CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(9), - DOB1=>Q(10), DOB2=>Q(11), DOB3=>Q(12), DOB4=>Q(13), - DOB5=>Q(14), DOB6=>Q(15), DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_121: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of debug_fifo_2kx16 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_1024x16x8.lpc b/gbe_ecp2m/ipcores/fifo_1024x16x8.lpc deleted file mode 100644 index 0bcc570..0000000 --- a/gbe_ecp2m/ipcores/fifo_1024x16x8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_1024x16x8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/05/2011 -Time=18:27:25 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=1024 -Width=18 -RDepth=2048 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_1024x16x8.vhd b/gbe_ecp2m/ipcores/fifo_1024x16x8.vhd deleted file mode 100644 index 956f91e..0000000 --- a/gbe_ecp2m/ipcores/fifo_1024x16x8.vhd +++ /dev/null @@ -1,1366 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 18 -depth 1024 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Mon Dec 5 18:27:25 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_1024x16x8 is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_1024x16x8; - -architecture Structure of fifo_1024x16x8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal rcount_w0: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal co5: std_logic; - signal wcount_10: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r8: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r9: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w9: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_1024x16x8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t23: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t22: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t21: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t20: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t19: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t18: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t17: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t16: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t15: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t14: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t13: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t12: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t11: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>w_gcount_r210, - DO0=>w_g2b_xor_cluster_0); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, - DO0=>w_g2b_xor_cluster_1); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r210, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), - DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_116: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_115: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_114: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_113: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_112: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_111: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_110: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_109: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_108: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_107: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_106: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_105: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_104: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_103: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_102: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_101: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_100: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_99: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_98: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_97: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_96: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_95: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_94: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_93: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_92: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_91: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_90: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_89: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_88: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_87: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_86: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_85: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_84: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_83: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_82: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_81: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_80: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_79: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_78: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_77: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_76: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_75: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_74: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_73: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_72: FD1P3DX - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_71: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_70: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_69: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_68: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_67: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_66: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_65: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_64: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_63: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_62: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_60: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_59: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_58: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_57: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_56: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_55: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_54: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_53: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_52: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_51: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_50: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_49: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_48: FD1P3DX - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_47: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_46: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_45: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_44: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_43: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_42: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_41: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_40: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_39: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_38: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_37: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_36: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_35: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_34: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_33: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_32: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_31: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_30: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_29: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_28: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_27: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_26: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_25: FD1S3DX - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_24: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_23: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_22: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_21: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_20: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_19: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_18: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_17: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_16: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_15: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_14: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_13: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5, - NC0=>iwcount_10, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r8, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r9, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>r_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_1024x16x8 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_1024x16x8_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_1024x16x8_tmpl.vhd deleted file mode 100644 index d7608a4..0000000 --- a/gbe_ecp2m/ipcores/fifo_1024x16x8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Mon Dec 5 18:27:25 2011 - --- parameterized module component declaration -component fifo_1024x16x8 - port (Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_1024x16x8 - port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_16kx8.vhd b/gbe_ecp2m/ipcores/fifo_16kx8.vhd deleted file mode 100644 index 12a3160..0000000 --- a/gbe_ecp2m/ipcores/fifo_16kx8.vhd +++ /dev/null @@ -1,2711 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.4 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 8 -depth 16384 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Mon Dec 6 19:08:10 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_16kx8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_16kx8; - -architecture Structure of fifo_16kx8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal co7: std_logic; - signal wcount_14: std_logic; - signal co6: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal co7_1: std_logic; - signal rcount_14: std_logic; - signal co6_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal wcount_r13: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal rcount_w13: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_16kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "1"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t30: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t29: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t28: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t27: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t26: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t25: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t24: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t23: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t22: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t21: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t20: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t19: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t18: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t17: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t16: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t15: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t14: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t13: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t12: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t11: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t10: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t9: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t8: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t7: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t6: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t5: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t4: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t3: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t2: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t1: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t0: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>w_gcount_r214, - DO0=>w_g2b_xor_cluster_0); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>w_gcount_r210, - DO0=>w_g2b_xor_cluster_1); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, - DO0=>w_g2b_xor_cluster_2); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_1); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r0); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>r_gcount_w214, - DO0=>r_g2b_xor_cluster_0); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>r_gcount_w210, - DO0=>r_g2b_xor_cluster_1); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_2); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w13); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_151: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_135: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_134: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_133: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_132: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_106: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7, - NC0=>iwcount_14, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1, - NC0=>ircount_14, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>w_g2b_xor_cluster_0, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>wcount_r13, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co6_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>rcount_w13, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co6_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_16kx8 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_2048x8.lpc b/gbe_ecp2m/ipcores/fifo_2048x8.lpc deleted file mode 100755 index 542bbe2..0000000 --- a/gbe_ecp2m/ipcores/fifo_2048x8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.2 -ModuleName=fifo_2048x8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/26/2009 -Time=00:12:59 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=2048 -Width=8 -RDepth=2048 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_2048x8.vhd b/gbe_ecp2m/ipcores/fifo_2048x8.vhd deleted file mode 100755 index 2b75855..0000000 --- a/gbe_ecp2m/ipcores/fifo_2048x8.vhd +++ /dev/null @@ -1,1913 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Sat Dec 26 00:12:59 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_2048x8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_2048x8; - -architecture Structure of fifo_2048x8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "9"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t24: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t23: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t22: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t21: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t20: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t19: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t18: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t17: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t16: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t15: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t14: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t13: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t12: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t11: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), - DOB6=>Q(6), DOB7=>Q(7), DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - FF_121: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_2048x8 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd deleted file mode 100755 index c365fcc..0000000 --- a/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 --- Sat Dec 26 00:12:59 2009 - --- parameterized module component declaration -component fifo_2048x8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_2048x8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_2048x8x16.lpc b/gbe_ecp2m/ipcores/fifo_2048x8x16.lpc deleted file mode 100644 index 4f4da58..0000000 --- a/gbe_ecp2m/ipcores/fifo_2048x8x16.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_2048x8x16 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/05/2011 -Time=18:26:53 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=2048 -Width=9 -RDepth=1024 -RWidth=18 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_2048x8x16.vhd b/gbe_ecp2m/ipcores/fifo_2048x8x16.vhd deleted file mode 100644 index 4486567..0000000 --- a/gbe_ecp2m/ipcores/fifo_2048x8x16.vhd +++ /dev/null @@ -1,1367 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 9 -depth 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -e - --- Mon Dec 5 18:26:53 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_2048x8x16 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_2048x8x16; - -architecture Structure of fifo_2048x8x16 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal wcount_r0: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal co5_1: std_logic; - signal rcount_10: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r7: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w8: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w9: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8x16.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t23: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t22: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t21: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t20: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t19: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t18: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t17: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t16: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t15: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t14: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t13: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t12: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t11: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t10: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t9: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t8: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t7: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t6: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t5: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t4: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t3: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t2: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t1: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t0: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - LUT4_29: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_28: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_27: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_26: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_25: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_24: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>r_gcount_w210, - DO0=>r_g2b_xor_cluster_0); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_1); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 9) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo, - ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, - ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, ADB11=>rptr_7, - ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, CLKB=>RdClock, - OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), - DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), - DOB11=>Q(11), DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), - DOB15=>Q(15), DOB16=>Q(16), DOB17=>Q(17)); - - FF_116: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_115: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_114: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_113: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_112: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_111: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_110: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_109: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_108: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_107: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_106: FD1P3DX - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_105: FD1P3DX - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_104: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_103: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_102: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_101: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_100: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_99: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_98: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_97: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_96: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_95: FD1P3DX - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_94: FD1P3DX - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_93: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_92: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_91: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_90: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_89: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_88: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_87: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_86: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_85: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_84: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_83: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_82: FD1P3DX - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_81: FD1P3DX - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_80: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_79: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_78: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_77: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_76: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_75: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_74: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_73: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_72: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_71: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_70: FD1P3DX - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_69: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_68: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_67: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_66: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_65: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_64: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_63: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_62: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_61: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_60: FD1P3DX - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_59: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_58: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_57: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_56: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_55: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_54: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_53: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_52: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_51: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_50: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_49: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_48: FD1P3DX - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_47: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_46: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_45: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_44: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_43: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_42: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_41: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_40: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_39: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_38: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_37: FD1S3DX - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_36: FD1S3DX - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_35: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_34: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_33: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_32: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_31: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_30: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_29: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_28: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_27: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_26: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_25: FD1S3DX - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_24: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_23: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_22: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_21: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_20: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_19: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_18: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_17: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_16: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_15: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_14: FD1S3DX - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_13: FD1S3DX - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_12: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_11: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_10: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_9: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_8: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_7: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_6: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_5: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_4: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_3: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_2: FD1S3DX - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, - NC0=>ircount_10, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1, - B1=>wcount_r2, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3, - B1=>wcount_r4, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5, - B1=>wcount_r6, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7, - B1=>w_g2b_xor_cluster_0, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9, - B1=>wcount_r10, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, - B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1, - B1=>rcount_w2, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3, - B1=>rcount_w4, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5, - B1=>rcount_w6, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w8, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_2048x8x16 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_2048x8x16_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_2048x8x16_tmpl.vhd deleted file mode 100644 index e3db862..0000000 --- a/gbe_ecp2m/ipcores/fifo_2048x8x16_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Mon Dec 5 18:26:53 2011 - --- parameterized module component declaration -component fifo_2048x8x16 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_2048x8x16 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc deleted file mode 100755 index 8c82306..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.3 -ModuleName=fifo_32kx16x8_mb -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=02/05/2010 -Time=16:48:12 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=16 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=16 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=32752 -PfDeassert=506 -RDataCount=1 -WDataCount=1 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd deleted file mode 100755 index d40ad50..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd +++ /dev/null @@ -1,5245 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 ---X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e - --- Fri Feb 05 16:48:13 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_32kx16x8_mb is - port ( - Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(7 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end fifo_32kx16x8_mb; - -architecture Structure of fifo_32kx16x8_mb is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal rcount_w0: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal rcnt_reg_15_inv: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal wptr_15: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_16: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal rcnt_reg_16: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co7: std_logic; - signal wcount_15: std_logic; - signal co6: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal wcnt_sub_0: std_logic; - signal wcnt_sub_1: std_logic; - signal wcnt_sub_2: std_logic; - signal co0_2: std_logic; - signal wcnt_sub_3: std_logic; - signal wcnt_sub_4: std_logic; - signal co1_2: std_logic; - signal wcnt_sub_5: std_logic; - signal wcnt_sub_6: std_logic; - signal co2_2: std_logic; - signal wcnt_sub_7: std_logic; - signal wcnt_sub_8: std_logic; - signal co3_2: std_logic; - signal wcnt_sub_9: std_logic; - signal wcnt_sub_10: std_logic; - signal co4_2: std_logic; - signal wcnt_sub_11: std_logic; - signal wcnt_sub_12: std_logic; - signal co5_2: std_logic; - signal wcnt_sub_13: std_logic; - signal wcnt_sub_14: std_logic; - signal co6_2: std_logic; - signal wcnt_sub_15: std_logic; - signal co7_2: std_logic; - signal wcnt_sub_msb: std_logic; - signal rcnt_sub_0: std_logic; - signal rcnt_sub_1: std_logic; - signal rcnt_sub_2: std_logic; - signal co0_3: std_logic; - signal rcnt_sub_3: std_logic; - signal rcnt_sub_4: std_logic; - signal co1_3: std_logic; - signal rcnt_sub_5: std_logic; - signal rcnt_sub_6: std_logic; - signal co2_3: std_logic; - signal rcnt_sub_7: std_logic; - signal rcnt_sub_8: std_logic; - signal co3_3: std_logic; - signal rcnt_sub_9: std_logic; - signal rcnt_sub_10: std_logic; - signal co4_3: std_logic; - signal rcnt_sub_11: std_logic; - signal rcnt_sub_12: std_logic; - signal co5_3: std_logic; - signal rcnt_sub_13: std_logic; - signal rcnt_sub_14: std_logic; - signal co6_3: std_logic; - signal rcnt_sub_15: std_logic; - signal rcnt_sub_16: std_logic; - signal co7_3: std_logic; - signal rcnt_sub_msb: std_logic; - signal co8_1d: std_logic; - signal co8_1: std_logic; - signal wfill_sub_0: std_logic; - signal wptr_0: std_logic; - signal wfill_sub_1: std_logic; - signal wfill_sub_2: std_logic; - signal co0_4: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wfill_sub_3: std_logic; - signal wfill_sub_4: std_logic; - signal co1_4: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wfill_sub_5: std_logic; - signal wfill_sub_6: std_logic; - signal co2_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wfill_sub_7: std_logic; - signal wfill_sub_8: std_logic; - signal co3_4: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wfill_sub_9: std_logic; - signal wfill_sub_10: std_logic; - signal co4_4: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wfill_sub_11: std_logic; - signal wfill_sub_12: std_logic; - signal co5_4: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wfill_sub_13: std_logic; - signal wfill_sub_14: std_logic; - signal co6_4: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wfill_sub_15: std_logic; - signal co7_4: std_logic; - signal wfill_sub_msb: std_logic; - signal rfill_sub_0: std_logic; - signal rptr_0: std_logic; - signal scuba_vhi: std_logic; - signal rfill_sub_1: std_logic; - signal rfill_sub_2: std_logic; - signal co0_5: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rfill_sub_3: std_logic; - signal rfill_sub_4: std_logic; - signal co1_5: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rfill_sub_5: std_logic; - signal rfill_sub_6: std_logic; - signal co2_5: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rfill_sub_7: std_logic; - signal rfill_sub_8: std_logic; - signal co3_5: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rfill_sub_9: std_logic; - signal rfill_sub_10: std_logic; - signal co4_5: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rfill_sub_11: std_logic; - signal rfill_sub_12: std_logic; - signal co5_5: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rfill_sub_13: std_logic; - signal rfill_sub_14: std_logic; - signal co6_5: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rfill_sub_15: std_logic; - signal rfill_sub_16: std_logic; - signal co7_5: std_logic; - signal rptr_15: std_logic; - signal rfill_sub_msb: std_logic; - signal co8_2d: std_logic; - signal co8_2: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_6: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_6: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_6: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_6: std_logic; - signal wcount_r7: std_logic; - signal wcount_r8: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_6: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_6: std_logic; - signal wcount_r11: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_6: std_logic; - signal wcount_r13: std_logic; - signal wcount_r14: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_6: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_7: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_7: std_logic; - signal rcount_w7: std_logic; - signal rcount_w8: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_7: std_logic; - signal rcount_w9: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_7: std_logic; - signal rcount_w11: std_logic; - signal rcount_w12: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w14: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_7: std_logic; - signal rcount_w15: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_14: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; - signal co0_8: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; - signal co1_8: std_logic; - signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; - signal co2_8: std_logic; - signal rcnt_reg_6: std_logic; - signal rcnt_reg_7: std_logic; - signal co3_8: std_logic; - signal rcnt_reg_8: std_logic; - signal rcnt_reg_9: std_logic; - signal co4_8: std_logic; - signal rcnt_reg_10: std_logic; - signal rcnt_reg_11: std_logic; - signal co5_8: std_logic; - signal rcnt_reg_12: std_logic; - signal rcnt_reg_13: std_logic; - signal co6_8: std_logic; - signal rcnt_reg_14: std_logic; - signal rcnt_reg_15: std_logic; - signal co7_7: std_logic; - signal ae_clrsig: std_logic; - signal ae_setsig: std_logic; - signal ae_d: std_logic; - signal ae_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_3: std_logic; - signal wcnt_reg_0: std_logic; - signal wcnt_reg_1: std_logic; - signal co0_9: std_logic; - signal wcnt_reg_2: std_logic; - signal wcnt_reg_3: std_logic; - signal co1_9: std_logic; - signal wcnt_reg_4: std_logic; - signal wcnt_reg_5: std_logic; - signal co2_9: std_logic; - signal wcnt_reg_6: std_logic; - signal wcnt_reg_7: std_logic; - signal co3_9: std_logic; - signal wcnt_reg_8: std_logic; - signal wcnt_reg_9: std_logic; - signal co4_9: std_logic; - signal wcnt_reg_10: std_logic; - signal wcnt_reg_11: std_logic; - signal co5_9: std_logic; - signal wcnt_reg_12: std_logic; - signal wcnt_reg_13: std_logic; - signal co6_9: std_logic; - signal wcnt_reg_14: std_logic; - signal wcnt_reg_15: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX41 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; SD1: in std_logic; SD2: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_52 : label is "0x6996"; - attribute initval of LUT4_51 : label is "0x6996"; - attribute initval of LUT4_50 : label is "0x6996"; - attribute initval of LUT4_49 : label is "0x6996"; - attribute initval of LUT4_48 : label is "0x6996"; - attribute initval of LUT4_47 : label is "0x6996"; - attribute initval of LUT4_46 : label is "0x6996"; - attribute initval of LUT4_45 : label is "0x6996"; - attribute initval of LUT4_44 : label is "0x6996"; - attribute initval of LUT4_43 : label is "0x6996"; - attribute initval of LUT4_42 : label is "0x6996"; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_30 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_29 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_28 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_28 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_28 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_28 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_28 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_28 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_28 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_28 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_3_28 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_27 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_27 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_27 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_27 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_27 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_27 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_27 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_27 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_27 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_4_27 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_26 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_26 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_26 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_26 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_26 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_26 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_26 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_26 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_26 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_5_26 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_25 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_25 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_25 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_25 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_25 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_25 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_25 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_25 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_25 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_6_25 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_24 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_24 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_24 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_24 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_24 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_24 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_24 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_24 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_24 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_7_24 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_23 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_23 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_23 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_23 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_23 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_23 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_23 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_23 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_23 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_0_23 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; - attribute CSDECODE_B of pdp_ram_1_1_22 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_1_22 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_1_22 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_1_22 : label is "NORMAL"; - attribute GSR of pdp_ram_1_1_22 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_1_22 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_1_22 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_1_22 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_1_22 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_1_22 : label is "2"; - attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; - attribute CSDECODE_B of pdp_ram_1_2_21 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_2_21 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_2_21 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_2_21 : label is "NORMAL"; - attribute GSR of pdp_ram_1_2_21 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_2_21 : label is "ASYNC"; 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- attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "2"; - attribute GSR of FF_236 : label is "ENABLED"; - attribute GSR of FF_235 : label is "ENABLED"; - attribute GSR of FF_234 : label is "ENABLED"; - attribute GSR of FF_233 : label is "ENABLED"; - attribute GSR of FF_232 : label is "ENABLED"; - attribute GSR of FF_231 : label is "ENABLED"; - attribute GSR of FF_230 : label is "ENABLED"; - attribute GSR of FF_229 : label is "ENABLED"; - attribute GSR of FF_228 : label is "ENABLED"; - attribute GSR of FF_227 : label is "ENABLED"; - attribute GSR of FF_226 : label is "ENABLED"; - attribute GSR of FF_225 : label is "ENABLED"; - attribute GSR of FF_224 : label is "ENABLED"; - attribute GSR of FF_223 : label is "ENABLED"; - attribute GSR of FF_222 : label is "ENABLED"; - attribute GSR of FF_221 : label is "ENABLED"; - attribute GSR of FF_220 : label is "ENABLED"; - attribute GSR of FF_219 : label is "ENABLED"; - attribute GSR of FF_218 : label is "ENABLED"; - attribute GSR of FF_217 : label is "ENABLED"; - attribute GSR of FF_216 : label is "ENABLED"; - attribute GSR of FF_215 : label is "ENABLED"; - attribute GSR of FF_214 : label is "ENABLED"; - attribute GSR of FF_213 : label is "ENABLED"; - attribute GSR of FF_212 : label is "ENABLED"; - attribute GSR of FF_211 : label is "ENABLED"; - attribute GSR of FF_210 : label is "ENABLED"; - attribute GSR of FF_209 : label is "ENABLED"; - attribute GSR of FF_208 : label is "ENABLED"; - attribute GSR of FF_207 : label is "ENABLED"; - attribute GSR of FF_206 : label is "ENABLED"; - attribute GSR of FF_205 : label is "ENABLED"; - attribute GSR of FF_204 : label is "ENABLED"; - attribute GSR of FF_203 : label is "ENABLED"; - attribute GSR of FF_202 : label is "ENABLED"; - attribute GSR of FF_201 : label is "ENABLED"; - attribute GSR of FF_200 : label is "ENABLED"; - attribute GSR of FF_199 : label is "ENABLED"; - attribute GSR of FF_198 : label is "ENABLED"; - attribute GSR of FF_197 : label is "ENABLED"; - attribute GSR of FF_196 : label is "ENABLED"; - attribute GSR of FF_195 : label is "ENABLED"; - attribute GSR of FF_194 : label is "ENABLED"; - attribute GSR of FF_193 : label is "ENABLED"; - attribute GSR of FF_192 : label is "ENABLED"; - attribute GSR of FF_191 : label is "ENABLED"; - attribute GSR of FF_190 : label is "ENABLED"; - attribute GSR of FF_189 : label is "ENABLED"; - attribute GSR of FF_188 : label is "ENABLED"; - attribute GSR of FF_187 : label is "ENABLED"; - attribute GSR of FF_186 : label is "ENABLED"; - attribute GSR of FF_185 : label is "ENABLED"; - attribute GSR of FF_184 : label is "ENABLED"; - attribute GSR of FF_183 : label is "ENABLED"; - attribute GSR of FF_182 : label is "ENABLED"; - attribute GSR of FF_181 : label is "ENABLED"; - attribute GSR of FF_180 : label is "ENABLED"; - attribute GSR of FF_179 : label is "ENABLED"; - attribute GSR of FF_178 : label is "ENABLED"; - attribute GSR of FF_177 : label is "ENABLED"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t39: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_2: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t38: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_1: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t37: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t36: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t35: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t34: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t33: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t32: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t31: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t30: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t29: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t28: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t27: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t26: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t25: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t24: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t23: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t22: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t21: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t20: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t19: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t18: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t17: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t16: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t15: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t14: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t13: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t12: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t11: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t9: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t8: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t7: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t6: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - XOR2_t5: XOR2 - port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); - - XOR2_t4: XOR2 - port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); - - XOR2_t3: XOR2 - port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - INV_0: INV - port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_3_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_4_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_5_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_6_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_7_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_1_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_2_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_3_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_4_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_5_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_6_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_7_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_1_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_2_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_3_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_4_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_5_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_6_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_7_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 2) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2, - ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, - ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, - ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_236: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_235: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_234: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_233: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_232: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_231: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_230: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_229: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_228: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_227: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_226: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_225: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_224: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_223: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_222: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_221: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_220: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_219: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_218: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_217: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_216: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_215: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_214: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_213: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_212: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_211: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_210: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_209: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_208: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_207: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_206: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_205: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_204: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_203: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_202: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_201: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_200: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_199: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_198: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_197: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_196: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_195: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_194: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_193: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_192: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_191: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_190: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_189: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_188: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_187: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_186: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_185: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_184: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_183: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_182: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_181: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_180: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_179: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_178: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_177: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_176: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_175: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_174: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_173: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_135: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_134: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_133: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_132: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_131: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_130: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_129: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_128: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_127: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_126: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_125: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_124: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_123: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_122: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_121: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_120: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_119: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_118: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_117: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_116: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_115: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_114: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_113: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_112: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_111: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_110: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_109: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_108: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_107: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_106: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_105: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_104: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_103: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_102: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_101: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_100: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_99: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_98: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_97: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_96: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_95: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_94: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_93: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_92: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_91: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_90: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_89: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_88: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_87: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_86: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_85: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_84: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_83: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_82: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_81: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_80: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_79: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_78: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_77: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_76: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_75: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_74: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_73: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_72: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_71: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_70: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); - - FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); - - FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); - - FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); - - FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); - - FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); - - FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); - - FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); - - FF_3: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>ircount_16, NC1=>open); - - mux_7: MUX41 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); - - mux_6: MUX41 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); - - mux_5: MUX41 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); - - mux_4: MUX41 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); - - mux_3: MUX41 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); - - mux_2: MUX41 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); - - mux_1: MUX41 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); - - mux_0: MUX41 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); - - wcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, - S1=>wcnt_sub_0); - - wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, - B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, - S1=>wcnt_sub_2); - - wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, - B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, - S1=>wcnt_sub_4); - - wcnt_3: FSUB2B - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, - B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, - S1=>wcnt_sub_6); - - wcnt_4: FSUB2B - port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, - B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, - S1=>wcnt_sub_8); - - wcnt_5: FSUB2B - port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, - S1=>wcnt_sub_10); - - wcnt_6: FSUB2B - port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, - S0=>wcnt_sub_11, S1=>wcnt_sub_12); - - wcnt_7: FSUB2B - port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, - S1=>wcnt_sub_14); - - wcnt_8: FSUB2B - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, - S1=>open); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, - B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, - B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, - B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcnt_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, - B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, - S1=>rcnt_sub_8); - - rcnt_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, - B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, - S1=>rcnt_sub_10); - - rcnt_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, - B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, - S1=>rcnt_sub_12); - - rcnt_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, - B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, - S1=>rcnt_sub_14); - - rcnt_8: FSUB2B - port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, - B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, - S1=>rcnt_sub_16); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); - - wfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open, - S1=>wfill_sub_0); - - wfill_1: FSUB2B - port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, - BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); - - wfill_2: FSUB2B - port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, - BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); - - wfill_3: FSUB2B - port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, - BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); - - wfill_4: FSUB2B - port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, - BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); - - wfill_5: FSUB2B - port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, - S1=>wfill_sub_10); - - wfill_6: FSUB2B - port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, - S0=>wfill_sub_11, S1=>wfill_sub_12); - - wfill_7: FSUB2B - port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, - S1=>wfill_sub_14); - - wfill_8: FSUB2B - port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, - S1=>rfill_sub_0); - - rfill_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, - BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); - - rfill_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, - BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); - - rfill_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, - BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); - - rfill_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, - BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); - - rfill_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, - BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); - - rfill_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, - B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, - S1=>rfill_sub_12); - - rfill_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, - B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, - S1=>rfill_sub_14); - - rfill_8: FSUB2B - port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, - B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, - S1=>rfill_sub_16); - - rfilld: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_6, GE=>co1_6); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_6, GE=>co2_6); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_6, GE=>co3_6); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>wcount_r8, CI=>co3_6, GE=>co4_6); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_6, GE=>co5_6); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, - B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, - B1=>wcount_r14, CI=>co6_6, GE=>co7_6); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_7, GE=>co1_7); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_7, GE=>co2_7); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_7, GE=>co3_7); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_7, GE=>co4_7); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, - B1=>rcount_w12, CI=>co4_7, GE=>co5_7); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w14, CI=>co5_7, GE=>co6_7); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, - B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); - - ae_cmp_3: AGEB2 - port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), - B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); - - ae_cmp_4: AGEB2 - port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), - B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); - - ae_cmp_5: AGEB2 - port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), - B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); - - ae_cmp_6: AGEB2 - port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), - B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); - - ae_cmp_7: AGEB2 - port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), - B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); - - ae_cmp_8: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - - af_d_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_d_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); - - af_d_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); - - af_d_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); - - af_d_cmp_3: AGEB2 - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); - - af_d_cmp_4: AGEB2 - port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), - B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); - - af_d_cmp_5: AGEB2 - port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), - B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); - - af_d_cmp_6: AGEB2 - port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), - B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); - - af_d_cmp_7: AGEB2 - port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), - B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_32kx16x8_mb is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX41 use entity ecp2m.MUX41(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.ipx b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.ipx deleted file mode 100644 index 388cfd7..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc deleted file mode 100644 index 54bda83..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc +++ /dev/null @@ -1,50 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F1152C -SpeedGrade=5 -Package=FPBGA1152 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.8 -ModuleName=fifo_32kx16x8_mb2 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=01/18/2018 -Time=18:38:11 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=18 -RDepth=65536 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=16 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=32752 -PfDeassert=506 -RDataCount=1 -WDataCount=1 -EnECC=0 - -[Command] -cmd_line= -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp deleted file mode 100644 index 047efc7..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp +++ /dev/null @@ -1,44 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.9.1.119 -Thu Jan 18 18:38:11 2018 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill - Circuit name : fifo_32kx16x8_mb2 - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : fifo_32kx16x8_mb2.edn - VHDL output : fifo_32kx16x8_mb2.vhd - VHDL template : fifo_32kx16x8_mb2_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb2.srp - Element Usage : - AGEB2 : 34 - AND2 : 4 - CU2 : 17 - FADD2B : 16 - FSUB2B : 36 - FD1P3BX : 2 - FD1P3DX : 102 - FD1S3BX : 2 - FD1S3DX : 134 - INV : 13 - MUX321 : 9 - OR2 : 1 - ROM16X1 : 181 - XOR2 : 35 - DP16KB : 32 - Estimated Resource Usage: - LUT : 499 - EBR : 32 - Reg : 240 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd deleted file mode 100644 index 09f89d5..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd +++ /dev/null @@ -1,6859 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 --- Module Version: 5.8 ---/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill - --- Thu Jan 18 18:38:11 2018 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_32kx16x8_mb2 is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(8 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end fifo_32kx16x8_mb2; - -architecture Structure of fifo_32kx16x8_mb2 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal func_and_inet: std_logic; - signal func_and_inet_1: std_logic; - signal func_and_inet_2: std_logic; - signal func_and_inet_3: std_logic; - signal func_and_inet_4: std_logic; - signal func_and_inet_5: std_logic; - signal func_and_inet_6: std_logic; - signal func_and_inet_7: std_logic; - signal func_and_inet_8: std_logic; - signal func_and_inet_9: std_logic; - signal func_and_inet_10: std_logic; - signal func_and_inet_11: std_logic; - signal func_and_inet_12: std_logic; - signal func_and_inet_13: std_logic; - signal func_and_inet_14: std_logic; - signal func_and_inet_15: std_logic; - signal func_and_inet_16: std_logic; - signal func_and_inet_17: std_logic; - signal func_and_inet_18: std_logic; - signal func_and_inet_19: std_logic; - signal func_and_inet_20: std_logic; - signal func_and_inet_21: std_logic; - signal func_and_inet_22: std_logic; - signal func_and_inet_23: std_logic; - signal func_and_inet_24: std_logic; - signal func_and_inet_25: std_logic; - signal func_and_inet_26: std_logic; - signal func_and_inet_27: std_logic; - signal func_and_inet_28: std_logic; - signal func_and_inet_29: std_logic; - signal wptr_14_inv: std_logic; - signal func_and_inet_30: std_logic; - signal rptr_15_inv: std_logic; - signal func_and_inet_31: std_logic; - signal func_and_inet_32: std_logic; - signal func_and_inet_33: std_logic; - signal func_and_inet_34: std_logic; - signal func_and_inet_35: std_logic; - signal func_and_inet_36: std_logic; - signal func_and_inet_37: std_logic; - signal func_and_inet_38: std_logic; - signal func_and_inet_39: std_logic; - signal func_and_inet_40: std_logic; - signal func_and_inet_41: std_logic; - signal func_and_inet_42: std_logic; - signal func_and_inet_43: std_logic; - signal func_and_inet_44: std_logic; - signal func_and_inet_45: std_logic; - signal wptr_13_inv: std_logic; - signal func_and_inet_46: std_logic; - signal rptr_14_inv: std_logic; - signal func_and_inet_47: std_logic; - signal func_and_inet_48: std_logic; - signal func_and_inet_49: std_logic; - signal func_and_inet_50: std_logic; - signal func_and_inet_51: std_logic; - signal func_and_inet_52: std_logic; - signal func_and_inet_53: std_logic; - signal wptr_12_inv: std_logic; - signal func_and_inet_54: std_logic; - signal rptr_13_inv: std_logic; - signal func_and_inet_55: std_logic; - signal func_and_inet_56: std_logic; - signal func_and_inet_57: std_logic; - signal wptr_11_inv: std_logic; - signal func_and_inet_58: std_logic; - signal rptr_12_inv: std_logic; - signal func_and_inet_59: std_logic; - signal wptr_10_inv: std_logic; - signal func_and_inet_60: std_logic; - signal rptr_11_inv: std_logic; - signal func_and_inet_61: std_logic; - signal func_and_inet_62: std_logic; - signal func_and_inet_63: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal rcount_w0: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal rcnt_reg_15_inv: std_logic; - signal dec1_r10: std_logic; - signal dec0_p00: std_logic; - signal dec3_r11: std_logic; - signal dec2_p01: std_logic; - signal dec5_r12: std_logic; - signal dec4_p02: std_logic; - signal dec7_r13: std_logic; - signal dec6_p03: std_logic; - signal dec9_r14: std_logic; - signal dec8_p04: std_logic; - signal dec11_r15: std_logic; - signal dec10_p05: std_logic; - signal dec13_r16: std_logic; - signal dec12_p06: std_logic; - signal dec15_r17: std_logic; - signal dec14_p07: std_logic; - signal dec17_r18: std_logic; - signal dec16_p08: std_logic; - signal dec19_r19: std_logic; - signal dec18_p09: std_logic; - signal dec21_r110: std_logic; - signal dec20_p010: std_logic; - signal dec23_r111: std_logic; - signal dec22_p011: std_logic; - signal dec25_r112: std_logic; - signal dec24_p012: std_logic; - signal dec27_r113: std_logic; - signal dec26_p013: std_logic; - signal dec29_r114: std_logic; - signal dec28_p014: std_logic; - signal dec31_r115: std_logic; - signal dec30_p015: std_logic; - signal dec33_r116: std_logic; - signal dec32_p016: std_logic; - signal dec35_r117: std_logic; - signal dec34_p017: std_logic; - signal dec37_r118: std_logic; - signal dec36_p018: std_logic; - signal dec39_r119: std_logic; - signal dec38_p019: std_logic; - signal dec41_r120: std_logic; - signal dec40_p020: std_logic; - signal dec43_r121: std_logic; - signal dec42_p021: std_logic; - signal dec45_r122: std_logic; - signal dec44_p022: std_logic; - signal dec47_r123: std_logic; - signal dec46_p023: std_logic; - signal dec49_r124: std_logic; - signal dec48_p024: std_logic; - signal dec51_r125: std_logic; - signal dec50_p025: std_logic; - signal dec53_r126: std_logic; - signal dec52_p026: std_logic; - signal dec55_r127: std_logic; - signal dec54_p027: std_logic; - signal dec57_r128: std_logic; - signal dec56_p028: std_logic; - signal dec59_r129: std_logic; - signal dec58_p029: std_logic; - signal dec61_r130: std_logic; - signal dec60_p030: std_logic; - signal dec63_r131: std_logic; - signal dec62_p031: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal wptr_15: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_16: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal rcnt_reg_16: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co7: std_logic; - signal co6: std_logic; - signal wcount_15: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8: std_logic; - signal co7_1: std_logic; - signal rcount_16: std_logic; - signal mdout1_31_0: std_logic; - signal mdout1_30_0: std_logic; - signal mdout1_29_0: std_logic; - signal mdout1_28_0: std_logic; - signal mdout1_27_0: std_logic; - signal mdout1_26_0: std_logic; - signal mdout1_25_0: std_logic; - signal mdout1_24_0: std_logic; - signal mdout1_23_0: std_logic; - signal mdout1_22_0: std_logic; - signal mdout1_21_0: std_logic; - signal mdout1_20_0: std_logic; - signal mdout1_19_0: std_logic; - signal mdout1_18_0: std_logic; - signal mdout1_17_0: std_logic; - signal mdout1_16_0: std_logic; - signal mdout1_15_0: std_logic; - signal mdout1_14_0: std_logic; - signal mdout1_13_0: std_logic; - signal mdout1_12_0: std_logic; - signal mdout1_11_0: std_logic; - signal mdout1_10_0: std_logic; - signal mdout1_9_0: std_logic; - signal mdout1_8_0: std_logic; - signal mdout1_7_0: std_logic; - signal mdout1_6_0: std_logic; - signal mdout1_5_0: std_logic; - signal mdout1_4_0: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_31_1: std_logic; - signal mdout1_30_1: std_logic; - signal mdout1_29_1: std_logic; - signal mdout1_28_1: std_logic; - signal mdout1_27_1: std_logic; - signal mdout1_26_1: std_logic; - signal mdout1_25_1: std_logic; - signal mdout1_24_1: std_logic; - signal mdout1_23_1: std_logic; - signal mdout1_22_1: std_logic; - signal mdout1_21_1: std_logic; - signal mdout1_20_1: std_logic; - signal mdout1_19_1: std_logic; - signal mdout1_18_1: std_logic; - signal mdout1_17_1: std_logic; - signal mdout1_16_1: std_logic; - signal mdout1_15_1: std_logic; - signal mdout1_14_1: std_logic; - signal mdout1_13_1: std_logic; - signal mdout1_12_1: std_logic; - signal mdout1_11_1: std_logic; - signal mdout1_10_1: std_logic; - signal mdout1_9_1: std_logic; - signal mdout1_8_1: std_logic; - signal mdout1_7_1: std_logic; - signal mdout1_6_1: std_logic; - signal mdout1_5_1: std_logic; - signal mdout1_4_1: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_31_2: std_logic; - signal mdout1_30_2: std_logic; - signal mdout1_29_2: std_logic; - signal mdout1_28_2: std_logic; - signal mdout1_27_2: std_logic; - signal mdout1_26_2: std_logic; - signal mdout1_25_2: std_logic; - signal mdout1_24_2: std_logic; - signal mdout1_23_2: std_logic; - signal mdout1_22_2: std_logic; - signal mdout1_21_2: std_logic; - signal mdout1_20_2: std_logic; - signal mdout1_19_2: std_logic; - signal mdout1_18_2: std_logic; - signal mdout1_17_2: std_logic; - signal mdout1_16_2: std_logic; - signal mdout1_15_2: std_logic; - signal mdout1_14_2: std_logic; - signal mdout1_13_2: std_logic; - signal mdout1_12_2: std_logic; - signal mdout1_11_2: std_logic; - signal mdout1_10_2: std_logic; - signal mdout1_9_2: std_logic; - signal mdout1_8_2: std_logic; - signal mdout1_7_2: std_logic; - signal mdout1_6_2: std_logic; - signal mdout1_5_2: std_logic; - signal mdout1_4_2: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_31_3: std_logic; - signal mdout1_30_3: std_logic; - signal mdout1_29_3: std_logic; - signal mdout1_28_3: std_logic; - signal mdout1_27_3: std_logic; - signal mdout1_26_3: std_logic; - signal mdout1_25_3: std_logic; - signal mdout1_24_3: std_logic; - signal mdout1_23_3: std_logic; - signal mdout1_22_3: std_logic; - signal mdout1_21_3: std_logic; - signal mdout1_20_3: std_logic; - signal mdout1_19_3: std_logic; - signal mdout1_18_3: std_logic; - signal mdout1_17_3: std_logic; - signal mdout1_16_3: std_logic; - signal mdout1_15_3: std_logic; - signal mdout1_14_3: std_logic; - signal mdout1_13_3: std_logic; - signal mdout1_12_3: std_logic; - signal mdout1_11_3: std_logic; - signal mdout1_10_3: std_logic; - signal mdout1_9_3: std_logic; - signal mdout1_8_3: std_logic; - signal mdout1_7_3: std_logic; - signal mdout1_6_3: std_logic; - signal mdout1_5_3: std_logic; - signal mdout1_4_3: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_31_4: std_logic; - signal mdout1_30_4: std_logic; - signal mdout1_29_4: std_logic; - signal mdout1_28_4: std_logic; - signal mdout1_27_4: std_logic; - signal mdout1_26_4: std_logic; - signal mdout1_25_4: std_logic; - signal mdout1_24_4: std_logic; - signal mdout1_23_4: std_logic; - signal mdout1_22_4: std_logic; - signal mdout1_21_4: std_logic; - signal mdout1_20_4: std_logic; - signal mdout1_19_4: std_logic; - signal mdout1_18_4: std_logic; - signal mdout1_17_4: std_logic; - signal mdout1_16_4: std_logic; - signal mdout1_15_4: std_logic; - signal mdout1_14_4: std_logic; - signal mdout1_13_4: std_logic; - signal mdout1_12_4: std_logic; - signal mdout1_11_4: std_logic; - signal mdout1_10_4: std_logic; - signal mdout1_9_4: std_logic; - signal mdout1_8_4: std_logic; - signal mdout1_7_4: std_logic; - signal mdout1_6_4: std_logic; - signal mdout1_5_4: std_logic; - signal mdout1_4_4: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_31_5: std_logic; - signal mdout1_30_5: std_logic; - signal mdout1_29_5: std_logic; - signal mdout1_28_5: std_logic; - signal mdout1_27_5: std_logic; - signal mdout1_26_5: std_logic; - signal mdout1_25_5: std_logic; - signal mdout1_24_5: std_logic; - signal mdout1_23_5: std_logic; - signal mdout1_22_5: std_logic; - signal mdout1_21_5: std_logic; - signal mdout1_20_5: std_logic; - signal mdout1_19_5: std_logic; - signal mdout1_18_5: std_logic; - signal mdout1_17_5: std_logic; - signal mdout1_16_5: std_logic; - signal mdout1_15_5: std_logic; - signal mdout1_14_5: std_logic; - signal mdout1_13_5: std_logic; - signal mdout1_12_5: std_logic; - signal mdout1_11_5: std_logic; - signal mdout1_10_5: std_logic; - signal mdout1_9_5: std_logic; - signal mdout1_8_5: std_logic; - signal mdout1_7_5: std_logic; - signal mdout1_6_5: std_logic; - signal mdout1_5_5: std_logic; - signal mdout1_4_5: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_31_6: std_logic; - signal mdout1_30_6: std_logic; - signal mdout1_29_6: std_logic; - signal mdout1_28_6: std_logic; - signal mdout1_27_6: std_logic; - signal mdout1_26_6: std_logic; - signal mdout1_25_6: std_logic; - signal mdout1_24_6: std_logic; - signal mdout1_23_6: std_logic; - signal mdout1_22_6: std_logic; - signal mdout1_21_6: std_logic; - signal mdout1_20_6: std_logic; - signal mdout1_19_6: std_logic; - signal mdout1_18_6: std_logic; - signal mdout1_17_6: std_logic; - signal mdout1_16_6: std_logic; - signal mdout1_15_6: std_logic; - signal mdout1_14_6: std_logic; - signal mdout1_13_6: std_logic; - signal mdout1_12_6: std_logic; - signal mdout1_11_6: std_logic; - signal mdout1_10_6: std_logic; - signal mdout1_9_6: std_logic; - signal mdout1_8_6: std_logic; - signal mdout1_7_6: std_logic; - signal mdout1_6_6: std_logic; - signal mdout1_5_6: std_logic; - signal mdout1_4_6: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_31_7: std_logic; - signal mdout1_30_7: std_logic; - signal mdout1_29_7: std_logic; - signal mdout1_28_7: std_logic; - signal mdout1_27_7: std_logic; - signal mdout1_26_7: std_logic; - signal mdout1_25_7: std_logic; - signal mdout1_24_7: std_logic; - signal mdout1_23_7: std_logic; - signal mdout1_22_7: std_logic; - signal mdout1_21_7: std_logic; - signal mdout1_20_7: std_logic; - signal mdout1_19_7: std_logic; - signal mdout1_18_7: std_logic; - signal mdout1_17_7: std_logic; - signal mdout1_16_7: std_logic; - signal mdout1_15_7: std_logic; - signal mdout1_14_7: std_logic; - signal mdout1_13_7: std_logic; - signal mdout1_12_7: std_logic; - signal mdout1_11_7: std_logic; - signal mdout1_10_7: std_logic; - signal mdout1_9_7: std_logic; - signal mdout1_8_7: std_logic; - signal mdout1_7_7: std_logic; - signal mdout1_6_7: std_logic; - signal mdout1_5_7: std_logic; - signal mdout1_4_7: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal rptr_13_ff: std_logic; - signal rptr_12_ff: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_31_8: std_logic; - signal mdout1_30_8: std_logic; - signal mdout1_29_8: std_logic; - signal mdout1_28_8: std_logic; - signal mdout1_27_8: std_logic; - signal mdout1_26_8: std_logic; - signal mdout1_25_8: std_logic; - signal mdout1_24_8: std_logic; - signal mdout1_23_8: std_logic; - signal mdout1_22_8: std_logic; - signal mdout1_21_8: std_logic; - signal mdout1_20_8: std_logic; - signal mdout1_19_8: std_logic; - signal mdout1_18_8: std_logic; - signal mdout1_17_8: std_logic; - signal mdout1_16_8: std_logic; - signal mdout1_15_8: std_logic; - signal mdout1_14_8: std_logic; - signal mdout1_13_8: std_logic; - signal mdout1_12_8: std_logic; - signal mdout1_11_8: std_logic; - signal mdout1_10_8: std_logic; - signal mdout1_9_8: std_logic; - signal mdout1_8_8: std_logic; - signal mdout1_7_8: std_logic; - signal mdout1_6_8: std_logic; - signal mdout1_5_8: std_logic; - signal mdout1_4_8: std_logic; - signal mdout1_3_8: std_logic; - signal mdout1_2_8: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal wcnt_sub_0: std_logic; - signal precin: std_logic; - signal wcnt_sub_1: std_logic; - signal wcnt_sub_2: std_logic; - signal co0_2: std_logic; - signal wcnt_sub_3: std_logic; - signal wcnt_sub_4: std_logic; - signal co1_2: std_logic; - signal wcnt_sub_5: std_logic; - signal wcnt_sub_6: std_logic; - signal co2_2: std_logic; - signal wcnt_sub_7: std_logic; - signal wcnt_sub_8: std_logic; - signal co3_2: std_logic; - signal wcnt_sub_9: std_logic; - signal wcnt_sub_10: std_logic; - signal co4_2: std_logic; - signal wcnt_sub_11: std_logic; - signal wcnt_sub_12: std_logic; - signal co5_2: std_logic; - signal wcnt_sub_13: std_logic; - signal wcnt_sub_14: std_logic; - signal co6_2: std_logic; - signal wcnt_sub_15: std_logic; - signal co7_2: std_logic; - signal wcnt_sub_msb: std_logic; - signal rcnt_sub_0: std_logic; - signal precin_1: std_logic; - signal rcnt_sub_1: std_logic; - signal rcnt_sub_2: std_logic; - signal co0_3: std_logic; - signal rcnt_sub_3: std_logic; - signal rcnt_sub_4: std_logic; - signal co1_3: std_logic; - signal rcnt_sub_5: std_logic; - signal rcnt_sub_6: std_logic; - signal co2_3: std_logic; - signal rcnt_sub_7: std_logic; - signal rcnt_sub_8: std_logic; - signal co3_3: std_logic; - signal rcnt_sub_9: std_logic; - signal rcnt_sub_10: std_logic; - signal co4_3: std_logic; - signal rcnt_sub_11: std_logic; - signal rcnt_sub_12: std_logic; - signal co5_3: std_logic; - signal rcnt_sub_13: std_logic; - signal rcnt_sub_14: std_logic; - signal co6_3: std_logic; - signal rcnt_sub_15: std_logic; - signal rcnt_sub_16: std_logic; - signal co7_3: std_logic; - signal rcnt_sub_msb: std_logic; - signal co8_1d: std_logic; - signal co8_1: std_logic; - signal wfill_sub_0: std_logic; - signal precin_2: std_logic; - signal wptr_0: std_logic; - signal wfill_sub_1: std_logic; - signal wfill_sub_2: std_logic; - signal co0_4: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wfill_sub_3: std_logic; - signal wfill_sub_4: std_logic; - signal co1_4: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wfill_sub_5: std_logic; - signal wfill_sub_6: std_logic; - signal co2_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wfill_sub_7: std_logic; - signal wfill_sub_8: std_logic; - signal co3_4: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wfill_sub_9: std_logic; - signal wfill_sub_10: std_logic; - signal co4_4: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wfill_sub_11: std_logic; - signal wfill_sub_12: std_logic; - signal co5_4: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wfill_sub_13: std_logic; - signal wfill_sub_14: std_logic; - signal co6_4: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wfill_sub_15: std_logic; - signal co7_4: std_logic; - signal wfill_sub_msb: std_logic; - signal rfill_sub_0: std_logic; - signal precin_3: std_logic; - signal rptr_0: std_logic; - signal scuba_vhi: std_logic; - signal rfill_sub_1: std_logic; - signal rfill_sub_2: std_logic; - signal co0_5: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rfill_sub_3: std_logic; - signal rfill_sub_4: std_logic; - signal co1_5: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rfill_sub_5: std_logic; - signal rfill_sub_6: std_logic; - signal co2_5: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rfill_sub_7: std_logic; - signal rfill_sub_8: std_logic; - signal co3_5: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rfill_sub_9: std_logic; - signal rfill_sub_10: std_logic; - signal co4_5: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rfill_sub_11: std_logic; - signal rfill_sub_12: std_logic; - signal co5_5: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rfill_sub_13: std_logic; - signal rfill_sub_14: std_logic; - signal co6_5: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rfill_sub_15: std_logic; - signal rfill_sub_16: std_logic; - signal co7_5: std_logic; - signal rptr_15: std_logic; - signal rfill_sub_msb: std_logic; - signal co8_2d: std_logic; - signal co8_2: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_6: std_logic; - signal wcount_r1: std_logic; - signal wcount_r2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_6: std_logic; - signal wcount_r3: std_logic; - signal wcount_r4: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_6: std_logic; - signal wcount_r5: std_logic; - signal wcount_r6: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_6: std_logic; - signal wcount_r7: std_logic; - signal wcount_r8: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_6: std_logic; - signal wcount_r9: std_logic; - signal wcount_r10: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_6: std_logic; - signal wcount_r11: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_6: std_logic; - signal wcount_r13: std_logic; - signal wcount_r14: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_6: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w1: std_logic; - signal rcount_w2: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w3: std_logic; - signal rcount_w4: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_7: std_logic; - signal rcount_w5: std_logic; - signal rcount_w6: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_7: std_logic; - signal rcount_w7: std_logic; - signal rcount_w8: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_7: std_logic; - signal rcount_w9: std_logic; - signal rcount_w10: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_7: std_logic; - signal rcount_w11: std_logic; - signal rcount_w12: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w14: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_7: std_logic; - signal rcount_w15: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_14: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; - signal co0_8: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; - signal co1_8: std_logic; - signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; - signal co2_8: std_logic; - signal rcnt_reg_6: std_logic; - signal rcnt_reg_7: std_logic; - signal co3_8: std_logic; - signal rcnt_reg_8: std_logic; - signal rcnt_reg_9: std_logic; - signal co4_8: std_logic; - signal rcnt_reg_10: std_logic; - signal rcnt_reg_11: std_logic; - signal co5_8: std_logic; - signal rcnt_reg_12: std_logic; - signal rcnt_reg_13: std_logic; - signal co6_8: std_logic; - signal rcnt_reg_14: std_logic; - signal rcnt_reg_15: std_logic; - signal co7_7: std_logic; - signal ae_clrsig: std_logic; - signal ae_setsig: std_logic; - signal ae_d: std_logic; - signal ae_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_3: std_logic; - signal wcnt_reg_0: std_logic; - signal wcnt_reg_1: std_logic; - signal co0_9: std_logic; - signal wcnt_reg_2: std_logic; - signal wcnt_reg_3: std_logic; - signal co1_9: std_logic; - signal wcnt_reg_4: std_logic; - signal wcnt_reg_5: std_logic; - signal co2_9: std_logic; - signal wcnt_reg_6: std_logic; - signal wcnt_reg_7: std_logic; - signal co3_9: std_logic; - signal wcnt_reg_8: std_logic; - signal wcnt_reg_9: std_logic; - signal co4_9: std_logic; - signal wcnt_reg_10: std_logic; - signal wcnt_reg_11: std_logic; - signal co5_9: std_logic; - signal wcnt_reg_12: std_logic; - signal wcnt_reg_13: std_logic; - signal co6_9: std_logic; - signal wcnt_reg_14: std_logic; - signal wcnt_reg_15: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX321 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; D4: in std_logic; D5: in std_logic; - D6: in std_logic; D7: in std_logic; D8: in std_logic; - D9: in std_logic; D10: in std_logic; D11: in std_logic; - D12: in std_logic; D13: in std_logic; D14: in std_logic; - D15: in std_logic; D16: in std_logic; D17: in std_logic; - D18: in std_logic; D19: in std_logic; D20: in std_logic; - D21: in std_logic; D22: in std_logic; D23: in std_logic; - D24: in std_logic; D25: in std_logic; D26: in std_logic; - D27: in std_logic; D28: in std_logic; D29: in std_logic; - D30: in std_logic; D31: in std_logic; SD1: in std_logic; - SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; - SD5: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_180 : label is "0x8000"; - attribute initval of LUT4_179 : label is "0x8000"; - attribute initval of LUT4_178 : label is "0x8000"; - attribute initval of LUT4_177 : label is "0x8000"; - attribute initval of LUT4_176 : label is "0x8000"; - attribute initval of LUT4_175 : label is "0x8000"; - attribute initval of LUT4_174 : label is "0x8000"; - attribute initval of LUT4_173 : label is "0x8000"; - attribute initval of LUT4_172 : label is "0x8000"; - attribute initval of LUT4_171 : label is "0x8000"; - attribute initval of LUT4_170 : label is "0x8000"; - attribute initval of LUT4_169 : label is "0x8000"; - attribute initval of LUT4_168 : label is "0x8000"; - attribute initval of LUT4_167 : label is "0x8000"; - attribute initval of LUT4_166 : label is "0x8000"; - attribute initval of LUT4_165 : label is "0x8000"; - attribute initval of LUT4_164 : label is "0x8000"; - attribute initval of LUT4_163 : label is "0x8000"; - attribute initval of LUT4_162 : label is "0x8000"; - attribute initval of LUT4_161 : label is "0x8000"; - attribute initval of LUT4_160 : label is "0x8000"; - attribute initval of LUT4_159 : label is "0x8000"; - attribute initval of LUT4_158 : label is "0x8000"; - attribute initval of LUT4_157 : label is "0x8000"; - attribute initval of LUT4_156 : label is "0x8000"; - attribute initval of LUT4_155 : label is "0x8000"; - attribute initval of LUT4_154 : label is "0x8000"; - attribute initval of LUT4_153 : label is "0x8000"; - attribute initval of LUT4_152 : label is "0x8000"; - attribute initval of LUT4_151 : label is "0x8000"; - attribute initval of LUT4_150 : label is "0x8000"; - attribute initval of LUT4_149 : label is "0x8000"; - attribute initval of LUT4_148 : label is "0x8000"; - attribute initval of LUT4_147 : label is "0x8000"; - attribute initval of LUT4_146 : label is "0x8000"; - attribute initval of LUT4_145 : label is "0x8000"; - attribute initval of LUT4_144 : label is "0x8000"; - attribute initval of LUT4_143 : label is "0x8000"; - attribute initval of LUT4_142 : label is "0x8000"; - attribute initval of LUT4_141 : label is "0x8000"; - attribute initval of LUT4_140 : label is "0x8000"; - attribute initval of LUT4_139 : label is "0x8000"; - attribute initval of LUT4_138 : label is "0x8000"; - attribute initval of LUT4_137 : label is "0x8000"; - attribute initval of LUT4_136 : label is "0x8000"; - attribute initval of LUT4_135 : label is "0x8000"; - attribute initval of LUT4_134 : label is "0x8000"; - attribute initval of LUT4_133 : label is "0x8000"; - attribute initval of LUT4_132 : label is "0x8000"; - attribute initval of LUT4_131 : label is "0x8000"; - attribute initval of LUT4_130 : label is "0x8000"; - attribute initval of LUT4_129 : label is "0x8000"; - attribute initval of LUT4_128 : label is "0x8000"; - attribute initval of LUT4_127 : label is "0x8000"; - attribute initval of LUT4_126 : label is "0x8000"; - attribute initval of LUT4_125 : label is "0x8000"; - attribute initval of LUT4_124 : label is "0x8000"; - attribute initval of LUT4_123 : label is "0x8000"; - attribute initval of LUT4_122 : label is "0x8000"; - attribute initval of LUT4_121 : label is "0x8000"; - attribute initval of LUT4_120 : label is "0x8000"; - attribute initval of LUT4_119 : label is "0x8000"; - attribute initval of LUT4_118 : label is "0x8000"; - attribute initval of LUT4_117 : label is "0x8000"; - attribute initval of LUT4_116 : label is "0x8000"; - attribute initval of LUT4_115 : label is "0x8000"; - attribute initval of LUT4_114 : label is "0x8000"; - attribute initval of LUT4_113 : label is "0x8000"; - attribute initval of LUT4_112 : label is "0x8000"; - attribute initval of LUT4_111 : label is "0x8000"; - attribute initval of LUT4_110 : label is "0x8000"; - attribute initval of LUT4_109 : label is "0x8000"; - attribute initval of LUT4_108 : label is "0x8000"; - attribute initval of LUT4_107 : label is "0x8000"; - attribute initval of LUT4_106 : label is "0x8000"; - attribute initval of LUT4_105 : label is "0x8000"; - attribute initval of LUT4_104 : label is "0x8000"; - attribute initval of LUT4_103 : label is "0x8000"; - attribute initval of LUT4_102 : label is "0x8000"; - attribute initval of LUT4_101 : label is "0x8000"; - attribute initval of LUT4_100 : label is "0x8000"; - attribute initval of LUT4_99 : label is "0x8000"; - attribute initval of LUT4_98 : label is "0x8000"; - attribute initval of LUT4_97 : label is "0x8000"; - attribute initval of LUT4_96 : label is "0x8000"; - attribute initval of LUT4_95 : label is "0x8000"; - attribute initval of LUT4_94 : label is "0x8000"; - attribute initval of LUT4_93 : label is "0x8000"; - attribute initval of LUT4_92 : label is "0x8000"; - attribute initval of LUT4_91 : label is "0x8000"; - attribute initval of LUT4_90 : label is "0x8000"; - attribute initval of LUT4_89 : label is "0x8000"; - attribute initval of LUT4_88 : label is "0x8000"; - attribute initval of LUT4_87 : label is "0x8000"; - attribute initval of LUT4_86 : label is "0x8000"; - attribute initval of LUT4_85 : label is "0x8000"; - attribute initval of LUT4_84 : label is "0x8000"; - attribute initval of LUT4_83 : label is "0x8000"; - attribute initval of LUT4_82 : label is "0x8000"; - attribute initval of LUT4_81 : label is "0x8000"; - attribute initval of LUT4_80 : label is "0x8000"; - attribute initval of LUT4_79 : label is "0x8000"; - attribute initval of LUT4_78 : label is "0x8000"; - attribute initval of LUT4_77 : label is "0x8000"; - attribute initval of LUT4_76 : label is "0x8000"; - attribute initval of LUT4_75 : label is "0x8000"; - attribute initval of LUT4_74 : label is "0x8000"; - attribute initval of LUT4_73 : label is "0x8000"; - attribute initval of LUT4_72 : label is "0x8000"; - attribute initval of LUT4_71 : label is "0x8000"; - attribute initval of LUT4_70 : label is "0x8000"; - attribute initval of LUT4_69 : label is "0x8000"; - attribute initval of LUT4_68 : label is "0x8000"; - attribute initval of LUT4_67 : label is "0x8000"; - attribute initval of LUT4_66 : label is "0x8000"; - attribute initval of LUT4_65 : label is "0x8000"; - attribute initval of LUT4_64 : label is "0x8000"; - attribute initval of LUT4_63 : label is "0x8000"; - attribute initval of LUT4_62 : label is "0x8000"; - attribute initval of LUT4_61 : label is "0x8000"; - attribute initval of LUT4_60 : label is "0x8000"; - attribute initval of LUT4_59 : label is "0x8000"; - attribute initval of LUT4_58 : label is "0x8000"; - attribute initval of LUT4_57 : label is "0x8000"; - attribute initval of LUT4_56 : label is "0x8000"; - attribute initval of LUT4_55 : label is "0x8000"; - attribute initval of LUT4_54 : label is "0x8000"; - attribute initval of LUT4_53 : label is "0x8000"; - attribute initval of LUT4_52 : label is "0x6996"; - attribute initval of LUT4_51 : label is "0x6996"; - attribute initval of LUT4_50 : label is "0x6996"; - attribute initval of LUT4_49 : label is "0x6996"; - attribute initval of LUT4_48 : label is "0x6996"; - attribute initval of LUT4_47 : label is "0x6996"; - attribute initval of LUT4_46 : label is "0x6996"; - attribute initval of LUT4_45 : label is "0x6996"; - attribute initval of LUT4_44 : label is "0x6996"; - attribute initval of LUT4_43 : label is "0x6996"; - attribute initval of LUT4_42 : label is "0x6996"; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "18"; - attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_30 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_30 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_30 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_30 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_30 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_30 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_30 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_30 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_30 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_1_0_30 : label is "18"; - attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; - attribute CSDECODE_B of pdp_ram_2_0_29 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_2_0_29 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_2_0_29 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_0_29 : label is "NORMAL"; - attribute GSR of pdp_ram_2_0_29 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_0_29 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_0_29 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_0_29 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_0_29 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_2_0_29 : label is "18"; - attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; - attribute CSDECODE_B of pdp_ram_3_0_28 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_3_0_28 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_3_0_28 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_0_28 : label is "NORMAL"; - attribute GSR of pdp_ram_3_0_28 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_0_28 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_0_28 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_0_28 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_0_28 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_3_0_28 : label is "18"; - attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; - attribute CSDECODE_B of pdp_ram_4_0_27 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_4_0_27 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_4_0_27 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_4_0_27 : label is "NORMAL"; - attribute GSR of pdp_ram_4_0_27 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_4_0_27 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_4_0_27 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_4_0_27 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_4_0_27 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_4_0_27 : label is "18"; - attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; - attribute CSDECODE_B of pdp_ram_5_0_26 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_5_0_26 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_5_0_26 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_5_0_26 : label is "NORMAL"; - attribute GSR of pdp_ram_5_0_26 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_5_0_26 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_5_0_26 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_5_0_26 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_5_0_26 : label is "9"; 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- attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; - attribute CSDECODE_B of pdp_ram_10_0_21 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_10_0_21 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_10_0_21 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_10_0_21 : label is "NORMAL"; - attribute GSR of pdp_ram_10_0_21 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_10_0_21 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_10_0_21 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_10_0_21 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_10_0_21 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_10_0_21 : label is "18"; - attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx16x8_mb2.lpc"; - attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; - attribute CSDECODE_B of pdp_ram_11_0_20 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_11_0_20 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_11_0_20 : label is "NORMAL"; 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- attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t39: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_12: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t38: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_11: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t37: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t36: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t35: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t34: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t33: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t32: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t31: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t30: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t29: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t28: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t27: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t26: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t25: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t24: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t23: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t22: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t21: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t20: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t19: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t18: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t17: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t16: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t15: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t14: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t13: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t12: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t11: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t9: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t8: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t7: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t6: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - INV_10: INV - port map (A=>wptr_10, Z=>wptr_10_inv); - - INV_9: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_8: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_7: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_6: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - LUT4_180: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet); - - LUT4_179: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_p00); - - INV_5: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_4: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_3: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_2: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - INV_1: INV - port map (A=>rptr_15, Z=>rptr_15_inv); - - LUT4_178: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_1); - - LUT4_177: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec1_r10); - - LUT4_176: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_2); - - LUT4_175: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec2_p01); - - LUT4_174: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_3); - - LUT4_173: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec3_r11); - - LUT4_172: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_4); - - LUT4_171: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec4_p02); - - LUT4_170: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_5); - - LUT4_169: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec5_r12); - - LUT4_168: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_6); - - LUT4_167: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec6_p03); - - LUT4_166: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_7); - - LUT4_165: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec7_r13); - - LUT4_164: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_8); - - LUT4_163: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec8_p04); - - LUT4_162: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_9); - - LUT4_161: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec9_r14); - - LUT4_160: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_10); - - LUT4_159: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - - LUT4_158: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_11); - - LUT4_157: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - - LUT4_156: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_12); - - LUT4_155: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - - LUT4_154: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_13); - - LUT4_153: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - - LUT4_152: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_14); - - LUT4_151: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - - LUT4_150: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_15); - - LUT4_149: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - - LUT4_148: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_16); - - LUT4_147: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - - LUT4_146: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_17); - - LUT4_145: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - - LUT4_144: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_18); - - LUT4_143: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - - LUT4_142: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_19); - - LUT4_141: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - - LUT4_140: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_20); - - LUT4_139: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - - LUT4_138: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_21); - - LUT4_137: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - - LUT4_136: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_22); - - LUT4_135: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - - LUT4_134: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_23); - - LUT4_133: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - - LUT4_132: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_24); - - LUT4_131: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - - LUT4_130: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_25); - - LUT4_129: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - - LUT4_128: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_26); - - LUT4_127: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - - LUT4_126: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_27); - - LUT4_125: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - - LUT4_124: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_28); - - LUT4_123: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - - LUT4_122: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_29); - - LUT4_121: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - - LUT4_120: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_30); - - LUT4_119: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - - LUT4_118: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_31); - - LUT4_117: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - - LUT4_116: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_32); - - LUT4_115: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec32_p016); - - LUT4_114: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_33); - - LUT4_113: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec33_r116); - - LUT4_112: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_34); - - LUT4_111: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec34_p017); - - LUT4_110: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_35); - - LUT4_109: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec35_r117); - - LUT4_108: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_36); - - LUT4_107: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec36_p018); - - LUT4_106: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_37); - - LUT4_105: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec37_r118); - - LUT4_104: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13_inv, DO0=>func_and_inet_38); - - LUT4_103: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec38_p019); - - LUT4_102: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_39); - - LUT4_101: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec39_r119); - - LUT4_100: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_40); - - LUT4_99: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec40_p020); - - LUT4_98: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_41); - - LUT4_97: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec41_r120); - - LUT4_96: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_42); - - LUT4_95: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec42_p021); - - LUT4_94: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_43); - - LUT4_93: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec43_r121); - - LUT4_92: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_44); - - LUT4_91: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec44_p022); - - LUT4_90: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_45); - - LUT4_89: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec45_r122); - - LUT4_88: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13_inv, DO0=>func_and_inet_46); - - LUT4_87: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec46_p023); - - LUT4_86: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_47); - - LUT4_85: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec47_r123); - - LUT4_84: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_48); - - LUT4_83: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec48_p024); - - LUT4_82: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_49); - - LUT4_81: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec49_r124); - - LUT4_80: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_50); - - LUT4_79: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec50_p025); - - LUT4_78: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_51); - - LUT4_77: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec51_r125); - - LUT4_76: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_52); - - LUT4_75: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec52_p026); - - LUT4_74: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_53); - - LUT4_73: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec53_r126); - - LUT4_72: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, - AD0=>wptr_13, DO0=>func_and_inet_54); - - LUT4_71: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec54_p027); - - LUT4_70: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_55); - - LUT4_69: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec55_r127); - - LUT4_68: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_56); - - LUT4_67: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec56_p028); - - LUT4_66: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_57); - - LUT4_65: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec57_r128); - - LUT4_64: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_58); - - LUT4_63: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec58_p029); - - LUT4_62: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_59); - - LUT4_61: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec59_r129); - - LUT4_60: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, - AD0=>wptr_13, DO0=>func_and_inet_60); - - LUT4_59: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec60_p030); - - LUT4_58: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_61); - - LUT4_57: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec61_r130); - - LUT4_56: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, - DO0=>func_and_inet_62); - - LUT4_55: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec62_p031); - - LUT4_54: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_63); - - LUT4_53: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec63_r131); - - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, - DO0=>w_g2b_xor_cluster_0); - - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_1); - - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_2); - - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_3); - - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r2); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r1); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r0); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - XOR2_t5: XOR2 - port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); - - XOR2_t4: XOR2 - port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); - - XOR2_t3: XOR2 - port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - INV_0: INV - port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec0_p00, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, - DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, - DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, - DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec2_p01, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, - DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, - DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, - DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec4_p02, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, - DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, - DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, - DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec6_p03, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, - DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, - DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, - DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec8_p04, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, - DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, - DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, - DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec10_p05, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, - DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, - DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, - DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec12_p06, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, - DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, - DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, - DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec14_p07, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, - DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, - DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, - DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec16_p08, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, - DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, - DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, - DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec18_p09, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, - DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, - DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, - DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec20_p010, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, - DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, - DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, - DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec22_p011, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, - DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, - DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, - DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec24_p012, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, - DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, - DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, - DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec26_p013, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, - DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, - DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, - DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec28_p014, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, - DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, - DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, - DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec30_p015, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, - DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, - DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, - DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec32_p016, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, - DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, - DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, - DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec34_p017, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, - DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, - DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, - DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec36_p018, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, - DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, - DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, - DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec38_p019, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, - DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, - DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, - DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec40_p020, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, - DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, - DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, - DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec42_p021, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, - DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, - DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, - DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec44_p022, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, - DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, - DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, - DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec46_p023, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, - DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, - DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, - DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec48_p024, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, - DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, - DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, - DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec50_p025, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, - DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, - DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, - DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec52_p026, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, - DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, - DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, - DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec54_p027, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, - DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, - DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, - DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec56_p028, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, - DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, - DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, - DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec58_p029, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, - DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, - DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, - DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec60_p030, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, - DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, - DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, - DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, - ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, - ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec62_p031, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, - DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, - DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, - DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_239: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_238: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_237: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_236: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_235: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_234: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_233: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_232: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_231: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_230: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_229: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_228: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_227: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_226: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_225: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_224: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_223: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_222: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_221: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_220: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_219: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_218: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_217: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_216: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_215: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_214: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_213: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_212: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_211: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_210: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_209: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_208: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_207: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_206: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_205: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_204: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_203: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_202: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_201: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_200: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_199: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_198: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_197: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_196: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_195: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_194: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_193: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_192: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_191: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_190: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_189: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_188: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_187: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_186: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_185: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_184: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_183: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_182: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_181: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_180: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_179: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_178: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_177: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_176: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_175: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_174: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_173: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_135: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_134: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_133: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_132: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_131: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_130: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_129: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_128: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_127: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_126: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_125: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_124: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_123: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_122: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_121: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_120: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_119: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_118: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_117: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_116: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_115: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_114: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_113: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_112: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_111: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_110: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_109: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_108: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_107: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_106: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_105: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_104: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_103: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_102: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_101: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_100: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_99: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_98: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_97: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_96: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_95: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_94: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_93: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_92: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_91: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_90: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_89: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_88: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_87: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_86: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_85: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_84: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_83: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_82: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_81: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_80: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_79: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_78: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_77: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_76: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_75: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_74: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_73: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_72: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_71: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_70: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); - - FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); - - FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); - - FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); - - FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); - - FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); - - FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); - - FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); - - FF_3: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>ircount_16, NC1=>open); - - mux_8: MUX321 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, - D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, - D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, - D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, - D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, - D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(0)); - - mux_7: MUX321 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, - D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, - D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, - D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, - D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, - D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(1)); - - mux_6: MUX321 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, - D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, - D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, - D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, - D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, - D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(2)); - - mux_5: MUX321 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, - D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, - D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, - D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, - D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, - D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(3)); - - mux_4: MUX321 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, - D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, - D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, - D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, - D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, - D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(4)); - - mux_3: MUX321 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, - D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, - D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, - D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, - D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, - D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(5)); - - mux_2: MUX321 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, - D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, - D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, - D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, - D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, - D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(6)); - - mux_1: MUX321 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, - D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, - D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, - D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, - D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, - D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(7)); - - mux_0: MUX321 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, - D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, - D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, - D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, - D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, - D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(8)); - - precin_inst860: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, - S1=>open); - - wcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>precin, BOUT=>co0_2, S0=>open, - S1=>wcnt_sub_0); - - wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, - B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, - S1=>wcnt_sub_2); - - wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, - B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, - S1=>wcnt_sub_4); - - wcnt_3: FSUB2B - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, - B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, - S1=>wcnt_sub_6); - - wcnt_4: FSUB2B - port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, - B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, - S1=>wcnt_sub_8); - - wcnt_5: FSUB2B - port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, - S1=>wcnt_sub_10); - - wcnt_6: FSUB2B - port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, - S0=>wcnt_sub_11, S1=>wcnt_sub_12); - - wcnt_7: FSUB2B - port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, - S1=>wcnt_sub_14); - - wcnt_8: FSUB2B - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, - S1=>open); - - precin_inst903: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_1, S0=>open, - S1=>open); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rcount_0, BI=>precin_1, BOUT=>co0_3, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, - B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, - B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, - B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcnt_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, - B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, - S1=>rcnt_sub_8); - - rcnt_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, - B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, - S1=>rcnt_sub_10); - - rcnt_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, - B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, - S1=>rcnt_sub_12); - - rcnt_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, - B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, - S1=>rcnt_sub_14); - - rcnt_8: FSUB2B - port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, - B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, - S1=>rcnt_sub_16); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); - - precin_inst948: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_2, S0=>open, - S1=>open); - - wfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, - B1=>rcount_w1, BI=>precin_2, BOUT=>co0_4, S0=>open, - S1=>wfill_sub_0); - - wfill_1: FSUB2B - port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, - BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); - - wfill_2: FSUB2B - port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, - BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); - - wfill_3: FSUB2B - port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, - BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); - - wfill_4: FSUB2B - port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, - BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); - - wfill_5: FSUB2B - port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, - B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, - S1=>wfill_sub_10); - - wfill_6: FSUB2B - port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, - S0=>wfill_sub_11, S1=>wfill_sub_12); - - wfill_7: FSUB2B - port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, - B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, - S1=>wfill_sub_14); - - wfill_8: FSUB2B - port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, - S1=>open); - - precin_inst975: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_3, S0=>open, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rfill_0: FSUB2B - port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>rptr_0, BI=>precin_3, BOUT=>co0_5, S0=>open, - S1=>rfill_sub_0); - - rfill_1: FSUB2B - port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2, - BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2); - - rfill_2: FSUB2B - port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4, - BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4); - - rfill_3: FSUB2B - port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6, - BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6); - - rfill_4: FSUB2B - port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8, - BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8); - - rfill_5: FSUB2B - port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10, - BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10); - - rfill_6: FSUB2B - port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11, - B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11, - S1=>rfill_sub_12); - - rfill_7: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13, - B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13, - S1=>rfill_sub_14); - - rfill_8: FSUB2B - port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15, - B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15, - S1=>rfill_sub_16); - - rfilld: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, - B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, - B1=>wcount_r2, CI=>co0_6, GE=>co1_6); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, - B1=>wcount_r4, CI=>co1_6, GE=>co2_6); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, - B1=>wcount_r6, CI=>co2_6, GE=>co3_6); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, - B1=>wcount_r8, CI=>co3_6, GE=>co4_6); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, - B1=>wcount_r10, CI=>co4_6, GE=>co5_6); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, - B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, - B1=>wcount_r14, CI=>co6_6, GE=>co7_6); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, - B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, - B1=>rcount_w4, CI=>co0_7, GE=>co1_7); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, - B1=>rcount_w6, CI=>co1_7, GE=>co2_7); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, - B1=>rcount_w8, CI=>co2_7, GE=>co3_7); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, - B1=>rcount_w10, CI=>co3_7, GE=>co4_7); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, - B1=>rcount_w12, CI=>co4_7, GE=>co5_7); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w14, CI=>co5_7, GE=>co6_7); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, - B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8); - - ae_cmp_3: AGEB2 - port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), - B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8); - - ae_cmp_4: AGEB2 - port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), - B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8); - - ae_cmp_5: AGEB2 - port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), - B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8); - - ae_cmp_6: AGEB2 - port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), - B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8); - - ae_cmp_7: AGEB2 - port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), - B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7); - - ae_cmp_8: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - - af_d_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_d_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9); - - af_d_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9); - - af_d_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9); - - af_d_cmp_3: AGEB2 - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9); - - af_d_cmp_4: AGEB2 - port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), - B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9); - - af_d_cmp_5: AGEB2 - port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), - B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9); - - af_d_cmp_6: AGEB2 - port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), - B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9); - - af_d_cmp_7: AGEB2 - port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), - B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_32kx16x8_mb2 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX321 use entity ecp2m.MUX321(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_generate.log b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_generate.log deleted file mode 100644 index 6d3aa14..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond (64-bit) 3.9.1.119 -Thu Jan 18 18:38:11 2018 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill - Circuit name : fifo_32kx16x8_mb2 - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[15:0], AmFullThresh[14:0] - Outputs : Q[8:0], WCNT[15:0], RCNT[16:0], Empty, Full, AlmostEmpty, AlmostFull - I/O buffer : not inserted - EDIF output : fifo_32kx16x8_mb2.edn - VHDL output : fifo_32kx16x8_mb2.vhd - VHDL template : fifo_32kx16x8_mb2_tmpl.vhd - VHDL testbench : tb_fifo_32kx16x8_mb2_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_32kx16x8_mb2.srp - Estimated Resource Usage: - LUT : 499 - EBR : 32 - Reg : 240 - -END SCUBA Module Synthesis - -File: fifo_32kx16x8_mb2.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd deleted file mode 100644 index faa3a80..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd +++ /dev/null @@ -1,26 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.9.1.119 --- Module Version: 5.8 --- Thu Jan 18 18:38:11 2018 - --- parameterized module component declaration -component fifo_32kx16x8_mb2 - port (Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(8 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_32kx16x8_mb2 - port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__, - AmFullThresh(14 downto 0)=>__, Q(8 downto 0)=>__, WCNT(15 downto 0)=>__, - RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__, - AlmostFull=>__); diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd deleted file mode 100755 index bc2e00d..0000000 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd +++ /dev/null @@ -1,26 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 --- Fri Feb 05 16:48:13 2010 - --- parameterized module component declaration -component fifo_32kx16x8_mb - port (Data: in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(15 downto 0); - AmFullThresh: in std_logic_vector(14 downto 0); - Q: out std_logic_vector(7 downto 0); - WCNT: out std_logic_vector(15 downto 0); - RCNT: out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_32kx16x8_mb - port map (Data(15 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(15 downto 0)=>__, - AmFullThresh(14 downto 0)=>__, Q(7 downto 0)=>__, WCNT(15 downto 0)=>__, - RCNT(16 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__, - AlmostFull=>__); diff --git a/gbe_ecp2m/ipcores/fifo_4096x32.lpc b/gbe_ecp2m/ipcores/fifo_4096x32.lpc deleted file mode 100755 index 3f5196b..0000000 --- a/gbe_ecp2m/ipcores/fifo_4096x32.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.3 -ModuleName=fifo_4096x32 -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=12/18/2009 -Time=03:02:30 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=32 -RDepth=4096 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_4096x32.vhd b/gbe_ecp2m/ipcores/fifo_4096x32.vhd deleted file mode 100755 index 51a2cd4..0000000 --- a/gbe_ecp2m/ipcores/fifo_4096x32.vhd +++ /dev/null @@ -1,2415 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - --- Fri Dec 18 03:02:30 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_4096x32 is - port ( - Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4096x32; - -architecture Structure of fifo_4096x32 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "4"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), - DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(8), DOB1=>Q(9), DOB2=>Q(10), - DOB3=>Q(11), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), - DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(12), DOB1=>Q(13), DOB2=>Q(14), - DOB3=>Q(15), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), - DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(16), DOB1=>Q(17), DOB2=>Q(18), - DOB3=>Q(19), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), - DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(20), DOB1=>Q(21), DOB2=>Q(22), - DOB3=>Q(23), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), - DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(24), DOB1=>Q(25), DOB2=>Q(26), - DOB3=>Q(27), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), - DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(28), DOB1=>Q(29), DOB2=>Q(30), - DOB3=>Q(31), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_131: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_92: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_4096x32 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd deleted file mode 100755 index 745eb44..0000000 --- a/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 --- Fri Dec 18 03:02:30 2009 - --- parameterized module component declaration -component fifo_4096x32 - port (Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x32 - port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_4096x9.lpc b/gbe_ecp2m/ipcores/fifo_4096x9.lpc deleted file mode 100755 index 22cb7c6..0000000 --- a/gbe_ecp2m/ipcores/fifo_4096x9.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.2 -ModuleName=fifo_4096x9 -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=01/05/2010 -Time=23:44:15 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=9 -RDepth=4096 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_4096x9.vhd b/gbe_ecp2m/ipcores/fifo_4096x9.vhd deleted file mode 100755 index ca644d2..0000000 --- a/gbe_ecp2m/ipcores/fifo_4096x9.vhd +++ /dev/null @@ -1,2171 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Tue Jan 5 23:44:15 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_4096x9 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4096x9; - -architecture Structure of fifo_4096x9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_12: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX21 - port (D0: in std_logic; D1: in std_logic; SD: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_0 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_0 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_0 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_1_0_0 : label is "9"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, - DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, - DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, - DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_1_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, - DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, - DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, - DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - FF_132: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_93: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - mux_8: MUX21 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, - Z=>Q(0)); - - mux_7: MUX21 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, - Z=>Q(1)); - - mux_6: MUX21 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, - Z=>Q(2)); - - mux_5: MUX21 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, - Z=>Q(3)); - - mux_4: MUX21 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, - Z=>Q(4)); - - mux_3: MUX21 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, - Z=>Q(5)); - - mux_2: MUX21 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, - Z=>Q(6)); - - mux_1: MUX21 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, - Z=>Q(7)); - - mux_0: MUX21 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, - Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_4096x9 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX21 use entity ecp2m.MUX21(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd deleted file mode 100755 index f754d74..0000000 --- a/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 --- Tue Jan 5 23:44:15 2010 - --- parameterized module component declaration -component fifo_4096x9 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x9 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_512x32.lpc b/gbe_ecp2m/ipcores/fifo_512x32.lpc deleted file mode 100644 index 67057ca..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x32.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x32 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:13:43 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=32 -RDepth=512 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_512x32.vhd b/gbe_ecp2m/ipcores/fifo_512x32.vhd deleted file mode 100644 index 73e04d7..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x32.vhd +++ /dev/null @@ -1,1193 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:13:43 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_512x32 is - port ( - Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_512x32; - -architecture Structure of fifo_512x32 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KC - generic (GSR : in String; CSDECODE_R : in String; - CSDECODE_W : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t20: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, - DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, - ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open, - DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), - DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), - DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), - DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); - - FF_101: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_512x32 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_512x32_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_512x32_tmpl.vhd deleted file mode 100644 index a461685..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x32_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:13:43 2011 - --- parameterized module component declaration -component fifo_512x32 - port (Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x32 - port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_512x64.lpc b/gbe_ecp2m/ipcores/fifo_512x64.lpc deleted file mode 100644 index f17569e..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x64.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x64 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:23:40 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=72 -RDepth=512 -RWidth=72 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_512x64.vhd b/gbe_ecp2m/ipcores/fifo_512x64.vhd deleted file mode 100644 index dae4c8f..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x64.vhd +++ /dev/null @@ -1,1231 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:23:40 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_512x64 is - port ( - Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_512x64; - -architecture Structure of fifo_512x64 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KC - generic (GSR : in String; CSDECODE_R : in String; - CSDECODE_W : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x64.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x64.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t20: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), - DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, - ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, - ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), - DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), - DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), - DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), - DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), - DO35=>Q(17)); - - pdp_ram_0_1_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), - DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), - DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), - DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), - DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), - DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), - DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), - DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), - DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), - DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), - DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), - DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, - ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, - ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, - BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, - CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, - ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, - ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, - ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, - ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), - DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), - DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), - DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), - DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), - DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), - DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), - DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), - DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); - - FF_101: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_512x64 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_512x64_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_512x64_tmpl.vhd deleted file mode 100644 index 490c7e6..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x64_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:23:40 2011 - --- parameterized module component declaration -component fifo_512x64 - port (Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x64 - port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_512x72.lpc b/gbe_ecp2m/ipcores/fifo_512x72.lpc deleted file mode 100644 index 1467961..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x72.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.4 -ModuleName=fifo_512x72 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:14:03 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=72 -RDepth=512 -RWidth=72 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_512x72.vhd b/gbe_ecp2m/ipcores/fifo_512x72.vhd deleted file mode 100644 index 4ffa914..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x72.vhd +++ /dev/null @@ -1,1231 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 72 -depth 512 -rdata_width 72 -no_enable -pe -1 -pf -1 -e - --- Thu Sep 22 11:14:04 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_512x72 is - port ( - Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_512x72; - -architecture Structure of fifo_512x72 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KC - generic (GSR : in String; CSDECODE_R : in String; - CSDECODE_W : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512x72.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_512x72.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t20: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_23: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_22: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_21: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_20: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_19: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), - DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), - DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), - DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), - DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), - DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, - ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, - ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), - DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), - DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), - DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), - DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), - DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), - DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), - DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), - DO35=>Q(17)); - - pdp_ram_0_1_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), - DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), - DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), - DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), - DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), - DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), - DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), - DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), - DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), - DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), - DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), - DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, - ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, - ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, - BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, - CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, - ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, - ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, - ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, - ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), - DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), - DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), - DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), - DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), - DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), - DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), - DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), - DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); - - FF_101: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_100: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_99: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_98: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_97: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_96: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_95: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_94: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_93: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_92: FD1P3DX - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_91: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_90: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_89: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_88: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_87: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_86: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_85: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_84: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_83: FD1P3DX - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_82: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_81: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_80: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_79: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_78: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_77: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_76: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_75: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_74: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_73: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_72: FD1P3DX - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_71: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_70: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_69: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_68: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_67: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_66: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_65: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_64: FD1P3DX - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_63: FD1P3DX - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_62: FD1P3DX - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_61: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_60: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_59: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_58: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_57: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_56: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_55: FD1P3DX - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_54: FD1P3DX - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_53: FD1P3DX - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_52: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_51: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_50: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_49: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_48: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_47: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_46: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_45: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_44: FD1P3DX - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_43: FD1P3DX - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_42: FD1P3DX - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_31: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_30: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_29: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_28: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_27: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_26: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_25: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_24: FD1S3DX - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_23: FD1S3DX - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_22: FD1S3DX - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_21: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_20: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_19: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_18: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_17: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_16: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_15: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_14: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_13: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_12: FD1S3DX - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_11: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_10: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_9: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_8: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_7: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_6: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_5: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_4: FD1S3DX - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_3: FD1S3DX - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_2: FD1S3DX - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_1: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_512x72 is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_512x72_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_512x72_tmpl.vhd deleted file mode 100644 index b52a2b9..0000000 --- a/gbe_ecp2m/ipcores/fifo_512x72_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 --- Thu Sep 22 11:14:04 2011 - --- parameterized module component declaration -component fifo_512x72 - port (Data: in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(71 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_512x72 - port map (Data(71 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(71 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_64kx8.lpc b/gbe_ecp2m/ipcores/fifo_64kx8.lpc deleted file mode 100755 index 3d27821..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx8.lpc +++ /dev/null @@ -1,47 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.2 -ModuleName=fifo_64kx8 -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=12/26/2009 -Time=00:12:05 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=65536 -Width=8 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_64kx8.vhd b/gbe_ecp2m/ipcores/fifo_64kx8.vhd deleted file mode 100755 index ba79880..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx8.vhd +++ /dev/null @@ -1,4435 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Sat Dec 26 00:12:05 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_64kx8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_64kx8; - -architecture Structure of fifo_64kx8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_9: std_logic; - signal func_xor_inet_8: std_logic; - signal func_xor_inet_7: std_logic; - signal func_xor_inet_6: std_logic; - signal func_xor_inet_10: std_logic; - signal func_xor_inet_11: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal w_gdata_15: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wptr_15: std_logic; - signal wptr_16: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_16: std_logic; - signal rptr_14: std_logic; - signal rptr_15: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal w_gcount_16: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal w_gcount_r216: std_logic; - signal w_gcount_r16: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co6: std_logic; - signal iwcount_16: std_logic; - signal co8: std_logic; - signal wcount_16: std_logic; - signal co7: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8_1: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal wcount_r14: std_logic; - signal wcount_r15: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal rcount_w14: std_logic; - signal rcount_w15: std_logic; - signal wcount_14: std_logic; - signal wcount_15: std_logic; - signal co7_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX41 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; SD1: in std_logic; SD2: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_59 : label is "0x6996"; - attribute initval of LUT4_58 : label is "0x6996"; - attribute initval of LUT4_57 : label is "0x6996"; - attribute initval of LUT4_56 : label is "0x6996"; - attribute initval of LUT4_55 : label is "0x6996"; - attribute initval of LUT4_54 : label is "0x6996"; - attribute initval of LUT4_53 : label is "0x6996"; - attribute initval of LUT4_52 : label is "0x6996"; - attribute initval of LUT4_51 : label is "0x6996"; - attribute initval of LUT4_50 : label is "0x6996"; - attribute initval of LUT4_49 : label is "0x6996"; - attribute initval of LUT4_48 : label is "0x6996"; - attribute initval of LUT4_47 : label is "0x6996"; - attribute initval of LUT4_46 : label is "0x6996"; - attribute initval of LUT4_45 : label is "0x6996"; - attribute initval of LUT4_44 : label is "0x6996"; - attribute initval of LUT4_43 : label is "0x6996"; - attribute initval of LUT4_42 : label is "0x6996"; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_30 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_29 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_28 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_28 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_28 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_28 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_28 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_28 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_28 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_28 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_3_28 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_27 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_27 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_27 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_27 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_27 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_27 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_27 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_27 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_27 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_4_27 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_26 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_26 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_26 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_26 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_26 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_26 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_26 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_26 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_26 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_5_26 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_25 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_25 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_25 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_25 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_25 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_25 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_25 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_25 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_25 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_6_25 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_24 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_24 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_24 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_24 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_24 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_24 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_24 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_24 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_24 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_7_24 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_23 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_23 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_23 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_23 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_23 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_23 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_23 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_23 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_23 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_0_23 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; - attribute CSDECODE_B of pdp_ram_1_1_22 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_1_22 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_1_22 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_1_22 : label is "NORMAL"; - attribute GSR of pdp_ram_1_1_22 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_1_22 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_1_22 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_1_22 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_1_22 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_1_22 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_64kx8.lpc"; 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- attribute WRITEMODE_B of pdp_ram_3_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_3_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_7_0 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "1"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t34: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t33: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t32: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t31: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t30: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t29: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t28: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t27: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t26: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t25: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t24: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t23: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t22: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t21: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t20: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t19: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t18: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t17: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t16: XOR2 - port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - LUT4_59: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>w_gcount_r216, - DO0=>w_g2b_xor_cluster_0); - - LUT4_58: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_1); - - LUT4_57: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_2); - - LUT4_56: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_3); - - LUT4_55: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r15); - - LUT4_54: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, - AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_53: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, - DO0=>wcount_r10); - - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r3); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r2); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_10); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, - AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, - DO0=>func_xor_inet_11); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_3_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_4_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_5_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_6_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_7_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_1_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_2_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_3_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_4_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_5_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_6_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_7_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_1_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_2_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_3_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_4_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_5_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_6_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_7_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_173: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_16); - - FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_16); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_135: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_134: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_133: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_132: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_16); - - FF_122: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r16); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r216); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - w_gctr_8: CU2 - port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>iwcount_16, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, - NC0=>ircount_16, NC1=>open); - - mux_7: MUX41 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); - - mux_6: MUX41 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); - - mux_5: MUX41 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); - - mux_4: MUX41 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); - - mux_3: MUX41 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); - - mux_2: MUX41 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); - - mux_1: MUX41 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); - - mux_0: MUX41 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, - B1=>wcount_r15, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, - B1=>rcount_w15, CI=>co6_3, GE=>co7_3); - - full_cmp_8: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_64kx8 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX41 use entity ecp2m.MUX41(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd deleted file mode 100755 index c0c7959..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 --- Sat Dec 26 00:12:05 2009 - --- parameterized module component declaration -component fifo_64kx8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_64kx8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_64kx9.ipx b/gbe_ecp2m/ipcores/fifo_64kx9.ipx deleted file mode 100644 index 7d82e48..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx9.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/gbe_ecp2m/ipcores/fifo_64kx9.lpc b/gbe_ecp2m/ipcores/fifo_64kx9.lpc deleted file mode 100644 index a33833d..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx9.lpc +++ /dev/null @@ -1,50 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F1152C -SpeedGrade=5 -Package=FPBGA1152 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.8 -ModuleName=fifo_64kx9 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=01/18/2018 -Time=18:38:41 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=65536 -Width=9 -RDepth=65536 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 - -[Command] -cmd_line= -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 diff --git a/gbe_ecp2m/ipcores/fifo_64kx9.srp b/gbe_ecp2m/ipcores/fifo_64kx9.srp deleted file mode 100644 index 6928a7b..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx9.srp +++ /dev/null @@ -1,43 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.9.1.119 -Thu Jan 18 18:38:41 2018 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 - Circuit name : fifo_64kx9 - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo_64kx9.edn - VHDL output : fifo_64kx9.vhd - VHDL template : fifo_64kx9_tmpl.vhd - VHDL testbench : tb_fifo_64kx9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx9.srp - Element Usage : - AGEB2 : 18 - AND2 : 2 - CU2 : 18 - FADD2B : 6 - FD1P3BX : 2 - FD1P3DX : 105 - FD1S3BX : 1 - FD1S3DX : 69 - INV : 12 - MUX321 : 9 - OR2 : 1 - ROM16X1 : 188 - XOR2 : 32 - DP16KB : 32 - Estimated Resource Usage: - LUT : 379 - EBR : 32 - Reg : 177 diff --git a/gbe_ecp2m/ipcores/fifo_64kx9.vhd b/gbe_ecp2m/ipcores/fifo_64kx9.vhd deleted file mode 100644 index 7b840df..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx9.vhd +++ /dev/null @@ -1,6025 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 --- Module Version: 5.8 ---/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 - --- Thu Jan 18 18:38:41 2018 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_64kx9 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_64kx9; - -architecture Structure of fifo_64kx9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal func_and_inet: std_logic; - signal func_and_inet_1: std_logic; - signal func_and_inet_2: std_logic; - signal func_and_inet_3: std_logic; - signal func_and_inet_4: std_logic; - signal func_and_inet_5: std_logic; - signal func_and_inet_6: std_logic; - signal func_and_inet_7: std_logic; - signal func_and_inet_8: std_logic; - signal func_and_inet_9: std_logic; - signal func_and_inet_10: std_logic; - signal func_and_inet_11: std_logic; - signal func_and_inet_12: std_logic; - signal func_and_inet_13: std_logic; - signal func_and_inet_14: std_logic; - signal func_and_inet_15: std_logic; - signal func_and_inet_16: std_logic; - signal func_and_inet_17: std_logic; - signal func_and_inet_18: std_logic; - signal func_and_inet_19: std_logic; - signal func_and_inet_20: std_logic; - signal func_and_inet_21: std_logic; - signal func_and_inet_22: std_logic; - signal func_and_inet_23: std_logic; - signal func_and_inet_24: std_logic; - signal func_and_inet_25: std_logic; - signal func_and_inet_26: std_logic; - signal func_and_inet_27: std_logic; - signal func_and_inet_28: std_logic; - signal func_and_inet_29: std_logic; - signal wptr_15_inv: std_logic; - signal func_and_inet_30: std_logic; - signal rptr_15_inv: std_logic; - signal func_and_inet_31: std_logic; - signal func_and_inet_32: std_logic; - signal func_and_inet_33: std_logic; - signal func_and_inet_34: std_logic; - signal func_and_inet_35: std_logic; - signal func_and_inet_36: std_logic; - signal func_and_inet_37: std_logic; - signal func_and_inet_38: std_logic; - signal func_and_inet_39: std_logic; - signal func_and_inet_40: std_logic; - signal func_and_inet_41: std_logic; - signal func_and_inet_42: std_logic; - signal func_and_inet_43: std_logic; - signal func_and_inet_44: std_logic; - signal func_and_inet_45: std_logic; - signal wptr_14_inv: std_logic; - signal func_and_inet_46: std_logic; - signal rptr_14_inv: std_logic; - signal func_and_inet_47: std_logic; - signal func_and_inet_48: std_logic; - signal func_and_inet_49: std_logic; - signal func_and_inet_50: std_logic; - signal func_and_inet_51: std_logic; - signal func_and_inet_52: std_logic; - signal func_and_inet_53: std_logic; - signal wptr_13_inv: std_logic; - signal func_and_inet_54: std_logic; - signal rptr_13_inv: std_logic; - signal func_and_inet_55: std_logic; - signal func_and_inet_56: std_logic; - signal func_and_inet_57: std_logic; - signal wptr_12_inv: std_logic; - signal func_and_inet_58: std_logic; - signal rptr_12_inv: std_logic; - signal func_and_inet_59: std_logic; - signal wptr_11_inv: std_logic; - signal func_and_inet_60: std_logic; - signal rptr_11_inv: std_logic; - signal func_and_inet_61: std_logic; - signal func_and_inet_62: std_logic; - signal func_and_inet_63: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_9: std_logic; - signal func_xor_inet_8: std_logic; - signal func_xor_inet_7: std_logic; - signal func_xor_inet_6: std_logic; - signal func_xor_inet_10: std_logic; - signal func_xor_inet_11: std_logic; - signal dec1_r10: std_logic; - signal dec0_p00: std_logic; - signal dec3_r11: std_logic; - signal dec2_p01: std_logic; - signal dec5_r12: std_logic; - signal dec4_p02: std_logic; - signal dec7_r13: std_logic; - signal dec6_p03: std_logic; - signal dec9_r14: std_logic; - signal dec8_p04: std_logic; - signal dec11_r15: std_logic; - signal dec10_p05: std_logic; - signal dec13_r16: std_logic; - signal dec12_p06: std_logic; - signal dec15_r17: std_logic; - signal dec14_p07: std_logic; - signal dec17_r18: std_logic; - signal dec16_p08: std_logic; - signal dec19_r19: std_logic; - signal dec18_p09: std_logic; - signal dec21_r110: std_logic; - signal dec20_p010: std_logic; - signal dec23_r111: std_logic; - signal dec22_p011: std_logic; - signal dec25_r112: std_logic; - signal dec24_p012: std_logic; - signal dec27_r113: std_logic; - signal dec26_p013: std_logic; - signal dec29_r114: std_logic; - signal dec28_p014: std_logic; - signal dec31_r115: std_logic; - signal dec30_p015: std_logic; - signal dec33_r116: std_logic; - signal dec32_p016: std_logic; - signal dec35_r117: std_logic; - signal dec34_p017: std_logic; - signal dec37_r118: std_logic; - signal dec36_p018: std_logic; - signal dec39_r119: std_logic; - signal dec38_p019: std_logic; - signal dec41_r120: std_logic; - signal dec40_p020: std_logic; - signal dec43_r121: std_logic; - signal dec42_p021: std_logic; - signal dec45_r122: std_logic; - signal dec44_p022: std_logic; - signal dec47_r123: std_logic; - signal dec46_p023: std_logic; - signal dec49_r124: std_logic; - signal dec48_p024: std_logic; - signal dec51_r125: std_logic; - signal dec50_p025: std_logic; - signal dec53_r126: std_logic; - signal dec52_p026: std_logic; - signal dec55_r127: std_logic; - signal dec54_p027: std_logic; - signal dec57_r128: std_logic; - signal dec56_p028: std_logic; - signal dec59_r129: std_logic; - signal dec58_p029: std_logic; - signal dec61_r130: std_logic; - signal dec60_p030: std_logic; - signal dec63_r131: std_logic; - signal dec62_p031: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal w_gdata_15: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wptr_15: std_logic; - signal wptr_16: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_16: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_14: std_logic; - signal rptr_15: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal w_gcount_16: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal w_gcount_r216: std_logic; - signal w_gcount_r16: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co6: std_logic; - signal iwcount_16: std_logic; - signal co8: std_logic; - signal co7: std_logic; - signal wcount_16: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8_1: std_logic; - signal co7_1: std_logic; - signal rcount_16: std_logic; - signal mdout1_31_0: std_logic; - signal mdout1_30_0: std_logic; - signal mdout1_29_0: std_logic; - signal mdout1_28_0: std_logic; - signal mdout1_27_0: std_logic; - signal mdout1_26_0: std_logic; - signal mdout1_25_0: std_logic; - signal mdout1_24_0: std_logic; - signal mdout1_23_0: std_logic; - signal mdout1_22_0: std_logic; - signal mdout1_21_0: std_logic; - signal mdout1_20_0: std_logic; - signal mdout1_19_0: std_logic; - signal mdout1_18_0: std_logic; - signal mdout1_17_0: std_logic; - signal mdout1_16_0: std_logic; - signal mdout1_15_0: std_logic; - signal mdout1_14_0: std_logic; - signal mdout1_13_0: std_logic; - signal mdout1_12_0: std_logic; - signal mdout1_11_0: std_logic; - signal mdout1_10_0: std_logic; - signal mdout1_9_0: std_logic; - signal mdout1_8_0: std_logic; - signal mdout1_7_0: std_logic; - signal mdout1_6_0: std_logic; - signal mdout1_5_0: std_logic; - signal mdout1_4_0: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_31_1: std_logic; - signal mdout1_30_1: std_logic; - signal mdout1_29_1: std_logic; - signal mdout1_28_1: std_logic; - signal mdout1_27_1: std_logic; - signal mdout1_26_1: std_logic; - signal mdout1_25_1: std_logic; - signal mdout1_24_1: std_logic; - signal mdout1_23_1: std_logic; - signal mdout1_22_1: std_logic; - signal mdout1_21_1: std_logic; - signal mdout1_20_1: std_logic; - signal mdout1_19_1: std_logic; - signal mdout1_18_1: std_logic; - signal mdout1_17_1: std_logic; - signal mdout1_16_1: std_logic; - signal mdout1_15_1: std_logic; - signal mdout1_14_1: std_logic; - signal mdout1_13_1: std_logic; - signal mdout1_12_1: std_logic; - signal mdout1_11_1: std_logic; - signal mdout1_10_1: std_logic; - signal mdout1_9_1: std_logic; - signal mdout1_8_1: std_logic; - signal mdout1_7_1: std_logic; - signal mdout1_6_1: std_logic; - signal mdout1_5_1: std_logic; - signal mdout1_4_1: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_31_2: std_logic; - signal mdout1_30_2: std_logic; - signal mdout1_29_2: std_logic; - signal mdout1_28_2: std_logic; - signal mdout1_27_2: std_logic; - signal mdout1_26_2: std_logic; - signal mdout1_25_2: std_logic; - signal mdout1_24_2: std_logic; - signal mdout1_23_2: std_logic; - signal mdout1_22_2: std_logic; - signal mdout1_21_2: std_logic; - signal mdout1_20_2: std_logic; - signal mdout1_19_2: std_logic; - signal mdout1_18_2: std_logic; - signal mdout1_17_2: std_logic; - signal mdout1_16_2: std_logic; - signal mdout1_15_2: std_logic; - signal mdout1_14_2: std_logic; - signal mdout1_13_2: std_logic; - signal mdout1_12_2: std_logic; - signal mdout1_11_2: std_logic; - signal mdout1_10_2: std_logic; - signal mdout1_9_2: std_logic; - signal mdout1_8_2: std_logic; - signal mdout1_7_2: std_logic; - signal mdout1_6_2: std_logic; - signal mdout1_5_2: std_logic; - signal mdout1_4_2: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_31_3: std_logic; - signal mdout1_30_3: std_logic; - signal mdout1_29_3: std_logic; - signal mdout1_28_3: std_logic; - signal mdout1_27_3: std_logic; - signal mdout1_26_3: std_logic; - signal mdout1_25_3: std_logic; - signal mdout1_24_3: std_logic; - signal mdout1_23_3: std_logic; - signal mdout1_22_3: std_logic; - signal mdout1_21_3: std_logic; - signal mdout1_20_3: std_logic; - signal mdout1_19_3: std_logic; - signal mdout1_18_3: std_logic; - signal mdout1_17_3: std_logic; - signal mdout1_16_3: std_logic; - signal mdout1_15_3: std_logic; - signal mdout1_14_3: std_logic; - signal mdout1_13_3: std_logic; - signal mdout1_12_3: std_logic; - signal mdout1_11_3: std_logic; - signal mdout1_10_3: std_logic; - signal mdout1_9_3: std_logic; - signal mdout1_8_3: std_logic; - signal mdout1_7_3: std_logic; - signal mdout1_6_3: std_logic; - signal mdout1_5_3: std_logic; - signal mdout1_4_3: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_31_4: std_logic; - signal mdout1_30_4: std_logic; - signal mdout1_29_4: std_logic; - signal mdout1_28_4: std_logic; - signal mdout1_27_4: std_logic; - signal mdout1_26_4: std_logic; - signal mdout1_25_4: std_logic; - signal mdout1_24_4: std_logic; - signal mdout1_23_4: std_logic; - signal mdout1_22_4: std_logic; - signal mdout1_21_4: std_logic; - signal mdout1_20_4: std_logic; - signal mdout1_19_4: std_logic; - signal mdout1_18_4: std_logic; - signal mdout1_17_4: std_logic; - signal mdout1_16_4: std_logic; - signal mdout1_15_4: std_logic; - signal mdout1_14_4: std_logic; - signal mdout1_13_4: std_logic; - signal mdout1_12_4: std_logic; - signal mdout1_11_4: std_logic; - signal mdout1_10_4: std_logic; - signal mdout1_9_4: std_logic; - signal mdout1_8_4: std_logic; - signal mdout1_7_4: std_logic; - signal mdout1_6_4: std_logic; - signal mdout1_5_4: std_logic; - signal mdout1_4_4: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_31_5: std_logic; - signal mdout1_30_5: std_logic; - signal mdout1_29_5: std_logic; - signal mdout1_28_5: std_logic; - signal mdout1_27_5: std_logic; - signal mdout1_26_5: std_logic; - signal mdout1_25_5: std_logic; - signal mdout1_24_5: std_logic; - signal mdout1_23_5: std_logic; - signal mdout1_22_5: std_logic; - signal mdout1_21_5: std_logic; - signal mdout1_20_5: std_logic; - signal mdout1_19_5: std_logic; - signal mdout1_18_5: std_logic; - signal mdout1_17_5: std_logic; - signal mdout1_16_5: std_logic; - signal mdout1_15_5: std_logic; - signal mdout1_14_5: std_logic; - signal mdout1_13_5: std_logic; - signal mdout1_12_5: std_logic; - signal mdout1_11_5: std_logic; - signal mdout1_10_5: std_logic; - signal mdout1_9_5: std_logic; - signal mdout1_8_5: std_logic; - signal mdout1_7_5: std_logic; - signal mdout1_6_5: std_logic; - signal mdout1_5_5: std_logic; - signal mdout1_4_5: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_31_6: std_logic; - signal mdout1_30_6: std_logic; - signal mdout1_29_6: std_logic; - signal mdout1_28_6: std_logic; - signal mdout1_27_6: std_logic; - signal mdout1_26_6: std_logic; - signal mdout1_25_6: std_logic; - signal mdout1_24_6: std_logic; - signal mdout1_23_6: std_logic; - signal mdout1_22_6: std_logic; - signal mdout1_21_6: std_logic; - signal mdout1_20_6: std_logic; - signal mdout1_19_6: std_logic; - signal mdout1_18_6: std_logic; - signal mdout1_17_6: std_logic; - signal mdout1_16_6: std_logic; - signal mdout1_15_6: std_logic; - signal mdout1_14_6: std_logic; - signal mdout1_13_6: std_logic; - signal mdout1_12_6: std_logic; - signal mdout1_11_6: std_logic; - signal mdout1_10_6: std_logic; - signal mdout1_9_6: std_logic; - signal mdout1_8_6: std_logic; - signal mdout1_7_6: std_logic; - signal mdout1_6_6: std_logic; - signal mdout1_5_6: std_logic; - signal mdout1_4_6: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_31_7: std_logic; - signal mdout1_30_7: std_logic; - signal mdout1_29_7: std_logic; - signal mdout1_28_7: std_logic; - signal mdout1_27_7: std_logic; - signal mdout1_26_7: std_logic; - signal mdout1_25_7: std_logic; - signal mdout1_24_7: std_logic; - signal mdout1_23_7: std_logic; - signal mdout1_22_7: std_logic; - signal mdout1_21_7: std_logic; - signal mdout1_20_7: std_logic; - signal mdout1_19_7: std_logic; - signal mdout1_18_7: std_logic; - signal mdout1_17_7: std_logic; - signal mdout1_16_7: std_logic; - signal mdout1_15_7: std_logic; - signal mdout1_14_7: std_logic; - signal mdout1_13_7: std_logic; - signal mdout1_12_7: std_logic; - signal mdout1_11_7: std_logic; - signal mdout1_10_7: std_logic; - signal mdout1_9_7: std_logic; - signal mdout1_8_7: std_logic; - signal mdout1_7_7: std_logic; - signal mdout1_6_7: std_logic; - signal mdout1_5_7: std_logic; - signal mdout1_4_7: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal rptr_13_ff: std_logic; - signal rptr_12_ff: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_31_8: std_logic; - signal mdout1_30_8: std_logic; - signal mdout1_29_8: std_logic; - signal mdout1_28_8: std_logic; - signal mdout1_27_8: std_logic; - signal mdout1_26_8: std_logic; - signal mdout1_25_8: std_logic; - signal mdout1_24_8: std_logic; - signal mdout1_23_8: std_logic; - signal mdout1_22_8: std_logic; - signal mdout1_21_8: std_logic; - signal mdout1_20_8: std_logic; - signal mdout1_19_8: std_logic; - signal mdout1_18_8: std_logic; - signal mdout1_17_8: std_logic; - signal mdout1_16_8: std_logic; - signal mdout1_15_8: std_logic; - signal mdout1_14_8: std_logic; - signal mdout1_13_8: std_logic; - signal mdout1_12_8: std_logic; - signal mdout1_11_8: std_logic; - signal mdout1_10_8: std_logic; - signal mdout1_9_8: std_logic; - signal mdout1_8_8: std_logic; - signal mdout1_7_8: std_logic; - signal mdout1_6_8: std_logic; - signal mdout1_5_8: std_logic; - signal mdout1_4_8: std_logic; - signal mdout1_3_8: std_logic; - signal mdout1_2_8: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal wcount_r14: std_logic; - signal wcount_r15: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal rcount_w14: std_logic; - signal rcount_w15: std_logic; - signal wcount_14: std_logic; - signal wcount_15: std_logic; - signal co7_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX321 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; D4: in std_logic; D5: in std_logic; - D6: in std_logic; D7: in std_logic; D8: in std_logic; - D9: in std_logic; D10: in std_logic; D11: in std_logic; - D12: in std_logic; D13: in std_logic; D14: in std_logic; - D15: in std_logic; D16: in std_logic; D17: in std_logic; - D18: in std_logic; D19: in std_logic; D20: in std_logic; - D21: in std_logic; D22: in std_logic; D23: in std_logic; - D24: in std_logic; D25: in std_logic; D26: in std_logic; - D27: in std_logic; D28: in std_logic; D29: in std_logic; - D30: in std_logic; D31: in std_logic; SD1: in std_logic; - SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; - SD5: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_187 : label is "0x8000"; - attribute initval of LUT4_186 : label is "0x8000"; - attribute initval of LUT4_185 : label is "0x8000"; - attribute initval of LUT4_184 : label is "0x8000"; - attribute initval of LUT4_183 : label is "0x8000"; - attribute initval of LUT4_182 : label is "0x8000"; - attribute initval of LUT4_181 : label is "0x8000"; - attribute initval of LUT4_180 : label is "0x8000"; - attribute initval of LUT4_179 : label is "0x8000"; - attribute initval of LUT4_178 : label is "0x8000"; - attribute initval of LUT4_177 : label is "0x8000"; - attribute initval of LUT4_176 : label is "0x8000"; - attribute initval of LUT4_175 : label is "0x8000"; - attribute initval of LUT4_174 : label is "0x8000"; - attribute initval of LUT4_173 : label is "0x8000"; - attribute initval of LUT4_172 : label is "0x8000"; - attribute initval of LUT4_171 : label is "0x8000"; - attribute initval of LUT4_170 : label is "0x8000"; - attribute initval of LUT4_169 : label is "0x8000"; - attribute initval of LUT4_168 : label is "0x8000"; - attribute initval of LUT4_167 : label is "0x8000"; - attribute initval of LUT4_166 : label is "0x8000"; - attribute initval of LUT4_165 : label is "0x8000"; - attribute initval of LUT4_164 : label is "0x8000"; - attribute initval of LUT4_163 : label is "0x8000"; - attribute initval of LUT4_162 : label is "0x8000"; - attribute initval of LUT4_161 : label is "0x8000"; - attribute initval of LUT4_160 : label is "0x8000"; - attribute initval of LUT4_159 : label is "0x8000"; - attribute initval of LUT4_158 : label is "0x8000"; - attribute initval of LUT4_157 : label is "0x8000"; - attribute initval of LUT4_156 : label is "0x8000"; - attribute initval of LUT4_155 : label is "0x8000"; - attribute initval of LUT4_154 : label is "0x8000"; - attribute initval of LUT4_153 : label is "0x8000"; - attribute initval of LUT4_152 : label is "0x8000"; - attribute initval of LUT4_151 : label is "0x8000"; - attribute initval of LUT4_150 : label is "0x8000"; - attribute initval of LUT4_149 : label is "0x8000"; - attribute initval of LUT4_148 : label is "0x8000"; - attribute initval of LUT4_147 : label is "0x8000"; - attribute initval of LUT4_146 : label is "0x8000"; - attribute initval of LUT4_145 : label is "0x8000"; - attribute initval of LUT4_144 : label is "0x8000"; - attribute initval of LUT4_143 : label is "0x8000"; - attribute initval of LUT4_142 : label is "0x8000"; - attribute initval of LUT4_141 : label is "0x8000"; - attribute initval of LUT4_140 : label is "0x8000"; - attribute initval of LUT4_139 : label is "0x8000"; - attribute initval of LUT4_138 : label is "0x8000"; - attribute initval of LUT4_137 : label is "0x8000"; - attribute initval of LUT4_136 : label is "0x8000"; - attribute initval of LUT4_135 : label is "0x8000"; - attribute initval of LUT4_134 : label is "0x8000"; - attribute initval of LUT4_133 : label is "0x8000"; - attribute initval of LUT4_132 : label is "0x8000"; - attribute initval of LUT4_131 : label is "0x8000"; - attribute initval of LUT4_130 : label is "0x8000"; - attribute initval of LUT4_129 : label is "0x8000"; - attribute initval of LUT4_128 : label is "0x8000"; - attribute initval of LUT4_127 : label is "0x8000"; - attribute initval of LUT4_126 : label is "0x8000"; - attribute initval of LUT4_125 : label is "0x8000"; - attribute initval of LUT4_124 : label is "0x8000"; - attribute initval of LUT4_123 : label is "0x8000"; - attribute initval of LUT4_122 : label is "0x8000"; - attribute initval of LUT4_121 : label is "0x8000"; - attribute initval of LUT4_120 : label is "0x8000"; - attribute initval of LUT4_119 : label is "0x8000"; - attribute initval of LUT4_118 : label is "0x8000"; - attribute initval of LUT4_117 : label is "0x8000"; - attribute initval of LUT4_116 : label is "0x8000"; - attribute initval of LUT4_115 : label is "0x8000"; - attribute initval of LUT4_114 : label is "0x8000"; - attribute initval of LUT4_113 : label is "0x8000"; - attribute initval of LUT4_112 : label is "0x8000"; - attribute initval of LUT4_111 : label is "0x8000"; - attribute initval of LUT4_110 : label is "0x8000"; - attribute initval of LUT4_109 : label is "0x8000"; - attribute initval of LUT4_108 : label is "0x8000"; - attribute initval of LUT4_107 : label is "0x8000"; - attribute initval of LUT4_106 : label is "0x8000"; - attribute initval of LUT4_105 : label is "0x8000"; - attribute initval of LUT4_104 : label is "0x8000"; - attribute initval of LUT4_103 : label is "0x8000"; - attribute initval of LUT4_102 : label is "0x8000"; - attribute initval of LUT4_101 : label is "0x8000"; - attribute initval of LUT4_100 : label is "0x8000"; - attribute initval of LUT4_99 : label is "0x8000"; - attribute initval of LUT4_98 : label is "0x8000"; - attribute initval of LUT4_97 : label is "0x8000"; - attribute initval of LUT4_96 : label is "0x8000"; - attribute initval of LUT4_95 : label is "0x8000"; - attribute initval of LUT4_94 : label is "0x8000"; - attribute initval of LUT4_93 : label is "0x8000"; - attribute initval of LUT4_92 : label is "0x8000"; - attribute initval of LUT4_91 : label is "0x8000"; - attribute initval of LUT4_90 : label is "0x8000"; - attribute initval of LUT4_89 : label is "0x8000"; - attribute initval of LUT4_88 : label is "0x8000"; - attribute initval of LUT4_87 : label is "0x8000"; - attribute initval of LUT4_86 : label is "0x8000"; - attribute initval of LUT4_85 : label is "0x8000"; - attribute initval of LUT4_84 : label is "0x8000"; - attribute initval of LUT4_83 : label is "0x8000"; - attribute initval of LUT4_82 : label is "0x8000"; - attribute initval of LUT4_81 : label is "0x8000"; - attribute initval of LUT4_80 : label is "0x8000"; - attribute initval of LUT4_79 : label is "0x8000"; - attribute initval of LUT4_78 : label is "0x8000"; - attribute initval of LUT4_77 : label is "0x8000"; - attribute initval of LUT4_76 : label is "0x8000"; - attribute initval of LUT4_75 : label is "0x8000"; - attribute initval of LUT4_74 : label is "0x8000"; - attribute initval of LUT4_73 : label is "0x8000"; - attribute initval of LUT4_72 : label is "0x8000"; - attribute initval of LUT4_71 : label is "0x8000"; - attribute initval of LUT4_70 : label is "0x8000"; - attribute initval of LUT4_69 : label is "0x8000"; - attribute initval of LUT4_68 : label is "0x8000"; - attribute initval of LUT4_67 : label is "0x8000"; - attribute initval of LUT4_66 : label is "0x8000"; - attribute initval of LUT4_65 : label is "0x8000"; - attribute initval of LUT4_64 : label is "0x8000"; - attribute initval of LUT4_63 : label is "0x8000"; - attribute initval of LUT4_62 : label is "0x8000"; - attribute initval of LUT4_61 : label is "0x8000"; - attribute initval of LUT4_60 : label is "0x8000"; - attribute initval of LUT4_59 : label is "0x6996"; - attribute initval of LUT4_58 : label is "0x6996"; - attribute initval of LUT4_57 : label is "0x6996"; - attribute initval of LUT4_56 : label is "0x6996"; - attribute initval of LUT4_55 : label is "0x6996"; - attribute initval of LUT4_54 : label is "0x6996"; - attribute initval of LUT4_53 : label is "0x6996"; - attribute initval of LUT4_52 : label is "0x6996"; - attribute initval of LUT4_51 : label is "0x6996"; - attribute initval of LUT4_50 : label is "0x6996"; - attribute initval of LUT4_49 : label is "0x6996"; - attribute initval of LUT4_48 : label is "0x6996"; - attribute initval of LUT4_47 : label is "0x6996"; - attribute initval of LUT4_46 : label is "0x6996"; - attribute initval of LUT4_45 : label is "0x6996"; - attribute initval of LUT4_44 : label is "0x6996"; - attribute initval of LUT4_43 : label is "0x6996"; - attribute initval of LUT4_42 : label is "0x6996"; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_30 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_30 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_30 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_30 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_30 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_30 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_30 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_30 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_30 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_1_0_30 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; - attribute CSDECODE_B of pdp_ram_2_0_29 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_2_0_29 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_2_0_29 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_0_29 : label is "NORMAL"; - attribute GSR of pdp_ram_2_0_29 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_0_29 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_0_29 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_0_29 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_0_29 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_2_0_29 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; - attribute CSDECODE_B of pdp_ram_3_0_28 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_3_0_28 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_3_0_28 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_0_28 : label is "NORMAL"; - attribute GSR of pdp_ram_3_0_28 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_0_28 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_0_28 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_0_28 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_0_28 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_3_0_28 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; - attribute CSDECODE_B of pdp_ram_4_0_27 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_4_0_27 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_4_0_27 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_4_0_27 : label is "NORMAL"; - attribute GSR of pdp_ram_4_0_27 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_4_0_27 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_4_0_27 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_4_0_27 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_4_0_27 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_4_0_27 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; - attribute CSDECODE_B of pdp_ram_5_0_26 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_5_0_26 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_5_0_26 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_5_0_26 : label is "NORMAL"; - attribute GSR of pdp_ram_5_0_26 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_5_0_26 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_5_0_26 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_5_0_26 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_5_0_26 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_5_0_26 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; - attribute CSDECODE_B of pdp_ram_6_0_25 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_6_0_25 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_6_0_25 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_6_0_25 : label is "NORMAL"; - attribute GSR of pdp_ram_6_0_25 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_6_0_25 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_6_0_25 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_6_0_25 : label is "NOREG"; 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- attribute RESETMODE of pdp_ram_26_0_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_26_0_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_26_0_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_26_0_5 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_26_0_5 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; - attribute CSDECODE_B of pdp_ram_27_0_4 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_27_0_4 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_27_0_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_27_0_4 : label is "NORMAL"; - attribute GSR of pdp_ram_27_0_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_27_0_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_27_0_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_27_0_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_27_0_4 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_27_0_4 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; - attribute CSDECODE_B of pdp_ram_28_0_3 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_28_0_3 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_28_0_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_28_0_3 : label is "NORMAL"; - attribute GSR of pdp_ram_28_0_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_28_0_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_28_0_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_28_0_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_28_0_3 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_28_0_3 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; - attribute CSDECODE_B of pdp_ram_29_0_2 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_29_0_2 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_29_0_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_29_0_2 : label is "NORMAL"; - attribute GSR of pdp_ram_29_0_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_29_0_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_29_0_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_29_0_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_29_0_2 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_29_0_2 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_30_0_1 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_30_0_1 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_30_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_30_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_30_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_30_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_30_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_30_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_30_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_30_0_1 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; - attribute CSDECODE_B of pdp_ram_31_0_0 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_31_0_0 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_31_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_31_0_0 : label is "NORMAL"; - attribute GSR of pdp_ram_31_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_31_0_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_31_0_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_31_0_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_31_0_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_31_0_0 : label is "9"; - attribute GSR of FF_176 : label is "ENABLED"; - attribute GSR of FF_175 : label is "ENABLED"; - attribute GSR of FF_174 : label is "ENABLED"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - AND2_t34: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_11: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t33: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_10: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t32: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t31: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t30: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t29: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t28: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t27: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t26: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t25: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t24: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t23: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t22: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t21: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t20: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t19: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t18: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t17: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t16: XOR2 - port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - INV_9: INV - port map (A=>wptr_11, Z=>wptr_11_inv); - - INV_8: INV - port map (A=>wptr_12, Z=>wptr_12_inv); - - INV_7: INV - port map (A=>wptr_13, Z=>wptr_13_inv); - - INV_6: INV - port map (A=>wptr_14, Z=>wptr_14_inv); - - INV_5: INV - port map (A=>wptr_15, Z=>wptr_15_inv); - - LUT4_187: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet); - - LUT4_186: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec0_p00); - - INV_4: INV - port map (A=>rptr_11, Z=>rptr_11_inv); - - INV_3: INV - port map (A=>rptr_12, Z=>rptr_12_inv); - - INV_2: INV - port map (A=>rptr_13, Z=>rptr_13_inv); - - INV_1: INV - port map (A=>rptr_14, Z=>rptr_14_inv); - - INV_0: INV - port map (A=>rptr_15, Z=>rptr_15_inv); - - LUT4_185: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_1); - - LUT4_184: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec1_r10); - - LUT4_183: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_2); - - LUT4_182: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec2_p01); - - LUT4_181: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_3); - - LUT4_180: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec3_r11); - - LUT4_179: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_4); - - LUT4_178: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec4_p02); - - LUT4_177: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_5); - - LUT4_176: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec5_r12); - - LUT4_175: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_6); - - LUT4_174: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec6_p03); - - LUT4_173: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_7); - - LUT4_172: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec7_r13); - - LUT4_171: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_8); - - LUT4_170: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec8_p04); - - LUT4_169: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_9); - - LUT4_168: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec9_r14); - - LUT4_167: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_10); - - LUT4_166: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - - LUT4_165: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_11); - - LUT4_164: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - - LUT4_163: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_12); - - LUT4_162: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - - LUT4_161: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_13); - - LUT4_160: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - - LUT4_159: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_14); - - LUT4_158: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - - LUT4_157: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_15); - - LUT4_156: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - - LUT4_155: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_16); - - LUT4_154: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - - LUT4_153: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_17); - - LUT4_152: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - - LUT4_151: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_18); - - LUT4_150: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - - LUT4_149: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_19); - - LUT4_148: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - - LUT4_147: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_20); - - LUT4_146: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - - LUT4_145: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_21); - - LUT4_144: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - - LUT4_143: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_22); - - LUT4_142: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - - LUT4_141: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_23); - - LUT4_140: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - - LUT4_139: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_24); - - LUT4_138: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - - LUT4_137: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_25); - - LUT4_136: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - - LUT4_135: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_26); - - LUT4_134: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - - LUT4_133: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_27); - - LUT4_132: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - - LUT4_131: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_28); - - LUT4_130: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - - LUT4_129: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_29); - - LUT4_128: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - - LUT4_127: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, - DO0=>func_and_inet_30); - - LUT4_126: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - - LUT4_125: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_31); - - LUT4_124: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, - AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - - LUT4_123: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_32); - - LUT4_122: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec32_p016); - - LUT4_121: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_33); - - LUT4_120: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec33_r116); - - LUT4_119: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_34); - - LUT4_118: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec34_p017); - - LUT4_117: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_35); - - LUT4_116: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec35_r117); - - LUT4_115: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_36); - - LUT4_114: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec36_p018); - - LUT4_113: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_37); - - LUT4_112: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec37_r118); - - LUT4_111: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14_inv, DO0=>func_and_inet_38); - - LUT4_110: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec38_p019); - - LUT4_109: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14_inv, DO0=>func_and_inet_39); - - LUT4_108: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec39_r119); - - LUT4_107: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_40); - - LUT4_106: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec40_p020); - - LUT4_105: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_41); - - LUT4_104: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec41_r120); - - LUT4_103: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_42); - - LUT4_102: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec42_p021); - - LUT4_101: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_43); - - LUT4_100: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec43_r121); - - LUT4_99: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_44); - - LUT4_98: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec44_p022); - - LUT4_97: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_45); - - LUT4_96: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec45_r122); - - LUT4_95: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14_inv, DO0=>func_and_inet_46); - - LUT4_94: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec46_p023); - - LUT4_93: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14_inv, DO0=>func_and_inet_47); - - LUT4_92: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec47_r123); - - LUT4_91: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_48); - - LUT4_90: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec48_p024); - - LUT4_89: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_49); - - LUT4_88: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec49_r124); - - LUT4_87: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_50); - - LUT4_86: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec50_p025); - - LUT4_85: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_51); - - LUT4_84: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec51_r125); - - LUT4_83: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_52); - - LUT4_82: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec52_p026); - - LUT4_81: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_53); - - LUT4_80: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec53_r126); - - LUT4_79: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, - AD0=>wptr_14, DO0=>func_and_inet_54); - - LUT4_78: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec54_p027); - - LUT4_77: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, - AD0=>rptr_14, DO0=>func_and_inet_55); - - LUT4_76: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec55_r127); - - LUT4_75: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_56); - - LUT4_74: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec56_p028); - - LUT4_73: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_57); - - LUT4_72: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec57_r128); - - LUT4_71: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_58); - - LUT4_70: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec58_p029); - - LUT4_69: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_59); - - LUT4_68: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec59_r129); - - LUT4_67: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, - AD0=>wptr_14, DO0=>func_and_inet_60); - - LUT4_66: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec60_p030); - - LUT4_65: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, - AD0=>rptr_14, DO0=>func_and_inet_61); - - LUT4_64: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec61_r130); - - LUT4_63: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, - DO0=>func_and_inet_62); - - LUT4_62: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec62_p031); - - LUT4_61: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, - DO0=>func_and_inet_63); - - LUT4_60: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on - port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, - AD0=>scuba_vhi, DO0=>dec63_r131); - - LUT4_59: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>w_gcount_r216, - DO0=>w_g2b_xor_cluster_0); - - LUT4_58: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_1); - - LUT4_57: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_2); - - LUT4_56: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_3); - - LUT4_55: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r15); - - LUT4_54: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, - AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_53: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, - DO0=>wcount_r10); - - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r3); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r2); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_10); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, - AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, - DO0=>func_xor_inet_11); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, - DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, - DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, - DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, - DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, - DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, - DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, - DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, - DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, - DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, - DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, - DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, - DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, - DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, - DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, - DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, - DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, - DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, - DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, - DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, - DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, - DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, - DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, - DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, - DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, - DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, - DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, - DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, - DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, - DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, - DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, - DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, - DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, - DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, - DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, - DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, - DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, - DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, - DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, - DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, - DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, - DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, - DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, - DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, - DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, - DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, - DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, - DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, - DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, - DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, - DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, - DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, - DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, - DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, - DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, - DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, - DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, - DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, - DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, - DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, - DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, - DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, - DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, - DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, - DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, - DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, - DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, - DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, - DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, - DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, - DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, - DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, - DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, - DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, - DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, - DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, - DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, - DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, - DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, - DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, - DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, - DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, - DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, - DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, - DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, - DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, - DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, - DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, - DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, - DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, - DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, - DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, - DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, - DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, - DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, - DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, - DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - FF_176: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_175: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_174: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_173: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_16); - - FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_16); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_135: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_134: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_133: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_132: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_16); - - FF_125: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_12_ff); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_13_ff); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r16); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r216); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - w_gctr_8: CU2 - port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>iwcount_16, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, - NC0=>ircount_16, NC1=>open); - - mux_8: MUX321 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, - D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, - D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, - D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, - D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, - D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, - D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, - D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, - D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, - D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(0)); - - mux_7: MUX321 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, - D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, - D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, - D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, - D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, - D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, - D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, - D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, - D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, - D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(1)); - - mux_6: MUX321 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, - D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, - D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, - D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, - D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, - D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, - D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, - D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, - D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, - D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(2)); - - mux_5: MUX321 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, - D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, - D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, - D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, - D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, - D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, - D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, - D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, - D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, - D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(3)); - - mux_4: MUX321 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, - D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, - D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, - D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, - D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, - D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, - D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, - D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, - D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, - D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(4)); - - mux_3: MUX321 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, - D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, - D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, - D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, - D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, - D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, - D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, - D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, - D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, - D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(5)); - - mux_2: MUX321 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, - D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, - D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, - D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, - D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, - D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, - D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, - D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, - D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, - D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(6)); - - mux_1: MUX321 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, - D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, - D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, - D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, - D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, - D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, - D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, - D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, - D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, - D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(7)); - - mux_0: MUX321 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, - D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, - D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, - D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, - D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, - D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, - D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, - D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, - D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, - D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, - D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, - SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, - SD5=>rptr_15_ff, Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, - B1=>wcount_r15, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, - B1=>rcount_w15, CI=>co6_3, GE=>co7_3); - - full_cmp_8: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_64kx9 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX321 use entity ecp2m.MUX321(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_64kx9_generate.log b/gbe_ecp2m/ipcores/fifo_64kx9_generate.log deleted file mode 100644 index 0cdd257..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx9_generate.log +++ /dev/null @@ -1,48 +0,0 @@ -Starting process: module - -Starting process: - -SCUBA, Version Diamond (64-bit) 3.9.1.119 -Thu Jan 18 18:38:41 2018 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 - Circuit name : fifo_64kx9 - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[8:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo_64kx9.edn - VHDL output : fifo_64kx9.vhd - VHDL template : fifo_64kx9_tmpl.vhd - VHDL testbench : tb_fifo_64kx9_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo_64kx9.srp - Estimated Resource Usage: - LUT : 379 - EBR : 32 - Reg : 177 - -END SCUBA Module Synthesis - -File: fifo_64kx9.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd deleted file mode 100644 index 80fb22a..0000000 --- a/gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd +++ /dev/null @@ -1,18 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.9.1.119 --- Module Version: 5.8 --- Thu Jan 18 18:38:41 2018 - --- parameterized module component declaration -component fifo_64kx9 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_64kx9 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); diff --git a/gbe_ecp2m/ipcores/ip_mem.lpc b/gbe_ecp2m/ipcores/ip_mem.lpc deleted file mode 100755 index 8383be6..0000000 --- a/gbe_ecp2m/ipcores/ip_mem.lpc +++ /dev/null @@ -1,57 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=RAM_DP_TRUE -CoreRevision=7.1 -ModuleName=ip_mem -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=03/29/2010 -Time=21:52:48 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -AAddress=256 -BAddress=256 -AData=32 -BData=32 -enByte=0 -ByteSize=9 -AadPipeline=0 -BadPipeline=0 -AinPipeline=0 -BinPipeline=0 -AoutPipeline=0 -BoutPipeline=1 -AMOR=0 -BMOR=0 -AInData=Registered -BInData=Registered -AAdControl=Registered -BAdControl=Registered -MemFile=/home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -MemFormat=orca -Reset=Sync -GSR=Enabled -WriteA=Normal -WriteB=Normal -Pad=0 -EnECC=0 -Optimization=Speed -Pipeline=0 diff --git a/gbe_ecp2m/ipcores/ip_mem.mem b/gbe_ecp2m/ipcores/ip_mem.mem deleted file mode 100755 index 836ca91..0000000 --- a/gbe_ecp2m/ipcores/ip_mem.mem +++ /dev/null @@ -1,277 +0,0 @@ -#Format=Address-Hex -#Depth=256 -#DataWidth=32 -#AddrRadix=3 -#DataRadix=3 - -00: 214397e9 -01: 0000001b -02: c0a80002 -03: 0000c350 -04: 023bdc00 -05: 00000013 -06: c0a80005 -07: 0000c350 -08: 00000578 -09: 00000000 -0a: 00000000 -0b: 00000000 -0c: 00000000 -0d: 00000000 -0e: 00000000 -0f: 00000000 - -10: 214397e9 -11: 0000001b -12: c0a80002 -13: 0000c351 -14: 023bdc01 -15: 00000013 -16: c0a80006 -17: 0000c350 -18: 00000578 -19: 00000000 -1a: 00000000 -1b: 00000000 -1c: 00000000 -1d: 00000000 -1e: 00000000 -1f: 00000000 - -20: 214397e9 -21: 0000001b -22: c0a80002 -23: 0000c352 -24: 023bdc02 -25: 00000013 -26: c0a80007 -27: 0000c350 -28: 00000578 -29: 00000000 -2a: 00000000 -2b: 00000000 -2c: 00000000 -2d: 00000000 -2e: 00000000 -2f: 00000000 - -30: 214397e9 -31: 0000001b -32: c0a80002 -33: 0000c353 -34: 023bdc03 -35: 00000013 -36: c0a80008 -37: 0000c350 -38: 00000578 -39: 00000000 -3a: 00000000 -3b: 00000000 -3c: 00000000 -3d: 00000000 -3e: 00000000 -3f: 00000000 - -40: 00000000 -41: 00000000 -42: 00000000 -43: 00000000 -44: 00000000 -45: 00000000 -46: 00000000 -47: 00000000 -48: 00000578 -49: 00000000 -4a: 00000000 -4b: 00000000 -4c: 00000000 -4d: 00000000 -4e: 00000000 -4f: 00000000 - -50: 00000000 -51: 00000000 -52: 00000000 -53: 00000000 -54: 00000000 -55: 00000000 -56: 00000000 -57: 00000000 -58: 00000578 -59: 00000000 -5a: 00000000 -5b: 00000000 -5c: 00000000 -5d: 00000000 -5e: 00000000 -5f: 00000000 - -60: 00000000 -61: 00000000 -62: 00000000 -63: 00000000 -64: 00000000 -65: 00000000 -66: 00000000 -67: 00000000 -68: 00000578 -69: 00000000 -6a: 00000000 -6b: 00000000 -6c: 00000000 -6d: 00000000 -6e: 00000000 -6f: 00000000 - -70: 00000000 -71: 00000000 -72: 00000000 -73: 00000000 -74: 00000000 -75: 00000000 -76: 00000000 -77: 00000000 -78: 00000578 -79: 00000000 -7a: 00000000 -7b: 00000000 -7c: 00000000 -7d: 00000000 -7e: 00000000 -7f: 00000000 - -80: 00000000 -81: 00000000 -82: 00000000 -83: 00000000 -84: 00000000 -85: 00000000 -86: 00000000 -87: 00000000 -88: 00000578 -89: 00000000 -8a: 00000000 -8b: 00000000 -8c: 00000000 -8d: 00000000 -8e: 00000000 -8f: 00000000 - -90: 00000000 -91: 00000000 -92: 00000000 -93: 00000000 -94: 00000000 -95: 00000000 -96: 00000000 -97: 00000000 -98: 00000578 -99: 00000000 -9a: 00000000 -9b: 00000000 -9c: 00000000 -9d: 00000000 -9e: 00000000 -9f: 00000000 - -a0: 00000000 -a1: 00000000 -a2: 00000000 -a3: 00000000 -a4: 00000000 -a5: 00000000 -a6: 00000000 -a7: 00000000 -a8: 00000578 -a9: 00000000 -aa: 00000000 -ab: 00000000 -ac: 00000000 -ad: 00000000 -ae: 00000000 -af: 00000000 - -b0: 00000000 -b1: 00000000 -b2: 00000000 -b3: 00000000 -b4: 00000000 -b5: 00000000 -b6: 00000000 -b7: 00000000 -b8: 00000578 -b9: 00000000 -ba: 00000000 -bb: 00000000 -bc: 00000000 -bd: 00000000 -be: 00000000 -bf: 00000000 - -c0: 00000000 -c1: 00000000 -c2: 00000000 -c3: 00000000 -c4: 00000000 -c5: 00000000 -c6: 00000000 -c7: 00000000 -c8: 00000578 -c9: 00000000 -ca: 00000000 -cb: 00000000 -cc: 00000000 -cd: 00000000 -ce: 00000000 -cf: 00000000 - -d0: 00000000 -d1: 00000000 -d2: 00000000 -d3: 00000000 -d4: 00000000 -d5: 00000000 -d6: 00000000 -d7: 00000000 -d8: 00000578 -d9: 00000000 -da: 00000000 -db: 00000000 -dc: 00000000 -dd: 00000000 -de: 00000000 -df: 00000000 - -e0: 00000000 -e1: 00000000 -e2: 00000000 -e3: 00000000 -e4: 00000000 -e5: 00000000 -e6: 00000000 -e7: 00000000 -e8: 00000578 -e9: 00000000 -ea: 00000000 -eb: 00000000 -ec: 00000000 -ed: 00000000 -ee: 00000000 -ef: 00000000 - -f0: 00000000 -f1: 00000000 -f2: 00000000 -f3: 00000000 -f4: 00000000 -f5: 00000000 -f6: 00000000 -f7: 00000000 -f8: 00000578 -f9: 00000000 -fa: 00000000 -fb: 00000000 -fc: 00000000 -fd: 00000000 -fe: 00000000 -ff: 00000000 diff --git a/gbe_ecp2m/ipcores/ip_mem.vhd b/gbe_ecp2m/ipcores/ip_mem.vhd deleted file mode 100755 index cfa2c6e..0000000 --- a/gbe_ecp2m/ipcores/ip_mem.vhd +++ /dev/null @@ -1,606 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 7.1 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e - --- Mon Mar 29 21:52:49 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity ip_mem is - port ( - DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(31 downto 0); - AddressA: in std_logic_vector(7 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(31 downto 0)); -end ip_mem; - -architecture Structure of ip_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (INITVAL_3F : in String; INITVAL_3E : in String; - INITVAL_3D : in String; INITVAL_3C : in String; - INITVAL_3B : in String; INITVAL_3A : in String; - INITVAL_39 : in String; INITVAL_38 : in String; - INITVAL_37 : in String; INITVAL_36 : in String; - INITVAL_35 : in String; INITVAL_34 : in String; - INITVAL_33 : in String; INITVAL_32 : in String; - INITVAL_31 : in String; INITVAL_30 : in String; - INITVAL_2F : in String; INITVAL_2E : in String; - INITVAL_2D : in String; INITVAL_2C : in String; - INITVAL_2B : in String; INITVAL_2A : in String; - INITVAL_29 : in String; INITVAL_28 : in String; - INITVAL_27 : in String; INITVAL_26 : in String; - INITVAL_25 : in String; INITVAL_24 : in String; - INITVAL_23 : in String; INITVAL_22 : in String; - INITVAL_21 : in String; INITVAL_20 : in String; - INITVAL_1F : in String; INITVAL_1E : in String; - INITVAL_1D : in String; INITVAL_1C : in String; - INITVAL_1B : in String; INITVAL_1A : in String; - INITVAL_19 : in String; INITVAL_18 : in String; - INITVAL_17 : in String; INITVAL_16 : in String; - INITVAL_15 : in String; INITVAL_14 : in String; - INITVAL_13 : in String; INITVAL_12 : in String; - INITVAL_11 : in String; INITVAL_10 : in String; - INITVAL_0F : in String; INITVAL_0E : in String; - INITVAL_0D : in String; INITVAL_0C : in String; - INITVAL_0B : in String; INITVAL_0A : in String; - INITVAL_09 : in String; INITVAL_08 : in String; - INITVAL_07 : in String; INITVAL_06 : in String; - INITVAL_05 : in String; INITVAL_04 : in String; - INITVAL_03 : in String; INITVAL_02 : in String; - INITVAL_01 : in String; INITVAL_00 : in String; - GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute INITVAL_3F : string; - attribute INITVAL_3E : string; - attribute INITVAL_3D : string; - attribute INITVAL_3C : string; - attribute INITVAL_3B : string; - attribute INITVAL_3A : string; - attribute INITVAL_39 : string; - attribute INITVAL_38 : string; - attribute INITVAL_37 : string; - attribute INITVAL_36 : string; - attribute INITVAL_35 : string; - attribute INITVAL_34 : string; - attribute INITVAL_33 : string; - attribute INITVAL_32 : string; - attribute INITVAL_31 : string; - attribute INITVAL_30 : string; - attribute INITVAL_2F : string; - attribute INITVAL_2E : string; - attribute INITVAL_2D : string; - attribute INITVAL_2C : string; - attribute INITVAL_2B : string; - attribute INITVAL_2A : string; - attribute INITVAL_29 : string; - attribute INITVAL_28 : string; - attribute INITVAL_27 : string; - attribute INITVAL_26 : string; - attribute INITVAL_25 : string; - attribute INITVAL_24 : string; - attribute INITVAL_23 : string; - attribute INITVAL_22 : string; - attribute INITVAL_21 : string; - attribute INITVAL_20 : string; - attribute INITVAL_1F : string; - attribute INITVAL_1E : string; - attribute INITVAL_1D : string; - attribute INITVAL_1C : string; - attribute INITVAL_1B : string; - attribute INITVAL_1A : string; - attribute INITVAL_19 : string; - attribute INITVAL_18 : string; - attribute INITVAL_17 : string; - attribute INITVAL_16 : string; - attribute INITVAL_15 : string; - attribute INITVAL_14 : string; - attribute INITVAL_13 : string; - attribute INITVAL_12 : string; - attribute INITVAL_11 : string; - attribute INITVAL_10 : string; - attribute INITVAL_0F : string; - attribute INITVAL_0E : string; - attribute INITVAL_0D : string; - attribute INITVAL_0C : string; - attribute INITVAL_0B : string; - attribute INITVAL_0A : string; - attribute INITVAL_09 : string; - attribute INITVAL_08 : string; - attribute INITVAL_07 : string; - attribute INITVAL_06 : string; - attribute INITVAL_05 : string; - attribute INITVAL_04 : string; - attribute INITVAL_03 : string; - attribute INITVAL_02 : string; - attribute INITVAL_01 : string; - attribute INITVAL_00 : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute GSR : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; - attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; - attribute INITVAL_3F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_39 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_38 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_37 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_36 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_35 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_34 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_33 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_32 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_31 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_30 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_29 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_28 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_27 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_26 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_25 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_24 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_23 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_22 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_21 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_20 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_19 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_18 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_17 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_16 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_15 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_14 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_13 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_12 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_11 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_10 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_09 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_08 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_07 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_06 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_05 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_04 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_03 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9"; - attribute INITVAL_02 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9"; - attribute INITVAL_01 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9"; - attribute INITVAL_00 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9"; - attribute CSDECODE_B of ip_mem_0_0_1 : label is "0b000"; - attribute CSDECODE_A of ip_mem_0_0_1 : label is "0b000"; - attribute WRITEMODE_B of ip_mem_0_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of ip_mem_0_0_1 : label is "NORMAL"; - attribute GSR of ip_mem_0_0_1 : label is "DISABLED"; - attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC"; - attribute REGMODE_B of ip_mem_0_0_1 : label is "OUTREG"; - attribute REGMODE_A of ip_mem_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of ip_mem_0_0_1 : label is "18"; - attribute DATA_WIDTH_A of ip_mem_0_0_1 : label is "18"; - attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; - attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; - attribute INITVAL_3F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_39 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_38 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_37 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_36 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_35 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_34 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_33 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_32 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_31 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_30 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_29 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_28 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_27 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_26 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_25 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_24 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_23 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_22 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_21 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_20 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_19 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_18 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_17 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_16 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_15 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_14 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_13 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_12 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_11 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_10 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_09 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_08 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_07 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_06 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_05 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_04 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_03 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute INITVAL_02 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute INITVAL_01 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute INITVAL_00 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute CSDECODE_B of ip_mem_0_1_0 : label is "0b000"; - attribute CSDECODE_A of ip_mem_0_1_0 : label is "0b000"; - attribute WRITEMODE_B of ip_mem_0_1_0 : label is "NORMAL"; - attribute WRITEMODE_A of ip_mem_0_1_0 : label is "NORMAL"; - attribute GSR of ip_mem_0_1_0 : label is "DISABLED"; - attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC"; - attribute REGMODE_B of ip_mem_0_1_0 : label is "OUTREG"; - attribute REGMODE_A of ip_mem_0_1_0 : label is "NOREG"; - attribute DATA_WIDTH_B of ip_mem_0_1_0 : label is "18"; - attribute DATA_WIDTH_A of ip_mem_0_1_0 : label is "18"; - -begin - -- component instantiation statements - ip_mem_0_0_1: DP16KB - -- synopsys translate_off - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9", - INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", - INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", - INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", - CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), - DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), - DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), - DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11), - DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14), - DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17), - ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, - ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), - ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), - ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, - CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0), - DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3), - DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6), - DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9), - DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12), - DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15), - DIB16=>DataInB(16), DIB17=>DataInB(17), ADB0=>scuba_vhi, - ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo, - ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2), - ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5), - ADB10=>AddressB(6), ADB11=>AddressB(7), ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2), - DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6), - DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10), - DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14), - DOA15=>QA(15), DOA16=>QA(16), DOA17=>QA(17), DOB0=>QB(0), - DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4), - DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8), - DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12), - DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>QB(16), - DOB17=>QB(17)); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - ip_mem_0_1_0: DP16KB - -- synopsys translate_off - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 18) - -- synopsys translate_on - port map (DIA0=>DataInA(18), DIA1=>DataInA(19), - DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22), - DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25), - DIA8=>DataInA(26), DIA9=>DataInA(27), DIA10=>DataInA(28), - DIA11=>DataInA(29), DIA12=>DataInA(30), DIA13=>DataInA(31), - DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo, - DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>AddressA(0), - ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3), - ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6), - ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, - DIB0=>DataInB(18), DIB1=>DataInB(19), DIB2=>DataInB(20), - DIB3=>DataInB(21), DIB4=>DataInB(22), DIB5=>DataInB(23), - DIB6=>DataInB(24), DIB7=>DataInB(25), DIB8=>DataInB(26), - DIB9=>DataInB(27), DIB10=>DataInB(28), DIB11=>DataInB(29), - DIB12=>DataInB(30), DIB13=>DataInB(31), DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1), - ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4), - ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7), - ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB, - CLKB=>ClockB, WEB=>WrB, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), - DOA2=>QA(20), DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), - DOA6=>QA(24), DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), - DOA10=>QA(28), DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>QB(18), DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), - DOB4=>QB(22), DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), - DOB8=>QB(26), DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), - DOB12=>QB(30), DOB13=>QB(31), DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of ip_mem is - for Structure - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd b/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd deleted file mode 100755 index 7d1cea6..0000000 --- a/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd +++ /dev/null @@ -1,23 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 7.1 --- Mon Mar 29 21:52:49 2010 - --- parameterized module component declaration -component ip_mem - port (DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(31 downto 0); - AddressA: in std_logic_vector(7 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; ClockB: in std_logic; - ClockEnA: in std_logic; ClockEnB: in std_logic; - WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic; - ResetB: in std_logic; QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(31 downto 0)); -end component; - --- parameterized module component instance -__ : ip_mem - port map (DataInA(31 downto 0)=>__, DataInB(31 downto 0)=>__, - AddressA(7 downto 0)=>__, AddressB(7 downto 0)=>__, ClockA=>__, - ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, - ResetB=>__, QA(31 downto 0)=>__, QB(31 downto 0)=>__); diff --git a/gbe_ecp2m/ipcores/macInitDataInvWithMac.mem b/gbe_ecp2m/ipcores/macInitDataInvWithMac.mem deleted file mode 100755 index c93b822..0000000 --- a/gbe_ecp2m/ipcores/macInitDataInvWithMac.mem +++ /dev/null @@ -1,59 +0,0 @@ -#Format=Bin -#Depth=54 -#Width=8 -#AddrRadix=3 -#DataRadix=3 -#Data -00001111 -00001111 -10011001 -00000001 -11101110 -00000101 -00000000 -00000000 -00001100 -00000000 -00110100 -00010010 -01111000 -01010110 -10111100 -10011010 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -10000000 diff --git a/gbe_ecp2m/ipcores/mac_init_mem.lpc b/gbe_ecp2m/ipcores/mac_init_mem.lpc deleted file mode 100755 index 02c8376..0000000 --- a/gbe_ecp2m/ipcores/mac_init_mem.lpc +++ /dev/null @@ -1,45 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-6F900C -SpeedGrade=-6 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=ROM -CoreRevision=5.0 -ModuleName=mac_init_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=08/20/2009 -Time=16:00:49 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Address=54 -Data=8 -adPipeline=0 -inPipeline=0 -outPipeline=1 -MOR=0 -InData=Registered -AdControl=Registered -MemFile=/home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -MemFormat=bin -Reset=Sync -Pad=0 -GSR=Enabled -EnECC=0 -Optimization=Speed -Pipeline=0 diff --git a/gbe_ecp2m/ipcores/mac_init_mem.vhd b/gbe_ecp2m/ipcores/mac_init_mem.vhd deleted file mode 100755 index c2c95e4..0000000 --- a/gbe_ecp2m/ipcores/mac_init_mem.vhd +++ /dev/null @@ -1,413 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.0 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - --- Thu Aug 20 16:00:49 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity mac_init_mem is - port ( - Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; - OutClockEn: in std_logic; - Reset: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end mac_init_mem; - -architecture Structure of mac_init_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (INITVAL_3F : in String; INITVAL_3E : in String; - INITVAL_3D : in String; INITVAL_3C : in String; - INITVAL_3B : in String; INITVAL_3A : in String; - INITVAL_39 : in String; INITVAL_38 : in String; - INITVAL_37 : in String; INITVAL_36 : in String; - INITVAL_35 : in String; INITVAL_34 : in String; - INITVAL_33 : in String; INITVAL_32 : in String; - INITVAL_31 : in String; INITVAL_30 : in String; - INITVAL_2F : in String; INITVAL_2E : in String; - INITVAL_2D : in String; INITVAL_2C : in String; - INITVAL_2B : in String; INITVAL_2A : in String; - INITVAL_29 : in String; INITVAL_28 : in String; - INITVAL_27 : in String; INITVAL_26 : in String; - INITVAL_25 : in String; INITVAL_24 : in String; - INITVAL_23 : in String; INITVAL_22 : in String; - INITVAL_21 : in String; INITVAL_20 : in String; - INITVAL_1F : in String; INITVAL_1E : in String; - INITVAL_1D : in String; INITVAL_1C : in String; - INITVAL_1B : in String; INITVAL_1A : in String; - INITVAL_19 : in String; INITVAL_18 : in String; - INITVAL_17 : in String; INITVAL_16 : in String; - INITVAL_15 : in String; INITVAL_14 : in String; - INITVAL_13 : in String; INITVAL_12 : in String; - INITVAL_11 : in String; INITVAL_10 : in String; - INITVAL_0F : in String; INITVAL_0E : in String; - INITVAL_0D : in String; INITVAL_0C : in String; - INITVAL_0B : in String; INITVAL_0A : in String; - INITVAL_09 : in String; INITVAL_08 : in String; - INITVAL_07 : in String; INITVAL_06 : in String; - INITVAL_05 : in String; INITVAL_04 : in String; - INITVAL_03 : in String; INITVAL_02 : in String; - INITVAL_01 : in String; INITVAL_00 : in String; - GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute INITVAL_3F : string; - attribute INITVAL_3E : string; - attribute INITVAL_3D : string; - attribute INITVAL_3C : string; - attribute INITVAL_3B : string; - attribute INITVAL_3A : string; - attribute INITVAL_39 : string; - attribute INITVAL_38 : string; - attribute INITVAL_37 : string; - attribute INITVAL_36 : string; - attribute INITVAL_35 : string; - attribute INITVAL_34 : string; - attribute INITVAL_33 : string; - attribute INITVAL_32 : string; - attribute INITVAL_31 : string; - attribute INITVAL_30 : string; - attribute INITVAL_2F : string; - attribute INITVAL_2E : string; - attribute INITVAL_2D : string; - attribute INITVAL_2C : string; - attribute INITVAL_2B : string; - attribute INITVAL_2A : string; - attribute INITVAL_29 : string; - attribute INITVAL_28 : string; - attribute INITVAL_27 : string; - attribute INITVAL_26 : string; - attribute INITVAL_25 : string; - attribute INITVAL_24 : string; - attribute INITVAL_23 : string; - attribute INITVAL_22 : string; - attribute INITVAL_21 : string; - attribute INITVAL_20 : string; - attribute INITVAL_1F : string; - attribute INITVAL_1E : string; - attribute INITVAL_1D : string; - attribute INITVAL_1C : string; - attribute INITVAL_1B : string; - attribute INITVAL_1A : string; - attribute INITVAL_19 : string; - attribute INITVAL_18 : string; - attribute INITVAL_17 : string; - attribute INITVAL_16 : string; - attribute INITVAL_15 : string; - attribute INITVAL_14 : string; - attribute INITVAL_13 : string; - attribute INITVAL_12 : string; - attribute INITVAL_11 : string; - attribute INITVAL_10 : string; - attribute INITVAL_0F : string; - attribute INITVAL_0E : string; - attribute INITVAL_0D : string; - attribute INITVAL_0C : string; - attribute INITVAL_0B : string; - attribute INITVAL_0A : string; - attribute INITVAL_09 : string; - attribute INITVAL_08 : string; - attribute INITVAL_07 : string; - attribute INITVAL_06 : string; - attribute INITVAL_05 : string; - attribute INITVAL_04 : string; - attribute INITVAL_03 : string; - attribute INITVAL_02 : string; - attribute INITVAL_01 : string; - attribute INITVAL_00 : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute GSR : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc"; - attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem"; - attribute INITVAL_3F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_39 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_38 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_37 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_36 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_35 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_34 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_33 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_32 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_31 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_30 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_29 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_28 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_27 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_26 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_25 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_24 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_23 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_22 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_21 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_20 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_19 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_18 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_17 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_16 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_15 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_14 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_13 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_12 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_11 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_10 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_09 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_08 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_07 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_06 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_05 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_04 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_03 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_02 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_01 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000"; - attribute INITVAL_00 of mac_init_mem_0_0_0 : label is "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F"; - attribute CSDECODE_B of mac_init_mem_0_0_0 : label is "0b111"; - attribute CSDECODE_A of mac_init_mem_0_0_0 : label is "0b000"; - attribute WRITEMODE_B of mac_init_mem_0_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of mac_init_mem_0_0_0 : label is "NORMAL"; - attribute GSR of mac_init_mem_0_0_0 : label is "DISABLED"; - attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC"; - attribute REGMODE_B of mac_init_mem_0_0_0 : label is "NOREG"; - attribute REGMODE_A of mac_init_mem_0_0_0 : label is "OUTREG"; - attribute DATA_WIDTH_B of mac_init_mem_0_0_0 : label is "9"; - attribute DATA_WIDTH_A of mac_init_mem_0_0_0 : label is "9"; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - mac_init_mem_0_0_0: DP16KB - -- synopsys translate_off - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", - INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", - CSDECODE_B=> "111", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, - ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), - ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), - ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, - CLKA=>OutClock, WEA=>scuba_vlo, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>scuba_vlo, - ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo, - ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo, - ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>scuba_vhi, - CLKB=>scuba_vlo, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>scuba_vlo, - DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), - DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7), DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>open, DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of mac_init_mem is - for Structure - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd b/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd deleted file mode 100755 index 1aee5c2..0000000 --- a/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd +++ /dev/null @@ -1,15 +0,0 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.0 --- Thu Aug 20 16:00:49 2009 - --- parameterized module component declaration -component mac_init_mem - port (Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q: out std_logic_vector(7 downto 0)); -end component; - --- parameterized module component instance -__ : mac_init_mem - port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__, - Reset=>__, Q(7 downto 0)=>__); diff --git a/gbe_ecp2m/ipcores/serdes/.cvsignore b/gbe_ecp2m/ipcores/serdes/.cvsignore deleted file mode 100644 index 85eef7b..0000000 --- a/gbe_ecp2m/ipcores/serdes/.cvsignore +++ /dev/null @@ -1,9 +0,0 @@ -*.jhd -*.naf -*.srp -*.sym -*.log -*.pp -*.tft -*.readme -*tmpl.vhd diff --git a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.lpc b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.lpc deleted file mode 100755 index 4efe9cf..0000000 --- a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.lpc +++ /dev/null @@ -1,140 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-6F900C -SpeedGrade=-6 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=7.0 -ModuleName=serdes_gbe_0_extclock_8b -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=08/20/2009 -Time=11:50:53 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Protocol=Quad -mode=Gigabit Ethernet -Channel0=SINGLE -Channel1=DISABLE -Channel2=DISABLE -Channel3=DISABLE -Rate0=None -Rate1=None -Rate2=None -Rate3=None -TxRefClk=REFCLK -RxRefClk=REFCLK -ClkRate=1.25 -ClkMult=10X -CalClkRate=125.0 -DataWidth=8 -FPGAClkRate=125.0 -TxRefClkCM=REFCLK -RxRefClk0CM=REFCLK -RxRefClk1CM=REFCLK -RxRefClk2CM=REFCLK -RxRefClk3CM=REFCLK -ClkRateH=0.625 -ClkMultH=10XH -CalClkRateH=125.0 -DataWidthH=8 -FPGAClkRateH=62.5 -VCh0=0 -VCh1=0 -VCh2=0 -VCh3=0 -PreCh0=DISABLE -PreCh1=DISABLE -PreCh2=DISABLE -PreCh3=DISABLE -TxCh0=50 -TxCh1=50 -TxCh2=50 -TxCh3=50 -EqCh0=DISABLE -EqCh1=DISABLE -EqCh2=DISABLE -EqCh3=DISABLE -RxTermCh0=50 -RxTermCh1=50 -RxTermCh2=50 -RxTermCh3=50 -RxCoupCh0=AC -RxCoupCh1=AC -RxCoupCh2=AC -RxCoupCh3=AC -Loss=0 -CDRLoss=0 -TxTerm=50 -TxCoup=AC -TxPllLoss=0 -TxInvCh0=NORMAL -TxInvCh1=NORMAL -TxInvCh2=NORMAL -TxInvCh3=NORMAL -RxInvCh0=NORMAL -RxInvCh1=NORMAL -RxInvCh2=NORMAL -RxInvCh3=NORMAL -RxModeCh0=NORMAL -RxModeCh1=NORMAL -RxModeCh2=NORMAL -RxModeCh3=NORMAL -Plus=1100000101 -Minus=0011111010 -Mask=1111111111 -Align=AUTO -CTCCh0=NORMAL -CTCCh1=NORMAL -CTCCh2=NORMAL -CTCCh3=NORMAL -CC_MATCH1=0000000000 -CC_MATCH2=0000000000 -CC_MATCH3=0110111100 -CC_MATCH4=0001010000 -MinIPG=3 -High=9 -Low=7 -CC_MATCH_MODE=MATCH_3_4 -RxDataCh0=FALSE -RxDataCh1=FALSE -RxDataCh2=FALSE -RxDataCh3=FALSE -AlignerCh0=FALSE -AlignerCh1=FALSE -AlignerCh2=FALSE -AlignerCh3=FALSE -DetectCh0=FALSE -DetectCh1=FALSE -DetectCh2=FALSE -DetectCh3=FALSE -ELSMCh0=FALSE -ELSMCh1=FALSE -ELSMCh2=FALSE -ELSMCh3=FALSE -_teidleCh0=FALSE -_teidleCh1=FALSE -_teidleCh2=FALSE -_teidleCh3=FALSE -Ports0=FALSE -rdoPorts0=Serial Loopback -Ports1=FALSE -Ports2=TRUE -Ports3=FALSE -Ports3_1=FALSE -Ports4=FALSE diff --git a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.txt b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.txt deleted file mode 100755 index 860001f..0000000 --- a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.txt +++ /dev/null @@ -1,49 +0,0 @@ - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSC quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSC quad to the final design requirements. - -DEVICE_NAME "LFE2M100E" -PROTOCOL "GIGE" -CH0_MODE "SINGLE" -CH1_MODE "DISABLE" -CH2_MODE "DISABLE" -CH3_MODE "DISABLE" -PLL_SRC "REFCLK" -DATARANGE "MED" -CH0_CDR_SRC "REFCLK" -CH0_DATA_WIDTH "8" -CH0_REFCK_MULT "10X" -#REFCLK_RATE 125.0 -#FPGAINTCLK_RATE 125.0 -CH0_TDRV_AMP "0" -CH0_TX_PRE "DISABLE" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLE" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -LOS_THRESHOLD "0" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "NORMAL" -CH0_RX_SB "NORMAL" -CH0_8B10B "NORMAL" -COMMA_A "1100000101" -COMMA_B "0011111010" -COMMA_M "1111111111" -CH0_COMMA_ALIGN "AUTO" -CH0_CTC_BYP "BYPASS" -CC_MATCH1 "0000000000" -CC_MATCH2 "0000000000" -CC_MATCH3 "0110111100" -CC_MATCH4 "0001010000" -CC_MATCH_MODE "MATCH_3_4" -CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -OS_REFCK2CORE "1" -OS_PLLQCLKPORTS "0" -OS_INT_ALL "0" - diff --git a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd b/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd deleted file mode 100755 index c3d0eda..0000000 --- a/gbe_ecp2m/ipcores/serdes/serdes_gbe_0_extclock_8b.vhd +++ /dev/null @@ -1,2182 +0,0 @@ - - ---synopsys translate_off - -library pcsc_work; -use pcsc_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSC is -GENERIC( - CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); - -end PCSC; - -architecture PCSC_arch of PCSC is - -component PCSC_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - -begin - -PCSC_sim_inst : PCSC_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, - FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, - FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, - FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, - FF_TX_F_CLK => FF_TX_F_CLK, - FF_TX_H_CLK => FF_TX_H_CLK, - FF_TX_Q_CLK => FF_TX_Q_CLK, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - OOB_OUT_0 => OOB_OUT_0, - OOB_OUT_1 => OOB_OUT_1, - OOB_OUT_2 => OOB_OUT_2, - OOB_OUT_3 => OOB_OUT_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7 - ); - -end PCSC_arch; - ---synopsys translate_on - ---synopsys translate_off -library ECP2; -use ECP2.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_extclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"); - port ( - refclkp, refclkn : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - refck2core : out std_logic; - ffs_plol : out std_logic); - -end serdes_gbe_0_extclock_8b; - -architecture serdes_gbe_0_extclock_8b_arch of serdes_gbe_0_extclock_8b is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; -component PCSC ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal fpsc_vlo : std_logic := '0'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSC_INST : PCSC ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - FFC_CK_CORE_TX => fpsc_vlo, - FFC_CK_CORE_RX => fpsc_vlo, - REFCLKP => refclkp, - REFCLKN => refclkn, - HDINP0 => hdinp0, - HDINN0 => hdinn0, - HDOUTP0 => hdoutp0, - HDOUTN0 => hdoutn0, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => ff_rxiclk_ch0, - FF_TXI_CLK_0 => ff_txiclk_ch0, - FF_EBRD_CLK_0 => ff_ebrd_clk_0, - FF_RX_F_CLK_0 => ff_rxfullclk_ch0, - FF_RX_H_CLK_0 => open, - FF_RX_Q_CLK_0 => open, - FF_TX_D_0_0 => ff_txdata_ch0(0), - FF_TX_D_0_1 => ff_txdata_ch0(1), - FF_TX_D_0_2 => ff_txdata_ch0(2), - FF_TX_D_0_3 => ff_txdata_ch0(3), - FF_TX_D_0_4 => ff_txdata_ch0(4), - FF_TX_D_0_5 => ff_txdata_ch0(5), - FF_TX_D_0_6 => ff_txdata_ch0(6), - FF_TX_D_0_7 => ff_txdata_ch0(7), - FF_TX_D_0_8 => ff_tx_k_cntrl_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => ff_xmit_ch0, - FF_TX_D_0_11 => ff_correct_disp_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => ff_rxdata_ch0(0), - FF_RX_D_0_1 => ff_rxdata_ch0(1), - FF_RX_D_0_2 => ff_rxdata_ch0(2), - FF_RX_D_0_3 => ff_rxdata_ch0(3), - FF_RX_D_0_4 => ff_rxdata_ch0(4), - FF_RX_D_0_5 => ff_rxdata_ch0(5), - FF_RX_D_0_6 => ff_rxdata_ch0(6), - FF_RX_D_0_7 => ff_rxdata_ch0(7), - FF_RX_D_0_8 => ff_rx_k_cntrl_ch0, - FF_RX_D_0_9 => ff_disp_err_ch0, - FF_RX_D_0_10 => ff_cv_ch0, - FF_RX_D_0_11 => ff_rx_even_ch0, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - FFC_RRST_0 => ffc_rrst_ch0, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFS_PCIE_DONE_0 => open, - FFS_PCIE_CON_0 => open, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, - FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, - FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, - FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, - FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, - FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, - FFS_CC_UNDERRUN_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - FFS_RLOL_0 => ffs_rlol_ch0, - OOB_OUT_0 => oob_out_ch0, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - HDOUTP1 => open, - HDOUTN1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_RX_Q_CLK_1 => open, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_PCIE_CON_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - OOB_OUT_1 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - HDOUTP2 => open, - HDOUTN2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_RX_Q_CLK_2 => open, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_PCIE_CON_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - OOB_OUT_2 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - HDOUTP3 => open, - HDOUTN3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_RX_Q_CLK_3 => open, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_PCIE_CON_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - OOB_OUT_3 => open, - SCIWDATA0 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA7 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIRDATA0 => open, - SCIRDATA1 => open, - SCIRDATA2 => open, - SCIRDATA3 => open, - SCIRDATA4 => open, - SCIRDATA5 => open, - SCIRDATA6 => open, - SCIRDATA7 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_MACRO_RST => ffc_macro_rst, - FFC_QUAD_RST => ffc_quad_rst, - FFC_TRST => ffc_trst, - FF_TX_F_CLK => ff_txfullclk, - FF_TX_H_CLK => ff_txhalfclk, - FF_TX_Q_CLK => open, - REFCK2CORE => refck2core, - CIN0 => cin(0), - CIN1 => cin(1), - CIN2 => cin(2), - CIN3 => cin(3), - CIN4 => cin(4), - CIN5 => cin(5), - CIN6 => cin(6), - CIN7 => cin(7), - CIN8 => cin(8), - CIN9 => cin(9), - CIN10 => cin(10), - CIN11 => cin(11), - COUT0 => cout(0), - COUT1 => cout(1), - COUT2 => cout(2), - COUT3 => cout(3), - COUT4 => cout(4), - COUT5 => cout(5), - COUT6 => cout(6), - COUT7 => cout(7), - COUT8 => cout(8), - COUT9 => cout(9), - COUT10 => cout(10), - COUT11 => cout(11), - COUT12 => cout(12), - COUT13 => cout(13), - COUT14 => cout(14), - COUT15 => cout(15), - COUT16 => cout(16), - COUT17 => cout(17), - COUT18 => cout(18), - COUT19 => cout(19), - FFS_PLOL => ffs_plol); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end serdes_gbe_0_extclock_8b_arch ; diff --git a/gbe_ecp2m/ipcores/serdes_ch4.ipx b/gbe_ecp2m/ipcores/serdes_ch4.ipx deleted file mode 100644 index 82a5965..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/gbe_ecp2m/ipcores/serdes_ch4.jhd b/gbe_ecp2m/ipcores/serdes_ch4.jhd deleted file mode 100644 index 0338a8f..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.jhd +++ /dev/null @@ -1,7 +0,0 @@ -MODULE serdes_ch4 DEFIN serdes_ch4.vhd - SUBMODULE PCSD - INSTANCE PCSD_INST - SUBMODULE VHI - INSTANCE vhi_inst - SUBMODULE VLO - INSTANCE vlo_inst diff --git a/gbe_ecp2m/ipcores/serdes_ch4.lpc b/gbe_ecp2m/ipcores/serdes_ch4.lpc deleted file mode 100644 index daf6272..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_ch4 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/04/2012 -Time=20:33:49 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=DISABLED -_mode1=DISABLED -_mode2=DISABLED -_mode3=RXTX -_protocol0=G8B10B -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=GIGE -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=1.25 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=125.0 -_tx_protocol0=DISABLED -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=GIGE -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=125.0 -_tx_ficlk_rate1=125.0 -_tx_ficlk_rate2=125.0 -_tx_ficlk_rate3=125.0 -_pll_rxsrc0=EXTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=INTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=2.5 -_rx_datarange1=2.5 -_rx_datarange2=2.5 -_rx_datarange3=1.25 -_rx_protocol0=DISABLED -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=GIGE -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=250.0 -_rxrefclk_rate1=250.0 -_rxrefclk_rate2=250.0 -_rxrefclk_rate3=125.0 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=ENABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=ENABLED -_rx_ficlk_rate0=250.0 -_rx_ficlk_rate1=250.0 -_rx_ficlk_rate2=250.0 -_rx_ficlk_rate3=125.0 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=AC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=AC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P157 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P5 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111100 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111111 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=1 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=2 -_k00=00 -_k01=00 -_k02=00 -_k03=01 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=01 -_k31=01 -_k32=01 -_k33=00 -_byten00=00000000 -_byten01=00000000 -_byten02=00000000 -_byten03=10111100 -_byten10=00000000 -_byten11=00000000 -_byten12=00000000 -_byten13=01010000 -_byten20=00011100 -_byten21=00011100 -_byten22=00011100 -_byten23=10111100 -_byten30=00011100 -_byten31=00011100 -_byten32=00011100 -_byten33=01010000 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=DISABLED -_sci_int_port=DISABLED -_refck2core=DISABLED -Regen=auto -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_ch4.pp=pp -serdes_ch4.tft=tft -serdes_ch4.txt=pcs_module -serdes_ch4.sym=sym diff --git a/gbe_ecp2m/ipcores/serdes_ch4.naf b/gbe_ecp2m/ipcores/serdes_ch4.naf deleted file mode 100644 index 22645f6..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.naf +++ /dev/null @@ -1,48 +0,0 @@ -hdinp_ch3 i -hdinn_ch3 i -hdoutp_ch3 o -hdoutn_ch3 o -rxiclk_ch3 i -txiclk_ch3 i -rx_full_clk_ch3 o -rx_half_clk_ch3 o -tx_full_clk_ch3 o -tx_half_clk_ch3 o -fpga_rxrefclk_ch3 i -txdata_ch3[7] i -txdata_ch3[6] i -txdata_ch3[5] i -txdata_ch3[4] i -txdata_ch3[3] i -txdata_ch3[2] i -txdata_ch3[1] i -txdata_ch3[0] i -tx_k_ch3 i -xmit_ch3 i -tx_disp_correct_ch3 i -rxdata_ch3[7] o -rxdata_ch3[6] o -rxdata_ch3[5] o -rxdata_ch3[4] o -rxdata_ch3[3] o -rxdata_ch3[2] o -rxdata_ch3[1] o -rxdata_ch3[0] o -rx_k_ch3 o -rx_disp_err_ch3 o -rx_cv_err_ch3 o -rx_serdes_rst_ch3_c i -sb_felb_ch3_c i -sb_felb_rst_ch3_c i -tx_pcs_rst_ch3_c i -tx_pwrup_ch3_c i -rx_pcs_rst_ch3_c i -rx_pwrup_ch3_c i -rx_los_low_ch3_s o -lsm_status_ch3_s o -rx_cdr_lol_ch3_s o -fpga_txrefclk i -tx_serdes_rst_c i -tx_pll_lol_qd_s o -rst_qd_c i -serdes_rst_qd_c i diff --git a/gbe_ecp2m/ipcores/serdes_ch4.pp b/gbe_ecp2m/ipcores/serdes_ch4.pp deleted file mode 100644 index 76f371d..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.pp +++ /dev/null @@ -1,191 +0,0 @@ -#define _device_name "LFE3-150EA" -#define _ch0_pll_rxsrc "REFCLK_EXT" -#define _ch0_mode "DISABLED" -#define _ch0_protocol "G8B10B" -#define _ch0_ldr "DISABLED" -#define _ch0_tx_data_rate "FULL" -#define _ch0_tx_data_width "8" -#define _ch0_tx_fifo "ENABLED" -#define _ch0_tx_ficlk_rate 125.0 -#define _ch0_rx_datarange "MEDHIGH" -#define _ch0_rx_data_rate "FULL" -#define _ch0_rxrefclk_rate "250.0" -#define _ch0_rx_data_width "8" -#define _ch0_rx_fifo "ENABLED" -#define _ch0_rx_ficlk_rate 250.0 -#define _ch0_tdrv "0" -#define _ch0_tx_pre "DISABLED" -#define _ch0_rterm_tx "50" -#define _ch0_rx_eq "DISABLED" -#define _ch0_rterm_rx "50" -#define _ch0_rx_dcc "AC" -#define _los_threshold_lo0 "2" -#define _ch0_tx_sb "DISABLED" -#define _ch0_tx_8b10b "ENABLED" -#define _ch0_rx_sb "DISABLED" -#define _ch0_ird "DISABLED" -#define _ch0_rx_8b10b "ENABLED" -#define _ch0_rxwa "ENABLED" -#define _ch0_ilsm "ENABLED" -#define _ch0_scomma "K28P157" -#define _ch0_comma_a "1100000101" -#define _ch0_comma_b "0011111010" -#define _ch0_comma_m "1111111100" -#define _ch0_ctc "DISABLED" -#define _ch0_cc_match_mode "1" -#define _ch0_byten "0000000000" -#define _ch0_byten1 "0000000000" -#define _ch0_byten2 "0100011100" -#define _ch0_byten3 "0100011100" -#define _ch0_cc_min_ipg "3" -#define _ch0_lbtype "DISABLED" -#define _ch0_teidle "DISABLED" -#define _ch0_rx_lol_port "INTERNAL" - -#define _ch1_pll_rxsrc "REFCLK_EXT" -#define _ch1_mode "DISABLED" -#define _ch1_protocol "G8B10B" -#define _ch1_ldr "DISABLED" -#define _ch1_tx_data_rate "FULL" -#define _ch1_tx_data_width "8" -#define _ch1_tx_fifo "ENABLED" -#define _ch1_tx_ficlk_rate 125.0 -#define _ch1_rx_datarange "MEDHIGH" -#define _ch1_rx_data_rate "FULL" -#define _ch1_rxrefclk_rate "250.0" -#define _ch1_rx_data_width "8" -#define _ch1_rx_fifo "ENABLED" -#define _ch1_rx_ficlk_rate 250.0 -#define _ch1_tdrv "0" -#define _ch1_tx_pre "DISABLED" -#define _ch1_rterm_tx "50" -#define _ch1_rx_eq "DISABLED" -#define _ch1_rterm_rx "50" -#define _ch1_rx_dcc "AC" -#define _los_threshold_lo1 "2" -#define _ch1_tx_sb "DISABLED" -#define _ch1_tx_8b10b "ENABLED" -#define _ch1_rx_sb "DISABLED" -#define _ch1_ird "DISABLED" -#define _ch1_rx_8b10b "ENABLED" -#define _ch1_rxwa "ENABLED" -#define _ch1_ilsm "ENABLED" -#define _ch1_scomma "K28P157" -#define _ch1_comma_a "1100000101" -#define _ch1_comma_b "0011111010" -#define _ch1_comma_m "1111111100" -#define _ch1_ctc "DISABLED" -#define _ch1_cc_match_mode "1" -#define _ch1_byten "0000000000" -#define _ch1_byten1 "0000000000" -#define _ch1_byten2 "0100011100" -#define _ch1_byten3 "0100011100" -#define _ch1_cc_min_ipg "3" -#define _ch1_lbtype "DISABLED" -#define _ch1_teidle "DISABLED" -#define _ch1_rx_lol_port "INTERNAL" - -#define _ch2_pll_rxsrc "REFCLK_EXT" -#define _ch2_mode "DISABLED" -#define _ch2_protocol "G8B10B" -#define _ch2_ldr "DISABLED" -#define _ch2_tx_data_rate "FULL" -#define _ch2_tx_data_width "8" -#define _ch2_tx_fifo "ENABLED" -#define _ch2_tx_ficlk_rate 125.0 -#define _ch2_rx_datarange "MEDHIGH" -#define _ch2_rx_data_rate "FULL" -#define _ch2_rxrefclk_rate "250.0" -#define _ch2_rx_data_width "8" -#define _ch2_rx_fifo "ENABLED" -#define _ch2_rx_ficlk_rate 250.0 -#define _ch2_tdrv "0" -#define _ch2_tx_pre "DISABLED" -#define _ch2_rterm_tx "50" -#define _ch2_rx_eq "DISABLED" -#define _ch2_rterm_rx "50" -#define _ch2_rx_dcc "AC" -#define _los_threshold_lo2 "2" -#define _ch2_tx_sb "DISABLED" -#define _ch2_tx_8b10b "ENABLED" -#define _ch2_rx_sb "DISABLED" -#define _ch2_ird "DISABLED" -#define _ch2_rx_8b10b "ENABLED" -#define _ch2_rxwa "ENABLED" -#define _ch2_ilsm "ENABLED" -#define _ch2_scomma "K28P157" -#define _ch2_comma_a "1100000101" -#define _ch2_comma_b "0011111010" -#define _ch2_comma_m "1111111100" -#define _ch2_ctc "DISABLED" -#define _ch2_cc_match_mode "1" -#define _ch2_byten "0000000000" -#define _ch2_byten1 "0000000000" -#define _ch2_byten2 "0100011100" -#define _ch2_byten3 "0100011100" -#define _ch2_cc_min_ipg "3" -#define _ch2_lbtype "DISABLED" -#define _ch2_teidle "DISABLED" -#define _ch2_rx_lol_port "INTERNAL" - -#define _ch3_pll_rxsrc "REFCLK_CORE" -#define _ch3_mode "RXTX" -#define _ch3_protocol "GIGE" -#define _ch3_ldr "DISABLED" -#define _ch3_tx_data_rate "FULL" -#define _ch3_tx_data_width "8" -#define _ch3_tx_fifo "ENABLED" -#define _ch3_tx_ficlk_rate 125.0 -#define _ch3_rx_datarange "MED" -#define _ch3_rx_data_rate "FULL" -#define _ch3_rxrefclk_rate "125.0" -#define _ch3_rx_data_width "8" -#define _ch3_rx_fifo "ENABLED" -#define _ch3_rx_ficlk_rate 125.0 -#define _ch3_tdrv "0" -#define _ch3_tx_pre "DISABLED" -#define _ch3_rterm_tx "50" -#define _ch3_rx_eq "DISABLED" -#define _ch3_rterm_rx "50" -#define _ch3_rx_dcc "AC" -#define _los_threshold_lo3 "2" -#define _ch3_tx_sb "DISABLED" -#define _ch3_tx_8b10b "ENABLED" -#define _ch3_rx_sb "DISABLED" -#define _ch3_ird "DISABLED" -#define _ch3_rx_8b10b "ENABLED" -#define _ch3_rxwa "ENABLED" -#define _ch3_ilsm "ENABLED" -#define _ch3_scomma "K28P5" -#define _ch3_comma_a "1100000101" -#define _ch3_comma_b "0011111010" -#define _ch3_comma_m "1111111111" -#define _ch3_ctc "DISABLED" -#define _ch3_cc_match_mode "2" -#define _ch3_byten "0110111100" -#define _ch3_byten1 "0001010000" -#define _ch3_byten2 "0110111100" -#define _ch3_byten3 "0001010000" -#define _ch3_cc_min_ipg "3" -#define _ch3_lbtype "DISABLED" -#define _ch3_teidle "DISABLED" -#define _ch3_rx_lol_port "INTERNAL" - -#define _datarange "MED" -#define _pll_txsrc "REFCLK_CORE" -#define _refclk_mult "10X" -#define _refclk_rate 125.0 -#define _pll_term "50" -#define _pll_dcc "AC" -#define _pll_lol_set "0" -#define _cchmark "9" -#define _cclmark "7" -#define _rst_gen "DISABLED" -#define _sci_ports "DISABLED" -#define _sci_int_port "DISABLED" -#define _refck2core "DISABLED" -#define _circuit_name serdes_ch4 -#define _lang vhdl - -#include -#include diff --git a/gbe_ecp2m/ipcores/serdes_ch4.readme b/gbe_ecp2m/ipcores/serdes_ch4.readme deleted file mode 100644 index 98e2a4b..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.readme +++ /dev/null @@ -1,141 +0,0 @@ - - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: Lattice Semiconductor Corporation - MODULE: serdes_ch4 - DESIGN: serdes_ch4 - FILENAME: serdes_ch4.readme - PROJECT: Unknown - VERSION: 2.0 - This file is auto generated by the ispLEVER - - -NOTE: This readme file has been provided to instantiate the interface -netlist. Since this template contains synthesis attributes for precision that -are crucial to the design flow, we recommend that you use this -template in your FPGA design. -entity chip is -port ( - --- Add your FPGA design top level I/Os here - - --- ASIC side pins for PCSD. These pins must exist for the --- PCS core. - refclkp : in std_logic; - refclkn : in std_logic; - hdinp_ch0 : in std_logic; - hdinn_ch0 : in std_logic; - hdinp_ch1 : in std_logic; - hdinn_ch1 : in std_logic; - hdinp_ch2 : in std_logic; - hdinn_ch2 : in std_logic; - hdinp_ch3 : in std_logic; - hdinn_ch3 : in std_logic; - - hdoutp_ch0 : out std_logic; - hdoutn_ch0 : out std_logic; - hdoutp_ch1 : out std_logic; - hdoutn_ch1 : out std_logic; - hdoutp_ch2 : out std_logic; - hdoutn_ch2 : out std_logic; - hdoutp_ch3 : out std_logic; - hdoutn_ch3 : out std_logic; - - -); -end chip; - -architecture chip_arch of chip is - --- This defines all the high-speed ports. You may have to remove --- some of them depending on your design. -attribute nopad : string; -attribute nopad of - refclkp, refclkn, - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1, - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3, - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1, - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true"; - - COMPONENT serdes_ch4 - PORT( - hdinp_ch3 : IN std_logic; - hdinn_ch3 : IN std_logic; - rxiclk_ch3 : IN std_logic; - txiclk_ch3 : IN std_logic; - fpga_rxrefclk_ch3 : IN std_logic; - txdata_ch3 : IN std_logic_vector(7 downto 0); - tx_k_ch3 : IN std_logic; - xmit_ch3 : IN std_logic; - tx_disp_correct_ch3 : IN std_logic; - rx_serdes_rst_ch3_c : IN std_logic; - sb_felb_ch3_c : IN std_logic; - sb_felb_rst_ch3_c : IN std_logic; - tx_pcs_rst_ch3_c : IN std_logic; - tx_pwrup_ch3_c : IN std_logic; - rx_pcs_rst_ch3_c : IN std_logic; - rx_pwrup_ch3_c : IN std_logic; - fpga_txrefclk : IN std_logic; - tx_serdes_rst_c : IN std_logic; - rst_qd_c : IN std_logic; - serdes_rst_qd_c : IN std_logic; - hdoutp_ch3 : OUT std_logic; - hdoutn_ch3 : OUT std_logic; - rx_full_clk_ch3 : OUT std_logic; - rx_half_clk_ch3 : OUT std_logic; - tx_full_clk_ch3 : OUT std_logic; - tx_half_clk_ch3 : OUT std_logic; - rxdata_ch3 : OUT std_logic_vector(7 downto 0); - rx_k_ch3 : OUT std_logic; - rx_disp_err_ch3 : OUT std_logic; - rx_cv_err_ch3 : OUT std_logic; - rx_los_low_ch3_s : OUT std_logic; - lsm_status_ch3_s : OUT std_logic; - rx_cdr_lol_ch3_s : OUT std_logic; - tx_pll_lol_qd_s : OUT std_logic - ); - END COMPONENT; - - - - uut: serdes_ch4 PORT MAP( - hdinp_ch3 => hdinp_ch3, - hdinn_ch3 => hdinn_ch3, - hdoutp_ch3 => hdoutp_ch3, - hdoutn_ch3 => hdoutn_ch3, - rxiclk_ch3 => rxiclk_ch3, - txiclk_ch3 => txiclk_ch3, - rx_full_clk_ch3 => rx_full_clk_ch3, - rx_half_clk_ch3 => rx_half_clk_ch3, - tx_full_clk_ch3 => tx_full_clk_ch3, - tx_half_clk_ch3 => tx_half_clk_ch3, - fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3, - txdata_ch3 => txdata_ch3, - tx_k_ch3 => tx_k_ch3, - xmit_ch3 => xmit_ch3, - tx_disp_correct_ch3 => tx_disp_correct_ch3, - rxdata_ch3 => rxdata_ch3, - rx_k_ch3 => rx_k_ch3, - rx_disp_err_ch3 => rx_disp_err_ch3, - rx_cv_err_ch3 => rx_cv_err_ch3, - rx_serdes_rst_ch3_c => rx_serdes_rst_ch3_c, - sb_felb_ch3_c => sb_felb_ch3_c, - sb_felb_rst_ch3_c => sb_felb_rst_ch3_c, - tx_pcs_rst_ch3_c => tx_pcs_rst_ch3_c, - tx_pwrup_ch3_c => tx_pwrup_ch3_c, - rx_pcs_rst_ch3_c => rx_pcs_rst_ch3_c, - rx_pwrup_ch3_c => rx_pwrup_ch3_c, - rx_los_low_ch3_s => rx_los_low_ch3_s, - lsm_status_ch3_s => lsm_status_ch3_s, - rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s, - fpga_txrefclk => fpga_txrefclk, - tx_serdes_rst_c => tx_serdes_rst_c, - tx_pll_lol_qd_s => tx_pll_lol_qd_s, - rst_qd_c => rst_qd_c, - serdes_rst_qd_c => serdes_rst_qd_c - ); - - - - diff --git a/gbe_ecp2m/ipcores/serdes_ch4.sort b/gbe_ecp2m/ipcores/serdes_ch4.sort deleted file mode 100644 index 9e836ba..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.sort +++ /dev/null @@ -1 +0,0 @@ -serdes_ch4.vhd diff --git a/gbe_ecp2m/ipcores/serdes_ch4.sym b/gbe_ecp2m/ipcores/serdes_ch4.sym deleted file mode 100644 index 9e4bc2056f3cc01409a4b03f74743dc4b3268e15..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1580 zcmZvbKZq1r5XP%sw=z4pvn{)bfgBSIavTN?io&vi$U2A!*TKqxciJ;Mf1JhEZM%E5 zBN@a%#GsMm0=Ynr4Gfl}5d(t@4lxipq>&3m3>GmE5g9}b#K7;>o6&LIfyex&zHjQi zs(Nqj7sAKF+OyTxh#%{!N~wJnKYR8;1akU`YV&~Y-SBkNkJ6~qZ3SoiR&Ou;hOnoO z8hujqWT;c3HR>8|qSszJcTWCu9dVZ~jm1NWuOgnQKTNz7#fg8u?YD>?AnvHYP27o6 zKWxRmmT>^BztH*AW20BJelc2+lv=f!DC9RrorW5BqIPFI!4KL&6_y&yQMxoLj%J}` z{G(AO<3+#Q2^NRjo`9C~ywSFgw6DiXwXWJmpBmd#in$Foz zC!n^QNmG~m>w#JKB-Np2wBM-ZWUNo8pt$TArIemsG9^%7k(E1%HCCV$r1bUGO_mq-|ev&B2p%)vDF^Su_QYOlPBOQD>q$TqlgH zyAoi#;ma7E>ndCW3gGG+SFag#zjNJ&E8`n*-Lj~J9f#8%WhrzPz61TCCDjGXF{-<` zvAPfNHTW5PZ)LY{CpgNs%SKO`>{@-sCVdMwJ^3NHT;2`WtZ{96ax~5I)G@dk#ucIo zy6?E>dOT*%L^I{#RcrP35%ujp7wRzdK09=nf5$UjR~}~QsawLX%yUiH0XyoRFzz=x z@j$o$7hDME;GCZeXW)!q*%Qdw05|x(#9c7f7QL4Pc6gic05uF~r*Hu-s3x3)b8>|< za7J@r!n>|w9TCpJnOYDI!J%phdtgrm!Y diff --git a/gbe_ecp2m/ipcores/serdes_ch4.tft b/gbe_ecp2m/ipcores/serdes_ch4.tft deleted file mode 100644 index b9db080..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.tft +++ /dev/null @@ -1,100 +0,0 @@ -@set suppresnewline=on@ - -@comment --------------------------------------------------------------------- @ -@comment Template-drive TFI generator @ -@comment Template for TFI generation. @ -@comment --------------------------------------------------------------------- @ - -@set suppresnewline=off@ - TOOL: orcapp - DATE: 19-MAR-2008 13:11:52 - TITLE: %title% - MODULE: %module% - DESIGN: %module% - FILENAME: %filename% - PROJECT: %project% - VERSION: %ver% - This file is auto generated by the ispLEVER -@set suppresnewline=on@ - -@cr@ -@cr@ - -@set sigdelim=@ - -NOTE: This readme file has been provided to instantiate the interface@cr@ -netlist. Since this template contains synthesis attributes for precision that@cr@ -are crucial to the design flow, we recommend that you use this@cr@ -template in your FPGA design.@cr@ -entity chip is@cr@ -port (@cr@ -@cr@ --- Add your FPGA design top level I/Os here@cr@ -@cr@ -@cr@ --- ASIC side pins for PCSD. These pins must exist for the@cr@ --- PCS core.@cr@ - refclkp : in std_logic;@cr@ - refclkn : in std_logic;@cr@ - hdinp_ch0 : in std_logic;@cr@ - hdinn_ch0 : in std_logic;@cr@ - hdinp_ch1 : in std_logic;@cr@ - hdinn_ch1 : in std_logic;@cr@ - hdinp_ch2 : in std_logic;@cr@ - hdinn_ch2 : in std_logic;@cr@ - hdinp_ch3 : in std_logic;@cr@ - hdinn_ch3 : in std_logic;@cr@ -@cr@ - hdoutp_ch0 : out std_logic;@cr@ - hdoutn_ch0 : out std_logic;@cr@ - hdoutp_ch1 : out std_logic;@cr@ - hdoutn_ch1 : out std_logic;@cr@ - hdoutp_ch2 : out std_logic;@cr@ - hdoutn_ch2 : out std_logic;@cr@ - hdoutp_ch3 : out std_logic;@cr@ - hdoutn_ch3 : out std_logic;@cr@ -@cr@ -@cr@ -);@cr@ -end chip;@cr@ -@cr@ -architecture chip_arch of chip is@cr@ -@cr@ --- This defines all the high-speed ports. You may have to remove@cr@ --- some of them depending on your design.@cr@ -attribute nopad : string;@cr@ -attribute nopad of@cr@ - refclkp, refclkn,@cr@ - hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@ - hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@ - hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@ - hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@ - -@cr@ -@tab@COMPONENT %module% -@set sigdelim=@ -@cr@@tab@PORT( -@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ -@ifhas oport=*@ @comment if the design has any output ports... @ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ - @set sigdelim=;@ - @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ -@endif@ -@ifnhas oport=*@ @comment we need an "else in this language! @ - @set sigdelim=;@ - @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ -@endif@ -@cr@@tab@@tab@);@cr@ -@tab@END COMPONENT;@cr@@cr@ -@comment Now do a signal declaration for each port @ - -@cr@@cr@ -@comment do the component instantiation @ -@set sigdelim=,@ -@tab@uut: %module% PORT MAP( -@iterate@%port% -@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ -@cr@@tab@);@cr@@cr@ -@set suppresnewline=off@ - - diff --git a/gbe_ecp2m/ipcores/serdes_ch4.txt b/gbe_ecp2m/ipcores/serdes_ch4.txt deleted file mode 100644 index 6b3b65f..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.txt +++ /dev/null @@ -1,59 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH3_PROTOCOL "GIGE" -CH0_MODE "DISABLED" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "RXTX" -CH3_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MED" -CH3_RX_DATARATE_RANGE "MED" -REFCK_MULT "10X" -#REFCLK_RATE 125.0 -CH3_RX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" -CH3_TX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" -CH3_TX_FIFO "ENABLED" -CH3_RX_FIFO "ENABLED" -CH3_TDRV "0" -#CH3_TX_FICLK_RATE 125.0 -#CH3_RXREFCLK_RATE "125.0" -#CH3_RX_FICLK_RATE 125.0 -CH3_TX_PRE "DISABLED" -CH3_RTERM_TX "50" -CH3_RX_EQ "DISABLED" -CH3_RTERM_RX "50" -CH3_RX_DCC "AC" -CH3_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH3_TX_SB "DISABLED" -CH3_RX_SB "DISABLED" -CH3_TX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" -CH3_COMMA_A "1100000101" -CH3_COMMA_B "0011111010" -CH3_COMMA_M "1111111111" -CH3_RXWA "ENABLED" -CH3_ILSM "ENABLED" -CH3_CTC "DISABLED" -CH3_CC_MATCH3 "0110111100" -CH3_CC_MATCH4 "0001010000" -CH3_CC_MATCH_MODE "2" -CH3_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH3_SSLB "DISABLED" -CH3_SPLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "DISABLED" - - diff --git a/gbe_ecp2m/ipcores/serdes_ch4.vhd b/gbe_ecp2m/ipcores/serdes_ch4.vhd deleted file mode 100644 index 9f3f819..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4.vhd +++ /dev/null @@ -1,2689 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_ch4.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_EXT"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_CORE"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - - - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_ch4 is - GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt"); - port ( ------------------- --- CH0 -- --- CH1 -- --- CH2 -- --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - rxiclk_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (7 downto 0); - tx_k_ch3 : in std_logic; - xmit_ch3 : in std_logic; - tx_disp_correct_ch3 : in std_logic; - rxdata_ch3 : out std_logic_vector (7 downto 0); - rx_k_ch3 : out std_logic; - rx_disp_err_ch3 : out std_logic; - rx_cv_err_ch3 : out std_logic; - rx_serdes_rst_ch3_c : in std_logic; - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pcs_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pcs_rst_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_ch4; - - -architecture serdes_ch4_arch of serdes_ch4 is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - - - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH3_CDR_SRC: string; - attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch3_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - - - - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - rx_los_low_ch3_s <= rx_los_low_ch3_sig; - rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch3 <= tx_full_clk_ch3_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH3_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => open, - HDOUTN0 => open, - HDINP0 => fpsc_vlo, - HDINN0 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => fpsc_vlo, - FF_TXI_CLK_0 => fpsc_vlo, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => open, - FF_RX_H_CLK_0 => open, - FF_TX_F_CLK_0 => open, - FF_TX_H_CLK_0 => open, - FFC_CK_CORE_RX_0 => fpsc_vlo, - FF_TX_D_0_0 => fpsc_vlo, - FF_TX_D_0_1 => fpsc_vlo, - FF_TX_D_0_2 => fpsc_vlo, - FF_TX_D_0_3 => fpsc_vlo, - FF_TX_D_0_4 => fpsc_vlo, - FF_TX_D_0_5 => fpsc_vlo, - FF_TX_D_0_6 => fpsc_vlo, - FF_TX_D_0_7 => fpsc_vlo, - FF_TX_D_0_8 => fpsc_vlo, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => fpsc_vlo, - FF_TX_D_0_11 => fpsc_vlo, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => open, - FF_RX_D_0_1 => open, - FF_RX_D_0_2 => open, - FF_RX_D_0_3 => open, - FF_RX_D_0_4 => open, - FF_RX_D_0_5 => open, - FF_RX_D_0_6 => open, - FF_RX_D_0_7 => open, - FF_RX_D_0_8 => open, - FF_RX_D_0_9 => open, - FF_RX_D_0_10 => open, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => fpsc_vlo, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => fpsc_vlo, - FFC_TXPWDNB_0 => fpsc_vlo, - FFC_LANE_RX_RST_0 => fpsc_vlo, - FFC_RXPWDNB_0 => fpsc_vlo, - FFS_RLOS_LO_0 => open, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => fpsc_vlo, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => fpsc_vlo, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => hdoutp_ch3, - HDOUTN3 => hdoutn_ch3, - HDINP3 => hdinp_ch3, - HDINN3 => hdinn_ch3, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => rxiclk_ch3, - FF_TXI_CLK_3 => txiclk_ch3, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => rx_full_clk_ch3, - FF_RX_H_CLK_3 => rx_half_clk_ch3, - FF_TX_F_CLK_3 => tx_full_clk_ch3_sig, - FF_TX_H_CLK_3 => tx_half_clk_ch3, - FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3, - FF_TX_D_3_0 => txdata_ch3(0), - FF_TX_D_3_1 => txdata_ch3(1), - FF_TX_D_3_2 => txdata_ch3(2), - FF_TX_D_3_3 => txdata_ch3(3), - FF_TX_D_3_4 => txdata_ch3(4), - FF_TX_D_3_5 => txdata_ch3(5), - FF_TX_D_3_6 => txdata_ch3(6), - FF_TX_D_3_7 => txdata_ch3(7), - FF_TX_D_3_8 => tx_k_ch3, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => xmit_ch3, - FF_TX_D_3_11 => tx_disp_correct_ch3, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => rxdata_ch3(0), - FF_RX_D_3_1 => rxdata_ch3(1), - FF_RX_D_3_2 => rxdata_ch3(2), - FF_RX_D_3_3 => rxdata_ch3(3), - FF_RX_D_3_4 => rxdata_ch3(4), - FF_RX_D_3_5 => rxdata_ch3(5), - FF_RX_D_3_6 => rxdata_ch3(6), - FF_RX_D_3_7 => rxdata_ch3(7), - FF_RX_D_3_8 => rx_k_ch3, - FF_RX_D_3_9 => rx_disp_err_ch3, - FF_RX_D_3_10 => rx_cv_err_ch3, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => rx_serdes_rst_ch3_c, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c, - FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c, - FFC_TXPWDNB_3 => tx_pwrup_ch3_c, - FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c, - FFC_RXPWDNB_3 => rx_pwrup_ch3_c, - FFS_RLOS_LO_3 => rx_los_low_ch3_sig, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => rx_cdr_lol_ch3_sig, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA0 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIRDATA7 => open, - SCIRDATA6 => open, - SCIRDATA5 => open, - SCIRDATA4 => open, - SCIRDATA3 => open, - SCIRDATA2 => open, - SCIRDATA1 => open, - SCIRDATA0 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - - - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_ch4_arch ; diff --git a/gbe_ecp2m/ipcores/serdes_ch4_generate.log b/gbe_ecp2m/ipcores/serdes_ch4_generate.log deleted file mode 100644 index 26130c0..0000000 --- a/gbe_ecp2m/ipcores/serdes_ch4_generate.log +++ /dev/null @@ -1,29 +0,0 @@ -Starting process: Module - -Starting process: - - Module Name: serdes_ch4 - Core Name: PCS - LPC file : serdes_ch4.lpc - Parameter File : serdes_ch4.pp - Command line: /opt/lattice/diamond/1.4/ispfpga/bin/lin/orcapp -Fmaco serdes_ch4.pp - Return Value: - - - - Module PCS has been generated in /home/greg/projects/trb3/trb3_gbe/. successfully! - -/opt/lattice/diamond/1.4/bin/lin/hdl2jhd -tfi -mod serdes_ch4 -ext readme -out serdes_ch4 -tpl serdes_ch4.tft serdes_ch4.vhd - -Done successfully! -File: serdes_ch4.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.lpc b/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.lpc deleted file mode 100644 index c331cfe..0000000 --- a/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.lpc +++ /dev/null @@ -1,140 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-6F900C -SpeedGrade=-6 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=7.0 -ModuleName=serdes_gbe_0_intclock_8b -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=04/28/2010 -Time=20:09:02 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Protocol=Quad -mode=Gigabit Ethernet -Channel0=SINGLE -Channel1=DISABLE -Channel2=DISABLE -Channel3=DISABLE -Rate0=None -Rate1=None -Rate2=None -Rate3=None -TxRefClk=CORE_TXREFCLK -RxRefClk=CORE_RXREFCLK -ClkRate=1.25 -ClkMult=10X -CalClkRate=125.0 -DataWidth=8 -FPGAClkRate=125.0 -TxRefClkCM=REFCLK -RxRefClk0CM=REFCLK -RxRefClk1CM=REFCLK -RxRefClk2CM=REFCLK -RxRefClk3CM=REFCLK -ClkRateH=0.625 -ClkMultH=10XH -CalClkRateH=125.0 -DataWidthH=8 -FPGAClkRateH=62.5 -VCh0=0 -VCh1=0 -VCh2=0 -VCh3=0 -PreCh0=DISABLE -PreCh1=DISABLE -PreCh2=DISABLE -PreCh3=DISABLE -TxCh0=50 -TxCh1=50 -TxCh2=50 -TxCh3=50 -EqCh0=DISABLE -EqCh1=DISABLE -EqCh2=DISABLE -EqCh3=DISABLE -RxTermCh0=50 -RxTermCh1=50 -RxTermCh2=50 -RxTermCh3=50 -RxCoupCh0=AC -RxCoupCh1=AC -RxCoupCh2=AC -RxCoupCh3=AC -Loss=0 -CDRLoss=0 -TxTerm=50 -TxCoup=AC -TxPllLoss=0 -TxInvCh0=NORMAL -TxInvCh1=NORMAL -TxInvCh2=NORMAL -TxInvCh3=NORMAL -RxInvCh0=NORMAL -RxInvCh1=NORMAL -RxInvCh2=NORMAL -RxInvCh3=NORMAL -RxModeCh0=NORMAL -RxModeCh1=NORMAL -RxModeCh2=NORMAL -RxModeCh3=NORMAL -Plus=1100000101 -Minus=0011111010 -Mask=1111111111 -Align=AUTO -CTCCh0=NORMAL -CTCCh1=NORMAL -CTCCh2=NORMAL -CTCCh3=NORMAL -CC_MATCH1=0000000000 -CC_MATCH2=0000000000 -CC_MATCH3=0110111100 -CC_MATCH4=0001010000 -MinIPG=3 -High=9 -Low=7 -CC_MATCH_MODE=MATCH_3_4 -RxDataCh0=FALSE -RxDataCh1=FALSE -RxDataCh2=FALSE -RxDataCh3=FALSE -AlignerCh0=FALSE -AlignerCh1=FALSE -AlignerCh2=FALSE -AlignerCh3=FALSE -DetectCh0=FALSE -DetectCh1=FALSE -DetectCh2=FALSE -DetectCh3=FALSE -ELSMCh0=FALSE -ELSMCh1=FALSE -ELSMCh2=FALSE -ELSMCh3=FALSE -_teidleCh0=FALSE -_teidleCh1=FALSE -_teidleCh2=FALSE -_teidleCh3=FALSE -Ports0=FALSE -rdoPorts0=Serial Loopback -Ports1=FALSE -Ports2=TRUE -Ports3=FALSE -Ports3_1=FALSE -Ports4=FALSE diff --git a/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.txt b/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.txt deleted file mode 100644 index a2e883f..0000000 --- a/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.txt +++ /dev/null @@ -1,49 +0,0 @@ - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSC quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSC quad to the final design requirements. - -DEVICE_NAME "LFE2M100E" -PROTOCOL "GIGE" -CH0_MODE "SINGLE" -CH1_MODE "DISABLE" -CH2_MODE "DISABLE" -CH3_MODE "DISABLE" -PLL_SRC "CORE_TXREFCLK" -DATARANGE "MED" -CH0_CDR_SRC "CORE_RXREFCLK" -CH0_DATA_WIDTH "8" -CH0_REFCK_MULT "10X" -#REFCLK_RATE 125.0 -#FPGAINTCLK_RATE 125.0 -CH0_TDRV_AMP "0" -CH0_TX_PRE "DISABLE" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLE" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -LOS_THRESHOLD "0" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "NORMAL" -CH0_RX_SB "NORMAL" -CH0_8B10B "NORMAL" -COMMA_A "1100000101" -COMMA_B "0011111010" -COMMA_M "1111111111" -CH0_COMMA_ALIGN "AUTO" -CH0_CTC_BYP "BYPASS" -CC_MATCH1 "0000000000" -CC_MATCH2 "0000000000" -CC_MATCH3 "0110111100" -CC_MATCH4 "0001010000" -CC_MATCH_MODE "MATCH_3_4" -CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -OS_REFCK2CORE "1" -OS_PLLQCLKPORTS "0" -OS_INT_ALL "0" - diff --git a/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.vhd b/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.vhd deleted file mode 100644 index f3224c6..0000000 --- a/gbe_ecp2m/ipcores/serdes_intclk/serdes_gbe_0_intclock_8b.vhd +++ /dev/null @@ -1,2183 +0,0 @@ - - ---synopsys translate_off - -library pcsc_work; -use pcsc_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSC is -GENERIC( - CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); - -end PCSC; - -architecture PCSC_arch of PCSC is - -component PCSC_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - -begin - -PCSC_sim_inst : PCSC_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, - FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, - FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, - FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, - FF_TX_F_CLK => FF_TX_F_CLK, - FF_TX_H_CLK => FF_TX_H_CLK, - FF_TX_Q_CLK => FF_TX_Q_CLK, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - OOB_OUT_0 => OOB_OUT_0, - OOB_OUT_1 => OOB_OUT_1, - OOB_OUT_2 => OOB_OUT_2, - OOB_OUT_3 => OOB_OUT_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7 - ); - -end PCSC_arch; - ---synopsys translate_on - ---synopsys translate_off -library ECP2; -use ECP2.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_intclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); - port ( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - refck2core : out std_logic; - ffs_plol : out std_logic); - -end serdes_gbe_0_intclock_8b; - -architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; -component PCSC ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal fpsc_vlo : std_logic := '0'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSC_INST : PCSC ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - FFC_CK_CORE_TX => core_txrefclk, - FFC_CK_CORE_RX => core_rxrefclk, - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - HDINP0 => hdinp0, - HDINN0 => hdinn0, - HDOUTP0 => hdoutp0, - HDOUTN0 => hdoutn0, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => ff_rxiclk_ch0, - FF_TXI_CLK_0 => ff_txiclk_ch0, - FF_EBRD_CLK_0 => ff_ebrd_clk_0, - FF_RX_F_CLK_0 => ff_rxfullclk_ch0, - FF_RX_H_CLK_0 => open, - FF_RX_Q_CLK_0 => open, - FF_TX_D_0_0 => ff_txdata_ch0(0), - FF_TX_D_0_1 => ff_txdata_ch0(1), - FF_TX_D_0_2 => ff_txdata_ch0(2), - FF_TX_D_0_3 => ff_txdata_ch0(3), - FF_TX_D_0_4 => ff_txdata_ch0(4), - FF_TX_D_0_5 => ff_txdata_ch0(5), - FF_TX_D_0_6 => ff_txdata_ch0(6), - FF_TX_D_0_7 => ff_txdata_ch0(7), - FF_TX_D_0_8 => ff_tx_k_cntrl_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => ff_xmit_ch0, - FF_TX_D_0_11 => ff_correct_disp_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => ff_rxdata_ch0(0), - FF_RX_D_0_1 => ff_rxdata_ch0(1), - FF_RX_D_0_2 => ff_rxdata_ch0(2), - FF_RX_D_0_3 => ff_rxdata_ch0(3), - FF_RX_D_0_4 => ff_rxdata_ch0(4), - FF_RX_D_0_5 => ff_rxdata_ch0(5), - FF_RX_D_0_6 => ff_rxdata_ch0(6), - FF_RX_D_0_7 => ff_rxdata_ch0(7), - FF_RX_D_0_8 => ff_rx_k_cntrl_ch0, - FF_RX_D_0_9 => ff_disp_err_ch0, - FF_RX_D_0_10 => ff_cv_ch0, - FF_RX_D_0_11 => ff_rx_even_ch0, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - FFC_RRST_0 => ffc_rrst_ch0, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFS_PCIE_DONE_0 => open, - FFS_PCIE_CON_0 => open, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, - FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, - FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, - FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, - FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, - FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, - FFS_CC_UNDERRUN_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - FFS_RLOL_0 => ffs_rlol_ch0, - OOB_OUT_0 => oob_out_ch0, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - HDOUTP1 => open, - HDOUTN1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_RX_Q_CLK_1 => open, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_PCIE_CON_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - OOB_OUT_1 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - HDOUTP2 => open, - HDOUTN2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_RX_Q_CLK_2 => open, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_PCIE_CON_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - OOB_OUT_2 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - HDOUTP3 => open, - HDOUTN3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_RX_Q_CLK_3 => open, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_PCIE_CON_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - OOB_OUT_3 => open, - SCIWDATA0 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA7 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIRDATA0 => open, - SCIRDATA1 => open, - SCIRDATA2 => open, - SCIRDATA3 => open, - SCIRDATA4 => open, - SCIRDATA5 => open, - SCIRDATA6 => open, - SCIRDATA7 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_MACRO_RST => ffc_macro_rst, - FFC_QUAD_RST => ffc_quad_rst, - FFC_TRST => ffc_trst, - FF_TX_F_CLK => ff_txfullclk, - FF_TX_H_CLK => ff_txhalfclk, - FF_TX_Q_CLK => open, - REFCK2CORE => refck2core, - CIN0 => cin(0), - CIN1 => cin(1), - CIN2 => cin(2), - CIN3 => cin(3), - CIN4 => cin(4), - CIN5 => cin(5), - CIN6 => cin(6), - CIN7 => cin(7), - CIN8 => cin(8), - CIN9 => cin(9), - CIN10 => cin(10), - CIN11 => cin(11), - COUT0 => cout(0), - COUT1 => cout(1), - COUT2 => cout(2), - COUT3 => cout(3), - COUT4 => cout(4), - COUT5 => cout(5), - COUT6 => cout(6), - COUT7 => cout(7), - COUT8 => cout(8), - COUT9 => cout(9), - COUT10 => cout(10), - COUT11 => cout(11), - COUT12 => cout(12), - COUT13 => cout(13), - COUT14 => cout(14), - COUT15 => cout(15), - COUT16 => cout(16), - COUT17 => cout(17), - COUT18 => cout(18), - COUT19 => cout(19), - FFS_PLOL => ffs_plol); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end serdes_gbe_0_intclock_8b_arch ; diff --git a/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.lpc b/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.lpc deleted file mode 100644 index 2a5b9c7..0000000 --- a/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.lpc +++ /dev/null @@ -1,145 +0,0 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M50E -PartName=LFE2M50E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_gbe_0_intclock_8b -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=07/31/2010 -Time=18:08:44 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Protocol=Quad -mode=Gigabit Ethernet -Channel0=SINGLE -Channel1=DISABLE -Channel2=DISABLE -Channel3=DISABLE -Rate0=None -Rate1=None -Rate2=None -Rate3=None -TxRefClk=CORE_TXREFCLK -RxRefClk=CORE_RXREFCLK -ClkRate=1.25 -ClkMult=10X -CalClkRate=125.0 -DataWidth=8 -FPGAClkRate=125.0 -TxRefClkCM=REFCLK -RxRefClk0CM=REFCLK -RxRefClk1CM=REFCLK -RxRefClk2CM=REFCLK -RxRefClk3CM=REFCLK -ClkRateH=0.625 -ClkMultH=10XH -CalClkRateH=125.0 -DataWidthH=8 -FPGAClkRateH=62.5 -VCh0=0 -VCh1=0 -VCh2=0 -VCh3=0 -PreCh0=DISABLE -PreCh1=DISABLE -PreCh2=DISABLE -PreCh3=DISABLE -TxCh0=50 -TxCh1=50 -TxCh2=50 -TxCh3=50 -EqCh0=DISABLE -EqCh1=DISABLE -EqCh2=DISABLE -EqCh3=DISABLE -RxTermCh0=50 -RxTermCh1=50 -RxTermCh2=50 -RxTermCh3=50 -RxCoupCh0=AC -RxCoupCh1=AC -RxCoupCh2=AC -RxCoupCh3=AC -Loss=0 -CDRLoss=0 -TxTerm=50 -TxCoup=AC -TxPllLoss=0 -TxInvCh0=NORMAL -TxInvCh1=NORMAL -TxInvCh2=NORMAL -TxInvCh3=NORMAL -RxInvCh0=NORMAL -RxInvCh1=NORMAL -RxInvCh2=NORMAL -RxInvCh3=NORMAL -RxModeCh0=NORMAL -RxModeCh1=NORMAL -RxModeCh2=NORMAL -RxModeCh3=NORMAL -Plus=1100000101 -Minus=0011111010 -Mask=1111111111 -Align=AUTO -CTCCh0=NORMAL -CTCCh1=NORMAL -CTCCh2=NORMAL -CTCCh3=NORMAL -CC_MATCH1=0000000000 -CC_MATCH2=0000000000 -CC_MATCH3=0110111100 -CC_MATCH4=0001010000 -MinIPG=3 -High=9 -Low=7 -CC_MATCH_MODE=MATCH_3_4 -RxDataCh0=FALSE -RxDataCh1=FALSE -RxDataCh2=FALSE -RxDataCh3=FALSE -AlignerCh0=FALSE -AlignerCh1=FALSE -AlignerCh2=FALSE -AlignerCh3=FALSE -DetectCh0=FALSE -DetectCh1=FALSE -DetectCh2=FALSE -DetectCh3=FALSE -ELSMCh0=FALSE -ELSMCh1=FALSE -ELSMCh2=FALSE -ELSMCh3=FALSE -_teidleCh0=FALSE -_teidleCh1=FALSE -_teidleCh2=FALSE -_teidleCh3=FALSE -Ports0=FALSE -rdoPorts0=Serial Loopback -Ports1=FALSE -Ports2=FALSE -Ports3=FALSE -Ports3_1=FALSE -Ports4=FALSE -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal diff --git a/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.txt b/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.txt deleted file mode 100644 index 4ac16e9..0000000 --- a/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.txt +++ /dev/null @@ -1,49 +0,0 @@ - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSC quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSC quad to the final design requirements. - -DEVICE_NAME "LFE2M50E" -PROTOCOL "GIGE" -CH0_MODE "SINGLE" -CH1_MODE "DISABLE" -CH2_MODE "DISABLE" -CH3_MODE "DISABLE" -PLL_SRC "CORE_TXREFCLK" -DATARANGE "MED" -CH0_CDR_SRC "CORE_RXREFCLK" -CH0_DATA_WIDTH "8" -CH0_REFCK_MULT "10X" -#REFCLK_RATE 125.0 -#FPGAINTCLK_RATE 125.0 -CH0_TDRV_AMP "0" -CH0_TX_PRE "DISABLE" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLE" -CH0_RTERM_RX "50" -CH0_RX_DCC "AC" -LOS_THRESHOLD "0" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "NORMAL" -CH0_RX_SB "NORMAL" -CH0_8B10B "NORMAL" -COMMA_A "1100000101" -COMMA_B "0011111010" -COMMA_M "1111111111" -CH0_COMMA_ALIGN "AUTO" -CH0_CTC_BYP "BYPASS" -CC_MATCH1 "0000000000" -CC_MATCH2 "0000000000" -CC_MATCH3 "0110111100" -CC_MATCH4 "0001010000" -CC_MATCH_MODE "MATCH_3_4" -CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -OS_REFCK2CORE "0" -OS_PLLQCLKPORTS "0" -OS_INT_ALL "0" - diff --git a/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.vhd b/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.vhd deleted file mode 100644 index b57bb59..0000000 --- a/gbe_ecp2m/ipcores/serdes_intclk_ecp2m50/serdes_gbe_0_intclock_8b.vhd +++ /dev/null @@ -1,2202 +0,0 @@ - - ---synopsys translate_off - -library pcsc_work; -use pcsc_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSC is -GENERIC( - CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); - -end PCSC; - -architecture PCSC_arch of PCSC is - -component PCSC_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - -begin - -PCSC_sim_inst : PCSC_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, - FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, - FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, - FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, - FF_TX_F_CLK => FF_TX_F_CLK, - FF_TX_H_CLK => FF_TX_H_CLK, - FF_TX_Q_CLK => FF_TX_Q_CLK, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - OOB_OUT_0 => OOB_OUT_0, - OOB_OUT_1 => OOB_OUT_1, - OOB_OUT_2 => OOB_OUT_2, - OOB_OUT_3 => OOB_OUT_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7 - ); - -end PCSC_arch; - ---synopsys translate_on - ---synopsys translate_off -library ECP2; -use ECP2.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_gbe_0_intclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); - port ( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - ffs_plol : out std_logic); - -end serdes_gbe_0_intclock_8b; - -architecture serdes_gbe_0_intclock_8b_arch of serdes_gbe_0_intclock_8b is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; -component PCSC ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSC_INST : label is "62.5"; - attribute FREQUENCY_PIN_FF_TX_F_CLK: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK of PCSC_INST : label is "125.0"; - attribute FREQUENCY_PIN_FF_TX_H_CLK: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK of PCSC_INST : label is "62.5"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal fpsc_vlo : std_logic := '0'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSC_INST : PCSC ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - FFC_CK_CORE_TX => core_txrefclk, - FFC_CK_CORE_RX => core_rxrefclk, - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - HDINP0 => hdinp0, - HDINN0 => hdinn0, - HDOUTP0 => hdoutp0, - HDOUTN0 => hdoutn0, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => ff_rxiclk_ch0, - FF_TXI_CLK_0 => ff_txiclk_ch0, - FF_EBRD_CLK_0 => ff_ebrd_clk_0, - FF_RX_F_CLK_0 => ff_rxfullclk_ch0, - FF_RX_H_CLK_0 => open, - FF_RX_Q_CLK_0 => open, - FF_TX_D_0_0 => ff_txdata_ch0(0), - FF_TX_D_0_1 => ff_txdata_ch0(1), - FF_TX_D_0_2 => ff_txdata_ch0(2), - FF_TX_D_0_3 => ff_txdata_ch0(3), - FF_TX_D_0_4 => ff_txdata_ch0(4), - FF_TX_D_0_5 => ff_txdata_ch0(5), - FF_TX_D_0_6 => ff_txdata_ch0(6), - FF_TX_D_0_7 => ff_txdata_ch0(7), - FF_TX_D_0_8 => ff_tx_k_cntrl_ch0, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => ff_xmit_ch0, - FF_TX_D_0_11 => ff_correct_disp_ch0, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => ff_rxdata_ch0(0), - FF_RX_D_0_1 => ff_rxdata_ch0(1), - FF_RX_D_0_2 => ff_rxdata_ch0(2), - FF_RX_D_0_3 => ff_rxdata_ch0(3), - FF_RX_D_0_4 => ff_rxdata_ch0(4), - FF_RX_D_0_5 => ff_rxdata_ch0(5), - FF_RX_D_0_6 => ff_rxdata_ch0(6), - FF_RX_D_0_7 => ff_rxdata_ch0(7), - FF_RX_D_0_8 => ff_rx_k_cntrl_ch0, - FF_RX_D_0_9 => ff_disp_err_ch0, - FF_RX_D_0_10 => ff_cv_ch0, - FF_RX_D_0_11 => ff_rx_even_ch0, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - FFC_RRST_0 => ffc_rrst_ch0, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFS_PCIE_DONE_0 => open, - FFS_PCIE_CON_0 => open, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, - FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, - FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, - FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, - FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, - FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, - FFS_CC_UNDERRUN_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - FFS_RLOL_0 => ffs_rlol_ch0, - OOB_OUT_0 => oob_out_ch0, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - HDOUTP1 => open, - HDOUTN1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_RX_Q_CLK_1 => open, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_PCIE_CON_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - OOB_OUT_1 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - HDOUTP2 => open, - HDOUTN2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_RX_Q_CLK_2 => open, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_PCIE_CON_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - OOB_OUT_2 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - HDOUTP3 => open, - HDOUTN3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_RX_Q_CLK_3 => open, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_PCIE_CON_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - OOB_OUT_3 => open, - SCIWDATA0 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA7 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIRDATA0 => open, - SCIRDATA1 => open, - SCIRDATA2 => open, - SCIRDATA3 => open, - SCIRDATA4 => open, - SCIRDATA5 => open, - SCIRDATA6 => open, - SCIRDATA7 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_MACRO_RST => ffc_macro_rst, - FFC_QUAD_RST => ffc_quad_rst, - FFC_TRST => ffc_trst, - FF_TX_F_CLK => ff_txfullclk, - FF_TX_H_CLK => ff_txhalfclk, - FF_TX_Q_CLK => open, - REFCK2CORE => open, - CIN0 => cin(0), - CIN1 => cin(1), - CIN2 => cin(2), - CIN3 => cin(3), - CIN4 => cin(4), - CIN5 => cin(5), - CIN6 => cin(6), - CIN7 => cin(7), - CIN8 => cin(8), - CIN9 => cin(9), - CIN10 => cin(10), - CIN11 => cin(11), - COUT0 => cout(0), - COUT1 => cout(1), - COUT2 => cout(2), - COUT3 => cout(3), - COUT4 => cout(4), - COUT5 => cout(5), - COUT6 => cout(6), - COUT7 => cout(7), - COUT8 => cout(8), - COUT9 => cout(9), - COUT10 => cout(10), - COUT11 => cout(11), - COUT12 => cout(12), - COUT13 => cout(13), - COUT14 => cout(14), - COUT15 => cout(15), - COUT16 => cout(16), - COUT17 => cout(17), - COUT18 => cout(18), - COUT19 => cout(19), - FFS_PLOL => ffs_plol); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end serdes_gbe_0_intclock_8b_arch ; diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/.cvsignore b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/.cvsignore deleted file mode 100644 index 67edf82..0000000 --- a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/.cvsignore +++ /dev/null @@ -1,11 +0,0 @@ -*.jhd -*.naf -*.srp -*.sym -*.log -*.v -*.htm -*.tcl -*tmpl.vhd -sgmii_pcs_eval - diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/pmi_fifo_dcLEan71301616161010.ngo b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/pmi_fifo_dcLEan71301616161010.ngo deleted file mode 100755 index d3c4b97c352a5cfa8fff25b327440ad74a0271e5..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 35501 zcmdsgd3+qjwY6+xs1Tb75JVv)3PP1ejP51Mi$$U0vOy9zXjm(?#^Fm3Y5OAqnJ zxZXJV=X!3LI)7cJ$=x>DBJ!GPTclU13a_P&dBr_%c;-R3CGl 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z9aE-v^io__jiV0%vuSHj4>cXu3jlU^^oaJ$w1h@V@Z-`FYa>ZZr7|tW1`JcW{Kk?j z<#M4qQxXntDX7}eBZM@BvZ9s-by3|4ig8pHi@qpYMb3z1z@c>IRg|2LqnF6EDmG)2 zki(0F>=>6=ujRv&#?hbaK`Y(S+o^|VNgWxk!-OT=0f3j^D3bmh$jZtzy1u@RvgJy# zZvE@7V2rjgP~O5zaSNb=)n*P}VuoIV-JGHI214sqG}ZbXYt>scNJFB{h%3n{|09Sy z3$`hnDcAh|PAra9i9>U7BXwOR#>u^Gnno30U?Q^ItooRE)xxAm3?f?x&Dd(rS>xSb z3QuZWsVh0p_Wpt1gqY499nqMmB%YlY{AJh+da6$toG;l%#Cp2(E11B_aLIWo>a6$wB IUuod~0z4IfD*ylh diff --git a/gbe_ecp2m/ipcores/statts_mem.lpc b/gbe_ecp2m/ipcores/statts_mem.lpc deleted file mode 100644 index c24e581..0000000 --- a/gbe_ecp2m/ipcores/statts_mem.lpc +++ /dev/null @@ -1,53 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=RAM_DP -CoreRevision=6.1 -ModuleName=statts_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/05/2011 -Time=22:40:38 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -RAddress=1020 -RData=8 -WAddress=255 -WData=32 -enByte=0 -ByteSize=9 -adPipeline=0 -inPipeline=0 -outPipeline=0 -MOR=0 -InData=Registered -AdControl=Registered -MemFile= -MemFormat=bin -Reset=Sync -GSR=Enabled -Pad=0 -EnECC=0 -Optimization=Speed -EnSleep=ENABLED -Pipeline=0 - -[FilesGenerated] -=mem diff --git a/gbe_ecp2m/ipcores/statts_mem.vhd b/gbe_ecp2m/ipcores/statts_mem.vhd deleted file mode 100644 index 2a03d69..0000000 --- a/gbe_ecp2m/ipcores/statts_mem.vhd +++ /dev/null @@ -1,159 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 6.1 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 8 -data_width 32 -num_rows 255 -cascade -1 -e - --- Mon Dec 5 22:40:38 2011 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity statts_mem is - port ( - WrAddress: in std_logic_vector(7 downto 0); - RdAddress: in std_logic_vector(9 downto 0); - Data: in std_logic_vector(31 downto 0); - WE: in std_logic; - RdClock: in std_logic; - RdClockEn: in std_logic; - Reset: in std_logic; - WrClock: in std_logic; - WrClockEn: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end statts_mem; - -architecture Structure of statts_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component PDPW16KC - generic (GSR : in String; CSDECODE_R : in String; - CSDECODE_W : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute MEM_LPC_FILE of statts_mem_0_0_0 : label is "statts_mem.lpc"; - attribute MEM_INIT_FILE of statts_mem_0_0_0 : label is ""; - attribute RESETMODE of statts_mem_0_0_0 : label is "SYNC"; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - statts_mem_0_0_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36) - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10), - DI12=>Data(11), DI13=>Data(12), DI14=>Data(13), - DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo, - DI18=>Data(16), DI19=>Data(17), DI20=>Data(18), - DI21=>Data(19), DI22=>Data(20), DI23=>Data(21), - DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo, - DI27=>Data(24), DI28=>Data(25), DI29=>Data(26), - DI30=>Data(27), DI31=>Data(28), DI32=>Data(29), - DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo, - ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2), - ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5), - ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>scuba_vlo, - BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>RdAddress(0), - ADR4=>RdAddress(1), ADR5=>RdAddress(2), ADR6=>RdAddress(3), - ADR7=>RdAddress(4), ADR8=>RdAddress(5), ADR9=>RdAddress(6), - ADR10=>RdAddress(7), ADR11=>RdAddress(8), - ADR12=>RdAddress(9), ADR13=>scuba_vlo, CER=>RdClockEn, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), - DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), - DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, - DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, - DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open, - DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open, - DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open, - DO33=>open, DO34=>open, DO35=>open); - -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of statts_mem is - for Structure - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/statts_mem_tmpl.vhd b/gbe_ecp2m/ipcores/statts_mem_tmpl.vhd deleted file mode 100644 index 9953b55..0000000 --- a/gbe_ecp2m/ipcores/statts_mem_tmpl.vhd +++ /dev/null @@ -1,19 +0,0 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 6.1 --- Mon Dec 5 22:40:38 2011 - --- parameterized module component declaration -component statts_mem - port (WrAddress: in std_logic_vector(7 downto 0); - RdAddress: in std_logic_vector(9 downto 0); - Data: in std_logic_vector(31 downto 0); WE: in std_logic; - RdClock: in std_logic; RdClockEn: in std_logic; - Reset: in std_logic; WrClock: in std_logic; - WrClockEn: in std_logic; Q: out std_logic_vector(7 downto 0)); -end component; - --- parameterized module component instance -__ : statts_mem - port map (WrAddress(7 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(31 downto 0)=>__, - WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__, - WrClockEn=>__, Q(7 downto 0)=>__); diff --git a/gbe_ecp2m/ipcores/tb_fifo_1024x16x8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_1024x16x8_tmpl.vhd deleted file mode 100644 index 2d1eced..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_1024x16x8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_1024x16x8 - port (Data : in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(17 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_1024x16x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 1027 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 1027 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 1027 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd deleted file mode 100755 index 343af71..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_2048x8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_2048x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 2051 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_2048x8x16_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_2048x8x16_tmpl.vhd deleted file mode 100644 index ceb4df6..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_2048x8x16_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_2048x8x16 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(17 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(17 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_2048x8x16 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 2051 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb2_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb2_tmpl.vhd deleted file mode 100644 index 080aaa7..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb2_tmpl.vhd +++ /dev/null @@ -1,119 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.9.1.119 -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -use IEEE.math_real.all; - -use IEEE.numeric_std.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8_mb2 - port (Data : in std_logic_vector(17 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic - ); - end component; - - signal Data : std_logic_vector(17 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0'); - signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0'); - signal Q : std_logic_vector(8 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; - signal AlmostEmpty: std_logic; - signal AlmostFull: std_logic; -begin - u1 : fifo_32kx16x8_mb2 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full, - AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd deleted file mode 100755 index 1ad6e7d..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd +++ /dev/null @@ -1,115 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8_mb - port (Data : in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostEmpty: out std_logic; - AlmostFull: out std_logic - ); - end component; - - signal Data : std_logic_vector(15 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal AmEmptyThresh : std_logic_vector(15 downto 0) := (others => '0'); - signal AmFullThresh : std_logic_vector(14 downto 0) := (others => '0'); - signal Q : std_logic_vector(7 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; - signal AlmostEmpty: std_logic; - signal AlmostFull: std_logic; -begin - u1 : fifo_32kx16x8_mb - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - AmEmptyThresh => AmEmptyThresh, AmFullThresh => AmFullThresh, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full, - AlmostEmpty => AlmostEmpty, AlmostFull => AlmostFull - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_tmpl.vhd deleted file mode 100755 index 3bbafb6..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_tmpl.vhd +++ /dev/null @@ -1,106 +0,0 @@ --- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_32kx16x8 - port (Data : in std_logic_vector(15 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(15 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal WCNT : std_logic_vector(15 downto 0); - signal RCNT : std_logic_vector(16 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_32kx16x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 32771 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 32771 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd deleted file mode 100755 index 0559dd7..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x32 - port (Data : in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(31 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x32 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd deleted file mode 100755 index 9352be8..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x9 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x9 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_512x32_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_512x32_tmpl.vhd deleted file mode 100644 index 7353ce2..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_512x32_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x32 - port (Data : in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(31 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x32 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_512x64_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_512x64_tmpl.vhd deleted file mode 100644 index dc94036..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_512x64_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x64 - port (Data : in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(71 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(71 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(71 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x64 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_512x72_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_512x72_tmpl.vhd deleted file mode 100644 index 7c36749..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_512x72_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_512x72 - port (Data : in std_logic_vector(71 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(71 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(71 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(71 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_512x72 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 515 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 515 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd deleted file mode 100755 index 2096041..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd +++ /dev/null @@ -1,102 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_64kx8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_64kx8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 65539 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_64kx9_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_64kx9_tmpl.vhd deleted file mode 100644 index d2a16b3..0000000 --- a/gbe_ecp2m/ipcores/tb_fifo_64kx9_tmpl.vhd +++ /dev/null @@ -1,106 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.9.1.119 -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -use IEEE.math_real.all; - -use IEEE.numeric_std.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_64kx9 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_64kx9 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 65539 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd b/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd deleted file mode 100755 index 862c84d..0000000 --- a/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd +++ /dev/null @@ -1,174 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component ip_mem - port (DataInA : in std_logic_vector(31 downto 0); - DataInB : in std_logic_vector(31 downto 0); - AddressA : in std_logic_vector(7 downto 0); - AddressB : in std_logic_vector(7 downto 0); ClockA: in std_logic; - ClockB: in std_logic; ClockEnA: in std_logic; - ClockEnB: in std_logic; WrA: in std_logic; WrB: in std_logic; - ResetA: in std_logic; ResetB: in std_logic; - QA : out std_logic_vector(31 downto 0); - QB : out std_logic_vector(31 downto 0) - ); - end component; - - signal DataInA : std_logic_vector(31 downto 0) := (others => '0'); - signal DataInB : std_logic_vector(31 downto 0) := (others => '0'); - signal AddressA : std_logic_vector(7 downto 0) := (others => '0'); - signal AddressB : std_logic_vector(7 downto 0) := (others => '0'); - signal ClockA: std_logic := '0'; - signal ClockB: std_logic := '0'; - signal ClockEnA: std_logic := '0'; - signal ClockEnB: std_logic := '0'; - signal WrA: std_logic := '0'; - signal WrB: std_logic := '0'; - signal ResetA: std_logic := '0'; - signal ResetB: std_logic := '0'; - signal QA : std_logic_vector(31 downto 0); - signal QB : std_logic_vector(31 downto 0); -begin - u1 : ip_mem - port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA, - AddressB => AddressB, ClockA => ClockA, ClockB => ClockB, - ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB, - ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB - ); - - process - - begin - DataInA <= (others => '0') ; - wait for 100 ns; - wait until ResetA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - DataInA <= DataInA + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - DataInB <= (others => '0') ; - wait for 100 ns; - wait until ResetB = '0'; - wait until WrB = '1'; - for i in 0 to 259 loop - wait until ClockB'event and ClockB = '1'; - DataInB <= DataInB + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - AddressA <= (others => '0') ; - wait for 100 ns; - wait until ResetA = '0'; - for i in 0 to 518 loop - wait until ClockA'event and ClockA = '1'; - AddressA <= AddressA + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - AddressB <= (others => '0') ; - wait for 100 ns; - wait until ResetB = '0'; - wait until WrB = '1'; - for i in 0 to 518 loop - wait until ClockB'event and ClockB = '1'; - AddressB <= AddressB + '1' after 1 ns; - end loop; - wait; - end process; - - ClockA <= not ClockA after 5.00 ns; - - ClockB <= not ClockB after 5.00 ns; - - process - - begin - ClockEnA <= '0' ; - wait for 100 ns; - wait until ResetA = '0'; - ClockEnA <= '1' ; - wait; - end process; - - process - - begin - ClockEnB <= '0' ; - wait for 100 ns; - wait until ResetB = '0'; - ClockEnB <= '1' ; - wait; - end process; - - process - - begin - WrA <= '0' ; - wait until ResetA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - WrA <= '1' after 1 ns; - end loop; - WrA <= '0' ; - wait; - end process; - - process - - begin - WrB <= '0' ; - wait until ResetB = '0'; - wait until WrA = '1'; - wait until WrA = '0'; - for i in 0 to 259 loop - wait until ClockA'event and ClockA = '1'; - end loop; - for i in 0 to 259 loop - wait until ClockB'event and ClockB = '1'; - WrB <= '1' after 1 ns; - end loop; - WrB <= '0' ; - wait; - end process; - - process - - begin - ResetA <= '1' ; - wait for 100 ns; - ResetA <= '0' ; - wait; - end process; - - process - - begin - ResetB <= '1' ; - wait for 100 ns; - ResetB <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd b/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd deleted file mode 100755 index 701eaf3..0000000 --- a/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd +++ /dev/null @@ -1,64 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component mac_init_mem - port (Address : in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q : out std_logic_vector(7 downto 0) - ); - end component; - - signal Address : std_logic_vector(5 downto 0) := (others => '0'); - signal OutClock: std_logic := '0'; - signal OutClockEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); -begin - u1 : mac_init_mem - port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn, - Reset => Reset, Q => Q - ); - - process - - begin - Address <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 57 loop - wait until OutClock'event and OutClock = '1'; - Address <= Address + '1' after 1 ns; - end loop; - wait; - end process; - - OutClock <= not OutClock after 5.00 ns; - - process - - begin - OutClockEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - OutClockEn <= '1' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - -end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_statts_mem_tmpl.vhd b/gbe_ecp2m/ipcores/tb_statts_mem_tmpl.vhd deleted file mode 100644 index 8428650..0000000 --- a/gbe_ecp2m/ipcores/tb_statts_mem_tmpl.vhd +++ /dev/null @@ -1,124 +0,0 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component statts_mem - port (WrAddress : in std_logic_vector(7 downto 0); - RdAddress : in std_logic_vector(9 downto 0); - Data : in std_logic_vector(31 downto 0); WE: in std_logic; - RdClock: in std_logic; RdClockEn: in std_logic; - Reset: in std_logic; WrClock: in std_logic; - WrClockEn: in std_logic; Q : out std_logic_vector(7 downto 0) - ); - end component; - - signal WrAddress : std_logic_vector(7 downto 0) := (others => '0'); - signal RdAddress : std_logic_vector(9 downto 0) := (others => '0'); - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WE: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal RdClockEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal WrClock: std_logic := '0'; - signal WrClockEn: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); -begin - u1 : statts_mem - port map (WrAddress => WrAddress, RdAddress => RdAddress, Data => Data, - WE => WE, RdClock => RdClock, RdClockEn => RdClockEn, Reset => Reset, - WrClock => WrClock, WrClockEn => WrClockEn, Q => Q - ); - - process - - begin - WrAddress <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 516 loop - wait until WrClock'event and WrClock = '1'; - WrAddress <= WrAddress + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - RdAddress <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 516 loop - wait until RdClock'event and RdClock = '1'; - RdAddress <= RdAddress + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 258 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - process - - begin - WE <= '0' ; - wait until Reset = '0'; - for i in 0 to 258 loop - wait until WrClock'event and WrClock = '1'; - WE <= '1' after 1 ns; - end loop; - WE <= '0' ; - wait; - end process; - - RdClock <= not RdClock after 20.00 ns; - - process - - begin - RdClockEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - RdClockEn <= '1' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 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zh1pGr%V)X0CL(^Dh1n#;7s-sth~MvE7DRkqGZjMoz6vUg;(jtNg7~~vW>LiNwNO(K z=_x(O5b14Y7Dwd#CaN5f3)*1nH5HKyEz~qb`Z}oTh**Nu3`F`RsGAY#A&+t+&RRKT%YcAJf%9b}JNV7sf7bLYUey@9$FL;fwN=E7!9QS)HyF5~9I*0Y6KC2V=M z)B@OgH&Y8?>r+83f=xb+@3k1V{<7O`uocv?x&*et_0&?>E=^Ji*siFimcdpe9V~}! zl+0KGn>;u6S_#{Y4vsVK%dN>c if ( (HCS_N = '0') and (HREAD_N = '0') ) then - HC_NEXT_STATE <= HC_READ; - elsif( (HCS_N = '0') and (HWRITE_N = '0') ) then - HC_NEXT_STATE <= HC_WRITE; - else - HC_NEXT_STATE <= HC_SLEEP; - end if; - when HC_READ => HC_NEXT_STATE <= HC_RACK; - hdataout_en_n_comb <= '0'; - hready_n_comb <= '0'; - when HC_RACK => HC_NEXT_STATE <= HC_SLEEP; - when HC_WRITE => HC_NEXT_STATE <= HC_WACK; - hready_n_comb <= '0'; - when HC_WACK => HC_NEXT_STATE <= HC_SLEEP; - when others => HC_NEXT_STATE <= HC_SLEEP; - end case; -end process HC_STATE_TRANSFORM; - -HREADY_N <= hready_n_buf; -HDATAOUT_EN_N <= hdataout_en_n_buf; - ------------------------------------------------------------------------------- --- state machine for "transmission" ------------------------------------------------------------------------------- - --- preread counter -THE_PREREAD_CTR: process( TX_MAC_CLK ) -begin - if ( RESET_N = '0' ) then - preread_ctr <= (others => '0'); - elsif( rising_edge(TX_MAC_CLK) ) then - if ( preread_rst_comb = '1' ) then - preread_ctr <= (others => '0'); - elsif( preread_ce_comb = '1' ) then - preread_ctr <= preread_ctr + 1; - end if; - end if; -end process THE_PREREAD_CTR; -preread_done_comb <= '1' when (preread_ctr = x"6") - else '0'; - --- state registers -TX_STATE_MEM: process( TX_MAC_CLK, RESET_N ) -begin - if ( RESET_N = '0' ) then - TX_CURRENT_STATE <= TX_SLEEP; - tx_done_buf <= '0'; - elsif( rising_edge(TX_MAC_CLK) ) then - TX_CURRENT_STATE <= TX_NEXT_STATE; - tx_done_buf <= tx_done_comb; - end if; -end process TX_STATE_MEM; - -tx_macread_comb <= preread_ce_comb or read_on_comb; - --- state transitions -TX_STATE_TRANSFORM: process( TX_CURRENT_STATE, TX_FIFOEMPTY, TX_FIFOAVAIL, TX_FIFOEOF, preread_done_comb ) -begin - TX_NEXT_STATE <= TX_SLEEP; -- avoid latches - preread_ce_comb <= '0'; - preread_rst_comb <= '0'; - read_on_comb <= '0'; - tx_done_comb <= '0'; - case TX_CURRENT_STATE is - when TX_SLEEP => tx_bsm <= x"0"; - if( TX_FIFOEMPTY = '0' ) then - TX_NEXT_STATE <= TX_READ; - preread_ce_comb <= '1'; - else - TX_NEXT_STATE <= TX_SLEEP; - end if; - when TX_READ => tx_bsm <= x"1"; - if ( TX_FIFOEMPTY = '1' ) then - TX_NEXT_STATE <= TX_DELAY; - preread_rst_comb <= '1'; - elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '0') ) then - TX_NEXT_STATE <= TX_DELAY; - preread_rst_comb <= '1'; - elsif( (preread_done_comb = '1') and (TX_FIFOAVAIL = '1') ) then - TX_NEXT_STATE <= TX_TRANS; - preread_rst_comb <= '1'; - read_on_comb <= '1'; - else - TX_NEXT_STATE <= TX_READ; - preread_ce_comb <= '1'; - end if; - when TX_DELAY => tx_bsm <= x"2"; - if( TX_FIFOAVAIL = '1' ) then - TX_NEXT_STATE <= TX_TRANS; - read_on_comb <= '1'; - else - TX_NEXT_STATE <= TX_DELAY; - end if; - when TX_TRANS => tx_bsm <= x"3"; - if( TX_FIFOEOF = '1' ) then - TX_NEXT_STATE <= TX_CHECK; - tx_done_comb <= '1'; -- don't know if this is realistic - else - TX_NEXT_STATE <= TX_TRANS; - read_on_comb <= '1'; - end if; - when TX_CHECK => tx_bsm <= x"4"; - if( (TX_FIFOEMPTY = '0') and (TX_FIFOAVAIL = '1') ) then - TX_NEXT_STATE <= TX_READ; - preread_ce_comb <= '1'; - else - TX_NEXT_STATE <= TX_SLEEP; - end if; - when others => tx_bsm <= x"f"; - TX_NEXT_STATE <= TX_SLEEP; - end case; -end process TX_STATE_TRANSFORM; - - - - ------------------------------------------------------------------------------- --- Fake signals ------------------------------------------------------------------------------- -RX_DBOUT <= preread_ctr & tx_bsm; -- x"00"; -RX_FIFO_ERROR <= '0'; -RX_STAT_VECTOR <= x"0000_0000"; -RX_STAT_EN <= '0'; -RX_WRITE <= '0'; -RX_EOF <= '0'; -RX_ERROR <= '0'; - -TX_DISCFRM <= '0'; -TX_EN <= '0'; -TX_ER <= '0'; -TX_STATVEC <= (others => '0'); -TX_STATEN <= '0'; -TXD <= x"00"; - -CPU_IF_GBIT_EN <= '0'; - -TX_DONE <= tx_done_buf; -TX_MACREAD <= tx_macread_comb; - -HDATAOUT <= x"00"; - - -end mb_mac_sim; - - ---port map( --- -------------------------------------------------------------------------- --- --------------- clock, reset, clock enable ------------------------------- --- hclk => CLK, -- (in) host clock (100MHz) --- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz) --- rxmac_clk => '0', -- (in) not used (no receiving on GbE) --- reset_n => GSR_N, -- (in) global set/reset --- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation --- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation --- -------------------------------------------------------------------------- --- --------------- SGMII receive interface ---------------------------------- --- rxd => x"00", -- (in) receive data from SGMII core --- rx_dv => '0', -- (in) data valid from SGMII core --- rx_er => '0', -- (in) receive data error --- col => TSM_COL_IN, -- (in) collision from SGMII core --- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core --- -------------------------------------------------------------------------- --- --------------- SGMII transmit interface --------------------------------- --- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core --- tx_en => CH_TX_EN_OUT, -- (out) transmit enable --- tx_er => CH_TX_ER_OUT, -- (out) transmit error --- -------------------------------------------------------------------------- --- --------------- CPU configuration interface ------------------------------ --- haddr => haddr, -- (in) host address bus for configuration --- hdatain => hdataout, -- (in) host data bus for write accesses --- hcs_n => hcs, -- (in) host chip select signal --- hwrite_n => hwrite, -- (in) host write strobe signal --- hread_n => hread, -- (in) host read strobe signal --- hdataout => hdatain, -- (out) host data bus for read accesses --- hdataout_en_n => hdataout_en, -- (out) read data valid signal --- hready_n => hready, -- (out) data acknowledge signal --- cpu_if_gbit_en => open, -- (out) status bit --- -------------------------------------------------------------------------- --- --------------- Transmit FIFO interface ---------------------------------- --- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus --- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available --- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame --- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty --- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read --- tx_done => mac_tx_done, -- (out) transmit done (without errors) --- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer --- tx_sndpausreq => '0', -- (in) PAUSE frame request --- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control) --- tx_discfrm => open, -- (out) discard frame --- tx_staten => open, -- (out) transmit statistics vector enable --- tx_statvec => open, -- (out) transmit statistics vector --- -------------------------------------------------------------------------- --- --------------- Receive FIFO interface ----------------------------------- --- rx_dbout => open, -- (out) receive FIFO data output --- rx_fifo_full => '0', -- (in) receive FIFO full --- ignore_pkt => '0', -- (in) ignore next packet --- rx_fifo_error => open, -- (out) receive FIFO error --- rx_stat_vector => open, -- (out) receive statistics vector --- rx_stat_en => open, -- (out) receive statistics vector enable --- rx_write => open, -- (out) receive FIFO write --- rx_eof => open, -- (out) end of frame --- rx_error => open -- (out) receive packet error ---); diff --git a/gbe_ecp2m/slv_mac_memory.vhd b/gbe_ecp2m/slv_mac_memory.vhd deleted file mode 100644 index bd74e03..0000000 --- a/gbe_ecp2m/slv_mac_memory.vhd +++ /dev/null @@ -1,178 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; - -entity slv_mac_memory is -port( - CLK : in std_logic; - RESET : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(7 downto 0); - MEM_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG -); -end entity; - -architecture Behavioral of slv_mac_memory is - -component ip_mem is -port( - DataInA : in std_logic_vector(31 downto 0); - DataInB : in std_logic_vector(31 downto 0); - AddressA : in std_logic_vector(7 downto 0); - AddressB : in std_logic_vector(7 downto 0); - ClockA : in std_logic; - ClockB : in std_logic; - ClockEnA : in std_logic; - ClockEnB : in std_logic; - WrA : in std_logic; - WrB : in std_logic; - ResetA : in std_logic; - ResetB : in std_logic; - QA : out std_logic_vector(31 downto 0); - QB : out std_logic_vector(31 downto 0) -); -end component ip_mem; - --- Signals -type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); -signal CURRENT_STATE, NEXT_STATE: STATES; - --- slave bus signals -signal slv_busy_x : std_logic; -signal slv_busy : std_logic; -signal slv_ack_x : std_logic; -signal slv_ack : std_logic; -signal store_wr_x : std_logic; -signal store_wr : std_logic; -signal store_rd_x : std_logic; -signal store_rd : std_logic; - -signal reg_busy : std_logic; - -begin - --- Fake -reg_busy <= busy_in; -stat <= (others => '0'); - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- --- State memory process -STATE_MEM: process( clk ) -begin - if( rising_edge(clk) ) then - if( reset = '1' ) then - CURRENT_STATE <= SLEEP; - slv_busy <= '0'; - slv_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - slv_busy <= slv_busy_x; - slv_ack <= slv_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; -end process STATE_MEM; - --- Transition matrix -TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) -begin - NEXT_STATE <= SLEEP; - slv_busy_x <= '0'; - slv_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_RDY; - store_rd_x <= '1'; - elsif( (reg_busy = '0') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_RDY; - store_wr_x <= '1'; - elsif( (reg_busy = '1') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_BSY; - elsif( (reg_busy = '1') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_BSY; - else - NEXT_STATE <= SLEEP; - end if; - when RD_RDY => NEXT_STATE <= RD_ACK; - when WR_RDY => NEXT_STATE <= WR_ACK; - when RD_ACK => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - slv_ack_x <= '1'; - else - NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - end if; - when WR_ACK => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - slv_ack_x <= '1'; - else - NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - end if; - when RD_BSY => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; - end if; - when WR_BSY => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; - end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - ---------------------------------------------------------- --- data handling -- ---------------------------------------------------------- - -THE_MAC_MEM: ip_mem -port map( - DataInA => slv_data_in, - AddressA => slv_addr_in, - ClockA => clk, - ClockEnA => '1', - QA => slv_data_out, - WrA => store_wr, - ResetA => reset, - DataInB => x"0000_0000", - AddressB => mem_addr_in, - ClockB => mem_clk_in, - ClockEnB => '1', - WrB => '0', -- never write - ResetB => reset, - QB => mem_data_out -); - --- output signals -slv_ack_out <= slv_ack; -slv_busy_out <= slv_busy; - -end Behavioral; diff --git a/gbe_ecp2m/slv_register.vhd b/gbe_ecp2m/slv_register.vhd deleted file mode 100755 index 763550b..0000000 --- a/gbe_ecp2m/slv_register.vhd +++ /dev/null @@ -1,177 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; ---use work.adcmv3_components.all; - - -entity slv_register is -generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - REG_DATA_IN : in std_logic_vector(31 downto 0); - REG_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); -end entity; - -architecture Behavioral of slv_register is - --- Signals - - type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- slave bus signals - signal slv_busy_x : std_logic; - signal slv_busy : std_logic; - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input - signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data - signal reg_busy : std_logic; - -begin - --- Fake -reg_busy <= busy_in; -stat <= (others => '0'); - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- --- State memory process -STATE_MEM: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - slv_busy <= '0'; - slv_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - slv_busy <= slv_busy_x; - slv_ack <= slv_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; -end process STATE_MEM; - --- Transition matrix -TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) -begin - NEXT_STATE <= SLEEP; - slv_busy_x <= '0'; - slv_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_RDY; - store_rd_x <= '1'; - elsif( (reg_busy = '0') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_RDY; - store_wr_x <= '1'; - elsif( (reg_busy = '1') and (slv_read_in = '1') ) then - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; -- added 23022009 - elsif( (reg_busy = '1') and (slv_write_in = '1') ) then - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; -- added 23022009 - else - NEXT_STATE <= SLEEP; - end if; - when RD_RDY => NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - when WR_RDY => NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - when RD_ACK => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - end if; - when WR_ACK => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - end if; - when RD_BSY => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= RD_BSY; - slv_busy_x <= '1'; - end if; - when WR_BSY => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - else - NEXT_STATE <= WR_BSY; - slv_busy_x <= '1'; - end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - ---------------------------------------------------------- --- data handling -- ---------------------------------------------------------- - --- register write -THE_WRITE_REG_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - reg_slv_data_in <= RESET_VALUE; - elsif( store_wr = '1' ) then - reg_slv_data_in <= slv_data_in; - end if; - end if; -end process THE_WRITE_REG_PROC; - --- register read -THE_READ_REG_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if ( reset_in = '1' ) then - reg_slv_data_out <= (others => '0'); - elsif( store_rd = '1' ) then - reg_slv_data_out <= reg_data_in; - end if; - end if; -end process THE_READ_REG_PROC; - --- output signals -slv_ack_out <= slv_ack; -slv_busy_out <= slv_busy; -slv_data_out <= reg_slv_data_out; - ---------------------------------------------------------- --- signals to backend -- ---------------------------------------------------------- - -reg_data_out <= reg_slv_data_in; - -end Behavioral; diff --git a/gbe_ecp2m/tb_feeder.vhd b/gbe_ecp2m/tb_feeder.vhd deleted file mode 100755 index d526404..0000000 --- a/gbe_ecp2m/tb_feeder.vhd +++ /dev/null @@ -1,300 +0,0 @@ - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT feeder - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); - CTS_CODE_IN : IN std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : IN std_logic; - CTS_READ_IN : IN std_logic; - FEE_DATA_IN : IN std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : IN std_logic; - FEE_BUSY_IN : IN std_logic; - FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); - PC_READY_IN : IN std_logic; - CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : OUT std_logic; - CTS_READOUT_FINISHED_OUT : OUT std_logic; - CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); - FEE_READ_OUT : OUT std_logic; - PC_WR_EN_OUT : OUT std_logic; - PC_DATA_OUT : OUT std_logic_vector(7 downto 0); - PC_SOS_OUT : OUT std_logic; - PC_EOD_OUT : OUT std_logic; - PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); - PC_PADDING_OUT : OUT std_logic; - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : OUT std_logic; - DBG_SF_WR_EN_OUT : OUT std_logic; - DBG_SF_EMPTY_OUT : OUT std_logic; - DBG_SF_FULL_OUT : OUT std_logic; - DBG_SF_AFULL_OUT : OUT std_logic; - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL PC_WR_EN_OUT : std_logic; - SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL PC_READY_IN : std_logic; - SIGNAL PC_SOS_OUT : std_logic; - SIGNAL PC_EOD_OUT : std_logic; - SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_PADDING_OUT : std_logic; - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); - SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); - SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RD_EN_OUT : std_logic; - SIGNAL DBG_SF_WR_EN_OUT : std_logic; - SIGNAL DBG_SF_EMPTY_OUT : std_logic; - SIGNAL DBG_SF_FULL_OUT : std_logic; - SIGNAL DBG_SF_AFULL_OUT : std_logic; - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: feeder PORT MAP( - CLK => CLK, - RESET => RESET, - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => CTS_READ_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - PC_WR_EN_OUT => PC_WR_EN_OUT, - PC_DATA_OUT => PC_DATA_OUT, - PC_READY_IN => PC_READY_IN, - PC_SOS_OUT => PC_SOS_OUT, - PC_EOD_OUT => PC_EOD_OUT, - PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, - PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, - PC_PADDING_OUT => PC_PADDING_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, - DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, - DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, - DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, - DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, - DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, - DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, - DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, - DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, - DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, - DEBUG_OUT => DEBUG_OUT - ); - -CLOCK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN; - --- Testbench -TESTBENCH_PROC: process -variable test_data_len : integer range 0 to 65535 := 49; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; -begin - -- Setup signals - reset <= '0'; - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"0000_0000"; - fee_busy_in <= '0'; - pc_ready_in <= '0'; - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 9; - test_data_len := 14; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - -- IPU transmission starts - wait until rising_edge(clk); - cts_number_in <= std_logic_vector( trigger_counter ); - cts_code_in <= x"aa"; - cts_information_in <= x"de"; - cts_readout_type_in <= x"1"; - cts_start_readout_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - fee_busy_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - -- ONE DATA TRANSMISSION - -- calculate the needed variables --- test_data_len := 4096; - test_loop_len := 2*(test_data_len - 1) + 1; - test_hdr_len := to_unsigned( test_data_len + 1, 16 ); - test_evt_len := to_unsigned( test_data_len, 16 ); - - -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) - fee_dataready_in <= '1'; - fee_data_in <= x"10aa"; - wait until rising_edge(clk); - fee_data_in <= std_logic_vector( trigger_counter ); - wait until rising_edge(clk); - fee_data_in <= std_logic_vector( test_hdr_len ); - wait until rising_edge(clk); - fee_data_in <= x"ff21"; - wait until rising_edge(clk); - fee_data_in <= std_logic_vector( test_evt_len ); - wait until rising_edge(clk); - fee_data_in <= x"ff22"; - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - wait until rising_edge(clk); - fee_data_in <= std_logic_vector(test_data); - end loop MY_DATA_LOOP; - - fee_busy_in <= '0'; -- correct? - wait until rising_edge(clk); - fee_dataready_in <= '0'; - fee_data_in <= x"0000"; - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_read_in <= '1'; - wait until rising_edge(clk); - cts_read_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_start_readout_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - end loop MY_TRIGGER_LOOP; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - - - wait for 300 ns; - - -- Start packet_constructor - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_ready_in <= '1'; - wait until rising_edge(clk); - - wait; - - wait until rising_edge(clk); - wait until pc_eod_out = '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_ready_in <= '0'; - - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - - -END; diff --git a/gbe_ecp2m/tb_gbe_buf.vhd b/gbe_ecp2m/tb_gbe_buf.vhd deleted file mode 100755 index 8347c02..0000000 --- a/gbe_ecp2m/tb_gbe_buf.vhd +++ /dev/null @@ -1,561 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.math_real.all; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - component trb_net16_gbe_buf is - generic( - DO_SIMULATION : integer range 0 to 1 := 1; - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 - ); - port( - CLK : in std_logic; - TEST_CLK : in std_logic; -- only for simulation! - CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode -RESET : IN std_logic; - GSR_N : IN std_logic; - STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0); - ------------------------ - IP_CFG_START_IN : IN std_logic; - IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0); - IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0); - MR_RESET_IN : IN std_logic; - MR_MODE_IN : IN std_logic; - MR_RESTART_IN : IN std_logic; - IP_CFG_MEM_CLK_OUT : OUT std_logic; - IP_CFG_DONE_OUT : OUT std_logic; - IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0); - -- gk 29.03.10 - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- gk 26.04.10 - -- registers setup interface - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - -- gk 23.04.10 - LED_PACKET_SENT_OUT : out std_logic; - LED_AN_DONE_N_OUT : out std_logic; - ------------------------ - CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); - CTS_CODE_IN : IN std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : IN std_logic; - CTS_READ_IN : IN std_logic; - FEE_DATA_IN : IN std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : IN std_logic; - FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); - FEE_BUSY_IN : IN std_logic; - SFP_RXD_P_IN : IN std_logic; - SFP_RXD_N_IN : IN std_logic; - SFP_REFCLK_P_IN : IN std_logic; - SFP_REFCLK_N_IN : IN std_logic; - SFP_PRSNT_N_IN : IN std_logic; - SFP_LOS_IN : IN std_logic; - STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : OUT std_logic; - CTS_READOUT_FINISHED_OUT : OUT std_logic; - CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); - FEE_READ_OUT : OUT std_logic; - SFP_TXD_P_OUT : OUT std_logic; - SFP_TXD_N_OUT : OUT std_logic; - SFP_TXDIS_OUT : OUT std_logic; - - ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL TEST_CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL GSR_N : std_logic; - SIGNAL STAGE_STAT_REGS_OUT : std_logic_vector(31 downto 0); - SIGNAL STAGE_CTRL_REGS_IN : std_logic_vector(31 downto 0); - SIGNAL IP_CFG_START_IN : std_logic; - SIGNAL IP_CFG_BANK_SEL_IN : std_logic_vector(3 downto 0); - SIGNAL IP_CFG_MEM_DATA_IN : std_logic_vector(31 downto 0); - SIGNAL MR_RESET_IN : std_logic; - SIGNAL MR_MODE_IN : std_logic; - SIGNAL MR_RESTART_IN : std_logic; - SIGNAL IP_CFG_MEM_CLK_OUT : std_logic; - SIGNAL IP_CFG_DONE_OUT : std_logic; - SIGNAL IP_CFG_MEM_ADDR_OUT : std_logic_vector(7 downto 0); - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL SFP_RXD_P_IN : std_logic; - SIGNAL SFP_RXD_N_IN : std_logic; - SIGNAL SFP_TXD_P_OUT : std_logic; - SIGNAL SFP_TXD_N_OUT : std_logic; - SIGNAL SFP_REFCLK_P_IN : std_logic; - SIGNAL SFP_REFCLK_N_IN : std_logic; - SIGNAL SFP_PRSNT_N_IN : std_logic; - SIGNAL SFP_LOS_IN : std_logic; - SIGNAL SFP_TXDIS_OUT : std_logic; - SIGNAL IG_CTS_CTR_TST : std_logic_vector(2 downto 0); - SIGNAL IG_REM_CTR_TST : std_logic_vector(3 downto 0); - SIGNAL IG_BSM_LOAD_TST : std_logic_vector(3 downto 0); - SIGNAL IG_BSM_SAVE_TST : std_logic_vector(3 downto 0); - SIGNAL IG_DATA_TST : std_logic_vector(15 downto 0); - SIGNAL IG_WCNT_TST : std_logic_vector(15 downto 0); - SIGNAL IG_RCNT_TST : std_logic_vector(16 downto 0); - SIGNAL IG_RD_EN_TST : std_logic; - SIGNAL IG_WR_EN_TST : std_logic; - SIGNAL IG_EMPTY_TST : std_logic; - SIGNAL IG_AEMPTY_TST : std_logic; - SIGNAL IG_FULL_TST : std_logic; - SIGNAL IG_AFULL_TST : std_logic; - SIGNAL PC_WR_EN_TST : std_logic; - SIGNAL PC_DATA_TST : std_logic_vector(7 downto 0); - SIGNAL PC_READY_TST : std_logic; - SIGNAL PC_START_OF_SUB_TST : std_logic; - SIGNAL PC_END_OF_DATA_TST : std_logic; - SIGNAL PC_SUB_SIZE_TST : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_TST : std_logic_vector(31 downto 0); - SIGNAL PC_PADDING_TST : std_logic; - SIGNAL PC_DECODING_TST : std_logic_vector(31 downto 0); - SIGNAL PC_EVENT_ID_TST : std_logic_vector(31 downto 0); - SIGNAL PC_QUEUE_DEC_TST : std_logic_vector(31 downto 0); - SIGNAL PC_BSM_CONSTR_TST : std_logic_vector(3 downto 0); - SIGNAL PC_BSM_LOAD_TST : std_logic_vector(3 downto 0); - SIGNAL PC_BSM_SAVE_TST : std_logic_vector(3 downto 0); - SIGNAL PC_SHF_EMPTY_TST : std_logic; - SIGNAL PC_SHF_FULL_TST : std_logic; - SIGNAL PC_SHF_WR_EN_TST : std_logic; - SIGNAL PC_SHF_RD_EN_TST : std_logic; - SIGNAL PC_SHF_Q_TST : std_logic_vector(7 downto 0); - SIGNAL PC_DF_EMPTY_TST : std_logic; - SIGNAL PC_DF_FULL_TST : std_logic; - SIGNAL PC_DF_WR_EN_TST : std_logic; - SIGNAL PC_DF_RD_EN_TST : std_logic; - SIGNAL PC_DF_Q_TST : std_logic_vector(7 downto 0); - SIGNAL PC_ALL_CTR_TST : std_logic_vector(4 downto 0); - SIGNAL PC_SUB_CTR_TST : std_logic_vector(4 downto 0); - SIGNAL PC_BYTES_LOADED_TST : std_logic_vector(15 downto 0); - SIGNAL PC_SIZE_LEFT_TST : std_logic_vector(31 downto 0); - SIGNAL PC_SUB_SIZE_TO_SAVE_TST : std_logic_vector(31 downto 0); - SIGNAL PC_SUB_SIZE_LOADED_TST : std_logic_vector(31 downto 0); - SIGNAL PC_SUB_BYTES_LOADED_TST : std_logic_vector(31 downto 0); - SIGNAL PC_QUEUE_SIZE_TST : std_logic_vector(31 downto 0); - SIGNAL PC_ACT_QUEUE_SIZE_TST : std_logic_vector(31 downto 0); - SIGNAL FC_WR_EN_TST : std_logic; - SIGNAL FC_DATA_TST : std_logic_vector(7 downto 0); - SIGNAL FC_H_READY_TST : std_logic; - SIGNAL FC_READY_TST : std_logic; - SIGNAL FC_IP_SIZE_TST : std_logic_vector(15 downto 0); - SIGNAL FC_UDP_SIZE_TST : std_logic_vector(15 downto 0); - SIGNAL FC_IDENT_TST : std_logic_vector(15 downto 0); - SIGNAL FC_FLAGS_OFFSET_TST : std_logic_vector(15 downto 0); - SIGNAL FC_SOD_TST : std_logic; - SIGNAL FC_EOD_TST : std_logic; - SIGNAL FC_BSM_CONSTR_TST : std_logic_vector(7 downto 0); - SIGNAL FC_BSM_TRANS_TST : std_logic_vector(3 downto 0); - SIGNAL FT_DATA_TST : std_logic_vector(8 downto 0); - SIGNAL FT_TX_EMPTY_TST : std_logic; - SIGNAL FT_START_OF_PACKET_TST : std_logic; - SIGNAL FT_BSM_INIT_TST : std_logic_vector(3 downto 0); - SIGNAL FT_BSM_MAC_TST : std_logic_vector(3 downto 0); - SIGNAL FT_BSM_TRANS_TST : std_logic_vector(3 downto 0); - SIGNAL MAC_HADDR_TST : std_logic_vector(7 downto 0); - SIGNAL MAC_HDATA_TST : std_logic_vector(7 downto 0); - SIGNAL MAC_HCS_TST : std_logic; - SIGNAL MAC_HWRITE_TST : std_logic; - SIGNAL MAC_HREAD_TST : std_logic; - SIGNAL MAC_HREADY_TST : std_logic; - SIGNAL MAC_HDATA_EN_TST : std_logic; - SIGNAL MAC_FIFOAVAIL_TST : std_logic; - SIGNAL MAC_FIFOEOF_TST : std_logic; - SIGNAL MAC_FIFOEMPTY_TST : std_logic; - SIGNAL MAC_TX_READ_TST : std_logic; - SIGNAL MAC_TX_DONE_TST : std_logic; - SIGNAL PCS_AN_LP_ABILITY_TST : std_logic_vector(15 downto 0); - SIGNAL PCS_AN_COMPLETE_TST : std_logic; - SIGNAL PCS_AN_PAGE_RX_TST : std_logic; - SIGNAL ANALYZER_DEBUG_OUT : std_logic_vector(63 downto 0); - --gk 29.03.10 - signal SLV_ADDR_IN : std_logic_vector(7 downto 0); - signal SLV_READ_IN : std_logic; - signal SLV_WRITE_IN : std_logic; - signal SLV_BUSY_OUT : std_logic; - signal SLV_ACK_OUT : std_logic; - signal SLV_DATA_IN : std_logic_vector(31 downto 0); - signal SLV_DATA_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_gbe_buf - GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 ) - PORT MAP( - CLK => CLK, - CLK_125_IN => '0', - TEST_CLK => TEST_CLK, - RESET => RESET, - GSR_N => GSR_N, - STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT, - STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN, - IP_CFG_START_IN => IP_CFG_START_IN, - IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN, - IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_RESTART_IN => MR_RESTART_IN, - IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT, - IP_CFG_DONE_OUT => IP_CFG_DONE_OUT, - IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT, - -- gk 29.03.10 - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - -- gk 22.04.10 - -- registers setup interface - BUS_ADDR_IN => x"00", - BUS_DATA_IN => x"0000_0000", - BUS_DATA_OUT => open, - BUS_WRITE_EN_IN => '0', - BUS_READ_EN_IN => '0', - BUS_ACK_OUT => open, - -- gk 23.04.10 - LED_PACKET_SENT_OUT => open, - LED_AN_DONE_N_OUT => open, - -------------------------- - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - SFP_RXD_P_IN => SFP_RXD_P_IN, - SFP_RXD_N_IN => SFP_RXD_N_IN, - SFP_TXD_P_OUT => SFP_TXD_P_OUT, - SFP_TXD_N_OUT => SFP_TXD_N_OUT, - SFP_REFCLK_P_IN => SFP_REFCLK_P_IN, - SFP_REFCLK_N_IN => SFP_REFCLK_N_IN, - SFP_PRSNT_N_IN => SFP_PRSNT_N_IN, - SFP_LOS_IN => SFP_LOS_IN, - SFP_TXDIS_OUT => SFP_TXDIS_OUT, - ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT - ); - - - --- 100 MHz system clock -CLOCK_GEN_PROC: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN_PROC; - --- 125 MHz MAC clock -CLOCK2_GEN_PROC: process -begin - test_clk <= '1'; wait for 4.0 ns; - test_clk <= '0'; wait for 3.0 ns; -end process CLOCK2_GEN_PROC; - --- Testbench -TESTBENCH_PROC: process --- test data from TRBnet -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; - --- 1400 bytes MTU => 350 as limit for fragmentation -variable max_event_size : real := 512.0; - -variable seed1 : positive; -- seed for random generator -variable seed2 : positive; -- seed for random generator -variable rand : real; -- random value (0.0 ... 1.0) -variable int_rand : integer; -- random value, scaled to your needs -variable cts_random_number : std_logic_vector(7 downto 0); - -variable stim : std_logic_vector(15 downto 0); - - --- RND test ---UNIFORM(seed1, seed2, rand); ---int_rand := INTEGER(TRUNC(rand*65536.0)); ---stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH)); - -begin - -- Setup signals - reset <= '0'; - gsr_n <= '1'; - - stage_ctrl_regs_in <= x"0000_0000"; - - --ip_cfg_start_in <= '0'; - --ip_cfg_bank_sel_in <= x"0"; - --ip_cfg_mem_data_in <= x"0000_0000"; - mr_reset_in <= '0'; - mr_mode_in <= '0'; - mr_restart_in <= '0'; - SLV_ADDR_IN <= x"00"; - SLV_READ_IN <= '0'; - SLV_WRITE_IN <= '0'; - SLV_DATA_IN <= x"0000_0000"; - - sfp_los_in <= '0'; -- signal from SFP is present - sfp_prsnt_n_in <= '0'; -- SFP itself is present - sfp_refclk_n_in <= '0'; - sfp_refclk_p_in <= '1'; - - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"1234_5678"; - fee_busy_in <= '0'; - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - gsr_n <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - gsr_n <= '1'; - wait until rising_edge(clk); - --wait for 100 ns; - - -- Tests may start here - wait until ft_bsm_init_tst = x"7"; - - --ip_cfg_start_in <= '1'; - - wait for 500 ns; - - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 10; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - -- generate a real random byte for CTS - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand*256.0)); - cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); - - -- IPU transmission starts - wait until rising_edge(clk); - cts_number_in <= std_logic_vector( trigger_counter ); - cts_code_in <= cts_random_number; - cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10 - cts_readout_type_in <= x"1"; - cts_start_readout_in <= '1'; - wait until rising_edge(clk); - wait for 400 ns; - - wait until rising_edge(clk); - fee_busy_in <= '1'; - wait for 300 ns; - wait until rising_edge(clk); - - -- ONE DATA TRANSMISSION - -- dice a length - UNIFORM(seed1, seed2, rand); - test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; - - test_data_len := 9685; - --test_data_len := 400; - - -- calculate the needed variables - test_loop_len := 2*(test_data_len - 1) + 1; - test_hdr_len := to_unsigned( test_data_len + 1, 16 ); - test_evt_len := to_unsigned( test_data_len, 16 ); - - -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) - fee_dataready_in <= '1'; - fee_data_in <= x"10" & cts_random_number; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( trigger_counter ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_hdr_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word - fee_data_in <= x"ff21"; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_evt_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_data_in <= x"ff22"; - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - wait until rising_edge(clk); - fee_data_in <= std_logic_vector(test_data); - if( (test_data MOD 5) = 0 ) then - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - else - fee_dataready_in <= '1'; - end if; - --fee_dataready_in <= '1'; - end loop MY_DATA_LOOP; - -- there must be padding words to get multiple of four LWs - - wait until rising_edge(clk); - fee_dataready_in <= '0'; - fee_data_in <= x"0000"; - - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_busy_in <= '0'; - - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_read_in <= '1'; - wait until rising_edge(clk); - cts_read_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_start_readout_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - --wait for 8 us; - - end loop MY_TRIGGER_LOOP; - --- wait for 8 us; -------------------------------------------------------------------------------- --- end of loop -------------------------------------------------------------------------------- - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - -END; - diff --git a/gbe_ecp2m/tb_ip_configurator.vhd b/gbe_ecp2m/tb_ip_configurator.vhd deleted file mode 100755 index 6188d42..0000000 --- a/gbe_ecp2m/tb_ip_configurator.vhd +++ /dev/null @@ -1,145 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT ip_configurator - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - START_CONFIG_IN : IN std_logic; - BANK_SELECT_IN : IN std_logic_vector(3 downto 0); - MEM_DATA_IN : IN std_logic_vector(31 downto 0); - CONFIG_DONE_OUT : OUT std_logic; - MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0); - MEM_CLK_OUT : OUT std_logic; - DEST_MAC_OUT : OUT std_logic_vector(47 downto 0); - DEST_IP_OUT : OUT std_logic_vector(31 downto 0); - DEST_UDP_OUT : OUT std_logic_vector(15 downto 0); - SRC_MAC_OUT : OUT std_logic_vector(47 downto 0); - SRC_IP_OUT : OUT std_logic_vector(31 downto 0); - SRC_UDP_OUT : OUT std_logic_vector(15 downto 0); - MTU_OUT : OUT std_logic_vector(15 downto 0); - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL START_CONFIG_IN : std_logic; - SIGNAL BANK_SELECT_IN : std_logic_vector(3 downto 0); - SIGNAL CONFIG_DONE_OUT : std_logic; - SIGNAL MEM_ADDR_OUT : std_logic_vector(7 downto 0); - SIGNAL MEM_DATA_IN : std_logic_vector(31 downto 0); - SIGNAL MEM_CLK_OUT : std_logic; - SIGNAL DEST_MAC_OUT : std_logic_vector(47 downto 0); - SIGNAL DEST_IP_OUT : std_logic_vector(31 downto 0); - SIGNAL DEST_UDP_OUT : std_logic_vector(15 downto 0); - SIGNAL SRC_MAC_OUT : std_logic_vector(47 downto 0); - SIGNAL SRC_IP_OUT : std_logic_vector(31 downto 0); - SIGNAL SRC_UDP_OUT : std_logic_vector(15 downto 0); - SIGNAL MTU_OUT : std_logic_vector(15 downto 0); - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: ip_configurator PORT MAP( - CLK => CLK, - RESET => RESET, - START_CONFIG_IN => START_CONFIG_IN, - BANK_SELECT_IN => BANK_SELECT_IN, - CONFIG_DONE_OUT => CONFIG_DONE_OUT, - MEM_ADDR_OUT => MEM_ADDR_OUT, - MEM_DATA_IN => MEM_DATA_IN, - MEM_CLK_OUT => MEM_CLK_OUT, - DEST_MAC_OUT => DEST_MAC_OUT, - DEST_IP_OUT => DEST_IP_OUT, - DEST_UDP_OUT => DEST_UDP_OUT, - SRC_MAC_OUT => SRC_MAC_OUT, - SRC_IP_OUT => SRC_IP_OUT, - SRC_UDP_OUT => SRC_UDP_OUT, - MTU_OUT => MTU_OUT, - DEBUG_OUT => DEBUG_OUT - ); - - -CLK_GEN_PROC: process -begin - clk <= '0'; wait for 5.0 ns; - clk <= '1'; wait for 5.0 ns; -end process CLK_GEN_PROC; - -THE_TESTBENCH: process -begin - -- Setup signals - reset <= '0'; - start_config_in <= '0'; - bank_select_in <= x"0"; - mem_data_in <= x"0000_0000"; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait for 100 ns; - wait until rising_edge(clk); - - -- Tests may start now - wait until rising_edge(clk); - start_config_in <= '1'; - wait until mem_addr_out(3 downto 0) = x"1"; - wait until rising_edge(clk); - mem_data_in <= x"4902d745"; -- dest MAC low - wait until rising_edge(clk); - mem_data_in <= x"00006cf0"; -- dest MAC high - wait until rising_edge(clk); - mem_data_in <= x"c0a80002"; -- dest IP - wait until rising_edge(clk); - mem_data_in <= x"0000c350"; -- dest port - wait until rising_edge(clk); - mem_data_in <= x"eeeeeeee"; -- src MAC low - wait until rising_edge(clk); - mem_data_in <= x"0000eeee"; -- src MAC high - wait until rising_edge(clk); - mem_data_in <= x"c0a80005"; -- src IP - wait until rising_edge(clk); - mem_data_in <= x"0000c350"; -- src port - wait until rising_edge(clk); - mem_data_in <= x"00000578"; -- MTU - wait until rising_edge(clk); - mem_data_in <= x"99999999"; - wait until rising_edge(clk); - mem_data_in <= x"aaaaaaaa"; - wait until rising_edge(clk); - mem_data_in <= x"bbbbbbbb"; - wait until rising_edge(clk); - mem_data_in <= x"cccccccc"; - wait until rising_edge(clk); - mem_data_in <= x"dddddddd"; - wait until rising_edge(clk); - mem_data_in <= x"eeeeeeee"; - wait until rising_edge(clk); - mem_data_in <= x"ffffffff"; - wait until rising_edge(clk); - mem_data_in <= x"00000000"; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - start_config_in <= '0'; - - -- Stay a while... stay forever!!! Muahahaha!!!!! - wait; -end process THE_TESTBENCH; - - -END; diff --git a/gbe_ecp2m/tb_ipu2gbe.vhd b/gbe_ecp2m/tb_ipu2gbe.vhd deleted file mode 100755 index 065e674..0000000 --- a/gbe_ecp2m/tb_ipu2gbe.vhd +++ /dev/null @@ -1,428 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.math_real.all; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_ipu2gbe - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - START_CONFIG_OUT : OUT std_logic; - BANK_SELECT_OUT : OUT std_logic_vector(3 downto 0); - CONFIG_DONE_IN : IN std_logic; - DATA_GBE_ENABLE_IN : IN std_logic; - DATA_IPU_ENABLE_IN : IN std_logic; - MULTI_EVT_ENABLE_IN : IN std_logic; - CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); - CTS_CODE_IN : IN std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : IN std_logic; - CTS_READ_IN : IN std_logic; - FEE_DATA_IN : IN std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : IN std_logic; - FEE_BUSY_IN : IN std_logic; - FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0); - PC_READY_IN : IN std_logic; - CTS_DATA_OUT : OUT std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : OUT std_logic; - CTS_READOUT_FINISHED_OUT : OUT std_logic; - CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); - FEE_READ_OUT : OUT std_logic; - PC_WR_EN_OUT : OUT std_logic; - PC_DATA_OUT : OUT std_logic_vector(7 downto 0); - PC_SOS_OUT : OUT std_logic; - PC_EOD_OUT : OUT std_logic; - PC_SUB_SIZE_OUT : OUT std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : OUT std_logic_vector(31 downto 0); - PC_PADDING_OUT : OUT std_logic; - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - DBG_REM_CTR_OUT : OUT std_logic_vector(3 downto 0); - DBG_CTS_CTR_OUT : OUT std_logic_vector(2 downto 0); - DBG_SF_WCNT_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RCNT_OUT : OUT std_logic_vector(16 downto 0); - DBG_SF_DATA_OUT : OUT std_logic_vector(15 downto 0); - DBG_SF_RD_EN_OUT : OUT std_logic; - DBG_SF_WR_EN_OUT : OUT std_logic; - DBG_SF_EMPTY_OUT : OUT std_logic; - DBG_SF_AEMPTY_OUT : OUT std_logic; - DBG_SF_FULL_OUT : OUT std_logic; - DBG_SF_AFULL_OUT : OUT std_logic; - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL START_CONFIG_OUT : std_logic; - SIGNAL BANK_SELECT_OUT : std_logic_vector(3 downto 0); - SIGNAL CONFIG_DONE_IN : std_logic; - SIGNAL DATA_GBE_ENABLE_IN : std_logic; - SIGNAL DATA_IPU_ENABLE_IN : std_logic; - SIGNAL MULTI_EVT_ENABLE_IN : std_logic; - SIGNAL CTS_NUMBER_IN : std_logic_vector(15 downto 0); - SIGNAL CTS_CODE_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_INFORMATION_IN : std_logic_vector(7 downto 0); - SIGNAL CTS_READOUT_TYPE_IN : std_logic_vector(3 downto 0); - SIGNAL CTS_START_READOUT_IN : std_logic; - SIGNAL CTS_READ_IN : std_logic; - SIGNAL CTS_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL CTS_DATAREADY_OUT : std_logic; - SIGNAL CTS_READOUT_FINISHED_OUT : std_logic; - SIGNAL CTS_LENGTH_OUT : std_logic_vector(15 downto 0); - SIGNAL CTS_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); - SIGNAL FEE_DATA_IN : std_logic_vector(15 downto 0); - SIGNAL FEE_DATAREADY_IN : std_logic; - SIGNAL FEE_READ_OUT : std_logic; - SIGNAL FEE_BUSY_IN : std_logic; - SIGNAL FEE_STATUS_BITS_IN : std_logic_vector(31 downto 0); - SIGNAL PC_WR_EN_OUT : std_logic; - SIGNAL PC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL PC_READY_IN : std_logic; - SIGNAL PC_SOS_OUT : std_logic; - SIGNAL PC_EOD_OUT : std_logic; - SIGNAL PC_SUB_SIZE_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_OUT : std_logic_vector(31 downto 0); - SIGNAL PC_PADDING_OUT : std_logic; - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_REM_CTR_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_CTS_CTR_OUT : std_logic_vector(2 downto 0); - SIGNAL DBG_SF_WCNT_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RCNT_OUT : std_logic_vector(16 downto 0); - SIGNAL DBG_SF_DATA_OUT : std_logic_vector(15 downto 0); - SIGNAL DBG_SF_RD_EN_OUT : std_logic; - SIGNAL DBG_SF_WR_EN_OUT : std_logic; - SIGNAL DBG_SF_EMPTY_OUT : std_logic; - SIGNAL DBG_SF_AEMPTY_OUT : std_logic; - SIGNAL DBG_SF_FULL_OUT : std_logic; - SIGNAL DBG_SF_AFULL_OUT : std_logic; - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_ipu2gbe PORT MAP( - CLK => CLK, - RESET => RESET, - START_CONFIG_OUT => START_CONFIG_OUT, - BANK_SELECT_OUT => BANK_SELECT_OUT, - CONFIG_DONE_IN => CONFIG_DONE_IN, - DATA_GBE_ENABLE_IN => DATA_GBE_ENABLE_IN, - DATA_IPU_ENABLE_IN => DATA_IPU_ENABLE_IN, - MULTI_EVT_ENABLE_IN => MULTI_EVT_ENABLE_IN, - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => CTS_READ_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - PC_WR_EN_OUT => PC_WR_EN_OUT, - PC_DATA_OUT => PC_DATA_OUT, - PC_READY_IN => PC_READY_IN, - PC_SOS_OUT => PC_SOS_OUT, - PC_EOD_OUT => PC_EOD_OUT, - PC_SUB_SIZE_OUT => PC_SUB_SIZE_OUT, - PC_TRIG_NR_OUT => PC_TRIG_NR_OUT, - PC_PADDING_OUT => PC_PADDING_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - DBG_REM_CTR_OUT => DBG_REM_CTR_OUT, - DBG_CTS_CTR_OUT => DBG_CTS_CTR_OUT, - DBG_SF_WCNT_OUT => DBG_SF_WCNT_OUT, - DBG_SF_RCNT_OUT => DBG_SF_RCNT_OUT, - DBG_SF_DATA_OUT => DBG_SF_DATA_OUT, - DBG_SF_RD_EN_OUT => DBG_SF_RD_EN_OUT, - DBG_SF_WR_EN_OUT => DBG_SF_WR_EN_OUT, - DBG_SF_EMPTY_OUT => DBG_SF_EMPTY_OUT, - DBG_SF_AEMPTY_OUT => DBG_SF_AEMPTY_OUT, - DBG_SF_FULL_OUT => DBG_SF_FULL_OUT, - DBG_SF_AFULL_OUT => DBG_SF_AFULL_OUT, - DEBUG_OUT => DEBUG_OUT - ); - -CLOCK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLOCK_GEN; - -PC_READY_PROC: process -begin - pc_ready_in <= '0'; - wait for 500 ns; - pc_ready_in <= '1'; - wait for 500 ns; - pc_ready_in <= '0'; - wait for 99 us; -end process PC_READY_PROC; - --- Testbench -TESTBENCH_PROC: process --- test data from TRBnet -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_hdr_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_data : unsigned(15 downto 0) := x"ffff"; - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; - --- 1400 bytes MTU => 350 as limit for fragmentation ---variable max_event_size : real := 512.0; -variable max_event_size : real := 17.0; - -variable seed1 : positive; -- seed for random generator -variable seed2 : positive; -- seed for random generator -variable rand : real; -- random value (0.0 ... 1.0) -variable int_rand : integer; -- random value, scaled to your needs -variable cts_random_number : std_logic_vector(7 downto 0); - -variable stim : std_logic_vector(15 downto 0); - -begin - -- Setup signals - reset <= '0'; - cts_number_in <= x"0000"; - cts_code_in <= x"00"; - cts_information_in <= x"00"; - cts_readout_type_in <= x"0"; - cts_start_readout_in <= '0'; - cts_read_in <= '0'; - fee_data_in <= x"0000"; - fee_dataready_in <= '0'; - fee_status_bits_in <= x"0000_0000"; - fee_busy_in <= '0'; --- pc_ready_in <= '0'; - - config_done_in <= '1'; - data_gbe_enable_in <= '1'; - data_ipu_enable_in <= '0'; - multi_evt_enable_in <= '0'; - - wait for 22 ns; - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - ---------------------------- - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 2; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - -- generate a real random byte for CTS - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand*256.0)); - cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH)); - - -- IPU transmission starts - wait until rising_edge(clk); - cts_number_in <= std_logic_vector( trigger_counter ); - cts_code_in <= cts_random_number; - cts_information_in <= x"de"; - cts_readout_type_in <= x"1"; - cts_start_readout_in <= '1'; - wait until rising_edge(clk); - wait for 400 ns; - - wait until rising_edge(clk); - fee_busy_in <= '1'; - wait for 300 ns; - wait until rising_edge(clk); - - -- ONE DATA TRANSMISSION - -- dice a length - UNIFORM(seed1, seed2, rand); - test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; - --- test_data_len := 9685; - - -- calculate the needed variables - test_loop_len := 2*(test_data_len - 1) + 1; - test_hdr_len := to_unsigned( test_data_len + 1, 16 ); - test_evt_len := to_unsigned( test_data_len, 16 ); - - -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21) - fee_dataready_in <= '1'; - fee_data_in <= x"10" & cts_random_number; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( trigger_counter ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); -- BLA - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_hdr_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word - fee_data_in <= x"ff21"; - wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - fee_data_in <= std_logic_vector( test_evt_len ); - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_data_in <= x"ff22"; - wait until rising_edge(clk) and (fee_read_out = '1'); - fee_dataready_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - wait until rising_edge(clk) and (fee_read_out = '1'); -- - fee_data_in <= std_logic_vector(test_data); - if( (test_data MOD 5) = 0 ) then - fee_dataready_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_dataready_in <= '1'; - else - fee_dataready_in <= '1'; - end if; - end loop MY_DATA_LOOP; - -- there must be padding words to get multiple of four LWs - - wait until rising_edge(clk); - fee_dataready_in <= '0'; - fee_data_in <= x"0000"; - - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fee_busy_in <= '0'; - - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_read_in <= '1'; - wait until rising_edge(clk); - cts_read_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - cts_start_readout_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - --wait for 8 us; - - end loop MY_TRIGGER_LOOP; - - - ---------------------------- ---------------------------- - wait for 300 ns; - - wait; - - -- Start packet_constructor - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '1'; - wait until rising_edge(clk); - - wait until rising_edge(clk); - wait until pc_eod_out = '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); --- pc_ready_in <= '0'; - - -- Stay a while... stay forever!!! - wait; - -end process TESTBENCH_PROC; - - -END; diff --git a/gbe_ecp2m/tb_lsm.vhd b/gbe_ecp2m/tb_lsm.vhd deleted file mode 100755 index 6e86029..0000000 --- a/gbe_ecp2m/tb_lsm.vhd +++ /dev/null @@ -1,113 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_lsm_sfp_gbe - PORT( - SYSCLK : IN std_logic; - RESET : IN std_logic; - CLEAR : IN std_logic; - SFP_MISSING_IN : IN std_logic; - SFP_LOS_IN : IN std_logic; - SD_LINK_OK_IN : IN std_logic; - SD_LOS_IN : IN std_logic; - SD_TXCLK_BAD_IN : IN std_logic; - SD_RXCLK_BAD_IN : IN std_logic; - FULL_RESET_OUT : OUT std_logic; - LANE_RESET_OUT : OUT std_logic; - USER_RESET_OUT : OUT std_logic; - TIMING_CTR_OUT : OUT std_logic_vector(18 downto 0); - BSM_OUT : OUT std_logic_vector(3 downto 0); - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL SYSCLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL CLEAR : std_logic; - SIGNAL SFP_MISSING_IN : std_logic; - SIGNAL SFP_LOS_IN : std_logic; - SIGNAL SD_LINK_OK_IN : std_logic; - SIGNAL SD_LOS_IN : std_logic; - SIGNAL SD_TXCLK_BAD_IN : std_logic; - SIGNAL SD_RXCLK_BAD_IN : std_logic; - SIGNAL FULL_RESET_OUT : std_logic; - SIGNAL LANE_RESET_OUT : std_logic; - SIGNAL USER_RESET_OUT : std_logic; - SIGNAL TIMING_CTR_OUT : std_logic_vector(18 downto 0); - SIGNAL BSM_OUT : std_logic_vector(3 downto 0); - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_lsm_sfp_gbe PORT MAP( - SYSCLK => SYSCLK, - RESET => RESET, - CLEAR => CLEAR, - SFP_MISSING_IN => SFP_MISSING_IN, - SFP_LOS_IN => SFP_LOS_IN, - SD_LINK_OK_IN => SD_LINK_OK_IN, - SD_LOS_IN => SD_LOS_IN, - SD_TXCLK_BAD_IN => SD_TXCLK_BAD_IN, - SD_RXCLK_BAD_IN => SD_RXCLK_BAD_IN, - FULL_RESET_OUT => FULL_RESET_OUT, - LANE_RESET_OUT => LANE_RESET_OUT, - USER_RESET_OUT => USER_RESET_OUT, - TIMING_CTR_OUT => TIMING_CTR_OUT, - BSM_OUT => BSM_OUT, - DEBUG_OUT => DEBUG_OUT - ); - - -CLOCK_GEN: process -begin - sysclk <= '1'; wait for 4.0 ns; - sysclk <= '0'; wait for 4.0 ns; -end process CLOCK_GEN; - -THE_TESTBENCH: process -begin - -- Setup signals - reset <= '0'; - clear <= '0'; - sfp_missing_in <= '0'; - sfp_los_in <= '0'; - sd_link_ok_in <= '0'; - sd_los_in <= '0'; - sd_txclk_bad_in <= '1'; - sd_rxclk_bad_in <= '1'; - wait for 100 ns; - - -- Reset - clear <= '1'; - wait for 100 ns; - clear <= '0'; - wait for 10 ns; - - -- Tests may start now - wait until falling_edge(full_reset_out); - wait for 123 ns; - sd_txclk_bad_in <= '0'; - wait for 433 ns; - sd_rxclk_bad_in <= '0'; - - wait for 1.1 us; - sd_rxclk_bad_in <= '1'; - wait for 33 ns; - sd_rxclk_bad_in <= '0'; - - - wait until rising_edge(sysclk); - - -- Stay a while.... stay forever!!! Muahahaha!!!! - wait; - -end process THE_TESTBENCH; - -END; \ No newline at end of file diff --git a/gbe_ecp2m/tb_pc.vhd b/gbe_ecp2m/tb_pc.vhd deleted file mode 100755 index ac85375..0000000 --- a/gbe_ecp2m/tb_pc.vhd +++ /dev/null @@ -1,310 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_gbe_packet_constr - PORT( - RESET : IN std_logic; - CLK : IN std_logic; - PC_WR_EN_IN : IN std_logic; - PC_DATA_IN : IN std_logic_vector(7 downto 0); - PC_START_OF_SUB_IN : IN std_logic; - PC_END_OF_DATA_IN : IN std_logic; - PC_SUB_SIZE_IN : IN std_logic_vector(31 downto 0); - PC_DECODING_IN : IN std_logic_vector(31 downto 0); - PC_EVENT_ID_IN : IN std_logic_vector(31 downto 0); - PC_TRIG_NR_IN : IN std_logic_vector(31 downto 0); - PC_QUEUE_DEC_IN : IN std_logic_vector(31 downto 0); - PC_MAX_FRAME_SIZE_IN : IN std_logic_vector(15 downto 0); - FC_H_READY_IN : IN std_logic; - FC_READY_IN : IN std_logic; - PC_READY_OUT : OUT std_logic; - FC_WR_EN_OUT : OUT std_logic; - FC_DATA_OUT : OUT std_logic_vector(7 downto 0); - FC_IP_SIZE_OUT : OUT std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : OUT std_logic_vector(15 downto 0); - FC_IDENT_OUT : OUT std_logic_vector(15 downto 0); - FC_FLAGS_OFFSET_OUT : OUT std_logic_vector(15 downto 0); - FC_SOD_OUT : OUT std_logic; - FC_EOD_OUT : OUT std_logic; - BSM_CONSTR_OUT : OUT std_logic_vector(3 downto 0); - BSM_LOAD_OUT : OUT std_logic_vector(3 downto 0); - BSM_SAVE_OUT : OUT std_logic_vector(3 downto 0); - DBG_SHF_EMPTY : OUT std_logic; - DBG_SHF_FULL : OUT std_logic; - DBG_SHF_WR_EN : OUT std_logic; - DBG_SHF_RD_EN : OUT std_logic; - DBG_DF_EMPTY : OUT std_logic; - DBG_DF_FULL : OUT std_logic; - DBG_DF_WR_EN : OUT std_logic; - DBG_DF_RD_EN : OUT std_logic; - DBG_ALL_CTR : OUT std_logic_vector(4 downto 0); - DBG_SUB_CTR : OUT std_logic_vector(4 downto 0); - DBG_MY_CTR : OUT std_logic_vector(1 downto 0); - DBG_BYTES_LOADED : OUT std_logic_vector(15 downto 0); - DBG_SIZE_LEFT : OUT std_logic_vector(31 downto 0); - DBG_SUB_SIZE_TO_SAVE : OUT std_logic_vector(31 downto 0); - DBG_SUB_SIZE_LOADED : OUT std_logic_vector(31 downto 0); - DBG_SUB_BYTES_LOADED : OUT std_logic_vector(31 downto 0); - DBG_QUEUE_SIZE : OUT std_logic_vector(31 downto 0); - DBG_ACT_QUEUE_SIZE : OUT std_logic_vector(31 downto 0); - DEBUG_OUT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL RESET : std_logic; - SIGNAL CLK : std_logic; - SIGNAL PC_WR_EN_IN : std_logic; - SIGNAL PC_DATA_IN : std_logic_vector(7 downto 0); - SIGNAL PC_READY_OUT : std_logic; - SIGNAL PC_START_OF_SUB_IN : std_logic; - SIGNAL PC_END_OF_DATA_IN : std_logic; - SIGNAL PC_SUB_SIZE_IN : std_logic_vector(31 downto 0); - SIGNAL PC_DECODING_IN : std_logic_vector(31 downto 0); - SIGNAL PC_EVENT_ID_IN : std_logic_vector(31 downto 0); - SIGNAL PC_TRIG_NR_IN : std_logic_vector(31 downto 0); - SIGNAL PC_QUEUE_DEC_IN : std_logic_vector(31 downto 0); - SIGNAL PC_MAX_FRAME_SIZE_IN : std_logic_vector(15 downto 0); - SIGNAL FC_WR_EN_OUT : std_logic; - SIGNAL FC_DATA_OUT : std_logic_vector(7 downto 0); - SIGNAL FC_H_READY_IN : std_logic; - SIGNAL FC_READY_IN : std_logic; - SIGNAL FC_IP_SIZE_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_UDP_SIZE_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_IDENT_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_FLAGS_OFFSET_OUT : std_logic_vector(15 downto 0); - SIGNAL FC_SOD_OUT : std_logic; - SIGNAL FC_EOD_OUT : std_logic; - SIGNAL BSM_CONSTR_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_LOAD_OUT : std_logic_vector(3 downto 0); - SIGNAL BSM_SAVE_OUT : std_logic_vector(3 downto 0); - SIGNAL DBG_SHF_EMPTY : std_logic; - SIGNAL DBG_SHF_FULL : std_logic; - SIGNAL DBG_SHF_WR_EN : std_logic; - SIGNAL DBG_SHF_RD_EN : std_logic; - SIGNAL DBG_DF_EMPTY : std_logic; - SIGNAL DBG_DF_FULL : std_logic; - SIGNAL DBG_DF_WR_EN : std_logic; - SIGNAL DBG_DF_RD_EN : std_logic; - SIGNAL DBG_ALL_CTR : std_logic_vector(4 downto 0); - SIGNAL DBG_SUB_CTR : std_logic_vector(4 downto 0); - SIGNAL DBG_MY_CTR : std_logic_vector(1 downto 0); - SIGNAL DBG_BYTES_LOADED : std_logic_vector(15 downto 0); - SIGNAL DBG_SIZE_LEFT : std_logic_vector(31 downto 0); - SIGNAL DBG_SUB_SIZE_TO_SAVE : std_logic_vector(31 downto 0); - SIGNAL DBG_SUB_SIZE_LOADED : std_logic_vector(31 downto 0); - SIGNAL DBG_SUB_BYTES_LOADED : std_logic_vector(31 downto 0); - SIGNAL DBG_QUEUE_SIZE : std_logic_vector(31 downto 0); - SIGNAL DBG_ACT_QUEUE_SIZE : std_logic_vector(31 downto 0); - SIGNAL DEBUG_OUT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: trb_net16_gbe_packet_constr PORT MAP( - RESET => RESET, - CLK => CLK, - PC_WR_EN_IN => PC_WR_EN_IN, - PC_DATA_IN => PC_DATA_IN, - PC_READY_OUT => PC_READY_OUT, - PC_START_OF_SUB_IN => PC_START_OF_SUB_IN, - PC_END_OF_DATA_IN => PC_END_OF_DATA_IN, - PC_SUB_SIZE_IN => PC_SUB_SIZE_IN, - PC_DECODING_IN => PC_DECODING_IN, - PC_EVENT_ID_IN => PC_EVENT_ID_IN, - PC_TRIG_NR_IN => PC_TRIG_NR_IN, - PC_QUEUE_DEC_IN => PC_QUEUE_DEC_IN, - PC_MAX_FRAME_SIZE_IN => PC_MAX_FRAME_SIZE_IN, - FC_WR_EN_OUT => FC_WR_EN_OUT, - FC_DATA_OUT => FC_DATA_OUT, - FC_H_READY_IN => FC_H_READY_IN, - FC_READY_IN => FC_READY_IN, - FC_IP_SIZE_OUT => FC_IP_SIZE_OUT, - FC_UDP_SIZE_OUT => FC_UDP_SIZE_OUT, - FC_IDENT_OUT => FC_IDENT_OUT, - FC_FLAGS_OFFSET_OUT => FC_FLAGS_OFFSET_OUT, - FC_SOD_OUT => FC_SOD_OUT, - FC_EOD_OUT => FC_EOD_OUT, - BSM_CONSTR_OUT => BSM_CONSTR_OUT, - BSM_LOAD_OUT => BSM_LOAD_OUT, - BSM_SAVE_OUT => BSM_SAVE_OUT, - DBG_SHF_EMPTY => DBG_SHF_EMPTY, - DBG_SHF_FULL => DBG_SHF_FULL, - DBG_SHF_WR_EN => DBG_SHF_WR_EN, - DBG_SHF_RD_EN => DBG_SHF_RD_EN, - DBG_DF_EMPTY => DBG_DF_EMPTY, - DBG_DF_FULL => DBG_DF_FULL, - DBG_DF_WR_EN => DBG_DF_WR_EN, - DBG_DF_RD_EN => DBG_DF_RD_EN, - DBG_ALL_CTR => DBG_ALL_CTR, - DBG_SUB_CTR => DBG_SUB_CTR, - DBG_MY_CTR => DBG_MY_CTR, - DBG_BYTES_LOADED => DBG_BYTES_LOADED, - DBG_SIZE_LEFT => DBG_SIZE_LEFT, - DBG_SUB_SIZE_TO_SAVE => DBG_SUB_SIZE_TO_SAVE, - DBG_SUB_SIZE_LOADED => DBG_SUB_SIZE_LOADED, - DBG_SUB_BYTES_LOADED => DBG_SUB_BYTES_LOADED, - DBG_QUEUE_SIZE => DBG_QUEUE_SIZE, - DBG_ACT_QUEUE_SIZE => DBG_ACT_QUEUE_SIZE, - DEBUG_OUT => DEBUG_OUT - ); - -CLK_GEN: process -begin - clk <= '1'; wait for 5.0 ns; - clk <= '0'; wait for 5.0 ns; -end process CLK_GEN; - -THE_TESTBENCH: process -variable test_data_len : integer range 0 to 65535 := 1; -variable test_loop_len : integer range 0 to 65535 := 0; -variable test_evt_len : unsigned(15 downto 0) := x"0000"; -variable test_evt_len_vec : std_logic_vector(15 downto 0); -variable test_sub_len : unsigned(15 downto 0) := x"0000"; -variable test_sub_len_vec : std_logic_vector(15 downto 0); -variable test_data : unsigned(15 downto 0) := x"ffff"; -variable test_data_vec : std_logic_vector(15 downto 0); - -variable trigger_counter : unsigned(15 downto 0) := x"4710"; -variable trigger_loop : integer range 0 to 65535 := 15; -begin - -- Set up signals - reset <= '0'; - pc_wr_en_in <= '0'; - pc_data_in <= x"00"; - pc_start_of_sub_in <= '0'; - pc_end_of_data_in <= '0'; - pc_sub_size_in <= x"0000_0000"; - pc_trig_nr_in <= x"0000_0000"; - pc_decoding_in <= x"0002_0001"; -- static - pc_event_id_in <= x"0000_00ca"; -- static - pc_queue_dec_in <= x"0003_0062"; -- static - pc_max_frame_size_in <= x"0578"; -- static - fc_h_ready_in <= '0'; - fc_ready_in <= '0'; - wait until rising_edge(clk); - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - wait for 200 ns; - wait until rising_edge(clk); - - -- Tests may start now - -------------------------------------------------------------------------------- --- Loop the transmissions -------------------------------------------------------------------------------- - trigger_counter := x"4710"; - trigger_loop := 0; - - test_data_len := 14; - - MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop - - -- calculate the needed variables - test_loop_len := 2*(test_data_len - 1) + 1; - test_evt_len := to_unsigned( test_data_len, 16 ); - test_evt_len_vec := std_logic_vector(test_evt_len); - test_sub_len := test_evt_len + 1; - test_sub_len_vec := std_logic_vector(test_sub_len); - - -- start of subevent marker - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_trig_nr_in <= x"0000" & std_logic_vector(trigger_counter); - pc_sub_size_in <= b"0000_0000_0000_00" & test_sub_len_vec & b"00"; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_start_of_sub_in <= '1'; - wait until rising_edge(clk); - pc_start_of_sub_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_data_in <= test_evt_len_vec(15 downto 8); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_data_in <= test_evt_len_vec(7 downto 0); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_wr_en_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - pc_data_in <= x"ff"; -- source address high byte - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_data_in <= x"22"; -- source address low byte - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_wr_en_in <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - - test_data := x"ffff"; - MY_DATA_LOOP: for J in 0 to test_loop_len loop - test_data := test_data + 1; - test_data_vec := std_logic_vector(test_data); - wait until rising_edge(clk); - pc_data_in <= test_data_vec(15 downto 8); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_data_in <= test_data_vec(7 downto 0); - pc_wr_en_in <= '1'; - wait until rising_edge(clk); - pc_wr_en_in <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); - end loop MY_DATA_LOOP; - - -- end of subevent marker --- wait until rising_edge(clk); - pc_end_of_data_in <= '1'; - wait until rising_edge(clk); - pc_end_of_data_in <= '0'; - pc_sub_size_in <= x"0000_0000"; - pc_trig_nr_in <= x"0000_0000"; - wait until rising_edge(clk); - wait until rising_edge(clk); - - trigger_loop := trigger_loop + 1; - trigger_counter := trigger_counter + 1; - - wait for 500 ns; - wait until rising_edge(clk); - end loop MY_TRIGGER_LOOP; - --- wait for 8 us; -------------------------------------------------------------------------------- --- end of loop -------------------------------------------------------------------------------- - - wait until rising_edge(clk); - fc_ready_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - fc_h_ready_in <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - - -- Stay a while... stay forever!!!Muahahah!!! - wait; - -end process THE_TESTBENCH; - -END; \ No newline at end of file diff --git a/gbe_ecp2m/tb_slv_mac_memory.vhd b/gbe_ecp2m/tb_slv_mac_memory.vhd deleted file mode 100755 index 00293c3..0000000 --- a/gbe_ecp2m/tb_slv_mac_memory.vhd +++ /dev/null @@ -1,114 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - - COMPONENT slv_mac_memory - PORT( - CLK : IN std_logic; - RESET : IN std_logic; - BUSY_IN : IN std_logic; - SLV_ADDR_IN : IN std_logic_vector(7 downto 0); - SLV_READ_IN : IN std_logic; - SLV_WRITE_IN : IN std_logic; - SLV_DATA_IN : IN std_logic_vector(31 downto 0); - MEM_CLK_IN : IN std_logic; - MEM_ADDR_IN : IN std_logic_vector(7 downto 0); - SLV_BUSY_OUT : OUT std_logic; - SLV_ACK_OUT : OUT std_logic; - SLV_DATA_OUT : OUT std_logic_vector(31 downto 0); - MEM_DATA_OUT : OUT std_logic_vector(31 downto 0); - STAT : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - - SIGNAL CLK : std_logic; - SIGNAL RESET : std_logic; - SIGNAL BUSY_IN : std_logic; - SIGNAL SLV_ADDR_IN : std_logic_vector(7 downto 0); - SIGNAL SLV_READ_IN : std_logic; - SIGNAL SLV_WRITE_IN : std_logic; - SIGNAL SLV_BUSY_OUT : std_logic; - SIGNAL SLV_ACK_OUT : std_logic; - SIGNAL SLV_DATA_IN : std_logic_vector(31 downto 0); - SIGNAL SLV_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL MEM_CLK_IN : std_logic; - SIGNAL MEM_ADDR_IN : std_logic_vector(7 downto 0); - SIGNAL MEM_DATA_OUT : std_logic_vector(31 downto 0); - SIGNAL STAT : std_logic_vector(31 downto 0); - -BEGIN - --- Please check and add your generic clause manually - uut: slv_mac_memory PORT MAP( - CLK => CLK, - RESET => RESET, - BUSY_IN => BUSY_IN, - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - MEM_CLK_IN => MEM_CLK_IN, - MEM_ADDR_IN => MEM_ADDR_IN, - MEM_DATA_OUT => MEM_DATA_OUT, - STAT => STAT - ); - -CLK_GEN_PROC: process -begin - clk <= '0'; mem_clk_in <= '0'; wait for 5.0 ns; - clk <= '1'; mem_clk_in <= '1'; wait for 5.0 ns; -end process CLK_GEN_PROC; - -THE_TESTBENCH: process -begin - -- Setup signals - reset <= '0'; - busy_in <= '0'; - slv_addr_in <= x"00"; - slv_read_in <= '0'; - slv_write_in <= '0'; - slv_data_in <= x"dead_beef"; - mem_addr_in <= x"f0"; - wait until rising_edge(clk); - - -- Reset the whole stuff - wait until rising_edge(clk); - reset <= '1'; - wait until rising_edge(clk); - wait until rising_edge(clk); - reset <= '0'; - wait until rising_edge(clk); - - -- Tests may start now - wait until rising_edge(clk); - mem_addr_in <= x"00"; - wait until rising_edge(clk); - mem_addr_in <= x"01"; - wait until rising_edge(clk); - mem_addr_in <= x"02"; - wait until rising_edge(clk); - mem_addr_in <= x"03"; - wait until rising_edge(clk); - mem_addr_in <= x"04"; - wait until rising_edge(clk); - mem_addr_in <= x"05"; - wait until rising_edge(clk); - mem_addr_in <= x"06"; - wait until rising_edge(clk); - mem_addr_in <= x"07"; - wait until rising_edge(clk); - mem_addr_in <= x"08"; - - -- Stay a while... stay forever!!! Muahahaha!!!!! - wait; -end process THE_TESTBENCH; - -END; diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd deleted file mode 100755 index a8f68b8..0000000 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ /dev/null @@ -1,1281 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; -use work.trb_net_gbe_components.all; ---use work.version.all; - -entity trb_net16_gbe_buf is -generic( - DO_SIMULATION : integer range 0 to 1 := 1; - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 -); -port( - CLK : in std_logic; - TEST_CLK : in std_logic; -- only for simulation! - CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - RESET : in std_logic; - GSR_N : in std_logic; - -- Debug - STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); - STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); - -- configuration interface - IP_CFG_START_IN : in std_logic; - IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); - IP_CFG_DONE_OUT : out std_logic; - IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); - IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); - IP_CFG_MEM_CLK_OUT : out std_logic; - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_RESTART_IN : in std_logic; - -- gk 29.03.10 - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- gk 22.04.10 - -- registers setup interface - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - -- gk 23.04.10 - LED_PACKET_SENT_OUT : out std_logic; - LED_AN_DONE_N_OUT : out std_logic; - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - --SFP Connection - SFP_RXD_P_IN : in std_logic; - SFP_RXD_N_IN : in std_logic; - SFP_TXD_P_OUT : out std_logic; - SFP_TXD_N_OUT : out std_logic; - SFP_REFCLK_P_IN : in std_logic; - SFP_REFCLK_N_IN : in std_logic; - SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SFP_TXDIS_OUT : out std_logic; -- SFP disable - -- debug ports - ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end entity trb_net16_gbe_buf; - -architecture trb_net16_gbe_buf of trb_net16_gbe_buf is - --- Placer Directives -attribute HGROUP : string; --- for whole architecture -attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group"; - - -component tsmac3 -port( - --------------- clock and reset port declarations ------------------ - hclk : in std_logic; - txmac_clk : in std_logic; - rxmac_clk : in std_logic; - reset_n : in std_logic; - txmac_clk_en : in std_logic; - rxmac_clk_en : in std_logic; - ------------------- Input signals to the GMII ---------------- - rxd : in std_logic_vector(7 downto 0); - rx_dv : in std_logic; - rx_er : in std_logic; - col : in std_logic; - crs : in std_logic; - -------------------- Input signals to the CPU I/F ------------------- - haddr : in std_logic_vector(7 downto 0); - hdatain : in std_logic_vector(7 downto 0); - hcs_n : in std_logic; - hwrite_n : in std_logic; - hread_n : in std_logic; - ---------------- Input signals to the Tx MAC FIFO I/F --------------- - tx_fifodata : in std_logic_vector(7 downto 0); - tx_fifoavail : in std_logic; - tx_fifoeof : in std_logic; - tx_fifoempty : in std_logic; - tx_sndpaustim : in std_logic_vector(15 downto 0); - tx_sndpausreq : in std_logic; - tx_fifoctrl : in std_logic; - ---------------- Input signals to the Rx MAC FIFO I/F --------------- - rx_fifo_full : in std_logic; - ignore_pkt : in std_logic; - -------------------- Output signals from the GMII ----------------------- - txd : out std_logic_vector(7 downto 0); - tx_en : out std_logic; - tx_er : out std_logic; - -------------------- Output signals from the CPU I/F ------------------- - hdataout : out std_logic_vector(7 downto 0); - hdataout_en_n : out std_logic; - hready_n : out std_logic; - cpu_if_gbit_en : out std_logic; - ---------------- Output signals from the Tx MAC FIFO I/F --------------- - tx_macread : out std_logic; - tx_discfrm : out std_logic; - tx_staten : out std_logic; - tx_done : out std_logic; - tx_statvec : out std_logic_vector(30 downto 0); - ---------------- Output signals from the Rx MAC FIFO I/F --------------- - rx_fifo_error : out std_logic; - rx_stat_vector : out std_logic_vector(31 downto 0); - rx_dbout : out std_logic_vector(7 downto 0); - rx_write : out std_logic; - rx_stat_en : out std_logic; - rx_eof : out std_logic; - rx_error : out std_logic -); -end component; - -component mb_mac_sim is -port ( - -------------------------------------------------------------------------- - --------------- clock, reset, clock enable ------------------------------- - HCLK : in std_logic; - TX_MAC_CLK : in std_logic; - RX_MAC_CLK : in std_logic; - RESET_N : in std_logic; - TXMAC_CLK_EN : in std_logic; - RXMAC_CLK_EN : in std_logic; - -------------------------------------------------------------------------- - --------------- SGMII receive interface ---------------------------------- - RXD : in std_logic_vector(7 downto 0); - RX_DV : in std_logic; - RX_ER : in std_logic; - COL : in std_logic; - CRS : in std_logic; - -------------------------------------------------------------------------- - --------------- SGMII transmit interface --------------------------------- - TXD : out std_logic_vector(7 downto 0); - TX_EN : out std_logic; - TX_ER : out std_logic; - -------------------------------------------------------------------------- - --------------- CPU configuration interface ------------------------------ - HADDR : in std_logic_vector(7 downto 0); - HDATAIN : in std_logic_vector(7 downto 0); - HCS_N : in std_logic; - HWRITE_N : in std_logic; - HREAD_N : in std_logic; - HDATAOUT : out std_logic_vector(7 downto 0); - HDATAOUT_EN_N : out std_logic; - HREADY_N : out std_logic; - CPU_IF_GBIT_EN : out std_logic; - -------------------------------------------------------------------------- - --------------- Transmit FIFO interface ---------------------------------- - TX_FIFODATA : in std_logic_vector(7 downto 0); - TX_FIFOAVAIL : in std_logic; - TX_FIFOEOF : in std_logic; - TX_FIFOEMPTY : in std_logic; - TX_MACREAD : out std_logic; - TX_DONE : out std_logic; - TX_SNDPAUSTIM : in std_logic_vector(15 downto 0); - TX_SNDPAUSREQ : in std_logic; - TX_FIFOCTRL : in std_logic; - TX_DISCFRM : out std_logic; - TX_STATEN : out std_logic; - TX_STATVEC : out std_logic_vector(30 downto 0); - -------------------------------------------------------------------------- - --------------- Receive FIFO interface ----------------------------------- - RX_DBOUT : out std_logic_vector(7 downto 0); - RX_FIFO_FULL : in std_logic; - IGNORE_PKT : in std_logic; - RX_FIFO_ERROR : out std_logic; - RX_STAT_VECTOR : out std_logic_vector(31 downto 0); - RX_STAT_EN : out std_logic; - RX_WRITE : out std_logic; - RX_EOF : out std_logic; - RX_ERROR : out std_logic -); -end component; - -component slv_mac_memory is -port( - CLK : in std_logic; - RESET : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(7 downto 0); - MEM_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG -); -end component; - -component fifo_4096x9 is -port( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -signal ig_bsm_save : std_logic_vector(3 downto 0); -signal ig_bsm_load : std_logic_vector(3 downto 0); -signal ig_cts_ctr : std_logic_vector(2 downto 0); -signal ig_rem_ctr : std_logic_vector(3 downto 0); -signal ig_debug : std_logic_vector(31 downto 0); -signal ig_data : std_logic_vector(15 downto 0); -signal ig_wcnt : std_logic_vector(15 downto 0); -signal ig_rcnt : std_logic_vector(16 downto 0); -signal ig_rd_en : std_logic; -signal ig_wr_en : std_logic; -signal ig_empty : std_logic; -signal ig_aempty : std_logic; -signal ig_full : std_logic; -signal ig_afull : std_logic; - -signal pc_wr_en : std_logic; -signal pc_data : std_logic_vector(7 downto 0); -signal pc_eod : std_logic; -signal pc_sos : std_logic; -signal pc_ready : std_logic; -signal pc_padding : std_logic; -signal pc_decoding : std_logic_vector(31 downto 0); -signal pc_event_id : std_logic_vector(31 downto 0); -signal pc_queue_dec : std_logic_vector(31 downto 0); -signal pc_max_frame_size : std_logic_vector(15 downto 0); -signal pc_bsm_constr : std_logic_vector(3 downto 0); -signal pc_bsm_load : std_logic_vector(3 downto 0); -signal pc_bsm_save : std_logic_vector(3 downto 0); -signal pc_shf_empty : std_logic; -signal pc_shf_full : std_logic; -signal pc_shf_wr_en : std_logic; -signal pc_shf_rd_en : std_logic; -signal pc_shf_q : std_logic_vector(7 downto 0); -signal pc_df_empty : std_logic; -signal pc_df_full : std_logic; -signal pc_df_wr_en : std_logic; -signal pc_df_rd_en : std_logic; -signal pc_df_q : std_logic_vector(7 downto 0); -signal pc_all_ctr : std_logic_vector(4 downto 0); -signal pc_sub_ctr : std_logic_vector(4 downto 0); -signal pc_bytes_loaded : std_logic_vector(15 downto 0); -signal pc_size_left : std_logic_vector(31 downto 0); -signal pc_sub_size_to_save : std_logic_vector(31 downto 0); -signal pc_sub_size_loaded : std_logic_vector(31 downto 0); -signal pc_sub_bytes_loaded : std_logic_vector(31 downto 0); -signal pc_queue_size : std_logic_vector(31 downto 0); -signal pc_act_queue_size : std_logic_vector(31 downto 0); - -signal fee_read : std_logic; -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_length : std_logic_vector(15 downto 0); -signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet -signal cts_error_pattern : std_logic_vector(31 downto 0); - -signal pc_sub_size : std_logic_vector(31 downto 0); -signal pc_trig_nr : std_logic_vector(31 downto 0); - -signal fc_wr_en : std_logic; -signal fc_data : std_logic_vector(7 downto 0); -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal fc_ident : std_logic_vector(15 downto 0); -signal fc_flags_offset : std_logic_vector(15 downto 0); -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_h_ready : std_logic; -signal fc_ready : std_logic; -signal fc_dest_mac : std_logic_vector(47 downto 0); -signal fc_dest_ip : std_logic_vector(31 downto 0); -signal fc_dest_udp : std_logic_vector(15 downto 0); -signal fc_src_mac : std_logic_vector(47 downto 0); -signal fc_src_ip : std_logic_vector(31 downto 0); -signal fc_src_udp : std_logic_vector(15 downto 0); -signal fc_type : std_logic_vector(15 downto 0); -signal fc_ihl_version : std_logic_vector(7 downto 0); -signal fc_tos : std_logic_vector(7 downto 0); -signal fc_ttl : std_logic_vector(7 downto 0); -signal fc_protocol : std_logic_vector(7 downto 0); -signal fc_bsm_constr : std_logic_vector(7 downto 0); -signal fc_bsm_trans : std_logic_vector(3 downto 0); - -signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10 -signal ft_tx_empty : std_logic; -signal ft_start_of_packet : std_logic; -signal ft_bsm_init : std_logic_vector(3 downto 0); -signal ft_bsm_mac : std_logic_vector(3 downto 0); -signal ft_bsm_trans : std_logic_vector(3 downto 0); - -signal mac_haddr : std_logic_vector(7 downto 0); -signal mac_hdataout : std_logic_vector(7 downto 0); -signal mac_hcs : std_logic; -signal mac_hwrite : std_logic; -signal mac_hread : std_logic; -signal mac_fifoavail : std_logic; -signal mac_fifoempty : std_logic; -signal mac_fifoeof : std_logic; -signal mac_hready : std_logic; -signal mac_hdata_en : std_logic; -signal mac_tx_done : std_logic; -signal mac_tx_read : std_logic; - -signal serdes_clk_125 : std_logic; -signal mac_tx_clk_en : std_logic; -signal mac_rx_clk_en : std_logic; -signal mac_col : std_logic; -signal mac_crs : std_logic; -signal pcs_txd : std_logic_vector(7 downto 0); -signal pcs_tx_en : std_logic; -signal pcs_tx_er : std_logic; -signal pcs_an_lp_ability : std_logic_vector(15 downto 0); -signal pcs_an_complete : std_logic; -signal pcs_an_page_rx : std_logic; - -signal pcs_stat_debug : std_logic_vector(63 downto 0); - -signal stage_stat_regs : std_logic_vector(31 downto 0); -signal stage_ctrl_regs : std_logic_vector(31 downto 0); - -signal analyzer_debug : std_logic_vector(63 downto 0); - -signal ip_cfg_start : std_logic; -signal ip_cfg_bank : std_logic_vector(3 downto 0); -signal ip_cfg_done : std_logic; - -signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); -signal ip_cfg_mem_data : std_logic_vector(31 downto 0); -signal ip_cfg_mem_clk : std_logic; - --- gk 22.04.10 -signal max_packet : std_logic_vector(31 downto 0); -signal min_packet : std_logic_vector(31 downto 0); -signal use_gbe : std_logic; -signal use_trbnet : std_logic; -signal use_multievents : std_logic; --- gk 26.04.10 -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_valid : std_logic; -signal gbe_trig_nr : std_logic_vector(31 downto 0); --- gk 28.04.10 -signal pc_delay : std_logic_vector(31 downto 0); --- gk 04.05.10 -signal ft_eod : std_logic; --- gk 01.06.10 -signal dbg_ipu2gbe1 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe2 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe3 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe4 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe5 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe6 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe7 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe8 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe9 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe10 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe11 : std_logic_vector(31 downto 0); -signal dbg_ipu2gbe12 : std_logic_vector(31 downto 0); -signal dbg_pc1 : std_logic_vector(31 downto 0); -signal dbg_pc2 : std_logic_vector(31 downto 0); -signal dbg_fc1 : std_logic_vector(31 downto 0); -signal dbg_fc2 : std_logic_vector(31 downto 0); -signal dbg_ft1 : std_logic_vector(31 downto 0); -signal dbg_ft2 : std_logic_vector(31 downto 0); --- gk 08.06.10 -signal mac_tx_staten : std_logic; -signal mac_tx_statevec : std_logic_vector(30 downto 0); -signal mac_tx_discfrm : std_logic; - -signal dbg_rd_en : std_logic; -signal dbg_q : std_logic_vector(15 downto 0); - --- gk 21.07.10 -signal allow_large : std_logic; - --- gk 28.07.10 -signal bytes_sent_ctr : std_logic_vector(31 downto 0); -signal monitor_sent : std_logic_vector(31 downto 0); -signal monitor_dropped : std_logic_vector(31 downto 0); -signal monitor_sm : std_logic_vector(31 downto 0); -signal monitor_lr : std_logic_vector(31 downto 0); -signal monitor_hr : std_logic_vector(31 downto 0); -signal monitor_fifos : std_logic_vector(31 downto 0); -signal monitor_fifos_q : std_logic_vector(31 downto 0); -signal monitor_discfrm : std_logic_vector(31 downto 0); - --- gk 02.08.10 -signal discfrm_ctr : std_logic_vector(31 downto 0); - --- gk 28.09.10 -signal dbg_reset_fifo : std_logic; -signal db_fifo_rst : std_logic; - --- gk 30.09.10 -signal fc_rd_en : std_logic; -signal link_ok : std_logic; -signal link_ok_timeout_ctr : std_logic_vector(15 downto 0); - -type linkStates is (ACTIVE, INACTIVE, TIMEOUT, FINALIZE); -signal link_current_state, link_next_state : linkStates; - -signal link_down_ctr : std_logic_vector(15 downto 0); -signal link_down_ctr_lock : std_logic; - -signal link_state : std_logic_vector(3 downto 0); - -signal monitor_empty : std_logic_vector(31 downto 0); - --- gk 07.10.10 -signal pc_eos : std_logic; - --- gk 09.12.10 -signal frame_delay : std_logic_vector(31 downto 0); - -begin - -stage_ctrl_regs <= STAGE_CTRL_REGS_IN; - --- gk 23.04.10 -LED_PACKET_SENT_OUT <= pc_ready; -LED_AN_DONE_N_OUT <= not link_ok; --not pcs_an_complete; - --- gk 22.04.10 moved to gbe_setup entity --- PacketConstructor fixed magic values ---pc_decoding <= x"00020001"; -- !!!! swap it!!!! -- gk 22.04.10 ---pc_event_id <= x"000000ca"; -- !!!! swap it!!!! -- gk 22.04.10 ---pc_queue_dec <= x"00030062"; -- !!!! swap it!!!! -- gk 22.04.10 - --- FrameConstructor fixed magic values -fc_type <= x"0008"; -fc_ihl_version <= x"45"; -fc_tos <= x"10"; -fc_ttl <= x"ff"; -fc_protocol <= x"11"; - --- gk 22.04.10 new entity to set values via slow control -SETUP : gbe_setup -port map( - CLK => CLK, - RESET => RESET, - - -- gk 26.04.10 - -- interface to regio bus - BUS_ADDR_IN => BUS_ADDR_IN, - BUS_DATA_IN => BUS_DATA_IN, - BUS_DATA_OUT => BUS_DATA_OUT, - BUS_WRITE_EN_IN => BUS_WRITE_EN_IN, - BUS_READ_EN_IN => BUS_READ_EN_IN, - BUS_ACK_OUT => BUS_ACK_OUT, - - GBE_TRIG_NR_IN => pc_trig_nr, -- gk 26.04.10 - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT => pc_event_id, - GBE_SUBEVENT_DEC_OUT => pc_decoding, - GBE_QUEUE_DEC_OUT => pc_queue_dec, - GBE_MAX_PACKET_OUT => max_packet, - GBE_MIN_PACKET_OUT => min_packet, -- gk 20.07.10 - GBE_MAX_FRAME_OUT => pc_max_frame_size, - GBE_USE_GBE_OUT => use_gbe, - GBE_USE_TRBNET_OUT => use_trbnet, - GBE_USE_MULTIEVENTS_OUT => use_multievents, - GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10 - GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10 - GBE_DELAY_OUT => pc_delay, - GBE_ALLOW_LARGE_OUT => allow_large, -- gk 21.07.10 - GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10 - -- gk 28.07.10 - MONITOR_BYTES_IN => bytes_sent_ctr, - MONITOR_SENT_IN => monitor_sent, - MONITOR_DROPPED_IN => monitor_dropped, - MONITOR_SM_IN => monitor_sm, - MONITOR_LR_IN => monitor_lr, - MONITOR_HDR_IN => monitor_hr, - MONITOR_FIFOS_IN => monitor_fifos_q, - MONITOR_DISCFRM_IN => monitor_discfrm, - MONITOR_EMPTY_IN => monitor_empty, - MONITOR_LINK_DWN_IN(15 downto 0) => link_down_ctr, -- gk 30.09.10 - MONITOR_LINK_DWN_IN(19 downto 16) => link_state, - MONITOR_LINK_DWN_IN(23 downto 20) => ft_bsm_trans, - MONITOR_LINK_DWN_IN(27 downto 24) => fc_bsm_trans, - MONITOR_LINK_DWN_IN(31 downto 28) => (others => '0'), - -- gk 01.06.10 - DBG_IPU2GBE1_IN => dbg_ipu2gbe1, - DBG_IPU2GBE2_IN => dbg_ipu2gbe2, - DBG_IPU2GBE3_IN => dbg_ipu2gbe3, - DBG_IPU2GBE4_IN => dbg_ipu2gbe4, - DBG_IPU2GBE5_IN => dbg_ipu2gbe5, - DBG_IPU2GBE6_IN => dbg_ipu2gbe6, - DBG_IPU2GBE7_IN => dbg_ipu2gbe7, - DBG_IPU2GBE8_IN => dbg_ipu2gbe8, - DBG_IPU2GBE9_IN => dbg_ipu2gbe9, - DBG_IPU2GBE10_IN => dbg_ipu2gbe10, - DBG_IPU2GBE11_IN => dbg_ipu2gbe11, - DBG_IPU2GBE12_IN => dbg_ipu2gbe12, - DBG_PC1_IN => dbg_pc1, - DBG_PC2_IN => dbg_pc2, - DBG_FC1_IN => dbg_fc1, - DBG_FC2_IN => dbg_fc2, - DBG_FT1_IN => dbg_ft1, - DBG_FT2_IN => dbg_ft2, - DBG_FIFO_RD_EN_OUT => dbg_rd_en, - DBG_FIFO_Q_IN => dbg_q - --DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10 -); - --- IP configurator: allows IP config to change for each event builder -THE_IP_CONFIGURATOR: ip_configurator -port map( - CLK => CLK, - RESET => RESET, - -- configuration interface - START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10 - BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10 - CONFIG_DONE_OUT => ip_cfg_done, --IP_CFG_DONE_OUT, -- new -- gk 27.03.10 - MEM_ADDR_OUT => ip_cfg_mem_addr, --IP_CFG_MEM_ADDR_OUT, -- new -- gk 27.03.10 - MEM_DATA_IN => ip_cfg_mem_data, --IP_CFG_MEM_DATA_IN, -- new -- gk 27.03.10 - MEM_CLK_OUT => ip_cfg_mem_clk, --IP_CFG_MEM_CLK_OUT, -- new -- gk 27.03.10 - -- information for IP cores - DEST_MAC_OUT => fc_dest_mac, - DEST_IP_OUT => fc_dest_ip, - DEST_UDP_OUT => fc_dest_udp, - SRC_MAC_OUT => fc_src_mac, - SRC_IP_OUT => fc_src_ip, - SRC_UDP_OUT => fc_src_udp, - MTU_OUT => open, --pc_max_frame_size, -- gk 22.04.10 - -- Debug - DEBUG_OUT => open -); - --- gk 27.03.01 -MB_IP_CONFIG: slv_mac_memory -port map( - CLK => CLK, -- clk_100, - RESET => RESET, --reset_i, - BUSY_IN => '0', - -- Slave bus - SLV_ADDR_IN => SLV_ADDR_IN, --x"00", --mb_ip_mem_addr(7 downto 0), - SLV_READ_IN => SLV_READ_IN, --'0', --mb_ip_mem_read, - SLV_WRITE_IN => SLV_WRITE_IN, --mb_ip_mem_write, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, --mb_ip_mem_ack, - SLV_DATA_IN => SLV_DATA_IN, --mb_ip_mem_data_wr, - SLV_DATA_OUT => SLV_DATA_OUT, --mb_ip_mem_data_rd, - -- I/O to the backend - MEM_CLK_IN => ip_cfg_mem_clk, - MEM_ADDR_IN => ip_cfg_mem_addr, - MEM_DATA_OUT => ip_cfg_mem_data, - -- Status lines - STAT => open -); - --- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS -THE_IPU_INTERFACE: trb_net16_ipu2gbe -port map( - CLK => CLK, - RESET => RESET, - --Event information coming from CTS - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_OUT => cts_data, - CTS_DATAREADY_OUT => cts_dataready, - CTS_READOUT_FINISHED_OUT => cts_readout_finished, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => cts_length, - CTS_ERROR_PATTERN_OUT => cts_error_pattern, - -- Data from Frontends - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => fee_read, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- slow control interface - START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10 - BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10 - CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10 - DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10 - DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10 - MULT_EVT_ENABLE_IN => use_multievents, - MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10 - MIN_MESSAGE_SIZE_IN => min_packet, -- gk 20.07.10 - READOUT_CTR_IN => readout_ctr, -- gk 26.04.10 - READOUT_CTR_VALID_IN => readout_ctr_valid, -- gk 26.04.10 - ALLOW_LARGE_IN => allow_large, -- gk 21.07.10 - -- PacketConstructor interface - PC_WR_EN_OUT => pc_wr_en, - PC_DATA_OUT => pc_data, - PC_READY_IN => pc_ready, - PC_SOS_OUT => pc_sos, - PC_EOS_OUT => pc_eos, -- gk 07.10.10 - PC_EOD_OUT => pc_eod, - PC_SUB_SIZE_OUT => pc_sub_size, - PC_TRIG_NR_OUT => pc_trig_nr, - PC_PADDING_OUT => pc_padding, - MONITOR_OUT(31 downto 0) => monitor_sent, - MONITOR_OUT(63 downto 32) => monitor_dropped, - MONITOR_OUT(95 downto 64) => monitor_hr, - MONITOR_OUT(127 downto 96) => monitor_sm, - MONITOR_OUT(159 downto 128) => monitor_lr, - MONITOR_OUT(191 downto 160) => monitor_fifos, - MONITOR_OUT(223 downto 192) => monitor_empty, - DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1, - DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2, - DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3, - DEBUG_OUT(127 downto 96) => dbg_ipu2gbe4, - DEBUG_OUT(159 downto 128) => dbg_ipu2gbe5, - DEBUG_OUT(191 downto 160) => dbg_ipu2gbe6, - DEBUG_OUT(223 downto 192) => dbg_ipu2gbe7, - DEBUG_OUT(255 downto 224) => dbg_ipu2gbe8, - DEBUG_OUT(287 downto 256) => dbg_ipu2gbe9, - DEBUG_OUT(319 downto 288) => dbg_ipu2gbe10, - DEBUG_OUT(351 downto 320) => dbg_ipu2gbe11, - DEBUG_OUT(383 downto 352) => dbg_ipu2gbe12 -); - --- Second stage: Packet constructor -PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr -port map( - -- ports for user logic - RESET => RESET, - CLK => CLK, - PC_WR_EN_IN => pc_wr_en, - PC_DATA_IN => pc_data, - PC_READY_OUT => pc_ready, - PC_START_OF_SUB_IN => pc_sos, - PC_END_OF_SUB_IN => pc_eos, -- gk 07.10.10 - PC_END_OF_DATA_IN => pc_eod, - -- queue and subevent layer headers - PC_SUB_SIZE_IN => pc_sub_size, - PC_PADDING_IN => pc_padding, -- gk 29.03.10 - PC_DECODING_IN => pc_decoding, - PC_EVENT_ID_IN => pc_event_id, - PC_TRIG_NR_IN => pc_trig_nr, - PC_QUEUE_DEC_IN => pc_queue_dec, - PC_MAX_FRAME_SIZE_IN => pc_max_frame_size, - PC_DELAY_IN => pc_delay, -- gk 28.04.10 - MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10 - -- NEW PORTS - FC_WR_EN_OUT => fc_wr_en, - FC_DATA_OUT => fc_data, - FC_H_READY_IN => fc_h_ready, - FC_READY_IN => fc_ready, - FC_IP_SIZE_OUT => fc_ip_size, - FC_UDP_SIZE_OUT => fc_udp_size, - FC_IDENT_OUT => fc_ident, - FC_FLAGS_OFFSET_OUT => fc_flags_offset, - FC_SOD_OUT => fc_sod, - FC_EOD_OUT => fc_eod, - DEBUG_OUT(31 downto 0) => dbg_pc1, - DEBUG_OUT(63 downto 32) => dbg_pc2 -); - --- gk 04.08.10 -MON_PROC : process(CLK) -begin - if rising_edge(CLK) then - monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0); - if (dbg_pc1(28) = '1') then - monitor_fifos_q(5 downto 4) <= b"11"; - else - monitor_fifos_q(5 downto 4) <= b"00"; - end if; - if (dbg_pc1(30) = '1') then - monitor_fifos_q(7 downto 6) <= b"11"; - else - monitor_fifos_q(7 downto 6) <= b"00"; - end if; - if (dbg_fc1(28) = '1') then - monitor_fifos_q(11 downto 8) <= b"1111"; - else - monitor_fifos_q(11 downto 8) <= b"0000"; - end if; - if (pcs_an_complete = '0') then - monitor_fifos_q(15 downto 12) <= b"1111"; - else - monitor_fifos_q(15 downto 12) <= b"0000"; - end if; - end if; -end process MON_PROC; - --- Third stage: Frame Constructor -FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr -port map( - -- ports for user logic - RESET => RESET, - CLK => CLK, - LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10 - -- - WR_EN_IN => fc_wr_en, - DATA_IN => fc_data, - START_OF_DATA_IN => fc_sod, - END_OF_DATA_IN => fc_eod, - IP_F_SIZE_IN => fc_ip_size, - UDP_P_SIZE_IN => fc_udp_size, - HEADERS_READY_OUT => fc_h_ready, - READY_OUT => fc_ready, - DEST_MAC_ADDRESS_IN => fc_dest_mac, - DEST_IP_ADDRESS_IN => fc_dest_ip, - DEST_UDP_PORT_IN => fc_dest_udp, - SRC_MAC_ADDRESS_IN => fc_src_mac, - SRC_IP_ADDRESS_IN => fc_src_ip, - SRC_UDP_PORT_IN => fc_src_udp, - FRAME_TYPE_IN => fc_type, - IHL_VERSION_IN => fc_ihl_version, - TOS_IN => fc_tos, - IDENTIFICATION_IN => fc_ident, - FLAGS_OFFSET_IN => fc_flags_offset, - TTL_IN => fc_ttl, - PROTOCOL_IN => fc_protocol, - FRAME_DELAY_IN => frame_delay, -- gk 09.12.10 - -- ports for packetTransmitter - RD_CLK => serdes_clk_125, - FT_DATA_OUT => ft_data, - --FT_EOD_OUT => ft_eod, -- gk 04.05.10 - FT_TX_EMPTY_OUT => ft_tx_empty, - FT_TX_RD_EN_IN => fc_rd_en, --mac_tx_read, -- gk 30.09.10 - FT_START_OF_PACKET_OUT => ft_start_of_packet, - FT_TX_DONE_IN => mac_tx_done, - FT_TX_DISCFRM_IN => mac_tx_discfrm, - -- debug ports - BSM_CONSTR_OUT => fc_bsm_constr, - BSM_TRANS_OUT => fc_bsm_trans, - DEBUG_OUT(31 downto 0) => dbg_fc1, - DEBUG_OUT(63 downto 32) => dbg_fc2 -); - ---*********************** --- LINK STATE CONTROL ---*********************** - --- gk 30.09.10 -fc_rd_en <= '1' when ((link_ok = '1') and (mac_tx_read = '1')) - or (link_ok = '0') - else '0'; - --- gk 30.09.10 -LINK_STATE_MACHINE_PROC : process(serdes_clk_125) -begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') or (dbg_reset_fifo = '1') then - link_current_state <= INACTIVE; - else - link_current_state <= link_next_state; - end if; - end if; -end process; - --- gk 30.09.10 -LINK_STATE_MACHINE : process(serdes_clk_125) -begin - case link_current_state is - - when ACTIVE => - link_state <= x"1"; - if (pcs_an_complete = '0') then - link_next_state <= INACTIVE; - else - link_next_state <= link_current_state; - end if; - - when INACTIVE => - link_state <= x"2"; - if (pcs_an_complete = '1') then - link_next_state <= TIMEOUT; - else - link_next_state <= link_current_state; - end if; - - when TIMEOUT => - link_state <= x"3"; - if (pcs_an_complete = '0') then - link_next_state <= INACTIVE; - else - if (link_ok_timeout_ctr = x"ffff") then - link_next_state <= FINALIZE; - else - link_next_state <= link_current_state; - end if; - end if; - - when FINALIZE => - link_state <= x"4"; - if (pcs_an_complete = '0') then - link_next_state <= INACTIVE; - else - if (pc_ready = '1') then - link_next_state <= ACTIVE; - else - link_next_state <= link_current_state; - end if; - end if; - - end case; -end process LINK_STATE_MACHINE; - --- gk 30.09.10 -LINK_OK_CTR_PROC : process(serdes_clk_125) -begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') or (link_current_state /= TIMEOUT) then - link_ok_timeout_ctr <= (others => '0'); - elsif (link_current_state = TIMEOUT) then - link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1"; - end if; - end if; -end process LINK_OK_CTR_PROC; - --- gk 30.09.10 -LINK_OK_PROC : process(serdes_clk_125) -begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') then - link_ok <= '0'; - elsif (link_current_state = ACTIVE) then - link_ok <= '1'; - else - link_ok <= '0'; - end if; - end if; -end process LINK_OK_PROC; - --- gk 30.09.10 -LINK_DOWN_CTR_PROC : process(serdes_clk_125) -begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') then - link_down_ctr <= (others => '0'); - link_down_ctr_lock <= '0'; - elsif (pcs_an_complete = '1') then - link_down_ctr_lock <= '0'; - elsif ((pcs_an_complete = '0') and (link_down_ctr_lock = '0')) then - link_down_ctr <= link_down_ctr + x"1"; - link_down_ctr_lock <= '1'; - end if; - end if; -end process LINK_DOWN_CTR_PROC; - - - - -FRAME_TRANSMITTER: trb_net16_gbe_frame_trans -port map( - CLK => CLK, - RESET => RESET, - LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10 - TX_MAC_CLK => serdes_clk_125, - TX_EMPTY_IN => ft_tx_empty, - START_OF_PACKET_IN => ft_start_of_packet, - DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10 - -- MAC interface - HADDR_OUT => mac_haddr, - HDATA_OUT => mac_hdataout, - HCS_OUT => mac_hcs, - HWRITE_OUT => mac_hwrite, - HREAD_OUT => mac_hread, - HREADY_IN => mac_hready, - HDATA_EN_IN => mac_hdata_en, - TX_FIFOAVAIL_OUT => mac_fifoavail, - TX_FIFOEOF_OUT => mac_fifoeof, - TX_FIFOEMPTY_OUT => mac_fifoempty, - TX_DONE_IN => mac_tx_done, - TX_DISCFRM_IN => mac_tx_discfrm, - -- Debug - BSM_INIT_OUT => ft_bsm_init, - BSM_MAC_OUT => ft_bsm_mac, - BSM_TRANS_OUT => ft_bsm_trans, - DBG_RD_DONE_OUT => open, - DBG_INIT_DONE_OUT => open, - DBG_ENABLED_OUT => open, - DEBUG_OUT => open - --DEBUG_OUT(31 downto 0) => open, - --DEBUG_OUT(63 downto 32) => open -); - --- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in -imp_gen: if (DO_SIMULATION = 0) generate - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - -- Implementation - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - - -- MAC part - MAC: tsmac3 - port map( - ----------------- clock and reset port declarations ------------------ - hclk => CLK, - txmac_clk => serdes_clk_125, - rxmac_clk => serdes_clk_125, - reset_n => GSR_N, - txmac_clk_en => mac_tx_clk_en, - rxmac_clk_en => mac_rx_clk_en, - ------------------- Input signals to the GMII ---------------- NOT USED - rxd => x"00", - rx_dv => '0', - rx_er => '0', - col => mac_col, - crs => mac_crs, - -------------------- Input signals to the CPU I/F ------------------- - haddr => mac_haddr, - hdatain => mac_hdataout, - hcs_n => mac_hcs, - hwrite_n => mac_hwrite, - hread_n => mac_hread, - ---------------- Input signals to the Tx MAC FIFO I/F --------------- - tx_fifodata => ft_data(7 downto 0), - tx_fifoavail => mac_fifoavail, - tx_fifoeof => mac_fifoeof, - tx_fifoempty => mac_fifoempty, - tx_sndpaustim => x"0000", - tx_sndpausreq => '0', - tx_fifoctrl => '0', -- always data frame - ---------------- Input signals to the Rx MAC FIFO I/F --------------- - rx_fifo_full => '0', - ignore_pkt => '0', - ---------------- Output signals from the GMII ----------------------- - txd => pcs_txd, - tx_en => pcs_tx_en, - tx_er => pcs_tx_er, - ----------------- Output signals from the CPU I/F ------------------- - hdataout => open, - hdataout_en_n => mac_hdata_en, - hready_n => mac_hready, - cpu_if_gbit_en => open, - ------------- Output signals from the Tx MAC FIFO I/F --------------- - tx_macread => mac_tx_read, - tx_discfrm => mac_tx_discfrm, - tx_staten => mac_tx_staten, -- gk 08.06.10 - tx_statvec => mac_tx_statevec, -- gk 08.06.10 - tx_done => mac_tx_done, - ------------- Output signals from the Rx MAC FIFO I/F --------------- - rx_fifo_error => open, - rx_stat_vector => open, - rx_dbout => open, - rx_write => open, - rx_stat_en => open, - rx_eof => open, - rx_error => open - ); - - -- gk 08.06.10 - dbg_statevec_proc : process(serdes_clk_125) - begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') then - dbg_ft1 <= (others => '0'); - elsif (mac_tx_staten = '1') then - dbg_ft1(30 downto 0) <= mac_tx_statevec; - dbg_ft1(31) <= mac_tx_discfrm; - end if; - end if; - end process dbg_statevec_proc; - - dbg_ft2 <= stage_stat_regs; - - serdes_intclk_gen: if (USE_125MHZ_EXTCLK = 0) generate - -- PHY part - PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b - generic map( - USE_125MHZ_EXTCLK => 0 - ) - port map( - RESET => RESET, - GSR_N => GSR_N, - CLK_125_OUT => serdes_clk_125, - CLK_125_IN => CLK_125_IN, - FT_TX_CLK_EN_OUT => mac_tx_clk_en, - FT_RX_CLK_EN_OUT => mac_rx_clk_en, - --connection to frame transmitter (tsmac) - FT_COL_OUT => mac_col, - FT_CRS_OUT => mac_crs, - FT_TXD_IN => pcs_txd, - FT_TX_EN_IN => pcs_tx_en, - FT_TX_ER_IN => pcs_tx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => SFP_REFCLK_P_IN, - SD_REFCLK_N_IN => SFP_REFCLK_N_IN, - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, - -- Autonegotiation stuff - MR_ADV_ABILITY_IN => x"0020", -- full duplex only - MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, - MR_AN_PAGE_RX_OUT => pcs_an_page_rx, - MR_AN_COMPLETE_OUT => pcs_an_complete, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_AN_ENABLE_IN => '1', -- do autonegotiation - MR_RESTART_AN_IN => MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" - ); - end generate serdes_intclk_gen; - - serdes_extclk_gen: if (USE_125MHZ_EXTCLK = 1) generate - -- PHY part - PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b - generic map( - USE_125MHZ_EXTCLK => 1 - ) - port map( - RESET => RESET, - GSR_N => GSR_N, - CLK_125_OUT => serdes_clk_125, - CLK_125_IN => '0', -- not used - FT_TX_CLK_EN_OUT => mac_tx_clk_en, - FT_RX_CLK_EN_OUT => mac_rx_clk_en, - --connection to frame transmitter (tsmac) - FT_COL_OUT => mac_col, - FT_CRS_OUT => mac_crs, - FT_TXD_IN => pcs_txd, - FT_TX_EN_IN => pcs_tx_en, - FT_TX_ER_IN => pcs_tx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => SFP_REFCLK_P_IN, - SD_REFCLK_N_IN => SFP_REFCLK_N_IN, - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, - -- Autonegotiation stuff - MR_ADV_ABILITY_IN => x"0020", -- full duplex only - MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, - MR_AN_PAGE_RX_OUT => pcs_an_page_rx, - MR_AN_COMPLETE_OUT => pcs_an_complete, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_AN_ENABLE_IN => '1', -- do autonegotiation - MR_RESTART_AN_IN => MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" - ); - end generate serdes_extclk_gen; - - stage_stat_regs(31 downto 28) <= x"e"; - stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link s-tatus - stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm - stage_stat_regs(19) <= '0'; - stage_stat_regs(18) <= link_ok; -- gk 30.09.10 - stage_stat_regs(17) <= pcs_an_complete; - stage_stat_regs(16) <= pcs_an_page_rx; - stage_stat_regs(15 downto 0) <= pcs_an_lp_ability; - -end generate imp_gen; - --- in case of simulation we include a fake MAC and no PHY/SerDes. -sim_gen: if (DO_SIMULATION = 1) generate - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - -- Simulation - -------------------------------------------------------------------------------------------- - -------------------------------------------------------------------------------------------- - MAC: mb_mac_sim - port map( -------------------------------------------------------------------------- - --------------- clock, reset, clock enable ------------------------------- - HCLK => CLK, - TX_MAC_CLK => serdes_clk_125, - RX_MAC_CLK => serdes_clk_125, - RESET_N => GSR_N, - TXMAC_CLK_EN => mac_tx_clk_en, - RXMAC_CLK_EN => mac_rx_clk_en, - -------------------------------------------------------------------------- - --------------- SGMII receive interface ---------------------------------- - RXD => x"00", - RX_DV => '0', - RX_ER => '0', - COL => mac_col, - CRS => mac_crs, - -------------------------------------------------------------------------- - --------------- SGMII transmit interface --------------------------------- - TXD => pcs_txd, - TX_EN => pcs_tx_en, - TX_ER => pcs_tx_er, - -------------------------------------------------------------------------- - --------------- CPU configuration interface ------------------------------ - HADDR => mac_haddr, - HDATAIN => mac_hdataout, - HCS_N => mac_hcs, - HWRITE_N => mac_hwrite, - HREAD_N => mac_hread, - HDATAOUT => open, - HDATAOUT_EN_N => mac_hdata_en, - HREADY_N => mac_hready, - CPU_IF_GBIT_EN => open, - -------------------------------------------------------------------------- - --------------- Transmit FIFO interface ---------------------------------- - TX_FIFODATA => ft_data(7 downto 0), - TX_FIFOAVAIL => mac_fifoavail, - TX_FIFOEOF => mac_fifoeof, - TX_FIFOEMPTY => mac_fifoempty, - TX_MACREAD => mac_tx_read, - TX_DONE => mac_tx_done, - TX_SNDPAUSTIM => x"0000", - TX_SNDPAUSREQ => '0', - TX_FIFOCTRL => '0', - TX_DISCFRM => open, - TX_STATEN => open, - TX_STATVEC => open, - -------------------------------------------------------------------------- - --------------- Receive FIFO interface ----------------------------------- - RX_DBOUT => open, - RX_FIFO_FULL => '0', - IGNORE_PKT => '0', - RX_FIFO_ERROR => open, - RX_STAT_VECTOR => open, - RX_STAT_EN => open, - RX_WRITE => open, - RX_EOF => open, - RX_ERROR => open - ); - - -- add external test clock for the MAC part - serdes_clk_125 <= TEST_CLK; - - -- fake signals - pcs_an_lp_ability <= x"4060"; - pcs_an_page_rx <= '0'; - pcs_an_complete <= '1'; - mac_tx_clk_en <= '1'; - mac_rx_clk_en <= '1'; - - stage_stat_regs(31 downto 0) <= (others => '0'); - - pcs_stat_debug(63 downto 0) <= (others => '0'); - - SFP_TXD_P_OUT <= '1'; - SFP_TXD_N_OUT <= '0'; - SFP_TXDIS_OUT <= '0'; - -end generate sim_gen; - --- gk 28.07.10 -BYTES_SENT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - bytes_sent_ctr <= (others => '0'); - elsif (fc_wr_en = '1') then - bytes_sent_ctr <= bytes_sent_ctr + x"1"; - end if; - end if; -end process BYTES_SENT_CTR_PROC; - --- gk 02.08.10 -DISCFRM_PROC : process(serdes_clk_125) -begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') then - discfrm_ctr <= (others => '0'); - elsif (mac_tx_discfrm = '1') then - discfrm_ctr <= discfrm_ctr + x"1"; - end if; - end if; -end process DISCFRM_PROC; - -discfrm_sync : signal_sync - generic map( - DEPTH => 2, - WIDTH => 32 - ) - port map( - RESET => RESET, - D_IN => discfrm_ctr, - CLK0 => serdes_clk_125, - CLK1 => CLK, - D_OUT => monitor_discfrm - ); - --- gk 29.09.10 --- debug fifo saves each sent frame, but drops it after receiving information that everything went fine --- otherwise, the frame will be kept to readout via slow control -db_fifo_rst <= '1' when ((RESET = '1') or ((mac_tx_done = '1') and (discfrm_ctr = x"00000000"))) else '0'; - --- debug_fifo : fifo_4096x9 --- port map( --- Data(7 downto 0) => pcs_txd, --- Data(8) => '0', --- WrClock => serdes_clk_125, --- RdClock => CLK, --- WrEn => pcs_tx_en, --- RdEn => dbg_rd_en, --- Reset => db_fifo_rst, --- RPReset => db_fifo_rst, --- Q => dbg_q(8 downto 0), --- Empty => open, --- Full => open --- ); - ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------- - ---*************** --- LOGIC ANALYZER SIGNALS ---*************** -analyzer_debug <= pcs_stat_debug; - --- Outputs -FEE_READ_OUT <= fee_read; - -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_DATA_OUT <= cts_data; -CTS_LENGTH_OUT <= cts_length; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; - -STAGE_STAT_REGS_OUT <= stage_stat_regs; - -ANALYZER_DEBUG_OUT <= analyzer_debug; - -end architecture; diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd deleted file mode 100755 index 4a7a56f..0000000 --- a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd +++ /dev/null @@ -1,562 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_frame_constr is -port( - -- ports for user logic - RESET : in std_logic; - CLK : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - -- - WR_EN_IN : in std_logic; - DATA_IN : in std_logic_vector(7 downto 0); - START_OF_DATA_IN : in std_logic; - END_OF_DATA_IN : in std_logic; - IP_F_SIZE_IN : in std_logic_vector(15 downto 0); - UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation - HEADERS_READY_OUT : out std_logic; - READY_OUT : out std_logic; - DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - IHL_VERSION_IN : in std_logic_vector(7 downto 0); - TOS_IN : in std_logic_vector(7 downto 0); - IDENTIFICATION_IN : in std_logic_vector(15 downto 0); - FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); - TTL_IN : in std_logic_vector(7 downto 0); - PROTOCOL_IN : in std_logic_vector(7 downto 0); - FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10 - -- ports for packetTransmitter - RD_CLK : in std_logic; -- 125MHz clock!!! - FT_DATA_OUT : out std_logic_vector(8 downto 0); - FT_TX_EMPTY_OUT : out std_logic; - FT_TX_RD_EN_IN : in std_logic; - FT_START_OF_PACKET_OUT : out std_logic; - FT_TX_DONE_IN : in std_logic; - FT_TX_DISCFRM_IN : in std_logic; - -- debug ports - BSM_CONSTR_OUT : out std_logic_vector(7 downto 0); - BSM_TRANS_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_frame_constr; - -architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_frame_group"; - -component fifo_4096x9 is -port( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -attribute sys_encoding : string; - -type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION, - TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS, - SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH, - UDP_CS, SAVE_DATA, CLEANUP, DELAY); -signal constructCurrentState, constructNextState : constructStates; -signal bsm_constr : std_logic_vector(7 downto 0); -attribute sys_encoding of constructCurrentState: signal is "safe,gray"; - -type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP); -signal transmitCurrentState, transmitNextState : transmitStates; -signal bsm_trans : std_logic_vector(3 downto 0); - -signal headers_int_counter : integer range 0 to 6; -signal fpf_data : std_logic_vector(7 downto 0); -signal fpf_empty : std_logic; -signal fpf_full : std_logic; -signal fpf_wr_en : std_logic; -signal fpf_rd_en : std_logic; -signal fpf_q : std_logic_vector(8 downto 0); -signal ip_size : std_logic_vector(15 downto 0); -signal ip_checksum : std_logic_vector(31 downto 0); -signal udp_size : std_logic_vector(15 downto 0); -signal udp_checksum : std_logic_vector(15 downto 0); -signal ft_sop : std_logic; -signal put_udp_headers : std_logic; -signal ready_frames_ctr : std_logic_vector(15 downto 0); -signal sent_frames_ctr : std_logic_vector(15 downto 0); -signal debug : std_logic_vector(63 downto 0); -signal ready : std_logic; -signal headers_ready : std_logic; - -signal cur_max : integer range 0 to 10; - -signal ready_frames_ctr_q : std_logic_vector(15 downto 0); -signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10 - -signal fpf_reset : std_logic; -- gk 01.01.01 - --- gk 09.12.10 -signal delay_ctr : std_logic_vector(31 downto 0); -signal frame_delay_reg : std_logic_vector(31 downto 0); - -begin - --- Fakes -udp_checksum <= x"0000"; -- no checksum test needed ---debug <= (others => '0'); - -ready <= '1' when (constructCurrentState = IDLE) - else '0'; -headers_ready <= '1' when (constructCurrentState = SAVE_DATA) - else '0'; - -sizeProc: process( put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN ) -begin - if( put_udp_headers = '1' ) then - ip_size <= IP_F_SIZE_IN + x"14" + x"8"; - udp_size <= UDP_P_SIZE_IN + x"8"; - else - ip_size <= IP_F_SIZE_IN + x"14"; - udp_size <= UDP_P_SIZE_IN; - end if; -end process sizeProc; - -ipCsProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (constructCurrentState = IDLE) then - ip_checksum <= x"00000000"; - else - case constructCurrentState is - when DEST_MAC_ADDR => - case headers_int_counter is - when 0 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(7 downto 0); - when 1 => - ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(15 downto 8); - when 2 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + SRC_IP_ADDRESS_IN(23 downto 16); - when 3 => - ip_checksum <= ip_checksum + SRC_IP_ADDRESS_IN(31 downto 24); - when 4 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(7 downto 0); - when 5 => - ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(15 downto 8); - when others => null; - end case; - when SRC_MAC_ADDR => - case headers_int_counter is - when 0 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + DEST_IP_ADDRESS_IN(23 downto 16); - when 1 => - ip_checksum <= ip_checksum + DEST_IP_ADDRESS_IN(31 downto 24); - when 2 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IHL_VERSION_IN; - when 3 => - ip_checksum <= ip_checksum + TOS_IN; - when 4 => - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + ip_size(15 downto 8); - when 5 => - ip_checksum <= ip_checksum + ip_size(7 downto 0); - when others => null; - end case; - when VERSION => - if headers_int_counter = 0 then - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + IDENTIFICATION_IN(7 downto 0); - end if; - when TOS_S => - if headers_int_counter = 0 then - ip_checksum <= ip_checksum + IDENTIFICATION_IN(15 downto 8); - end if; - when IP_LENGTH => - if headers_int_counter = 0 then - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + FLAGS_OFFSET_IN(15 downto 8); - elsif headers_int_counter = 1 then - ip_checksum <= ip_checksum + FLAGS_OFFSET_IN(7 downto 0); - end if; - when IDENT => - if headers_int_counter = 0 then - ip_checksum(31 downto 8) <= ip_checksum(31 downto 8) + TTL_IN; - elsif headers_int_counter = 1 then - ip_checksum <= ip_checksum + PROTOCOL_IN; - end if; - -- gk 29.03.10 corrected the bug with bad checksums when sum larger than 16b - when FLAGS => - if headers_int_counter = 0 then - ip_cs_temp_right <= ip_checksum(31 downto 16); - elsif headers_int_counter = 1 then - ip_checksum(31 downto 16) <= (others => '0'); - end if; - when TTL_S => - if headers_int_counter = 0 then - ip_checksum <= ip_checksum + ip_cs_temp_right; - end if; - when PROTO => - if headers_int_counter = 0 then - ip_checksum(15 downto 0) <= ip_checksum(15 downto 0) + ip_checksum(31 downto 16); - end if; - when others => null; - end case; - end if; - end if; -end process ipCsProc; - - -constructMachineProc: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - constructCurrentState <= IDLE; - else - constructCurrentState <= constructNextState; - end if; - end if; -end process constructMachineProc; - ---find next state of construct machine -constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, delay_ctr, FRAME_DELAY_IN ) -begin - constructNextState <= constructCurrentState; - if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0 - case constructCurrentState is - when IDLE => - if( START_OF_DATA_IN = '1' ) then - constructNextState <= DEST_MAC_ADDR; - end if; - when DEST_MAC_ADDR => - constructNextState <= SRC_MAC_ADDR; - when SRC_MAC_ADDR => - constructNextState <= FRAME_TYPE_S; - when FRAME_TYPE_S => - constructNextState <= VERSION; - when VERSION => - constructNextState <= TOS_S; - when TOS_S => - constructNextState <= IP_LENGTH; - when IP_LENGTH => - constructNextState <= IDENT; - when IDENT => - constructNextState <= FLAGS; - when FLAGS => - constructNextState <= TTL_S; - when TTL_S => - constructNextState <= PROTO; - when PROTO => - constructNextState <= HEADER_CS; - when HEADER_CS => - constructNextState <= SRC_IP_ADDR; - when SRC_IP_ADDR => - constructNextState <= DEST_IP_ADDR; - when DEST_IP_ADDR => - if (put_udp_headers = '1') then - constructNextState <= SRC_PORT; - else - constructNextState <= SAVE_DATA; - end if; - when SRC_PORT => - constructNextState <= DEST_PORT; - when DEST_PORT => - constructNextState <= UDP_LENGTH; - when UDP_LENGTH => - constructNextState <= UDP_CS; - when UDP_CS => - constructNextState <= SAVE_DATA; - when SAVE_DATA => - if (END_OF_DATA_IN = '1') then - constructNextState <= CLEANUP; - end if; - when CLEANUP => - constructNextState <= DELAY; -- gk 10.12.10 IDLE; - - -- gk 09.12.10 - when DELAY => - if (delay_ctr = FRAME_DELAY_IN) then - constructNextState <= IDLE; - else - constructNextState <= DELAY; - end if; - - when others => - constructNextState <= IDLE; - end case; - end if; -end process constructMachine; - --- gk 09.12.10 -delayCtrProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (constructCurrentState = IDLE) or (constructCurrentState = CLEANUP) then - delay_ctr <= (others => '0'); - elsif (constructCurrentState = DELAY) then - delay_ctr <= delay_ctr + x"1"; - end if; - - frame_delay_reg <= FRAME_DELAY_IN; - end if; -end process delayCtrProc; - - -bsmConstrProc : process(constructCurrentState) -begin ---find maximum time in each state & set state bits - case constructCurrentState is - when IDLE => cur_max <= 0; bsm_constr <= x"01"; - when DEST_MAC_ADDR => cur_max <= 5; bsm_constr <= x"02"; - when SRC_MAC_ADDR => cur_max <= 5; bsm_constr <= x"03"; - when FRAME_TYPE_S => cur_max <= 1; bsm_constr <= x"04"; - when VERSION => cur_max <= 0; bsm_constr <= x"05"; - when TOS_S => cur_max <= 0; bsm_constr <= x"06"; - when IP_LENGTH => cur_max <= 1; bsm_constr <= x"07"; - when IDENT => cur_max <= 1; bsm_constr <= x"08"; - when FLAGS => cur_max <= 1; bsm_constr <= x"09"; - when TTL_S => cur_max <= 0; bsm_constr <= x"0a"; - when PROTO => cur_max <= 0; bsm_constr <= x"0b"; - when HEADER_CS => cur_max <= 1; bsm_constr <= x"0c"; - when SRC_IP_ADDR => cur_max <= 3; bsm_constr <= x"0d"; - when DEST_IP_ADDR => cur_max <= 3; bsm_constr <= x"0e"; - when SRC_PORT => cur_max <= 1; bsm_constr <= x"0f"; - when DEST_PORT => cur_max <= 1; bsm_constr <= x"10"; - when UDP_LENGTH => cur_max <= 1; bsm_constr <= x"11"; - when UDP_CS => cur_max <= 1; bsm_constr <= x"12"; - when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13"; - when CLEANUP => cur_max <= 0; bsm_constr <= x"14"; - when DELAY => cur_max <= 0; bsm_constr <= x"15"; - when others => cur_max <= 0; bsm_constr <= x"1f"; - end case; -end process; - - -headersIntProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (constructCurrentState = IDLE) then - headers_int_counter <= 0; - else - if (headers_int_counter = cur_max) then - headers_int_counter <= 0; - else - headers_int_counter <= headers_int_counter + 1; - end if; - end if; - end if; -end process headersIntProc; - - - -putUdpHeadersProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (FLAGS_OFFSET_IN(12 downto 0) = "0000000000000") then - put_udp_headers <= '1'; - else - put_udp_headers <= '0'; - end if; - end if; -end process putUdpHeadersProc; - - -fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET, LINK_OK_IN) -begin - if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 - fpf_wr_en <= '0'; - elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) and (constructCurrentState /= DELAY) then - fpf_wr_en <= '1'; - elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then - fpf_wr_en <= '1'; - else - fpf_wr_en <= '0'; - end if; -end process fpfWrEnProc; - -fpfDataProc : process(constructCurrentState, DEST_MAC_ADDRESS_IN, SRC_MAC_ADDRESS_IN, FRAME_TYPE_IN, IHL_VERSION_IN, - TOS_IN, ip_size, IDENTIFICATION_IN, FLAGS_OFFSET_IN, TTL_IN, PROTOCOL_IN, - ip_checksum, SRC_IP_ADDRESS_IN, DEST_IP_ADDRESS_IN, - SRC_UDP_PORT_IN, DEST_UDP_PORT_IN, udp_size, udp_checksum, headers_int_counter, DATA_IN) -begin - case constructCurrentState is - when IDLE => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when DEST_MAC_ADDR => fpf_data <= DEST_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when SRC_MAC_ADDR => fpf_data <= SRC_MAC_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when FRAME_TYPE_S => fpf_data <= FRAME_TYPE_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when VERSION => fpf_data <= IHL_VERSION_IN; - when TOS_S => fpf_data <= TOS_IN; - when IP_LENGTH => fpf_data <= ip_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when IDENT => fpf_data <= IDENTIFICATION_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when FLAGS => fpf_data <= FLAGS_OFFSET_IN(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when TTL_S => fpf_data <= TTL_IN; - when PROTO => fpf_data <= PROTOCOL_IN; - when HEADER_CS => fpf_data <= x"ff" - ip_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when SRC_IP_ADDR => fpf_data <= SRC_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when DEST_IP_ADDR => fpf_data <= DEST_IP_ADDRESS_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when SRC_PORT => fpf_data <= SRC_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when DEST_PORT => fpf_data <= DEST_UDP_PORT_IN(headers_int_counter * 8 + 7 downto headers_int_counter * 8); - when UDP_LENGTH => fpf_data <= udp_size(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); - when SAVE_DATA => fpf_data <= DATA_IN; - when CLEANUP => fpf_data <= x"ab"; - when DELAY => fpf_data <= x"ac"; - when others => fpf_data <= x"00"; - end case; -end process fpfDataProc; - - -readyFramesCtrProc: process( CLK ) -begin - if rising_edge(CLK) then - if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 - ready_frames_ctr <= (others => '0'); - elsif (constructCurrentState = CLEANUP) then - ready_frames_ctr <= ready_frames_ctr + 1; - end if; - end if; -end process readyFramesCtrProc; - -fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10 - -FINAL_PACKET_FIFO: fifo_4096x9 -port map( - Data(7 downto 0) => fpf_data, - Data(8) => END_OF_DATA_IN, - WrClock => CLK, - RdClock => RD_CLK, - WrEn => fpf_wr_en, - RdEn => FT_TX_RD_EN_IN, - Reset => fpf_reset, - RPReset => fpf_reset, - Q => fpf_q, - Empty => fpf_empty, - Full => fpf_full -); - -transferToRdClock : signal_sync - generic map( - DEPTH => 2, - WIDTH => 16 - ) - port map( - RESET => RESET, - D_IN => ready_frames_ctr, - CLK0 => RD_CLK, --CLK, - CLK1 => RD_CLK, - D_OUT => ready_frames_ctr_q - ); - -transmitMachineProc: process( RD_CLK ) -begin - if( rising_edge(RD_CLK) ) then - if( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10 - transmitCurrentState <= T_IDLE; - else - transmitCurrentState <= transmitNextState; - end if; - end if; -end process transmitMachineProc; - -transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, ready_frames_ctr_q, FT_TX_DISCFRM_IN ) -begin - case transmitCurrentState is - when T_IDLE => - bsm_trans <= x"0"; - if( (sent_frames_ctr /= ready_frames_ctr_q) ) then - transmitNextState <= T_LOAD; - else - transmitNextState <= T_IDLE; - end if; - when T_LOAD => - bsm_trans <= x"1"; - if( fpf_q(8) = '1' ) then - transmitNextState <= T_TRANSMIT; - else - transmitNextState <= T_LOAD; - end if; - when T_TRANSMIT => - bsm_trans <= x"2"; - -- gk 03.08.10 - if ((LINK_OK_IN = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then - transmitNextState <= T_CLEANUP; - elsif (LINK_OK_IN = '0') then - transmitNextState <= T_PAUSE; - else - transmitNextState <= T_TRANSMIT; - end if; - when T_PAUSE => - transmitNextState <= T_CLEANUP; - when T_CLEANUP => - bsm_trans <= x"3"; - transmitNextState <= T_IDLE; - when others => - bsm_trans <= x"f"; - transmitNextState <= T_IDLE; - end case; -end process transmitMachine; - - - -sopProc: process( RD_CLK ) -begin - if rising_edge(RD_CLK) then - if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10 - ft_sop <= '0'; - elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then - ft_sop <= '1'; - else - ft_sop <= '0'; - end if; - end if; -end process sopProc; - -sentFramesCtrProc: process( RD_CLK ) -begin - if rising_edge(RD_CLK) then - if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10 - sent_frames_ctr <= (others => '0'); - -- gk 03.08.10 - elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then - sent_frames_ctr <= sent_frames_ctr + 1; - end if; - end if; -end process sentFramesCtrProc; - -debug(7 downto 0) <= bsm_constr; -debug(11 downto 8) <= bsm_trans; -debug(27 downto 12) <= sent_frames_ctr; -debug(28) <= fpf_full; -debug(29) <= fpf_empty; -debug(30) <= ready; -debug(31) <= headers_ready; -debug(47 downto 32) <= ready_frames_ctr_q; -debug(48) <= '0'; - - --- Output -FT_DATA_OUT <= fpf_q; -FT_TX_EMPTY_OUT <= fpf_empty; -FT_START_OF_PACKET_OUT <= ft_sop; -READY_OUT <= ready; -HEADERS_READY_OUT <= headers_ready; - -BSM_CONSTR_OUT <= bsm_constr; -BSM_TRANS_OUT <= bsm_trans; -DEBUG_OUT <= debug; - -end trb_net16_gbe_frame_constr; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd deleted file mode 100755 index ca58728..0000000 --- a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd +++ /dev/null @@ -1,588 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_frame_trans is -port ( - CLK : in std_logic; - RESET : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - TX_MAC_CLK : in std_logic; - TX_EMPTY_IN : in std_logic; - START_OF_PACKET_IN : in std_logic; - DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC - -- NEW PORTS - HADDR_OUT : out std_logic_vector(7 downto 0); - HDATA_OUT : out std_logic_vector(7 downto 0); - HCS_OUT : out std_logic; - HWRITE_OUT : out std_logic; - HREAD_OUT : out std_logic; - HREADY_IN : in std_logic; - HDATA_EN_IN : in std_logic; - TX_FIFOAVAIL_OUT : out std_logic; - TX_FIFOEOF_OUT : out std_logic; - TX_FIFOEMPTY_OUT : out std_logic; - TX_DONE_IN : in std_logic; - TX_DISCFRM_IN : in std_logic; - -- Debug - BSM_INIT_OUT : out std_logic_vector(3 downto 0); - BSM_MAC_OUT : out std_logic_vector(3 downto 0); - BSM_TRANS_OUT : out std_logic_vector(3 downto 0); - DBG_RD_DONE_OUT : out std_logic; - DBG_INIT_DONE_OUT : out std_logic; - DBG_ENABLED_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_frame_trans; - --- FifoRd ?!? - -architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of trb_net16_gbe_frame_trans : architecture is "GBE_frame_group"; - -component mac_init_mem is -port ( - Address : in std_logic_vector(5 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0) -); -end component; - -attribute syn_encoding : string; - -type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED); -signal macInitState, macInitNextState : macInitStates; -attribute syn_encoding of macInitState: signal is "safe,gray"; -signal bsm_init : std_logic_vector(3 downto 0); - -type macStates is (M_RESETING, M_IDLE, M_INIT); -signal macCurrentState, macNextState : macStates; -signal bsm_mac : std_logic_vector(3 downto 0); - -type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO); -signal transmitCurrentState, transmitNextState : transmitStates; -attribute syn_encoding of transmitCurrentState: signal is "safe,gray"; -signal bsm_trans : std_logic_vector(3 downto 0); - -signal tx_fifoavail_i : std_logic; -signal tx_fifoeof_i : std_logic; - --- host interface signals -signal hcs_n_i : std_logic; -signal hwrite_n_i : std_logic; -signal hread_n_i : std_logic; - --- MAC INITIALIZATION signals -signal macInitMemAddr : std_logic_vector(5 downto 0); -signal macInitMemQ : std_logic_vector(7 downto 0); -signal macInitMemEn : std_logic; -signal reading_done : std_logic; -signal init_done : std_logic; -signal enabled : std_logic; -signal addrSig : std_logic_vector(5 downto 0); -signal addr2 : std_logic_vector(5 downto 0); -signal resetAddr : std_logic; - -signal FifoEmpty : std_logic; -signal debug : std_logic_vector(63 downto 0); - -begin - --- Fakes -debug <= (others => '0'); - - -TransmitStateMachineProc : process (TX_MAC_CLK) -begin - if rising_edge(TX_MAC_CLK) then - if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 - transmitCurrentState <= T_IDLE; - else - transmitCurrentState <= transmitNextState; - end if; - end if; -end process TransmitStatemachineProc; - -TransmitStateMachine : process (transmitCurrentState, macCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN) -begin - case transmitCurrentState is - when T_IDLE => - bsm_trans <= x"0"; - if ((START_OF_PACKET_IN = '1') and (macCurrentState = M_IDLE)) then - transmitNextState <= T_TRANSMIT; - else - transmitNextState <= T_IDLE; - end if; - when T_TRANSMIT => - bsm_trans <= x"1"; - if (DATA_ENDFLAG_IN = '1') then - transmitNextState <= T_WAITFORFIFO; - else - transmitNextState <= T_TRANSMIT; - end if; - when T_WAITFORFIFO => - bsm_trans <= x"2"; - if (TX_DONE_IN = '1') then --or (TX_DISCFRM_IN = '1') then - transmitNextState <= T_IDLE; - else - transmitNextState <= T_WAITFORFIFO; - end if; - when others => - bsm_trans <= x"f"; - transmitNextState <= T_IDLE; - end case; -end process TransmitStateMachine; - -FifoAvailProc : process (TX_MAC_CLK) -begin - if rising_edge(TX_MAC_CLK) then - if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 - tx_fifoavail_i <= '0'; - elsif (transmitCurrentState = T_TRANSMIT) then - tx_fifoavail_i <= '1'; - else - tx_fifoavail_i <= '0'; - end if; - end if; -end process FifoAvailProc; - -FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, RESET) -begin - if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 - FifoEmpty <= '1'; - elsif (transmitCurrentState = T_WAITFORFIFO) then - FifoEmpty <= '1'; - elsif (transmitCurrentState = T_TRANSMIT) then - FifoEmpty <= TX_EMPTY_IN; - elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then - FifoEmpty <= '0'; - else - FifoEmpty <= '1'; - end if; -end process FifoEmptyProc; - -tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) - else '0'; - --- main MAC state machine -MacStateMachineProc : process (CLK) -begin - if rising_edge(CLK) then - if RESET = '1' then - macCurrentState <= M_RESETING; - else - macCurrentState <= macNextState; - end if; - end if; -end process MacStateMachineProc; - -MacStatesMachine: process(macCurrentState, reading_done) -begin - case macCurrentState is - when M_RESETING => - bsm_mac <= x"0"; - macNextState <= M_INIT; - when M_IDLE => - bsm_mac <= x"1"; - macNextState <= M_IDLE; - when M_INIT => - bsm_mac <= x"2"; - if (reading_done = '1') then - macNextState <= M_IDLE; - else - macNextState <= M_INIT; - end if; - when others => - bsm_mac <= x"f"; - macNextState <= M_RESETING; - end case; -end process MacStatesMachine; - - ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- --- MAC initialization statemachine, memory and address counters ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- - --- state machine used to initialize MAC registers with data saved in macInitDataInv2.mem via macInitMem -MacInitStateMachineProc : process (CLK) -begin - if rising_edge(CLK) then - if RESET = '1' then - macInitState <= I_IDLE; - else - macInitState <= macInitNextState; - end if; - end if; -end process MacInitStateMachineProc; - -MacInitStateMachine : process (macInitState, macCurrentState, init_done, HREADY_IN, reading_done, HDATA_EN_IN, enabled) -begin - case macInitState is - when I_IDLE => - bsm_init <= x"0"; - if (macCurrentState = M_INIT) then - macInitNextState <= I_WRITE; - else - macInitNextState <= I_IDLE; - end if; - when I_INCRADDRESS => - bsm_init <= x"1"; - if ((init_done = '0') and (enabled = '0') and (reading_done = '0')) then -- write to regs 2 and up - macInitNextState <= I_PAUSE; - elsif ((init_done = '1') and (enabled = '0') and (reading_done = '0')) then -- write to regs 0 and 1 - macInitNextState <= I_PAUSE3; - elsif ((init_done = '1') and (enabled = '1') and (reading_done = '0')) then -- read all regs to fifo - macInitNextState <= I_PAUSE2; - else - macInitNextState <= I_ENDED; - end if; - when I_PAUSE => - bsm_init <= x"2"; - if (HREADY_IN = '1') then - macInitNextState <= I_WRITE; - else - macInitNextState <= I_PAUSE; - end if; - when I_WRITE => - bsm_init <= x"3"; - if (HREADY_IN = '0') then - macInitNextState <= I_INCRADDRESS; - else - macInitNextState <= I_WRITE; - end if; - when I_PAUSE2 => - bsm_init <= x"4"; - if (HREADY_IN = '1') then - macInitNextState <= I_READ; - else - macInitNextState <= I_PAUSE2; - end if; - when I_READ => - bsm_init <= x"5"; - if (HDATA_EN_IN = '0') then - macInitNextState <= I_INCRADDRESS; - else - macInitNextState <= I_READ; - end if; - when I_PAUSE3 => - bsm_init <= x"6"; - if (HREADY_IN = '1') then - macInitNextState <= I_WRITE; - else - macInitNextState <= I_PAUSE3; - end if; - when I_ENDED => - bsm_init <= x"7"; - macInitNextState <= I_ENDED; - when others => - bsm_init <= x"f"; - macInitNextState <= I_IDLE; - end case; -end process MacInitStateMachine; - -addrSig <= addr2 when ((reading_done = '0') and (init_done = '1') and (enabled = '1')) - else macInitMemAddr; - --- initialization ROM -MacInitMemory : mac_init_mem -port map ( - Address => macInitMemAddr, - OutClock => CLK, - OutClockEn => macInitMemEn, - Reset => RESET, - Q => macInitMemQ -); - --- MAC ready signal (?) -enabledProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - enabled <= '0'; - elsif ((reading_done = '0') and (init_done = '1') and (macInitMemAddr = "000010")) then -- write only to the first register (mode) - enabled <= '1'; - elsif (macInitState = I_IDLE) then - enabled <= '0'; - end if; - end if; -end process enabledProc; - -add2 : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - addr2 <= "111111"; - elsif ((macInitState = I_INCRADDRESS) and (init_done = '1') and (enabled = '1')) then - addr2 <= addr2 + "1"; - elsif (macInitState = I_IDLE) then - addr2 <= "111111"; - end if; - end if; -end process add2; - -readingDoneProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - reading_done <= '0'; - elsif (macInitState = I_IDLE) then - reading_done <= '0'; - elsif (addr2 = "110101") then -- read all registers - reading_done <= '1'; - end if; - end if; -end process readingDoneProc; - -initDoneProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - init_done <= '0'; - elsif (macInitState = I_IDLE) then - init_done <= '0'; - elsif (macInitMemAddr = "110101") then -- write to all registers - init_done <= '1'; - end if; - end if; -end process initDoneProc; - --- HWRITE signal (registered) -hwriteProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - hwrite_n_i <= '1'; - elsif ((macInitState = I_WRITE) and (HREADY_IN = '1')) then - hwrite_n_i <= '0'; - else - hwrite_n_i <= '1'; - end if; - end if; -end process hwriteProc; - --- HREAD signal (registered) -hreadProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - hread_n_i <= '1'; - elsif ((macInitState = I_READ) and (HREADY_IN = '1')) then - hread_n_i <= '0'; - else - hread_n_i <= '1'; - end if; - end if; -end process hreadProc; - --- HCS signal (registered) -hcsProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - hcs_n_i <= '1'; - elsif ((macInitState = I_WRITE) and (HREADY_IN = '1')) then - hcs_n_i <= '0'; - elsif ((macInitState = I_READ) and (HREADY_IN = '1')) then - hcs_n_i <= '0'; - else - hcs_n_i <= '1'; - end if; - end if; -end process hcsProc; - --- address lines for the initialization memory -macInitMemAddrProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - macInitMemAddr <= "000010"; - elsif (resetAddr = '1') then - macInitMemAddr <= "000000"; - else - if (macInitState = I_INCRADDRESS) then - macInitMemAddr <= macInitMemAddr + "1"; - elsif (macInitState = I_IDLE) then - macInitMemAddr <= "000010"; - end if; - end if; - end if; -end process macInitMemAddrProc; - --- address counter reset signal (registered) -resetAddrProc : process (CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - resetAddr <= '0'; - elsif (macInitState = I_IDLE) then - resetAddr <= '0'; - elsif (macInitMemAddr = "110101") then - resetAddr <= '1'; - elsif (macInitState = I_PAUSE3) then - resetAddr <= '0'; - end if; - end if; -end process resetAddrProc; - -macInitMemEn <= '1' when (macCurrentState = M_INIT) - else '0'; - - - --- Outputs -HADDR_OUT <= b"00" & addrSig; -HDATA_OUT <= macInitMemQ; -HCS_OUT <= hcs_n_i; -HWRITE_OUT <= hwrite_n_i; -HREAD_OUT <= hread_n_i; -TX_FIFOAVAIL_OUT <= tx_fifoavail_i; -TX_FIFOEOF_OUT <= tx_fifoeof_i; -TX_FIFOEMPTY_OUT <= FifoEmpty; - -BSM_INIT_OUT <= bsm_init; -BSM_MAC_OUT <= bsm_mac; -BSM_TRANS_OUT <= bsm_trans; -DBG_RD_DONE_OUT <= reading_done; -DBG_INIT_DONE_OUT <= init_done; -DBG_ENABLED_OUT <= enabled; -DEBUG_OUT <= debug; - -end trb_net16_gbe_frame_trans; - - ---MAC : tsmac3 ---port map( --- -------------------------------------------------------------------------- --- --------------- clock, reset, clock enable ------------------------------- --- hclk => CLK, -- (in) host clock (100MHz) --- txmac_clk => TX_MAC_CLK, -- (in) GbE clock (125MHz) --- rxmac_clk => '0', -- (in) not used (no receiving on GbE) --- reset_n => GSR_N, -- (in) global set/reset --- txmac_clk_en => TSM_TX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation --- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- (in) from SGMII core, '1' for 1GbE operation --- -------------------------------------------------------------------------- --- --------------- SGMII receive interface ---------------------------------- --- rxd => x"00", -- (in) receive data from SGMII core --- rx_dv => '0', -- (in) data valid from SGMII core --- rx_er => '0', -- (in) receive data error --- col => TSM_COL_IN, -- (in) collision from SGMII core --- crs => TSM_CRS_IN, -- (in) carrier sense from SGMII core --- -------------------------------------------------------------------------- --- --------------- SGMII transmit interface --------------------------------- --- txd => CH_TXD_OUT, -- (out) transmit data to SGMII core --- tx_en => CH_TX_EN_OUT, -- (out) transmit enable --- tx_er => CH_TX_ER_OUT, -- (out) transmit error --- -------------------------------------------------------------------------- --- --------------- CPU configuration interface ------------------------------ --- haddr => haddr, -- (in) host address bus for configuration --- hdatain => hdataout, -- (in) host data bus for write accesses --- hcs_n => hcs, -- (in) host chip select signal --- hwrite_n => hwrite, -- (in) host write strobe signal --- hread_n => hread, -- (in) host read strobe signal --- hdataout => hdatain, -- (out) host data bus for read accesses --- hdataout_en_n => hdataout_en, -- (out) read data valid signal --- hready_n => hready, -- (out) data acknowledge signal --- cpu_if_gbit_en => open, -- (out) status bit --- -------------------------------------------------------------------------- --- --------------- Transmit FIFO interface ---------------------------------- --- tx_fifodata => ft_data(7 downto 0), -- (in) transmit FIFO data bus --- tx_fifoavail => mac_fifoavail, -- (in) transmit FIFO data available --- tx_fifoeof => mac_fifoeof, -- (in) transmit FIFO end of frame --- tx_fifoempty => mac_fifoempty, -- (in) transmit FIFO empty --- tx_macread => mac_tx_rd_en, -- (out) transmit FIFO read --- tx_done => mac_tx_done, -- (out) transmit done (without errors) --- tx_sndpaustim => x"0000", -- (in) PAUSE frame timer --- tx_sndpausreq => '0', -- (in) PAUSE frame request --- tx_fifoctrl => '0', -- (in) FIFO control frame ('0' = data, '1' = control) --- tx_discfrm => open, -- (out) discard frame --- tx_staten => open, -- (out) transmit statistics vector enable --- tx_statvec => open, -- (out) transmit statistics vector --- -------------------------------------------------------------------------- --- --------------- Receive FIFO interface ----------------------------------- --- rx_dbout => open, -- (out) receive FIFO data output --- rx_fifo_full => '0', -- (in) receive FIFO full --- ignore_pkt => '0', -- (in) ignore next packet --- rx_fifo_error => open, -- (out) receive FIFO error --- rx_stat_vector => open, -- (out) receive statistics vector --- rx_stat_en => open, -- (out) receive statistics vector enable --- rx_write => open, -- (out) receive FIFO write --- rx_eof => open, -- (out) end of frame --- rx_error => open -- (out) receive packet error ---); - - - - - - ---MAC : tsmac3 ---port map( ------------------ clock and reset port declarations ------------------ --- hclk => LVDS_CLK_200P, --- txmac_clk => TX_MAC_CLK, --- rxmac_clk => '0', --- reset_n => GSR_N, -- done --- txmac_clk_en => TSM_TX_CLK_EN_IN, -- done --- rxmac_clk_en => TSM_RX_CLK_EN_IN, -- done ---------------------- Input signals to the GMII ---------------- NOT USED --- rxd => x"00", --- rx_dv => '0', --- rx_er => '0', --- col => TSM_COL_IN, -- done --- crs => TSM_CRS_IN, -- done --- -------------------- Input signals to the CPU I/F ------------------- --- haddr(5 downto 0) => addrSig, -- done --- haddr(7 downto 6) => "00", --- hdatain => macInitMemQ, -- done --- hcs_n => hcs_n_i, -- done --- hwrite_n => hwrite_n_i, -- done --- hread_n => hread_n_i, -- done ------------------- Input signals to the Tx MAC FIFO I/F --------------- --- tx_fifodata => DATA_IN(7 downto 0), -- done --- tx_fifoavail => tx_fifoavail_i, -- done --- tx_fifoeof => tx_fifoeof_i, -- done --- tx_fifoempty => FifoEmpty, -- done --- tx_sndpaustim => x"0000", --- tx_sndpausreq => '0', --- tx_fifoctrl => '0', -- always data frame ------------------- Input signals to the Rx MAC FIFO I/F --------------- --- rx_fifo_full => '0', --- ignore_pkt => '0', ----------------------- Output signals from the GMII ----------------------- --- txd => CH_TXD_OUT, -- done --- tx_en => CH_TX_EN_OUT, -- done --- tx_er => CH_TX_ER_OUT, -- done ----------------------- Output signals from the CPU I/F ------------------- --- hdataout => hdataout_i, -- done --- hdataout_en_n => hdataout_en_n_i, -- done --- hready_n => hready_n_i, -- done --- cpu_if_gbit_en => gbe_enabled, -- done ------------------- Output signals from the Tx MAC FIFO I/F --------------- --- tx_macread => FifoRd, -- done --- tx_discfrm => tx_discfrm_i, -- not used --- tx_staten => tx_staten_i, -- done --- tx_statvec => tx_statvec_i, -- done --- tx_done => tx_done_i, -- done ------------------- Output signals from the Rx MAC FIFO I/F --------------- --- rx_fifo_error => open, --- rx_stat_vector => open, --- rx_dbout => open, --- rx_write => open, --- rx_stat_en => open, --- rx_eof => rx_eof_i, -- done --- rx_error => rx_error_i -- done ---); diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd deleted file mode 100755 index c37ad00..0000000 --- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd +++ /dev/null @@ -1,1045 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -entity trb_net16_gbe_packet_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_DATA_IN : in std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_PADDING_IN : in std_logic; -- gk 29.03.10 - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP - PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 - MULT_EVT_ENABLE_IN : in std_logic; -- gk 08.11.10 - PC_END_OF_SUB_IN : in std_logic; -- gk 08.10.11 - -- FrameConstructor ports - FC_WR_EN_OUT : out std_logic; - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_H_READY_IN : in std_logic; - FC_READY_IN : in std_logic; - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end trb_net16_gbe_packet_constr; - -architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_packet_constr_group"; - -component fifo_64kx9 -port ( - Data : in std_logic_vector(8 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(8 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - --- FIFO for SubEventHeader information --- gk 06.12.10 component fifo_2048x8 is ---component fifo_16kx8 is -component fifo_2048x8 is -port ( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -signal df_wr_en : std_logic; -signal df_rd_en : std_logic; -signal df_q : std_logic_vector(7 downto 0); -signal df_q_reg : std_logic_vector(7 downto 0); -signal df_empty : std_logic; -signal df_full : std_logic; - -signal fc_data : std_logic_vector(7 downto 0); -signal fc_wr_en : std_logic; -signal fc_sod : std_logic; -signal fc_eod : std_logic; -signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter! -signal fc_flags_offset : std_logic_vector(15 downto 0); - -signal shf_data : std_logic_vector(7 downto 0); -signal shf_wr_en : std_logic; -signal shf_rd_en : std_logic; -signal shf_q : std_logic_vector(7 downto 0); -signal shf_empty : std_logic; -signal shf_full : std_logic; - -type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD); -signal constructCurrentState, constructNextState : constructStates; -signal constr_state : std_logic_vector(3 downto 0); -signal all_int_ctr : integer range 0 to 31; -signal all_ctr : std_logic_vector(4 downto 0); - -type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM); -signal saveSubCurrentState, saveSubNextState : saveSubStates; -signal save_state : std_logic_vector(3 downto 0); -signal sub_int_ctr : integer range 0 to 31; -signal sub_ctr : std_logic_vector(4 downto 0); -signal my_int_ctr : integer range 0 to 3; -signal my_ctr : std_logic_vector(1 downto 0); - -type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY); -signal loadCurrentState, loadNextState: loadStates; -signal load_state : std_logic_vector(3 downto 0); - -signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination -signal queue_size_temp : std_logic_vector(31 downto 0); -signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid -signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame -signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf -signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted -signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent -signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet -signal size_left : std_logic_vector(31 downto 0); -signal fc_ip_size : std_logic_vector(15 downto 0); -signal fc_udp_size : std_logic_vector(15 downto 0); -signal max_frame_size : std_logic_vector(15 downto 0); -signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term -signal debug : std_logic_vector(63 downto 0); -signal pc_ready : std_logic; - -signal pc_sub_size : std_logic_vector(31 downto 0); -signal pc_trig_nr : std_logic_vector(31 downto 0); -signal rst_after_sub_comb : std_logic; -- gk 08.04.10 -signal rst_after_sub : std_logic; -- gk 08.04.10 -signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10 -signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10 -signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10 - --- gk 26.07.10 -signal load_eod : std_logic; -signal load_eod_q : std_logic; - --- gk 08.11.11 -signal df_eod : std_logic; - --- gk 04.12.10 -signal first_sub_in_multi : std_logic; -signal from_divide_state : std_logic; -signal disable_prep : std_logic; - -begin - --- Fakes ---debug <= (others => '0'); - -my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order -load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10 - -all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging -sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging -my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging - -max_frame_size <= PC_MAX_FRAME_SIZE_IN; - --- Ready signal for PacketConstructor -pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0'; - --- store event information on Start_of_Subevent -THE_EVT_INFO_STORE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if (RESET = '1') then -- gk 31.05.10 - pc_sub_size <= (others => '0'); - pc_trig_nr <= (others => '0'); - elsif( PC_START_OF_SUB_IN = '1' ) then - pc_sub_size <= PC_SUB_SIZE_IN; - pc_trig_nr <= PC_TRIG_NR_IN; - end if; - end if; -end process; - --- Data FIFO for incoming packet data from IPU buffer --- gk 26.07.10 -DATA_FIFO : fifo_64kx9 -port map( - Data(7 downto 0) => PC_DATA_IN, - Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 08.11.10 - WrClock => CLK, - RdClock => CLK, - WrEn => df_wr_en, - RdEn => df_rd_en, - Reset => RESET, - RPReset => RESET, - Q(7 downto 0) => df_q, - Q(8) => load_eod, - Empty => df_empty, - Full => df_full -); - --- gk 08.11.10 -df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1')) - or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1')) - else '0'; - -LOAD_EOD_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - load_eod_q <= '0'; - else - load_eod_q <= load_eod; - end if; - end if; -end process LOAD_EOD_PROC; - --- Write enable for the data FIFO --- !!!combinatorial signal!!! --- could be avoided as IPU2GBE does only send data in case of PC_READY. -df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) - else '0'; - --- Output register for data FIFO -dfQProc : process(CLK) -begin - if rising_edge(CLK) then - df_q_reg <= df_q; - end if; -end process dfQProc; - --- Construction state machine -constructMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - constructCurrentState <= CIDLE; - else - constructCurrentState <= constructNextState; - end if; - end if; -end process constructMachineProc; - -constructMachine : process(constructCurrentState, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr) -begin - case constructCurrentState is - when CIDLE => - constr_state <= x"0"; - --if( PC_WR_EN_IN = '1' ) then - -- gk 04.12.10 - if (PC_START_OF_SUB_IN = '1') then - constructNextState <= SAVE_DATA; - else - constructNextState <= CIDLE; - end if; - when SAVE_DATA => - constr_state <= x"1"; - if( PC_END_OF_DATA_IN = '1' ) then - constructNextState <= WAIT_FOR_LOAD; - else - constructNextState <= SAVE_DATA; - end if; - when WAIT_FOR_LOAD => - constr_state <= x"2"; - if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted - constructNextState <= CIDLE; - else - constructNextState <= WAIT_FOR_LOAD; - end if; - when others => - constr_state <= x"f"; - constructNextState <= CIDLE; - end case; -end process constructMachine; - ---*********************** --- SIZE COUNTERS FOR SAVING SIDE ---*********************** - --- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size --- that's why they are removed if pc_padding flag is asserted -sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0') - else (x"c" + pc_sub_size); -- subevent headers + data - --- BUG HERE BUG HERE BUG HERE BUG HERE --- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents -queueSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = CLEANUP) then - queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination - elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then - queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers - end if; - end if; -end process queueSizeProc; - ---*********************** --- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION ---*********************** - -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loadCurrentState <= LIDLE; - else - loadCurrentState <= loadNextState; - end if; - end if; -end process loadMachineProc; - -loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty, - sub_bytes_loaded, sub_size_loaded, size_left, FC_H_READY_IN, max_frame_size, - bytes_loaded, divide_position, PC_DELAY_IN, delay_ctr, load_eod_q) -begin - case loadCurrentState is - when LIDLE => - load_state <= x"0"; - if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then - loadNextState <= WAIT_FOR_FC; - else - loadNextState <= LIDLE; - end if; - when WAIT_FOR_FC => - load_state <= x"1"; - if (FC_H_READY_IN = '1') then - loadNextState <= PUT_Q_LEN; - else - loadNextState <= WAIT_FOR_FC; - end if; - when PUT_Q_LEN => - load_state <= x"2"; - if (all_int_ctr = 3) then - loadNextState <= PUT_Q_DEC; - else - loadNextState <= PUT_Q_LEN; - end if; - when PUT_Q_DEC => - load_state <= x"3"; - if (all_int_ctr = 3) then - loadNextState <= LOAD_SUB; - else - loadNextState <= PUT_Q_DEC; - end if; - when LOAD_SUB => - load_state <= x"4"; - if (bytes_loaded = max_frame_size - 1) then - loadNextState <= DIVIDE; - elsif (all_int_ctr = 15) then - loadNextState <= PREP_DATA; - else - loadNextState <= LOAD_SUB; - end if; - when PREP_DATA => - load_state <= x"5"; - loadNextState <= LOAD_DATA; --- when LOAD_DATA => --- load_state <= x"6"; --- if (bytes_loaded = max_frame_size - 1) then --- loadNextState <= DIVIDE; --- -- gk 26.07.10 --- -- close packet after one event loaded --- elsif (load_eod_q = '1') then --- loadNextState <= LOAD_TERM; --- -- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded --- -- if (size_left = x"00000021") then -- and there is no more data, only termination left --- -- -- gk 21.07.10 --- -- if (PC_SKIP_TERM_IN = '0') then --- -- loadNextState <= LOAD_TERM; -- add termination and close packet --- -- else --- -- loadNextState <= CLEANUP; --- -- end if; --- -- else -- there is more data in fifo --- -- loadNextState <= LOAD_SUB; -- add another subevent --- -- end if; --- else --- loadNextState <= LOAD_DATA; --- end if; - -- gk 04.12.10 - when LOAD_DATA => - load_state <= x"6"; - if (bytes_loaded = max_frame_size - 1) then - loadNextState <= DIVIDE; - -- gk 07.10.10 - elsif (load_eod_q = '1') then - if (MULT_EVT_ENABLE_IN = '1') then - if (size_left < x"0000_0030") then - loadNextState <= LOAD_TERM; - else - loadNextState <= LOAD_SUB; - end if; - else - loadNextState <= LOAD_TERM; - end if; - else - loadNextState <= LOAD_DATA; - end if; - when DIVIDE => - load_state <= x"7"; - if (FC_H_READY_IN = '1') then - if (divide_position = "00") then - loadNextState <= PREP_DATA; - elsif (divide_position = "01") then - loadNextState <= LOAD_SUB; - else - loadNextState <= LOAD_TERM; - end if; - else - loadNextState <= DIVIDE; - end if; - when LOAD_TERM => - load_state <= x"8"; - if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then - loadNextState <= DIVIDE; - elsif (all_int_ctr = 31) then - loadNextState <= CLEANUP; - else - loadNextState <= LOAD_TERM; - end if; - -- gk 28.04.10 - when CLEANUP => - load_state <= x"9"; - if (PC_DELAY_IN = x"0000_0000") then - loadNextState <= LIDLE; - else - loadNextState <= DELAY; - end if; - -- gk 28.04.10 - when DELAY => - load_state <= x"a"; - if (delay_ctr = x"0000_0000") then - loadNextState <= LIDLE; - else - loadNextState <= DELAY; - end if; - when others => - load_state <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- gk 04.12.10 -firstSubInMultiProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LOAD_TERM) then - first_sub_in_multi <= '1'; - elsif (loadCurrentState = LOAD_DATA) then - first_sub_in_multi <= '0'; - end if; - end if; -end process; - --- gk 04.12.10 -fromDivideStateProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - from_divide_state <= '0'; - elsif (loadCurrentState = DIVIDE) then - from_divide_state <= '1'; - elsif (loadCurrentState = PREP_DATA) then - from_divide_state <= '0'; - end if; - end if; -end process fromDivideStateProc; - -dividePositionProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - divide_position <= "00"; - elsif (bytes_loaded = max_frame_size - 1) then - if (loadCurrentState = LIDLE) then - divide_position <= "00"; - disable_prep <= '0'; -- gk 05.12.10 - elsif (loadCurrentState = LOAD_DATA) then - -- gk 05.12.10 - -- gk 26.07.10 - if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term - divide_position <= "11"; - disable_prep <= '0'; -- gk 05.12.10 - elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then - if (size_left > x"0000_0028") then - divide_position <= "01"; - disable_prep <= '0'; -- gk 05.12.10 - else - divide_position <= "11"; - disable_prep <= '0'; -- gk 05.12.10 - end if; - else - divide_position <= "00"; -- still data loaded divide on data - disable_prep <= '1'; -- gk 05.12.10 - end if; - elsif (loadCurrentState = LOAD_SUB) then - if (all_int_ctr = 15) then - divide_position <= "00"; - disable_prep <= '1'; -- gk 05.12.10 - else - divide_position <= "01"; - disable_prep <= '0'; -- gk 05.12.10 - end if; - elsif (loadCurrentState = LOAD_TERM) then - divide_position <= "11"; - disable_prep <= '0'; -- gk 05.12.10 - end if; - elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep - disable_prep <= '0'; - end if; - end if; -end process dividePositionProc; - -allIntCtrProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then -- gk 31.05.10 - all_int_ctr <= 0; - else - case loadCurrentState is - - when LIDLE => all_int_ctr <= 0; - - when WAIT_FOR_FC => all_int_ctr <= 0; - - when PUT_Q_LEN => - if (all_int_ctr = 3) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when PUT_Q_DEC => - if (all_int_ctr = 3) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when LOAD_SUB => - if (all_int_ctr = 15) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when LOAD_DATA => all_int_ctr <= 0; - - when LOAD_TERM => - if (all_int_ctr = 31) then - all_int_ctr <= 0; - else - all_int_ctr <= all_int_ctr + 1; - end if; - - when DIVIDE => null; --all_int_ctr <= all_int_ctr; - - when CLEANUP => all_int_ctr <= 0; - - when PREP_DATA => all_int_ctr <= 0; - - when DELAY => all_int_ctr <= 0; - end case; - end if; - end if; -end process allIntCtrProc; - -dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, - sub_size_loaded, all_int_ctr, RESET, load_eod, load_eod_q) -begin - if (RESET = '1') then -- gk 31.05.10 - df_rd_en <= '0'; - elsif (loadCurrentState = LOAD_DATA) then --- if (bytes_loaded >= max_frame_size - x"1") then --- df_rd_en <= '0'; --- elsif (sub_bytes_loaded >= sub_size_loaded) then --- df_rd_en <= '0'; - if (bytes_loaded = max_frame_size - x"1") then - df_rd_en <= '0'; - -- gk 26.07.10 - --elsif (load_eod = '1') or (load_eod_q = '1') then - elsif (load_eod_q = '1') then - df_rd_en <= '0'; --- elsif (sub_bytes_loaded = sub_size_loaded) then --- df_rd_en <= '0'; - else - df_rd_en <= '1'; - end if; - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then - df_rd_en <= '1'; - elsif (loadCurrentState = PREP_DATA) then - df_rd_en <= '1'; - else - df_rd_en <= '0'; - end if; -end process dfRdEnProc; - -shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET) -begin - if (RESET = '1') then -- gk 31.05.10 - shf_rd_en <= '0'; - elsif (loadCurrentState = LOAD_SUB) then - shf_rd_en <= '1'; - elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then - shf_rd_en <= '1'; - elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then - shf_rd_en <= '1'; - else - shf_rd_en <= '0'; - end if; -end process shfRdEnProc; - - -fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep) -begin - if (RESET = '1') then -- gk 31.05.10 - fc_wr_en <= '0'; - elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then - fc_wr_en <= '1'; - elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then - fc_wr_en <= '1'; - -- gk 04.12.10 - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then - fc_wr_en <= '1'; - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then - fc_wr_en <= '1'; - else - fc_wr_en <= '0'; - end if; -end process fcWrEnProc; - --- was all_int_ctr -fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr) -begin - case loadCurrentState is - when LIDLE => fc_data <= x"af"; - when WAIT_FOR_FC => fc_data <= x"bf"; - -- gk 08.04.10 my_int_ctr changed to load_int_ctr - when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8); - when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8); - when LOAD_SUB => fc_data <= shf_q; - when PREP_DATA => fc_data <= df_q_reg; - when LOAD_DATA => fc_data <= df_q_reg; - when LOAD_TERM => fc_data <= shf_q; - when DIVIDE => fc_data <= x"cf"; - when CLEANUP => fc_data <= x"df"; - when others => fc_data <= x"00"; - end case; -end process fcDataProc; - --- delay counters --- gk 28.04.10 -DELAY_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (loadCurrentState = LIDLE)) then - delay_ctr <= PC_DELAY_IN; - elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then - delay_ctr <= delay_ctr - x"1"; - end if; - end if; -end process DELAY_CTR_PROC; - --- gk 28.04.10 -TICKS_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then - ticks_ctr <= x"00"; - elsif (loadCurrentState = DELAY) then - ticks_ctr <= ticks_ctr + x"1"; - end if; - end if; -end process TICKS_CTR_PROC; - - ---*********************** --- SIZE COUNTERS FOR LOADING SIDE ---*********************** - -queue_size_temp <= queue_size - x"20"; -- size of data without termination - --- gk 08.04.10 -rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or - ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) - else '0'; - --- gk 08.04.10 -RST_AFTER_SUB_PROC : process(CLK) -begin - if(rising_edge(CLK)) then - if(RESET = '1') then - rst_after_sub <= '0'; - else - rst_after_sub <= rst_after_sub_comb; - end if; - end if; -end process RST_AFTER_SUB_PROC; - --- counts all bytes loaded to divide data into frames -bytesLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then - bytes_loaded <= x"0000"; - elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then - bytes_loaded <= bytes_loaded + x"1"; - -- gk 05.12.10 --- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then --- bytes_loaded <= bytes_loaded + x"1"; - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then - bytes_loaded <= bytes_loaded + x"1"; - elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then - bytes_loaded <= bytes_loaded + x"1"; - end if; - end if; -end process bytesLoadedProc; - --- size of subevent loaded from memory -subSizeLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10 - sub_size_loaded <= x"00000000"; - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then - -- was all_int_ctr - -- gk 08.04.10 my_int_ctr changed to load_int_ctr - sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q; - -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo - elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then - sub_size_loaded <= sub_size_loaded + x"4"; - end if; - end if; -end process subSizeLoadedProc; - --- counts only raw data bytes being loaded -subBytesLoadedProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10 - sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count - elsif (loadCurrentState = LOAD_DATA) then - sub_bytes_loaded <= sub_bytes_loaded + x"1"; - end if; - end if; -end process subBytesLoadedProc; - --- counts the size of the large udp packet -actualPacketProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - actual_packet_size <= x"0008"; - elsif (fc_wr_en = '1') then - actual_packet_size <= actual_packet_size + x"1"; - end if; - end if; -end process actualPacketProc; - -actualQueueSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = CLEANUP) then - actual_queue_size <= (others => '0'); - elsif (loadCurrentState = LIDLE) then - actual_queue_size <= queue_size; - end if; - end if; -end process actualQueueSizeProc; - --- amount of bytes left to send in current packet -sizeLeftProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = CLEANUP) then - size_left <= (others => '0'); - elsif (loadCurrentState = LIDLE) then - size_left <= queue_size; - elsif (fc_wr_en = '1') then - size_left <= size_left - 1; - end if; - end if; -end process sizeLeftProc; - --- HOT FIX: don't rely on CTS information, count the packets on your own. --- In this case, we increment the fragmented packet ID with EOD from ipu2gbe. -THE_FC_IDENT_COUNTER_PROC: process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_ident <= (others => '0'); - elsif (PC_END_OF_DATA_IN = '1') then - fc_ident <= fc_ident + 1; - end if; - end if; -end process THE_FC_IDENT_COUNTER_PROC; - -fc_flags_offset(15 downto 14) <= "00"; - -moreFragmentsProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - fc_flags_offset(13) <= '0'; - elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then - if ((actual_queue_size - actual_packet_size) < max_frame_size) then - fc_flags_offset(13) <= '0'; -- no more fragments - else - fc_flags_offset(13) <= '1'; -- more fragments - end if; - end if; - end if; -end process moreFragmentsProc; - -eodProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_eod <= '0'; - elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then - fc_eod <= '1'; - elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then - fc_eod <= '1'; - elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then - fc_eod <= '1'; - else - fc_eod <= '0'; - end if; - end if; -end process eodProc; - -sodProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_sod <= '0'; - elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then - fc_sod <= '1'; - elsif (loadCurrentState = DIVIDE) and (FC_READY_IN = '1') then - fc_sod <= '1'; - else - fc_sod <= '0'; - end if; - end if; -end process sodProc; - -offsetProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then - fc_flags_offset(12 downto 0) <= (others => '0'); - elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) then - fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3); - end if; - end if; -end process offsetProc; - -fcIPSizeProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET= '1') then - fc_ip_size <= (others => '0'); - elsif ((loadCurrentState = DIVIDE) and (FC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1')) then - if (size_left >= max_frame_size) then - fc_ip_size <= max_frame_size; - else - fc_ip_size <= size_left(15 downto 0); - end if; - end if; - end if; -end process fcIPSizeProc; - -fcUDPSizeProc : process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - fc_udp_size <= (others => '0'); - elsif (loadCurrentState = WAIT_FOR_FC) and (FC_READY_IN = '1') then - fc_udp_size <= queue_size(15 downto 0); - end if; - end if; -end process fcUDPSizeProc; - - ---*********************** --- SUBEVENT HEADERS WRITE AND READ ---*********************** - ---SUBEVENT_HEADERS_FIFO : fifo_16kx8 -- gk 06.12.10 fifo_2048x8 -SUBEVENT_HEADERS_FIFO : fifo_2048x8 -port map( - Data => shf_data, - WrClock => CLK, - RdClock => CLK, - WrEn => shf_wr_en, - RdEn => shf_rd_en, - Reset => RESET, - RPReset => RESET, - Q => shf_q, - Empty => shf_empty, - Full => shf_full -); - --- write enable for SHF -shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA)) - else '0'; - --- data multiplexing for SHF (convert 32bit LWs to 8bit) --- CHANGED. --- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC. -shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, - pc_trig_nr, my_int_ctr, fc_data) -begin - case saveSubCurrentState is - when SIDLE => shf_data <= x"ac"; - when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8); - when SAVE_TERM => shf_data <= fc_data; - when others => shf_data <= x"00"; - end case; -end process shfDataProc; - -saveSubMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saveSubCurrentState <= SIDLE; - else - saveSubCurrentState <= saveSubNextState; - end if; - end if; -end process saveSubMachineProc; - -saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, FC_H_READY_IN) -begin - case saveSubCurrentState is - when SIDLE => - save_state <= x"0"; - if (PC_START_OF_SUB_IN = '1') then - saveSubNextState <= SAVE_SIZE; - -- this branch is dangerous! - elsif (loadCurrentState = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len - saveSubNextState <= SAVE_TERM; - else - saveSubNextState <= SIDLE; - end if; - when SAVE_SIZE => - save_state <= x"1"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_DECODING; - else - saveSubNextState <= SAVE_SIZE; - end if; - when SAVE_DECODING => - save_state <= x"2"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_ID; - else - saveSubNextState <= SAVE_DECODING; - end if; - when SAVE_ID => - save_state <= x"3"; - if (sub_int_ctr = 3) then - saveSubNextState <= SAVE_TRIG_NR; - else - saveSubNextState <= SAVE_ID; - end if; - when SAVE_TRIG_NR => - save_state <= x"4"; - if (sub_int_ctr = 3) then - saveSubNextState <= SIDLE; - else - saveSubNextState <= SAVE_TRIG_NR; - end if; - when SAVE_TERM => - save_state <= x"5"; - if (sub_int_ctr = 31) then - saveSubNextState <= SIDLE; - else - saveSubNextState <= SAVE_TERM; - end if; - when others => - save_state <= x"f"; - saveSubNextState <= SIDLE; - end case; -end process; - --- This counter is used for breaking down 32bit information words into 8bit bytes for --- storing them in the SHF. --- It is also used for the termination 32byte sequence. -subIntProc: process( CLK ) -begin - if rising_edge(CLK) then - if (RESET = '1') or (saveSubCurrentState = SIDLE) then - sub_int_ctr <= 0; - elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then - sub_int_ctr <= 0; - elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then - sub_int_ctr <= 0; - elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then - sub_int_ctr <= sub_int_ctr + 1; - end if; - end if; -end process subIntProc; - -debug(3 downto 0) <= constr_state; -debug(7 downto 4) <= save_state; -debug(11 downto 8) <= load_state; -debug(27 downto 12) <= queue_size(15 downto 0); -debug(28) <= df_full; -debug(29) <= df_empty; -debug(30) <= shf_full; -debug(31) <= shf_empty; - -debug(47 downto 32) <= size_left(15 downto 0); -debug(52 downto 48) <= all_ctr; -debug(53) <= pc_ready; - --- outputs -PC_READY_OUT <= pc_ready; -FC_WR_EN_OUT <= fc_wr_en; -FC_DATA_OUT <= fc_data; -FC_IP_SIZE_OUT <= fc_ip_size; -FC_UDP_SIZE_OUT <= fc_udp_size; -FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0); -FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8); -FC_FLAGS_OFFSET_OUT <= fc_flags_offset; -FC_SOD_OUT <= fc_sod; -FC_EOD_OUT <= fc_eod; - -DEBUG_OUT <= debug; - -end trb_net16_gbe_packet_constr; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_gbe_setup.vhd b/gbe_ecp2m/trb_net16_gbe_setup.vhd deleted file mode 100644 index 42d5d73..0000000 --- a/gbe_ecp2m/trb_net16_gbe_setup.vhd +++ /dev/null @@ -1,445 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; ---use work.version.all; - - -entity gbe_setup is -port( - CLK : in std_logic; - RESET : in std_logic; - - -- interface to regio bus - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - - -- gk 26.04.10 - -- input from gbe_buf (only to return the whole trigger number via regio) - GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0); - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); - GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0); - GBE_MIN_PACKET_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); - GBE_USE_GBE_OUT : out std_logic; - GBE_USE_TRBNET_OUT : out std_logic; - GBE_USE_MULTIEVENTS_OUT : out std_logic; - GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10 - GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 - GBE_DELAY_OUT : out std_logic_vector(31 downto 0); - GBE_ALLOW_LARGE_OUT : out std_logic; - GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10 - -- gk 28.07.10 - MONITOR_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_SENT_IN : in std_logic_vector(31 downto 0); - MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0); - MONITOR_SM_IN : in std_logic_vector(31 downto 0); - MONITOR_LR_IN : in std_logic_vector(31 downto 0); - MONITOR_HDR_IN : in std_logic_vector(31 downto 0); - MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0); - MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0); - MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10 - MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10 - -- gk 01.06.10 - DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE3_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE4_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE5_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE6_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE7_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE8_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE9_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE10_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE11_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE12_IN : in std_logic_vector(31 downto 0); - DBG_PC1_IN : in std_logic_vector(31 downto 0); - DBG_PC2_IN : in std_logic_vector(31 downto 0); - DBG_FC1_IN : in std_logic_vector(31 downto 0); - DBG_FC2_IN : in std_logic_vector(31 downto 0); - DBG_FT1_IN : in std_logic_vector(31 downto 0); - DBG_FT2_IN : in std_logic_vector(31 downto 0); - DBG_FIFO_RD_EN_OUT : out std_logic; - DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0) - --DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10 -); -end entity; - -architecture gbe_setup of gbe_setup is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of gbe_setup : architecture is "GBE_conf_group"; - -signal reset_values : std_logic; - -signal subevent_id : std_logic_vector(31 downto 0); -signal subevent_dec : std_logic_vector(31 downto 0); -signal queue_dec : std_logic_vector(31 downto 0); -signal max_packet : std_logic_vector(31 downto 0); -signal min_packet : std_logic_vector(31 downto 0); -- gk 07.20.10 -signal max_frame : std_logic_vector(15 downto 0); -signal use_gbe : std_logic; -signal use_trbnet : std_logic; -signal use_multievents : std_logic; -signal readout_ctr : std_logic_vector(23 downto 0); -- gk 26.04.10 -signal readout_ctr_valid : std_logic; -- gk 26.04.10 -signal ack : std_logic; -- gk 26.04.10 -signal ack_q : std_logic; -- gk 26.04.10 -signal data_out : std_logic_vector(31 downto 0); -- gk 26.04.10 -signal delay : std_logic_vector(31 downto 0); -- gk 28.04.10 -signal allow_large : std_logic; -- gk 21.07.10 -signal reset_fifo : std_logic; -- gk 28.09.10 -signal frame_delay : std_logic_vector(31 downto 0); -- gk 09.12.10 - -begin - -OUT_PROC : process(CLK) -begin - if rising_edge(CLK) then - GBE_SUBEVENT_ID_OUT <= subevent_id; - GBE_SUBEVENT_DEC_OUT <= subevent_dec; - GBE_QUEUE_DEC_OUT <= queue_dec; - GBE_MAX_PACKET_OUT <= max_packet; - GBE_MIN_PACKET_OUT <= min_packet; - GBE_MAX_FRAME_OUT <= max_frame; - GBE_USE_GBE_OUT <= use_gbe; - GBE_USE_TRBNET_OUT <= use_trbnet; - GBE_USE_MULTIEVENTS_OUT <= use_multievents; - GBE_READOUT_CTR_OUT <= readout_ctr; -- gk 26.04.10 - GBE_READOUT_CTR_VALID_OUT <= readout_ctr_valid; -- gk 26.04.10 - BUS_ACK_OUT <= ack_q; -- gk 26.04.10 - ack_q <= ack; -- gk 26.04.10 - BUS_DATA_OUT <= data_out; -- gk 26.04.10 - GBE_DELAY_OUT <= delay; -- gk 28.04.10 - GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10 - --DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10 - GBE_FRAME_DELAY_OUT <= frame_delay; -- gk 09.12.10 - end if; -end process OUT_PROC; - --- gk 26.04.10 -ACK_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - ack <= '0'; - elsif ((BUS_WRITE_EN_IN = '1') or (BUS_READ_EN_IN = '1')) then - ack <= '1'; - else - ack <= '0'; - end if; - end if; -end process ACK_PROC; - -WRITE_PROC : process(CLK) -begin - DBG_FIFO_RD_EN_OUT <= '0'; - - if rising_edge(CLK) then - if ( (RESET = '1') or (reset_values = '1') ) then - subevent_id <= x"0000_00cf"; - subevent_dec <= x"0002_0001"; - queue_dec <= x"0003_0062"; - max_packet <= x"0000_ea60"; --x"0000_fde8"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester - min_packet <= x"0000_0007"; -- gk 20.07.10 - max_frame <= x"0578"; - use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured - use_trbnet <= '0'; - use_multievents <= '0'; - reset_values <= '0'; - readout_ctr <= x"00_0000"; -- gk 26.04.10 -- gk 07.06.10 corrected bug found by Sergey - readout_ctr_valid <= '0'; -- gk 26.04.10 - delay <= x"0000_0000"; -- gk 28.04.10 - DBG_FIFO_RD_EN_OUT <= '0'; - allow_large <= '0'; -- gk 21.07.10 - reset_fifo <= '0'; -- gk 28.09.10 - frame_delay <= x"0000_0000"; -- gk 09.12.10 - - elsif (BUS_WRITE_EN_IN = '1') then - case BUS_ADDR_IN is - - when x"00" => - subevent_id <= BUS_DATA_IN; - - when x"01" => - subevent_dec <= BUS_DATA_IN; - - when x"02" => - queue_dec <= BUS_DATA_IN; - - when x"03" => - max_packet <= BUS_DATA_IN; - - when x"04" => - max_frame <= BUS_DATA_IN(15 downto 0); - - when x"05" => - if (BUS_DATA_IN = x"0000_0000") then - use_gbe <= '0'; - else - use_gbe <= '1'; - end if; - - when x"06" => - if (BUS_DATA_IN = x"0000_0000") then - use_trbnet <= '0'; - else - use_trbnet <= '1'; - end if; - - when x"07" => - if (BUS_DATA_IN = x"0000_0000") then - use_multievents <= '0'; - else - use_multievents <= '1'; - end if; - - -- gk 26.04.10 - when x"08" => - readout_ctr <= BUS_DATA_IN(23 downto 0); - readout_ctr_valid <= '1'; - - -- gk 28.04.10 - when x"09" => - delay <= BUS_DATA_IN; - - when x"0a" => - DBG_FIFO_RD_EN_OUT <= '1'; - - -- gk 20.07.10 - when x"0b" => - min_packet <= BUS_DATA_IN; - - -- gk 21.07.10 - when x"0c" => - if (BUS_DATA_IN = x"0000_0000") then - allow_large <= '0'; - else - allow_large <= '1'; - end if; - - -- gk 09.12.10 - when x"0d" => - frame_delay <= BUS_DATA_IN; - - -- gk 28.09.10 - when x"fe" => - if (BUS_DATA_IN = x"ffff_ffff") then - reset_fifo <= '1'; - else - reset_fifo <= '0'; - end if; - - when x"ff" => - if (BUS_DATA_IN = x"ffff_ffff") then - reset_values <= '1'; - else - reset_values <= '0'; - end if; - - when others => - subevent_id <= subevent_id; - subevent_dec <= subevent_dec; - queue_dec <= queue_dec; - max_packet <= max_packet; - min_packet <= min_packet; - max_frame <= max_frame; - use_gbe <= use_gbe; - use_trbnet <= use_trbnet; - use_multievents <= use_multievents; - reset_values <= reset_values; - readout_ctr <= readout_ctr; -- gk 26.04.10 - readout_ctr_valid <= readout_ctr_valid; -- gk 26.04.10 - delay <= delay; -- gk 28.04.10 - DBG_FIFO_RD_EN_OUT <= '0'; - allow_large <= allow_large; - reset_fifo <= reset_fifo; -- gk 28.09.10 - frame_delay <= frame_delay; - end case; - else - reset_values <= '0'; - readout_ctr_valid <= '0'; -- gk 26.04.10 - --reset_fifo <= '0'; -- gk 28.09.10 - end if; - end if; -end process WRITE_PROC; - --- gk 26.04.10 -READ_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - data_out <= (others => '0'); - elsif (BUS_READ_EN_IN = '1') then - case BUS_ADDR_IN is - - when x"00" => - data_out <= subevent_id; - - when x"01" => - data_out <= subevent_dec; - - when x"02" => - data_out <= queue_dec; - - when x"03" => - data_out <= max_packet; - - when x"04" => - data_out(15 downto 0) <= max_frame; - data_out(31 downto 16) <= (others => '0'); - - when x"05" => - if (use_gbe = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when x"06" => - if (use_trbnet = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when x"07" => - if (use_multievents = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - when x"08" => - data_out <= GBE_TRIG_NR_IN; - - when x"09" => - data_out <= delay; - - when x"0b" => - data_out <= min_packet; - - -- gk 21.07.10 - when x"0c" => - if (allow_large = '0') then - data_out <= x"0000_0000"; - else - data_out <= x"0000_0001"; - end if; - - -- gk 09.12.10 - when x"0d" => - data_out <= frame_delay; - - -- gk 01.06.10 - when x"e0" => - data_out <= DBG_IPU2GBE1_IN; - - when x"e1" => - data_out <= DBG_IPU2GBE2_IN; - - when x"e2" => - data_out <= DBG_PC1_IN; - - when x"e3" => - data_out <= DBG_PC2_IN; - - when x"e4" => - data_out <= DBG_FC1_IN; - - when x"e5" => - data_out <= DBG_FC2_IN; - - when x"e6" => - data_out <= DBG_FT1_IN; - - when x"e7" => - data_out <= DBG_FT2_IN; - - when x"e8" => - data_out(15 downto 0) <= DBG_FIFO_Q_IN; - data_out(31 downto 16) <= (others => '0'); - - when x"e9" => - data_out <= DBG_IPU2GBE3_IN; - - when x"ea" => - data_out <= DBG_IPU2GBE4_IN; - - when x"eb" => - data_out <= DBG_IPU2GBE5_IN; - - when x"ec" => - data_out <= DBG_IPU2GBE6_IN; - - when x"ed" => - data_out <= DBG_IPU2GBE7_IN; - - when x"ee" => - data_out <= DBG_IPU2GBE8_IN; - - when x"ef" => - data_out <= DBG_IPU2GBE9_IN; - - when x"f0" => - data_out <= DBG_IPU2GBE10_IN; - - when x"f1" => - data_out <= DBG_IPU2GBE11_IN; - - when x"f2" => - data_out <= DBG_IPU2GBE12_IN; - - when x"f3" => - data_out <= MONITOR_BYTES_IN; - - when x"f4" => - data_out <= MONITOR_SENT_IN; - - when x"f5" => - data_out <= MONITOR_DROPPED_IN; - - when x"f6" => - data_out <= MONITOR_SM_IN; - - when x"f7" => - data_out <= MONITOR_LR_IN; - - when x"f8" => - data_out <= MONITOR_HDR_IN; - - when x"f9" => - data_out <= MONITOR_FIFOS_IN; - - when x"fa" => - data_out <= MONITOR_DISCFRM_IN; - - when x"fb" => - data_out <= MONITOR_LINK_DWN_IN; - - when x"fc" => - data_out <= MONITOR_EMPTY_IN; - - when others => - data_out <= (others => '0'); - end case; - end if; - end if; -end process READ_PROC; - -end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd deleted file mode 100755 index 4a1506f..0000000 --- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd +++ /dev/null @@ -1,1435 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -use IEEE.std_logic_arith.all; - -library work; - -entity trb_net16_ipu2gbe is -port( - CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 - MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - -- PacketConstructor interface - ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; -- gk 08.11.10 - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) -); -end entity; - -architecture trb_net16_ipu2gbe of trb_net16_ipu2gbe is - --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of trb_net16_ipu2gbe : architecture is "GBE_ipu2gbe_group"; - -component fifo_32kx16x8_mb2 -port( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - AmEmptyThresh : in std_logic_vector(15 downto 0); - AmFullThresh : in std_logic_vector(14 downto 0); - Q : out std_logic_vector(8 downto 0); - WCNT : out std_logic_vector(15 downto 0); - RCNT : out std_logic_vector(16 downto 0); - Empty : out std_logic; - AlmostEmpty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic -); -end component; - -type saveStates is (SIDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SCLOSE); -signal saveCurrentState, saveNextState : saveStates; -signal state : std_logic_vector(3 downto 0); -signal data_req_comb : std_logic; -signal data_req : std_logic; -- request data signal, will be used for fee_read generation -signal rst_saved_ctr_comb : std_logic; -signal rst_saved_ctr : std_logic; - -signal fee_read_comb : std_logic; -signal fee_read : std_logic; -- fee_read signal -signal saved_ctr : std_logic_vector(16 downto 0); -signal ce_saved_ctr : std_logic; - --- header data -signal cts_rnd : std_logic_vector(15 downto 0); -signal cts_rnd_saved : std_logic; -signal cts_trg : std_logic_vector(15 downto 0); -signal cts_trg_saved : std_logic; -signal cts_len : std_logic_vector(16 downto 0); -signal cts_len_saved : std_logic; - --- CTS interface -signal cts_error_pattern : std_logic_vector(31 downto 0); -signal cts_length : std_logic_vector(15 downto 0); -signal cts_readout_finished : std_logic; -signal cts_dataready : std_logic; -signal cts_data : std_logic_vector(31 downto 0); - --- Split FIFO signals -signal sf_data : std_logic_vector(15 downto 0); -signal sf_wr_en_comb : std_logic; -signal sf_wr_en : std_logic; -- write signal for FIFO -signal sf_rd_en_comb : std_logic; -signal sf_rd_en : std_logic; -- read signal for FIFO -signal sf_wcnt : std_logic_vector(15 downto 0); -signal sf_rcnt : std_logic_vector(16 downto 0); -signal sf_empty : std_logic; -signal sf_aempty : std_logic; -signal sf_full : std_logic; -signal sf_afull : std_logic; - -------------------------------------------------------------------- -type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC, DROP, WAIT_TO_REMOVE, DROP_SUBSUB, PAUSE_BEFORE_DROP1, PAUSE_BEFORE_DROP2); -signal loadCurrentState, loadNextState : loadStates; -signal state2 : std_logic_vector(3 downto 0); - -signal rem_ctr : std_logic_vector(3 downto 0); -- counter for stripping / storing header data -signal rst_rem_ctr_comb : std_logic; -signal rst_rem_ctr : std_logic; -- reset the remove counter -signal rst_regs_comb : std_logic; -signal rst_regs : std_logic; -- reset storage registers -signal rem_phase_comb : std_logic; -signal rem_phase : std_logic; -- header remove phase -signal data_phase_comb : std_logic; -signal data_phase : std_logic; -- data transport phase from split fifo to PC -signal pad_phase_comb : std_logic; -signal pad_phase : std_logic; -- padding phase -signal calc_pad_comb : std_logic; -signal calc_pad : std_logic; -- check if padding bytes need to be added to PC_SUB_SIZE -signal pad_data_comb : std_logic; -signal pad_data : std_logic; -- reset PC_DATA register to known padding byte value - -signal pc_sos_comb : std_logic; -signal pc_sos : std_logic; -- start of data signal -signal pc_eod_comb : std_logic; -signal pc_eod : std_logic; -- end of data signal - -signal ce_rem_ctr_comb : std_logic; -signal ce_rem_ctr : std_logic; -- count enable for remove counter -signal remove_done_comb : std_logic; -signal remove_done : std_logic; -- end of header stripping process -signal read_done_comb : std_logic; -signal read_done : std_logic; -- end of data phase (read phase from SF) - -signal pc_data : std_logic_vector(7 downto 0); -signal pc_data_q : std_logic_vector(7 downto 0); -signal pc_trig_nr : std_logic_vector(15 downto 0); -signal pc_sub_size : std_logic_vector(17 downto 0); -signal read_size : std_logic_vector(17 downto 0); -- number of byte to be read from split fifo -signal padding_needed : std_logic; -signal pc_wr_en_comb : std_logic; -signal pc_wr_en_q : std_logic; -signal pc_wr_en_qq : std_logic; -signal pc_wr_en_qqq : std_logic; -signal pc_eod_q : std_logic; - -signal debug : std_logic_vector(383 downto 0); - --- gk -signal bank_select : std_logic_vector(3 downto 0); -signal save_addr_comb : std_logic; -signal save_addr : std_logic; -signal addr_saved_comb : std_logic; -signal addr_saved : std_logic; -signal start_config : std_logic; -signal config_done : std_logic; -signal add_sub_state : std_logic; -signal add_sub_state_comb : std_logic; -signal add_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub : std_logic; -signal load_sub_comb : std_logic; -signal load_sub_done : std_logic; -signal load_sub_done_comb : std_logic; -signal load_sub_ctr : std_logic_vector(3 downto 0); -signal load_sub_ctr_comb : std_logic; -signal actual_message_size : std_logic_vector(31 downto 0); -signal more_subevents : std_logic; -signal trig_random : std_logic_vector(7 downto 0); -signal readout_ctr : std_logic_vector(23 downto 0); -signal readout_ctr_lock : std_logic; -signal pc_trig_nr_q : std_logic_vector(31 downto 0); - --- gk 20.07.10 -signal inc_data_ctr : std_logic_vector(31 downto 0); -signal dropped_sm_events_ctr : std_logic_vector(31 downto 0); -signal dropped_lr_events_ctr : std_logic_vector(31 downto 0); -signal dropped_ctr : std_logic_vector(31 downto 0); --- gk 22.07.10 -signal headers_invalid : std_logic; -signal headers_invalid_ctr : std_logic_vector(31 downto 0); -signal cts_len_q : std_logic_vector(15 downto 0); -signal cts_trg_q : std_logic_vector(15 downto 0); -signal cts_rnd_q : std_logic_vector(15 downto 0); -signal first_run_trg : std_logic_vector(15 downto 0); -signal first_run_addr : std_logic_vector(15 downto 0); -signal first_run_lock : std_logic; -signal cts_addr : std_logic_vector(15 downto 0); -signal cts_addr_q : std_logic_vector(15 downto 0); -signal cts_addr_saved : std_logic; - --- gk 24.07.10 -signal save_eod : std_logic; -signal save_eod_comb : std_logic; - -signal load_eod : std_logic; -signal endpoint_addr : std_logic_vector(15 downto 0); -signal endp_addr_lock : std_logic; - -signal saved_events_ctr : std_logic_vector(15 downto 0); -signal loaded_events_ctr : std_logic_vector(15 downto 0); -signal constr_events_ctr : std_logic_vector(31 downto 0); -signal event_waiting : std_logic; - -signal drop_sub : std_logic; -signal drop_sub_comb : std_logic; -signal drop_event : std_logic; -signal drop_event_comb : std_logic; -signal drop_small : std_logic; -signal drop_large : std_logic; -signal drop_headers : std_logic; -signal drop_small_comb : std_logic; -signal drop_large_comb : std_logic; -signal drop_headers_comb : std_logic; -signal inc_trg_ctr : std_logic; -signal inc_trg_ctr_comb : std_logic; - -signal invalid_hsize_ctr : std_logic_vector(15 downto 0); -signal invalid_hsize_lock : std_logic; - -signal load_eod_q : std_logic; -signal read_size_q : std_logic_vector(17 downto 0); - --- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked -signal sf_real_wr_en : std_logic; - --- gk 01.10.10 -signal found_empty_evt : std_logic; -signal found_empty_evt_comb : std_logic; -signal found_empty_evt_ctr : std_logic_vector(31 downto 0); - --- gk 06.10.10 -signal message_size : std_logic_vector(31 downto 0); - --- gk 07.12.10 -signal prev_bank_select : std_logic_vector(3 downto 0); -signal first_event : std_logic; - --- gk 29.07.11 -signal trg_type : std_logic_vector(3 downto 0); -signal prev_trg_type : std_logic_vector(3 downto 0); - -begin - -BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 -START_CONFIG_OUT <= start_config; -- gk 27.03.10 -config_done <= CONFIG_DONE_IN; -- gk 29.03.10 - --- CTS interface signals -cts_error_pattern <= (others => '0'); -- FAKE - -cts_length <= x"0000"; -- length of data payload is always 0 -cts_data <= b"0001" & cts_rnd(11 downto 0) & cts_trg; -- reserved bits = '0', pack bit = '1' - -cts_readout_finished <= '1' when (saveCurrentState = SCLOSE) else '0'; - -cts_dataready <= '1' when ((saveCurrentState = SAVE_DATA) and (FEE_BUSY_IN = '0')) or (saveCurrentState = TERMINATE) - else '0'; - --- Byte swapping... done here. TAKE CARE! --- The split FIFO is in natural bus order (i.e. Motorola style, [15:0]). This means that the two bytes --- on the write side need to be swapped to appear in GbE style (i.e. Intel style) on the 8bit port. --- Please mind that PC_SUB_SIZE and PC_TRIG_NR stay in a human readable format, and need to be byteswapped --- for GbE inside the packet constructor. --- --- Long live the Endianess! - --- Sync all critical pathes -THE_SYNC_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - --sf_data <= FEE_DATA_IN; -- gk 27.03.10 moved out to the process below - sf_wr_en <= sf_wr_en_comb; - ce_rem_ctr <= ce_rem_ctr_comb; - sf_rd_en <= sf_rd_en_comb; - fee_read <= fee_read_comb; - read_done <= read_done_comb; - pc_eod_q <= pc_eod; - pc_wr_en_qqq <= pc_wr_en_qq; - pc_wr_en_qq <= pc_wr_en_q; - pc_wr_en_q <= pc_wr_en_comb; - end if; -end process THE_SYNC_PROC; - --- gk 27.03.10 data selector for sf to write the evt builder address on top of data -SF_DATA_PROC : process( CLK ) -begin - if( rising_edge(CLK) ) then - if (RESET = '1') then -- gk 31.05.10 - sf_data <= (others => '0'); - elsif( save_addr = '1' ) then - -- gk 29.07.11 added to this data word the trigger type in order to close multi events - sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address - sf_data(11 downto 4) <= x"bc"; - sf_data(15 downto 12) <= CTS_READOUT_TYPE_IN; - -- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent - elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then - sf_data <= x"0001"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then - sf_data <= x"5555"; -- gk 11.06.10 - elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then - sf_data <= FEE_STATUS_BITS_IN(31 downto 16); - elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then - sf_data <= FEE_STATUS_BITS_IN(15 downto 0); - else - sf_data <= FEE_DATA_IN; - end if; - end if; -end process SF_DATA_PROC; - --- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY -fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled - else '0'; - --- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY -sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled - (save_addr = '1') or - (add_sub_state = '1') -- gk 29.03.10 save the subsubevent - else '0'; - --- gk 06.08.10 -sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0'; - --- gk 27.03.10 do not count evt builder address as saved ipu bytes ---ce_saved_ctr <= sf_wr_en; -ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en; - --- Statemachine for reading data payload, handling IPU channel and storing data in the SPLIT_FIFO -saveMachineProc: process( CLK ) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saveCurrentState <= SIDLE; - data_req <= '0'; - rst_saved_ctr <= '0'; - save_addr <= '0'; -- gk 27.03.10 - addr_saved <= '0'; -- gk 27.03.10 - add_sub_state <= '0'; -- gk 29.03.10 - save_eod <= '0'; -- gk 25.07.10 - else - saveCurrentState <= saveNextState; - data_req <= data_req_comb; - rst_saved_ctr <= rst_saved_ctr_comb; - save_addr <= save_addr_comb; -- gk 27.03.10 - addr_saved <= addr_saved_comb; -- gk 27.03.10 - add_sub_state <= add_sub_state_comb; -- gk 29.03.10 - save_eod <= save_eod_comb; -- gk 25.07.10 - end if; - end if; -end process saveMachineProc; - -saveMachine: process( saveCurrentState, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN) -begin - saveNextState <= SIDLE; - data_req_comb <= '0'; - rst_saved_ctr_comb <= '0'; - save_addr_comb <= '0'; -- gk 27.03.10 - addr_saved_comb <= '0'; -- gk 27.03.10 - add_sub_state_comb <= '0'; -- gk 29.03.10 - save_eod_comb <= '0'; -- gk 25.07.10 - case saveCurrentState is - when SIDLE => - state <= x"0"; - if (CTS_START_READOUT_IN = '1') then - saveNextState <= SAVE_EVT_ADDR; --WAIT_FOR_DATA; -- gk 27.03.10 - data_req_comb <= '1'; - rst_saved_ctr_comb <= '1'; - else - saveNextState <= SIDLE; - end if; - -- gk 27.03.10 - when SAVE_EVT_ADDR => - state <= x"5"; - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - save_addr_comb <= '1'; - when WAIT_FOR_DATA => - state <= x"1"; - if (FEE_BUSY_IN = '1') then - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - else - saveNextState <= WAIT_FOR_DATA; - data_req_comb <= '1'; - end if; - addr_saved_comb <= '1'; -- gk 27.03.10 - when SAVE_DATA => - state <= x"2"; - if (FEE_BUSY_IN = '0') then - saveNextState <= TERMINATE; - else - saveNextState <= SAVE_DATA; - data_req_comb <= '1'; - end if; - when TERMINATE => - state <= x"3"; - if (CTS_READ_IN = '1') then - saveNextState <= SCLOSE; - else - saveNextState <= TERMINATE; - end if; - when SCLOSE => - state <= x"4"; - if (CTS_START_READOUT_IN = '0') then - saveNextState <= ADD_SUBSUB1; --SIDLE; -- gk 29.03.10 - else - saveNextState <= SCLOSE; - end if; - -- gk 29.03.10 new states during which the subsub bytes are saved - when ADD_SUBSUB1 => - state <= x"6"; - saveNextState <= ADD_SUBSUB2; - add_sub_state_comb <= '1'; - when ADD_SUBSUB2 => - state<= x"7"; - saveNextState <= ADD_SUBSUB3; - add_sub_state_comb <= '1'; - save_eod_comb <= '1'; - when ADD_SUBSUB3 => - state<= x"8"; - saveNextState <= ADD_SUBSUB4; - add_sub_state_comb <= '1'; - when ADD_SUBSUB4 => - state<= x"9"; - saveNextState <= SIDLE; - add_sub_state_comb <= '1'; - when others => - state <= x"f"; - saveNextState <= SIDLE; - end case; -end process saveMachine; - --- gk 29.03.10 -ADD_SUB_CTR_PROC : process( CLK ) -begin - if( rising_edge( CLK ) ) then - if( (RESET = '1') or (rst_saved_ctr = '1') ) then - add_sub_ctr <= (others => '0'); - elsif( add_sub_state = '1' ) then - add_sub_ctr <= add_sub_ctr + 1; - end if; - end if; -end process ADD_SUB_CTR_PROC; - ---******** --- SAVE INCOMING EVENT HEADERS ---******** - --- Counter for header word storage -THE_CTS_SAVED_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - saved_ctr <= (others => '0'); - elsif( ce_saved_ctr = '1' ) then - saved_ctr <= saved_ctr + 1; - end if; - end if; -end process THE_CTS_SAVED_CTR; - --- save triggerRnd from incoming data for cts response -CTS_RND_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_rnd <= (others => '0'); - cts_rnd_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"000") and (sf_wr_en = '1') and (cts_rnd_saved = '0') ) then - cts_rnd <= sf_data; - cts_rnd_saved <= '1'; - end if; - end if; -end process CTS_RND_PROC; - --- save triggerNr from incoming data for cts response -CTS_TRG_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_trg <= (others => '0'); - cts_trg_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"001") and (sf_wr_en = '1') and (cts_trg_saved = '0') ) then - cts_trg <= sf_data; - cts_trg_saved <= '1'; - end if; - end if; -end process CTS_TRG_PROC; - --- save size from incoming data for cts response (future) and to get rid of padding -CTS_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_len <= (others => '0'); - cts_len_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"010") and (sf_wr_en = '1') and (cts_len_saved = '0') ) then - cts_len(16 downto 1) <= sf_data; -- change from 32b words to 16b words - cts_len(0) <= '0'; - elsif( (saved_ctr(2 downto 0) = b"011") and (cts_len_saved = '0') ) then - cts_len <= cts_len + x"4"; - cts_len_saved <= '1'; - end if; - end if; -end process CTS_SIZE_PROC; - --- gk 22.07.10 -CTS_ADDR_PROC : process(CLK) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_saved_ctr = '1') ) then - cts_addr <= (others => '0'); - cts_addr_saved <= '0'; - elsif( (saved_ctr(2 downto 0) = b"011") and (sf_wr_en = '1') and (cts_addr_saved = '0') ) then - cts_addr <= sf_data; - cts_addr_saved <= '1'; - end if; - end if; -end process CTS_ADDR_PROC; - ---****** --- SAVE FIRST EVENT HEADER VALUES ---****** - --- gk 22.07.10 -FIRST_RUN_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - first_run_trg <= (others => '0'); - first_run_addr <= (others => '0'); - first_run_lock <= '0'; - elsif (first_run_lock = '0') and (cts_addr_saved = '1') then - first_run_trg <= cts_trg; - first_run_addr <= cts_addr; - first_run_lock <= '1'; - -- important: value saved by saveMachine but incremented by loadMachine - elsif (first_run_lock = '1') and (inc_trg_ctr = '1') then - first_run_trg <= first_run_trg + x"1"; - end if; - end if; -end process FIRST_RUN_PROC; - --- gk 25.07.10 -SAVED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - saved_events_ctr <= (others => '0'); - elsif (save_eod = '1') then - saved_events_ctr <= saved_events_ctr + x"1"; - end if; - end if; -end process SAVED_EVT_CTR_PROC; - - --- gk 20.07.10 -INC_DATA_CTR_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_saved_ctr = '1') then - inc_data_ctr <= (others => '0'); - elsif (sf_wr_en = '1') and (data_req = '1') then - inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1"; - end if; - end if; -end process INC_DATA_CTR_proc; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Split FIFO -THE_SPLIT_FIFO: fifo_32kx16x8_mb2 -port map( - -- Byte swapping for correct byte order on readout side of FIFO - Data(7 downto 0) => sf_data(15 downto 8), - Data(8) => '0', - Data(16 downto 9) => sf_data(7 downto 0), - Data(17) => save_eod, - WrClock => CLK, - RdClock => CLK, - WrEn => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en, - RdEn => sf_rd_en, - Reset => RESET, - RPReset => RESET, - AmEmptyThresh => b"0000_0000_0000_0010", -- one byte ahead - AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 - Q(7 downto 0) => pc_data, - Q(8) => load_eod, - WCNT => sf_wcnt, - RCNT => sf_rcnt, - Empty => sf_empty, - AlmostEmpty => sf_aempty, - Full => sf_full, - AlmostFull => sf_afull -); - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- gk 25.07.10 -EVENT_WAITING_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - event_waiting <= '0'; - elsif (loaded_events_ctr /= saved_events_ctr) then - event_waiting <= '1'; - else - event_waiting <= '0'; - end if; - end if; -end process EVENT_WAITING_PROC; - --- write signal for PC data -pc_wr_en_comb <= '1' when ((data_phase = '1') and (sf_rd_en = '1')) or - (pad_phase = '1') or - ((load_sub = '1') and (sf_rd_en = '1')) or - ((drop_sub = '1') and (sf_rd_en = '1')) or - ((drop_event = '1') and (sf_rd_en = '1')) - else '0'; - -sf_rd_en_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and (remove_done = '0') ) or - --( (sf_aempty = '0') and (data_phase = '1') and (read_done = '0') ) or - ( (sf_aempty = '0') and (data_phase = '1') and (load_eod = '0') ) or -- gk 26.07.10 - ( (sf_aempty = '0') and (load_sub = '1') and (load_sub_done = '0') ) or -- gk 30.03.10 - ( (sf_aempty = '0') and (drop_event = '1') and (load_eod = '0') ) or - ( (sf_aempty = '0') and (drop_sub = '1') and (load_sub_done = '0') ) - else '0'; - -ce_rem_ctr_comb <= '1' when ( (sf_aempty = '0') and (rem_phase = '1') and ( remove_done = '0') ) - else '0'; - --- FIFO data delay process (also forces padding bytes to known value) -THE_DATA_DELAY_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if( pad_data = '1' ) then - pc_data_q <= x"aa"; -- padding for 64bit - -- gk 21.07.10 - -- set the error flag if a broken packet is sent - elsif (drop_sub = '1') and (load_sub_ctr = x"3") then - pc_data_q <= pc_data(7 downto 3) & '1' & pc_data(1 downto 0); - else - pc_data_q <= pc_data; - end if; - end if; -end process THE_DATA_DELAY_PROC; - --- Statemachine for reading the data payload from the SPLIT_FIFO and feeding --- it into the packet constructor -loadMachineProc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loadCurrentState <= LIDLE; - rst_rem_ctr <= '0'; - rem_phase <= '0'; - calc_pad <= '0'; - data_phase <= '0'; - pad_phase <= '0'; - pc_sos <= '0'; - pc_eod <= '0'; - rst_regs <= '0'; - pad_data <= '0'; - load_sub <= '0'; -- gk 30.03.10 - drop_sub <= '0'; -- gk 25.07.10 - drop_event <= '0'; -- gk 25.07.10 - drop_small <= '0'; -- gk 25.07.10 - drop_large <= '0'; -- gk 25.07.10 - drop_headers <= '0'; -- gk 25.07.10 - inc_trg_ctr <= '0'; -- gk 26.07.10 - found_empty_evt <= '0'; -- gk 01.10.10 - else - loadCurrentState <= loadNextState; - rst_rem_ctr <= rst_rem_ctr_comb; - rem_phase <= rem_phase_comb; - calc_pad <= calc_pad_comb; - data_phase <= data_phase_comb; - pad_phase <= pad_phase_comb; - pc_sos <= pc_sos_comb; - pc_eod <= pc_eod_comb; - rst_regs <= rst_regs_comb; - pad_data <= pad_data_comb; - load_sub <= load_sub_comb; -- gk 30.03.1 - drop_sub <= drop_sub_comb; -- gk 25.07.10 - drop_event <= drop_event_comb; -- gk 25.07.10 - drop_small <= drop_small_comb; -- gk 25.07.10 - drop_large <= drop_large_comb; -- gk 25.07.10 - drop_headers <= drop_headers_comb; -- gk 25.07.10 - inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10 - found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10 - end if; - end if; -end process loadMachineProc; - -loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting, bank_select, prev_bank_select) -begin - loadNextState <= LIDLE; - rst_rem_ctr_comb <= '0'; - rem_phase_comb <= '0'; - calc_pad_comb <= '0'; - data_phase_comb <= '0'; - pad_phase_comb <= '0'; - pc_sos_comb <= '0'; - pc_eod_comb <= '0'; - rst_regs_comb <= '0'; - pad_data_comb <= '0'; - load_sub_comb <= '0'; -- gk 30.03.10 - drop_sub_comb <= '0'; -- gk 25.07.10 - drop_event_comb <= '0'; -- gk 25.07.10 - drop_small_comb <= '0'; -- gk 25.07.10 - drop_large_comb <= '0'; -- gk 25.07.10 - drop_headers_comb <= '0'; -- gk 25.07.10 - inc_trg_ctr_comb <= '0'; -- gk 26.07.10 - found_empty_evt_comb <= '0'; -- gk 01.10.10 - case loadCurrentState is - when LIDLE => - state2 <= x"0"; - -- gk 23.07.10 - --if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 - -- gk 04.12.10 - if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then - loadNextState <= INIT; - rst_rem_ctr_comb <= '1'; - rst_regs_comb <= '1'; - else - loadNextState <= LIDLE; - end if; - when INIT => - state2 <= x"1"; - loadNextState <= REMOVE; - rem_phase_comb <= '1'; --- when REMOVE => --- state2 <= x"2"; --- if( remove_done = '1' ) then --- loadNextState <= WAIT_TO_REMOVE; --- inc_trg_ctr_comb <= '1'; --- else --- loadNextState <= REMOVE; --- rem_phase_comb <= '1'; --- end if; - -- gk 03.12.10 - when REMOVE => - state2 <= x"2"; - if( remove_done = '1' ) then - -- gk 06.10.10 - if (MULT_EVT_ENABLE_IN = '1') then - if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then - -- gk 07.12.10 - if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet - loadNextState <= WAIT_PC; - -- gk 29.07.11 - elsif (first_event = '0') and (prev_trg_type /= trg_type) then -- check if the trigger type has changed, if so close the current packet - loadNextState <= WAIT_PC; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - else - loadNextState <= WAIT_PC; - end if; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - inc_trg_ctr_comb <= '1'; - else - loadNextState <= REMOVE; - rem_phase_comb <= '1'; - end if; - - when WAIT_TO_REMOVE => - if (rem_ctr = x"a") then - loadNextState <= DECIDE; - else - loadNextState <= WAIT_TO_REMOVE; - end if; - when DECIDE => - if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_large_comb <= '1'; - elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10 - loadNextState <= CALCA; - found_empty_evt_comb <= '1'; - elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_small_comb <= '1'; - elsif (pc_trig_nr + x"1" /= first_run_trg) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_headers_comb <= '1'; - elsif (endpoint_addr /= first_run_addr) then - loadNextState <= PAUSE_BEFORE_DROP1; - drop_headers_comb <= '1'; - else - loadNextState <= CALCA; - end if; - calc_pad_comb <= '1'; - when CALCA => - state2 <= x"3"; - loadNextState <= CALCB; - pc_sos_comb <= '1'; - when CALCB => - -- we need a branch in case of length "0"!!!! - state2 <= x"4"; - loadNextState <= LOAD; - data_phase_comb <= '1'; - when LOAD => - state2 <= x"5"; - -- gk 31.03.10 after loading subevent data read the subsubevent from sf - if (load_eod = '1') then - loadNextState <= LOAD_SUBSUB; - else - loadNextState <= LOAD; - data_phase_comb <= '1'; - end if; - -- gk 31.03.10 - when LOAD_SUBSUB => - state2 <= x"d"; - if( load_sub_done = '1' ) then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= LOAD_SUBSUB; - load_sub_comb <= '1'; - end if; - when PAD0 => - state2 <= x"6"; - loadNextState <= PAD1; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD1 => - state2 <= x"7"; - loadNextState <= PAD2; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD2 => - state2 <= x"8"; - loadNextState <= PAD3; - pad_phase_comb <= '1'; - pad_data_comb <= '1'; - when PAD3 => - state2 <= x"9"; - loadNextState <= CALCC; - pad_data_comb <= '1'; --- when CALCC => --- state2 <= x"a"; --- loadNextState <= CLOSE; --- pc_eod_comb <= '1'; - -- gk 04.12.10 - when CALCC => - state2 <= x"a"; - if (MULT_EVT_ENABLE_IN = '1') then - loadNextState <= LIDLE; - else - loadNextState <= CLOSE; - end if; - pc_eod_comb <= '1'; - when CLOSE => - state2 <= x"b"; - loadNextState <= WAIT_PC; - rst_regs_comb <= '1'; --- when WAIT_PC => --- state2 <= x"c"; --- if( PC_READY_IN = '1' ) then --- loadNextState <= LIDLE; --- else --- loadNextState <= WAIT_PC; --- end if; - -- gk 03.12.10 - when WAIT_PC => - state2 <= x"c"; - if( PC_READY_IN = '1' ) then - -- gk 06.10.10 - if (MULT_EVT_ENABLE_IN = '1') then - loadNextState <= WAIT_TO_REMOVE; - else - loadNextState <= LIDLE; - end if; - else - loadNextState <= WAIT_PC; - end if; - when PAUSE_BEFORE_DROP1 => - loadNextState <= PAUSE_BEFORE_DROP2; - pc_sos_comb <= '1'; - when PAUSE_BEFORE_DROP2 => - loadNextState <= DROP; - drop_event_comb <= '1'; - -- gk 23.07.10 - when DROP => - state2 <= x"e"; - -- when data is dropped the eod marker stands as its end - if (load_eod = '1') then - loadNextState <= DROP_SUBSUB; - else - loadNextState <= DROP; - drop_event_comb <= '1'; - end if; - -- gk 25.07.10 - when DROP_SUBSUB => - if (load_sub_done = '1') then - if( padding_needed = '0' ) then - loadNextState <= CALCC; - else - loadNextState <= PAD0; - pad_phase_comb <= '1'; - end if; - else - loadNextState <= DROP_SUBSUB; - drop_sub_comb <= '1'; - end if; - when others => - state2 <= x"f"; - loadNextState <= LIDLE; - end case; -end process loadMachine; - --- gk 07.10.10 -PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0'; - --- gk 25.07.10 -INVALID_STATS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - dropped_lr_events_ctr <= (others => '0'); - dropped_sm_events_ctr <= (others => '0'); - headers_invalid_ctr <= (others => '0'); - dropped_ctr <= (others => '0'); - invalid_hsize_ctr <= (others => '0'); - found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10 - elsif (rst_regs = '1') then - invalid_hsize_lock <= '0'; - elsif (drop_small = '1') then - dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1"; - dropped_ctr <= dropped_ctr + x"1"; - elsif (drop_large = '1') then - dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1"; - dropped_ctr <= dropped_ctr + x"1"; - elsif (drop_headers = '1') then - headers_invalid_ctr <= headers_invalid_ctr + x"1"; - dropped_ctr <= dropped_ctr + x"1"; - elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ?? - invalid_hsize_ctr <= invalid_hsize_ctr + x"1"; - invalid_hsize_lock <= '1'; - -- gk 01.10.10 - elsif (found_empty_evt = '1') then - found_empty_evt_ctr <= found_empty_evt_ctr + x"1"; - end if; - end if; -end process INVALID_STATS_PROC; - --- gk 05.08.10 -INVALID_H_PROC : process(CLK) -begin - if rising_edge(CLK) then - load_eod_q <= load_eod; - read_size_q <= read_size; - end if; -end process INVALID_H_PROC; - --- gk 26.04.10 -READOUT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then - readout_ctr <= READOUT_CTR_IN; - readout_ctr_lock <= '0'; - elsif (pc_sos = '1') then - readout_ctr <= readout_ctr + x"1"; - end if; - end if; -end process READOUT_CTR_PROC; - ---****** --- SELECTION OF EVENT BUILDER ---****** - --- gk 29.07.11 added trigger type --- gk 27.03.10 -bank_select_proc : process( CLK ) -begin - if rising_edge( CLK ) then - -- gk 29.03.10 - if ((RESET = '1') or (rst_regs = '1')) then - bank_select <= "0000"; - trg_type <= "0000"; - -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q - elsif ((sf_rd_en = '1') and (rem_ctr = x"2")) then - bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0); - elsif ((sf_rd_en = '1') and (rem_ctr = x"1")) then - trg_type <= pc_data(7 downto 4); - end if; - end if; -end process bank_select_proc; - --- gk 07.12.10 -first_event_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - first_event <= '1'; - elsif (remove_done = '1') then - first_event <= '0'; - end if; - end if; -end process first_event_proc; - --- gk 29.07.11 added trigger type --- gk 07.12.10 -prev_bank_proc : process(CLK) -begin - if (RESET = '1') or (loadCurrentState = WAIT_PC) then - prev_bank_select <= "0000"; - prev_trg_type <= "0000"; - elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then - prev_bank_select <= bank_select; - prev_trg_type <= trg_type; - end if; -end process prev_bank_proc; - --- gk 29.03.10 -start_config_proc : process( CLK ) -begin - if rising_edge( CLK ) then - if ((RESET = '1') or (config_done = '1') or (rst_regs = '1')) then - start_config <= '0'; - elsif ((sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1')) then -- gk 01.06.10 - start_config <= '1'; - end if; - end if; -end process start_config_proc; - - ---****** --- LOAD SUBSUBEVENT ---****** - --- gk 30.03.10 -load_sub_ctr_comb <= '1' when ( ((load_sub = '1') or (drop_sub = '1')) and (load_sub_done = '0') and (sf_aempty = '0') ) - else '0'; - --- gk 30.03.10 -LOAD_SUB_CTR_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_ctr <= (others => '0'); - elsif( (load_sub_ctr_comb = '1') ) then - load_sub_ctr <= load_sub_ctr + 1; - end if; - end if; -end process LOAD_SUB_CTR_PROC; - --- gk 30.03.10 --- load_sub_done_comb <= '1' when ((load_sub_ctr = x"7") and (drop_sub = '0')) or --- ((load_sub_ctr = x"4") and (drop_sub = '1')) --- else '0'; -load_sub_done_comb <= '1' when (load_sub_ctr = x"4") else '0'; - --- gk 30.03.10 -LOAD_SUB_DONE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then -- gk 08.04.10 - load_sub_done <= '0'; - else - load_sub_done <= load_sub_done_comb; - end if; - end if; -end process LOAD_SUB_DONE_PROC; - ---****** --- EXTRACT EVENT HEADERS FROM SPLITFIFO ---****** - --- Counter for stripping the unneeded parts of the data stream, and saving the important parts -THE_REMOVE_CTR: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - rem_ctr <= (others => '0'); - elsif( (ce_rem_ctr = '1') ) then - rem_ctr <= rem_ctr + 1; - end if; - end if; -end process THE_REMOVE_CTR; - -remove_done_comb <= '1' when ( rem_ctr = x"8" ) else '0'; --( rem_ctr = x"6" ) else '0'; -- gk 29.03.10 two more for evt builder address - -THE_REM_DONE_SYNC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_rem_ctr = '1') ) then - remove_done <= '0'; - else - remove_done <= remove_done_comb; - end if; - end if; -end process THE_REM_DONE_SYNC; - --- gk 26.04.10 -TRIG_RANDOM_PROC : process(CLK) -begin - if rising_edge(CLK) then - if ((RESET = '1') or (rst_regs = '1')) then - trig_random <= (others => '0'); - elsif ((sf_rd_en = '1') and (rem_ctr = x"4")) then - trig_random <= pc_data; - end if; - end if; -end process TRIG_RANDOM_PROC; - --- extract the trigger number from splitfifo data -THE_TRG_NR_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_trig_nr <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"6") ) then -- x"4" gk 29.03.10 - pc_trig_nr(7 downto 0) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"5") ) then -- x"3" gk 29.03.10 - pc_trig_nr(15 downto 8) <= pc_data; - end if; - end if; -end process THE_TRG_NR_PROC; - --- extract the subevent size from the splitfifo data, convert it from 32b to 8b units, --- and in case of padding needed increase it accordingly -THE_SUB_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then - pc_sub_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - pc_sub_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - pc_sub_size(17 downto 10) <= pc_data; - -- gk 20.07.10 - -- gk 30.03.10 bug fixed in the way that is written below - -- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save - elsif( (calc_pad = '1') and (padding_needed = '1') ) then - pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!! - elsif( (calc_pad = '1') and (padding_needed = '0') ) then - pc_sub_size <= pc_sub_size + x"8"; - end if; - end if; -end process THE_SUB_SIZE_PROC; - --- gk 06.10.10 -MESSAGE_SIZE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - message_size <= x"0000_0028"; - elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then - message_size <= x"0000_0028"; - elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then - message_size <= x"0000_0028"; - elsif (pc_sos = '1') then - message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers - end if; - end if; -end process MESSAGE_SIZE_PROC; - --- gk 25.07.10 -ENDP_ADDRESS_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_regs = '1') then - endpoint_addr <= (others => '0'); - endp_addr_lock <= '0'; - elsif( (rem_ctr = x"a") and (endp_addr_lock = '0') ) then - endpoint_addr(7 downto 0) <= pc_data; - endp_addr_lock <= '1'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"9") ) then - endpoint_addr(15 downto 8) <= pc_data; - endp_addr_lock <= '0'; - end if; - end if; -end process ENDP_ADDRESS_PROC; - - - --- check for padding -THE_PADDING_NEEDED_PROC: process( CLK ) -begin - if rising_edge(CLK) then - if ( (RESET = '1') or (rst_regs = '1') ) then - padding_needed <= '0'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '1') ) then - padding_needed <= '1'; - elsif( (remove_done = '1') and (pc_sub_size(2) = '0') ) then - padding_needed <= '0'; - end if; - end if; -end process THE_PADDING_NEEDED_PROC; - --- number of bytes to read from split fifo -THE_READ_SIZE_PROC: process( CLK ) -begin - if( rising_edge(CLK) ) then - if ( (RESET = '1') or (rst_regs = '1') ) then --(rst_rem_ctr = '1') ) then - read_size <= (others => '0'); - elsif( (sf_rd_en = '1') and (rem_ctr = x"8") ) then -- x"6" gk 29.03.10 - read_size(9 downto 2) <= pc_data; - elsif( (sf_rd_en = '1') and (rem_ctr = x"7") ) then -- x"5" gk 29.03.10 - read_size(17 downto 10) <= pc_data; - elsif( ((sf_rd_en = '1') and (data_phase = '1')) ) then - read_size <= read_size - 1; - -- gk 25.07.10 - elsif( ((sf_rd_en = '1') and (drop_event = '1')) ) then - read_size <= read_size - 1; - end if; - end if; -end process THE_READ_SIZE_PROC; - -read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2" - ---****** --- EVENTS COUNTERS ---****** - --- gk 25.07.10 -LOADED_EVT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - loaded_events_ctr <= (others => '0'); - elsif (remove_done = '1') then - loaded_events_ctr <= loaded_events_ctr + x"1"; - end if; - end if; -end process LOADED_EVT_CTR_PROC; - --- gk 25.07.10 -CONSTR_EVENTS_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - constr_events_ctr <= (others => '0'); - elsif (pc_eod = '1') then - constr_events_ctr <= constr_events_ctr + x"1"; - end if; - end if; -end process CONSTR_EVENTS_CTR_PROC; - ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - --- Debug signals -debug(0) <= sf_full; -debug(1) <= sf_empty; -debug(2) <= sf_afull; -debug(3) <= sf_aempty; - -debug(7 downto 4) <= state2; - -debug(11 downto 8) <= state; - -dbg_bs_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - debug(15 downto 12) <= (others => '0'); - elsif ((sf_rd_en = '1') and (rem_ctr = x"3")) then - debug(15 downto 12) <= bank_select; - end if; - end if; -end process dbg_bs_proc; - -debug(16) <= config_done; -debug(17) <= '0'; --remove_done; -debug(18) <= read_done; -debug(19) <= padding_needed; - -debug(20) <= load_sub_done; - -dbg_cts_inf_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - debug(39 downto 32) <= (others => '0'); - elsif ( save_addr = '1' ) then - debug(39 downto 32) <= CTS_INFORMATION_IN; - end if; - end if; -end process dbg_cts_inf_proc; - -debug(47 downto 40) <= (others => '0'); - - -debug(63 downto 48) <= actual_message_size(15 downto 0); - -dbg_pc_sub_size_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - debug(81 downto 64) <= (others => '0'); - elsif (loadCurrentState = DECIDE) then - debug(81 downto 64) <= pc_sub_size; - end if; - end if; -end process dbg_pc_sub_size_proc; - -dbg_empty_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') or (rst_regs = '1') then - debug(84 downto 82) <= (others => '0'); - elsif (read_size = 2) then - debug(82) <= sf_empty; - elsif (read_size = 1) then - debug(83) <= sf_empty; - elsif (read_size = 0) then - debug(84) <= sf_empty; - end if; - end if; -end process dbg_empty_proc; - -debug(95 downto 85) <= (others => '0'); - -dbg_inc_ctr_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - debug(127 downto 96) <= (others => '1'); - elsif (saveCurrentState = SCLOSE) then - debug(127 downto 96) <= inc_data_ctr; - end if; - end if; -end process dbg_inc_ctr_proc; - -debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0); -debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0); - -debug(175 downto 160) <= headers_invalid_ctr(15 downto 0); -debug(191 downto 176) <= (others => '0'); - -dbg_cts_q_proc : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - cts_len_q <= (others => '0'); - cts_rnd_q <= (others => '0'); - cts_trg_q <= (others => '0'); - cts_addr_q <= (others => '0'); - elsif (cts_len_saved = '1') then - cts_len_q <= cts_len(16 downto 1); - cts_addr_q <= cts_addr; - cts_rnd_q <= cts_rnd; - cts_trg_q <= cts_trg; - end if; - end if; -end process dbg_cts_q_proc; - -debug(207 downto 192) <= cts_trg_q; -debug(223 downto 208) <= cts_rnd_q; -debug(239 downto 224) <= cts_addr_q; -debug(255 downto 240) <= cts_len_q; -debug(271 downto 256) <= first_run_trg; -debug(287 downto 272) <= first_run_addr; - -debug(303 downto 288) <= saved_events_ctr; -debug(319 downto 304) <= loaded_events_ctr; - -debug(335 downto 320) <= constr_events_ctr(15 downto 0); -debug(351 downto 336) <= dropped_ctr(15 downto 0); - -debug(367 downto 352) <= invalid_hsize_ctr; -debug(383 downto 368) <= (others => '0'); - -MONITOR_OUT(31 downto 0) <= constr_events_ctr; -MONITOR_OUT(63 downto 32) <= dropped_ctr; -MONITOR_OUT(95 downto 64) <= headers_invalid_ctr; -MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr; -MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr; -MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000"; -MONITOR_OUT(191 downto 164) <= (others => '0'); -MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10 - --- Outputs -FEE_READ_OUT <= fee_read; -CTS_ERROR_PATTERN_OUT <= cts_error_pattern; -CTS_DATA_OUT <= cts_data; -CTS_DATAREADY_OUT <= cts_dataready; -CTS_READOUT_FINISHED_OUT <= cts_readout_finished; -CTS_LENGTH_OUT <= cts_length; - -PC_SOS_OUT <= pc_sos; ---PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q; -PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1')) - or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) - -- gk 07.12.10 - or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) - else '0'; -- gk 07.10.10 -PC_DATA_OUT <= pc_data_q; -PC_WR_EN_OUT <= pc_wr_en_qq; - -PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & pc_trig_nr & trig_random; - -PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size; -PC_PADDING_OUT <= padding_needed; - -DEBUG_OUT <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd b/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd deleted file mode 100755 index 7624a16..0000000 --- a/gbe_ecp2m/trb_net16_lsm_sfp_gbe.vhd +++ /dev/null @@ -1,236 +0,0 @@ --- LinkStateMachine for SFPs (GigE) - --- Still missing: link reset features, fifo full error handling, signals on stat_op --- Take care: all input signals must be synchronous to SYSCLK, --- all output signals are synchronous to SYSCLK. --- Clock Domain Crossing is in your responsibility! - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; ---use work.trb_net_std.all; - -entity trb_net16_lsm_sfp_gbe is -port( SYSCLK : in std_logic; -- fabric clock (100MHz) - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available - -- status signals - SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) - SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) - SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) - SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) - -- control signals - FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset - LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset - USER_RESET_OUT : out std_logic; -- FPGA reset for user logic - -- debug signals - TIMING_CTR_OUT : out std_logic_vector(18 downto 0); - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture lsm_sfp_gbe of trb_net16_lsm_sfp_gbe is - --- state machine signals -type STATES is ( QRST, SLEEP, DELAY, USERRST, LINK ); -signal CURRENT_STATE, NEXT_STATE: STATES; - -signal state_bits : std_logic_vector(3 downto 0); -signal next_ce_tctr : std_logic; -signal ce_tctr : std_logic; -signal next_rst_tctr : std_logic; -signal rst_tctr : std_logic; -signal next_quad_rst : std_logic; -signal quad_rst : std_logic; -signal next_lane_rst : std_logic; -signal lane_rst : std_logic; -signal next_user_rst : std_logic; -signal user_rst : std_logic; -signal sfp_missing_q : std_logic; -signal sfp_missing_qq : std_logic; -signal sfp_los_q : std_logic; -signal sfp_los_qq : std_logic; -signal sd_rxclk_bad_q : std_logic; -signal sd_rxclk_bad_qq : std_logic; -signal sd_rxclk_bad_qqq : std_logic; -signal sd_txclk_bad_q : std_logic; -signal sd_txclk_bad_qq : std_logic; -signal sd_txclk_bad_qqq : std_logic; -signal sd_rxclk_warn_comb : std_logic; -signal sd_rxclk_warn : std_logic; -- rising edge on rlol detected -signal sd_txclk_warn_comb : std_logic; -signal sd_txclk_warn : std_logic; -- rising edge on plol detected -signal timing_ctr : std_logic_vector(18 downto 0); -signal debug : std_logic_vector(31 downto 0); - -begin - --- Debug signals -debug(31 downto 4) <= (others => '0'); -debug(3) <= sd_txclk_warn; -debug(2) <= sd_rxclk_warn; -debug(1) <= rst_tctr; -debug(0) <= ce_tctr; - --- synchronize external signals from SFP -THE_SYNC_PROC: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - -- SFP input signals - sfp_missing_qq <= sfp_missing_q; - sfp_missing_q <= sfp_missing_in; - sfp_los_qq <= sfp_los_q; - sfp_los_q <= sfp_los_in; - -- SerDes input signals - sd_rxclk_bad_qqq <= sd_rxclk_bad_qq; - sd_rxclk_bad_qq <= sd_rxclk_bad_q; - sd_rxclk_bad_q <= sd_rxclk_bad_in; - sd_txclk_bad_qqq <= sd_txclk_bad_q; - sd_txclk_bad_qq <= sd_txclk_bad_q; - sd_txclk_bad_q <= sd_txclk_bad_in; - -- edge detectors - sd_rxclk_warn <= sd_rxclk_warn_comb; - sd_txclk_warn <= sd_txclk_warn_comb; - end if; -end process THE_SYNC_PROC; - --- combinatorial part of edge detectors (rlol, see remark on page 8-63 in HB1003.pdf) -sd_rxclk_warn_comb <= '1' when ( (sd_rxclk_bad_qqq = '0') and (sd_rxclk_bad_qq = '1') ) else '0'; -sd_txclk_warn_comb <= '1' when ( (sd_txclk_bad_qqq = '0') and (sd_txclk_bad_qq = '1') ) else '0'; - --------------------------------------------------------------------------- --- Main control state machine, startup control for SFP --------------------------------------------------------------------------- - --- Timing counter for reset sequencing -THE_TIMING_COUNTER_PROC: process( sysclk, clear ) -begin - if( clear = '1' ) then - timing_ctr <= (others => '0'); - elsif( rising_edge(sysclk) ) then - if ( (rst_tctr = '1') or (sd_rxclk_warn = '1') or (sd_txclk_warn = '1') ) then - timing_ctr <= (others => '0'); - elsif( ce_tctr = '1' ) then - timing_ctr <= timing_ctr + 1; - end if; - end if; -end process THE_TIMING_COUNTER_PROC; - --- State machine --- state registers -STATE_MEM: process( sysclk, clear ) -begin - if( clear = '1' ) then - CURRENT_STATE <= QRST; - ce_tctr <= '0'; - rst_tctr <= '0'; - quad_rst <= '1'; - lane_rst <= '1'; - user_rst <= '1'; - elsif( rising_edge(sysclk) ) then - CURRENT_STATE <= NEXT_STATE; - ce_tctr <= next_ce_tctr; - rst_tctr <= next_rst_tctr; - quad_rst <= next_quad_rst; - lane_rst <= next_lane_rst; - user_rst <= next_user_rst; - end if; -end process STATE_MEM; - --- state transitions -PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_missing_qq, sfp_los_qq, sd_txclk_bad_qqq, sd_rxclk_bad_qqq, - timing_ctr(8), timing_ctr(18), timing_ctr(17), - reset ) -begin - NEXT_STATE <= QRST; -- avoid latches - next_ce_tctr <= '0'; - next_rst_tctr <= '0'; - next_quad_rst <= '0'; - next_lane_rst <= '0'; - next_user_rst <= '0'; - case CURRENT_STATE is - when QRST => -- initial state, we stay there unless CLEAR is deasserted. - state_bits <= x"0"; - if( (timing_ctr(8) = '1') ) then - NEXT_STATE <= SLEEP; -- release QUAD_RST, wait for lock of RxClock and TxClock - next_lane_rst <= '1'; - next_user_rst <= '1'; - next_rst_tctr <= '1'; - else - NEXT_STATE <= QRST; -- count delay - next_ce_tctr <= '1'; - next_quad_rst <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; - when SLEEP => -- we check for SFP presence and signal - state_bits <= x"1"; - if( (sfp_missing_qq = '0') and (sfp_los_qq = '0') ) then - NEXT_STATE <= DELAY; -- do a correctly timed QUAD reset (about 150ns) - next_ce_tctr <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - else - NEXT_STATE <= SLEEP; -- wait for SFP present signal - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; - when DELAY => -- we wait approx. 4ms and check for PLL lock in the SerDes - state_bits <= x"2"; - if( (timing_ctr(18) = '1') and (timing_ctr(17) = '1') and (sd_rxclk_bad_qqq = '0') and (sd_txclk_bad_qqq = '0') ) then - NEXT_STATE <= USERRST; -- we release lane reset - next_ce_tctr <= '1'; - next_user_rst <= '1'; - else - NEXT_STATE <= DELAY; - next_ce_tctr <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; - when USERRST => -- short delay for user reset - state_bits <= x"3"; - if( (timing_ctr(18) = '0') and (timing_ctr(17) = '0') ) then - NEXT_STATE <= LINK; - next_rst_tctr <= '1'; - else - NEXT_STATE <= USERRST; - next_ce_tctr <= '1'; - next_user_rst <= '1'; - end if; - when LINK => -- operational - state_bits <= x"4"; - NEXT_STATE <= LINK; - when others => - NEXT_STATE <= QRST; - end case; - - -- emergency jumps in case of SFP problems - if( ((sfp_missing_qq = '1') or (sfp_los_qq = '1') or (RESET = '1')) and CURRENT_STATE /= QRST ) then - NEXT_STATE <= SLEEP; -- wait for SFP present signal - next_rst_tctr <= '1'; - next_lane_rst <= '1'; - next_user_rst <= '1'; - end if; -end process; - --------------------------------------------------------------------------- --- Output signals --------------------------------------------------------------------------- -full_reset_out <= quad_rst; -lane_reset_out <= lane_rst; -user_reset_out <= user_rst; - --------------------------------------------------------------------------- --- Debug output --------------------------------------------------------------------------- -timing_ctr_out <= timing_ctr; -bsm_out <= state_bits; -debug_out <= debug; - -end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd deleted file mode 100755 index f7b381a..0000000 --- a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd +++ /dev/null @@ -1,457 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; - -entity trb_net16_med_ecp_sfp_gbe_8b is --- gk 28.04.10 -generic ( - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 -); -port( - RESET : in std_logic; - GSR_N : in std_logic; - CLK_125_OUT : out std_logic; - CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk - --SGMII connection to frame transmitter (tsmac) - FT_TX_CLK_EN_OUT : out std_logic; - FT_RX_CLK_EN_OUT : out std_logic; - FT_COL_OUT : out std_logic; - FT_CRS_OUT : out std_logic; - FT_TXD_IN : in std_logic_vector(7 downto 0); - FT_TX_EN_IN : in std_logic; - FT_TX_ER_IN : in std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable - -- Autonegotiation stuff - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); -- should be x"0020 - MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); -- advert page from link partner - MR_AN_PAGE_RX_OUT : out std_logic; - MR_AN_COMPLETE_OUT : out std_logic; - MR_AN_ENABLE_IN : in std_logic; - MR_RESTART_AN_IN : in std_logic; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) -); -end entity; - -architecture trb_net16_med_ecp_sfp_gbe_8b of trb_net16_med_ecp_sfp_gbe_8b is - --- Placer Directives -attribute HGROUP : string; --- for whole architecture -attribute HGROUP of trb_net16_med_ecp_sfp_gbe_8b : architecture is "media_interface_group"; -attribute syn_sharing : string; -attribute syn_sharing of trb_net16_med_ecp_sfp_gbe_8b : architecture is "off"; - -component serdes_gbe_0_extclock_8b is -GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"); -port( refclkp : in std_logic; - refclkn : in std_logic; - hdinp0 : in std_logic; - hdinn0 : in std_logic; - hdoutp0 : out std_logic; - hdoutn0 : out std_logic; - ff_rxiclk_ch0 : in std_logic; - ff_txiclk_ch0 : in std_logic; - ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0 : out std_logic; - ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - refck2core : out std_logic; - ffs_plol : out std_logic - ); -end component; - -component serdes_gbe_0_intclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); - port ( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - ffs_plol : out std_logic); - -end component; - -component sgmii_gbe_pcs32 -port( rst_n : in std_logic; - signal_detect : in std_logic; - gbe_mode : in std_logic; - sgmii_mode : in std_logic; - operational_rate : in std_logic_vector(1 downto 0); - debug_link_timer_short : in std_logic; - rx_compensation_err : out std_logic; - tx_clk_125 : in std_logic; - tx_clock_enable_source : out std_logic; - tx_clock_enable_sink : in std_logic; - tx_d : in std_logic_vector(7 downto 0); - tx_en : in std_logic; - tx_er : in std_logic; - rx_clk_125 : in std_logic; - rx_clock_enable_source : out std_logic; - rx_clock_enable_sink : in std_logic; - rx_d : out std_logic_vector(7 downto 0); - rx_dv : out std_logic; - rx_er : out std_logic; - col : out std_logic; - crs : out std_logic; - tx_data : out std_logic_vector(7 downto 0); - tx_kcntl : out std_logic; - tx_disparity_cntl : out std_logic; - serdes_recovered_clk : in std_logic; - rx_data : in std_logic_vector(7 downto 0); - rx_even : in std_logic; - rx_kcntl : in std_logic; - rx_disp_err : in std_logic; - rx_cv_err : in std_logic; - rx_err_decode_mode : in std_logic; - mr_an_complete : out std_logic; - mr_page_rx : out std_logic; - mr_lp_adv_ability : out std_logic_vector(15 downto 0); - mr_main_reset : in std_logic; - mr_an_enable : in std_logic; - mr_restart_an : in std_logic; - mr_adv_ability : in std_logic_vector(15 downto 0) - ); -end component; - -component trb_net16_lsm_sfp_gbe is -port( SYSCLK : in std_logic; -- fabric clock (100MHz) - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available - -- status signals - SFP_MISSING_IN : in std_logic; -- SFP Missing ('1' = no SFP mounted, '0' = SFP in place) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established) - SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost) - SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked) - SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked) - -- control signals - FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset - LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset - USER_RESET_OUT : out std_logic; -- FPGA reset for user logic - -- debug signals - TIMING_CTR_OUT : out std_logic_vector(18 downto 0); - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); -end component; - -signal refclkcore : std_logic; - -signal sd_link_ok : std_logic; -signal sd_link_error : std_logic_vector(2 downto 0); - -signal sd_tx_data : std_logic_vector(7 downto 0); -signal sd_tx_kcntl : std_logic; -signal sd_tx_correct_disp : std_logic; -signal sd_tx_clk : std_logic; - -signal sd_rx_data : std_logic_vector(7 downto 0); -signal sd_rx_even : std_logic; -signal sd_rx_kcntl : std_logic; -signal sd_rx_disp_error : std_logic; -signal sd_rx_cv_error : std_logic; -signal sd_rx_clk : std_logic; - -signal pcs_mr_an_complete : std_logic; -signal pcs_mr_ability : std_logic_vector(15 downto 0); -signal pcs_mr_page_rx : std_logic; -signal pcs_mr_reset : std_logic; - -signal pcs_tx_clk_en : std_logic; -signal pcs_rx_clk_en : std_logic; -signal pcs_rx_comp_err : std_logic; - -signal pcs_rx_d : std_logic_vector(7 downto 0); -signal pcs_rx_dv : std_logic; -signal pcs_rx_er : std_logic; - -signal sd_rx_debug : std_logic_vector(15 downto 0); -signal sd_tx_debug : std_logic_vector(15 downto 0); - -signal buf_stat_debug : std_logic_vector(63 downto 0); - -signal quad_rst : std_logic; -signal lane_rst : std_logic; -signal user_rst : std_logic; - -signal reset_bsm : std_logic_vector(3 downto 0); -signal reset_debug : std_logic_vector(31 downto 0); - -begin - --- Reset state machine for SerDes -THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe -port map( - SYSCLK => refclkcore, - RESET => '0', -- really? - CLEAR => RESET, -- from 100MHz PLL, includes async part - -- status signals - SFP_MISSING_IN => SD_PRSNT_N_IN, - SFP_LOS_IN => SD_LOS_IN, - SD_LINK_OK_IN => '1', -- not used - SD_LOS_IN => '0', -- not used - SD_TXCLK_BAD_IN => sd_link_error(2), -- plol - SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol - -- control signals - FULL_RESET_OUT => quad_rst, - LANE_RESET_OUT => lane_rst, - USER_RESET_OUT => user_rst, - -- debug signals - TIMING_CTR_OUT => open, - BSM_OUT => reset_bsm, - DEBUG_OUT => reset_debug -); - --- gk 28.04.10 --- SerDes for GbE -clk_int : if (USE_125MHZ_EXTCLK = 0) generate - - refclkcore <= CLK_125_IN; - - SERDES_GBE : serdes_gbe_0_intclock_8b - port map( - core_txrefclk => CLK_125_IN, - core_rxrefclk => CLK_125_IN, - hdinp0 => SD_RXD_P_IN, - hdinn0 => SD_RXD_N_IN, - hdoutp0 => SD_TXD_P_OUT, - hdoutn0 => SD_TXD_N_OUT, - ff_rxiclk_ch0 => sd_rx_clk, - ff_txiclk_ch0 => sd_tx_clk, - ff_ebrd_clk_0 => sd_rx_clk, - ff_txdata_ch0 => sd_tx_data, - ff_rxdata_ch0 => sd_rx_data, - ff_tx_k_cntrl_ch0 => sd_tx_kcntl, - ff_rx_k_cntrl_ch0 => sd_rx_kcntl, - ff_rxfullclk_ch0 => sd_rx_clk, - ff_xmit_ch0 => '0', - ff_correct_disp_ch0 => sd_tx_correct_disp, - ff_disp_err_ch0 => sd_rx_disp_error, - ff_cv_ch0 => sd_rx_cv_error, - ff_rx_even_ch0 => sd_rx_even, - ffc_rrst_ch0 => '0', - ffc_lane_tx_rst_ch0 => lane_rst, - ffc_lane_rx_rst_ch0 => lane_rst, - ffc_txpwdnb_ch0 => '1', - ffc_rxpwdnb_ch0 => '1', - ffs_rlos_lo_ch0 => sd_link_error(0), - ffs_ls_sync_status_ch0 => sd_link_ok, - ffs_rlol_ch0 => sd_link_error(1), - oob_out_ch0 => open, - ffc_macro_rst => '0', - ffc_quad_rst => quad_rst, - ffc_trst => '0', - ff_txfullclk => sd_tx_clk, - ff_txhalfclk => open, - ffs_plol => sd_link_error(2) - ); -end generate clk_int; - -clk_ext : if (USE_125MHZ_EXTCLK = 1) generate - SERDES_GBE : serdes_gbe_0_extclock_8b - port map( -- SerDes connection to outside world - refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input - refclkn => SD_REFCLK_N_IN, - hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input - hdinn0 => SD_RXD_N_IN, - hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output - hdoutn0 => SD_TXD_N_OUT, - refck2core => refclkcore, -- reference clock from input - -- RX part - ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output - ff_rxiclk_ch0 => sd_rx_clk, - ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice - ff_rxdata_ch0 => sd_rx_data, -- RX data output - ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output - ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output) - ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error - ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error - -- TX part - ff_txfullclk => sd_tx_clk, -- TX full clock output - ff_txiclk_ch0 => sd_tx_clk, - ff_txhalfclk => open, - ff_txdata_ch0 => sd_tx_data, -- TX data input - ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input - ff_xmit_ch0 => '0', -- for autonegotiation (input) - ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input) - -- Resets and power down - ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high) - ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel - ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel - ffc_rrst_ch0 => '0', -- '0' for normal operation - ffc_macro_rst => '0', -- '0' for normal operation - ffc_trst => '0', -- '0' for normal operation - ffc_txpwdnb_ch0 => '1', -- must be '1' - ffc_rxpwdnb_ch0 => '1', -- must be '1' - -- Status outputs - ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas? - ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel - ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL - ffs_plol => sd_link_error(2), -- loss of lock in TX PLL - oob_out_ch0 => open -- not needed - ); -end generate clk_ext; - -SD_RX_DATA_PROC: process( sd_rx_clk ) -begin - if( rising_edge(sd_rx_clk) ) then - sd_rx_debug(15 downto 12) <= (others => '0'); - sd_rx_debug(11) <= sd_rx_disp_error; - sd_rx_debug(10) <= sd_rx_even; - sd_rx_debug(9) <= sd_rx_cv_error; - sd_rx_debug(8) <= sd_rx_kcntl; - sd_rx_debug(7 downto 0) <= sd_rx_data; - end if; -end process SD_RX_DATA_PROC; - -SD_TX_DATA_PROC: process( sd_tx_clk ) -begin - if( rising_edge(sd_tx_clk) ) then - sd_tx_debug(15 downto 10) <= (others => '0'); - sd_tx_debug(9) <= sd_tx_correct_disp; - sd_tx_debug(8) <= sd_tx_kcntl; - sd_tx_debug(7 downto 0) <= sd_tx_data; - end if; -end process SD_TX_DATA_PROC; - -buf_stat_debug(63 downto 40) <= (others => '0'); -buf_stat_debug(39 downto 36) <= reset_debug(3 downto 0); -buf_stat_debug(35 downto 32) <= reset_bsm; --- logic analyzer signals -buf_stat_debug(31) <= pcs_mr_page_rx; -buf_stat_debug(30) <= pcs_mr_reset; --pcs_mr_an_complete; -buf_stat_debug(28 downto 26) <= reset_bsm(2 downto 0); -buf_stat_debug(25 downto 23) <= sd_link_error(2 downto 0); -buf_stat_debug(22) <= sd_link_ok; -buf_stat_debug(21 downto 12) <= sd_tx_debug(9 downto 0); -buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0); - - -SGMII_GBE_PCS : sgmii_gbe_pcs32 -port map( - rst_n => GSR_N, - signal_detect => sd_link_ok, - gbe_mode => '1', - sgmii_mode => MR_MODE_IN, - operational_rate => "10", - debug_link_timer_short => '0', - rx_compensation_err => pcs_rx_comp_err, - -- MAC interface - tx_clk_125 => refclkcore, -- original clock from SerDes - tx_clock_enable_source => pcs_tx_clk_en, - tx_clock_enable_sink => pcs_tx_clk_en, - tx_d => FT_TXD_IN, -- TX data from MAC - tx_en => FT_TX_EN_IN, -- TX data enable from MAC - tx_er => FT_TX_ER_IN, -- TX error from MAC - rx_clk_125 => refclkcore, -- original clock from SerDes - rx_clock_enable_source => pcs_rx_clk_en, - rx_clock_enable_sink => pcs_rx_clk_en, - rx_d => pcs_rx_d, -- RX data to MAC - rx_dv => pcs_rx_dv, -- RX data enable to MAC - rx_er => pcs_rx_er, -- RX error to MAC - col => FT_COL_OUT, - crs => FT_CRS_OUT, - -- SerDes interface - tx_data => sd_tx_data, -- TX data to SerDes - tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes - tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes) - serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream - rx_data => sd_rx_data, -- RX data from SerDes - rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes - rx_err_decode_mode => '0', -- receive error control mode fixed to normal - rx_even => '0', -- unused (receive error control mode = normal, tie to GND) - rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes - rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes - -- Autonegotiation stuff - mr_an_complete => pcs_mr_an_complete, - mr_page_rx => pcs_mr_page_rx, - mr_lp_adv_ability => pcs_mr_ability, - mr_main_reset => pcs_mr_reset, - mr_an_enable => MR_AN_ENABLE_IN, - mr_restart_an => MR_RESTART_AN_IN, - mr_adv_ability => MR_ADV_ABILITY_IN -); - -pcs_mr_reset <= MR_RESET_IN or RESET or user_rst; - -FT_TX_CLK_EN_OUT <= pcs_tx_clk_en; -- to MAC -FT_RX_CLK_EN_OUT <= pcs_rx_clk_en; -- to MAC - -MR_AN_LP_ABILITY_OUT <= pcs_mr_ability; -MR_AN_COMPLETE_OUT <= pcs_mr_an_complete; -MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx; - --- Clock games -CLK_125_OUT <= refclkcore; - --- Fakes -STAT_OP <= (others => '0'); -SD_TXDIS_OUT <= '0'; -- enable -STAT_DEBUG <= buf_stat_debug; - -end architecture; \ No newline at end of file diff --git a/gbe_ecp2m/trb_net_gbe_components.vhd b/gbe_ecp2m/trb_net_gbe_components.vhd deleted file mode 100644 index 2091080..0000000 --- a/gbe_ecp2m/trb_net_gbe_components.vhd +++ /dev/null @@ -1,309 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -library work; -use work.trb_net_std.all; - -package trb_net_gbe_components is - --- gk 01.07.10 -component trb_net16_ipu2gbe is -port( - CLK : in std_logic; - RESET : in std_logic; - -- IPU interface directed toward the CTS - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- slow control interface - START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size - BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address - CONFIG_DONE_IN : in std_logic; -- configuration finished - DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE - DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet - MULT_EVT_ENABLE_IN : in std_logic; - MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10 - MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10 - READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10 - READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10 - -- PacketConstructor interface - ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10 - PC_WR_EN_OUT : out std_logic; - PC_DATA_OUT : out std_logic_vector (7 downto 0); - PC_READY_IN : in std_logic; - PC_SOS_OUT : out std_logic; - PC_EOS_OUT : out std_logic; -- gk 07.10.10 - PC_EOD_OUT : out std_logic; - PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); - PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); - PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(223 downto 0); - DEBUG_OUT : out std_logic_vector(383 downto 0) -); -end component; - -component trb_net16_gbe_packet_constr is -port( - RESET : in std_logic; - CLK : in std_logic; - MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10 - -- ports for user logic - PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic - PC_DATA_IN : in std_logic_vector(7 downto 0); - PC_READY_OUT : out std_logic; - PC_START_OF_SUB_IN : in std_logic; - PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10 - PC_END_OF_DATA_IN : in std_logic; - -- queue and subevent layer headers - PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap - PC_PADDING_IN : in std_logic; -- gk 29.03.10 - PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap - PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap - PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap! - PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap - PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP - PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 - -- FrameConstructor ports - FC_WR_EN_OUT : out std_logic; - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_H_READY_IN : in std_logic; - FC_READY_IN : in std_logic; - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_frame_constr is -port( - -- ports for user logic - RESET : in std_logic; - CLK : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - -- - WR_EN_IN : in std_logic; - DATA_IN : in std_logic_vector(7 downto 0); - START_OF_DATA_IN : in std_logic; - END_OF_DATA_IN : in std_logic; - IP_F_SIZE_IN : in std_logic_vector(15 downto 0); - UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation - HEADERS_READY_OUT : out std_logic; - READY_OUT : out std_logic; - DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - IHL_VERSION_IN : in std_logic_vector(7 downto 0); - TOS_IN : in std_logic_vector(7 downto 0); - IDENTIFICATION_IN : in std_logic_vector(15 downto 0); - FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); - TTL_IN : in std_logic_vector(7 downto 0); - PROTOCOL_IN : in std_logic_vector(7 downto 0); - FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10 - -- ports for packetTransmitter - RD_CLK : in std_logic; -- 125MHz clock!!! - FT_DATA_OUT : out std_logic_vector(8 downto 0); - FT_TX_EMPTY_OUT : out std_logic; - FT_TX_RD_EN_IN : in std_logic; - FT_START_OF_PACKET_OUT : out std_logic; - FT_TX_DONE_IN : in std_logic; - FT_TX_DISCFRM_IN : in std_logic; - -- debug ports - BSM_CONSTR_OUT : out std_logic_vector(7 downto 0); - BSM_TRANS_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_gbe_frame_trans is -port ( - CLK : in std_logic; - RESET : in std_logic; - LINK_OK_IN : in std_logic; -- gk 03.08.10 - TX_MAC_CLK : in std_logic; - TX_EMPTY_IN : in std_logic; - START_OF_PACKET_IN : in std_logic; - DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC - -- NEW PORTS - HADDR_OUT : out std_logic_vector(7 downto 0); - HDATA_OUT : out std_logic_vector(7 downto 0); - HCS_OUT : out std_logic; - HWRITE_OUT : out std_logic; - HREAD_OUT : out std_logic; - HREADY_IN : in std_logic; - HDATA_EN_IN : in std_logic; - TX_FIFOAVAIL_OUT : out std_logic; - TX_FIFOEOF_OUT : out std_logic; - TX_FIFOEMPTY_OUT : out std_logic; - TX_DONE_IN : in std_logic; - TX_DISCFRM_IN : in std_logic; - -- Debug - BSM_INIT_OUT : out std_logic_vector(3 downto 0); - BSM_MAC_OUT : out std_logic_vector(3 downto 0); - BSM_TRANS_OUT : out std_logic_vector(3 downto 0); - DBG_RD_DONE_OUT : out std_logic; - DBG_INIT_DONE_OUT : out std_logic; - DBG_ENABLED_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) -); -end component; - -component trb_net16_med_ecp_sfp_gbe_8b is --- gk 28.04.10 -generic ( - USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 -); -port( - RESET : in std_logic; - GSR_N : in std_logic; - CLK_125_OUT : out std_logic; - CLK_125_IN : in std_logic; -- gk 28.04.10 used when intclk - --SGMII connection to frame transmitter (tsmac) - FT_TX_CLK_EN_OUT : out std_logic; - FT_RX_CLK_EN_OUT : out std_logic; - FT_COL_OUT : out std_logic; - FT_CRS_OUT : out std_logic; - FT_TXD_IN : in std_logic_vector(7 downto 0); - FT_TX_EN_IN : in std_logic; - FT_TX_ER_IN : in std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable - -- Autonegotiation stuff - MR_RESET_IN : in std_logic; - MR_MODE_IN : in std_logic; - MR_ADV_ABILITY_IN : in std_logic_vector(15 downto 0); - MR_AN_LP_ABILITY_OUT : out std_logic_vector(15 downto 0); - MR_AN_PAGE_RX_OUT : out std_logic; - MR_AN_COMPLETE_OUT : out std_logic; - MR_AN_ENABLE_IN : in std_logic; - MR_RESTART_AN_IN : in std_logic; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) -); -end component; - -component gbe_setup is -port( - CLK : in std_logic; - RESET : in std_logic; - - -- interface to regio bus - BUS_ADDR_IN : in std_logic_vector(7 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - - GBE_TRIG_NR_IN : in std_logic_vector(31 downto 0); - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT : out std_logic_vector(31 downto 0); - GBE_SUBEVENT_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_QUEUE_DEC_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_PACKET_OUT : out std_logic_vector(31 downto 0); - GBE_MIN_PACKET_OUT : out std_logic_vector(31 downto 0); - GBE_MAX_FRAME_OUT : out std_logic_vector(15 downto 0); - GBE_USE_GBE_OUT : out std_logic; - GBE_USE_TRBNET_OUT : out std_logic; - GBE_USE_MULTIEVENTS_OUT : out std_logic; - GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10 - GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 - GBE_DELAY_OUT : out std_logic_vector(31 downto 0); - GBE_ALLOW_LARGE_OUT : out std_logic; - GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10 - -- gk 28.07.10 - MONITOR_BYTES_IN : in std_logic_vector(31 downto 0); - MONITOR_SENT_IN : in std_logic_vector(31 downto 0); - MONITOR_DROPPED_IN : in std_logic_vector(31 downto 0); - MONITOR_SM_IN : in std_logic_vector(31 downto 0); - MONITOR_LR_IN : in std_logic_vector(31 downto 0); - MONITOR_HDR_IN : in std_logic_vector(31 downto 0); - MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0); - MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0); - MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10 - MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10 - -- gk 01.06.10 - DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE3_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE4_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE5_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE6_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE7_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE8_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE9_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE10_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE11_IN : in std_logic_vector(31 downto 0); - DBG_IPU2GBE12_IN : in std_logic_vector(31 downto 0); - DBG_PC1_IN : in std_logic_vector(31 downto 0); - DBG_PC2_IN : in std_logic_vector(31 downto 0); - DBG_FC1_IN : in std_logic_vector(31 downto 0); - DBG_FC2_IN : in std_logic_vector(31 downto 0); - DBG_FT1_IN : in std_logic_vector(31 downto 0); - DBG_FT2_IN : in std_logic_vector(31 downto 0); - DBG_FIFO_RD_EN_OUT : out std_logic; - DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0) - --DBG_FIFO_RESET_OUT : out std_logic -); -end component; - - -component ip_configurator is -port( - CLK : in std_logic; - RESET : in std_logic; - -- configuration interface - START_CONFIG_IN : in std_logic; -- start configuration run - BANK_SELECT_IN : in std_logic_vector(3 downto 0); -- selects config bank - CONFIG_DONE_OUT : out std_logic; -- configuration run ended, new values can be used - MEM_ADDR_OUT : out std_logic_vector(7 downto 0); -- address for - MEM_DATA_IN : in std_logic_vector(31 downto 0); -- data from IP memory - MEM_CLK_OUT : out std_logic; -- clock for BlockRAM - -- information for IP cores - DEST_MAC_OUT : out std_logic_vector(47 downto 0); -- destination MAC address - DEST_IP_OUT : out std_logic_vector(31 downto 0); -- destination IP address - DEST_UDP_OUT : out std_logic_vector(15 downto 0); -- destination port - SRC_MAC_OUT : out std_logic_vector(47 downto 0); -- source MAC address - SRC_IP_OUT : out std_logic_vector(31 downto 0); -- source IP address - SRC_UDP_OUT : out std_logic_vector(15 downto 0); -- source port - MTU_OUT : out std_logic_vector(15 downto 0); -- MTU size (max frame size) - -- Debug - DEBUG_OUT : out std_logic_vector(31 downto 0) -); -end component; - -end package; \ No newline at end of file diff --git a/gbe_trb/base/trb_net16_gbe_mac_control.vhd b/gbe_trb/base/trb_net16_gbe_mac_control.vhd index 4c29bd5..130c151 100644 --- a/gbe_trb/base/trb_net16_gbe_mac_control.vhd +++ b/gbe_trb/base/trb_net16_gbe_mac_control.vhd @@ -84,10 +84,12 @@ reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode MAC_CONF_MACHINE_PROC : process(CLK) begin - if RESET = '1' then - mac_conf_current_state <= IDLE; - elsif rising_edge(CLK) then - mac_conf_current_state <= mac_conf_next_state; + if( rising_edge(CLK) ) then + if( RESET = '1' ) then + mac_conf_current_state <= IDLE; + else + mac_conf_current_state <= mac_conf_next_state; + end if; end if; end process MAC_CONF_MACHINE_PROC; diff --git a/gbe_trb_ecp3/base/forwarder.vhd b/gbe_trb_ecp3/base/forwarder.vhd deleted file mode 100644 index e9cda4c..0000000 --- a/gbe_trb_ecp3/base/forwarder.vhd +++ /dev/null @@ -1,82 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity forwarder is - port( - CLK : in std_logic; - CLEAR : in std_logic; - RESET : in std_logic; - -- - FRAME_AVAIL_IN : in std_logic; - FIFO_FULL_IN : in std_logic; - FRAME_REQ_OUT : out std_logic; - FRAME_ACK_IN : in std_logic; - -- - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity forwarder; - -architecture forwarder_arch of forwarder is - --- Components - --- state machine signals - type state_t is (IDLE,REQ,ACK); - signal STATE, NEXT_STATE : state_t; - --- Signals - signal rb_full : std_logic; - signal req_x : std_logic; - signal req_q : std_logic; - -begin - - ----------------------------------------------------------- - -- statemachine: clocked process - ----------------------------------------------------------- - THE_FSM: process( CLK, CLEAR ) - begin - if ( CLEAR = '1' ) then - STATE <= IDLE; - req_q <= '0'; - elsif( rising_edge(CLK) ) then - STATE <= NEXT_STATE; - req_q <= req_x; - end if; - end process THE_FSM; - - THE_STATE_TRANSITIONS: process( STATE, FIFO_FULL_IN, FRAME_AVAIL_IN, FRAME_ACK_IN ) - begin - req_x <= '0'; - - case STATE is - - when IDLE => - if( (FIFO_FULL_IN = '0') and (FRAME_AVAIL_IN = '1') ) then - NEXT_STATE <= REQ; - req_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; - - when REQ => - if( FRAME_ACK_IN = '1' ) then - NEXT_STATE <= ACK; - else - NEXT_STATE <= REQ; - end if; - - when ACK => - NEXT_STATE <= IDLE; - - when others => - NEXT_STATE <= IDLE; - end case; - end process THE_STATE_TRANSITIONS; - - FRAME_REQ_OUT <= req_q; - -end architecture; diff --git a/gbe_trb_ecp3/base/gather_ports.vhd b/gbe_trb_ecp3/base/gather_ports.vhd deleted file mode 100644 index 18eedb6..0000000 --- a/gbe_trb_ecp3/base/gather_ports.vhd +++ /dev/null @@ -1,176 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity gather_ports is - port( - CLK : in std_logic; - CLEAR : in std_logic; - RESET : in std_logic; - -- - FRAME_AVAIL_IN : in std_logic_vector(15 downto 0) := (others => '0'); - FRAME_REQ_OUT : out std_logic_vector(15 downto 0); - FRAME_ACK_IN : in std_logic_vector(15 downto 0) := (others => '0'); - PORT_SELECT_OUT : out std_logic_vector(15 downto 0); - CYCLE_DONE_OUT : out std_logic; - -- - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity gather_ports; - -architecture gather_ports_arch of gather_ports is - --- Components - --- state machine signals - type state_t is (IDLE, STORE, DO_PORTS, DELAY, CLEANUP); - signal STATE, NEXT_STATE : state_t; - --- Signals - signal gather_needed_x : std_logic; - signal store_ports_x : std_logic; - signal all_ports_done_x : std_logic; - signal stored_ports : std_logic_vector(15 downto 0); - signal next_port_x : std_logic_vector(15 downto 0); - signal select_ports : std_logic_vector(15 downto 0); - signal req_ports : std_logic_vector(15 downto 0); - -begin - - -- we need to start a gather cycle if any src port has frames available - gather_needed_x <= '1' when FRAME_AVAIL_IN /= x"0000" else '0'; - - -- store the src port status - GEN_REGS: for I in 0 to 15 generate - THE_SRC_STORE_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - stored_ports(I) <= '0'; - elsif( rising_edge(CLK) ) then - if( store_ports_x = '1' ) then - stored_ports(I) <= FRAME_AVAIL_IN(I); - elsif( FRAME_ACK_IN(I) = '1' ) then - stored_ports(I) <= '0'; - end if; - end if; - end process THE_SRC_STORE_PROC; - end generate; - - all_ports_done_x <= '1' when stored_ports = x"0000" else '0'; - - -- select the port data - THE_SELECT_PORT_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - select_ports <= (others => '0'); - elsif( rising_edge(CLK) ) then - select_ports <= next_port_x; - end if; - end process THE_SELECT_PORT_PROC; - - PORT_SELECT_OUT <= select_ports; - - -- port frame request, one clock cycle pulse - req_ports <= not select_ports and next_port_x when rising_edge(CLK); - - FRAME_REQ_OUT <= req_ports; - - CYCLE_DONE_OUT <= '1' when STATE = CLEANUP else '0'; - - -- priority decoced "next port to serve" signals - THE_NEXT_PORT_PROC: process( stored_ports ) - begin - if ( stored_ports(0) = '1' ) then - next_port_x <= x"0001"; - elsif( stored_ports(1) = '1' ) then - next_port_x <= x"0002"; - elsif( stored_ports(2) = '1' ) then - next_port_x <= x"0004"; - elsif( stored_ports(3) = '1' ) then - next_port_x <= x"0008"; - elsif( stored_ports(4) = '1' ) then - next_port_x <= x"0010"; - elsif( stored_ports(5) = '1' ) then - next_port_x <= x"0020"; - elsif( stored_ports(6) = '1' ) then - next_port_x <= x"0040"; - elsif( stored_ports(7) = '1' ) then - next_port_x <= x"0080"; - elsif( stored_ports(8) = '1' ) then - next_port_x <= x"0100"; - elsif( stored_ports(9) = '1' ) then - next_port_x <= x"0200"; - elsif( stored_ports(10) = '1' ) then - next_port_x <= x"0400"; - elsif( stored_ports(11) = '1' ) then - next_port_x <= x"0800"; - elsif( stored_ports(12) = '1' ) then - next_port_x <= x"1000"; - elsif( stored_ports(13) = '1' ) then - next_port_x <= x"2000"; - elsif( stored_ports(14) = '1' ) then - next_port_x <= x"4000"; - elsif( stored_ports(15) = '1' ) then - next_port_x <= x"8000"; - else - next_port_x <= x"0000"; - end if; - end process THE_NEXT_PORT_PROC; - - ----------------------------------------------------------- - -- statemachine: clocked process - ----------------------------------------------------------- - THE_FSM: process( CLK, CLEAR ) - begin - if ( CLEAR = '1' ) then - STATE <= IDLE; - elsif( rising_edge(CLK) ) then - STATE <= NEXT_STATE; - end if; - end process THE_FSM; - - THE_STATE_TRANSITIONS: process( STATE, gather_needed_x, all_ports_done_x ) - begin - store_ports_x <= '0'; - - case STATE is - - when IDLE => - if( gather_needed_x = '1' ) then - NEXT_STATE <= STORE; - store_ports_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; - - when STORE => - NEXT_STATE <= DO_PORTS; - - when DO_PORTS => - if( all_ports_done_x = '1' ) then - NEXT_STATE <= DELAY; - else - NEXT_STATE <= DO_PORTS; - end if; - - when DELAY => - NEXT_STATE <= CLEANUP; - - when CLEANUP => - if( gather_needed_x = '1' ) then - NEXT_STATE <= STORE; - store_ports_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; - - when others => - NEXT_STATE <= IDLE; - end case; - end process THE_STATE_TRANSITIONS; - - - -end architecture; diff --git a/gbe_trb_ecp3/base/gbe_lsm.vhd b/gbe_trb_ecp3/base/gbe_lsm.vhd deleted file mode 100644 index 4f284ae..0000000 --- a/gbe_trb_ecp3/base/gbe_lsm.vhd +++ /dev/null @@ -1,137 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity gbe_lsm is - port( - CLK : in std_logic; - CLEAR : in std_logic; - RESET : in std_logic; - -- - MAC_AN_COMPLETE_IN : in std_logic; -- PCS Autonegotiation completed - MAC_READY_CONF_IN : in std_logic; -- MAC configuration completed - MAC_RECONF_OUT : out std_logic; -- start MAC configuration - -- - LINK_ACTIVE_OUT : out std_logic; - -- - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity gbe_lsm; - -architecture gbe_lsm_arch of gbe_lsm is - --- Components - --- state machine signals - type state_t is (INACTIVE,WAIT_PCS,ENABLE_MAC,DELAY,ACTIVATED); - signal STATE, NEXT_STATE : state_t; - --- Signals - signal dly_ctr : unsigned(15 downto 0); - signal ce_dly_ctr : std_logic; - signal rst_dly_ctr : std_logic; - signal dly_ctr_done : std_logic; - signal reconf_mac : std_logic; - -begin - - MAC_RECONF_OUT <= reconf_mac; - - LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0'; - - THE_DLY_CTR: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - dly_ctr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if ( rst_dly_ctr = '1' ) then - dly_ctr <= (others => '0'); - elsif( ce_dly_ctr = '1' ) then - dly_ctr <= dly_ctr + 1; - end if; - end if; - end process THE_DLY_CTR; - - dly_ctr_done <= '1' when dly_ctr = x"ffff" else '0'; - - ----------------------------------------------------------- - -- statemachine: clocked process - ----------------------------------------------------------- - THE_FSM: process( CLK, CLEAR ) - begin - if ( CLEAR = '1' ) then - STATE <= INACTIVE; - elsif( rising_edge(CLK) ) then - STATE <= NEXT_STATE; - end if; - end process THE_FSM; - - THE_STATE_TRANSITIONS: process( STATE, MAC_AN_COMPLETE_IN, MAC_READY_CONF_IN, dly_ctr_done ) - begin - reconf_mac <= '0'; - ce_dly_ctr <= '0'; - rst_dly_ctr <= '0'; - - case STATE is - - when INACTIVE => - rst_dly_ctr <= '1'; - if( MAC_AN_COMPLETE_IN = '1' ) then - NEXT_STATE <= WAIT_PCS; - else - NEXT_STATE <= INACTIVE; - end if; - - when WAIT_PCS => - ce_dly_ctr <= '1'; - if( MAC_AN_COMPLETE_IN = '0' ) then - NEXT_STATE <= INACTIVE; - else - if( dly_ctr_done = '1' ) then - NEXT_STATE <= ENABLE_MAC; - reconf_mac <= '1'; - else - NEXT_STATE <= WAIT_PCS; - end if; - end if; - - when ENABLE_MAC => - rst_dly_ctr <= '1'; - if( MAC_AN_COMPLETE_IN = '0' ) then - NEXT_STATE <= INACTIVE; - else - if( MAC_READY_CONF_IN = '1' ) then - NEXT_STATE <= DELAY; - else - NEXT_STATE <= ENABLE_MAC; - end if; - end if; - - when DELAY => - ce_dly_ctr <= '1'; - if( MAC_AN_COMPLETE_IN = '0' ) then - NEXT_STATE <= INACTIVE; - else - if( dly_ctr_done = '1' ) then - NEXT_STATE <= ACTIVATED; - else - NEXT_STATE <= DELAY; - end if; - end if; - - when ACTIVATED => - rst_dly_ctr <= '1'; - if( MAC_AN_COMPLETE_IN = '0' ) then - NEXT_STATE <= INACTIVE; - else - NEXT_STATE <= ACTIVATED; - end if; - - when others => - NEXT_STATE <= INACTIVE; - end case; - end process THE_STATE_TRANSITIONS; - -end architecture; diff --git a/gbe_trb_ecp3/base/gbe_med_fifo.vhd b/gbe_trb_ecp3/base/gbe_med_fifo.vhd index 8ed6b65..ef120d7 100644 --- a/gbe_trb_ecp3/base/gbe_med_fifo.vhd +++ b/gbe_trb_ecp3/base/gbe_med_fifo.vhd @@ -15,10 +15,10 @@ entity gbe_med_fifo is ); port( RESET : in std_logic; - GSR_N : in std_logic; - CLK_SYS : in std_logic; + RESET_N : in std_logic; + CLEAR : in std_logic; + CLEAR_N : in std_logic; CLK_125 : in std_logic; - CLK_125_RX : out std_logic_vector(3 downto 0); -- FIFO interface RX FIFO_DATA_OUT : out std_logic_vector(4 * 9 - 1 downto 0); FIFO_FULL_IN : in std_logic_vector(3 downto 0); @@ -47,7 +47,7 @@ entity gbe_med_fifo is ); end entity gbe_med_fifo; -architecture RTL of gbe_med_fifo is +architecture gbe_med_fifo_arch of gbe_med_fifo is component sgmii_gbe_pcs42 port( @@ -204,7 +204,6 @@ architecture RTL of gbe_med_fifo is signal rx_pcs_rst_q : std_logic_vector(3 downto 0); signal rx_serdes_rst : std_logic_vector(3 downto 0); signal rx_serdes_rst_q : std_logic_vector(3 downto 0); - signal init_quad : std_logic; signal tx_plol_lol : std_logic; signal debug : std_logic_vector(63 downto 0); @@ -236,10 +235,13 @@ architecture RTL of gbe_med_fifo is signal led_timer_done : std_logic; signal led_activity_x : std_logic_vector(3 downto 0); signal led_activity : std_logic_vector(4 * 2 - 1 downto 0); - -begin - init_quad <= not GSR_N; + attribute HGROUP : string; +-- attribute BBOX : string; + attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group"; +-- attribute BBOX of ddmtd_arch : architecture is "2,2"; + +begin gbe_serdes: entity serdes_gbe_4ch_ds port map( @@ -367,7 +369,7 @@ begin fpga_txrefclk => CLK_125, tx_serdes_rst_c => '0', tx_pll_lol_qd_s => tx_plol_lol, - rst_qd_c => init_quad, + rst_qd_c => CLEAR, -- ONLY ONCE serdes_rst_qd_c => '0', tx_sync_qd_c => '0' ); @@ -385,7 +387,7 @@ begin -- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock! THE_MAIN_RX_RST: main_rx_reset_RS port map( - CLEAR => init_quad, + CLEAR => CLEAR, CLK_REF => CLK_125, CDR_LOL_IN => rx_cdr_lol(i), CV_IN => sd_rx_cv_error(i), @@ -412,13 +414,11 @@ begin D_OUT(0) => rx_pcs_rst_q(i), D_OUT(1) => rx_serdes_rst_q(i) ); - - CLK_125_RX(i) <= sd_rx_clk(i); -- SGMII core SGMII_GBE_PCS : sgmii_gbe_pcs42 port map( - rst_n => GSR_N, + rst_n => RESET_N, signal_detect => link_rx_ready(i), gbe_mode => '1', sgmii_mode => '0', @@ -470,7 +470,7 @@ begin operational_rate((i + 1) * 2 - 1 downto i * 2) <= b"10"; - mr_main_reset(i) <= init_quad; + mr_main_reset(i) <= RESET; mr_restart_an(i) <= pulse(i); mr_an_enable(i) <= link_rx_ready(i); mr_adv_ability((i + 1) * 16 - 1 downto i * 16) <= x"0020"; @@ -491,7 +491,7 @@ begin hclk => CLK_125, -- BUG: can be CLK_125 txmac_clk => CLK_125, rxmac_clk => CLK_125, - reset_n => GSR_N, + reset_n => RESET_N, ------------------- Input signals to the GMII ---------------- rxd => pcs_rxd((i + 1) * 8 - 1 downto i * 8), rx_dv => pcs_rx_en(i), @@ -542,7 +542,7 @@ begin -- CAN BE OPTIMIZED TSMAC_CONTROLLER : trb_net16_gbe_mac_control port map( - CLK => CLK_125, -- BUG: can be CLK_125 + CLK => CLK_125, RESET => RESET, -- signals to/from main controller MC_TSMAC_READY_OUT => mac_ready_conf(i), @@ -566,8 +566,7 @@ begin -- initializes MAC after AN is complete THE_FW_GBE_LSM: entity gbe_lsm port map( - CLK => CLK_125, -- BUG: can be CLK_125 - CLEAR => init_quad, + CLK => CLK_125, RESET => RESET, -- MAC_AN_COMPLETE_IN => an_complete(i), @@ -583,7 +582,6 @@ begin THE_FW_RB: entity rx_rb port map( CLK => CLK_125, - CLEAR => init_quad, RESET => RESET, -- MAC interface (RX) MAC_RX_DATA_IN => mac_rx_data((i + 1) * 8 - 1 downto i * 8), @@ -607,7 +605,6 @@ begin THE_FW_FIFO: entity tx_fifo port map( CLK => CLK_125, - CLEAR => init_quad, RESET => RESET, -- MAC interface MAC_TX_DATA_OUT => mac_tx_data((i + 1) * 8 - 1 downto i * 8), @@ -685,4 +682,4 @@ begin led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0'; -end architecture RTL; +end architecture gbe_med_fifo_arch; diff --git a/gbe_trb_ecp3/base/gbe_med_raw.vhd b/gbe_trb_ecp3/base/gbe_med_raw.vhd index 42bee4c..b1db479 100644 --- a/gbe_trb_ecp3/base/gbe_med_raw.vhd +++ b/gbe_trb_ecp3/base/gbe_med_raw.vhd @@ -16,9 +16,7 @@ entity gbe_med_raw is port( RESET : in std_logic; GSR_N : in std_logic; - CLK_SYS : in std_logic; CLK_125 : in std_logic; - CLK_125_RX : out std_logic_vector(3 downto 0); -- MAC status and config MAC_READY_CONF_OUT : out std_logic_vector(3 downto 0); MAC_RECONF_IN : in std_logic_vector(3 downto 0) := (others => '0'); @@ -407,8 +405,6 @@ begin D_OUT(0) => rx_pcs_rst_q(i), D_OUT(1) => rx_serdes_rst_q(i) ); - - CLK_125_RX(i) <= sd_rx_clk(i); -- SGMII core SGMII_GBE_PCS : sgmii_gbe_pcs42 @@ -484,7 +480,7 @@ begin MAC: tsmac41 port map( ----------------- clock and reset port declarations ------------------ - hclk => CLK_SYS, + hclk => CLK_125, txmac_clk => CLK_125, rxmac_clk => CLK_125, reset_n => GSR_N, @@ -536,7 +532,7 @@ begin TSMAC_CONTROLLER : trb_net16_gbe_mac_control port map( - CLK => CLK_SYS, + CLK => CLK_125, RESET => RESET, -- signals to/from main controller MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i), diff --git a/gbe_trb_ecp3/base/rx_rb.vhd b/gbe_trb_ecp3/base/rx_rb.vhd deleted file mode 100644 index dd0a413..0000000 --- a/gbe_trb_ecp3/base/rx_rb.vhd +++ /dev/null @@ -1,289 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity rx_rb is - port( - CLK : in std_logic; - CLEAR : in std_logic; - RESET : in std_logic; - -- MAC interface (RX) - MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); -- RX data from TSMAC - MAC_RX_WR_IN : in std_logic; -- RX data write from TSMAC - MAC_RX_EOF_IN : in std_logic; -- RX EndOfFrame from TSMAC - MAC_RX_ERROR_IN : in std_logic; -- RX Error from TSMAC - MAC_RX_FIFOFULL_OUT : out std_logic; - -- FIFO interface (TX) - FIFO_FULL_IN : in std_logic; -- TX fifo full, delay read from ring buffer - FIFO_WR_OUT : out std_logic; -- TX fifo write - FIFO_Q_OUT : out std_logic_vector(8 downto 0); -- TX data - FRAME_REQ_IN : in std_logic; -- one pulse starts readout of frame stored in ring buffer - FRAME_ACK_OUT : out std_logic; -- one pulse for "end of frame" - FRAME_AVAIL_OUT : out std_logic; -- number of frames stored in ring buffer - FRAME_START_OUT : out std_logic; -- StartOfFrame signal - -- - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity rx_rb; - -architecture rx_rb_arch of rx_rb is - --- Components - component rb_4k_9 - port( - WRADDRESS : in std_logic_vector(11 downto 0); - RDADDRESS : in std_logic_vector(11 downto 0); - DATA : in std_logic_vector(8 downto 0); - WE : in std_logic; - RDCLOCK : in std_logic; - RDCLOCKEN : in std_logic; - RESET : in std_logic; - WRCLOCK : in std_logic; - WRCLOCKEN : in std_logic; - Q : out std_logic_vector(8 downto 0) - ); - end component rb_4k_9; - --- state machine signals - type state_t is (RX_DENY,RX_READY,RX_FRAME,FRAME_OK,FRAME_BAD,FORWARD,SKIP); - signal STATE, NEXT_STATE : state_t; - --- Signals - signal rd_ptr : unsigned(11 downto 0); - signal wr_ptr : unsigned(11 downto 0); - signal last_wr_ptr : std_logic_vector(11 downto 0); - signal rb_used : unsigned(11 downto 0); - signal rb_full : std_logic; - signal rb_empty : std_logic; - signal ce_wr_ptr : std_logic; - signal ld_wr_ptr : std_logic; - signal ce_rd_ptr : std_logic; - signal wr_ram : std_logic; - signal rd_ram : std_logic; - signal ram_q : std_logic_vector(8 downto 0); - signal frame_active : std_logic; - signal frame_requested : std_logic; - signal fifo_wr_int : std_logic; - signal empty_read_ack : std_logic; - signal normal_read_ack : std_logic; - signal sof_int : std_logic; - signal frames_avail : unsigned(7 downto 0); - - -begin - - -- FrameActive: we must not change to "receive" in the middle of a frame - -- when "buffer full" condition is deasserted - THE_FRAME_ACTIVE_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - frame_active <= '0'; - elsif( rising_edge(CLK) ) then - if( (MAC_RX_WR_IN = '1') and (frame_active = '0') ) then - frame_active <= '1'; - elsif( (MAC_RX_EOF_IN = '1') and (frame_active = '1') ) then - frame_active <= '0'; - end if; - end if; - end process THE_FRAME_ACTIVE_PROC; - - -- Write pointer for ring buffer - THE_WR_PTR_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - wr_ptr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if ( ld_wr_ptr = '1' ) then - wr_ptr <= unsigned(last_wr_ptr); - elsif( ce_wr_ptr = '1' ) then - wr_ptr <= wr_ptr + 1; - end if; - end if; - end process THE_WR_PTR_PROC; - - -- Read pointer for ring buffer - THE_RD_PTR_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - rd_ptr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( ce_rd_ptr = '1' ) then - rd_ptr <= rd_ptr + 1; - end if; - end if; - end process THE_RD_PTR_PROC; - - -- ring buffer fill level - rb_used <= wr_ptr - rd_ptr; - - -- ring buffer full - -- TAKE CARE: the last byte of a frame is taken into account - -- by "one less" for the full condition - rb_full <= '1' when (rb_used(11 downto 1) = b"1111_1111_111") else '0'; - - rb_empty <= '1' when (rb_used(11 downto 0) = b"0000_0000_0000") else '0'; - - MAC_RX_FIFOFULL_OUT <= rb_full; - - -- last write pointer: used to drop a broken frame, in case - THE_LAST_WR_PTR_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - last_wr_ptr <= (others => '0'); - elsif( rising_edge(CLK) ) then - if( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then - last_wr_ptr <= std_logic_vector(wr_ptr); - end if; - end if; - end process THE_LAST_WR_PTR_PROC; - - -- DPRAM as ring buffer - THE_DP_RAM: rb_4k_9 - port map( - WRADDRESS => std_logic_vector(wr_ptr), - RDADDRESS => std_logic_vector(rd_ptr), - DATA(8) => MAC_RX_EOF_IN, - DATA(7 downto 0) => MAC_RX_DATA_IN, - WE => wr_ram, - RDCLOCK => CLK, - RDCLOCKEN => '1', - RESET => CLEAR, - WRCLOCK => CLK, - WRCLOCKEN => '1', - Q => ram_q - ); - - -- write signal - wr_ram <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or - ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) - else '0'; - ce_wr_ptr <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or - ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) - else '0'; - - -- FrameReq signal, one pulse only - THE_FRAME_REQ_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - frame_requested <= '0'; - elsif( rising_edge(CLK) ) then - if( (FRAME_REQ_IN = '1') and (frame_requested = '0') ) then - frame_requested <= '1'; - elsif( ((ram_q(8) = '1') and (frame_requested = '1')) or (empty_read_ack = '1') ) then - frame_requested <= '0'; - end if; - end if; - end process THE_FRAME_REQ_PROC; - - -- EmptyReadAck signal, used to handle a request to RX_RB with no frame to send - empty_read_ack <= FRAME_REQ_IN and rb_empty when rising_edge(CLK); - - -- NormalReadAck signal - normal_read_ack <= ram_q(8) and fifo_wr_int; - - -- read signal - rd_ram <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0'; - ce_rd_ptr <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0'; - - sof_int <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK); - - FRAME_ACK_OUT <= normal_read_ack or empty_read_ack; - - FRAME_START_OUT <= sof_int; - - FIFO_Q_OUT <= ram_q; - - fifo_wr_int <= rd_ram when rising_edge(CLK); - - FIFO_WR_OUT <= fifo_wr_int; - - -- FramesAvailable counter - THE_FRAMES_AVAIL_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - frames_avail <= (others => '0'); - elsif( rising_edge(CLK) ) then - if ( (STATE = FRAME_OK) and (normal_read_ack = '0') ) then - -- one frame written successfully - frames_avail <= frames_avail + 1; - elsif( (STATE /= FRAME_OK) and (normal_read_ack = '1') ) then - -- one frame read successfully - frames_avail <= frames_avail - 1; - end if; - end if; - end process THE_FRAMES_AVAIL_PROC; - - FRAME_AVAIL_OUT <= '1' when (frames_avail /= x"00") else '0'; - - ----------------------------------------------------------- - -- statemachine: clocked process - ----------------------------------------------------------- - THE_FSM: process( CLK, CLEAR ) - begin - if ( CLEAR = '1' ) then - STATE <= RX_DENY; - elsif( rising_edge(CLK) ) then - STATE <= NEXT_STATE; - end if; - end process THE_FSM; - - THE_STATE_TRANSITIONS: process( STATE, MAC_RX_WR_IN, MAC_RX_EOF_IN, MAC_RX_ERROR_IN, frame_active, rb_full ) - begin - ld_wr_ptr <= '0'; - - case STATE is - - when RX_DENY => - if( (frame_active = '0') and (rb_full = '0') ) then - NEXT_STATE <= RX_READY; - else - NEXT_STATE <= RX_DENY; - end if; - - when RX_READY => - if( MAC_RX_WR_IN = '1' ) then - NEXT_STATE <= RX_FRAME; - else - NEXT_STATE <= RX_READY; - end if; - - when RX_FRAME => - if ( (MAC_RX_EOF_IN = '1') and (MAC_RX_ERROR_IN = '0') and (rb_full = '0') ) then - NEXT_STATE <= FRAME_OK; - elsif( (MAC_RX_EOF_IN = '1') and ((MAC_RX_ERROR_IN = '1') or (rb_full = '1')) ) then - NEXT_STATE <= FRAME_BAD; - ld_wr_ptr <= '1'; - else - NEXT_STATE <= RX_FRAME; - end if; - - when FRAME_OK => - NEXT_STATE <= FORWARD; - - when FORWARD => - if( rb_full = '0' ) then - NEXT_STATE <= RX_READY; - else - NEXT_STATE <= RX_DENY; - end if; - - when FRAME_BAD => - NEXT_STATE <= SKIP; - - when SKIP => - if( rb_full = '0' ) then - NEXT_STATE <= RX_READY; - else - NEXT_STATE <= RX_DENY; - end if; - - when others => - NEXT_STATE <= RX_DENY; - end case; - end process THE_STATE_TRANSITIONS; - - - -end architecture; diff --git a/gbe_trb_ecp3/base/scatter_ports.vhd b/gbe_trb_ecp3/base/scatter_ports.vhd deleted file mode 100644 index ba1c083..0000000 --- a/gbe_trb_ecp3/base/scatter_ports.vhd +++ /dev/null @@ -1,97 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity scatter_ports is - port( - CLK : in std_logic; - CLEAR : in std_logic; - RESET : in std_logic; - -- - FIFO_FULL_IN : in std_logic_vector(15 downto 0) := (others => '0'); - FIFO_FULL_OUT : out std_logic; - FRAME_AVAIL_IN : in std_logic := '0'; - FRAME_REQ_OUT : out std_logic; - FRAME_ACK_IN : in std_logic := '0'; - CYCLE_DONE_OUT : out std_logic; - -- - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity scatter_ports; - -architecture scatter_ports_arch of scatter_ports is - --- Components - --- state machine signals - type state_t is (IDLE, DO_PORT, DELAY, CLEANUP); - signal STATE, NEXT_STATE : state_t; - --- Signals - signal req_int : std_logic; - signal req_x : std_logic; - -begin - - CYCLE_DONE_OUT <= '1' when STATE = CLEANUP else '0'; - - FRAME_REQ_OUT <= req_int; - - FIFO_FULL_OUT <= '0' when FIFO_FULL_IN = x"0000" else '1'; - - ----------------------------------------------------------- - -- statemachine: clocked process - ----------------------------------------------------------- - THE_FSM: process( CLK, CLEAR ) - begin - if ( CLEAR = '1' ) then - STATE <= IDLE; - req_int <= '0'; - elsif( rising_edge(CLK) ) then - STATE <= NEXT_STATE; - req_int <= req_x; - end if; - end process THE_FSM; - - THE_STATE_TRANSITIONS: process( STATE, FRAME_AVAIL_IN, FRAME_ACK_IN ) - begin - req_x <= '0'; - - case STATE is - - when IDLE => - if( FRAME_AVAIL_IN = '1' ) then - NEXT_STATE <= DO_PORT; - req_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; - - when DO_PORT => - if( FRAME_ACK_IN = '1' ) then - NEXT_STATE <= DELAY; - else - NEXT_STATE <= DO_PORT; - end if; - - when DELAY => - NEXT_STATE <= CLEANUP; - - when CLEANUP => - if( FRAME_AVAIL_IN = '1' ) then - NEXT_STATE <= DO_PORT; - req_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; - - when others => - NEXT_STATE <= IDLE; - end case; - end process THE_STATE_TRANSITIONS; - - - -end architecture; diff --git a/gbe_trb_ecp3/base/tx_fifo.vhd b/gbe_trb_ecp3/base/tx_fifo.vhd deleted file mode 100644 index e406353..0000000 --- a/gbe_trb_ecp3/base/tx_fifo.vhd +++ /dev/null @@ -1,155 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; - -entity tx_fifo is - port( - CLK : in std_logic; - CLEAR : in std_logic; - RESET : in std_logic; - -- MAC interface - MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); - MAC_TX_READ_IN : in std_logic; - MAC_FIFOEOF_OUT : out std_logic; -- end of frame marker - MAC_FIFOEMPTY_OUT : out std_logic; -- must never happen during TX - MAC_FIFOAVAIL_OUT : out std_logic; -- starts TX process in MAC - MAC_TX_DONE_IN : in std_logic; -- frame sent - -- FIFO interface - FIFO_FULL_OUT : out std_logic; - FIFO_WR_IN : in std_logic; - FIFO_D_IN : in std_logic_vector(8 downto 0); - -- Link stuff - FRAME_START_IN : in std_logic; - LINK_ACTIVE_IN : in std_logic; - -- - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity tx_fifo; - -architecture tx_fifo_arch of tx_fifo is - --- Components - component fifo_4k_9 - port( - DATA : in std_logic_vector(8 downto 0); - CLOCK : in std_logic; - WREN : in std_logic; - RDEN : in std_logic; - RESET : in std_logic; - Q : out std_logic_vector(8 downto 0); - EMPTY : out std_logic; - FULL : out std_logic; - ALMOSTFULL : out std_logic - ); - end component fifo_4k_9; - --- component fifo_4k_9 --- port( --- DATA : in std_logic_vector(8 downto 0); --- WRCLOCK : in std_logic; --- RDCLOCK : in std_logic; --- WREN : in std_logic; --- RDEN : in std_logic; --- RESET : in std_logic; --- RPRESET : in std_logic; --- Q : out std_logic_vector(8 downto 0); --- EMPTY : out std_logic; --- FULL : out std_logic; --- ALMOSTEMPTY : out std_logic; --- ALMOSTFULL : out std_logic --- ); --- end component fifo_4k_9; - --- state machine signals - --- Signals - signal frames_avail : unsigned(7 downto 0); - signal frame_written : std_logic; - signal frame_read : std_logic; - signal mac_fifoeof : std_logic; - signal mac_tx_read : std_logic; - signal frame_active : std_logic; - signal fifo_wr : std_logic; - -begin - - -- FrameActice signal - used to inhibt acceptance of runt frames - THE_FRAME_ACTIVE_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - frame_active <= '0'; - elsif( rising_edge(CLK) ) then - if ( FRAME_START_IN = '1' ) then - frame_active <= LINK_ACTIVE_IN; - elsif( frame_written = '1' ) then - frame_active <= '0'; - end if; - end if; - end process THE_FRAME_ACTIVE_PROC; - - fifo_wr <= FIFO_WR_IN and frame_active; - - -- TX FIFO storing full outgoing frames - THE_TX_FIFO: fifo_4k_9 - port map( - DATA => FIFO_D_IN, - CLOCK => CLK, - WREN => fifo_wr, --FIFO_WR_IN, - RDEN => MAC_TX_READ_IN, - RESET => CLEAR, - Q(8) => mac_fifoeof, - Q(7 downto 0) => MAC_TX_DATA_OUT, - EMPTY => MAC_FIFOEMPTY_OUT, - FULL => open, - ALMOSTFULL => FIFO_FULL_OUT - ); - --- -- TX FIFO storing full outgoing frames --- THE_TX_FIFO: fifo_4k_9 --- port map( --- DATA => FIFO_D_IN, --- WRCLOCK => CLK, --- RDCLOCK => CLK, --- WREN => fifo_wr, --FIFO_WR_IN, --- RDEN => MAC_TX_READ_IN, --- RESET => CLEAR, --- RPRESET => CLEAR, --- Q(8) => mac_fifoeof, --- Q(7 downto 0) => MAC_TX_DATA_OUT, --- EMPTY => MAC_FIFOEMPTY_OUT, --- FULL => open, --- ALMOSTEMPTY => open, --- ALMOSTFULL => FIFO_FULL_OUT --- ); - - MAC_FIFOEOF_OUT <= mac_fifoeof; - - mac_tx_read <= MAC_TX_READ_IN when rising_edge(CLK); - - -- one frame written to FIFO - frame_written <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0'; - - -- one frame read from FIFO - frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0'; - - -- FramesAvailable counter - THE_FRAMES_AVAIL_PROC: process( CLK, CLEAR ) - begin - if( CLEAR = '1' ) then - frames_avail <= (others => '0'); - elsif( rising_edge(CLK) ) then - if ( (frame_written = '1') and (frame_read = '0') ) then - -- one frame written successfully - frames_avail <= frames_avail + 1; - elsif( (frame_written = '0') and (frame_read = '1') ) then - -- one frame read successfully - frames_avail <= frames_avail - 1; - end if; - end if; - end process THE_FRAMES_AVAIL_PROC; - - MAC_FIFOAVAIL_OUT <= '1' when (frames_avail /= x"00") else '0'; - -end architecture; diff --git a/oldfiles/L12TrigBusInterface.vhd b/oldfiles/L12TrigBusInterface.vhd deleted file mode 100644 index 1b7a989..0000000 --- a/oldfiles/L12TrigBusInterface.vhd +++ /dev/null @@ -1,213 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Detector Trigger Unit --- Project : HADES Second Level Trigger -------------------------------------------------------------------------------- --- File : L12TrugBusInterface.vhd --- Author : Markus Petri, Daniel Schaefer --- Created : 2002/03/27 --- Last modified : 2007/01/12 T. Perez -------------------------------------------------------------------------------- --- Description : Generic Interace for the Trigger Bus --- -------------------------------------------------------------------------------- --- Modification history : --- 2002/03/27 : created --- 2002/05/31 : corrected TrigBus sequence, implemented BSY; --- 2007/01/12 : change in libraries to adapt to trbnet: numeric -> arith --- CLK_10 removed. Now DTU code is much faster than TRIGGERBUS. --- 2007/02/23 : DVAL is not being produced. ??? -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity L12TrigBusInterface is - port ( --- from Trigger bus - TSTR : in std_logic; -- trigger strobe - DSTR : in std_logic; -- data strobe - DIN : in std_logic_vector(3 downto 0); --- to Trigger bus - BSY : out std_logic; - ERR : out std_logic; --- general - RES : in std_logic; - CLK : in std_logic; -- should be 40 MHz!! --- CLK_10 : in std_logic; -- should be 10 MHz --- to state engine (and others) - DVAL : out std_logic; -- high for 2 clk cycles when TRIGTAG - -- and TRIGCODE have been received - TRIGTAG : out std_logic_vector(7 downto 0); - TRIGCODE : out std_logic_vector(3 downto 0); --- from state engine - TRIGTAG_MISMATCH : in std_logic; -- this is high whenever the received - -- TRIGTAG is not equal to the DTU's - -- internal counter and is not starting - -- with a 0 at begin - BUSY : in std_logic -- this should be controlled by the - -- state engine and is passed directly - -- to the trigger bus (where it is wired- - -- or with all the other busy's from - -- the DTU's, CTU) - ); -end L12TrigBusInterface; - -architecture ARCH_L12TrigInterface of L12TrigBusInterface is -------------------------------------------------------------------------------- - type ShiftReg is array (0 to 2) of - std_logic_vector(3 downto 0); -------------------------------------------------------------------------------- - signal NIBCNT : integer range 0 to 3; -- # of current nibble - signal TRIGBUFF : ShiftReg; - signal TSTR_REG, TSTR_REG_REG : std_logic; - signal DSTR_REG, DSTR_REG_REG : std_logic; --- signal DVAL_REG, DVAL_REG_LONG, DVAL_sync : std_logic; - signal DVAL_REG, DVAL_REG_REG : std_logic; - signal DIN_REG : std_logic_vector(3 downto 0); --- signal counter_for_DVAL : integer range 0 to 3; - - signal TRIGCODE_i : std_logic_vector(3 downto 0); - signal BUSY_FAST, BUSY_i : std_logic; -------------------------------------------------------------------------------- - -begin - - -- first we register all our inputs - - reg_DIN : process (CLK, RES) - begin -- process reg_DIN - if RES = '1' then -- asynchronous reset (active high) - DIN_REG <= (others => '0'); - elsif CLK'event and CLK = '1' then -- rising clock edge - DIN_REG <= (DIN); - end if; - end process reg_DIN; - - reg_TSTR : process (CLK, RES) - begin -- process reg_NEW_TAG - if RES = '1' then -- asynchronous reset (active high) - TSTR_REG <= '0'; - elsif CLK'event and CLK = '1' then -- rising clock edge - TSTR_REG <= TSTR; - end if; - end process reg_TSTR; - - reg_reg_TSTR : process (CLK, RES) - begin -- process reg_NEW_TAG - if RES = '1' then -- asynchronous reset (active high) - TSTR_REG_REG <= '0'; - elsif CLK'event and CLK = '1' then -- rising clock edge - TSTR_REG_REG <= TSTR_REG; - end if; - end process reg_reg_TSTR; - - reg_DSTR : process (CLK, RES) - begin -- process reg_NEW_TAG - if RES = '1' then -- asynchronous reset (active high) - DSTR_REG <= '0'; - elsif CLK'event and CLK = '1' then -- rising clock edge - DSTR_REG <= DSTR; - end if; - end process reg_DSTR; - - reg_reg_DSTR : process (CLK, RES) - begin -- process reg_NEW_TAG - if RES = '1' then -- asynchronous reset (active high) - DSTR_REG_REG <= '0'; - elsif CLK'event and CLK = '1' then -- rising clock edge - DSTR_REG_REG <= DSTR_REG; - end if; - end process reg_reg_DSTR; - - CodeBuffering : process (CLK, RES) - begin -- process CodeBuffering - if RES = '1' then - TRIGCODE_i <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (TSTR_REG = '0') and (TSTR_REG_REG = '1') then - -- falling edge of TSTR - TRIGCODE_i <= DIN_REG; - -- den registerten Wert - end if; - end if; - end process CodeBuffering; - - TagBuffering : process (CLK, RES) - begin -- process TagBuffering - if RES = '1' then -- asynchronous reset (active high) - NIBCNT <= 0; - DVAL_REG <= '0'; - elsif CLK'event and CLK = '1' then -- rising clock edge - DVAL_REG <= '0'; - if NIBCNT >= 3 then - NIBCNT <= 0; - DVAL_REG <= '1'; - elsif (DSTR_REG = '0') and (DSTR_REG_REG = '1') then - NIBCNT <= NIBCNT + 1; - end if; - end if; - end process TagBuffering; - - Shift_Reg : process (CLK, RES) - begin -- process TagBuffering - if RES = '1' then -- asynchronous reset (active high) - TRIGBUFF(0) <= (others => '0'); - TRIGBUFF(1) <= (others => '0'); - TRIGBUFF(2) <= (others => '0'); - elsif CLK'event and CLK = '1' then -- rising clock edge - if (DSTR_REG = '0') and (DSTR_REG_REG = '1') then -- falling edge of DSTR - TRIGBUFF(2) <= TRIGBUFF(1); - TRIGBUFF(1) <= TRIGBUFF(0); - TRIGBUFF(0) <= DIN_REG; -- shift register - end if; - end if; - end process Shift_Reg; - - -- purpose: register DVAL - -- type : sequential - -- inputs : CLK, RES, DVAL - -- outputs: DVAL_sync - DVAL_OUT : process (CLK, RES, DVAL_REG) - begin -- process DVAL_reg - if RES = '1' then -- asynchronous reset (active low) - DVAL_REG_REG <= '0'; - DVAL <= '0'; - elsif CLK'event and CLK = '1' then -- rising clock edge - DVAL_REG_REG <= DVAL_REG; - DVAL <= DVAL_REG or DVAL_REG_REG; - end if; - end process DVAL_OUT; - - - SynchBSY : process(RES, CLK) - begin - if (RES = '1') then - BSY <= '0'; - elsif (CLK'event and CLK = '1') then - BSY <= BUSY_i; - end if; - end process SynchBSY; -------------------------------------------------------------------------------- --- Combinatorial Signals -------------------------------------------------------------------------------- - TRIGTAG <= TRIGBUFF(1) & TRIGBUFF(2); - TRIGCODE <= TRIGCODE_i; - ERR <= TRIGTAG_MISMATCH; --- DSTR_INV <= NOT(DSTR); - -- purpose: Set a fast busy on TSTR - -- type : sequential - -- inputs : CLK, RES, BUSY - -- outputs: BUSY_FASt - FastBusy : process (CLK, RES, BUSY) - begin -- process FastBusy - if RES = '1' or BUSY = '1'then -- asynchronous reset (active high) - BUSY_FAST <= '0'; - elsif CLK'event and CLK = '1' then -- rising clock edge - if TSTR_REG = '1' then - BUSY_FAST <= '1'; - end if; - end if; - end process FastBusy; - BUSY_i <= BUSY or BUSY_FAST; -end ARCH_L12TrigInterface; diff --git a/oldfiles/bus_handler.vhd b/oldfiles/bus_handler.vhd deleted file mode 100644 index c38450e..0000000 --- a/oldfiles/bus_handler.vhd +++ /dev/null @@ -1,293 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bus_handler is -port( CLK_IN : in std_logic; - CLEAR_IN : in std_logic; - RESET_IN : in std_logic; - DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - DAT_READ_ENABLE_IN : in std_logic; -- read pulse - DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse - DAT_TIMEOUT_IN : in std_logic; -- access timed out - DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested - DAT_WRITE_ACK_OUT : out std_logic; -- data accepted - DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - SLV_SELECT_OUT : out std_logic_vector(47 downto 0); -- select signal for slave entities - SLV_READ_OUT : out std_logic; -- read signal for slave entities - SLV_WRITE_OUT : out std_logic; -- write signal for slave entities - SLV_BUSY_IN : in std_logic; -- wired OR busy from slave entities - SLV_ACK_IN : in std_logic; -- slave has accepted access - SLV_DATA_IN : in std_logic_vector(31 downto 0); -- read data from slaves - SLV_DATA_OUT : out std_logic_vector(31 downto 0); -- write data to slaves - STAT : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture Behavioral of bus_handler is - --- Signals - type STATES is (SLEEP,RACC,WACC,RFAIL,WFAIL,ROK,WOK,STATW,STATS,STATD,NOONE,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal bsm : std_logic_vector(3 downto 0); - - signal rst_strb_x : std_logic; - signal rst_strb : std_logic; - signal buf_dat_write_ack_x : std_logic; - signal buf_dat_write_ack : std_logic; - signal buf_dat_dataready_x : std_logic; - signal buf_dat_dataready : std_logic; - signal buf_dat_no_more_data_x : std_logic; - signal buf_dat_no_more_data : std_logic; - signal buf_dat_unknown_addr_x : std_logic; - signal buf_dat_unknown_addr : std_logic; - - signal buf_slv_select_x : std_logic_vector(47 downto 0); - signal buf_slv_select : std_logic_vector(47 downto 0); - signal buf_slv_read : std_logic; - signal buf_slv_write : std_logic; - signal no_slave_reg_x : std_logic; - signal no_slave_mem_x : std_logic; - signal no_slave : std_logic; - signal slave_busy : std_logic; - signal slave_ack : std_logic; - -begin - --- Memory map: --- 80xx => single registers --- axxx => pedestal memory APV[15:0] --- bxxx => threshold memory APV[15:0] - ------------------------------------------------------------------------------- --- This part is crucial, as ACK and BSY are tristate signals! ------------------------------------------------------------------------------- --- Slave address decoder - registers (single address decoding) -THE_ADDRESS_DEC_REG_PROC: process( dat_addr_in ) -begin - case dat_addr_in is - when x"8083" => buf_slv_select_x(15 downto 0) <= x"8000"; no_slave_reg_x <= '0'; -- trigger 3 - when x"8082" => buf_slv_select_x(15 downto 0) <= x"4000"; no_slave_reg_x <= '0'; -- trigger 2 - when x"8081" => buf_slv_select_x(15 downto 0) <= x"2000"; no_slave_reg_x <= '0'; -- trigger 1 - when x"8080" => buf_slv_select_x(15 downto 0) <= x"1000"; no_slave_reg_x <= '0'; -- trigger 0 - when x"8040" => buf_slv_select_x(15 downto 0) <= x"0800"; no_slave_reg_x <= '0'; -- I2C master - when x"8021" => buf_slv_select_x(15 downto 0) <= x"0400"; no_slave_reg_x <= '0'; -- EDS_DONE - when x"8020" => buf_slv_select_x(15 downto 0) <= x"0200"; no_slave_reg_x <= '0'; -- BUF_DONE - when x"8001" => buf_slv_select_x(15 downto 0) <= x"0100"; no_slave_reg_x <= '0'; -- test register bad - when x"8000" => buf_slv_select_x(15 downto 0) <= x"0080"; no_slave_reg_x <= '0'; -- test register good - when x"8002" => buf_slv_select_x(15 downto 0) <= x"0040"; no_slave_reg_x <= '0'; -- real test register - when others => buf_slv_select_x(15 downto 0) <= x"0000"; no_slave_reg_x <= '1'; - end case; -end process THE_ADDRESS_DEC_REG_PROC; - --- Slave address decoder - memory (256 longwords decoding) -THE_ADDRESS_DEC_MEM_PROC: process( dat_addr_in(15 downto 8) ) -begin - case dat_addr_in(15 downto 8) is - when x"a0" => buf_slv_select_x(47 downto 16) <= x"8000_0000"; no_slave_mem_x <= '0'; -- pedestal 0 - when x"a1" => buf_slv_select_x(47 downto 16) <= x"4000_0000"; no_slave_mem_x <= '0'; -- pedestal 1 - when x"a2" => buf_slv_select_x(47 downto 16) <= x"2000_0000"; no_slave_mem_x <= '0'; -- pedestal 2 - when x"a3" => buf_slv_select_x(47 downto 16) <= x"1000_0000"; no_slave_mem_x <= '0'; -- pedestal 3 - when x"a4" => buf_slv_select_x(47 downto 16) <= x"0800_0000"; no_slave_mem_x <= '0'; -- pedestal 4 - when x"a5" => buf_slv_select_x(47 downto 16) <= x"0400_0000"; no_slave_mem_x <= '0'; -- pedestal 5 - when x"a6" => buf_slv_select_x(47 downto 16) <= x"0200_0000"; no_slave_mem_x <= '0'; -- pedestal 6 - when x"a7" => buf_slv_select_x(47 downto 16) <= x"0100_0000"; no_slave_mem_x <= '0'; -- pedestal 7 - when x"a8" => buf_slv_select_x(47 downto 16) <= x"0080_0000"; no_slave_mem_x <= '0'; -- pedestal 8 - when x"a9" => buf_slv_select_x(47 downto 16) <= x"0040_0000"; no_slave_mem_x <= '0'; -- pedestal 9 - when x"aa" => buf_slv_select_x(47 downto 16) <= x"0020_0000"; no_slave_mem_x <= '0'; -- pedestal 10 - when x"ab" => buf_slv_select_x(47 downto 16) <= x"0010_0000"; no_slave_mem_x <= '0'; -- pedestal 11 - when x"ac" => buf_slv_select_x(47 downto 16) <= x"0008_0000"; no_slave_mem_x <= '0'; -- pedestal 12 - when x"ad" => buf_slv_select_x(47 downto 16) <= x"0004_0000"; no_slave_mem_x <= '0'; -- pedestal 13 - when x"ae" => buf_slv_select_x(47 downto 16) <= x"0002_0000"; no_slave_mem_x <= '0'; -- pedestal 14 - when x"af" => buf_slv_select_x(47 downto 16) <= x"0001_0000"; no_slave_mem_x <= '0'; -- pedestal 15 - when x"b0" => buf_slv_select_x(47 downto 16) <= x"0000_8000"; no_slave_mem_x <= '0'; -- threshold 0 - when x"b1" => buf_slv_select_x(47 downto 16) <= x"0000_4000"; no_slave_mem_x <= '0'; -- threshold 1 - when x"b2" => buf_slv_select_x(47 downto 16) <= x"0000_2000"; no_slave_mem_x <= '0'; -- threshold 2 - when x"b3" => buf_slv_select_x(47 downto 16) <= x"0000_1000"; no_slave_mem_x <= '0'; -- threshold 3 - when x"b4" => buf_slv_select_x(47 downto 16) <= x"0000_0800"; no_slave_mem_x <= '0'; -- threshold 4 - when x"b5" => buf_slv_select_x(47 downto 16) <= x"0000_0400"; no_slave_mem_x <= '0'; -- threshold 5 - when x"b6" => buf_slv_select_x(47 downto 16) <= x"0000_0200"; no_slave_mem_x <= '0'; -- threshold 6 - when x"b7" => buf_slv_select_x(47 downto 16) <= x"0000_0100"; no_slave_mem_x <= '0'; -- threshold 7 - when x"b8" => buf_slv_select_x(47 downto 16) <= x"0000_0080"; no_slave_mem_x <= '0'; -- threshold 8 - when x"b9" => buf_slv_select_x(47 downto 16) <= x"0000_0040"; no_slave_mem_x <= '0'; -- threshold 9 - when x"ba" => buf_slv_select_x(47 downto 16) <= x"0000_0020"; no_slave_mem_x <= '0'; -- threshold 10 - when x"bb" => buf_slv_select_x(47 downto 16) <= x"0000_0010"; no_slave_mem_x <= '0'; -- threshold 11 - when x"bc" => buf_slv_select_x(47 downto 16) <= x"0000_0008"; no_slave_mem_x <= '0'; -- threshold 12 - when x"bd" => buf_slv_select_x(47 downto 16) <= x"0000_0004"; no_slave_mem_x <= '0'; -- threshold 13 - when x"be" => buf_slv_select_x(47 downto 16) <= x"0000_0002"; no_slave_mem_x <= '0'; -- threshold 14 - when x"bf" => buf_slv_select_x(47 downto 16) <= x"0000_0001"; no_slave_mem_x <= '0'; -- threshold 15 - when others => buf_slv_select_x(47 downto 16) <= x"0000_0000"; no_slave_mem_x <= '1'; - end case; -end process THE_ADDRESS_DEC_MEM_PROC; - - --- synchronize signals -THE_SYNC_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - buf_slv_select <= buf_slv_select_x; - no_slave <= no_slave_reg_x and no_slave_mem_x; - end if; -end process THE_SYNC_PROC; - - --- Slave response lines -slave_ack <= slv_ack_in when ( no_slave = '0' ) else '0'; -slave_busy <= slv_busy_in when ( no_slave = '0' ) else '0'; -dat_data_out <= slv_data_in when ( no_slave = '0' ) else (others => '0'); - --- Data tunneling to slave entities -slv_data_out <= dat_data_in; - --- Read / write strobe -THE_READ_WRITE_STROBE_PROC: process( clk_in, clear_in ) -begin - if( clear_in = '1' ) then - buf_slv_read <= '0'; - buf_slv_write <= '0'; - elsif( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - buf_slv_read <= '0'; - buf_slv_write <= '0'; - elsif( (dat_read_enable_in = '1') and (dat_write_enable_in = '0') ) then - buf_slv_read <= '1'; - buf_slv_write <= '0'; - elsif( (dat_read_enable_in = '0') and (dat_write_enable_in = '1') ) then - buf_slv_read <= '0'; - buf_slv_write <= '1'; - elsif( rst_strb = '1' ) then - buf_slv_read <= '0'; - buf_slv_write <= '0'; - end if; - end if; -end process THE_READ_WRITE_STROBE_PROC; - - - --- The main state machine --- State memory process -STATE_MEM: process( clk_in, clear_in ) -begin - if( clear_in = '1' ) then - CURRENT_STATE <= SLEEP; - rst_strb <= '0'; - buf_dat_dataready <= '0'; - buf_dat_no_more_data <= '0'; - buf_dat_write_ack <= '0'; - buf_dat_unknown_addr <= '0'; - elsif( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - rst_strb <= '0'; - buf_dat_dataready <= '0'; - buf_dat_no_more_data <= '0'; - buf_dat_write_ack <= '0'; - buf_dat_unknown_addr <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - rst_strb <= rst_strb_x; - buf_dat_dataready <= buf_dat_dataready_x; - buf_dat_no_more_data <= buf_dat_no_more_data_x; - buf_dat_write_ack <= buf_dat_write_ack_x; - buf_dat_unknown_addr <= buf_dat_unknown_addr_x; - end if; - end if; -end process STATE_MEM; - --- Transition matrix -TRANSFORM: process(CURRENT_STATE, no_slave, buf_slv_read, buf_slv_write, slave_ack, slave_busy, dat_timeout_in ) -begin - NEXT_STATE <= SLEEP; - rst_strb_x <= '0'; - buf_dat_dataready_x <= '0'; - buf_dat_no_more_data_x <= '0'; - buf_dat_write_ack_x <= '0'; - buf_dat_unknown_addr_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( (no_slave = '1') and ((buf_slv_read = '1') or (buf_slv_write = '1')) ) then - NEXT_STATE <= NOONE; - buf_dat_unknown_addr_x <= '1'; - elsif( (buf_slv_read = '1') and (buf_slv_write = '0') ) then - NEXT_STATE <= RACC; - elsif( (buf_slv_read = '0') and (buf_slv_write = '1') ) then - NEXT_STATE <= WACC; - else - NEXT_STATE <= SLEEP; - end if; - when RACC => if ( dat_timeout_in = '1' ) then - NEXT_STATE <= DONE; - rst_strb_x <= '1'; - elsif( slave_busy = '1' ) then - NEXT_STATE <= RFAIL; - buf_dat_no_more_data_x <= '1'; - elsif( slave_ack = '1' ) then - NEXT_STATE <= ROK; - buf_dat_dataready_x <= '1'; - else - NEXT_STATE <= RACC; - end if; - when RFAIL => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when ROK => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when WACC => if ( dat_timeout_in = '1' ) then - NEXT_STATE <= DONE; - rst_strb_x <= '1'; - elsif( slave_busy = '1' ) then - NEXT_STATE <= WFAIL; - buf_dat_no_more_data_x <= '1'; - elsif( slave_ack = '1' ) then - NEXT_STATE <= WOK; - buf_dat_write_ack_x <= '1'; - else - NEXT_STATE <= WACC; - end if; - when WFAIL => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when WOK => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when NOONE => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when DONE => NEXT_STATE <= SLEEP; -- ????? - -- Just in case... - when others => NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - --- Output decoding -DECODE: process(CURRENT_STATE) -begin - case CURRENT_STATE is - when SLEEP => bsm <= x"0"; - when RACC => bsm <= x"1"; - when ROK => bsm <= x"2"; - when RFAIL => bsm <= x"3"; - when WACC => bsm <= x"4"; - when WOK => bsm <= x"5"; - when NOONE => bsm <= x"6"; - when DONE => bsm <= x"7"; - when others => bsm <= x"f"; - end case; -end process DECODE; - --- Outputs -dat_dataready_out <= buf_dat_dataready; -dat_no_more_data_out <= buf_dat_no_more_data; -dat_unknown_addr_out <= buf_dat_unknown_addr; -dat_write_ack_out <= buf_dat_write_ack; - -slv_select_out <= buf_slv_select; -slv_read_out <= buf_slv_read; -slv_write_out <= buf_slv_write; - -stat(31 downto 9) <= (others => '0'); -stat(8) <= rst_strb; -stat(7 downto 4) <= (others => '0'); -stat(3 downto 0) <= bsm; - -end Behavioral; diff --git a/oldfiles/bus_handler_oepb.vhd b/oldfiles/bus_handler_oepb.vhd deleted file mode 100644 index 9b959e7..0000000 --- a/oldfiles/bus_handler_oepb.vhd +++ /dev/null @@ -1,264 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity bus_handler_oepb is - generic( - AMOUNT_OF_SLAVES : integer := 17 - ); - port( - CLK_IN : in std_logic; - CLEAR_IN : in std_logic; - RESET_IN : in std_logic; - DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - DAT_READ_ENABLE_IN : in std_logic; -- read pulse - DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse - DAT_TIMEOUT_IN : in std_logic; -- access timed out - DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested - DAT_WRITE_ACK_OUT : out std_logic; -- data accepted - DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - SLV_SELECT_OUT : out std_logic_vector(AMOUNT_OF_SLAVES-1 downto 0); -- select signal for slave entities - SLV_READ_OUT : out std_logic; -- read signal for slave entities - SLV_WRITE_OUT : out std_logic; -- write signal for slave entities - SLV_BUSY_IN : in std_logic; -- wired OR busy from slave entities - SLV_ACK_IN : in std_logic; -- slave has accepted access - SLV_DATA_IN : in std_logic_vector(31 downto 0); -- read data from slaves - SLV_DATA_OUT : out std_logic_vector(31 downto 0); -- write data to slaves - STAT : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture Behavioral of bus_handler_oepb is - --- Signals - type STATES is (SLEEP,RACC,WACC,RFAIL,WFAIL,ROK,WOK,STATW,STATS,STATD,NOONE,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal bsm : std_logic_vector(3 downto 0); - - signal rst_strb_x : std_logic; - signal rst_strb : std_logic; - signal buf_dat_write_ack_x : std_logic; - signal buf_dat_write_ack : std_logic; - signal buf_dat_dataready_x : std_logic; - signal buf_dat_dataready : std_logic; - signal buf_dat_no_more_data_x : std_logic; - signal buf_dat_no_more_data : std_logic; - signal buf_dat_unknown_addr_x : std_logic; - signal buf_dat_unknown_addr : std_logic; - - signal buf_slv_select_x : std_logic_vector(AMOUNT_OF_SLAVES-1 downto 0); - signal buf_slv_select : std_logic_vector(AMOUNT_OF_SLAVES-1 downto 0); - signal buf_slv_read : std_logic; - signal buf_slv_write : std_logic; - signal no_slave_reg_x : std_logic; - signal no_slave_mem_x : std_logic; - signal no_slave : std_logic; - signal slave_busy : std_logic; - signal slave_ack : std_logic; - -begin - --- Memory map: --- full range: 8000 - FFFF --- 8000 - 80FF ADC (17) --- 9000 - 9FFF SPI --- A000 - A7FF Threshold Bytes (16) --- F000 - F00F Test readout addresses (15-0) - - --- 80xx => single registers --- axxx => pedestal memory APV[15:0] --- bxxx => threshold memory APV[15:0] - ------------------------------------------------------------------------------- --- This part is crucial, as ACK and BSY are tristate signals! ------------------------------------------------------------------------------- - -THE_ADDRESS_DEC_REG_PROC: process( dat_addr_in ) - begin - buf_slv_select_x <= (others => '0'); - no_slave_reg_x <= '0'; - if dat_addr_in(15 downto 4) = x"F00" then - buf_slv_select_x(to_integer(unsigned(dat_addr_in(3 downto 0)))) <= '1'; - elsif dat_addr_in(15 downto 11) = x"A" & '0' then - buf_slv_select_x(16) <= '1'; - elsif dat_addr_in(15 downto 8) = x"80" then - buf_slv_select_x(17) <= '1'; - else - no_slave_reg_x <= '1'; - end if; - end process; - - - - --- synchronize signals -THE_SYNC_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - buf_slv_select <= buf_slv_select_x; - no_slave <= no_slave_reg_x and no_slave_mem_x; - end if; -end process THE_SYNC_PROC; - - --- Slave response lines -slave_ack <= slv_ack_in when ( no_slave = '0' ) else '0'; -slave_busy <= slv_busy_in when ( no_slave = '0' ) else '0'; -dat_data_out <= slv_data_in when ( no_slave = '0' ) else (others => '0'); - --- Data tunneling to slave entities -slv_data_out <= dat_data_in; - --- Read / write strobe -THE_READ_WRITE_STROBE_PROC: process( clk_in, clear_in ) -begin - if( clear_in = '1' ) then - buf_slv_read <= '0'; - buf_slv_write <= '0'; - elsif( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - buf_slv_read <= '0'; - buf_slv_write <= '0'; - elsif( (dat_read_enable_in = '1') and (dat_write_enable_in = '0') ) then - buf_slv_read <= '1'; - buf_slv_write <= '0'; - elsif( (dat_read_enable_in = '0') and (dat_write_enable_in = '1') ) then - buf_slv_read <= '0'; - buf_slv_write <= '1'; - elsif( rst_strb = '1' ) then - buf_slv_read <= '0'; - buf_slv_write <= '0'; - end if; - end if; -end process THE_READ_WRITE_STROBE_PROC; - - - --- The main state machine --- State memory process -STATE_MEM: process( clk_in, clear_in ) -begin - if( clear_in = '1' ) then - CURRENT_STATE <= SLEEP; - rst_strb <= '0'; - buf_dat_dataready <= '0'; - buf_dat_no_more_data <= '0'; - buf_dat_write_ack <= '0'; - buf_dat_unknown_addr <= '0'; - elsif( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - rst_strb <= '0'; - buf_dat_dataready <= '0'; - buf_dat_no_more_data <= '0'; - buf_dat_write_ack <= '0'; - buf_dat_unknown_addr <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - rst_strb <= rst_strb_x; - buf_dat_dataready <= buf_dat_dataready_x; - buf_dat_no_more_data <= buf_dat_no_more_data_x; - buf_dat_write_ack <= buf_dat_write_ack_x; - buf_dat_unknown_addr <= buf_dat_unknown_addr_x; - end if; - end if; -end process STATE_MEM; - --- Transition matrix -TRANSFORM: process(CURRENT_STATE, no_slave, buf_slv_read, buf_slv_write, slave_ack, slave_busy, dat_timeout_in ) -begin - NEXT_STATE <= SLEEP; - rst_strb_x <= '0'; - buf_dat_dataready_x <= '0'; - buf_dat_no_more_data_x <= '0'; - buf_dat_write_ack_x <= '0'; - buf_dat_unknown_addr_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( (no_slave = '1') and ((buf_slv_read = '1') or (buf_slv_write = '1')) ) then - NEXT_STATE <= NOONE; - buf_dat_unknown_addr_x <= '1'; - elsif( (buf_slv_read = '1') and (buf_slv_write = '0') ) then - NEXT_STATE <= RACC; - elsif( (buf_slv_read = '0') and (buf_slv_write = '1') ) then - NEXT_STATE <= WACC; - else - NEXT_STATE <= SLEEP; - end if; - when RACC => if ( dat_timeout_in = '1' ) then - NEXT_STATE <= DONE; - rst_strb_x <= '1'; - elsif( slave_busy = '1' ) then - NEXT_STATE <= RFAIL; - buf_dat_no_more_data_x <= '1'; - elsif( slave_ack = '1' ) then - NEXT_STATE <= ROK; - buf_dat_dataready_x <= '1'; - else - NEXT_STATE <= RACC; - end if; - when RFAIL => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when ROK => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when WACC => if ( dat_timeout_in = '1' ) then - NEXT_STATE <= DONE; - rst_strb_x <= '1'; - elsif( slave_busy = '1' ) then - NEXT_STATE <= WFAIL; - buf_dat_no_more_data_x <= '1'; - elsif( slave_ack = '1' ) then - NEXT_STATE <= WOK; - buf_dat_write_ack_x <= '1'; - else - NEXT_STATE <= WACC; - end if; - when WFAIL => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when WOK => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when NOONE => NEXT_STATE <= DONE; - rst_strb_x <= '1'; - when DONE => NEXT_STATE <= SLEEP; -- ????? - -- Just in case... - when others => NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - --- Output decoding -DECODE: process(CURRENT_STATE) -begin - case CURRENT_STATE is - when SLEEP => bsm <= x"0"; - when RACC => bsm <= x"1"; - when ROK => bsm <= x"2"; - when RFAIL => bsm <= x"3"; - when WACC => bsm <= x"4"; - when WOK => bsm <= x"5"; - when NOONE => bsm <= x"6"; - when DONE => bsm <= x"7"; - when others => bsm <= x"f"; - end case; -end process DECODE; - --- Outputs -dat_dataready_out <= buf_dat_dataready; -dat_no_more_data_out <= buf_dat_no_more_data; -dat_unknown_addr_out <= buf_dat_unknown_addr; -dat_write_ack_out <= buf_dat_write_ack; - -slv_select_out <= buf_slv_select; -slv_read_out <= buf_slv_read; -slv_write_out <= buf_slv_write; - -stat(31 downto 9) <= (others => '0'); -stat(8) <= rst_strb; -stat(7 downto 4) <= (others => '0'); -stat(3 downto 0) <= bsm; - -end Behavioral; diff --git a/oldfiles/etrax_interface.vhd b/oldfiles/etrax_interface.vhd deleted file mode 100644 index 3137620..0000000 --- a/oldfiles/etrax_interface.vhd +++ /dev/null @@ -1,274 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.all; - - -entity etrax_interface is - generic( - STATUS_REGISTERS : integer := 4; - CONTROL_REGISTERS : integer := 4 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - --Connection to Etrax - ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0); - ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0); - ETRAX_BUS_BUSY : out std_logic; - --Connection to internal FPGA logic (all addresses above 0x100) - INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); - INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); - INTERNAL_READ_OUT : out std_logic; - INTERNAL_WRITE_OUT : out std_logic; - INTERNAL_DATAREADY_IN : in std_logic; - INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0); - --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl) - FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0); - FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0); - --Reset FPGA via Etrax - EXTERNAL_RESET : out std_logic; - STAT : out std_logic_vector(15 downto 0) - ); -end etrax_interface; -architecture etrax_interface of etrax_interface is - - component signal_sync is - generic( - WIDTH : integer := 2; - DEPTH : integer := 1 - ); - port( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic_vector(WIDTH-1 downto 0); - D_OUT : out std_logic_vector(WIDTH-1 downto 0) - ); - end component; - - type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_DATA_2, WAIT_FOR_DATA, SEND_EXTERNAL_TRIGGER ); --SEND_VALID - signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate : ETRAX_RW_STATE_MACHINE; - - signal etrax_trigger_pulse : std_logic; - signal saved_address : std_logic_vector (15 downto 0); - signal saved_data : std_logic_vector(31 downto 0); - signal saved_data_fpga : std_logic_vector(31 downto 0); - - signal read_cycle : std_logic; - signal write_cycle : std_logic; - - signal etrax_is_ready_to_read_i : std_logic; - signal internal_reset_i : std_logic; - signal communication_state : std_logic_vector(3 downto 0); - signal buf_FPGA_REGISTER_OUT : std_logic_vector(CONTROL_REGISTERS*32-1 downto 0); - signal last_BUSC : std_logic_vector(17 downto 16); - signal reg_BUSC : std_logic_vector(17 downto 0); - - signal delayed_internal_reset_i : std_logic; - -begin - - STAT(3 downto 0) <= communication_state; - STAT(4) <= read_cycle; - STAT(5) <= write_cycle; - STAT(6) <= reg_BUSC(16); - STAT(7) <= etrax_trigger_pulse; - STAT(8) <= reg_BUSC(17); - - MAKE_RESET: process (CLK) - begin - if rising_edge(CLK) then - if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') or RESET = '1' then - internal_reset_i <= '1'; - else - internal_reset_i <= '0'; - end if; - end if; - end process MAKE_RESET; - - BUSC_SYNC : signal_sync - generic map( - WIDTH => 18, - DEPTH => 1 - ) - port map( - RESET => RESET, - CLK0 => CLK, - CLK1 => CLK, - D_IN => ETRAX_DATA_BUS_C, - D_OUT => reg_BUSC - ); - - THE_RESET_DELAY : signal_sync - generic map( - WIDTH => 1, - DEPTH => 4 - ) - port map( - RESET => '0', - CLK0 => CLK, - CLK1 => CLK, - D_IN(0) => internal_reset_i, - D_OUT(0) => delayed_internal_reset_i - ); - - process(CLK) - begin - if rising_edge(CLK) then - last_BUSC <= reg_BUSC(17 downto 16); - end if; - end process; - - etrax_trigger_pulse <= (last_BUSC(16) xor reg_BUSC(16)) and not delayed_internal_reset_i; - - EXTERNAL_RESET <= internal_reset_i or delayed_internal_reset_i; - ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1'; - - read_cycle <= saved_address(15); - write_cycle <= not saved_address(15); - - ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK) - begin - if rising_edge(CLK) then - if delayed_internal_reset_i = '1' then - ETRAX_RW_STATE_currentstate <= IDLE; - else - ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate; - end if; - end if; - end process; - - ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse, --saved_rw_mode(15) - read_cycle, write_cycle, INTERNAL_DATAREADY_IN, saved_address) - begin - communication_state <= x"1"; - ETRAX_RW_STATE_nextstate <= ETRAX_RW_STATE_currentstate; - case ETRAX_RW_STATE_currentstate is - when IDLE => - communication_state <= x"1"; - if etrax_trigger_pulse = '1' then - ETRAX_RW_STATE_nextstate <= SAVE_DATA_1; - end if; - - when SAVE_DATA_1 => - communication_state <= x"2"; - if read_cycle = '1' then - ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER; - elsif etrax_trigger_pulse = '1' then - ETRAX_RW_STATE_nextstate <= SAVE_DATA_2; - end if; - - when SAVE_DATA_2 => - communication_state <= x"3"; - if etrax_trigger_pulse = '1' then - ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER; - end if; - - when SEND_EXTERNAL_TRIGGER => - communication_state <= x"4"; - if read_cycle = '1' and (INTERNAL_DATAREADY_IN = '1' or saved_address(14 downto 5) = 0) then - ETRAX_RW_STATE_nextstate <= SEND_DATA_1; - elsif write_cycle = '1' then - ETRAX_RW_STATE_nextstate <= IDLE; - else - ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA; - end if; - - when WAIT_FOR_DATA => - communication_state <= x"5"; - if INTERNAL_DATAREADY_IN = '1' then - ETRAX_RW_STATE_nextstate <= SEND_DATA_1; - end if; - - when SEND_DATA_1 => - communication_state <= x"6"; - if etrax_trigger_pulse = '1' then - ETRAX_RW_STATE_nextstate <= SEND_DATA_2; - end if; - - when SEND_DATA_2 => - communication_state <= x"7"; - if etrax_trigger_pulse = '1' then - ETRAX_RW_STATE_nextstate <= IDLE; - end if; - end case; - end process ETRAX_FPGA_COMUNICATION; - - REGISTER_ETRAX_BUS: process (CLK) - begin - if rising_edge(CLK) then - if delayed_internal_reset_i = '1' then - saved_address <= (others => '0'); - saved_data <= (others => '0'); - elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then - saved_address(15 downto 0) <= reg_BUSC(15 downto 0); - elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then - saved_data(31 downto 16) <= reg_BUSC(15 downto 0); - elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then - saved_data(15 downto 0) <= reg_BUSC(15 downto 0); - end if; - end if; - end process REGISTER_ETRAX_BUS; - - - INTERNAL_ADDRESS_OUT <= '0' & saved_address(14 downto 0); - INTERNAL_DATA_OUT <= saved_data; - - INTERNAL_WRITE_OUT <= '1' when write_cycle = '1' and saved_address(14 downto 5) /= 0 - and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER - else '0'; - INTERNAL_READ_OUT <= '1' when read_cycle = '1' and saved_address(14 downto 5) /= 0 - and ETRAX_RW_STATE_currentstate = SAVE_DATA_1 - else '0'; - - FPGA_REGISTER_OUT <= buf_FPGA_REGISTER_OUT; - - ETRAX_DATA_BUS_CHOOSE : process (CLK) - begin - if rising_edge(CLK) then - if delayed_internal_reset_i = '1' then - ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000"; - elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then - ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16); - ETRAX_DATA_BUS_B(16) <= '1'; - elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 then - ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0); - ETRAX_DATA_BUS_B(16) <= '1'; - else - ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000"; - end if; - end if; - end process ETRAX_DATA_BUS_CHOOSE; - - ETRAX_DATA_BUS_B(17) <= '1'; - - DATA_SOURCE_SELECT : process (CLK) - variable stat_num : integer range 0 to STATUS_REGISTERS-1; - variable ctrl_num : integer range 0 to CONTROL_REGISTERS-1; - begin - if rising_edge(CLK) then - stat_num := conv_integer(saved_address(3 downto 0)); - ctrl_num := conv_integer(saved_address(3 downto 0)); - if read_cycle = '1' then - if saved_address(14 downto 5) = 0 then - if saved_address(4) = '0' then --status regs - saved_data_fpga <= FPGA_REGISTER_IN((stat_num)*32+31 downto stat_num*32); - elsif saved_address(4) = '1' then - saved_data_fpga <= buf_FPGA_REGISTER_OUT((ctrl_num)*32+31 downto (ctrl_num)*32); - else - saved_data_fpga <= (others => '0'); - end if; - elsif INTERNAL_DATAREADY_IN = '1' then - saved_data_fpga <= INTERNAL_DATA_IN; - end if; - elsif write_cycle = '1' and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER then - if saved_address(4) = '1' and saved_address(14 downto 5) = 0 then - buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data; - end if; - end if; - - end if; - end process DATA_SOURCE_SELECT; -end architecture; diff --git a/oldfiles/rom_16x8.vhd b/oldfiles/rom_16x8.vhd deleted file mode 100644 index f664fe8..0000000 --- a/oldfiles/rom_16x8.vhd +++ /dev/null @@ -1,47 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity rom_16x8 is - generic( - INIT0 : std_logic_vector(15 downto 0) := x"12A0"; - INIT1 : std_logic_vector(15 downto 0) := x"23b1"; - INIT2 : std_logic_vector(15 downto 0) := x"34c2"; - INIT3 : std_logic_vector(15 downto 0) := x"49d3"; - INIT4 : std_logic_vector(15 downto 0) := x"56e5"; - INIT5 : std_logic_vector(15 downto 0) := x"67d5"; - INIT6 : std_logic_vector(15 downto 0) := x"7818"; - INIT7 : std_logic_vector(15 downto 0) := x"8927" - ); - port( - CLK : in std_logic; - a : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture rom_16x8_arch of rom_16x8 is - type ram_t is array(0 to 7) of std_logic_vector(15 downto 0); - SIGNAL rom : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7); -begin - rom(0) <= INIT0; - rom(1) <= INIT1; - rom(2) <= INIT2; - rom(3) <= INIT3; - rom(4) <= INIT4; - rom(5) <= INIT5; - rom(6) <= INIT6; - rom(7) <= INIT7; - - process(CLK) - begin - if rising_edge(CLK) then - dout <= rom(conv_integer(a)); - end if; - end process; - -end architecture; \ No newline at end of file diff --git a/oldfiles/serdes_sync_0/serdes_sync_0.vhd b/oldfiles/serdes_sync_0/serdes_sync_0.vhd deleted file mode 100644 index e16adaf..0000000 --- a/oldfiles/serdes_sync_0/serdes_sync_0.vhd +++ /dev/null @@ -1,435 +0,0 @@ - --- --- Verific VHDL Description of module DCUA --- - --- DCUA is a black-box. Cannot print a valid VHDL entity description for it - --- --- Verific VHDL Description of module serdes_sync_0rsl_core --- - --- serdes_sync_0rsl_core is a black-box. Cannot print a valid VHDL entity description for it - --- --- Verific VHDL Description of module serdes_sync_0sll_core --- - --- serdes_sync_0sll_core is a black-box. Cannot print a valid VHDL entity description for it - --- --- Verific VHDL Description of module serdes_sync_0 --- - -library ieee ; -use ieee.std_logic_1164.all ; - -library ecp5um ; -use ecp5um.components.all ; - -entity serdes_sync_0 is - port (hdoutp: out std_logic; - hdoutn: out std_logic; - hdinp: in std_logic; - hdinn: in std_logic; - rxrefclk: in std_logic; - rx_pclk: out std_logic; - tx_pclk: out std_logic; - txdata: in std_logic_vector(7 downto 0); - tx_k: in std_logic_vector(0 downto 0); - tx_force_disp: in std_logic_vector(0 downto 0); - tx_disp_sel: in std_logic_vector(0 downto 0); - rxdata: out std_logic_vector(7 downto 0); - rx_k: out std_logic_vector(0 downto 0); - rx_disp_err: out std_logic_vector(0 downto 0); - rx_cv_err: out std_logic_vector(0 downto 0); - tx_idle_c: in std_logic; - signal_detect_c: in std_logic; - rx_los_low_s: out std_logic; - lsm_status_s: out std_logic; - rx_cdr_lol_s: out std_logic; - sli_rst: in std_logic; - tx_pwrup_c: in std_logic; - rx_pwrup_c: in std_logic; - sci_wrdata: in std_logic_vector(7 downto 0); - sci_addr: in std_logic_vector(5 downto 0); - sci_rddata: out std_logic_vector(7 downto 0); - sci_en_dual: in std_logic; - sci_sel_dual: in std_logic; - sci_en: in std_logic; - sci_sel: in std_logic; - sci_rd: in std_logic; - sci_wrn: in std_logic; - sci_int: out std_logic; - cyawstn: in std_logic; - serdes_pdb: in std_logic; - pll_refclki: in std_logic; - rsl_disable: in std_logic; - rsl_rst: in std_logic; - serdes_rst_dual_c: in std_logic; - rst_dual_c: in std_logic; - tx_serdes_rst_c: in std_logic; - tx_pcs_rst_c: in std_logic; - pll_lol: out std_logic; - rsl_tx_rdy: out std_logic; - rx_serdes_rst_c: in std_logic; - rx_pcs_rst_c: in std_logic; - rsl_rx_rdy: out std_logic - ); - -end entity serdes_sync_0; - -architecture v1 of serdes_sync_0 is - component serdes_sync_0rsl_core is - generic (pnum_channels: integer := 1; - pprotocol: string := "G8B10B"; - pserdes_mode: string := "RX AND TX"; - pport_tx_rdy: string := "ENABLED"; - pwait_tx_rdy: integer := 3000; - pport_rx_rdy: string := "ENABLED"; - pwait_rx_rdy: integer := 3000); - port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) - rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) - rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) - rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) - rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) - rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) - rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) - rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) - rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) - rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) - rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) - rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) - rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) - rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) - rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) - ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) - rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) - rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) - ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) - rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) - rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) - ); - - end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) - component serdes_sync_0sll_core is - generic (PPROTOCOL: string := "G8B10B"; - PLOL_SETTING: integer := 1; - PDYN_RATE_CTRL: string := "DISABLED"; - PPCIE_MAX_RATE: string := "2.5"; - PDIFF_VAL_LOCK: integer := 19; - PDIFF_VAL_UNLOCK: integer := 131; - PPCLK_TC: integer := 65536; - PDIFF_DIV11_VAL_LOCK: integer := 0; - PDIFF_DIV11_VAL_UNLOCK: integer := 0; - PPCLK_DIV11_TC: integer := 0); - port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) - sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) - sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) - sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) - sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) - sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) - sli_cpri_mode: in std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) - sli_pcie_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) - slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) - ); - - end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) - signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9, - n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17, - n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c, - rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23, - n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37, - n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51, - n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65, - n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79, - n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93, - n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114, - n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122, - n123,\_Z\,n127,n126,gnd,pwr : std_logic; - attribute LOC : string; - attribute LOC of DCU0_inst : label is "DCU0"; - attribute CHAN : string; - attribute CHAN of DCU0_inst : label is "CH0"; -begin - rx_pclk <= rx_pclk_c; - tx_pclk <= tx_pclk_c; - rx_los_low_s <= rx_los_low_s_c; - rx_cdr_lol_s <= rx_cdr_lol_s_c; - pll_lol <= pll_lol_c; - DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", - D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", - D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", - D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", - CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", - CH0_GE_AN_ENABLE=>"0b0",CH0_PRBS_LOCK=>"0b0",CH0_PRBS_ENABLE=>"0b0", - CH0_ENABLE_CG_ALIGN=>"0b1",CH0_TX_GEAR_MODE=>"0b0",CH0_RX_GEAR_MODE=>"0b0", - CH0_PCS_DET_TIME_SEL=>"0b00",CH0_PCIE_EI_EN=>"0b0",CH0_TX_GEAR_BYPASS=>"0b0", - CH0_ENC_BYPASS=>"0b0",CH0_SB_BYPASS=>"0b0",CH0_RX_SB_BYPASS=>"0b0", - CH0_WA_BYPASS=>"0b0",CH0_DEC_BYPASS=>"0b0",CH0_CTC_BYPASS=>"0b1", - CH0_RX_GEAR_BYPASS=>"0b0",CH0_LSM_DISABLE=>"0b0",CH0_MATCH_2_ENABLE=>"0b0", - CH0_MATCH_4_ENABLE=>"0b1",CH0_MIN_IPG_CNT=>"0b11",CH0_CC_MATCH_1=>"0x1BC", - CH0_CC_MATCH_2=>"0x11C",CH0_CC_MATCH_3=>"0x11C",CH0_CC_MATCH_4=>"0x11C", - CH0_UDF_COMMA_MASK=>"0x0ff",CH0_UDF_COMMA_A=>"0x083",CH0_UDF_COMMA_B=>"0x07C", - CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1", - CH0_RATE_MODE_TX=>"0b0",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00", - CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b00",CH0_TDRV_SLICE1_SEL=>"0b00", - CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b01", - CH0_TDRV_SLICE5_SEL=>"0b00",CH0_TDRV_SLICE0_CUR=>"0b000",CH0_TDRV_SLICE1_CUR=>"0b000", - CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b11",CH0_TDRV_SLICE4_CUR=>"0b01", - CH0_TDRV_SLICE5_CUR=>"0b00",CH0_TDRV_DAT_SEL=>"0b00",CH0_TX_DIV11_SEL=>"0b0", - CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b0",CH0_RX_DIV11_SEL=>"0b0", - CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0", - CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0", - CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00", - CH0_REQ_EN=>"0b1",CH0_RTERM_RX=>"0d22",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b1", - CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000", - CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b100",CH0_RX_LOS_CEQ=>"0b11", - CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0", - CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH0_CDR_MAX_RATE=>"2", - CH0_TXAMPLITUDE=>"0d800",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED", - CH0_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01", - D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001", - D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH0_CDR_CNT4SEL=>"0b00", - CH0_CDR_CNT8SEL=>"0b00",CH0_DCOATDCFG=>"0b00",CH0_DCOATDDLY=>"0b00", - CH0_DCOBYPSATD=>"0b1",CH0_DCOCALDIV=>"0b000",CH0_DCOCTLGI=>"0b011", - CH0_DCODISBDAVOID=>"0b0",CH0_DCOFLTDAC=>"0b00",CH0_DCOFTNRG=>"0b001", - CH0_DCOIOSTUNE=>"0b010",CH0_DCOITUNE=>"0b00",CH0_DCOITUNE4LSB=>"0b010", - CH0_DCOIUPDNX2=>"0b1",CH0_DCONUOFLSB=>"0b100",CH0_DCOSCALEI=>"0b01", - CH0_DCOSTARTVAL=>"0b010",CH0_DCOSTEP=>"0b11",CH0_BAND_THRESHOLD=>"0d0", - CH0_AUTO_FACQ_EN=>"0b1",CH0_AUTO_CALIB_EN=>"0b1",CH0_CALIB_CK_MODE=>"0b0", - CH0_REG_BAND_OFFSET=>"0d0",CH0_REG_BAND_SEL=>"0d0",CH0_REG_IDAC_SEL=>"0d0", - CH0_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", - D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", - D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", - D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d10", - D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01", - D_RG_EN=>"0b0",D_RG_SET=>"0b00") - port map (CH0_HDINP=>hdinp,CH1_HDINP=>n106,CH0_HDINN=>hdinn,CH1_HDINN=>n106, - D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47, - CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n106,CH0_FF_RXI_CLK=>rx_pclk_c, - CH1_FF_RXI_CLK=>n105,CH0_FF_TXI_CLK=>tx_pclk_c,CH1_FF_TXI_CLK=>n105,CH0_FF_EBRD_CLK=>n48, - CH1_FF_EBRD_CLK=>n105,CH0_FF_TX_D_0=>txdata(0),CH1_FF_TX_D_0=>n106,CH0_FF_TX_D_1=>txdata(1), - CH1_FF_TX_D_1=>n106,CH0_FF_TX_D_2=>txdata(2),CH1_FF_TX_D_2=>n106,CH0_FF_TX_D_3=>txdata(3), - CH1_FF_TX_D_3=>n106,CH0_FF_TX_D_4=>txdata(4),CH1_FF_TX_D_4=>n106,CH0_FF_TX_D_5=>txdata(5), - CH1_FF_TX_D_5=>n106,CH0_FF_TX_D_6=>txdata(6),CH1_FF_TX_D_6=>n106,CH0_FF_TX_D_7=>txdata(7), - CH1_FF_TX_D_7=>n106,CH0_FF_TX_D_8=>tx_k(0),CH1_FF_TX_D_8=>n106,CH0_FF_TX_D_9=>tx_force_disp(0), - CH1_FF_TX_D_9=>n106,CH0_FF_TX_D_10=>tx_disp_sel(0),CH1_FF_TX_D_10=>n106, - CH0_FF_TX_D_11=>n47,CH1_FF_TX_D_11=>n106,CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106, - CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106,CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106, - CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106,CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106, - CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106,CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106, - CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106,CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106, - CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106,CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106, - CH0_FF_TX_D_23=>n47,CH1_FF_TX_D_23=>n106,CH0_FFC_EI_EN=>tx_idle_c,CH1_FFC_EI_EN=>n106, - CH0_FFC_PCIE_DET_EN=>n47,CH1_FFC_PCIE_DET_EN=>n106,CH0_FFC_PCIE_CT=>n47, - CH1_FFC_PCIE_CT=>n106,CH0_FFC_SB_INV_RX=>n106,CH1_FFC_SB_INV_RX=>n106, - CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106,CH0_FFC_SIGNAL_DETECT=>signal_detect_c, - CH1_FFC_SIGNAL_DETECT=>n106,CH0_FFC_FB_LOOPBACK=>n47,CH1_FFC_FB_LOOPBACK=>n106, - CH0_FFC_SB_PFIFO_LP=>n47,CH1_FFC_SB_PFIFO_LP=>n106,CH0_FFC_PFIFO_CLR=>n47, - CH1_FFC_PFIFO_CLR=>n106,CH0_FFC_RATE_MODE_RX=>n106,CH1_FFC_RATE_MODE_RX=>n106, - CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106,CH0_FFC_DIV11_MODE_RX=>n47, - CH1_FFC_DIV11_MODE_RX=>n106,CH0_FFC_DIV11_MODE_TX=>n47,CH1_FFC_DIV11_MODE_TX=>n106, - CH0_FFC_RX_GEAR_MODE=>n47,CH1_FFC_RX_GEAR_MODE=>n106,CH0_FFC_TX_GEAR_MODE=>n47, - CH1_FFC_TX_GEAR_MODE=>n106,CH0_FFC_LDR_CORE2TX_EN=>n106,CH1_FFC_LDR_CORE2TX_EN=>n106, - CH0_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH1_FFC_LANE_TX_RST=>n106,CH0_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c, - CH1_FFC_LANE_RX_RST=>n106,CH0_FFC_RRST=>rsl_rx_serdes_rst_c,CH1_FFC_RRST=>n106, - CH0_FFC_TXPWDNB=>tx_pwrup_c,CH1_FFC_TXPWDNB=>n106,CH0_FFC_RXPWDNB=>rx_pwrup_c, - CH1_FFC_RXPWDNB=>n106,CH0_LDR_CORE2TX=>n106,CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0), - D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3), - D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6), - D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1), - D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4), - D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual, - CH0_SCIEN=>sci_en,CH1_SCIEN=>n106,CH0_SCISEL=>sci_sel,CH1_SCISEL=>n106, - D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106, - D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, - D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n47, - CH1_FFC_CDR_EN_BITSLIP=>n106,D_SCAN_ENABLE=>n47,D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47, - D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47,D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47, - D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47,D_SCAN_MODE=>n47,D_SCAN_RESET=>n47, - D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47,D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47, - D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47,D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47, - CH0_HDOUTP=>hdoutp,CH1_HDOUTP=>n50,CH0_HDOUTN=>hdoutn,CH1_HDOUTN=>n51, - D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, - CH0_FF_RX_F_CLK=>n5,CH1_FF_RX_F_CLK=>n52,CH0_FF_RX_H_CLK=>n6,CH1_FF_RX_H_CLK=>n53, - CH0_FF_TX_F_CLK=>n7,CH1_FF_TX_F_CLK=>n54,CH0_FF_TX_H_CLK=>n8,CH1_FF_TX_H_CLK=>n55, - CH0_FF_RX_PCLK=>rx_pclk_c,CH1_FF_RX_PCLK=>n56,CH0_FF_TX_PCLK=>tx_pclk_c, - CH1_FF_TX_PCLK=>n57,CH0_FF_RX_D_0=>rxdata(0),CH1_FF_RX_D_0=>n58,CH0_FF_RX_D_1=>rxdata(1), - CH1_FF_RX_D_1=>n59,CH0_FF_RX_D_2=>rxdata(2),CH1_FF_RX_D_2=>n60,CH0_FF_RX_D_3=>rxdata(3), - CH1_FF_RX_D_3=>n61,CH0_FF_RX_D_4=>rxdata(4),CH1_FF_RX_D_4=>n62,CH0_FF_RX_D_5=>rxdata(5), - CH1_FF_RX_D_5=>n63,CH0_FF_RX_D_6=>rxdata(6),CH1_FF_RX_D_6=>n64,CH0_FF_RX_D_7=>rxdata(7), - CH1_FF_RX_D_7=>n65,CH0_FF_RX_D_8=>rx_k(0),CH1_FF_RX_D_8=>n66,CH0_FF_RX_D_9=>rx_disp_err(0), - CH1_FF_RX_D_9=>n67,CH0_FF_RX_D_10=>rx_cv_err(0),CH1_FF_RX_D_10=>n68,CH0_FF_RX_D_11=>n9, - CH1_FF_RX_D_11=>n69,CH0_FF_RX_D_12=>n70,CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72, - CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76, - CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80, - CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84, - CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88, - CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n10, - CH1_FF_RX_D_23=>n92,CH0_FFS_PCIE_DONE=>n11,CH1_FFS_PCIE_DONE=>n93,CH0_FFS_PCIE_CON=>n12, - CH1_FFS_PCIE_CON=>n94,CH0_FFS_RLOS=>rx_los_low_s_c,CH1_FFS_RLOS=>n95, - CH0_FFS_LS_SYNC_STATUS=>lsm_status_s,CH1_FFS_LS_SYNC_STATUS=>n96,CH0_FFS_CC_UNDERRUN=>n13, - CH1_FFS_CC_UNDERRUN=>n97,CH0_FFS_CC_OVERRUN=>n14,CH1_FFS_CC_OVERRUN=>n98, - CH0_FFS_RXFBFIFO_ERROR=>n15,CH1_FFS_RXFBFIFO_ERROR=>n99,CH0_FFS_TXFBFIFO_ERROR=>n16, - CH1_FFS_TXFBFIFO_ERROR=>n100,CH0_FFS_RLOL=>rx_cdr_lol_s_c,CH1_FFS_RLOL=>n101, - CH0_FFS_SKP_ADDED=>n17,CH1_FFS_SKP_ADDED=>n102,CH0_FFS_SKP_DELETED=>n18, - CH1_FFS_SKP_DELETED=>n103,CH0_LDR_RX2CORE=>n104,CH1_LDR_RX2CORE=>n115, - D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), - D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), - D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, - D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,D_SCAN_OUT_3=>n22, - D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,D_SCAN_OUT_7=>n26, - D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,D_COUT4=>n31,D_COUT5=>n32, - D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,D_COUT10=>n37,D_COUT11=>n38, - D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,D_COUT15=>n42,D_COUT16=>n43, - D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49); - n48 <= '1' ; - n47 <= '0' ; - n1 <= 'Z' ; - n2 <= 'Z' ; - n3 <= 'Z' ; - n4 <= 'Z' ; - n5 <= 'Z' ; - n6 <= 'Z' ; - n7 <= 'Z' ; - n8 <= 'Z' ; - n9 <= 'Z' ; - n10 <= 'Z' ; - n11 <= 'Z' ; - n12 <= 'Z' ; - n13 <= 'Z' ; - n14 <= 'Z' ; - n15 <= 'Z' ; - n16 <= 'Z' ; - n17 <= 'Z' ; - n18 <= 'Z' ; - n19 <= 'Z' ; - n20 <= 'Z' ; - n21 <= 'Z' ; - n22 <= 'Z' ; - n23 <= 'Z' ; - n24 <= 'Z' ; - n25 <= 'Z' ; - n26 <= 'Z' ; - n27 <= 'Z' ; - n28 <= 'Z' ; - n29 <= 'Z' ; - n30 <= 'Z' ; - n31 <= 'Z' ; - n32 <= 'Z' ; - n33 <= 'Z' ; - n34 <= 'Z' ; - n35 <= 'Z' ; - n36 <= 'Z' ; - n37 <= 'Z' ; - n38 <= 'Z' ; - n39 <= 'Z' ; - n40 <= 'Z' ; - n41 <= 'Z' ; - n42 <= 'Z' ; - n43 <= 'Z' ; - n44 <= 'Z' ; - n45 <= 'Z' ; - n46 <= 'Z' ; - n49 <= 'Z' ; - n106 <= '0' ; - n105 <= '1' ; - n50 <= 'Z' ; - n51 <= 'Z' ; - n52 <= 'Z' ; - n53 <= 'Z' ; - n54 <= 'Z' ; - n55 <= 'Z' ; - n56 <= 'Z' ; - n57 <= 'Z' ; - n58 <= 'Z' ; - n59 <= 'Z' ; - n60 <= 'Z' ; - n61 <= 'Z' ; - n62 <= 'Z' ; - n63 <= 'Z' ; - n64 <= 'Z' ; - n65 <= 'Z' ; - n66 <= 'Z' ; - n67 <= 'Z' ; - n68 <= 'Z' ; - n69 <= 'Z' ; - n70 <= 'Z' ; - n71 <= 'Z' ; - n72 <= 'Z' ; - n73 <= 'Z' ; - n74 <= 'Z' ; - n75 <= 'Z' ; - n76 <= 'Z' ; - n77 <= 'Z' ; - n78 <= 'Z' ; - n79 <= 'Z' ; - n80 <= 'Z' ; - n81 <= 'Z' ; - n82 <= 'Z' ; - n83 <= 'Z' ; - n84 <= 'Z' ; - n85 <= 'Z' ; - n86 <= 'Z' ; - n87 <= 'Z' ; - n88 <= 'Z' ; - n89 <= 'Z' ; - n90 <= 'Z' ; - n91 <= 'Z' ; - n92 <= 'Z' ; - n93 <= 'Z' ; - n94 <= 'Z' ; - n95 <= 'Z' ; - n96 <= 'Z' ; - n97 <= 'Z' ; - n98 <= 'Z' ; - n99 <= 'Z' ; - n100 <= 'Z' ; - n101 <= 'Z' ; - n102 <= 'Z' ; - n103 <= 'Z' ; - n104 <= 'Z' ; - n115 <= 'Z' ; - rsl_inst: component serdes_sync_0rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, - rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, - rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125, - rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, - rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125, - rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, - rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125, - rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125, - rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c, - rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125, - rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, - rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, - rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118, - rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119, - rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, - rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\, - rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); - n114 <= '1' ; - n113 <= '0' ; - n125 <= '0' ; - n124 <= '1' ; - n116 <= 'Z' ; - n117 <= 'Z' ; - n118 <= 'Z' ; - n119 <= 'Z' ; - n120 <= 'Z' ; - n121 <= 'Z' ; - n122 <= 'Z' ; - n123 <= 'Z' ; - \_Z\ <= 'Z' ; - sll_inst: component serdes_sync_0sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, - sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, - sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, - sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); - n127 <= '1' ; - n126 <= '0' ; - gnd <= '0' ; - pwr <= '1' ; - -end architecture v1; - diff --git a/oldfiles/serdes_sync_0/serdes_sync_0_softlogic.v b/oldfiles/serdes_sync_0/serdes_sync_0_softlogic.v deleted file mode 100644 index 186f088..0000000 --- a/oldfiles/serdes_sync_0/serdes_sync_0_softlogic.v +++ /dev/null @@ -1,2003 +0,0 @@ - - -// =========================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// --------------------------------------------------------------------------- -// Copyright (c) 2016 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code -// pursuant to the terms of the Lattice Reference Design License Agreement. -// -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// --------------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// --------------------------------------------------------------------------- -// -// ============================================================================= -// FILE DETAILS -// Project : RSL- Reset Sequence Logic -// File : rsl_core.v -// Title : Top-level file for RSL -// Dependencies : 1. -// : 2. -// Description : -// ============================================================================= -// REVISION HISTORY -// Version : 1.0 -// Author(s) : BM -// Mod. Date : October 28, 2013 -// Changes Made : Initial Creation -// ----------------------------------------------------------------------------- -// Version : 1.1 -// Author(s) : BM -// Mod. Date : November 06, 2013 -// Changes Made : Tx/Rx separation, ready port code exclusion -// ----------------------------------------------------------------------------- -// Version : 1.2 -// Author(s) : BM -// Mod. Date : June 13, 2014 -// Changes Made : Updated Rx PCS reset method -// ----------------------------------------------------------------------------- -// ----------------------------------------------------------------------------- -// Version : 1.3 -// Author(s) : UA -// Mod. Date : Dec 19, 2014 -// Changes Made : Added new parameter fro PCIE -// ----------------------------------------------------------------------------- -// Version : 1.31 -// Author(s) : BM/UM -// Mod. Date : Feb 23, 2016 -// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy -// and the rx_rdy wait counter are reset to zero on -// LOL or LOS. Reverted back the counter value change for PCIE. -// ----------------------------------------------------------------------------- -// Version : 1.4 -// Author(s) : EB -// Mod. Date: : March 21, 2017 -// Changes Made : -// ----------------------------------------------------------------------------- -// Version : 1.5 -// Author(s) : ES -// Mod. Date: : May 8, 2017 -// Changes Made : Implemented common RSL behaviour as proposed by BM. -// ============================================================================= - -`timescale 1ns/10ps - -module serdes_sync_0rsl_core ( - // ------------ Inputs - // Common - rui_rst, // Active high reset for the RSL module - rui_serdes_rst_dual_c, // SERDES macro reset user command - rui_rst_dual_c, // PCS dual reset user command - rui_rsl_disable, // Active high signal that disables all reset outputs of RSL - // Tx - rui_tx_ref_clk, // Tx reference clock - rui_tx_serdes_rst_c, // Tx SERDES reset user command - rui_tx_pcs_rst_c, // Tx lane reset user command - rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES - // Rx - rui_rx_ref_clk, // Rx reference clock - rui_rx_serdes_rst_c, // SERDES Receive channel reset user command - rui_rx_pcs_rst_c, // Rx lane reset user command - rdi_rx_los_low_s, // Receive loss of signal status input from SERDES - rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES - - // ------------ Outputs - // Common - rdo_serdes_rst_dual_c, // SERDES macro reset command output - rdo_rst_dual_c, // PCS dual reset command output - // Tx - ruo_tx_rdy, // Tx lane ready status output - rdo_tx_serdes_rst_c, // SERDES Tx reset command output - rdo_tx_pcs_rst_c, // PCS Tx lane reset command output - // Rx - ruo_rx_rdy, // Rx lane ready status output - rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output - rdo_rx_pcs_rst_c // PCS Rx lane reset command output - ); - -// ------------ Module parameters -`ifdef NUM_CHANNELS - parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 -`else - parameter pnum_channels = 1; -`endif - -`ifdef PCIE - parameter pprotocol = "PCIE"; -`else - parameter pprotocol = ""; -`endif - -`ifdef RX_ONLY - parameter pserdes_mode = "RX ONLY"; -`else - `ifdef TX_ONLY - parameter pserdes_mode = "TX ONLY"; - `else - parameter pserdes_mode = "RX AND TX"; - `endif -`endif - -`ifdef PORT_TX_RDY - parameter pport_tx_rdy = "ENABLED"; -`else - parameter pport_tx_rdy = "DISABLED"; -`endif - -`ifdef WAIT_TX_RDY - parameter pwait_tx_rdy = `WAIT_TX_RDY; -`else - parameter pwait_tx_rdy = 3000; -`endif - -`ifdef PORT_RX_RDY - parameter pport_rx_rdy = "ENABLED"; -`else - parameter pport_rx_rdy = "DISABLED"; -`endif - -`ifdef WAIT_RX_RDY - parameter pwait_rx_rdy = `WAIT_RX_RDY; -`else - parameter pwait_rx_rdy = 3000; -`endif - -// ------------ Local parameters - localparam wa_num_cycles = 1024; - localparam dac_num_cycles = 3; - localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 - localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz - localparam lwait_b4_trst_s = 781; // for simulation - localparam lplol_cnt_width = 20; // width for lwait_b4_trst - localparam lwait_after_plol0 = 4; - localparam lwait_b4_rrst = 180224; // total calibration time - localparam lrrst_wait_width = 20; - localparam lwait_after_rrst = 800000; // For CPRI- unused - localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team - localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst - localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles - localparam lwait_after_lols_s = 150; // wait cycles provided by design team - localparam llols_cnt_width = 18; // lols count width - localparam lrdb_max = 15; // maximum debounce count - localparam ltxr_wait_width = 12; // width of tx ready wait counter - localparam lrxr_wait_width = 12; // width of tx ready wait counter - -// ------------ input ports - input rui_rst; - input rui_serdes_rst_dual_c; - input rui_rst_dual_c; - input rui_rsl_disable; - - input rui_tx_ref_clk; - input rui_tx_serdes_rst_c; - input [3:0] rui_tx_pcs_rst_c; - input rdi_pll_lol; - - input rui_rx_ref_clk; - input [3:0] rui_rx_serdes_rst_c; - input [3:0] rui_rx_pcs_rst_c; - input [3:0] rdi_rx_los_low_s; - input [3:0] rdi_rx_cdr_lol_s; - -// ------------ output ports - output rdo_serdes_rst_dual_c; - output rdo_rst_dual_c; - - output ruo_tx_rdy; - output rdo_tx_serdes_rst_c; - output [3:0] rdo_tx_pcs_rst_c; - - output ruo_rx_rdy; - output [3:0] rdo_rx_serdes_rst_c; - output [3:0] rdo_rx_pcs_rst_c; - -// ------------ Internal registers and wires - // inputs - wire rui_rst; - wire rui_serdes_rst_dual_c; - wire rui_rst_dual_c; - wire rui_rsl_disable; - wire rui_tx_ref_clk; - wire rui_tx_serdes_rst_c; - wire [3:0] rui_tx_pcs_rst_c; - wire rdi_pll_lol; - wire rui_rx_ref_clk; - wire [3:0] rui_rx_serdes_rst_c; - wire [3:0] rui_rx_pcs_rst_c; - wire [3:0] rdi_rx_los_low_s; - wire [3:0] rdi_rx_cdr_lol_s; - - // outputs - wire rdo_serdes_rst_dual_c; - wire rdo_rst_dual_c; - wire ruo_tx_rdy; - wire rdo_tx_serdes_rst_c; - wire [3:0] rdo_tx_pcs_rst_c; - wire ruo_rx_rdy; - wire [3:0] rdo_rx_serdes_rst_c; - wire [3:0] rdo_rx_pcs_rst_c; - - // internal signals - // common - wire rsl_enable; - wire [lplol_cnt_width-1:0] wait_b4_trst; - wire [lrlol_cnt_width-1:0] wait_b4_rrst; - wire [llols_cnt_width-1:0] wait_after_lols; - reg pll_lol_p1; - reg pll_lol_p2; - reg pll_lol_p3; - // ------------ Tx - // rdo_tx_serdes_rst_c - reg [lplol_cnt_width-1:0] plol_cnt; - wire plol_cnt_tc; - - reg [2:0] txs_cnt; - reg txs_rst; - wire txs_cnt_tc; - // rdo_tx_pcs_rst_c - wire plol_fedge; - wire plol_redge; - reg waita_plol0; - reg [2:0] plol0_cnt; - wire plol0_cnt_tc; - reg [2:0] txp_cnt; - reg txp_rst; - wire txp_cnt_tc; - // ruo_tx_rdy - wire dual_or_serd_rst; - wire tx_any_pcs_rst; - wire tx_any_rst; - reg txsr_appd /* synthesis syn_keep=1 */; - reg txdpr_appd; - reg [pnum_channels-1:0] txpr_appd; - reg txr_wt_en; - reg [ltxr_wait_width-1:0] txr_wt_cnt; - wire txr_wt_tc; - reg ruo_tx_rdyr; - - // ------------ Rx - wire comb_rlos; - wire comb_rlol; - //wire rlols; - wire rx_all_well; - - //reg rlols_p1; - //reg rlols_p2; - //reg rlols_p3; - - reg rlol_p1; - reg rlol_p2; - reg rlol_p3; - reg rlos_p1; - reg rlos_p2; - reg rlos_p3; - - //reg [3:0] rdb_cnt; - //wire rdb_cnt_max; - //wire rdb_cnt_zero; - //reg rlols_db; - //reg rlols_db_p1; - - reg [3:0] rlol_db_cnt; - wire rlol_db_cnt_max; - wire rlol_db_cnt_zero; - reg rlol_db; - reg rlol_db_p1; - - reg [3:0] rlos_db_cnt; - wire rlos_db_cnt_max; - wire rlos_db_cnt_zero; - reg rlos_db; - reg rlos_db_p1; - - // rdo_rx_serdes_rst_c - reg [lrlol_cnt_width-1:0] rlol1_cnt; - wire rlol1_cnt_tc; - reg [2:0] rxs_cnt; - reg rxs_rst; - wire rxs_cnt_tc; - reg [lrrst_wait_width-1:0] rrst_cnt; - wire rrst_cnt_tc; - reg rrst_wait; - // rdo_rx_pcs_rst_c - //wire rlols_fedge; - //wire rlols_redge; - wire rlol_fedge; - wire rlol_redge; - wire rlos_fedge; - wire rlos_redge; - - reg wait_calib; - reg waita_rlols0; - reg [llols_cnt_width-1:0] rlols0_cnt; - wire rlols0_cnt_tc; - reg [2:0] rxp_cnt; - reg rxp_rst; - wire rxp_cnt_tc; - - wire rx_any_serd_rst; - reg [llols_cnt_width-1:0] rlolsz_cnt; - wire rlolsz_cnt_tc; - reg [2:0] rxp_cnt2; - reg rxp_rst2; - wire rxp_cnt2_tc; - reg [15:0] data_loop_b_cnt; - reg data_loop_b; - wire data_loop_b_tc; - - // ruo_rx_rdy - reg [pnum_channels-1:0] rxsr_appd; - reg [pnum_channels-1:0] rxpr_appd; - reg rxsdr_appd /* synthesis syn_keep=1 */; - reg rxdpr_appd; - wire rxsdr_or_sr_appd; - wire dual_or_rserd_rst; - wire rx_any_pcs_rst; - wire rx_any_rst; - reg rxr_wt_en; - reg [lrxr_wait_width-1:0] rxr_wt_cnt; - wire rxr_wt_tc; - reg ruo_rx_rdyr; - -// ================================================================== -// Start of code -// ================================================================== - assign rsl_enable = ~rui_rsl_disable; - -// ------------ rdo_serdes_rst_dual_c - assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; - -// ------------ rdo_rst_dual_c - assign rdo_rst_dual_c = rui_rst_dual_c; - -// ------------ Setting counter values for RSL_SIM_MODE - `ifdef RSL_SIM_MODE - assign wait_b4_trst = lwait_b4_trst_s; - assign wait_b4_rrst = lwait_b4_rrst_s; - assign wait_after_lols = lwait_after_lols_s; - `else - assign wait_b4_trst = lwait_b4_trst; - assign wait_b4_rrst = lwait_b4_rrst; - assign wait_after_lols = lwait_after_lols; - `endif - -// ================================================================== -// Tx -// ================================================================== - generate - if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin - -// ------------ Synchronizing pll_lol to the tx clock - always @(posedge rui_tx_ref_clk or posedge rui_rst) begin - if(rui_rst==1'b1) begin - pll_lol_p1 <= 1'd0; - pll_lol_p2 <= 1'd0; - pll_lol_p3 <= 1'd0; - end - else begin - pll_lol_p1 <= rdi_pll_lol; - pll_lol_p2 <= pll_lol_p1; - pll_lol_p3 <= pll_lol_p2; - end - end - -// ------------ rdo_tx_serdes_rst_c - always @(posedge rui_tx_ref_clk or posedge rui_rst) begin - if(rui_rst==1'b1) - plol_cnt <= 'd0; - else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) - plol_cnt <= 'd0; - else - plol_cnt <= plol_cnt+1; - end - assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; - - always @(posedge rui_tx_ref_clk or posedge rui_rst) begin - if(rui_rst==1'b1) begin - txs_cnt <= 'd0; // tx serdes reset pulse count - txs_rst <= 1'b0; // tx serdes reset - end - else if(plol_cnt_tc==1) - txs_rst <= 1'b1; - else if(txs_cnt_tc==1) begin - txs_cnt <= 'd0; - txs_rst <= 1'b0; - end - else if(txs_rst==1) - txs_cnt <= txs_cnt+1; - end - assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; - - assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; - -// ------------ rdo_tx_pcs_rst_c - assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; - assign plol_redge = pll_lol_p2 & ~pll_lol_p3; - always @(posedge rui_tx_ref_clk or posedge rui_rst) begin - if(rui_rst==1'b1) - waita_plol0 <= 1'd0; - else if(plol_fedge==1'b1) - waita_plol0 <= 1'b1; - else if((plol0_cnt_tc==1)||(plol_redge==1)) - waita_plol0 <= 1'd0; - end - always @(posedge rui_tx_ref_clk or posedge rui_rst) begin - if(rui_rst==1'b1) - plol0_cnt <= 'd0; - else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) - plol0_cnt <= 'd0; - else if(waita_plol0==1'b1) - plol0_cnt <= plol0_cnt+1; - end - assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; - - always @(posedge rui_tx_ref_clk or posedge rui_rst) begin - if(rui_rst==1'b1) begin - txp_cnt <= 'd0; // tx serdes reset pulse count - txp_rst <= 1'b0; // tx serdes reset - end - else if(plol0_cnt_tc==1) - txp_rst <= 1'b1; - else if(txp_cnt_tc==1) begin - txp_cnt <= 'd0; - txp_rst <= 1'b0; - end - else if(txp_rst==1) - txp_cnt <= txp_cnt+1; - end - assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; - - genvar i; - for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// --------------------------------------------------------------------------- -// Copyright (c) 2015 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code -// pursuant to the terms of the Lattice Reference Design License Agreement. -// -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// --------------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// --------------------------------------------------------------------------- -// -// ============================================================================= -// FILE DETAILS -// Project : SLL - Soft Loss Of Lock(LOL) Logic -// File : sll_core.v -// Title : Top-level file for SLL -// Dependencies : 1. -// : 2. -// Description : -// ============================================================================= -// REVISION HISTORY -// Version : 1.0 -// Author(s) : AV -// Mod. Date : March 2, 2015 -// Changes Made : Initial Creation -// ============================================================================= -// REVISION HISTORY -// Version : 1.1 -// Author(s) : AV -// Mod. Date : June 8, 2015 -// Changes Made : Following updates were made -// : 1. Changed all the PLOL status logic and FSM to run -// : on sli_refclk. -// : 2. Added the HB logic for presence of tx_pclk -// : 3. Changed the lparam assignment scheme for -// : simulation purposes. -// ============================================================================= -// REVISION HISTORY -// Version : 1.2 -// Author(s) : AV -// Mod. Date : June 24, 2015 -// Changes Made : Updated the gearing logic for SDI dynamic rate change -// ============================================================================= -// REVISION HISTORY -// Version : 1.3 -// Author(s) : AV -// Mod. Date : July 14, 2015 -// Changes Made : Added the logic for dynamic rate change in CPRI -// ============================================================================= -// REVISION HISTORY -// Version : 1.4 -// Author(s) : AV -// Mod. Date : August 21, 2015 -// Changes Made : Added the logic for dynamic rate change of 5G CPRI & -// PCIe. -// ============================================================================= -// REVISION HISTORY -// Version : 1.5 -// Author(s) : ES/EB -// Mod. Date : March 21, 2017 -// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff -// : to sli_refclk. -// : 2. Updated terminal count logic for PCIe 5G -// : 3. Modified checking of pcount_diff in SLL state -// : machine to cover actual count -// : (from 16-bits to 22-bits) -// ============================================================================= -// REVISION HISTORY -// Version : 1.6 -// Author(s) : ES -// Mod. Date : April 19, 2017 -// Changes Made : 1. Added registered lock and unlock signal from -// pdiff_sync to totally decouple pcount_diff from -// SLL state machine. -// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI -// is operating @ 4.9125Gbps data rate. -// ============================================================================= -`timescale 1ns/10ps - -module serdes_sync_0sll_core ( - //Reset and Clock inputs - sli_rst, //Active high asynchronous reset input - sli_refclk, //Refclk input to the Tx PLL - sli_pclk, //Tx pclk output from the PCS - - //Control inputs - sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate - sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 - sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 - sli_cpri_mode, //Mode of operation specific to CPRI protocol - sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) - - //LOL Output - slo_plol //Tx PLL Loss of Lock output to the user logic - ); - -// Inputs -input sli_rst; -input sli_refclk; -input sli_pclk; -input sli_div2_rate; -input sli_div11_rate; -input sli_gear_mode; -input [2:0] sli_cpri_mode; -input sli_pcie_mode; - -// Outputs -output slo_plol; - - -// Parameters -parameter PPROTOCOL = "PCIE"; //Protocol selected by the User -parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 -parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control -parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate -parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock -parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock -parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk -parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 -parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 -parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk - - -// Local Parameters -localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state -localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state -localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state -localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state -`ifdef RSL_SIM_MODE -localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk -`else -localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk -`endif -localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse -localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal - -// Local Parameters related to the CPRI dynamic modes -// Terminal count values for the four CPRI modes -localparam LPCLK_TC_0 = 32768; -localparam LPCLK_TC_1 = 65536; -localparam LPCLK_TC_2 = 131072; -localparam LPCLK_TC_3 = 163840; -localparam LPCLK_TC_4 = 65536; - -// Lock values count values for the four CPRI modes and four PLOL settings (4x5) -// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 -localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; -localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; -localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; -localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; - -// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) -// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 -localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; -localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; -localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; -localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; - -// Input and Output reg and wire declarations -wire sli_rst; -wire sli_refclk; -wire sli_pclk; -wire sli_div2_rate; -wire sli_div11_rate; -wire sli_gear_mode; -wire [2:0] sli_cpri_mode; -wire sli_pcie_mode; -wire slo_plol; - -//-------------- Internal signals reg and wire declarations -------------------- - -//Signals running on sli_refclk -reg [15:0] rcount; //16-bit Counter -reg rtc_pul; //Terminal count pulse -reg rtc_pul_p1; //Terminal count pulse pipeline -reg rtc_ctrl; //Terminal count pulse control - -reg [7:0] rhb_wait_cnt; //Heartbeat wait counter - -//Heatbeat synchronization and pipeline registers -wire rhb_sync; -reg rhb_sync_p2; -reg rhb_sync_p1; - -//Pipeling registers for dynamic control mode -wire rgear; -wire rdiv2; -wire rdiv11; -reg rgear_p1; -reg rdiv2_p1; -reg rdiv11_p1; - -reg rstat_pclk; //Pclk presence/absence status - -reg [21:0] rcount_tc; //Tx_pclk terminal count register -reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock -reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock - -wire rpcie_mode; //PCIe mode signal synchronized to refclk -reg rpcie_mode_p1; //PCIe mode pipeline register - -wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk -reg rcpri_mod_ch_p1; //CPRI mode change pipeline register -reg rcpri_mod_ch_p2; //CPRI mode change pipeline register -reg rcpri_mod_ch_st; //CPRI mode change status - -reg [1:0] sll_state; //Current-state register for LOL FSM - -reg pll_lock; //PLL Lock signal - -//Signals running on sli_pclk -//Synchronization and pipeline registers -wire ppul_sync; -reg ppul_sync_p1; -reg ppul_sync_p2; -reg ppul_sync_p3; - -wire pdiff_sync; -reg pdiff_sync_p1; - -reg [21:0] pcount; //22-bit counter -reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value - -//Heartbeat counter and heartbeat signal running on pclk -reg [2:0] phb_cnt; -reg phb; - -//CPRI dynamic mode releated signals -reg [2:0] pcpri_mode; -reg pcpri_mod_ch; - -//Assignment scheme changed mainly for simulation purpose -wire [15:0] LRCLK_TC_w; -assign LRCLK_TC_w = LRCLK_TC; - -reg unlock; -reg lock; - -//Heartbeat synchronization -sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( - .clk (sli_refclk), - .rst (sli_rst), - .data_in (phb), - .data_out(rhb_sync) - ); - - -//Terminal count pulse synchronization -sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( - .clk (sli_pclk), - .rst (sli_rst), - .data_in (rtc_pul), - .data_out(ppul_sync) - ); - -//Differential value logic update synchronization -sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( - .clk (sli_refclk), - .rst (sli_rst), - .data_in (ppul_sync), - .data_out(pdiff_sync) - ); - -//Gear mode synchronization -sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( - .clk (sli_refclk), - .rst (sli_rst), - .data_in (sli_gear_mode), - .data_out(rgear) - ); - -//Div2 synchronization -sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( - .clk (sli_refclk), - .rst (sli_rst), - .data_in (sli_div2_rate), - .data_out(rdiv2) - ); - -//Div11 synchronization -sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( - .clk (sli_refclk), - .rst (sli_rst), - .data_in (sli_div11_rate), - .data_out(rdiv11) - ); - -//CPRI mode change synchronization -sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( - .clk (sli_refclk), - .rst (sli_rst), - .data_in (pcpri_mod_ch), - .data_out(rcpri_mod_ch_sync) - ); - -//PCIe mode change synchronization -sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( - .clk (sli_refclk), - .rst (sli_rst), - .data_in (sli_pcie_mode), - .data_out(rpcie_mode) - ); - -// ============================================================================= -// Synchronized Lock/Unlock signals -// ============================================================================= -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - unlock <= 1'b0; - lock <= 1'b0; - pdiff_sync_p1 <= 1'b0; - end - else begin - pdiff_sync_p1 <= pdiff_sync; - if (unlock) begin - unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; - end - else begin - unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; - end - if (lock) begin - lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; - end - else begin - lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; - end - end -end - -// ============================================================================= -// Refclk Counter, pulse generation logic and Heartbeat monitor logic -// ============================================================================= -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - rcount <= 16'd0; - rtc_pul <= 1'b0; - rtc_ctrl <= 1'b0; - rtc_pul_p1 <= 1'b0; - end - else begin - //Counter logic - if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin - if (rtc_ctrl == 1'b1) begin - rcount <= LRCLK_TC_PUL_WIDTH; - end - end - else begin - if (rcount != LRCLK_TC_w) begin - rcount <= rcount + 1; - end - else begin - rcount <= 16'd0; - end - end - - //Pulse control logic - if (rcount == LRCLK_TC_w - 1) begin - rtc_ctrl <= 1'b1; - end - - //Pulse Generation logic - if (rtc_ctrl == 1'b1) begin - if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin - rtc_pul <= 1'b1; - end - else begin - rtc_pul <= 1'b0; - end - end - - rtc_pul_p1 <= rtc_pul; - end -end - - -// ============================================================================= -// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic -// ============================================================================= -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - rhb_sync_p1 <= 1'b0; - rhb_sync_p2 <= 1'b0; - rhb_wait_cnt <= 8'd0; - rstat_pclk <= 1'b0; - rgear_p1 <= 1'b0; - rdiv2_p1 <= 1'b0; - rdiv11_p1 <= 1'b0; - rcpri_mod_ch_p1 <= 1'b0; - rcpri_mod_ch_p2 <= 1'b0; - rcpri_mod_ch_st <= 1'b0; - rpcie_mode_p1 <= 1'b0; - - end - else begin - //Pipeline stages for the Heartbeat - rhb_sync_p1 <= rhb_sync; - rhb_sync_p2 <= rhb_sync_p1; - - //Pipeline stages of the Dynamic rate control signals - rgear_p1 <= rgear; - rdiv2_p1 <= rdiv2; - rdiv11_p1 <= rdiv11; - - //Pipeline stage for PCIe mode - rpcie_mode_p1 <= rpcie_mode; - - //Pipeline stage for CPRI mode change - rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; - rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; - - //CPRI mode change status logic - if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin - rcpri_mod_ch_st <= 1'b1; - end - - //Heartbeat wait counter and monitor logic - if (rtc_ctrl == 1'b1) begin - if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin - rhb_wait_cnt <= 8'd0; - rstat_pclk <= 1'b1; - end - else if (rhb_wait_cnt == LHB_WAIT_CNT) begin - rhb_wait_cnt <= 8'd0; - rstat_pclk <= 1'b0; - end - else begin - rhb_wait_cnt <= rhb_wait_cnt + 1; - end - end - end -end - - -// ============================================================================= -// Pipleline registers for the TC pulse and CPRI mode change logic -// ============================================================================= -always @(posedge sli_pclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - ppul_sync_p1 <= 1'b0; - ppul_sync_p2 <= 1'b0; - ppul_sync_p3 <= 1'b0; - pcpri_mode <= 3'b0; - pcpri_mod_ch <= 1'b0; - end - else begin - ppul_sync_p1 <= ppul_sync; - ppul_sync_p2 <= ppul_sync_p1; - ppul_sync_p3 <= ppul_sync_p2; - - //CPRI mode change logic - pcpri_mode <= sli_cpri_mode; - - if (pcpri_mode != sli_cpri_mode) begin - pcpri_mod_ch <= ~pcpri_mod_ch; - end - end -end - - -// ============================================================================= -// Terminal count logic -// ============================================================================= - -//For SDI protocol with Dynamic rate control enabled -generate -if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - rcount_tc <= 22'd0; - rdiff_comp_lock <= 16'd0; - rdiff_comp_unlock <= 16'd0; - end - else begin - //Terminal count logic - //Div by 11 is enabled - if (rdiv11 == 1'b1) begin - //Gear mode is 16/20 - if (rgear == 1'b1) begin - rcount_tc <= PPCLK_DIV11_TC; - rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; - end - else begin - rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; - rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; - rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; - end - end - //Div by 2 is enabled - else if (rdiv2 == 1'b1) begin - //Gear mode is 16/20 - if (rgear == 1'b1) begin - rcount_tc <= {1'b0,PPCLK_TC[21:1]}; - rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; - rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; - end - else begin - rcount_tc <= PPCLK_TC; - rdiff_comp_lock <= PDIFF_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; - end - end - //Both div by 11 and div by 2 are disabled - else begin - //Gear mode is 16/20 - if (rgear == 1'b1) begin - rcount_tc <= PPCLK_TC; - rdiff_comp_lock <= PDIFF_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; - end - else begin - rcount_tc <= {PPCLK_TC[20:0],1'b0}; - rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; - rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; - end - end - end -end -end -endgenerate - -//For G8B10B protocol with Dynamic rate control enabled -generate -if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - rcount_tc <= 22'd0; - rdiff_comp_lock <= 16'd0; - rdiff_comp_unlock <= 16'd0; - end - else begin - //Terminal count logic - //Div by 2 is enabled - if (rdiv2 == 1'b1) begin - rcount_tc <= {1'b0,PPCLK_TC[21:1]}; - rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; - rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; - end - else begin - rcount_tc <= PPCLK_TC; - rdiff_comp_lock <= PDIFF_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; - end - end -end -end -endgenerate - - -//For CPRI protocol with Dynamic rate control is disabled -generate -if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - rcount_tc <= 22'd0; - rdiff_comp_lock <= 16'd0; - rdiff_comp_unlock <= 16'd0; - end - else begin - //Terminal count logic for CPRI protocol - //Only if there is a change in the rate mode from the default - if (rcpri_mod_ch_st == 1'b1) begin - if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin - case(sli_cpri_mode) - 3'd0 : begin //For 0.6Gbps - rcount_tc <= LPCLK_TC_0; - case(PLOL_SETTING) - 'd0 : begin - rdiff_comp_lock <= LPDIFF_LOCK_00; - rdiff_comp_unlock <= LPDIFF_UNLOCK_00; - end - - 'd1 : begin - rdiff_comp_lock <= LPDIFF_LOCK_01; - rdiff_comp_unlock <= LPDIFF_UNLOCK_01; - end - - 'd2 : begin - rdiff_comp_lock <= LPDIFF_LOCK_02; - rdiff_comp_unlock <= LPDIFF_UNLOCK_02; - end - - 'd3 : begin - rdiff_comp_lock <= LPDIFF_LOCK_03; - rdiff_comp_unlock <= LPDIFF_UNLOCK_03; - end - - default : begin - rdiff_comp_lock <= LPDIFF_LOCK_00; - rdiff_comp_unlock <= LPDIFF_UNLOCK_00; - end - endcase - end - - 3'd1 : begin //For 1.2Gbps - rcount_tc <= LPCLK_TC_1; - case(PLOL_SETTING) - 'd0 : begin - rdiff_comp_lock <= LPDIFF_LOCK_10; - rdiff_comp_unlock <= LPDIFF_UNLOCK_10; - end - - 'd1 : begin - rdiff_comp_lock <= LPDIFF_LOCK_11; - rdiff_comp_unlock <= LPDIFF_UNLOCK_11; - end - - 'd2 : begin - rdiff_comp_lock <= LPDIFF_LOCK_12; - rdiff_comp_unlock <= LPDIFF_UNLOCK_12; - end - - 'd3 : begin - rdiff_comp_lock <= LPDIFF_LOCK_13; - rdiff_comp_unlock <= LPDIFF_UNLOCK_13; - end - - default : begin - rdiff_comp_lock <= LPDIFF_LOCK_10; - rdiff_comp_unlock <= LPDIFF_UNLOCK_10; - end - endcase - end - - 3'd2 : begin //For 2.4Gbps - rcount_tc <= LPCLK_TC_2; - case(PLOL_SETTING) - 'd0 : begin - rdiff_comp_lock <= LPDIFF_LOCK_20; - rdiff_comp_unlock <= LPDIFF_UNLOCK_20; - end - - 'd1 : begin - rdiff_comp_lock <= LPDIFF_LOCK_21; - rdiff_comp_unlock <= LPDIFF_UNLOCK_21; - end - - 'd2 : begin - rdiff_comp_lock <= LPDIFF_LOCK_22; - rdiff_comp_unlock <= LPDIFF_UNLOCK_22; - end - - 'd3 : begin - rdiff_comp_lock <= LPDIFF_LOCK_23; - rdiff_comp_unlock <= LPDIFF_UNLOCK_23; - end - - default : begin - rdiff_comp_lock <= LPDIFF_LOCK_20; - rdiff_comp_unlock <= LPDIFF_UNLOCK_20; - end - endcase - end - - 3'd3 : begin //For 3.07Gbps - rcount_tc <= LPCLK_TC_3; - case(PLOL_SETTING) - 'd0 : begin - rdiff_comp_lock <= LPDIFF_LOCK_30; - rdiff_comp_unlock <= LPDIFF_UNLOCK_30; - end - - 'd1 : begin - rdiff_comp_lock <= LPDIFF_LOCK_31; - rdiff_comp_unlock <= LPDIFF_UNLOCK_31; - end - - 'd2 : begin - rdiff_comp_lock <= LPDIFF_LOCK_32; - rdiff_comp_unlock <= LPDIFF_UNLOCK_32; - end - - 'd3 : begin - rdiff_comp_lock <= LPDIFF_LOCK_33; - rdiff_comp_unlock <= LPDIFF_UNLOCK_33; - end - endcase - end - - 3'd4 : begin //For 4.9125bps - rcount_tc <= LPCLK_TC_4; - case(PLOL_SETTING) - 'd0 : begin - rdiff_comp_lock <= LPDIFF_LOCK_40; - rdiff_comp_unlock <= LPDIFF_UNLOCK_40; - end - - 'd1 : begin - rdiff_comp_lock <= LPDIFF_LOCK_41; - rdiff_comp_unlock <= LPDIFF_UNLOCK_41; - end - - 'd2 : begin - rdiff_comp_lock <= LPDIFF_LOCK_42; - rdiff_comp_unlock <= LPDIFF_UNLOCK_42; - end - - 'd3 : begin - rdiff_comp_lock <= LPDIFF_LOCK_43; - rdiff_comp_unlock <= LPDIFF_UNLOCK_43; - end - - default : begin - rdiff_comp_lock <= LPDIFF_LOCK_40; - rdiff_comp_unlock <= LPDIFF_UNLOCK_40; - end - endcase - end - - default : begin - rcount_tc <= LPCLK_TC_0; - rdiff_comp_lock <= LPDIFF_LOCK_00; - rdiff_comp_unlock <= LPDIFF_UNLOCK_00; - end - endcase - end - end - else begin - //If there is no change in the CPRI rate mode from default - rcount_tc <= PPCLK_TC; - rdiff_comp_lock <= PDIFF_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; - end - end -end -end -endgenerate - -//For PCIe protocol with Dynamic rate control disabled -generate -if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - rcount_tc <= 22'd0; - rdiff_comp_lock <= 16'd0; - rdiff_comp_unlock <= 16'd0; - end - else begin - //Terminal count logic - if (PPCIE_MAX_RATE == "2.5") begin - //2.5G mode is enabled - rcount_tc <= PPCLK_TC; - rdiff_comp_lock <= PDIFF_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; - end - else begin - //5G mode is enabled - if (rpcie_mode == 1'b1) begin - rcount_tc <= PPCLK_TC; - rdiff_comp_lock <= PDIFF_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; - end - else begin - //2.5G mode is enabled - rcount_tc <= {1'b0,PPCLK_TC[21:1]}; - rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; - rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; - end - end - end -end -end -endgenerate - -//For all protocols other than CPRI & PCIe -generate -if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - rcount_tc <= 22'd0; - rdiff_comp_lock <= 16'd0; - rdiff_comp_unlock <= 16'd0; - end - else begin - //Terminal count logic for all protocols other than CPRI & PCIe - rcount_tc <= PPCLK_TC; - rdiff_comp_lock <= PDIFF_VAL_LOCK; - rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; - end -end -end -endgenerate - - -// ============================================================================= -// Tx_pclk counter, Heartbeat and Differential value logic -// ============================================================================= -always @(posedge sli_pclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - pcount <= 22'd0; - pcount_diff <= 22'd65535; - phb_cnt <= 3'd0; - phb <= 1'b0; - end - else begin - //Counter logic - if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin - pcount <= 22'd0; - end - else begin - pcount <= pcount + 1; - end - - //Heartbeat logic - phb_cnt <= phb_cnt + 1; - - if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin - phb <= 1'b1; - end - else begin - phb <= 1'b0; - end - - //Differential value logic - if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin - pcount_diff <= rcount_tc + ~(pcount) + 1; - end - else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin - if (pcount_diff[21] == 1'b1) begin - pcount_diff <= ~(pcount_diff) + 1; - end - end - end -end - - -// ============================================================================= -// State transition logic for SLL FSM -// ============================================================================= -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - sll_state <= LPLL_LOSS_ST; - end - else begin - //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI - if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || - (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin - sll_state <= LPLL_LOSS_ST; - end - else begin - case(sll_state) - LPLL_LOSS_ST : begin - if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin - if (unlock) begin - sll_state <= LPLL_LOSS_ST; - end - else if (lock) begin - if (PLOL_SETTING == 2'd0) begin - sll_state <= LPLL_PRELOCK_ST; - end - else begin - sll_state <= LPLL_LOCK_ST; - end - end - end - end - - LPLL_LOCK_ST : begin - if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin - if (lock) begin - sll_state <= LPLL_LOCK_ST; - end - else begin - if (PLOL_SETTING == 2'd0) begin - sll_state <= LPLL_LOSS_ST; - end - else begin - sll_state <= LPLL_PRELOSS_ST; - end - end - end - end - - LPLL_PRELOCK_ST : begin - if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin - if (lock) begin - sll_state <= LPLL_LOCK_ST; - end - else begin - sll_state <= LPLL_PRELOSS_ST; - end - end - end - - LPLL_PRELOSS_ST : begin - if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin - if (unlock) begin - sll_state <= LPLL_PRELOSS_ST; - end - else if (lock) begin - sll_state <= LPLL_LOCK_ST; - end - end - end - - default: begin - sll_state <= LPLL_LOSS_ST; - end - endcase - end - end -end - - -// ============================================================================= -// Logic for Tx PLL Lock -// ============================================================================= -always @(posedge sli_refclk or posedge sli_rst) begin - if (sli_rst == 1'b1) begin - pll_lock <= 1'b0; - end - else begin - case(sll_state) - LPLL_LOSS_ST : begin - pll_lock <= 1'b0; - end - - LPLL_LOCK_ST : begin - pll_lock <= 1'b1; - end - - LPLL_PRELOSS_ST : begin - pll_lock <= 1'b0; - end - - default: begin - pll_lock <= 1'b0; - end - endcase - end -end - -assign slo_plol = ~(pll_lock); - -endmodule - - -// =========================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -// --------------------------------------------------------------------------- -// Copyright (c) 2015 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code -// pursuant to the terms of the Lattice Reference Design License Agreement. -// -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// --------------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// --------------------------------------------------------------------------- -// -// ============================================================================= -// FILE DETAILS -// Project : Synchronizer Logic -// File : sync.v -// Title : Synchronizer module -// Description : -// ============================================================================= -// REVISION HISTORY -// Version : 1.0 -// Author(s) : AV -// Mod. Date : July 7, 2015 -// Changes Made : Initial Creation -// ----------------------------------------------------------------------------- -// Version : 1.1 -// Author(s) : EB -// Mod. Date : March 21, 2017 -// Changes Made : -// ============================================================================= - -`ifndef PCS_SYNC_MODULE -`define PCS_SYNC_MODULE -module sync ( - clk, - rst, - data_in, - data_out - ); - -input clk; //Clock in which the async data needs to be synchronized to -input rst; //Active high reset -input data_in; //Asynchronous data -output data_out; //Synchronized data - -parameter PDATA_RST_VAL = 0; //Reset value for the registers - -reg data_p1; -reg data_p2; - -// ============================================================================= -// Synchronization logic -// ============================================================================= -always @(posedge clk or posedge rst) begin - if (rst == 1'b1) begin - data_p1 <= PDATA_RST_VAL; - data_p2 <= PDATA_RST_VAL; - end - else begin - data_p1 <= data_in; - data_p2 <= data_p1; - end -end - -assign data_out = data_p2; - -endmodule -`endif - diff --git a/oldfiles/serdes_test/ecp2m_link_fifo.vhd b/oldfiles/serdes_test/ecp2m_link_fifo.vhd deleted file mode 100644 index 2e1120a..0000000 --- a/oldfiles/serdes_test/ecp2m_link_fifo.vhd +++ /dev/null @@ -1,1992 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) --- Module Version: 4.4 ---/opt/lattice/isplever7.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 18 -depth 512 -no_enable -pe 10 -pf 508 -e - --- Thu Mar 19 16:21:17 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity ecp2m_link_fifo is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end ecp2m_link_fifo; - -architecture Structure of ecp2m_link_fifo is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co4: std_logic; - signal wcount_9: std_logic; - signal co3: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co4_1: std_logic; - signal rcount_9: std_logic; - signal co3_1: std_logic; - signal cmp_ci: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_8: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal cmp_ci_1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_8: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal iae_setcount_0: std_logic; - signal iae_setcount_1: std_logic; - signal ae_set_ctr_ci: std_logic; - signal iae_setcount_2: std_logic; - signal iae_setcount_3: std_logic; - signal co0_4: std_logic; - signal iae_setcount_4: std_logic; - signal iae_setcount_5: std_logic; - signal co1_4: std_logic; - signal iae_setcount_6: std_logic; - signal iae_setcount_7: std_logic; - signal co2_4: std_logic; - signal iae_setcount_8: std_logic; - signal iae_setcount_9: std_logic; - signal co4_2: std_logic; - signal ae_setcount_9: std_logic; - signal co3_4: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal ae_setcount_0: std_logic; - signal ae_setcount_1: std_logic; - signal co0_5: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal ae_setcount_2: std_logic; - signal ae_setcount_3: std_logic; - signal co1_5: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal ae_setcount_4: std_logic; - signal ae_setcount_5: std_logic; - signal co2_5: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r7: std_logic; - signal ae_setcount_6: std_logic; - signal ae_setcount_7: std_logic; - signal co3_5: std_logic; - signal wcount_r8: std_logic; - signal ae_set_cmp_clr: std_logic; - signal ae_setcount_8: std_logic; - signal ae_set_cmp_set: std_logic; - signal ae_set_d: std_logic; - signal ae_set_d_c: std_logic; - signal scuba_vhi: std_logic; - signal iaf_setcount_0: std_logic; - signal iaf_setcount_1: std_logic; - signal af_set_ctr_ci: std_logic; - signal iaf_setcount_2: std_logic; - signal iaf_setcount_3: std_logic; - signal co0_6: std_logic; - signal iaf_setcount_4: std_logic; - signal iaf_setcount_5: std_logic; - signal co1_6: std_logic; - signal iaf_setcount_6: std_logic; - signal iaf_setcount_7: std_logic; - signal co2_6: std_logic; - signal iaf_setcount_8: std_logic; - signal iaf_setcount_9: std_logic; - signal co4_3: std_logic; - signal af_setcount_9: std_logic; - signal co3_6: std_logic; - signal wren_i: std_logic; - signal cmp_ci_3: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal af_setcount_0: std_logic; - signal af_setcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal af_setcount_2: std_logic; - signal af_setcount_3: std_logic; - signal co1_7: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal af_setcount_4: std_logic; - signal af_setcount_5: std_logic; - signal co2_7: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w7: std_logic; - signal af_setcount_6: std_logic; - signal af_setcount_7: std_logic; - signal co3_7: std_logic; - signal rcount_w8: std_logic; - signal af_set_cmp_clr: std_logic; - signal af_setcount_8: std_logic; - signal af_set_cmp_set: std_logic; - signal af_set: std_logic; - signal af_set_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component PDPW16KB - -- synopsys translate_off - generic (CSDECODE_R : in std_logic_vector(2 downto 0); - CSDECODE_W : in std_logic_vector(2 downto 0); - GSR : in String; RESETMODE : in String; - REGMODE : in String; DATA_WIDTH_R : in Integer; - DATA_WIDTH_W : in Integer); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - ADW0: in std_logic; ADW1: in std_logic; - ADW2: in std_logic; ADW3: in std_logic; - ADW4: in std_logic; ADW5: in std_logic; - ADW6: in std_logic; ADW7: in std_logic; - ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; - BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; - CLKW: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; CSW2: in std_logic; - ADR0: in std_logic; ADR1: in std_logic; - ADR2: in std_logic; ADR3: in std_logic; - ADR4: in std_logic; ADR5: in std_logic; - ADR6: in std_logic; ADR7: in std_logic; - ADR8: in std_logic; ADR9: in std_logic; - ADR10: in std_logic; ADR11: in std_logic; - ADR12: in std_logic; ADR13: in std_logic; - CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; - CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_R : string; - attribute CSDECODE_W : string; - attribute RESETMODE : string; - attribute REGMODE : string; - attribute DATA_WIDTH_R : string; - attribute DATA_WIDTH_W : string; - attribute GSR : string; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x0410"; - attribute initval of LUT4_6 : label is "0x1004"; - attribute initval of LUT4_5 : label is "0x0140"; - attribute initval of LUT4_4 : label is "0x4001"; - attribute initval of LUT4_3 : label is "0x13c8"; - attribute initval of LUT4_2 : label is "0x2004"; - attribute initval of LUT4_1 : label is "0x4c32"; - attribute initval of LUT4_0 : label is "0x8001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "ecp2m_link_fifo.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000"; - attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001"; - attribute GSR of pdp_ram_0_0_0 : label is "ENABLED"; - attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; - attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG"; - attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36"; - attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t20: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t19: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t18: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t17: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t16: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t15: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t14: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t13: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t12: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t11: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t10: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t9: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t2: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t1: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t0: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_gcount_r29, - DO0=>w_g2b_xor_cluster_0); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_gcount_r25, - DO0=>w_g2b_xor_cluster_1); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_gcount_w29, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>r_gcount_w25, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x13c8") - -- synopsys translate_on - port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>rptr_9, DO0=>ae_set_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x2004") - -- synopsys translate_on - port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29, - AD0=>rptr_9, DO0=>ae_set_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4c32") - -- synopsys translate_on - port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>wptr_9, DO0=>af_set_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8001") - -- synopsys translate_on - port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, - AD0=>wptr_9, DO0=>af_set_cmp_clr); - - pdp_ram_0_0_0: PDPW16KB - -- synopsys translate_off - generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "ENABLED", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, - DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, - DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, - DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, - DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, - DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, - DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, - ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, - ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, - BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, - CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, - ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, - ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, - ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, - ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, - CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, - RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, - DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, - DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, - DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), - DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), - DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), - DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), - DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); - - FF_123: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_93: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_23: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_21: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>ae_setcount_0); - - FF_20: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_1, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>ae_setcount_1); - - FF_19: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_2); - - FF_18: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_3, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>ae_setcount_3); - - FF_17: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_4); - - FF_16: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_5); - - FF_15: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_6); - - FF_14: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_7); - - FF_13: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_8); - - FF_12: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_9); - - FF_11: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ae_set_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_10: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_0); - - FF_9: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_1); - - FF_8: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_2); - - FF_7: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_3); - - FF_6: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_4); - - FF_5: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_5); - - FF_4: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_6); - - FF_3: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_7); - - FF_2: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_8); - - FF_1: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_9); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, - B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, - B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_set_ctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>ae_set_ctr_ci, S0=>open, - S1=>open); - - ae_set_ctr_0: CU2 - port map (CI=>ae_set_ctr_ci, PC0=>ae_setcount_0, - PC1=>ae_setcount_1, CO=>co0_4, NC0=>iae_setcount_0, - NC1=>iae_setcount_1); - - ae_set_ctr_1: CU2 - port map (CI=>co0_4, PC0=>ae_setcount_2, PC1=>ae_setcount_3, - CO=>co1_4, NC0=>iae_setcount_2, NC1=>iae_setcount_3); - - ae_set_ctr_2: CU2 - port map (CI=>co1_4, PC0=>ae_setcount_4, PC1=>ae_setcount_5, - CO=>co2_4, NC0=>iae_setcount_4, NC1=>iae_setcount_5); - - ae_set_ctr_3: CU2 - port map (CI=>co2_4, PC0=>ae_setcount_6, PC1=>ae_setcount_7, - CO=>co3_4, NC0=>iae_setcount_6, NC1=>iae_setcount_7); - - ae_set_ctr_4: CU2 - port map (CI=>co3_4, PC0=>ae_setcount_8, PC1=>ae_setcount_9, - CO=>co4_2, NC0=>iae_setcount_8, NC1=>iae_setcount_9); - - ae_set_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_set_cmp_0: AGEB2 - port map (A0=>ae_setcount_0, A1=>ae_setcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci_2, GE=>co0_5); - - ae_set_cmp_1: AGEB2 - port map (A0=>ae_setcount_2, A1=>ae_setcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_5, GE=>co1_5); - - ae_set_cmp_2: AGEB2 - port map (A0=>ae_setcount_4, A1=>ae_setcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_5, GE=>co2_5); - - ae_set_cmp_3: AGEB2 - port map (A0=>ae_setcount_6, A1=>ae_setcount_7, - B0=>w_g2b_xor_cluster_0, B1=>wcount_r7, CI=>co2_5, GE=>co3_5); - - ae_set_cmp_4: AGEB2 - port map (A0=>ae_setcount_8, A1=>ae_set_cmp_set, B0=>wcount_r8, - B1=>ae_set_cmp_clr, CI=>co3_5, GE=>ae_set_d_c); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, - S1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - af_set_ctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, - S1=>open); - - af_set_ctr_0: CU2 - port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, - PC1=>af_setcount_1, CO=>co0_6, NC0=>iaf_setcount_0, - NC1=>iaf_setcount_1); - - af_set_ctr_1: CU2 - port map (CI=>co0_6, PC0=>af_setcount_2, PC1=>af_setcount_3, - CO=>co1_6, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); - - af_set_ctr_2: CU2 - port map (CI=>co1_6, PC0=>af_setcount_4, PC1=>af_setcount_5, - CO=>co2_6, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); - - af_set_ctr_3: CU2 - port map (CI=>co2_6, PC0=>af_setcount_6, PC1=>af_setcount_7, - CO=>co3_6, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); - - af_set_ctr_4: CU2 - port map (CI=>co3_6, PC0=>af_setcount_8, PC1=>af_setcount_9, - CO=>co4_3, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9); - - af_set_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - af_set_cmp_0: AGEB2 - port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7); - - af_set_cmp_1: AGEB2 - port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_7, GE=>co1_7); - - af_set_cmp_2: AGEB2 - port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_7, GE=>co2_7); - - af_set_cmp_3: AGEB2 - port map (A0=>af_setcount_6, A1=>af_setcount_7, - B0=>r_g2b_xor_cluster_0, B1=>rcount_w7, CI=>co2_7, GE=>co3_7); - - af_set_cmp_4: AGEB2 - port map (A0=>af_setcount_8, A1=>af_set_cmp_set, B0=>rcount_w8, - B1=>af_set_cmp_clr, CI=>co3_7, GE=>af_set_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of ecp2m_link_fifo is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/oldfiles/serdes_test/etrax_interfacev2.vhd b/oldfiles/serdes_test/etrax_interfacev2.vhd deleted file mode 100644 index b1887f3..0000000 --- a/oldfiles/serdes_test/etrax_interfacev2.vhd +++ /dev/null @@ -1,490 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.all; ---library UNISIM; ---use UNISIM.VCOMPONENTS.all; - -entity etrax_interfacev2 is - generic ( - RW_SYSTEM : integer range 1 to 2:=1 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_BUS : in std_logic_vector(31 downto 0); - ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0); - ETRAX_DATA_BUS_B_17 : in std_logic;--_vector(16 downto 0); - ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0); - ETRAX_DATA_BUS_E : inout std_logic_vector(9 downto 8); - DATA_VALID : in std_logic; - ETRAX_BUS_BUSY : in std_logic; - ETRAX_IS_READY_TO_READ : out std_logic; - TDC_TCK : out std_logic; - TDC_TDI : out std_logic; - TDC_TMS : out std_logic; - TDC_TRST : out std_logic; - TDC_TDO : in std_logic; - TDC_RESET : out std_logic; - EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); - EXTERNAL_ACK : out std_logic; - EXTERNAL_VALID : in std_logic; - EXTERNAL_MODE : out std_logic_vector(15 downto 0); - FPGA_REGISTER_00 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0E : out std_logic_vector(31 downto 0); - LVL2_VALID : in std_logic - -- DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0) - ); -end etrax_interfacev2; - -architecture etrax_interfacev2 of etrax_interfacev2 is - - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - - signal etrax_trigger_pulse : std_logic; - signal rw_operation_finished_pulse : std_logic; - signal saved_rw_mode : std_logic_vector(15 downto 0); - signal saved_address : std_logic_vector (31 downto 0); - signal saved_data : std_logic_vector(31 downto 0); - signal saved_data_fpga : std_logic_vector(31 downto 0); - - signal fpga_register_00_i : std_logic_vector(31 downto 0); - signal fpga_register_01_i : std_logic_vector(31 downto 0); - signal fpga_register_02_i : std_logic_vector(31 downto 0); - signal fpga_register_03_i : std_logic_vector(31 downto 0); - signal fpga_register_04_i : std_logic_vector(31 downto 0); - signal fpga_register_05_i : std_logic_vector(31 downto 0); - signal fpga_register_06_i : std_logic_vector(31 downto 0); - signal fpga_register_07_i : std_logic_vector(31 downto 0); - signal fpga_register_08_i : std_logic_vector(31 downto 0); - signal fpga_register_09_i : std_logic_vector(31 downto 0); - signal fpga_register_0A_i : std_logic_vector(31 downto 0); - signal fpga_register_0B_i : std_logic_vector(31 downto 0); - signal fpga_register_0C_i : std_logic_vector(31 downto 0); - signal fpga_register_0D_i : std_logic_vector(31 downto 0); - signal fpga_register_0E_i : std_logic_vector(31 downto 0); - signal saved_external_data : std_logic_vector(31 downto 0); - signal etrax_is_ready_to_read_i : std_logic; - signal lvl2_not_valid_pulse : std_logic; - signal counter_for_pulses : std_logic_vector(2 downto 0); - signal internal_reset_i : std_logic := '0'; - - signal data_from_etrax : std_logic_vector(80 downto 0); - signal etrax_std_data_counter : std_logic_vector(7 downto 0):=x"00"; - signal enable_transmition : std_logic :='1'; - signal etrax_strobe : std_logic; - signal data_to_etrax : std_logic_vector(31 downto 0); - signal reset_counter : std_logic_vector(15 downto 0) := x"0000"; - signal external_reset_counter : std_logic_vector(31 downto 0); - signal en_trigg_to_etrax : std_logic; - signal busy_dma_counter : std_logic_vector(3 downto 0); - signal busy_dma : std_logic; - signal etrax_busy_end_pulse : std_logic; - signal not_etrax_busy : std_logic; - signal data_valid_synch : std_logic; - signal send_data : std_logic; - signal data_bus_reg : std_logic_vector(31 downto 0); - constant INTERFACE_FOR_TRANSFER : integer := 2; --1 DMA, 2 no DMA - signal readout_lvl2_fifo_to_long :std_logic; - signal readout_lvl2_fifo_to_long_synch :std_logic; - signal readout_lvl2_fifo :std_logic; - signal etrax_busy_start : std_logic; - signal data_valid_start_pulse : std_logic; - signal data_valid_end_pulse : std_logic; - signal data_valid_not : std_logic; - signal etrax_busy_end : std_logic; - signal write_to_dma : std_logic; - signal write_to_dma_synch : std_logic; - signal word16_counter : std_logic_vector(7 downto 0); - signal write_to_dma_synch_synch : std_logic; -begin - - -------------------------------------------------------------------------------- --- transmition for reading, writing fpga registers, dsp, sdram , addon . . . -------------------------------------------------------------------------------- - - TRB_SYSTEM : if RW_SYSTEM = 1 generate - ETRAX_DATA_BUS_C(17) <= 'Z'; - STROBE_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ETRAX_DATA_BUS_C(17), - pulse => etrax_strobe); - - SAVE_ETRAX_DATA : process (CLK, RESET) - variable etrax_data_counter : integer := 0; - begin - if rising_edge(CLK)then - if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then - etrax_data_counter := 0; - data_from_etrax <= (others => '0'); - ETRAX_DATA_BUS_C(16) <= 'Z'; - enable_transmition <= '1'; - etrax_std_data_counter <= x"00"; - elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then -- and etrax_data_counter < 81 and etrax_data_counter > 0 then - data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_C(16); - etrax_data_counter := etrax_data_counter + 1; - ETRAX_DATA_BUS_C(16) <= 'Z'; - enable_transmition <= '0'; - etrax_std_data_counter <= etrax_std_data_counter + 1; - elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then - data_from_etrax <= data_from_etrax; - ETRAX_DATA_BUS_C(16) <= data_to_etrax(0); - etrax_data_counter := etrax_data_counter + 1; - etrax_std_data_counter <= etrax_std_data_counter + 1; - enable_transmition <= '0'; - elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then - data_from_etrax <= data_from_etrax; - ETRAX_DATA_BUS_C(16) <= data_to_etrax((etrax_data_counter-81) mod 32); - etrax_data_counter := etrax_data_counter + 1; - etrax_std_data_counter <= etrax_std_data_counter + 1; - enable_transmition <= '0'; - end if; - end if; - end process SAVE_ETRAX_DATA; - end generate TRB_SYSTEM; - -- we should add one state to wait for the data from external device (valid - -- pulse- > one long puls on the data bus !) - ADDON_SYSTEM : if RW_SYSTEM = 2 generate - ETRAX_DATA_BUS_E(8) <= 'Z'; - STROBE_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ETRAX_DATA_BUS_E(9),-- - pulse => etrax_strobe); - - SAVE_ETRAX_DATA : process (CLK, RESET) - variable etrax_data_counter : integer := 0; - begin - if rising_edge(CLK)then - if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then - etrax_data_counter := 0; - data_from_etrax <= (others => '0'); - ETRAX_DATA_BUS_E(8) <= 'Z'; - enable_transmition <= '1'; - etrax_std_data_counter <= x"00"; - elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then -- and etrax_data_counter < 81 and etrax_data_counter > 0 then - data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_E(8); - etrax_data_counter := etrax_data_counter + 1; - ETRAX_DATA_BUS_E(8) <= 'Z'; - enable_transmition <= '0'; - etrax_std_data_counter <= etrax_std_data_counter + 1; - elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then - data_from_etrax <= data_from_etrax; - ETRAX_DATA_BUS_E(8) <= data_to_etrax(0); - etrax_data_counter := etrax_data_counter + 1; - etrax_std_data_counter <= etrax_std_data_counter + 1; - enable_transmition <= '0'; - elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then - data_from_etrax <= data_from_etrax; - ETRAX_DATA_BUS_E(8) <= data_to_etrax( (etrax_data_counter-81) mod 32); - etrax_data_counter := etrax_data_counter + 1; - etrax_std_data_counter <= etrax_std_data_counter + 1; - enable_transmition <= '0'; - end if; - end if; - end process SAVE_ETRAX_DATA; - end generate ADDON_SYSTEM; - - data_to_etrax <= saved_data_fpga when saved_rw_mode(7 downto 0) = x"00" else saved_external_data; - RW_FINISHED_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => EXTERNAL_VALID, - pulse => rw_operation_finished_pulse); - --for reading only 1us for responce for any external device !!! - ask RADEK - --abut timing - REGISTER_ETRAX_BUS: process (CLK, RESET) - begin - if rising_edge(CLK) then - if rw_operation_finished_pulse = '1' then - saved_external_data <= EXTERNAL_DATA_IN; - else - saved_external_data <= saved_external_data; - end if; - end if; - end process REGISTER_ETRAX_BUS; - EXTERNAL_ADDRESS <= saved_address; - EXTERNAL_MODE <= saved_rw_mode(15 downto 0); - EXTERNAL_DATA_OUT <= saved_data; - EXTERNAL_ACK <= '1' when etrax_std_data_counter = 80 else '0'; - - CLOCK_SAVED_DATA: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_rw_mode <= (others => '0'); - saved_address <= (others => '0'); - saved_data <= (others => '0'); - else - saved_rw_mode <= data_from_etrax(15 downto 0); - saved_address <= data_from_etrax(47 downto 16); - saved_data <= data_from_etrax(79 downto 48); - end if; - end if; - end process CLOCK_SAVED_DATA; - - REGISTERS: process (CLK) - begin - if rising_edge(CLK) then --- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then - fpga_register_01_i <= FPGA_REGISTER_01; - fpga_register_02_i <= FPGA_REGISTER_02; - fpga_register_03_i <= FPGA_REGISTER_03; - fpga_register_04_i <= FPGA_REGISTER_04; - fpga_register_05_i <= FPGA_REGISTER_05; - FPGA_REGISTER_06 <= fpga_register_06_i; --this used for TDCjtag enable(0) - FPGA_REGISTER_07 <= fpga_register_07_i; - fpga_register_08_i <= FPGA_REGISTER_08; - fpga_register_09_i <= FPGA_REGISTER_09; - fpga_register_0A_i <= FPGA_REGISTER_0A; - fpga_register_0B_i <= FPGA_REGISTER_0B; - fpga_register_0c_i <= FPGA_REGISTER_0C; - fpga_register_0d_i <= FPGA_REGISTER_0D; - FPGA_REGISTER_0E <= fpga_register_0e_i; - end if; - end process REGISTERS; - - DATA_SOURCE_SELECT : process (CLK,RESET,saved_rw_mode,saved_address) - begin - if rising_edge(CLK) then - if RESET = '1' then--(ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then - fpga_register_06_i <= x"00000000"; - fpga_register_07_i <= x"00000000"; - fpga_register_0e_i <= x"00000000"; - else - case saved_rw_mode(7 downto 0) is - when "00000000" => - if saved_rw_mode(15) = '1' then - case saved_address(31 downto 0) is - when x"00000000" => saved_data_fpga <= fpga_register_00_i; - when x"00000001" => saved_data_fpga <= fpga_register_01_i; - when x"00000002" => saved_data_fpga <= fpga_register_02_i; - when x"00000003" => saved_data_fpga <= fpga_register_03_i; - when x"00000004" => saved_data_fpga <= fpga_register_04_i; - when x"00000005" => saved_data_fpga <= fpga_register_05_i; - when x"00000006" => saved_data_fpga <= fpga_register_06_i; - when x"00000007" => saved_data_fpga <= fpga_register_07_i; - when x"00000008" => saved_data_fpga <= fpga_register_08_i; - when x"00000009" => saved_data_fpga <= fpga_register_09_i; - when x"0000000A" => saved_data_fpga <= fpga_register_0A_i; - when x"0000000B" => saved_data_fpga <= fpga_register_0B_i; - when x"0000000C" => saved_data_fpga <= fpga_register_0C_i; - when x"0000000D" => saved_data_fpga <= fpga_register_0D_i; - when x"0000000E" => saved_data_fpga <= fpga_register_0E_i; - when others => saved_data_fpga <= x"deadface"; - end case; - elsif saved_rw_mode(15) = '0' and etrax_std_data_counter = 80 then - case saved_address(31 downto 0) is - when x"00000006" => fpga_register_06_i <= saved_data; - when x"00000007" => fpga_register_07_i <= saved_data; - when x"0000000e" => fpga_register_0e_i <= saved_data; - when others => null; - end case; - end if; - when "00000001" => --DSP write read - saved_data_fpga <= saved_external_data; - when x"02" => --sdram - saved_data_fpga <= saved_external_data; - when x"03" => --ADDON board write read - saved_data_fpga <= saved_external_data; - when others => - saved_data_fpga <= x"deadface"; - end case; - end if; - end if; - end process DATA_SOURCE_SELECT; - -------------------------------------------------------------------------------- --- data transmitio fpga -> etrax -------------------------------------------------------------------------------- ---DMA - DMA_INTERFACE: if INTERFACE_FOR_TRANSFER=1 generate - - REG_DATA_TO_ETRAXa:process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - data_bus_reg <= (others => '0'); - write_to_dma_synch <= '0'; - write_to_dma_synch_synch <= '0'; - else - data_bus_reg <= DATA_BUS; - write_to_dma_synch <= readout_lvl2_fifo;--write_to_dma; - write_to_dma_synch_synch <= write_to_dma_synch; - end if; - end if; - end process REG_DATA_TO_ETRAXa; - ETRAX_DATA_BUS_B(7 downto 0) <= data_bus_reg(31 downto 24); --- ETRAX_DATA_BUS_B(6 downto 0) <= data_bus_reg(30 downto 24); --!!!test - ETRAX_DATA_BUS_B(15 downto 8) <= data_bus_reg(23 downto 16); - ETRAX_DATA_BUS_C(15 downto 8) <= data_bus_reg(15 downto 8); - ETRAX_DATA_BUS_C(7 downto 4) <= data_bus_reg(7 downto 4); - - --- ETRAX_DATA_BUS_B(7) <= ETRAX_DATA_BUS_B_17; --for test - - TDC_TMS <= ETRAX_DATA_BUS_C(1) when fpga_register_06_i(0) = '1' else '1'; - TDC_TCK <= ETRAX_DATA_BUS_C(2) when fpga_register_06_i(0) = '1' else '1'; - TDC_TDI <= ETRAX_DATA_BUS_C(3) when fpga_register_06_i(0) = '1' else '1'; - ETRAX_DATA_BUS_C(0) <= TDC_TDO when fpga_register_06_i(0) = '1' else data_bus_reg(0); - ETRAX_DATA_BUS_C(1) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(1); - ETRAX_DATA_BUS_C(2) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(2); - ETRAX_DATA_BUS_C(3) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(3); - - START_READOUT : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => DATA_VALID, - pulse => data_valid_start_pulse); - data_valid_not <= not DATA_VALID; - - END_READOUT : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => data_valid_not, - pulse => data_valid_end_pulse); - - ETRAX_BUSY_START_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ETRAX_DATA_BUS_B_17, - pulse => etrax_busy_start); - - not_etrax_busy <= not ETRAX_DATA_BUS_B_17; - - ETRAX_BUSY_END_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => not_etrax_busy, - pulse => etrax_busy_end); - - COUNTER_FOR_READOUT: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - word16_counter <= x"FF"; - elsif (data_valid_start_pulse = '1') or (etrax_busy_end = '1' and DATA_VALID = '1') then - word16_counter <= x"00"; - elsif word16_counter < x"1e" then - word16_counter <= word16_counter + 1; - else - word16_counter <= word16_counter; - end if; - end if; - end process COUNTER_FOR_READOUT; - - READOUT_LVL2_FIFO_PROC: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' or data_valid_end_pulse = '1' or word16_counter = x"1e" then - readout_lvl2_fifo <= '0'; - elsif word16_counter < x"1e" then - readout_lvl2_fifo <= word16_counter(0); - end if; - end if; - end process READOUT_LVL2_FIFO_PROC; - - WRITE_TO_ETRAX_DMA: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' or word16_counter = x"1e" then - write_to_dma <= '0'; - elsif word16_counter = x"00" then - write_to_dma <= '1'; - end if; - end if; - end process WRITE_TO_ETRAX_DMA; - - etrax_is_ready_to_read_i <= (data_valid_start_pulse or readout_lvl2_fifo) and DATA_VALID; - ETRAX_IS_READY_TO_READ <= readout_lvl2_fifo; - ETRAX_DATA_BUS_B(16) <= write_to_dma_synch_synch;--(not CLK) and (write_to_dma_synch_synch); - - end generate DMA_INTERFACE; - - --- NO DMA - WITHOUT_DMA_ETRAX_INTERFACE: if INTERFACE_FOR_TRANSFER = 2 generate - - ETRAX_READY_PULSE : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ETRAX_DATA_BUS_B_17, - pulse => etrax_is_ready_to_read_i); - - MAKE_PULSES: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - counter_for_pulses <= "000"; - else - counter_for_pulses <= counter_for_pulses + 1; - end if; - end if; - end process make_pulses; - - LVL2_NOT_VALID_READY_PULSE : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => counter_for_pulses(2), - pulse => lvl2_not_valid_pulse); - - ETRAX_IS_READY_TO_READ <= DATA_VALID and ((etrax_is_ready_to_read_i and (not LVL2_VALID)) or (lvl2_not_valid_pulse and LVL2_VALID)); - - TDC_TMS <= ETRAX_DATA_BUS_C(1) when fpga_register_06_i(0) = '1' else '1'; - TDC_TCK <= ETRAX_DATA_BUS_C(2) when fpga_register_06_i(0) = '1' else '1'; - TDC_TDI <= ETRAX_DATA_BUS_C(3) when fpga_register_06_i(0) = '1' else '1'; - ETRAX_DATA_BUS_C(0) <= TDC_TDO when fpga_register_06_i(0) = '1' else DATA_BUS(16); - ETRAX_DATA_BUS_C(1) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(17); - ETRAX_DATA_BUS_C(2) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(18); - ETRAX_DATA_BUS_C(3) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(19); - ETRAX_DATA_BUS_C(15 downto 4) <= DATA_BUS(31 downto 20); - ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0); - ETRAX_DATA_BUS_B(16) <= DATA_VALID and (not LVL2_VALID); - - - REG_DATA_TO_ETRAX: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - data_bus_reg <= (others => '0'); - else - data_bus_reg <= DATA_BUS; - end if; - end if; - end process REG_DATA_TO_ETRAX; -end generate WITHOUT_DMA_ETRAX_INTERFACE; - -end etrax_interfacev2; diff --git a/oldfiles/serdes_test/f_divider.vhd b/oldfiles/serdes_test/f_divider.vhd deleted file mode 100644 index 8ed1794..0000000 --- a/oldfiles/serdes_test/f_divider.vhd +++ /dev/null @@ -1,174 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_arith.all; -use IEEE.STD_LOGIC_unsigned.all; - - -entity f_divider is - - generic( - cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. -- - ); - - port ( - clk : in std_logic; - ena_cnt : in std_logic; - f_div : out std_logic - ); - -end f_divider; - - - -architecture arch_f_divider of f_divider is - - function How_many_Bits (int : integer) return integer is - variable i, tmp : integer; - begin - tmp := int; - i := 0; - while tmp > 0 loop - tmp := tmp / 2; - i := i + 1; - end loop; - return i; - end How_many_bits; - - - --+ - --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? | - --+ - constant c_counter_width : integer := How_many_Bits(cnt - 2); - - --+ ---------------------------------------------------------------------------------------------+ - --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" | - --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne | - --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. | - --+ ---------------------------------------------------------------------------------------------+ - signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1); - - --+ ---------------------------------------------------------------------------------------------+ - --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem | - --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. | - --+ ---------------------------------------------------------------------------------------------+ - constant c_ld_value : integer := cnt - 2; - -begin - p_f_divider : process (clk) - begin - if clk'event and clk = '1' then - if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen -- - s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length); - elsif ena_cnt = '1' then - if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter -- - s_counter <= s_counter - 1; -- subtrahieren. -- - end if; - end if; - end if; - end process p_f_divider; - - f_div <= s_counter(s_counter'high); - -end arch_f_divider; - - - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - - ---library synplify; ---use synplify.attributes.all; - - -entity edge_to_pulse is - - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - -end edge_to_pulse; - -architecture arch_edge_to_pulse of edge_to_pulse is - signal signal_sync : std_logic; - signal old_sync : std_logic; - type state is (idle, high, wait_for_low); -- state - signal current_state, next_state : state; - -begin -- arch_edge_to_pulse - - fsm : process (clock) - begin -- process fsm - if rising_edge(clock) then -- rising clock edge - if en_clk = '1' then - current_state <= next_state; - signal_sync <= signal_in; - end if; - end if; - end process fsm; - - - fsm_comb : process (current_state, signal_sync) - begin -- process fsm_comb - case current_state is - when idle => - pulse <= '0'; - if signal_sync = '1' then - next_state <= high; - else - next_state <= idle; - end if; - when high => - pulse <= '1'; - next_state <= wait_for_low; --- when wait_for_low_1 => --- pulse <= '1'; --- next_state <= wait_for_low; - when wait_for_low => - pulse <= '0'; - if signal_sync = '0' then - next_state <= idle; - else - next_state <= wait_for_low; - end if; - when others => - pulse <= '0'; - next_state <= idle; - end case; - end process fsm_comb; - - -end arch_edge_to_pulse; - - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package support is - - component f_divider - generic ( - cnt : integer); - port ( - clk : in std_logic; - ena_cnt : in std_logic; - f_div : out std_logic); - end component; - - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - - -end support; - diff --git a/oldfiles/serdes_test/flexi_PCS_channel_synch.vhd b/oldfiles/serdes_test/flexi_PCS_channel_synch.vhd deleted file mode 100644 index e261606..0000000 --- a/oldfiles/serdes_test/flexi_PCS_channel_synch.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---library UNISIM; ---use UNISIM.VCOMPONENTS.all; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; -use work.trb_net_std.all; -use work.trb_net16_hub_func.all; - -entity flexi_PCS_channel_synch is - - port ( - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic; - RX_CLK : in std_logic; - RESET : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RXD_SYNCH : out std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : in std_logic_vector(15 downto 0); - TXD_SYNCH : out std_logic_vector(15 downto 0); - TX_K : out std_logic_vector(1 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(2 downto 0); - MED_READ_IN : in std_logic - ); - -end flexi_PCS_channel_synch; -architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is - component flexi_PCS_fifo_EBR - port ( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(17 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic); - end component; - - component ecp2m_link_fifo - port ( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(17 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic); - end component; - - component simpleupcounter_32bit - port ( - QOUT : out std_logic_vector(31 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_16bit - port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_8bit - port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component edge_to_pulse - port ( - CLOCK : in std_logic; - EN_CLK : in std_logic; - SIGNAL_IN : in std_logic; - PULSE : out std_logic); - end component; - type SYNCH_MACHINE is (IDLE, SYNCH_START, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, NORMAL_OPERATION_1, NORMAL_OPERATION_2); - signal SYNCH_CURRENT, SYNCH_NEXT : SYNCH_MACHINE; - signal fsm_debug_register : std_logic_vector(2 downto 0); - signal resync_counter_up :std_logic; - signal resync_counter_clr :std_logic; - signal resync_counter : std_logic_vector(31 downto 0); - signal cv_i : std_logic_vector(1 downto 0); - signal cv_or : std_logic; - signal cv_counter : std_logic_vector(15 downto 0); - signal rx_rst_i : std_logic; - signal rxd_synch_i : std_logic_vector(15 downto 0); - signal rxd_synch_synch_i : std_logic_vector(15 downto 0); - signal rx_k_synch_i : std_logic_vector(1 downto 0); - signal rx_k_synch_synch_i : std_logic_vector(1 downto 0); - signal fifo_data_in : std_logic_vector(17 downto 0); - signal fifo_data_out : std_logic_vector(17 downto 0); - signal fifo_wr_en : std_logic; - signal fifo_rd_en : std_logic; - signal fifo_rst : std_logic; - signal fifo_full : std_logic; - signal fifo_almost_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal start_counter_1 : std_logic_vector(31 downto 0); - signal start_counter_2 : std_logic_vector(31 downto 0); - signal fifo_rd_pulse : std_logic; - signal fifo_rd_cnt : std_logic_vector(15 downto 0); - signal fifo_wr_cnt : std_logic_vector(15 downto 0); - signal not_fifo_empty : std_logic; - signal fifo_rd_en_dv : std_logic; - ----------------------------------------------------------------------------- - -- fifo to optical link - ----------------------------------------------------------------------------- - signal data_valid_out_i : std_logic; - signal fifo_opt_not_empty : std_logic; - signal fifo_opt_empty : std_logic; - signal fifo_opt_empty_synch : std_logic; - signal data_opt_in : std_logic_vector(17 downto 0); - signal txd_fifo_out : std_logic_vector(17 downto 0); - signal fifo_opt_full : std_logic; - signal fifo_opt_almost_empty : std_logic; - signal fifo_opt_almost_full : std_logic; - signal not_clk : std_logic; - signal txd_synch_i : std_logic_vector(15 downto 0); - signal tx_k_i : std_logic; - signal fifo_opt_empty_synch_synch : std_logic; - signal fifo_rd_en_hub : std_logic; - constant SYSTEM : Integer := 2; -begin - SEND_ERROR: process (SYSTEM_CLK, RESET,SYNCH_CURRENT) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - MED_ERROR_OUT <= ERROR_NC; - elsif SYNCH_CURRENT = NORMAL_OPERATION_1 or SYNCH_CURRENT = NORMAL_OPERATION_2 then - MED_ERROR_OUT <= ERROR_OK; - elsif SYNCH_CURRENT = WAIT_1 or SYNCH_CURRENT = WAIT_2 then - MED_ERROR_OUT <= ERROR_WAIT; - else - MED_ERROR_OUT <= ERROR_NC; - end if; - end if; - end process SEND_ERROR; - PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - packet_number <= "011"; - elsif fifo_rd_en = '1' then - if packet_number = c_max_word_number then - packet_number <= "000"; - else - packet_number <= packet_number + 1; - end if; - end if; - end if; - end process PACKET_NUM; - MED_PACKET_NUM_OUT <= packet_number; - LINK_STATUS : process (SYSTEM_CLK,RESET) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - RX_RST <= '0'; - FLEXI_PCS_STATUS(15 downto 0) <= (others => '0'); - else - RX_RST <= rx_rst_i; - FLEXI_PCS_STATUS(2 downto 0) <= fsm_debug_register; - FLEXI_PCS_STATUS(7 downto 3) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full & DATA_VALID_IN;--fifo_almost_full & - --'0'; - FLEXI_PCS_STATUS(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); --- FLEXI_PCS_STATUS(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); - end if; - end if; - end process LINK_STATUS; - ----------------------------------------------------------------------------- - -- data from hub to link - ----------------------------------------------------------------------------- - data_opt_in <= "00" & TXD; - SYSTEM_SCM_MEMa: if SYSTEM=1 generate - CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR - port map ( - Data => data_opt_in, - WrClock => SYSTEM_CLK, - RdClock => TX_CLK, - WrEn => DATA_VALID_IN, - RdEn => fifo_opt_not_empty, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => txd_fifo_out, - Empty => fifo_opt_empty, - Full => fifo_opt_full, - AlmostEmpty => fifo_opt_almost_empty, - AlmostFull => fifo_opt_almost_full - ); - end generate SYSTEM_SCM_MEMa; - - SYSTEM_ECP2_MEMa: if SYSTEM=2 generate - CHANNEL_FIFO_TO_OPT: ecp2m_link_fifo - port map ( - Data => data_opt_in, - WrClock => SYSTEM_CLK, - RdClock => TX_CLK, - WrEn => DATA_VALID_IN, - RdEn => fifo_opt_not_empty, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => txd_fifo_out, - Empty => fifo_opt_empty, - Full => fifo_opt_full, - AlmostEmpty => fifo_opt_almost_empty, - AlmostFull => fifo_opt_almost_full - ); - end generate SYSTEM_ECP2_MEMa; - - - DATA_SEND_TO_LINK: process (TX_CLK, RESET, DATA_VALID_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch) - begin - if rising_edge(TX_CLK) then --falling ??? - if RESET = '1' then - tx_k_i <= '0'; - txd_synch_i <= (others => '0'); - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then - tx_k_i <= '0'; - txd_synch_i <= txd_fifo_out(15 downto 0); - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - else - tx_k_i <= '1'; - txd_synch_i <= x"c5bc"; - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - end if; - end if; - end process DATA_SEND_TO_LINK; - SYNCH_DATA: process (TX_CLK) - begin - if rising_edge(TX_CLK) then - TXD_SYNCH <= txd_synch_i; - TX_K(0) <= tx_k_i; - TX_K(1) <= '0'; - end if; - end process SYNCH_DATA; --- TX_FORCE_DISP(1) <= '0'; - ----------------------------------------------------------------------------- - -- from link to hub - ----------------------------------------------------------------------------- - SYSTEM_SCM_MEMb: if SYSTEM=1 generate - CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR - port map ( - Data => fifo_data_in, - WrClock => RX_CLK, - RdClock => SYSTEM_CLK, - WrEn => fifo_wr_en, - RdEn => fifo_rd_en, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => fifo_data_out, - Empty => fifo_empty, - Full => fifo_full, - AlmostEmpty => fifo_almost_empty, - AlmostFull => fifo_almost_full - ); - end generate SYSTEM_SCM_MEMb; - - SYSTEM_ECP2_MEMb: if SYSTEM=2 generate - CHANNEL_FIFO_TO_FPGA: ecp2m_link_fifo - port map ( - Data => fifo_data_in, - WrClock => RX_CLK, - RdClock => SYSTEM_CLK, - WrEn => fifo_wr_en, - RdEn => fifo_rd_en, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => fifo_data_out, - Empty => fifo_empty, - Full => fifo_full, - AlmostEmpty => fifo_almost_empty, - AlmostFull => fifo_almost_full - ); - end generate SYSTEM_ECP2_MEMb; - - not_fifo_empty <= not fifo_empty; - RD_FIFO_PULSE: edge_to_pulse - port map ( - clock => SYSTEM_CLK, - en_clk => '1', - signal_in => not_fifo_empty, - pulse => fifo_rd_pulse); - READING_THE_FIFO: process (SYSTEM_CLK, RESET, fifo_rd_pulse,MED_READ_IN,fifo_empty,data_valid_out_i) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - data_valid_out_i <= '0'; - fifo_rd_en_hub <= '0'; - elsif fifo_rd_pulse = '1' then - data_valid_out_i <= '1'; - fifo_rd_en_hub <= MED_READ_IN; - elsif MED_READ_IN = '1' and fifo_empty = '1' and data_valid_out_i = '1' then - data_valid_out_i <= '0'; - fifo_rd_en_hub <= '0'; - elsif data_valid_out_i = '1' and fifo_empty = '0' then - data_valid_out_i <= '1'; - fifo_rd_en_hub <= MED_READ_IN; - end if; - end if; - end process READING_THE_FIFO; - DATA_VALID_OUT <= data_valid_out_i; - fifo_rd_en <= (fifo_rd_en_hub and (not fifo_empty)) or fifo_rd_pulse; - RXD_SYNCH <= fifo_data_out(15 downto 0); --- DATA_VALID_OUT <= fifo_data_out(16) and (not fifo_empty); - VALID_DATA_SEND_TO_API: process (RX_CLK, RESET) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - rxd_synch_i <= (others => '0'); - rxd_synch_synch_i <= rxd_synch_i; - rx_k_synch_i <= "00"; - rx_k_synch_synch_i <= rx_k_synch_i; - else-- RX_K(0) = '1' then - rxd_synch_i <= RXD; - rxd_synch_synch_i <= rxd_synch_i; - rx_k_synch_i <= RX_K; - rx_k_synch_synch_i <= rx_k_synch_i; - end if; - end if; - end process VALID_DATA_SEND_TO_API; - SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNCH_CURRENT) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - fifo_data_in <= (others => '0'); - elsif SYNCH_CURRENT = NORMAL_OPERATION_2 then - fifo_data_in <= '0' & (not RX_K(0)) & RXD; - elsif SYNCH_CURRENT = NORMAL_OPERATION_1 then - fifo_data_in <= '0' & (not RX_K(1)) & rxd_synch_i(7 downto 0) & RXD(15 downto 8); - else - fifo_data_in <= (others => '0'); - end if; - end if; - end process SHIFT_OR_NOT_DATA_IN; - --- SYNCH_CLOCK : process (RX_CLK, RESET) - SYNCH_CLOCK : process (SYSTEM_CLK, RESET) - begin - if rising_edge (SYSTEM_CLK) then - if RESET = '1' then - SYNCH_CURRENT <= IDLE; --no_sim-- ---sim-- SYNCH_CURRENT <= NORMAL_OPERATION_2; - cv_i <= (others => '0'); - else - SYNCH_CURRENT <= SYNCH_NEXT; - cv_i <= CV; - end if; - end if; - end process SYNCH_CLOCK; - SYNCH_FSM : process( SYNCH_CURRENT, rxd_synch_i, resync_counter, cv_i,RX_K, MED_READ_IN ,fifo_rd_pulse, fifo_rd_en_hub,rx_k_synch_i) - begin - case (SYNCH_CURRENT) is - when IDLE => - fifo_rst <= '1'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "001"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '1'; --- if rxd_synch_i = x"bc50" then --- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1;--WAIT_1; - --els - if rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc" then - SYNCH_NEXT <= WAIT_2;--NORMAL_OPERATION_2; --WAIT_2; - else - SYNCH_NEXT <= RESYNC1; - end if; - when RESYNC1 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '1'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(8) = '1' then - SYNCH_NEXT <= RESYNC2; - else - SYNCH_NEXT <= RESYNC1; - end if; - when RESYNC2 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '0'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(16) = '1' then --at least 400us - SYNCH_NEXT <= RESYNC3; - else - SYNCH_NEXT <= RESYNC2; - end if; - - when RESYNC3 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '1'; --- if rxd_synch_i = x"bc50" and rx_k_synch_i(1) = '1' then --- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1; - --els - if (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then - SYNCH_NEXT <= WAIT_2;--no_sim-- ---sim-- SYNCH_NEXT <= NORMAL_OPERATION_2; - else - SYNCH_NEXT <= IDLE; - end if; - when WAIT_1 => - fifo_rst <= '0'; - rx_rst_i <= '0'; - fifo_wr_en <= '0'; - fsm_debug_register(2 downto 0) <= "011"; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(27) = '1' and (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' then - SYNCH_NEXT <= NORMAL_OPERATION_1; - elsif resync_counter(26) = '1' and (rxd_synch_i /= x"bc50" or rx_k_synch_i(1) = '0') then - SYNCH_NEXT <= RESYNC1; - else - SYNCH_NEXT <= WAIT_1; - end if; - when WAIT_2 => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - rx_rst_i <= '0'; - fsm_debug_register(2 downto 0) <= "011"; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter(27) = '1' and (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then - SYNCH_NEXT <= NORMAL_OPERATION_2; - elsif resync_counter(26) = '1' and (rxd_synch_i(7 downto 0) /= x"bc" or rx_k_synch_i(0) = '0') then - SYNCH_NEXT <= RESYNC1; - else - SYNCH_NEXT <= WAIT_2; - end if; - when NORMAL_OPERATION_1 => - fifo_rst <= '0'; - fifo_wr_en <= not rx_k_synch_i(1); - fsm_debug_register(2 downto 0) <= "110"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - if cv_i(0) = '1' or cv_i(1) = '1' then - SYNCH_NEXT <= IDLE; - else - SYNCH_NEXT <= NORMAL_OPERATION_1; - end if; - when NORMAL_OPERATION_2 => - fifo_rst <='0';--no_sim-- ---sim-- fifo_rst <=RESET; - fifo_wr_en <= not rx_k_synch_i(0); - fsm_debug_register(2 downto 0) <= "111"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - if cv_i(0) = '1' or cv_i(1) = '1' then - SYNCH_NEXT <= IDLE; - else - SYNCH_NEXT <= NORMAL_OPERATION_2; - end if; - when others => - fifo_rst <= '0'; - fifo_wr_en <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - fsm_debug_register(2 downto 0) <= "000"; - rx_rst_i <= '0'; - SYNCH_NEXT <= IDLE; - end case; - end process SYNCH_FSM; - - RESYNC_COUNTER_INST : simpleupcounter_32bit - port map ( - QOUT => resync_counter, - UP => resync_counter_up, - CLK => SYSTEM_CLK, - CLR => resync_counter_clr); - cv_or <= cv_i(0) or cv_i(1); - CV_COUNTER_INST: simpleupcounter_16bit - port map ( - QOUT => cv_counter, - UP => cv_or, - CLK => RX_CLK, - CLR => RESET); - WR_COUNTER_INST: simpleupcounter_16bit - port map ( - QOUT => fifo_wr_cnt, - UP => fifo_wr_en, - CLK => SYSTEM_CLK, - CLR => RESET); - fifo_rd_en_dv <= fifo_rd_en and fifo_data_out(16) and fifo_empty; - RD_COUNTER_INST: simpleupcounter_16bit - port map ( - QOUT => fifo_rd_cnt, - UP => DATA_VALID_IN,--fifo_rd_en_dv,--fifo_rd_en, - CLK => SYSTEM_CLK, - CLR => RESET); -end flexi_PCS_channel_synch; ---reciving idle for 1ms and start e11o until recive e11o and idle ---write to fifo when rx_k is 1 ? --- wait for reset --- wait for pll locked --- send idles --- wait 650ms (counter(27) = 1) --- enable rx --- wait 650ms (counter(27) = 1) --- enable tx --- ready diff --git a/oldfiles/serdes_test/flexi_PCS_fifo_EBR.vhd b/oldfiles/serdes_test/flexi_PCS_fifo_EBR.vhd deleted file mode 100644 index 5fbed36..0000000 --- a/oldfiles/serdes_test/flexi_PCS_fifo_EBR.vhd +++ /dev/null @@ -1,180 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) --- Module Version: 4.2 ---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_EBR -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e - --- Tue Nov 27 10:58:36 2007 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library SCM; -use SCM.COMPONENTS.all; --- synopsys translate_on - -entity flexi_PCS_fifo_EBR is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end flexi_PCS_fifo_EBR; - -architecture Structure of flexi_PCS_fifo_EBR is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal Empty_int: std_logic; - signal Full_int: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component FIFO16KA - -- synopsys translate_off - generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); - FULLPOINTER : in std_logic_vector(14 downto 0); - AFPOINTER1 : in std_logic_vector(14 downto 0); - AEPOINTER1 : in std_logic_vector(14 downto 0); - AFPOINTER : in std_logic_vector(14 downto 0); - AEPOINTER : in std_logic_vector(14 downto 0); - CSDECODE_R : in std_logic_vector(1 downto 0); - CSDECODE_W : in std_logic_vector(1 downto 0); - RESETMODE : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - FULLI: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; EMPTYI: in std_logic; - CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic; - RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic; - RST: in std_logic; RPRST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic; - EF: out std_logic; AEF: out std_logic; AFF: out std_logic; - FF: out std_logic); - end component; - attribute FULLPOINTER1 : string; - attribute FULLPOINTER : string; - attribute AFPOINTER1 : string; - attribute AFPOINTER : string; - attribute AEPOINTER1 : string; - attribute AEPOINTER : string; - attribute RESETMODE : string; - attribute REGMODE : string; - attribute CSDECODE_R : string; - attribute CSDECODE_W : string; - attribute DATA_WIDTH_R : string; - attribute DATA_WIDTH_W : string; - attribute FULLPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111000001"; - attribute FULLPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111100001"; - attribute AFPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101000001"; - attribute AFPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101100001"; - attribute AEPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101111111"; - attribute AEPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101011111"; - attribute RESETMODE of flexi_PCS_fifo_EBR_0_0 : label is "ASYNC"; - attribute REGMODE of flexi_PCS_fifo_EBR_0_0 : label is "NOREG"; - attribute CSDECODE_R of flexi_PCS_fifo_EBR_0_0 : label is "0b11"; - attribute CSDECODE_W of flexi_PCS_fifo_EBR_0_0 : label is "0b11"; - attribute DATA_WIDTH_R of flexi_PCS_fifo_EBR_0_0 : label is "36"; - attribute DATA_WIDTH_W of flexi_PCS_fifo_EBR_0_0 : label is "36"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - flexi_PCS_fifo_EBR_0_0: FIFO16KA - -- synopsys translate_off - generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", - AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001", - AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", - CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, - DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, - DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, - DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, - DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, - DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, - EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, - WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, - RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, - DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, - DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, - DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), - DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), - DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), - DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), - DO33=>Q(15), DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, - AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int); - - Empty <= Empty_int; - Full <= Full_int; -end Structure; - --- synopsys translate_off -library SCM; -configuration Structure_CON of flexi_PCS_fifo_EBR is - for Structure - for all:VHI use entity SCM.VHI(V); end for; - for all:VLO use entity SCM.VLO(V); end for; - for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/oldfiles/serdes_test/flexi_PCS_synch.vhd b/oldfiles/serdes_test/flexi_PCS_synch.vhd deleted file mode 100644 index bb6aff9..0000000 --- a/oldfiles/serdes_test/flexi_PCS_synch.vhd +++ /dev/null @@ -1,90 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---library UNISIM; ---use UNISIM.VCOMPONENTS.all; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; -use work.trb_net_std.all; - -entity flexi_PCS_synch is - generic ( - HOW_MANY_CHANNELS : positive); - port ( - SYSTEM_CLK : in std_logic; - CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0); - MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0); - MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0) - ); -end flexi_PCS_synch; -architecture flexi_PCS_synch of flexi_PCS_synch is - component flexi_PCS_channel_synch - port ( - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic; - RX_CLK : in std_logic; - RESET : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RXD_SYNCH : out std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : in std_logic_vector(15 downto 0); - TXD_SYNCH : out std_logic_vector(15 downto 0); - TX_K : out std_logic_vector(1 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(2 downto 0); - MED_READ_IN : in std_logic - ); - end component; -begin - CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate - begin - MED_READ_OUT <= (others => '1'); - - SYNCH :flexi_PCS_channel_synch - port map ( - SYSTEM_CLK => SYSTEM_CLK, - TX_CLK => CLK(bit_index/4), --4 different channles clk - RX_CLK => RX_CLK(bit_index), - RESET => RESET, - RXD => RXD((bit_index*16+15) downto bit_index*16), - RXD_SYNCH => MED_DATA_OUT((bit_index*16+15) downto bit_index*16), - RX_K => RX_K(bit_index*2+1 downto bit_index*2), - RX_RST => RX_RST(bit_index), - CV => CV((bit_index*2+1) downto bit_index*2), - TXD => MED_DATA_IN((bit_index*16+15) downto bit_index*16), - TXD_SYNCH => TXD_SYNCH((bit_index*16+15) downto bit_index*16), - TX_K => TX_K(bit_index*2+1 downto bit_index*2), - DATA_VALID_IN => MED_DATAREADY_IN(bit_index), - DATA_VALID_OUT => MED_DATAREADY_OUT(bit_index), - FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH), - MED_ERROR_OUT => MED_ERROR_OUT((bit_index*3+2) downto bit_index*3), - MED_READ_IN => MED_READ_IN(bit_index) - ); - end generate; -end flexi_PCS_synch; diff --git a/oldfiles/serdes_test/hub.vhd b/oldfiles/serdes_test/hub.vhd deleted file mode 100644 index 5699c6a..0000000 --- a/oldfiles/serdes_test/hub.vhd +++ /dev/null @@ -1,1076 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---library UNISIM; ---use UNISIM.VCOMPONENTS.all; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; -use work.version.all; -use work.trb_net_std.all; -use work.trb_net16_hub_func.all; --- library sc; --- use sc.components.all; -entity hub is - generic ( - HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 16 - ); - port ( - LVDS_CLK_200P : in std_logic; --- LVDS_CLK_200N : in std_logic; --- SERDES_200N : in std_logic; --- SERDES_200P : in std_logic; --- ADO_LV : in std_logic_vector(61 downto 0); - --addon connector - ADO_TTL : inout std_logic_vector(46 downto 0); - --diode - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; - --data to/from optical tranceivers - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0); - --tempsens - FS_PE_11 : inout std_logic; - --etrax_interface - FS_PE : inout std_logic_vector(9 downto 8)--sim-- ; ---sim-- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); ---sim-- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); ---sim-- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); ---sim-- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0) - ); -end hub; -architecture hub of hub is - component trb_hub_interface - port ( - CLK : in std_logic; - RESET : in std_logic; - STROBE : in std_logic; - INTERNAL_DATA_IN : in std_logic_vector(7 downto 0); - INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0); - INTERNAL_ADDRESS : in std_logic_vector(15 downto 0); - INTERNAL_MODE : in std_logic; - VALID_DATA_SENT : out std_logic; - hub_register_00 : in std_logic_vector(7 downto 0); - hub_register_01 : in std_logic_vector(7 downto 0); - hub_register_02 : in std_logic_vector(7 downto 0); - hub_register_03 : in std_logic_vector(7 downto 0); - hub_register_04 : in std_logic_vector(7 downto 0); - hub_register_05 : in std_logic_vector(7 downto 0); - hub_register_06 : in std_logic_vector(7 downto 0); - hub_register_07 : in std_logic_vector(7 downto 0); - hub_register_08 : in std_logic_vector(7 downto 0); - hub_register_09 : in std_logic_vector(7 downto 0); - hub_register_0a : out std_logic_vector(7 downto 0); - hub_register_0b : out std_logic_vector(7 downto 0); - hub_register_0c : out std_logic_vector(7 downto 0); - hub_register_0d : out std_logic_vector(7 downto 0); - hub_register_0e : out std_logic_vector(7 downto 0); - hub_register_0f : out std_logic_vector(7 downto 0); - hub_register_10 : in std_logic_vector(7 downto 0); - hub_register_11 : in std_logic_vector(7 downto 0); - hub_register_12 : in std_logic_vector(7 downto 0); - hub_register_13 : in std_logic_vector(7 downto 0); - hub_register_14 : in std_logic_vector(7 downto 0); - hub_register_15 : in std_logic_vector(7 downto 0); - hub_register_16 : in std_logic_vector(7 downto 0) - ); - end component; - component serdes_fpga_ref_clk--serdes, flexi PCS - port( --- refclkp : in std_logic; --- refclkn : in std_logic; - rxrefclk : in std_logic; - refclk : in std_logic; - hdinp_0 : in std_logic; - hdinn_0 : in std_logic; - tclk_0 : in std_logic; - rclk_0 : in std_logic; - tx_rst_0 : in std_logic; - rx_rst_0 : in std_logic; - txd_0 : in std_logic_vector(15 downto 0); - tx_k_0 : in std_logic_vector(1 downto 0); - tx_force_disp_0 : in std_logic_vector(1 downto 0); - tx_disp_sel_0 : in std_logic_vector(1 downto 0); - tx_crc_init_0 : in std_logic_vector(1 downto 0); - word_align_en_0 : in std_logic; - mca_align_en_0 : in std_logic; - felb_0 : in std_logic; - lsm_en_0 : in std_logic; - hdinp_1 : in std_logic; - hdinn_1 : in std_logic; - tclk_1 : in std_logic; - rclk_1 : in std_logic; - tx_rst_1 : in std_logic; - rx_rst_1 : in std_logic; - txd_1 : in std_logic_vector(15 downto 0); - tx_k_1 : in std_logic_vector(1 downto 0); - tx_force_disp_1 : in std_logic_vector(1 downto 0); - tx_disp_sel_1 : in std_logic_vector(1 downto 0); - tx_crc_init_1 : in std_logic_vector(1 downto 0); - word_align_en_1 : in std_logic; - mca_align_en_1 : in std_logic; - felb_1 : in std_logic; - lsm_en_1 : in std_logic; - hdinp_2 : in std_logic; - hdinn_2 : in std_logic; - tclk_2 : in std_logic; - rclk_2 : in std_logic; - tx_rst_2 : in std_logic; - rx_rst_2 : in std_logic; - txd_2 : in std_logic_vector(15 downto 0); - tx_k_2 : in std_logic_vector(1 downto 0); - tx_force_disp_2 : in std_logic_vector(1 downto 0); - tx_disp_sel_2 : in std_logic_vector(1 downto 0); - tx_crc_init_2 : in std_logic_vector(1 downto 0); - word_align_en_2 : in std_logic; - mca_align_en_2 : in std_logic; - felb_2 : in std_logic; - lsm_en_2 : in std_logic; - hdinp_3 : in std_logic; - hdinn_3 : in std_logic; - tclk_3 : in std_logic; - rclk_3 : in std_logic; - tx_rst_3 : in std_logic; - rx_rst_3 : in std_logic; - txd_3 : in std_logic_vector(15 downto 0); - tx_k_3 : in std_logic_vector(1 downto 0); - tx_force_disp_3 : in std_logic_vector(1 downto 0); - tx_disp_sel_3 : in std_logic_vector(1 downto 0); - tx_crc_init_3 : in std_logic_vector(1 downto 0); - word_align_en_3 : in std_logic; - mca_align_en_3 : in std_logic; - felb_3 : in std_logic; - lsm_en_3 : in std_logic; - mca_resync_01 : in std_logic; - mca_resync_23 : in std_logic; - quad_rst : in std_logic; - serdes_rst : in std_logic; - rxa_pclk : out std_logic; - rxb_pclk : out std_logic; - hdoutp_0 : out std_logic; - hdoutn_0 : out std_logic; - ref_0_sclk : out std_logic; - rx_0_sclk : out std_logic; - rxd_0 : out std_logic_vector(15 downto 0); - rx_k_0 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_0 : out std_logic_vector(1 downto 0); - rx_cv_detect_0 : out std_logic_vector(1 downto 0); - rx_crc_eop_0 : out std_logic_vector(1 downto 0); - lsm_status_0 : out std_logic; - hdoutp_1 : out std_logic; - hdoutn_1 : out std_logic; - ref_1_sclk : out std_logic; - rx_1_sclk : out std_logic; - rxd_1 : out std_logic_vector(15 downto 0); - rx_k_1 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_1 : out std_logic_vector(1 downto 0); - rx_cv_detect_1 : out std_logic_vector(1 downto 0); - rx_crc_eop_1 : out std_logic_vector(1 downto 0); - lsm_status_1 : out std_logic; - hdoutp_2 : out std_logic; - hdoutn_2 : out std_logic; - ref_2_sclk : out std_logic; - rx_2_sclk : OUT std_logic; - rxd_2 : OUT std_logic_vector(15 downto 0); - rx_k_2 : OUT std_logic_vector(1 downto 0); - rx_disp_err_detect_2 : OUT std_logic_vector(1 downto 0); - rx_cv_detect_2 : OUT std_logic_vector(1 downto 0); - rx_crc_eop_2 : OUT std_logic_vector(1 downto 0); - lsm_status_2 : OUT std_logic; - hdoutp_3 : OUT std_logic; - hdoutn_3 : OUT std_logic; - ref_3_sclk : OUT std_logic; - rx_3_sclk : OUT std_logic; - rxd_3 : OUT std_logic_vector(15 downto 0); - rx_k_3 : OUT std_logic_vector(1 downto 0); - rx_disp_err_detect_3 : out std_logic_vector(1 downto 0); - rx_cv_detect_3 : out std_logic_vector(1 downto 0); - rx_crc_eop_3 : out std_logic_vector(1 downto 0); - lsm_status_3 : out std_logic; - mca_aligned_01 : out std_logic; - mca_inskew_01 : out std_logic; - mca_outskew_01 : out std_logic; - mca_aligned_23 : out std_logic; - mca_inskew_23 : out std_logic; - mca_outskew_23 : out std_logic; - ref_pclk : out std_logic - ); - end component; - component flexi_PCS_synch - generic ( - HOW_MANY_CHANNELS : positive); - port ( - SYSTEM_CLK : in std_logic; - CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0); - MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0); - MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0) - ); - end component; - component pll_ref - port ( - clk : in std_logic; - clkop : out std_logic; - clkos : out std_logic; - lock : out std_logic); - end component; --- component trb_net16_hub_base --- generic ( --- --general settings --- MUX_SECURE_MODE : integer range 0 to 1 := c_NO; --- --hub control --- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0;--c_SLOW_CTRL_CHANNEL; --- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; --- HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4; --- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES); --- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; --- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F00A"; --- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); --- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; --- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; --- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; --- --media interfaces --- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := HOW_MANY_CHANNELS; --- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; --- -- settings for apis --- API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; --- API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); --- API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0); --- API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1); --- API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1); --- --trigger reading interfaces --- TRG_NUMBER : integer range 0 to c_MAX_TRG_PER_HUB := 0; --- TRG_SECURE_MODE : integer range 0 to 1 := c_NO; --- TRG_CHANNELS : hub_api_config_t := (0,1,0,0,0,0,0,0) --- ); --- port ( --- CLK : in std_logic; --- RESET : in std_logic; --- CLK_EN : in std_logic; --- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); --- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); --- MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); --- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); --- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); --- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); --- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); --- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); --- MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0); --- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0); --- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0); --- APL_DATA_IN : in std_logic_vector (API_NUMBER*c_DATA_WIDTH downto 0); --- APL_PACKET_NUM_IN : in std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0); --- APL_DATAREADY_IN : in std_logic_vector (API_NUMBER downto 0); --- APL_READ_OUT : out std_logic_vector (API_NUMBER downto 0); --- APL_SHORT_TRANSFER_IN : in std_logic_vector (API_NUMBER downto 0); --- APL_DTYPE_IN : in std_logic_vector (API_NUMBER*4 downto 0); --- APL_ERROR_PATTERN_IN : in std_logic_vector (API_NUMBER*32 downto 0); --- APL_SEND_IN : in std_logic_vector (API_NUMBER downto 0); --- APL_TARGET_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0); --- APL_DATA_OUT : out std_logic_vector (API_NUMBER*16 downto 0); --- APL_PACKET_NUM_OUT : out std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0); --- APL_TYP_OUT : out std_logic_vector (API_NUMBER*3 downto 0); --- APL_DATAREADY_OUT : out std_logic_vector (API_NUMBER downto 0); --- APL_READ_IN : in std_logic_vector (API_NUMBER downto 0); --- APL_RUN_OUT : out std_logic_vector (API_NUMBER downto 0); --- APL_MY_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0); --- APL_SEQNR_OUT : out std_logic_vector (API_NUMBER*8 downto 0); --- TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0); --- TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0); --- TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0); --- TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0); --- TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0); --- TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0); --- ONEWIRE : inout std_logic; --- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); --- HUB_STAT_GEN : out std_logic_vector (31 downto 0); --- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); --- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); --- ETRAX_CTRL : in std_logic_vector (15 downto 0) --- ); --- end component; - component simpleupcounter_16bit - port ( - QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component simpleupcounter_32bit - port ( - QOUT : out std_logic_vector(31 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); - end component; - component trb_net_onewire - generic ( - USE_TEMPERATURE_READOUT : integer range 0 to 1; - CLK_PERIOD : integer); - port ( - CLK : in std_logic; - RESET : in std_logic; - ONEWIRE : inout std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT : out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - STAT : out std_logic_vector(31 downto 0)); - end component; - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - component DCS --- synthesis translate_off - --sim - generic ( - DCSMODE : string := "LOW_LOW"); --- synthesis translate_on - port ( - CLK0 : in std_logic; - CLK1 : in std_logic; - SEL : in std_logic; - DCSOUT : out std_logic); - end component; - component etrax_interfacev2 - generic ( - RW_SYSTEM : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_BUS : in std_logic_vector(31 downto 0); - ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0); - ETRAX_DATA_BUS_B_17 : in std_logic; - ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0); - ETRAX_DATA_BUS_E : inout std_logic_vector(10 downto 9); - DATA_VALID : in std_logic; - ETRAX_BUS_BUSY : in std_logic; - ETRAX_IS_READY_TO_READ : out std_logic; - TDC_TCK : out std_logic; - TDC_TDI : out std_logic; - TDC_TMS : out std_logic; - TDC_TRST : out std_logic; - TDC_TDO : in std_logic; - TDC_RESET : out std_logic; - EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); - EXTERNAL_ACK : out std_logic; - EXTERNAL_VALID : in std_logic; - EXTERNAL_MODE : out std_logic_vector(15 downto 0); - FPGA_REGISTER_00 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0E : out std_logic_vector(31 downto 0); --- EXTERNAL_RESET : out std_logic; - LVL2_VALID : in std_logic); - end component; - - component hub_etrax_interface - port ( - CLK : in std_logic; - RESET : in std_logic; - ETRAX_DATA_BUS : inout std_logic_vector(17 downto 5); - EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); - EXTERNAL_ACK : out std_logic; - EXTERNAL_VALID : in std_logic; - EXTERNAL_MODE : out std_logic_vector(7 downto 0); - FPGA_REGISTER_00 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0E : out std_logic_vector(31 downto 0); - EXTERNAL_RESET : out std_logic); - end component; - - component simple_hub - generic ( - HOW_MANY_CHANNELS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - DATA_IN_VALID : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - SEND_DATA : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - ENABLE_CHANNELS : in std_logic_vector(15 downto 0); - READ_DATA : out std_logic_vector(HOW_MANY_CHANNELS -1 downto 0); - HUB_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; --- constant HOW_MANY_CHANNELS : integer := 16; - ----------------------------------------------------------------------------- - -- FLEXI_PCS - ----------------------------------------------------------------------------- - signal ref_pclk : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0); - signal rxd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal rxd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal rx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rx_rst_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal cv_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal txd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal tx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0); - signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal flexi_pcs_synch_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal word_align_en : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - ----------------------------------------------------------------------------- - -- hub trb interface - ----------------------------------------------------------------------------- - signal hub_register_00_i : std_logic_vector(31 downto 0); - signal hub_register_01_i : std_logic_vector(31 downto 0); - signal hub_register_02_i : std_logic_vector(31 downto 0); - signal hub_register_03_i : std_logic_vector(31 downto 0); - signal hub_register_04_i : std_logic_vector(31 downto 0); - signal hub_register_05_i : std_logic_vector(31 downto 0); - signal hub_register_06_i : std_logic_vector(31 downto 0); - signal hub_register_07_i : std_logic_vector(31 downto 0); - signal hub_register_08_i : std_logic_vector(31 downto 0); - signal hub_register_09_i : std_logic_vector(31 downto 0); - signal hub_register_0a_i : std_logic_vector(31 downto 0); - signal hub_register_0b_i : std_logic_vector(31 downto 0); - signal hub_register_0c_i : std_logic_vector(31 downto 0); - signal hub_register_0d_i : std_logic_vector(31 downto 0); - signal hub_register_0e_i : std_logic_vector(31 downto 0); - signal hub_register_0f_i : std_logic_vector(31 downto 0); - signal hub_register_10_i : std_logic_vector(31 downto 0); - signal hub_register_11_i : std_logic_vector(31 downto 0); - signal hub_register_12_i : std_logic_vector(31 downto 0); - signal hub_register_13_i : std_logic_vector(31 downto 0); - signal hub_register_14_i : std_logic_vector(31 downto 0); - signal hub_register_15_i : std_logic_vector(31 downto 0); - signal hub_register_16_i : std_logic_vector(31 downto 0); - signal ADO_TTL_12 : std_logic; - ----------------------------------------------------------------------------- - -- flexi_PCS to hub interface - ----------------------------------------------------------------------------- - signal med_dataready_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - --test - signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_dataready_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_read_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_read_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - signal med_error_out_i : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0); - signal med_stat_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal hub_stat_channel_i : std_logic_vector(2**(c_MUX_WIDTH-1)*16-1 downto 0); - signal hub_stat_gen_i : std_logic_vector(31 downto 0); - - ----------------------------------------------------------------------------- - -- other - ----------------------------------------------------------------------------- - signal hub_register_0e_and_0d : std_logic_vector(15 downto 0) := x"0006"; - signal cv_counter : std_logic_vector(31 downto 0); - signal cv_countera : std_logic_vector(31 downto 0); - signal serdes_ref_clk : std_logic; - signal serdes_ref_lock : std_logic; - signal serdes_ref_clks : std_logic; - signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0); - signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0); - signal word_counter_for_api_00 : std_logic_vector(1 downto 0); - signal word_counter_for_api_01 : std_logic_vector(1 downto 0); - signal global_reset_i : std_logic; - signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0"; - signal registered_signals : std_logic_vector(7 downto 0); - signal hub_register_0a_i_synch : std_logic_vector(7 downto 0); - signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0); - signal test_signal : std_logic_vector(1 downto 0); - signal pulse_test : std_logic; - signal saved_lvl1_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0'); - signal saved_lvl2_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0'); - signal all_lvl1_ready : std_logic; - signal all_lvl2_ready : std_logic; - signal flexi_pcs_ref_clk : std_logic; - signal lok_i : std_logic_vector(16 downto 1); - signal not_used_lok : std_logic_vector(15 downto 0); - signal used_channels_locked : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal channels_locked : std_logic_vector(16 downto 1); - signal switch_rx_clk : std_logic; - signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal all_lvl1_ready_delay1 : std_logic; - signal all_lvl1_ready_delay2 : std_logic; - signal all_lvl2_ready_delay1 : std_logic; - signal all_lvl2_ready_delay2 : std_logic; - -- etrax interface --- signal external_address_i : std_logic_vector(31 downto 0); --- signal external_data_out_i : std_logic_vector(31 downto 0); --- signal external_data_in_i : std_logic_vector(31 downto 0); --- signal external_ack_i : std_logic; --- signal external_valid_i : std_logic; --- signal external_mode_i : std_logic_vector(7 downto 0); --- signal data_valid_i : std_logic; - signal debug_register_00_i : std_logic_vector(7 downto 0); - signal test2 : std_logic_vector(1 downto 0); - signal med_read_counter : std_logic_vector(3 downto 0); - -- simulation - signal rx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal tx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - constant trb_net_enable : integer := 0; - --etrax interface - signal external_address_i : std_logic_vector(31 downto 0); - signal external_data_out_i : std_logic_vector(31 downto 0); - signal external_data_in_i : std_logic_vector(31 downto 0); - signal external_ack_i : std_logic; - signal external_valid_i : std_logic; - signal external_mode_i : std_logic_vector(15 downto 0); - signal fpga_register_00_i : std_logic_vector(31 downto 0); - signal fpga_register_01_i : std_logic_vector(31 downto 0); - signal fpga_register_02_i : std_logic_vector(31 downto 0); - signal fpga_register_03_i : std_logic_vector(31 downto 0); - signal fpga_register_04_i : std_logic_vector(31 downto 0); - signal fpga_register_05_i : std_logic_vector(31 downto 0); - signal fpga_register_06_i : std_logic_vector(31 downto 0):=x"00000003"; - signal fpga_register_07_i : std_logic_vector(31 downto 0); - signal fpga_register_08_i : std_logic_vector(31 downto 0); - signal fpga_register_09_i : std_logic_vector(31 downto 0); - signal fpga_register_0a_i : std_logic_vector(31 downto 0); - signal fpga_register_0b_i : std_logic_vector(31 downto 0); - signal fpga_register_0c_i : std_logic_vector(31 downto 0); - signal fpga_register_0d_i : std_logic_vector(31 downto 0); - signal fpga_register_0e_i : std_logic_vector(31 downto 0); - --simple hub - signal hub_debug_i : std_logic_vector(31 downto 0); - --test - constant OPT_TEST_MODE : integer := 1; - -begin - GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_cnt < x"e" then - global_reset_cnt <= global_reset_cnt + 1; - global_reset_i <= '1'; - elsif global_reset_cnt = x"e" then - global_reset_i <= '0'; - global_reset_cnt <= x"e"; - else - global_reset_i <= '0'; - global_reset_cnt <= global_reset_cnt; - end if; - end if; - end process GLOBAL_RESET; - REF_PLL: pll_ref - port map ( - clk => LVDS_CLK_200P, - clkop => serdes_ref_clk, - clkos => serdes_ref_clks, - lock => serdes_ref_lock); - TEST: edge_to_pulse - port map ( - clock => ref_pclk(0), - en_clk => '1', - signal_in => hub_register_0a_i(0), - pulse => pulse_test); - test_signal(1) <= pulse_test; - test_signal(0) <= pulse_test; - REF_CLK_SELECT: DCS - -- synthesis translate_off - - generic map (--no_sim-- - DCSMODE => DCSMODE)--no_sim-- - -- synthesis translate_on - port map ( - CLK0 => LVDS_CLK_200P, - CLK1 => '0', - SEL => switch_rx_clk,--hub_register_0a_i(0),--'0',--switch_rx_clk, - DCSOUT => flexi_pcs_ref_clk); - SWITCH_CLOCK: process (LVDS_CLK_200P, global_reset_i) - begin -- process SWITCH_CLOCK - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' or lock_pattern /= used_channels_locked then -- asynchronous reset (active low) - switch_rx_clk <= '0'; - lock_pattern <= (others => '1'); - elsif lock_pattern = used_channels_locked then - switch_rx_clk <= '1'; - lock_pattern <= (others => '1'); - end if; - end if; - end process SWITCH_CLOCK; --- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate --- begin --- used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16); --- end generate LOK_STATUS_DIOD_EN; - - --lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1); - QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate - begin - QUAD : serdes_fpga_ref_clk - port map ( --- refclkp => SERDES_200P, --- refclkn => SERDES_200N, - rxrefclk => flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, - refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, - hdinp_0 => SFP_INP_P(bit_index*4+0), - hdinn_0 => SFP_INP_N(bit_index*4+0), - tclk_0 => ref_pclk(bit_index), - rclk_0 => rx_clk_i(0+bit_index*4), - tx_rst_0 => '0', - rx_rst_0 => rx_rst_i(0+bit_index*4),--hub_register_0a_i(0), - txd_0 => txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,-- - tx_k_0 => tx_k_i(1+bit_index*8 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10", - tx_force_disp_0 => "00",--hub_register_0a_i(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8), - tx_disp_sel_0 => "00",--hub_register_0a_i(5 downto 4), --"00",--hub_register_0a_i_synch(5 downto 4),--"00", - tx_crc_init_0 => "00", - word_align_en_0 => '1',--word_align_en(0+bit_index*4),--'1', - mca_align_en_0 => '0', - felb_0 => '0', - lsm_en_0 => '0', - hdinp_1 => SFP_INP_P(bit_index*4+1), - hdinn_1 => SFP_INP_N(bit_index*4+1), - tclk_1 => ref_pclk(bit_index), - rclk_1 => rx_clk_i(1+bit_index*4), - tx_rst_1 => '0', - rx_rst_1 => rx_rst_i(1+bit_index*4), - txd_1 => txd_synch_i(31+bit_index*64 downto 16+bit_index*64), - tx_k_1 => tx_k_i(3+bit_index*8 downto 2+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10", - tx_force_disp_1 => "00",--tx_k_i(3+bit_index*8 downto 2+bit_index*8), - tx_disp_sel_1 => "00", - tx_crc_init_1 => "00", - word_align_en_1 => '1',--word_align_en(1+bit_index*4),--'1',-- - mca_align_en_1 => '0', - felb_1 => '0', - lsm_en_1 => '0', - hdinp_2 => SFP_INP_P(bit_index*4+2), - hdinn_2 => SFP_INP_N(bit_index*4+2), - tclk_2 => ref_pclk(bit_index), - rclk_2 => rx_clk_i(2+bit_index*4), - tx_rst_2 => '0', - rx_rst_2 => rx_rst_i(2+bit_index*4), - txd_2 => txd_synch_i(47+bit_index*64 downto 32+bit_index*64), - tx_k_2 => tx_k_i(5+bit_index*8 downto 4+bit_index*8),--"10", - tx_force_disp_2 => "00",-- - tx_disp_sel_2 => "00", - tx_crc_init_2 => "00", - word_align_en_2 => '1',--word_align_en(2+bit_index*4),--'1', - mca_align_en_2 => '0', - felb_2 => '0', - lsm_en_2 => '0', - hdinp_3 => SFP_INP_P(bit_index*4+3), - hdinn_3 => SFP_INP_N(bit_index*4+3), - tclk_3 => ref_pclk(bit_index), - rclk_3 => rx_clk_i(3+bit_index*4), - tx_rst_3 => '0', - rx_rst_3 => rx_rst_i(3+bit_index*4), - txd_3 => txd_synch_i(63+bit_index*64 downto 48+bit_index*64), - tx_k_3 => tx_k_i(7+bit_index*8 downto 6+bit_index*8),--"10", - tx_force_disp_3 => "00", - tx_disp_sel_3 => "00", - tx_crc_init_3 => "00", - word_align_en_3 => '1',--word_align_en(3+bit_index*4),--'1', - mca_align_en_3 => '0', - felb_3 => '0', - lsm_en_3 => '0', - mca_resync_01 => '0', - mca_resync_23 => '0', - quad_rst => '0', - serdes_rst => '0', - rxa_pclk => rx_clk_i(0+bit_index*4), - rxb_pclk => rxb_pclk_a(bit_index), - hdoutp_0 => SFP_OUT_P(bit_index*4+0), - hdoutn_0 => SFP_OUT_N(bit_index*4+0), - ref_0_sclk => open, - rx_0_sclk => open, - rxd_0 => rxd_i(15+bit_index*64 downto 0+bit_index*64), - rx_k_0 => rx_k_i(1+bit_index*8 downto 0+bit_index*8), - rx_disp_err_detect_0 => open, --rx_disp_err_detect_0_a, - rx_cv_detect_0 => cv_i(1+bit_index*8 downto 0+bit_index*8), - rx_crc_eop_0 => open, - lsm_status_0 => open, - hdoutp_1 => SFP_OUT_P(bit_index*4+1), - hdoutn_1 => SFP_OUT_N(bit_index*4+1), - ref_1_sclk => open, - rx_1_sclk => rx_clk_i(1+bit_index*4), - rxd_1 => rxd_i(31+bit_index*64 downto 16+bit_index*64), - rx_k_1 => rx_k_i(3+bit_index*8 downto 2+bit_index*8), - rx_disp_err_detect_1 => open, --rx_disp_err_detect_1_a, - rx_cv_detect_1 => cv_i(3+bit_index*8 downto 2+bit_index*8), - rx_crc_eop_1 => open, - lsm_status_1 => open, - hdoutp_2 => SFP_OUT_P(bit_index*4+2), - hdoutn_2 => SFP_OUT_N(bit_index*4+2), - ref_2_sclk => open, - rx_2_sclk => rx_clk_i(2+bit_index*4), - rxd_2 => rxd_i(47+bit_index*64 downto 32+bit_index*64), - rx_k_2 => rx_k_i(5+bit_index*8 downto 4+bit_index*8), - rx_disp_err_detect_2 => open, --rx_disp_err_detect_2_a, - rx_cv_detect_2 => cv_i(5+bit_index*8 downto 4+bit_index*8), - rx_crc_eop_2 => open, - lsm_status_2 => open, - hdoutp_3 => SFP_OUT_P(bit_index*4+3), - hdoutn_3 => SFP_OUT_N(bit_index*4+3), - ref_3_sclk => open, - rx_3_sclk => rx_clk_i(3+bit_index*4), - rxd_3 => rxd_i(63+bit_index*64 downto 48+bit_index*64), - rx_k_3 => rx_k_i(7+bit_index*8 downto 6+bit_index*8), - rx_disp_err_detect_3 => open, --rx_disp_err_detect_3_a, - rx_cv_detect_3 => cv_i(7+bit_index*8 downto 6+bit_index*8), - rx_crc_eop_3 => open, - lsm_status_3 => open, - mca_aligned_01 => open, --mca_aligned_01_i, - mca_inskew_01 => open, --mca_inskew_01_i, - mca_outskew_01 => open, --mca_outskew_01_i, - mca_aligned_23 => open, --mca_aligned_23_i, - mca_inskew_23 => open, --mca_inskew_23_i, - mca_outskew_23 => open, --mca_outskew_23_i, - ref_pclk => ref_pclk(bit_index) - ); - end generate QUAD_GENERATE; - -- word_align_en <= not rx_rst_i; ---sim-- SIMULATION_CONNECTION: for i in 0 to HOW_MANY_CHANNELS-1 generate ---sim-- rx_k_sim(i*2) <= not OPT_DATA_VALID_IN(i); ---sim-- rx_k_sim(i*2+1) <= '0'; ---sim-- OPT_DATA_VALID_OUT(i) <= not tx_k_sim(i*2); ---sim-- rx_clk_sim <= (others => LVDS_CLK_200P); ---sim-- ref_pclk_sim <= (others => LVDS_CLK_200P); ---sim-- cv_sim <= (others => '0'); ---sim-- end generate SIMULATION_CONNECTION; - FLEXI_PCS_INT : flexi_PCS_synch - generic map ( - HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) - port map ( - SYSTEM_CLK => LVDS_CLK_200P, - CLK => ref_pclk,--no_sim-- ---sim-- CLK => ref_pclk_sim, - RX_CLK => rx_clk_i,--no_sim-- ---sim-- RX_CLK => rx_clk_sim, - RESET => global_reset_i, - RXD => rxd_i,--no_sim-- ---sim-- RXD => OPT_DATA_IN, - MED_DATA_OUT => med_data_out_i, - RX_K => rx_k_i,--no_sim-- ---sim-- RX_K => rx_k_sim, - RX_RST => rx_rst_i, - CV => cv_i,--no_sim-- ---sim-- CV => cv_sim, - MED_DATA_IN => med_data_in_i, - TXD_SYNCH => txd_synch_i, --no_sim-- ---sim-- TXD_SYNCH => OPT_DATA_OUT, - TX_K => tx_k_i, --no_sim-- ---sim-- TX_K => tx_k_sim, - FLEXI_PCS_SYNCH_STATUS => flexi_pcs_synch_status_i, - MED_DATAREADY_IN => med_dataready_in_i, - MED_DATAREADY_OUT => med_dataready_out_i, - MED_PACKET_NUM_IN => med_packet_num_in_i, - MED_PACKET_NUM_OUT => med_packet_num_out_i, - MED_READ_IN => med_read_in_i, - MED_READ_OUT => med_read_out_i, - MED_ERROR_OUT => med_error_out_i, - MED_STAT_OP => med_stat_op_i, - MED_CTRL_OP => med_ctrl_op_i - ); --- SIMPLE_HUB_GEN: if trb_net_enable = 0 and OPT_TEST_MODE = 0 generate --- SIMPLE_HUB_INST: simple_hub --- generic map ( --- HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) --- port map ( --- CLK => LVDS_CLK_200P, --- RESET => global_reset_i, --- DATA_IN => med_data_out_i, --- DATA_OUT => med_data_in_i, --- DATA_IN_VALID => med_dataready_out_i, --- SEND_DATA => med_dataready_in_i, --- ENABLE_CHANNELS => fpga_register_06_i(15 downto 0), --- READ_DATA => med_read_in_i, --- HUB_DEBUG => hub_debug_i --- ); - --- end generate SIMPLE_HUB_GEN; - --- ENABLE_OPT_TEST: if OPT_TEST_MODE = 1 generate - med_read_in_i <= (others => '1'); - med_data_in_i <= med_data_out_i; - med_dataready_in_i <= med_dataready_out_i; --- end generate ENABLE_OPT_TEST; --- ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0); --- ADO_TTL(34 downto 19) <= med_dataready_out_i(0)& med_data_out_i(14 downto 0); --- ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0); --- ADO_TTL(15 downto 0) <= rx_k_i(1 downto 0) & rxd_i(13 downto 0); --- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d; --- med_read_in_i <= (others => '1'); --test - --- ENABLE_TRB_NET: if trb_net_enable = 1 generate --- HUB_API: trb_net16_hub_base --- port map ( --- CLK => LVDS_CLK_200P, --- RESET => global_reset_i, --- CLK_EN => '1', --- MED_DATAREADY_OUT => med_dataready_in_i, --- MED_DATA_OUT => med_data_in_i, --- MED_PACKET_NUM_OUT => med_packet_num_in_i, --- MED_READ_IN => med_read_out_i, --- MED_DATAREADY_IN => med_dataready_out_i, --- MED_DATA_IN => med_data_out_i, --- MED_PACKET_NUM_IN => med_packet_num_out_i, --- MED_READ_OUT => med_read_in_i, --- MED_ERROR_IN => med_error_out_i, --- MED_STAT_OP => med_stat_op_i, --- MED_CTRL_OP => med_ctrl_op_i, --- APL_DATA_IN => (others => '0'), --- APL_PACKET_NUM_IN => (others => '0'), --- APL_DATAREADY_IN => (others => '0'), --- APL_READ_OUT => open, --- APL_SHORT_TRANSFER_IN => (others => '0'), --- APL_DTYPE_IN => (others => '0'), --- APL_ERROR_PATTERN_IN => (others => '0'), --- APL_SEND_IN => (others => '0'), --- APL_TARGET_ADDRESS_IN => (others => '0'), --- APL_DATA_OUT => open, --- APL_PACKET_NUM_OUT => open, --- APL_TYP_OUT => open, --- APL_DATAREADY_OUT => open, --- APL_READ_IN => (others => '0'), --- APL_RUN_OUT => open, --- APL_MY_ADDRESS_IN => (others => '0'), --- APL_SEQNR_OUT => open, --- TRG_GOT_TRIGGER_OUT => open, --- TRG_ERROR_PATTERN_OUT => open, --- TRG_DTYPE_OUT => open, --- TRG_SEQNR_OUT => open, --- TRG_ERROR_PATTERN_IN => (others => '0'), --- TRG_RELEASE_IN => (others => '0'), --- ONEWIRE => FS_PE_11, --- HUB_STAT_CHANNEL => hub_stat_channel_i, --- HUB_STAT_GEN => hub_stat_gen_i, --- MPLEX_CTRL => mplex_ctrl_i, --- MPLEX_STAT => open, --- ETRAX_CTRL => hub_register_0e_and_0d --- ); --- end generate ENABLE_TRB_NET; - ETRAX_RW_DATA_INTERFACE: etrax_interfacev2 - generic map ( - RW_SYSTEM => 2) - port map ( - CLK => LVDS_CLK_200P, - RESET => global_reset_i, - DATA_BUS => (others => '0'), - ETRAX_DATA_BUS_B => open,--(others => '0'), - ETRAX_DATA_BUS_B_17 => '0', - ETRAX_DATA_BUS_C => open,--(others => '0'), - ETRAX_DATA_BUS_E => FS_PE(9 downto 8), - DATA_VALID => '0', - ETRAX_BUS_BUSY => '0', - ETRAX_IS_READY_TO_READ => open, - TDC_TCK => open, - TDC_TDI => open, - TDC_TMS => open, - TDC_TRST => open, - TDC_TDO => '0', - TDC_RESET => open, - EXTERNAL_ADDRESS => external_address_i, - EXTERNAL_DATA_OUT => external_data_out_i, - EXTERNAL_DATA_IN => x"ddbbccaa",--external_data_in_i, - EXTERNAL_ACK => external_ack_i, - EXTERNAL_VALID => external_ack_i,--external_valid_i, - EXTERNAL_MODE => external_mode_i, - FPGA_REGISTER_00 => fpga_register_00_i, - FPGA_REGISTER_01 => fpga_register_01_i, - FPGA_REGISTER_02 => fpga_register_02_i, - FPGA_REGISTER_03 => fpga_register_03_i, - FPGA_REGISTER_04 => fpga_register_04_i, - FPGA_REGISTER_05 => fpga_register_05_i, - FPGA_REGISTER_06 => fpga_register_06_i, - FPGA_REGISTER_07 => fpga_register_07_i, - FPGA_REGISTER_08 => fpga_register_08_i, - FPGA_REGISTER_09 => fpga_register_09_i, - FPGA_REGISTER_0A => fpga_register_0A_i, - FPGA_REGISTER_0B => fpga_register_0B_i, - FPGA_REGISTER_0C => fpga_register_0C_i, - FPGA_REGISTER_0D => fpga_register_0D_i, - FPGA_REGISTER_0E => fpga_register_0E_i, - -- EXTERNAL_RESET => open, - LVL2_VALID => '0'); - fpga_register_00_i <= x"0000"& lok_i; - fpga_register_01_i <= hub_debug_i; - fpga_register_02_i <= flexi_pcs_synch_status_i(31 downto 0); - fpga_register_03_i <= flexi_pcs_synch_status_i(63 downto 32); - fpga_register_04_i <= flexi_pcs_synch_status_i(95 downto 64); - - COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i ) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - fpga_register_05_i <= (others => '0'); - elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"1" then - fpga_register_05_i <= fpga_register_05_i + 1; - end if; - end if; - end process COUNT_LVL1_START; - - COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i ) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - fpga_register_08_i <= (others => '0'); - elsif med_dataready_in_i(1) = '1' and med_data_in_i(31 downto 28) = x"1" then - fpga_register_08_i <= fpga_register_08_i + 1; - end if; - end if; - end process COUNT_LVL1_SEND; - - COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i ) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - fpga_register_09_i <= (others => '0'); - elsif med_dataready_in_i(1) = '1' then - fpga_register_09_i <= fpga_register_08_i + 1; - end if; - end if; - end process COUNT_LVL1_SEND; - - COUNT_LVL1_END: process (LVDS_CLK_200P, global_reset_i ) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - fpga_register_07_i <= (others => '0'); - elsif med_dataready_out_i(1) = '1' and med_data_out_i(31 downto 28) = x"1" then - fpga_register_07_i <= fpga_register_07_i + 1; - end if; - end if; - end process COUNT_LVL1_END; - - TX_DIS_g : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate - begin - TX_DIS(synch_fsm_state+1) <= '0'; - end generate; - - TX_DIS_g1 : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate - begin - WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate - TX_DIS(16-not_connected) <= '1'; - end generate WHEN_NOT_ALL_EN; - end generate; - ---------------------------------------------------------------------------- --- setting LED ---------------------------------------------------------------------------- - - --correct this for channels 11-8 - mirrored due to schematics -- also - --adressing of sfps !!! - LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate - begin - lok_i(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16); - end generate LOK_STATUS_DIOD_EN; - - LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate - begin - hub_register_00_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16); - end generate LOK_STATUS_REGISTER_0; - - LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate - begin - hub_register_01_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16+8*16); - end generate LOK_STATUS_REGISTER_1; - - LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate - begin - WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate - lok_i(16-not_connected) <= '1'; - end generate WHEN_NOT_ALL_EN; - end generate LOK_STATUS_DIOD_DIS; - LOK <= lok_i; - IPLL <= '0'; - OPLL <= '0'; - DBAD <= ADO_TTL(11); - DGOOD <= '1'; - DINT <= '0'; - DWAIT <= global_reset_i; - - CV_COUNTERaaa: process (LVDS_CLK_200P, global_reset_i) - begin - if rising_edge(LVDS_CLK_200P) then -- rising clock edge - if global_reset_i = '1' then -- asynchronous reset (active low) - cv_counter <= (others => '0'); - else - cv_counter <= cv_counter + 1; - end if; - end if; - end process CV_COUNTERaaa; - CV_COUNTERaab: process (ref_pclk(0), global_reset_i) - begin - if rising_edge(ref_pclk(0)) then -- rising clock edge - if global_reset_i = '1' then -- asynchronous reset (active low) - cv_countera <= (others => '0'); - else - cv_countera <= cv_countera + 1; - end if; - end if; - end process CV_COUNTERaab; - RT(8) <= cv_counter(23); - RT(9) <= med_read_in_i(0); - RT(16 downto 10) <= flexi_pcs_synch_status_i(7 downto 1); - RT(2) <= flexi_pcs_ref_clk;--cv_counter(0); - RT(1) <= not switch_rx_clk;--ref_pclk(0); - - RT(3) <= LVDS_CLK_200P; - - RT(4) <= rx_k_i(0); - - RT(5) <= med_dataready_out_i(0);--serdes_ref_clk; - RT(6) <= med_data_out_i(0);--serdes_ref_clks; - RT(7) <= med_data_out_i(1);--serdes_ref_lock; - -end hub; - diff --git a/oldfiles/serdes_test/link_test.vhd b/oldfiles/serdes_test/link_test.vhd deleted file mode 100644 index 5b333fe..0000000 --- a/oldfiles/serdes_test/link_test.vhd +++ /dev/null @@ -1,326 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -entity link_test is - - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_OUT : out std_logic_vector(15 downto 0); - VALID_IN : in std_logic; - VALID_OUT : out std_logic; - LINK_DEBUG : out std_logic_vector(31 downto 0); - LINK_INFO : in std_logic_vector(15 downto 0) - ); - -end link_test; - -architecture link_test of link_test is - - component up_down_counter - generic ( - NUMBER_OF_BITS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic; - DOWN_IN : in std_logic); - end component; - - component mdc_dc_lvl1_dpram_rand - port ( - DataInA : in std_logic_vector(7 downto 0); - DataInB : in std_logic_vector(7 downto 0); - AddressA : in std_logic_vector(8 downto 0); - AddressB : in std_logic_vector(8 downto 0); - ClockA : in std_logic; - ClockB : in std_logic; - ClockEnA : in std_logic; - ClockEnB : in std_logic; - WrA : in std_logic; - WrB : in std_logic; - ResetA : in std_logic; - ResetB : in std_logic; - QA : out std_logic_vector(7 downto 0); - QB : out std_logic_vector(7 downto 0)); - end component; - - component mdc_dc_lvl1_dpram_zero - port ( - DataInA : in std_logic_vector(7 downto 0); - DataInB : in std_logic_vector(7 downto 0); - AddressA : in std_logic_vector(8 downto 0); - AddressB : in std_logic_vector(8 downto 0); - ClockA : in std_logic; - ClockB : in std_logic; - ClockEnA : in std_logic; - ClockEnB : in std_logic; - WrA : in std_logic; - WrB : in std_logic; - ResetA : in std_logic; - ResetB : in std_logic; - QA : out std_logic_vector(7 downto 0); - QB : out std_logic_vector(7 downto 0)); - end component; - type TEST_LINK_FSM is (IDLE, TEST1, TEST2, TEST3, TEST4, TRANSMITION_ERROR) ; - signal TEST_LINK_FSM_current, TEST_LINK_FSM_next : TEST_LINK_FSM; - signal wait_for_second_board_counter : std_logic_vector(31 downto 0); - signal enable_sec_board_counter : std_logic; - signal mem_diff : std_logic; - signal mem_check_ok : std_logic; - - signal random_memory_address : std_logic_vector(8 downto 0); - signal random_memory_send : std_logic; - - signal zero_memory_read_address : std_logic_vector(8 downto 0); - signal zero_memory_write_address : std_logic_vector(8 downto 0); - signal zero_memory_read : std_logic; - - signal zero_memory_data_out : std_logic_vector(7 downto 0); - signal rand_memory_data_out : std_logic_vector(7 downto 0); - - signal counter_for_send_en : std_logic_vector(10 downto 0); - - signal rand_memory_data_out_synch : std_logic_vector(7 downto 0); - signal rand_memory_data_out_synch_synch : std_logic_vector(7 downto 0); - signal rand_memory_data_out_synch_synch_synch : std_logic_vector(7 downto 0); - - signal wait_for_data_counter : std_logic_vector(27 downto 0); - signal wait_for_data_en : std_logic; - - signal link_debug_i : std_logic_vector(1 downto 0); - signal wait_for_data_reset : std_logic; - - signal zero_memory_read_synch : std_logic; - signal wait_for_second_board_reset : std_logic; - - -begin - TEST_CLOCK : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - TEST_LINK_FSM_current <= IDLE; - else - TEST_LINK_FSM_current <= TEST_LINK_FSM_next; - end if; - end if; - end process TEST_CLOCK; - FSM_TO_TEST_LINK : process (CLK) - begin - case TEST_LINK_FSM_current is - when IDLE => - link_debug_i <= "01"; - enable_sec_board_counter <= '0'; - mem_check_ok <= '0'; - random_memory_send <= '0'; - wait_for_data_reset <= '1'; - VALID_OUT <= '0'; - wait_for_second_board_reset <= '1'; - if LINK_INFO(0)='1' then - TEST_LINK_FSM_next <= TEST1; - else - TEST_LINK_FSM_next <= IDLE; - end if; - when TEST1 => - link_debug_i <= "10"; - enable_sec_board_counter <= '1'; - mem_check_ok <= '0'; - random_memory_send <= '0'; - VALID_OUT <= '0'; - wait_for_data_reset <= '1'; - wait_for_second_board_reset <= '0'; - if wait_for_second_board_counter(27)='1' then - TEST_LINK_FSM_next <= TEST2; - else - TEST_LINK_FSM_next <= TEST1; - end if; - when TEST2 => - link_debug_i <= "11"; - enable_sec_board_counter <= '0'; - mem_check_ok <= '1'; - random_memory_send <= '1'; - VALID_OUT <= counter_for_send_en(10); - wait_for_data_reset <= '0'; - wait_for_second_board_reset <= '0'; - if (LINK_INFO(1)= '1' or LINK_INFO(2)='1' or mem_diff = '1') and wait_for_data_en = '0' then - TEST_LINK_FSM_next <= IDLE; - else - TEST_LINK_FSM_next <= TEST2; - end if; - when TRANSMITION_ERROR => - link_debug_i <= "00"; - enable_sec_board_counter <= '0'; - mem_check_ok <= '0'; - random_memory_send <= '0'; - wait_for_data_reset <= '1'; - wait_for_second_board_reset <= '0'; - when others => - link_debug_i <= "00"; - enable_sec_board_counter <= '0'; - mem_check_ok <= '0'; - random_memory_send <= '0'; - wait_for_data_reset <= '1'; - wait_for_second_board_reset <= '0'; - TEST_LINK_FSM_next <= IDLE; - end case; - end process FSM_TO_TEST_LINK; - - - WAIT_FOR_SECOND_BOARD: up_down_counter - generic map ( - NUMBER_OF_BITS => 32) - port map ( - CLK => CLK, - RESET => wait_for_second_board_reset, - COUNT_OUT => wait_for_second_board_counter, - UP_IN => enable_sec_board_counter, - DOWN_IN => '0'); - wait_for_data_en <= random_memory_send and (not wait_for_data_counter(27)); - - WAIT_FOR_DATA: up_down_counter - generic map ( - NUMBER_OF_BITS => 28) - port map ( - CLK => CLK, - RESET => wait_for_data_reset, - COUNT_OUT => wait_for_data_counter, - UP_IN => wait_for_data_en, - DOWN_IN => '0'); - - - WRITE_ZERO_MEM_ADDRESS: up_down_counter - generic map ( - NUMBER_OF_BITS => 9) - port map ( - CLK => CLK, - RESET => wait_for_second_board_reset,--RESET, - COUNT_OUT => zero_memory_write_address, - UP_IN => VALID_IN, - DOWN_IN => '0'); - - READ_ZERO_MEM_ADDRESS: up_down_counter - generic map ( - NUMBER_OF_BITS => 9) - port map ( - CLK => CLK, - RESET => wait_for_second_board_reset,--RESET, - COUNT_OUT => zero_memory_read_address, - UP_IN => zero_memory_read, - DOWN_IN => '0'); - - READ_RAND_MEM_ADDRESS: up_down_counter - generic map ( - NUMBER_OF_BITS => 9) - port map ( - CLK => CLK, - RESET => wait_for_second_board_reset,--RESET, - COUNT_OUT => random_memory_address, - UP_IN => random_memory_send, - DOWN_IN => '0'); - - SEND_RAND_MEM_EN: up_down_counter - generic map ( - NUMBER_OF_BITS => 11) - port map ( - CLK => CLK, - RESET => wait_for_second_board_reset,--RESET, - COUNT_OUT => counter_for_send_en, - UP_IN => '1', - DOWN_IN => '0'); - - MEM_RANDOM: mdc_dc_lvl1_dpram_rand - port map ( - DataInA => (others => '0'), - DataInB => (others => '0'), - AddressA => random_memory_address, - AddressB => (others => '0'), - ClockA => CLK, - ClockB => CLK, - ClockEnA => '1', - ClockEnB => '0', - WrA => '0', - WrB => '0', - ResetA => '0', - ResetB => '0', - QA => rand_memory_data_out, - QB => open); - - MEM_ZERO: mdc_dc_lvl1_dpram_zero - port map ( - DataInA => DATA_IN(7 downto 0), - DataInB => (others => '0'), - AddressA => zero_memory_write_address, - AddressB => zero_memory_read_address, - ClockA => CLK, - ClockB => CLK, - ClockEnA => '1', - ClockEnB => '1', - WrA => VALID_IN, - WrB => '0', - ResetA => '0', - ResetB => '0', - QA => open, - QB => zero_memory_data_out); - START_COMPARISON: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1'or TEST_LINK_FSM_current = IDLE then - zero_memory_read <= '0'; - elsif rand_memory_data_out = zero_memory_data_out then - zero_memory_read <= '1'; - else --- zero_memory_read <= '0'; - zero_memory_read <= zero_memory_read; - end if; - end if; - end process START_COMPARISON; - MAKE_COMPARISON: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1'or wait_for_second_board_reset = '1' then - mem_diff <= '1'; - elsif rand_memory_data_out_synch_synch = zero_memory_data_out then - mem_diff <= '0'; - elsif zero_memory_read_synch = '1' and rand_memory_data_out_synch_synch_synch /= zero_memory_data_out then - mem_diff <= '1'; --- mem_diff <= '0'; - end if; - end if; - end process MAKE_COMPARISON; - - SYNCH_DATA: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' or wait_for_second_board_reset = '1' then - rand_memory_data_out_synch_synch_synch <= (others => '0'); - rand_memory_data_out_synch_synch <= (others => '0'); - rand_memory_data_out_synch <= (others => '0'); - zero_memory_read_synch <= '0'; - else - rand_memory_data_out_synch_synch_synch<= rand_memory_data_out_synch_synch; - rand_memory_data_out_synch_synch<= rand_memory_data_out_synch; - rand_memory_data_out_synch <= rand_memory_data_out; - zero_memory_read_synch <= zero_memory_read; - end if; - end if; - end process SYNCH_DATA; - - - LINK_DEBUG(3 downto 0) <= zero_memory_data_out(3 downto 0); - LINK_DEBUG(7 downto 4) <= rand_memory_data_out_synch_synch_synch(3 downto 0); - LINK_DEBUG(9 downto 8) <= link_debug_i; - LINK_DEBUG(10) <= VALID_IN; - LINK_DEBUG(11) <= random_memory_send; - LINK_DEBUG(12) <= zero_memory_read; - LINK_DEBUG(14 downto 13) <= LINK_INFO(2 downto 1); - LINK_DEBUG(15) <= mem_diff; - DATA_OUT <= rand_memory_data_out & rand_memory_data_out; - -end link_test; diff --git a/oldfiles/serdes_test/pcs_for_ecp2m.txt b/oldfiles/serdes_test/pcs_for_ecp2m.txt deleted file mode 100644 index 91ea907..0000000 --- a/oldfiles/serdes_test/pcs_for_ecp2m.txt +++ /dev/null @@ -1,49 +0,0 @@ - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSC quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSC quad to the final design requirements. - -DEVICE_NAME "LFE2M35E" -PROTOCOL "G8B10B" -CH0_MODE "DISABLE" -CH1_MODE "DISABLE" -CH2_MODE "SINGLE" -CH3_MODE "DISABLE" -PLL_SRC "CORE_TXREFCLK" -DATARANGE "MEDHIGH" -CH2_CDR_SRC "CORE_RXREFCLK" -CH2_DATA_WIDTH "16" -CH2_REFCK_MULT "20X" -#REFCLK_RATE 100 -#FPGAINTCLK_RATE 100 -CH2_TDRV_AMP "0" -CH2_TX_PRE "DISABLE" -CH2_RTERM_TX "50" -CH2_RX_EQ "DISABLE" -CH2_RTERM_RX "50" -CH2_RX_DCC "DC" -LOS_THRESHOLD "0" -PLL_TERM "50" -PLL_DCC "DC" -PLL_LOL_SET "0" -CH2_TX_SB "NORMAL" -CH2_RX_SB "NORMAL" -CH2_8B10B "NORMAL" -COMMA_A "1100000101" -COMMA_B "0011111010" -COMMA_M "1111111111" -CH2_COMMA_ALIGN "DYNAMIC" -CH2_CTC_BYP "BYPASS" -CC_MATCH1 "0000000000" -CC_MATCH2 "0000000000" -CC_MATCH3 "0100011100" -CC_MATCH4 "0100011100" -CC_MATCH_MODE "MATCH_4" -CC_MIN_IPG "0" -CCHMARK "4" -CCLMARK "4" -OS_REFCK2CORE "1" -OS_PLLQCLKPORTS "0" -OS_INT_ALL "0" - diff --git a/oldfiles/serdes_test/pcs_for_ecp2m.vhd b/oldfiles/serdes_test/pcs_for_ecp2m.vhd deleted file mode 100644 index ee1ecf9..0000000 --- a/oldfiles/serdes_test/pcs_for_ecp2m.vhd +++ /dev/null @@ -1,2185 +0,0 @@ - - ---synopsys translate_off - -library pcsc_work; -use pcsc_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSC is -GENERIC( - CONFIG_FILE : String := "pcs_for_ecp2m.txt" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); - -end PCSC; - -architecture PCSC_arch of PCSC is - -component PCSC_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - -begin - -PCSC_sim_inst : PCSC_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, - FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, - FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, - FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, - FF_TX_F_CLK => FF_TX_F_CLK, - FF_TX_H_CLK => FF_TX_H_CLK, - FF_TX_Q_CLK => FF_TX_Q_CLK, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - OOB_OUT_0 => OOB_OUT_0, - OOB_OUT_1 => OOB_OUT_1, - OOB_OUT_2 => OOB_OUT_2, - OOB_OUT_3 => OOB_OUT_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7 - ); - -end PCSC_arch; - ---synopsys translate_on - ---synopsys translate_off -library ECP2; -use ECP2.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity pcs_for_ecp2m is - GENERIC (USER_CONFIG_FILE : String := "pcs_for_ecp2m.txt"); - port ( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp2, hdinn2 : in std_logic; - hdoutp2, hdoutn2 : out std_logic; - ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic; - ff_txdata_ch2 : in std_logic_vector (15 downto 0); - ff_rxdata_ch2 : out std_logic_vector (15 downto 0); - ff_tx_k_cntrl_ch2 : in std_logic_vector (1 downto 0); - ff_rx_k_cntrl_ch2 : out std_logic_vector (1 downto 0); - ff_rxfullclk_ch2 : out std_logic; - ff_rxhalfclk_ch2 : out std_logic; - ff_force_disp_ch2 : in std_logic_vector (1 downto 0); - ff_disp_sel_ch2 : in std_logic_vector (1 downto 0); - ff_correct_disp_ch2 : in std_logic_vector (1 downto 0); - ff_disp_err_ch2, ff_cv_ch2 : out std_logic_vector (1 downto 0); - ffc_rrst_ch2 : in std_logic; - ffc_signal_detect_ch2 : in std_logic; - ffc_enable_cgalign_ch2 : in std_logic; - ffc_lane_tx_rst_ch2 : in std_logic; - ffc_lane_rx_rst_ch2 : in std_logic; - ffc_txpwdnb_ch2 : in std_logic; - ffc_rxpwdnb_ch2 : in std_logic; - ffs_rlos_lo_ch2 : out std_logic; - ffs_rlol_ch2 : out std_logic; - oob_out_ch2 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - refck2core : out std_logic; - ffs_plol : out std_logic); - -end pcs_for_ecp2m; - -architecture pcs_for_ecp2m_arch of pcs_for_ecp2m is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; -component PCSC ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_RX_Q_CLK_0 : out std_logic; - FF_RX_Q_CLK_1 : out std_logic; - FF_RX_Q_CLK_2 : out std_logic; - FF_RX_Q_CLK_3 : out std_logic; - FF_TX_F_CLK : out std_logic; - FF_TX_H_CLK : out std_logic; - FF_TX_Q_CLK : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - OOB_OUT_0 : out std_logic; - OOB_OUT_1 : out std_logic; - OOB_OUT_2 : out std_logic; - OOB_OUT_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal fpsc_vlo : std_logic := '0'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSC_INST : PCSC ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - FFC_CK_CORE_TX => core_txrefclk, - FFC_CK_CORE_RX => core_rxrefclk, - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - HDINP0 => fpsc_vlo, - HDINN0 => fpsc_vlo, - HDOUTP0 => open, - HDOUTN0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => fpsc_vlo, - FF_TXI_CLK_0 => fpsc_vlo, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => open, - FF_RX_H_CLK_0 => open, - FF_RX_Q_CLK_0 => open, - FF_TX_D_0_0 => fpsc_vlo, - FF_TX_D_0_1 => fpsc_vlo, - FF_TX_D_0_2 => fpsc_vlo, - FF_TX_D_0_3 => fpsc_vlo, - FF_TX_D_0_4 => fpsc_vlo, - FF_TX_D_0_5 => fpsc_vlo, - FF_TX_D_0_6 => fpsc_vlo, - FF_TX_D_0_7 => fpsc_vlo, - FF_TX_D_0_8 => fpsc_vlo, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => fpsc_vlo, - FF_TX_D_0_11 => fpsc_vlo, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => open, - FF_RX_D_0_1 => open, - FF_RX_D_0_2 => open, - FF_RX_D_0_3 => open, - FF_RX_D_0_4 => open, - FF_RX_D_0_5 => open, - FF_RX_D_0_6 => open, - FF_RX_D_0_7 => open, - FF_RX_D_0_8 => open, - FF_RX_D_0_9 => open, - FF_RX_D_0_10 => open, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - FFC_RRST_0 => fpsc_vlo, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => fpsc_vlo, - FFC_LANE_RX_RST_0 => fpsc_vlo, - FFC_TXPWDNB_0 => fpsc_vlo, - FFC_RXPWDNB_0 => fpsc_vlo, - FFS_RLOS_LO_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_PCIE_CON_0 => open, - FFS_LS_SYNC_STATUS_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_RLOL_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - OOB_OUT_0 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - HDOUTP1 => open, - HDOUTN1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_RX_Q_CLK_1 => open, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_PCIE_CON_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - OOB_OUT_1 => open, - HDINP2 => hdinp2, - HDINN2 => hdinn2, - HDOUTP2 => hdoutp2, - HDOUTN2 => hdoutn2, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => ff_rxiclk_ch2, - FF_TXI_CLK_2 => ff_txiclk_ch2, - FF_EBRD_CLK_2 => ff_ebrd_clk_2, - FF_RX_F_CLK_2 => ff_rxfullclk_ch2, - FF_RX_H_CLK_2 => ff_rxhalfclk_ch2, - FF_RX_Q_CLK_2 => open, - FF_TX_D_2_0 => ff_txdata_ch2(0), - FF_TX_D_2_1 => ff_txdata_ch2(1), - FF_TX_D_2_2 => ff_txdata_ch2(2), - FF_TX_D_2_3 => ff_txdata_ch2(3), - FF_TX_D_2_4 => ff_txdata_ch2(4), - FF_TX_D_2_5 => ff_txdata_ch2(5), - FF_TX_D_2_6 => ff_txdata_ch2(6), - FF_TX_D_2_7 => ff_txdata_ch2(7), - FF_TX_D_2_8 => ff_tx_k_cntrl_ch2(0), - FF_TX_D_2_9 => ff_force_disp_ch2(0), - FF_TX_D_2_10 => ff_disp_sel_ch2(0), - FF_TX_D_2_11 => ff_correct_disp_ch2(0), - FF_TX_D_2_12 => ff_txdata_ch2(8), - FF_TX_D_2_13 => ff_txdata_ch2(9), - FF_TX_D_2_14 => ff_txdata_ch2(10), - FF_TX_D_2_15 => ff_txdata_ch2(11), - FF_TX_D_2_16 => ff_txdata_ch2(12), - FF_TX_D_2_17 => ff_txdata_ch2(13), - FF_TX_D_2_18 => ff_txdata_ch2(14), - FF_TX_D_2_19 => ff_txdata_ch2(15), - FF_TX_D_2_20 => ff_tx_k_cntrl_ch2(1), - FF_TX_D_2_21 => ff_force_disp_ch2(1), - FF_TX_D_2_22 => ff_disp_sel_ch2(1), - FF_TX_D_2_23 => ff_correct_disp_ch2(1), - FF_RX_D_2_0 => ff_rxdata_ch2(0), - FF_RX_D_2_1 => ff_rxdata_ch2(1), - FF_RX_D_2_2 => ff_rxdata_ch2(2), - FF_RX_D_2_3 => ff_rxdata_ch2(3), - FF_RX_D_2_4 => ff_rxdata_ch2(4), - FF_RX_D_2_5 => ff_rxdata_ch2(5), - FF_RX_D_2_6 => ff_rxdata_ch2(6), - FF_RX_D_2_7 => ff_rxdata_ch2(7), - FF_RX_D_2_8 => ff_rx_k_cntrl_ch2(0), - FF_RX_D_2_9 => ff_disp_err_ch2(0), - FF_RX_D_2_10 => ff_cv_ch2(0), - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => ff_rxdata_ch2(8), - FF_RX_D_2_13 => ff_rxdata_ch2(9), - FF_RX_D_2_14 => ff_rxdata_ch2(10), - FF_RX_D_2_15 => ff_rxdata_ch2(11), - FF_RX_D_2_16 => ff_rxdata_ch2(12), - FF_RX_D_2_17 => ff_rxdata_ch2(13), - FF_RX_D_2_18 => ff_rxdata_ch2(14), - FF_RX_D_2_19 => ff_rxdata_ch2(15), - FF_RX_D_2_20 => ff_rx_k_cntrl_ch2(1), - FF_RX_D_2_21 => ff_disp_err_ch2(1), - FF_RX_D_2_22 => ff_cv_ch2(1), - FF_RX_D_2_23 => open, - FFC_RRST_2 => ffc_rrst_ch2, - FFC_SIGNAL_DETECT_2 => ffc_signal_detect_ch2, - FFC_ENABLE_CGALIGN_2 => ffc_enable_cgalign_ch2, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFS_PCIE_DONE_2 => open, - FFS_PCIE_CON_2 => open, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2, - FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2, - FFC_TXPWDNB_2 => ffc_txpwdnb_ch2, - FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2, - FFS_RLOS_LO_2 => ffs_rlos_lo_ch2, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - FFS_RLOL_2 => ffs_rlol_ch2, - OOB_OUT_2 => oob_out_ch2, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - HDOUTP3 => open, - HDOUTN3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_RX_Q_CLK_3 => open, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_PCIE_CON_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - OOB_OUT_3 => open, - SCIWDATA0 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA7 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIRDATA0 => open, - SCIRDATA1 => open, - SCIRDATA2 => open, - SCIRDATA3 => open, - SCIRDATA4 => open, - SCIRDATA5 => open, - SCIRDATA6 => open, - SCIRDATA7 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_MACRO_RST => ffc_macro_rst, - FFC_QUAD_RST => ffc_quad_rst, - FFC_TRST => ffc_trst, - FF_TX_F_CLK => ff_txfullclk, - FF_TX_H_CLK => ff_txhalfclk, - FF_TX_Q_CLK => open, - REFCK2CORE => refck2core, - CIN0 => cin(0), - CIN1 => cin(1), - CIN2 => cin(2), - CIN3 => cin(3), - CIN4 => cin(4), - CIN5 => cin(5), - CIN6 => cin(6), - CIN7 => cin(7), - CIN8 => cin(8), - CIN9 => cin(9), - CIN10 => cin(10), - CIN11 => cin(11), - COUT0 => cout(0), - COUT1 => cout(1), - COUT2 => cout(2), - COUT3 => cout(3), - COUT4 => cout(4), - COUT5 => cout(5), - COUT6 => cout(6), - COUT7 => cout(7), - COUT8 => cout(8), - COUT9 => cout(9), - COUT10 => cout(10), - COUT11 => cout(11), - COUT12 => cout(12), - COUT13 => cout(13), - COUT14 => cout(14), - COUT15 => cout(15), - COUT16 => cout(16), - COUT17 => cout(17), - COUT18 => cout(18), - COUT19 => cout(19), - FFS_PLOL => ffs_plol); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end pcs_for_ecp2m_arch ; diff --git a/oldfiles/serdes_test/rich.vhd b/oldfiles/serdes_test/rich.vhd deleted file mode 100644 index 1b6e6a2..0000000 --- a/oldfiles/serdes_test/rich.vhd +++ /dev/null @@ -1,350 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - - - -entity rich is - port( - CLK40M : in std_logic; - CLK100M_P : in std_logic; - CLK100M_N : in std_logic; - FPGA_LED : out std_logic_vector(4 downto 0); - SD_RXD_P : in std_logic; - SD_RXD_N : in std_logic; - SD_TXD_P : out std_logic; - SD_TXD_N : out std_logic; - SD_MD : inout std_logic_vector(2 downto 0); - SD_TXDIS : out std_logic; - SD_LOS : in std_logic; - SD_TXFAULT : out std_logic; - SD_RATE : out std_logic; - ONEWIRE : inout std_logic; - FPGA_EXP : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture rich of rich is - - component pcs_for_ecp2m - port( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp2 : in std_logic; - hdinn2 : in std_logic; - ff_rxiclk_ch2 : in std_logic; - ff_txiclk_ch2 : in std_logic; - ff_ebrd_clk_2 : in std_logic; - ff_txdata_ch2 : in std_logic_vector(15 downto 0); - ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0); - ff_force_disp_ch2 : in std_logic_vector(1 downto 0); - ff_disp_sel_ch2 : in std_logic_vector(1 downto 0); - ff_correct_disp_ch2 : in std_logic_vector(1 downto 0); - ffc_rrst_ch2 : in std_logic; - ffc_signal_detect_ch2 : in std_logic; - ffc_enable_cgalign_ch2 : in std_logic; - ffc_lane_tx_rst_ch2 : in std_logic; - ffc_lane_rx_rst_ch2 : in std_logic; - ffc_txpwdnb_ch2 : in std_logic; - ffc_rxpwdnb_ch2 : in std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - hdoutp2 : out std_logic; - hdoutn2 : out std_logic; - ff_rxdata_ch2 : out std_logic_vector(15 downto 0); - ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0); - ff_rxfullclk_ch2 : out std_logic; - ff_rxhalfclk_ch2 : out std_logic; - ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0); - ff_cv_ch2 : OUT std_logic_vector(1 downto 0); - ffs_rlos_lo_ch2 : OUT std_logic; - ffs_rlol_ch2 : OUT std_logic; - oob_out_ch2 : OUT std_logic; - ff_txfullclk : OUT std_logic; - ff_txhalfclk : OUT std_logic; - refck2core : OUT std_logic; - ffs_plol : OUT std_logic - ); - END COMPONENT; - - component flexi_PCS_channel_synch - port ( - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic; - RX_CLK : in std_logic; - RESET : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RXD_SYNCH : out std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : in std_logic_vector(15 downto 0); - TXD_SYNCH : out std_logic_vector(15 downto 0); - TX_K : out std_logic_vector(1 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(2 downto 0); - MED_READ_IN : in std_logic); - end component; - - component flexi_PCS_synch - generic ( - HOW_MANY_CHANNELS : positive); - port ( - SYSTEM_CLK : in std_logic; - CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0); - MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0); - MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0); - MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0) - ); - end component; - - component DCS --- synthesis translate_off - --sim - generic ( - DCSMODE : string := "POS"); --- synthesis translate_on - port ( - CLK0 : in std_logic; - CLK1 : in std_logic; - SEL : in std_logic; - DCSOUT : out std_logic); - end component; - - component link_test - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_OUT : out std_logic_vector(15 downto 0); - VALID_IN : in std_logic; - VALID_OUT : out std_logic; - LINK_DEBUG : out std_logic_vector(31 downto 0); - LINK_INFO : in std_logic_vector(15 downto 0)); - end component; - - signal core_txrefclk_i : std_logic; - signal core_rxrefclk_i : std_logic; - signal hdinp2_i : std_logic; - signal hdinn2_i : std_logic; - signal ff_rxiclk_ch2_i : std_logic; - signal ff_txiclk_ch2_i : std_logic; - signal ff_ebrd_clk_2_i : std_logic; - signal ff_txdata_ch2_i : std_logic_vector(15 downto 0); - signal ff_tx_k_cntrl_ch2_i : std_logic_vector(1 downto 0); - signal ff_force_disp_ch2_i : std_logic_vector(1 downto 0); - signal ff_disp_sel_ch2_i : std_logic_vector(1 downto 0); - signal ff_correct_disp_ch2_i : std_logic_vector(1 downto 0); - signal ffc_rrst_ch2_i : std_logic; - signal ffc_signal_detect_ch2_i : std_logic; - signal ffc_enable_cgalign_ch2_i : std_logic; - signal ffc_lane_tx_rst_ch2_i : std_logic; - signal ffc_lane_rx_rst_ch2_i : std_logic; - signal ffc_txpwdnb_ch2_i : std_logic; - signal ffc_rxpwdnb_ch2_i : std_logic; - signal ffc_macro_rst_i : std_logic; - signal ffc_quad_rst_i : std_logic; - signal ffc_trst_i : std_logic; - signal hdoutp2_i : std_logic; - signal hdoutn2_i : std_logic; - signal ff_rxdata_ch2_i : std_logic_vector(15 downto 0); - signal ff_rx_k_cntrl_ch2_i : std_logic_vector(1 downto 0); - signal ff_rxfullclk_ch2_i : std_logic; - signal ff_rxhalfclk_ch2_i : std_logic; - signal ff_disp_err_ch2_i : std_logic_vector(1 downto 0); - signal ff_cv_ch2_i : std_logic_vector(1 downto 0); - signal ffs_rlos_lo_ch2_i : std_logic; - signal ffs_rlol_ch2_i : std_logic; - signal oob_out_ch2_i : std_logic; - signal ff_txfullclk_i : std_logic; - signal ff_txhalfclk_i : std_logic; - signal refck2core_i : std_logic; - signal ffs_plol_i : std_logic; - -- reset - signal global_reset_cnt : std_logic_vector(3 downto 0); - signal global_reset_i : std_logic:='0'; - signal counter : std_logic_vector(31 downto 0); - -- dcs_clock - signal dcs_clk_out : std_logic; - signal not_lock : std_logic; - --synch - signal data_valid_out_i : std_logic; - signal flexi_PCS_status_i : std_logic_vector(15 downto 0); - signal ffc_lane_rx_rst_ch2_start : std_logic; - signal ffc_lane_rx_rst_ch2_resync : std_logic; - --test - signal data_out_i : std_logic_vector(15 downto 0); - signal data_in_i : std_logic_vector(15 downto 0); - signal data_valid_in_i : std_logic; - signal test_link_debug : std_logic_vector(31 downto 0); - signal test_link_info : std_logic_vector(15 downto 0); -begin -- rich - RESET_COUNTER_a : process (CLK40M) - begin - if rising_edge(CLK40M) then - if counter < x"0ffffffe" then - counter <= counter +1; - else - counter <= counter; - end if; - end if; - end process RESET_COUNTER_a; - - ffc_quad_rst_i <= '1' when (counter > x"0000ffff" and counter < x"0001000f") else '0'; - ffc_lane_tx_rst_ch2_i <= '1' when (counter > x"00ffffff" and counter < x"0f00000f") else '0'; - ffc_lane_rx_rst_ch2_start <= '1' when (counter > x"00ffffff" and counter < x"0f00000f") else '0'; - - REF_CLK_SELECT: DCS - -- synthesis translate_off - - generic map (--no_sim-- - DCSMODE => "POS")--no_sim-- - -- synthesis translate_on - port map ( - CLK0 => ff_rxhalfclk_ch2_i, - CLK1 => CLK40M, - SEL => ffs_rlol_ch2_i,--hub_register_0a_i(0),--'0',--switch_rx_clk, - DCSOUT => dcs_clk_out); - - serdes : pcs_for_ecp2m port map( - core_txrefclk => CLK40M, - core_rxrefclk => dcs_clk_out,--CLK40M,--ff_rxhalfclk_ch2_i, - hdinp2 => SD_RXD_P, - hdinn2 => SD_RXD_N, - hdoutp2 => SD_TXD_P, - hdoutn2 => SD_TXD_N, - ff_rxiclk_ch2 => ff_rxhalfclk_ch2_i, - ff_txiclk_ch2 => ff_txhalfclk_i, - ff_ebrd_clk_2 => open,--ff_ebrd_clk_2_i, - ff_txdata_ch2 => ff_txdata_ch2_i, - ff_rxdata_ch2 => ff_rxdata_ch2_i, - ff_tx_k_cntrl_ch2 => ff_tx_k_cntrl_ch2_i, - ff_rx_k_cntrl_ch2 => ff_rx_k_cntrl_ch2_i, - ff_rxfullclk_ch2 => ff_rxfullclk_ch2_i, - ff_rxhalfclk_ch2 => ff_rxhalfclk_ch2_i, - ff_force_disp_ch2 => "00",--ff_force_disp_ch2_i, - ff_disp_sel_ch2 => "00",--ff_disp_sel_ch2_i, - ff_correct_disp_ch2 => ff_correct_disp_ch2_i, - ff_disp_err_ch2 => ff_disp_err_ch2_i, - ff_cv_ch2 => ff_cv_ch2_i, - ffc_rrst_ch2 => '0',--ffc_rrst_ch2_i, - ffc_signal_detect_ch2 => '1',--ffc_signal_detect_ch2_i, - ffc_enable_cgalign_ch2 => '1',--ffc_enable_cgalign_ch2_i, - ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2_i, - ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2_i, - ffc_txpwdnb_ch2 => '1',--ffc_txpwdnb_ch2_i, - ffc_rxpwdnb_ch2 => '1',--ffc_rxpwdnb_ch2_i, - ffs_rlos_lo_ch2 => ffs_rlos_lo_ch2_i, - ffs_rlol_ch2 => ffs_rlol_ch2_i, - oob_out_ch2 => oob_out_ch2_i, - ffc_macro_rst => '0',--ffc_macro_rst_i, - ffc_quad_rst => global_reset_i,--ffc_quad_rst_i, - ffc_trst => '0',--ffc_trst_i, - ff_txfullclk => ff_txfullclk_i, - ff_txhalfclk => ff_txhalfclk_i, - refck2core => refck2core_i, - ffs_plol => ffs_plol_i - ); - ffc_lane_rx_rst_ch2_i <= ffc_lane_rx_rst_ch2_resync or ffc_lane_rx_rst_ch2_start; - - SYNCH: flexi_PCS_channel_synch - port map ( - SYSTEM_CLK => CLK40M, - TX_CLK => ff_txhalfclk_i, - RX_CLK => ff_rxhalfclk_ch2_i, - RESET => global_reset_i, - RXD => ff_rxdata_ch2_i, - RXD_SYNCH => data_in_i, - RX_K => ff_rx_k_cntrl_ch2_i, - RX_RST => ffc_lane_rx_rst_ch2_resync, - CV => ff_cv_ch2_i, - TXD => data_out_i, - TXD_SYNCH => ff_txdata_ch2_i, - TX_K => ff_tx_k_cntrl_ch2_i, - DATA_VALID_IN => data_valid_in_i, - DATA_VALID_OUT => data_valid_out_i, - FLEXI_PCS_STATUS => flexi_pcs_status_i, - MED_PACKET_NUM_OUT => open, - MED_ERROR_OUT => open, - MED_READ_IN => '1'); - - test_link_info(2 downto 0) <= ff_cv_ch2_i & flexi_pcs_status_i(2); - - LINK_TETS_INST: link_test - port map ( - CLK => CLK40M, - RESET => global_reset_i, - DATA_IN => data_in_i, - DATA_OUT => data_out_i, - VALID_IN => data_valid_out_i, - VALID_OUT => data_valid_in_i, - LINK_DEBUG => test_link_debug, - LINK_INFO => test_link_info); - - - - GLOBAL_RESET: process(CLK40M,global_reset_cnt,global_reset_i) - begin - if rising_edge(CLK40M) then - if global_reset_cnt < x"e" or global_reset_cnt =x"f" then - global_reset_cnt <= global_reset_cnt + 1; - global_reset_i <= '1'; - elsif global_reset_cnt = x"e" then - global_reset_i <= '0'; - global_reset_cnt <= x"e"; - else - global_reset_i <= '0'; - global_reset_cnt <= global_reset_cnt; - end if; - end if; - end process GLOBAL_RESET; - --- ff_tx_k_cntrl_ch2_i <= "10"; --- ff_txdata_ch2_i <= x"bcc5"; - FPGA_LED(4 downto 1) <= "1010"; - FPGA_LED(0) <= not flexi_pcs_status_i(2); - - FPGA_EXP <= test_link_debug(15 downto 0); - --- FPGA_EXP(0) <= CLK40M; --- FPGA_EXP(1) <= ff_rxhalfclk_ch2_i; --- FPGA_EXP(2) <= dcs_clk_out; --- FPGA_EXP(3) <= ff_cv_ch2_i(0); --- FPGA_EXP(4) <= ff_cv_ch2_i(1); --- FPGA_EXP(5) <= ff_rx_k_cntrl_ch2_i(0); --- FPGA_EXP(6) <= ff_rx_k_cntrl_ch2_i(1); --- FPGA_EXP(7) <= ff_disp_err_ch2_i(0); --- FPGA_EXP(8) <= ff_disp_err_ch2_i(1); --- FPGA_EXP(9) <= ffs_rlos_lo_ch2_i; --- FPGA_EXP(10)<= ffs_rlol_ch2_i; --- FPGA_EXP(11)<= global_reset_i; --- FPGA_EXP(12)<= ffs_plol_i; --- FPGA_EXP(13) <= not flexi_pcs_status_i(2); --- FPGA_EXP(14) <= ffc_lane_rx_rst_ch2_i; - -end rich; diff --git a/oldfiles/serdes_test/serdes_fpga_ref_clk.txt b/oldfiles/serdes_test/serdes_fpga_ref_clk.txt deleted file mode 100644 index c664b6f..0000000 --- a/oldfiles/serdes_test/serdes_fpga_ref_clk.txt +++ /dev/null @@ -1,61 +0,0 @@ - - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCS quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCS quad to the final design requirements. -# channel_0 is in "8b10b" mode -# channel_1 is in "8b10b" mode -# channel_2 is in "8b10b" mode -# channel_3 is in "8b10b" mode - -ch0 13 03 # Powerup Channel -ch0 00 00 -ch1 13 03 # Powerup Channel -ch1 00 00 -ch2 13 03 # Powerup Channel -ch2 00 00 -ch3 13 03 # Powerup Channel -ch3 00 00 -quad 00 00 -quad 01 E4 -quad 28 40 # Reference clock multiplier -quad 29 11 # FPGA sourced refclk -quad 02 00 # ref_pclk source is ch0 -quad 04 00 # MCA enable 4 channels - -quad 18 10 # 8b10b Mode -quad 14 FF # Word Alignment Mask -quad 15 7c # +ve K -quad 16 b6 # -ve K -quad 17 36 - -quad 19 8C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit - -#quad 1e 01 #SOP EOP only 1 word 24.04.2008 -#quad 1f ff -#quad 20 7c -#quad 21 7c -#quad 22 5 -#quad 23 7c -#quad 24 7c -#quad 25 5 - - -ch0 14 90 # 16% pre-emphasis -ch0 15 10 # +6dB equalization -ch1 14 90 # 16% pre-emphasis -ch1 15 10 # +6dB equalization -ch2 14 90 # 16% pre-emphasis -ch2 15 10 # +6dB equalization -ch3 14 90 # 16% pre-emphasis -ch3 15 10 # +6dB equalization - -# These lines must appear last in the autoconfig file. These lines apply the correct -# reset sequence to the PCS block upon bitstream configuration -quad 41 00 # de-assert serdes_rst -quad 40 ff # assert datapath reset for all channels -quad 40 00 # de-assert datapath reset for all channels - - - diff --git a/oldfiles/serdes_test/up_down_counter.vhd b/oldfiles/serdes_test/up_down_counter.vhd deleted file mode 100644 index 7a02ead..0000000 --- a/oldfiles/serdes_test/up_down_counter.vhd +++ /dev/null @@ -1,44 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity up_down_counter is - - generic ( - NUMBER_OF_BITS : positive - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic; - DOWN_IN : in std_logic - ); - -end up_down_counter; - -architecture up_down_counter of up_down_counter is - -signal counter: std_logic_vector (NUMBER_OF_BITS-1 downto 0); - -begin - - COUNTER_PROC : process (CLK, RESET, UP_IN, DOWN_IN) - begin - if rising_edge(clk) then - if RESET = '1' then - counter <= (others => '0'); - elsif UP_IN = '1' and DOWN_IN = '0' then - counter <= counter + 1; - elsif UP_IN = '0' and DOWN_IN = '1' then - counter <= counter - 1; - else - counter <= counter; - end if; - end if; - end process COUNTER_PROC; - - COUNT_OUT <= counter; - -end up_down_counter; diff --git a/oldfiles/sfp_interface.vhd b/oldfiles/sfp_interface.vhd deleted file mode 100644 index 3577341..0000000 --- a/oldfiles/sfp_interface.vhd +++ /dev/null @@ -1,544 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; - -entity Sfp_Interface is - generic ( - I2C_SPEED : std_logic_vector(15 downto 0) := x"0200" ------------------------------------------------------------------------------------- --- I2C_SPEED = 100 MHz / working frequency | --- max working frequency 400 kHz | --- Example: for 400 kHz working frequency => I2C_SPEED = FPGA freq / Working freq | --- I2C_SPEED = 100MHz / 400kHz | --- I2C_SPEED = 250 = x"FA" | ------------------------------------------------------------------------------------- - ); - port( - CLK_IN : in std_logic; -- System clock - RST_IN : in std_logic; -- System reset --- host side - START_PULSE : in std_logic; -- System start pulse - DEVICE_ADDRESS : in std_logic_vector(7 downto 0) :=x"06"; -- Device address input: x"06" for SFP_Interface - DATA_OUT : out std_logic_vector(15 downto 0); -- Data output from optical transmitter - READ_DONE : out std_logic; -- Reading process done - SFP_ADDRESS : in std_logic_vector(7 downto 0); -- SFP address ---------------------------------------------------------------- --- SFP_ADDRESS values: | ---------------------------------------------------------------| --- x"60" => Internally measured module temperature | --- x"66" => Measured TX optical output power | --- x"68" => Measured RX optical input power | ---------------------------------------------------------------- --- optical transceiver side - SCL : out std_logic_vector(15 downto 0); -- I2C Serial clock I/O - SDA : inout std_logic_vector(15 downto 0); -- I2C Serial data I/O - DEBUG : out std_logic_vector(31 downto 0) - ); - -end Sfp_Interface; -------------------------------------------------------------------------------- - -architecture behavioral of Sfp_Interface is -------------------------------------------------------------------------------- --- Internal Lines -------------------------------------------------------------------------------- - signal scl_int : std_logic := '1'; - signal sda_int : std_logic := '1'; - signal sda_int_mem : std_logic := '1'; - signal byte_2_send : std_logic_vector(7 downto 0) := x"00"; - signal byte_2_send_mem : std_logic_vector(7 downto 0) := x"00"; - signal byte_2_read : std_logic_vector(15 downto 0) := x"0000"; - signal data_out_int : std_logic_vector(15 downto 0) := x"0000"; - signal data_out_int_mem : std_logic_vector(15 downto 0) := x"0000"; - signal bit_read : std_logic := '0'; - signal bit_read_mem : std_logic := '0'; - signal read_done_int : std_logic := '0'; --- - signal en_reset_cnt : std_logic := '0'; - signal stop_reset_cnt : std_logic := '0'; - signal rst_reset_cnt : std_logic := '0'; - signal reset_cnt : std_logic_vector(3 downto 0) := "0001"; - signal reset_done : std_logic := '0'; - signal reset_done_mem : std_logic := '0'; --- - signal en_bit_cnt : std_logic := '0'; - signal stop_bit_cnt : std_logic := '0'; - signal rst_bit_cnt : std_logic := '0'; - signal bit_cnt : std_logic_vector(5 downto 0) := "000000"; --- - signal stop_fre_cnt : std_logic := '0'; - signal rst_fre_cnt : std_logic := '0'; - signal fre_cnt : std_logic_vector(15 downto 0) := x"0000"; --- - signal en_shift_reg : std_logic := '0'; - signal en_FSM : std_logic := '0'; - signal sfp_address_i : std_logic_vector(7 downto 0) := x"00"; - signal device_address_i : std_logic_vector(7 downto 0) := x"06"; - signal start_pulse_i : std_logic := '0'; --- - signal debug_signal : std_logic_vector(31 downto 0) := x"00000000"; - signal select_line : integer range 0 to 15; -------------------------------------------------------------------------------- - type STATES is (IDLE, RESET_A, RESET_B, RESET_C, RESET_D, START_A, START_B, - START_C, START_D, STOP_A, STOP_B, STOP_C, STOP_D, SEND_BYTE_A, - SEND_BYTE_B, SEND_BYTE_C, SEND_BYTE_D, READ_BYTE_A, READ_BYTE_B, - READ_BYTE_C, READ_BYTE_D, SEND_ACK_A, SEND_ACK_B, SEND_ACK_C, - SEND_ACK_D, READ_ACK_A, READ_ACK_B, READ_ACK_C, READ_ACK_D); - signal STATE_CURRENT : STATES; - signal STATE_NEXT : STATES; -------------------------------------------------------------------------------- - - -------------------------------------------------------------------------------- -begin - stop_reset_cnt <= rst_in or rst_reset_cnt; - stop_bit_cnt <= rst_in or rst_bit_cnt; - stop_fre_cnt <= rst_in or rst_fre_cnt; - select_line <= to_integer(unsigned(DEVICE_ADDRESS(3 downto 0))); - - proc_counters : process begin - wait until rising_edge(CLK_IN); - if stop_fre_cnt = '1' then - fre_cnt <= x"0000"; - else - fre_cnt <= std_logic_vector(unsigned(fre_cnt)+1); - end if; - - if stop_bit_cnt = '1' then - bit_cnt <= "000000"; - elsif en_bit_cnt = '1' then - bit_cnt <= std_logic_vector(unsigned(bit_cnt)+1); - end if; - - if stop_reset_cnt = '1' then - reset_cnt <= "0000"; - elsif en_reset_cnt = '1' then - reset_cnt <= std_logic_vector(unsigned(reset_cnt)+1); - end if; - - - end process; - - Frequency_Division : process (CLK_IN, RST_IN, fre_cnt) - begin - if rising_edge(CLK_IN) then - if RST_IN = '1' then - en_FSM <= '0'; - rst_fre_cnt <= '0'; - elsif fre_cnt = I2C_SPEED then - en_FSM <= '1'; - rst_fre_cnt <= '1'; - else - en_FSM <= '0'; - rst_fre_cnt <= '0'; - end if; - end if; - end process Frequency_Division; -------------------------------------------------------------------------------- - Address_Assingment : process (CLK_IN, RST_IN, START_PULSE) - begin - if rising_edge(CLK_IN) then - if RST_IN = '1' then - sfp_address_i <= x"00"; - device_address_i <= x"00"; - start_pulse_i <= '0'; - elsif START_PULSE = '1' then - sfp_address_i <= SFP_ADDRESS; - device_address_i <= DEVICE_ADDRESS; - start_pulse_i <= START_PULSE; - else - start_pulse_i <= '0'; - end if; - end if; - end process Address_Assingment; -------------------------------------------------------------------------------- - Syncronising : process (CLK_IN, RST_IN) - begin - if rising_edge(CLK_IN) then - if RST_IN = '1' then - STATE_CURRENT <= IDLE; - DATA_OUT <= x"0000"; - READ_DONE <= '0'; - data_out_int_mem <= x"0000"; - byte_2_send_mem <= x"00"; - reset_done_mem <= '0'; - bit_read_mem <= '0'; - SCL <= (others => 'Z'); - SDA <= (others => 'Z'); - sda_int_mem <= '1'; - DEBUG <= x"00000000"; - else - STATE_CURRENT <= STATE_NEXT; - DATA_OUT <= data_out_int; - READ_DONE <= read_done_int; - data_out_int_mem <= data_out_int; - byte_2_send_mem <= byte_2_send; - reset_done_mem <= reset_done; - sda_int_mem <= sda_int; - bit_read_mem <= bit_read; - SCL <= (others => scl_int); - SDA <= (others => sda_int); - DEBUG <= debug_signal; - end if; - end if; - end process Syncronising; -------------------------------------------------------------------------------- - Shift_Register : process (CLK_IN, RST_IN, en_shift_reg) - begin - if rising_edge(CLK_IN) then - if RST_IN = '1' then - byte_2_read <= x"0000"; - elsif en_shift_reg = '1' then - byte_2_read <= byte_2_read(14 downto 0) & bit_read; - end if; - end if; - end process Shift_Register; -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- --- The State Machine -------------------------------------------------------------------------------- - State_Decoder : process (start_pulse_i, device_address_i, STATE_CURRENT, - reset_cnt, reset_done, reset_done_mem, bit_cnt, SDA, - byte_2_send_mem, byte_2_read, data_out_int_mem, - en_FSM, sda_int_mem, sfp_address_i, bit_read_mem) - begin - en_reset_cnt <= '0'; - rst_reset_cnt <= '0'; - en_bit_cnt <= '0'; - rst_bit_cnt <= '0'; - en_shift_reg <= '0'; - sda_int <= 'Z'; - scl_int <= 'Z'; - byte_2_send <= byte_2_send_mem; - data_out_int <= data_out_int_mem; - reset_done <= reset_done_mem; - bit_read <= bit_read_mem; - read_done_int <= '0'; - STATE_NEXT <= STATE_CURRENT; - - case (STATE_CURRENT) is ---IDLE - when IDLE => - if start_pulse_i = '1' and reset_done = '0' then - STATE_NEXT <= RESET_C; - elsif start_pulse_i = '1' and reset_done = '1' then - STATE_NEXT <= START_A; - else - STATE_NEXT <= IDLE; - end if; - debug_signal <= x"00000001"; ---RESET - when RESET_A => - scl_int <= '0'; - sda_int <= '1'; - if en_FSM = '1' then - STATE_NEXT <= RESET_B; - end if; - debug_signal <= x"00000002"; --- - when RESET_B => - scl_int <= '0'; - sda_int <= '1'; - if reset_cnt = "1000" and en_FSM = '1' then - STATE_NEXT <= START_C; - rst_reset_cnt <= '1'; - reset_done <= '1'; - elsif en_FSM = '1' then - STATE_NEXT <= RESET_C; - en_reset_cnt <= '1'; - end if; - debug_signal <= x"00000003"; --- - when RESET_C => - scl_int <= '1'; - sda_int <= '1'; - if en_FSM = '1' then - STATE_NEXT <= RESET_D; - end if; - debug_signal <= x"00000004"; --- - when RESET_D => - scl_int <= '1'; - sda_int <= '1'; - if en_FSM = '1' then - STATE_NEXT <= RESET_A; - end if; - debug_signal <= x"00000005"; ---START - when START_A => - scl_int <= '0'; - sda_int <= '1'; - if en_FSM = '1' then - STATE_NEXT <= START_B; - end if; - debug_signal <= x"00000006"; --- - when START_B => - scl_int <= '0'; - sda_int <= '1'; - if en_FSM = '1' then - STATE_NEXT <= START_C; - end if; - debug_signal <= x"00000007"; --- - when START_C => - scl_int <= '1'; - sda_int <= '1'; - if en_FSM = '1' then - STATE_NEXT <= START_D; - end if; - debug_signal <= x"00000008"; --- - when START_D => - scl_int <= '1'; - sda_int <= '0'; - if bit_cnt = "010011" and en_FSM = '1' then - byte_2_send <= x"A3"; - STATE_NEXT <= SEND_BYTE_A; - en_bit_cnt <= '1'; - elsif bit_cnt = "000000" and en_FSM = '1' then - byte_2_send <= x"A2"; - STATE_NEXT <= SEND_BYTE_A; - en_bit_cnt <= '1'; - elsif en_FSM = '0' then - STATE_NEXT <= STATE_CURRENT; - else - byte_2_send <= x"00"; - STATE_NEXT <= IDLE; - end if; - debug_signal <= x"00000009"; ---STOP - when STOP_A => - scl_int <= '0'; - sda_int <= '0'; - if en_FSM = '1' then - STATE_NEXT <= STOP_B; - end if; - debug_signal <= x"0000000a"; --- - when STOP_B => - scl_int <= '0'; - sda_int <= '0'; - if en_FSM = '1' then - STATE_NEXT <= STOP_C; - end if; - debug_signal <= x"0000000b"; --- - when STOP_C => - scl_int <= '1'; - sda_int <= '0'; - if en_FSM = '1' then - STATE_NEXT <= STOP_D; - end if; - debug_signal <= x"0000000c"; --- - when STOP_D => - scl_int <= '1'; - sda_int <= '1'; - rst_bit_cnt <= '1'; - if en_FSM = '1' then - STATE_NEXT <= IDLE; - end if; - debug_signal <= x"0000000d"; ---SEND_BYTE - when SEND_BYTE_A => - scl_int <= '0'; - sda_int <= byte_2_send(7); - if en_FSM = '1' then - STATE_NEXT <= SEND_BYTE_B; - end if; - debug_signal <= x"0000000e"; --- - when SEND_BYTE_B => - scl_int <= '0'; - sda_int <= byte_2_send(7); - if en_FSM = '1' then - STATE_NEXT <= SEND_BYTE_C; - end if; - debug_signal <= x"0000000f"; --- - when SEND_BYTE_C => - scl_int <= '1'; - sda_int <= byte_2_send(7); - if en_FSM = '1' then - STATE_NEXT <= SEND_BYTE_D; - end if; - debug_signal <= x"00000010"; --- - when SEND_BYTE_D => - scl_int <= '1'; - sda_int <= byte_2_send(7); - if (bit_cnt = "001000" or bit_cnt = "010001" or bit_cnt = "011011") and en_FSM = '1' then - STATE_NEXT <= READ_ACK_A; - byte_2_send <= byte_2_send_mem(6 downto 0) & byte_2_send_mem(7); - en_bit_cnt <= '1'; - en_shift_reg <= '1'; - elsif en_FSM = '1' then - STATE_NEXT <= SEND_BYTE_A; - byte_2_send <= byte_2_send_mem(6 downto 0) & byte_2_send_mem(7); - en_bit_cnt <= '1'; - en_shift_reg <= '1'; - else - STATE_NEXT <= STATE_CURRENT; - end if; - debug_signal <= x"00000011"; ---READ_BYTE - when READ_BYTE_A => - scl_int <= '0'; - if en_FSM = '1' then - STATE_NEXT <= READ_BYTE_B; - end if; - debug_signal <= x"00000012"; --- - when READ_BYTE_B => - scl_int <= '0'; - if en_FSM = '1' then - STATE_NEXT <= READ_BYTE_C; - end if; - debug_signal <= x"00000013"; --- - when READ_BYTE_C => - scl_int <= '1'; - bit_read <= SDA(select_line); - if en_FSM = '1' then - STATE_NEXT <= READ_BYTE_D; - end if; - debug_signal <= x"00000014"; --- - when READ_BYTE_D => - scl_int <= '1'; - if (bit_cnt = "100100" or bit_cnt = "101100") and en_FSM = '1' then - STATE_NEXT <= SEND_ACK_A; - en_bit_cnt <= '1'; - en_shift_reg <= '1'; - elsif en_FSM = '1' then - STATE_NEXT <= READ_BYTE_A; - en_bit_cnt <= '1'; - en_shift_reg <= '1'; - else - STATE_NEXT <= STATE_CURRENT; - end if; - debug_signal <= x"00000015"; ---SEND_ACK - when SEND_ACK_A => - scl_int <= '0'; - if bit_cnt = "101101" then - sda_int <= '1'; - elsif bit_cnt = "100101" then - sda_int <= '0'; - else - sda_int <= 'X'; - end if; - if en_FSM = '1' then - STATE_NEXT <= SEND_ACK_B; - end if; - debug_signal <= x"00000016"; --- - when SEND_ACK_B => - scl_int <= '0'; - if bit_cnt = "101101" then - sda_int <= '1'; - elsif bit_cnt = "100101" then - sda_int <= '0'; - else - sda_int <= 'X'; - end if; - if en_FSM = '1' then - STATE_NEXT <= SEND_ACK_C; - end if; - debug_signal <= x"00000017"; --- - when SEND_ACK_C => - scl_int <= '1'; - if bit_cnt = "101101" then - sda_int <= '1'; - elsif bit_cnt = "100101" then - sda_int <= '0'; - else - sda_int <= 'X'; - end if; - if en_FSM = '1' then - STATE_NEXT <= SEND_ACK_D; - end if; - debug_signal <= x"00000018"; --- - when SEND_ACK_D => - scl_int <= '1'; - if bit_cnt = "101101" and en_FSM = '1' then - sda_int <= '1'; - STATE_NEXT <= STOP_A; - data_out_int <= byte_2_read; - read_done_int <= '1'; - elsif bit_cnt = "100101" and en_FSM = '1' then - sda_int <= '0'; - STATE_NEXT <= READ_BYTE_A; - elsif en_FSM = '0' then - sda_int <= sda_int_mem; - STATE_NEXT <= STATE_CURRENT; - else - sda_int <= 'X'; - STATE_NEXT <= IDLE; - end if; - debug_signal <= x"00000019"; ---READ_ACK - when READ_ACK_A => - scl_int <= '0'; - if en_FSM = '1' then - STATE_NEXT <= READ_ACK_B; - end if; - debug_signal <= x"0000001a"; --- - when READ_ACK_B => - scl_int <= '0'; - if en_FSM = '1' then - STATE_NEXT <= READ_ACK_C; - end if; - debug_signal <= x"0000001b"; --- - when READ_ACK_C => - scl_int <= '1'; - bit_read <= SDA(select_line); - if en_FSM = '1' then - STATE_NEXT <= READ_ACK_D; - end if; - debug_signal <= x"0000001c"; --- - when READ_ACK_D => - scl_int <= '1'; - if bit_read = '0' and bit_cnt = "001001" and en_FSM = '1' then - STATE_NEXT <= SEND_BYTE_A; - byte_2_send <= sfp_address_i(7 downto 0); - en_bit_cnt <= '1'; - elsif bit_read = '0' and bit_cnt = "010010" and en_FSM = '1' then - STATE_NEXT <= START_A; - en_bit_cnt <= '1'; - elsif bit_read = '0' and bit_cnt = "011100" and en_FSM = '1' then - STATE_NEXT <= READ_BYTE_A; - en_bit_cnt <= '1'; - elsif bit_read = '1' and en_FSM = '1' then - STATE_NEXT <= STOP_A; - en_bit_cnt <= '1'; - elsif en_FSM = '0' then - STATE_NEXT <= STATE_CURRENT; - else - STATE_NEXT <= IDLE; - end if; - debug_signal <= x"0000001d"; ---OTHERS - when others => - scl_int <= '1'; - sda_int <= '1'; - byte_2_send <= x"00"; - STATE_NEXT <= IDLE; - debug_signal <= x"0000001e"; - - end case; -end process State_Decoder; -------------------------------------------------------------------------------- - -end behavioral; diff --git a/oldfiles/sram_is61.vhd b/oldfiles/sram_is61.vhd deleted file mode 100644 index e9a3018..0000000 --- a/oldfiles/sram_is61.vhd +++ /dev/null @@ -1,169 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; - -entity sram_is61 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - RAM_CLK : out std_logic; - RAM_DATA : inout std_logic_vector(17 downto 0); - RAM_ADDR : out std_logic_vector(19 downto 0); - RAM_ADVN : out std_logic; - RAM_ADSCN : out std_logic; - RAM_ADSPN : out std_logic; - RAM_GWN : out std_logic; - RAM_CEN : out std_logic; - RAM_OEN : out std_logic; - - INT_DATA_IN : in std_logic_vector(17 downto 0); - INT_ADDR_IN : in std_logic_vector(19 downto 0); - INT_DATA_OUT : out std_logic_vector(17 downto 0); - INT_WRITE_EN : in std_logic; - INT_BURST_WRITE_EN : in std_logic; - INT_READ_EN : in std_logic; - INT_BURST_READ_EN : in std_logic; - INT_BUSY_OUT : out std_logic; - INT_VALID_OUT : out std_logic; - - STAT_DEBUG : out std_logic_vector(31 downto 0); - ); -end entity; - --- write_en is always followed by two or more clock cycles busy time --- up to four burst_write might come in subsequent clock cycles, then several cycles busy followe --- if burst_write goes low after the first, 2nd or 3rd clock cycle, the burst cycle is finished. --- start of a burst cycle is always with lower two address bits = 0. --- address is read only once during burst cycle - --- pulse on read_en will give one data word from ram, thus one valid --- pulse on burst_read_en will read four words from ram, thus four consecutive valids --- user must be able to read offered data, no waitstates are possible - --- after falling edge of busy signal the next access can be started immediately - - - -architecture sram_is61_arch of sram_is61 is - -component ddr_off - port (Clk: in std_logic; Data: in std_logic_vector(1 downto 0); - Q: out std_logic_vector(0 downto 0)); -end component; - - - - type state_t is (IDLE, ); - signal current_state : state_t; - signal next_state : state_t; - - signal next_oe : std_logic; -- output enable - signal next_ce : std_logic; -- chip enable - signal next_gw : std_logic; -- write enable - signal next_adsp : std_logic; -- address register enable - signal next_adsc : std_logic; -- address register enable - signal next_adv : std_logic; -- address advance - - signal reg_oen : std_logic; - signal reg_cen : std_logic; - signal reg_gwn : std_logic; - signal reg_adspn : std_logic; - signal reg_adscn : std_logic; - signal reg_advn : std_logic; - signal ram_clock : std_logic; - signal next_ram_data : std_logic_vector(17 downto 0); - signal reg_ram_data : std_logic_vector(17 downto 0); - signal reg_ram_data_in : std_logic_vector(17 dowtno 0); - - signal last_oe : std_logic; - signal current_oe : std_logic; - -begin - -RAM_CEN <= reg_cen; -RAM_OEN <= reg_oen; -RAM_GWN <= reg_gwn; -RAM_ADSPN <= reg_adspn; -RAM_ADSCN <= reg_adscn; -RAM_ADVN <= reg_advn; -RAM_CLK <= ram_clock; - - THE_RAM_CLOCK : ddr_off - port map ( - Clk => CLK, - Data(1 downto 0) => "01", - Q(0) => ram_clock - ); - - - THE_DATA_OUTPUT_PROC : process(last_oe, reg_ram_data) - begin - if last_oe = '1' then - RAM_DATA <= (others => 'Z'); - else - RAM_DATA <= reg_ram_data; - end if; - end process; - - - THE_DATA_INPUT_SYNC : process(CLK) - begin - if rising_edge(CLK) then - reg_ram_data_in <= RAM_DATA; - end if; - end process; - - - THE_OUTPUT_SYNC : process(CLK) - begin - if rising_edge(CLK) then - reg_oen <= not next_oe; - reg_cen <= not next_ce; - reg_gwn <= not next_gw; - reg_adspn <= not next_adsp; - reg_adscn <= not next_adsc; - reg_advn <= not next_adv; - end if; - end process; - - - - THE_FSM_SYNC : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_state <= IDLE; - else - current_state <= next_state; - current_oe <= next_oe; - last_oe <= current_oe; - end if; - end if; - end process; - - THE_MAIN_FSM : process(current_state) - begin - next_state <= current_state; - next_oe <= '0'; - next_ce <= not RESET; - next_gw <= '0'; - next_adsp <= '0'; - next_adsc <= '0'; - next_adv <= '0'; - next_ram_data <= reg_ram_data; - - case current_state is - when IDLE => - end case; - end process; - - - - - -end architecture; \ No newline at end of file diff --git a/oldfiles/timing/api_timing.tex b/oldfiles/timing/api_timing.tex deleted file mode 100644 index a058277..0000000 --- a/oldfiles/timing/api_timing.tex +++ /dev/null @@ -1,210 +0,0 @@ -\documentstyle[german,timing,12pt,a4wide]{article} -\pagestyle{empty} -\begin{document} - -\begin{timing}[2s]{4cm} -\tin{1}{FIFO\_FULL\_OUT} -\tin{2}{DATA\_IN} -\tin{3}{WRITE\_IN} -\tin{4}{SEND\_IN} -\tin{5}{RUN\_OUT} -\til{1}{ -%..xxx...xxx...xxx...xxx... -LLLLLLLLLHHHHHHHHHLLLLLLLLL} -\til{2}{ -ZZZVVVXVVXVVVVVVVVVVVVVVXVV} -\tnote{2}{3.7}{D1} -\tnote{2}{6.7}{D2} -\tnote{2}{9.7}{D3} -\tnote{2}{24.7}{D3} -\til{3}{ -LLLHHHHHHHHHLLLLLLLLLHHHHHH} -\til{4}{ -LLLLLLLLLLLLHHHHHHHHHHHHHHH} -\til{5}{ -LLLLLLLLLLLLLLLHHHHHHHHHHHH} -%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status} -%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status} -\sline{0.5}{0}{5} -\sline{0.5}{3}{5} -\sline{0.5}{6}{5} -\sline{0.5}{9}{5} -\sline{0.5}{12}{5} -\sline{0.5}{15}{5} -\sline{0.5}{18}{5} -\sline{0.5}{21}{5} -\sline{0.5}{24}{5} -\sline{0.5}{27}{5} -\end{timing} - -%Early pre-fill and the starting phase of the channel master. This also shows -%the behaviour of a released transfer: During the FIFO\_FULL the master -%releases the writing, and after the FIFO\_FULL is pulled down it takes 2 clock -%cycles after the new data word can be written - -\newpage - -\begin{timing}[2s]{4cm} -\tin{1}{FIFO\_FULL\_OUT} -\tin{2}{DATA\_IN} -\tin{3}{WRITE\_IN} -\til{1}{ -%..xxx...xxx...xxx...xxx... -LLLLLLLLLHHHHHHHHHLLLLLLLLLHHHLLLLLL} -\til{2}{ -ZZZVVVXVVXVVVVVVVVVVVXVVXVVXVVVVVXVV} -\tnote{2}{3.7}{D1} -\tnote{2}{6.7}{D2} -\tnote{2}{9.7}{D3} -\tnote{2}{21.7}{D3} -\tnote{2}{24.7}{D4} -\tnote{2}{27.7}{D5} -\tnote{2}{33.7}{D6} -\til{3}{ -LLLHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH} -\sline{0.5}{0}{3} -\sline{0.5}{3}{3} -\sline{0.5}{6}{3} -\sline{0.5}{9}{3} -\sline{0.5}{12}{3} -\sline{0.5}{15}{3} -\sline{0.5}{18}{3} -\sline{0.5}{21}{3} -\sline{0.5}{24}{3} -\sline{0.5}{27}{3} -\sline{0.5}{30}{3} -\sline{0.5}{33}{3} -\sline{0.5}{36}{3} -\end{timing} - -%The running channel: Continous transfer if data words are always in the -%pipeline. Care has to be taken if no new data word can be provided, then -%WRITE\_IN has to be pulled down after the last valid word. - - -\newpage - - - -\begin{timing}[2s]{4cm} -\tin{1}{FIFO\_FULL\_OUT} -\tin{2}{DATA\_IN} -\tin{3}{WRITE\_IN} -\tin{4}{SEND\_IN} -\tin{5}{RUN\_OUT} -\til{1}{ -%..xxx...xxx...xxx...xxx... -LLLLLLLLLLLLLLLLLLLLLLLLLLL} -\til{2}{ -VVVXVVXVVXVVXVVUUUUUUUUUUUU} -\tnote{2}{0.7}{D1} -\tnote{2}{3.7}{D2} -\tnote{2}{6.7}{D3} -\tnote{2}{9.7}{D4} -\til{3}{ -HHHHHHHHHHHHHHHFFFFFFFFFFFF} -\til{4}{ -HHHHHHHHHHHHHHHLLLLLLLLLLLL} -\til{5}{ -HHHHHHHHHHHHHHHHHHHHHHHHHHH} -%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status} -%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status} -\sline{0.5}{0}{5} -\sline{0.5}{3}{5} -\sline{0.5}{6}{5} -\sline{0.5}{9}{5} -\sline{0.5}{12}{5} -\sline{0.5}{15}{5} -\sline{0.5}{18}{5} -\sline{0.5}{21}{5} -\sline{0.5}{24}{5} -\sline{0.5}{27}{5} -\end{timing} - -%The last words. SEND\_IN is released, -%RUN\_OUT will stay high. During this stage, all writes are ignored. -%Now it is time to wait for the answer! - -\newpage - - - -\begin{timing}[2s]{4cm} -\tin{1}{DATAREADY\_OUT} -\tin{2}{DATA\_OUT} -\tin{3}{READ\_IN} -\tin{4}{TYP\_OUT} -\til{1}{ -%..xxx...xxx...xxx...xxx... -LLLHHHHHHHHHLLLLLLHHHHHHHHH} -\til{2}{ -UUUXVVVVVXVVUUUUUUXVVVVVXVV} -\tnote{2}{3.7}{D1} -\tnote{2}{9.7}{D2} -\tnote{2}{18.7}{D3} -\tnote{2}{24.7}{D4} -\til{3}{ -LLLLLLHHHHHHHHHLLLLLLHHHHHH} -\til{4}{ -UUUVVVVVVVVVUUUUUUVVVVVVVVV} -\tnote{4}{3.7}{DAT or HDR} -\tnote{4}{18.7}{DAT or HDR} -%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status} -%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status} -\sline{0.5}{0}{4} -\sline{0.5}{3}{4} -\sline{0.5}{6}{4} -\sline{0.5}{9}{4} -\sline{0.5}{12}{4} -\sline{0.5}{15}{4} -\sline{0.5}{18}{4} -\sline{0.5}{21}{4} -\sline{0.5}{24}{4} -\sline{0.5}{27}{4} -\end{timing} - -%A typical read cycle after the answer arrives from the slaves. -%Same is true like for the writing: READ\_IN may stay high to save -%1 clock cycle. But the target must be able to read the offered word, otherwise -%it is lost. - -\newpage - - - -\begin{timing}[2s]{4cm} -\tin{1}{DATAREADY\_OUT} -\tin{2}{DATA\_OUT} -\tin{3}{READ\_IN} -\tin{4}{TYP\_OUT} -\tin{5}{RUN\_OUT} -\til{1}{ -%..xxx...xxx...xxx...xxx... -LLLHHHHHHLLLLLLLLL} -\til{2}{ -UUUXVVVVVUUUUUUUUU} -\tnote{2}{3.7}{TRM} -\til{3}{ -LLLLLLHHHLLLLLLLLL} -\til{4}{ -UUUVVVVVVUUUUUUUUU} -\tnote{4}{3.7}{TRM} -\til{5}{ -HHHHHHHHHFFFFFFLLL} -%\tnote{2}{3}{Adressen}\tnote{2}{11}{Status} -%\tnote{2}{36}{Adressen}\tnote{2}{44}{Status} -\sline{0.5}{0}{5} -\sline{0.5}{3}{5} -\sline{0.5}{6}{5} -\sline{0.5}{9}{5} -\sline{0.5}{12}{5} -\sline{0.5}{15}{5} -\sline{0.5}{18}{5} - -\end{timing} - -%The end of the story: The TRM word. After this has been read, the -%RUN\_OUT will be released and a new transfer may by initialized. - -\end{document} - diff --git a/oldfiles/timing/timing.mf b/oldfiles/timing/timing.mf deleted file mode 100644 index 2aef4c8..0000000 --- a/oldfiles/timing/timing.mf +++ /dev/null @@ -1,492 +0,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% TIMING.MF -% -% Zeichensatz zum Darstellen von Zeitdiagrammen digitaler -% Schaltungen. -% Hauptdatei fr alle Zeichens„tze -% -% Ludwig May, Dezember 1991 -% Jens Leilich, Žnderungen im Mai 1994 -% -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% - -define_pixels(p_size,p3_size); -%define_good_x_pixels(c_width); -%define_good_y_pixels(c_height); -define_whole_pixels(c_width,c_height,p2_size); -if not odd c_width: c_width:=c_width-1; fi - -font_x_height c_height#; -font_quad c_width#; - -pen pinsel; -pinsel=(pencircle xscaled (0.8*p_size) yscaled p_size); - - -beginchar("H",c_width#,c_height#,bt#); "High Level"; - -pickup pinsel; -draw (-c_width,c_height)--(0,c_height); -showit; -endchar; - - -beginchar("L",c_width#,c_height#,bt#); "Low Level"; - -pickup pinsel; -draw (-c_width,0)--(0,0); -showit; -endchar; - -%1/12->xs#/12, damit Steigung von HL und LH wie UV (JL,8.1.94) -beginchar(0,2*c_width#,c_height#,bt#); "High-Low"; - -pickup pinsel; -draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0); -showit; -endchar; - -beginchar(1,2*c_width#,c_height#,bt#); "Low-High"; - -pickup pinsel; -draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height); -showit; -endchar; - -beginchar(12,2*c_width#,c_height#,bt#); "Change Bus"; - -pickup pinsel; -draw (-c_width,0)--(-xs#/12*c_width,0); -draw (-c_width,c_height)--(-xs#/12*c_width,c_height); -draw (xs#/12*c_width,0)--(c_width,0); -draw (xs#/12*c_width,c_height)--(c_width,c_height); -draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height); -draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0); -showit; -endchar; - -beginchar("V",c_width#,c_height#,bt#); "Valid Bus"; - -pickup pinsel; -draw (-c_width,0)--(0,0); -draw (-c_width,c_height)--(0,c_height); -showit; -endchar; - -beginchar("Z",c_width#,c_height#,bt#); "Tristate Bus"; - -pickup pinsel; -draw (-c_width,c_height/2)--(0,c_height/2); -showit; -endchar; - -beginchar(2,2*c_width#,c_height#,bt#); "Tristate -> Valid Bus"; - -pickup pinsel; -draw (-c_width,c_height/2)--(0/12*c_width,c_height/2); -draw (0/12*c_width,c_height/2)--(xs#/12*c_width,c_height)--(c_width,c_height); -draw (0/12*c_width,c_height/2)--(xs#/12*c_width,0)--(c_width,0); -showit; -endchar; - -beginchar(3,2*c_width#,c_height#,bt#); "Valid -> Tristate Bus"; - -pickup pinsel; -draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(0/12*c_width,c_height/2); -draw (-c_width,0)--(-xs#/12*c_width,0)--(0/12*c_width,c_height/2); -draw (0/12*c_width,c_height/2)--(c_width,c_height/2); -showit; -endchar; - - -beginchar("U",c_width#,c_height#,bt#); "Invalid Bus"; - -pickup pinsel; -draw (-c_width,0)--(0,0); -draw (-c_width,c_height)--(0,c_height); - -pickup pencircle scaled p3_size; -draw (-c_width,5/6*c_height)--(-c_width/2,c_height); -draw (-c_width,c_height/2)--(0,5/6*c_height); -draw (-c_width,1/6*c_height)--(0,c_height/2); -draw (-c_width/2,0)--(0,1/6*c_height); -showit; -endchar; - - -beginchar(4,2*c_width#,c_height#,bt#); "Tristate -> Invalid Bus"; - -y1=s_f#*2/3*(x1+c_width)+1/2*c_height; -x1=y1*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 1. Linie -%y1=s_f#* 12/xs#*(x1+c_width)-(6/xs#-0.5)*c_height;% Startpunkt der 1. Linie -y2=s_f#*2/3*(x2+c_width)+1/6*c_height; -x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie -%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height;% Startpunkt der 2. Linie -y3=s_f#*2/3*(x3+c_width)-1/6*c_height; -x3=y3*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 3. Linie -%y3=s_f#*-12/xs#*(x3+c_width)+(6/xs#+0.5)*c_height;% Startpunkt der 3. Linie - -pickup pinsel; -draw (-c_width,c_height/2)--(0/12*c_width,c_height/2); -draw (0/12*c_width,c_height/2)--(xs#/12*c_width,c_height)--(c_width,c_height); -draw (0/12*c_width,c_height/2)--(xs#/12*c_width,0)--(c_width,0); - -pickup pencircle scaled p3_size; -draw z1--(1/2*c_width,c_height); -draw z2--(c_width,5/6*c_height); -draw z3--(c_width,c_height/2); -draw (1/2*c_width,0)--(c_width,1/6*c_height); -showit; -endchar; - -beginchar(5,2*c_width#,c_height#,bt#); "Invalid -> Tristate Bus"; - -y1=s_f#*2/3*(x1+c_width)+1/2*c_height ; -x1=y1*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 1. Linie -%y1=s_f#*-12/xs#*(x1+c_width)+(6/xs#+0.5)*c_height; % Startpunkt der 1. Linie -y2=s_f#*2/3*(x2+c_width)+1/6*c_height ; -x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie -%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height; % Startpunkt der 2. Linie -y3=s_f#*2/3*(x3+c_width)-1/6*c_height ; -x3=y3*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 3. Linie -%y3=s_f#* 12/xs#*(x3+c_width)-(6/xs#-0.5)*c_height; % Startpunkt der 3. Linie - -pickup pinsel; -draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(0/12*c_width,c_height/2); -draw (-c_width,0)--(-xs#/12*c_width,0)--(0/12*c_width,c_height/2); -draw (0/12*c_width,c_height/2)--(c_width,c_height/2); - -pickup pencircle scaled p3_size; -draw (-c_width,5/6*c_height)--(-c_width/2,c_height); -draw (-c_width,c_height/2)--z1; -draw (-c_width,1/6*c_height)--z2; -draw (-c_width/2,0)--z3; -showit; -endchar; - - -beginchar(6,2*c_width#,c_height#,bt#); "Valid -> Invalid Bus"; - -y1=s_f#*2/3*(x1+c_width)+1/2*c_height; -x1=y1*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 1. Linie -%y1=s_f#* 12/xs#*(x1+c_width)-(6/xs#-0.5)*c_height;% 1. Linie -y2=s_f#*2/3*(x2+c_width)+1/6*c_height; -x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie -%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height;% 2. Linie -y3=s_f#*2/3*(x3+c_width)-1/6*c_height; -x3=y3*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 3. Linie -%y3=s_f#*-12/xs#*(x3+c_width)+(6/xs#+0.5)*c_height;% 3. Linie - -pickup pinsel; -draw (-c_width,0)--(-xs#/12*c_width,0); -draw (-c_width,c_height)--(-xs#/12*c_width,c_height); -draw (xs#/12*c_width,0)--(c_width,0); -draw (xs#/12*c_width,c_height)--(c_width,c_height); -draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height); -draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0); - -pickup pencircle scaled p3_size; -draw z1--(1/2*c_width,c_height); -draw z2--(c_width,5/6*c_height); -draw z3--(c_width,1/2*c_height); -draw (1/2*c_width,0)--(c_width,1/6*c_height); -showit; -endchar; - -beginchar(7,2*c_width#,c_height#,bt#); "Invalid -> Valid Bus"; - -y1=s_f#*2/3*(x1+c_width)+1/2*c_height; -x1=y1*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 1. Linie -%y1=s_f#*-12/xs#*(x1+c_width)+(6/xs#+0.5)*c_height;% 1. Linie -y2=s_f#*2/3*(x2+c_width)+1/6*c_height; -x2=y2*(xs#/s_f#/-12)-(6+xs#*0.5)*c_height/s_f#/-12-c_width;% Startpunkt der 2. Linie -%y2=s_f#*-12/xs#*(x2+c_width)+(6/xs#+0.5)*c_height;% 2. Linie -y3=s_f#*2/3*(x3+c_width)-1/6*c_height; -x3=y3*(xs#/s_f#/12)+(6-xs#*0.5)*c_height/s_f#/12-c_width;% Startpunkt der 3. Linie -%y3=s_f#* 12/xs#*(x3+c_width)-(6/xs#-0.5)*c_height;% 3. Linie - -pickup pinsel; -draw (-c_width,0)--(-xs#/12*c_width,0); -draw (-c_width,c_height)--(-xs#/12*c_width,c_height); -draw (xs#/12*c_width,0)--(c_width,0); -draw (xs#/12*c_width,c_height)--(c_width,c_height); -draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height); -draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0); - -pickup pencircle scaled p3_size; -draw (-c_width,5/6*c_height)--(-1/2*c_width,c_height); -draw (-c_width,1/2*c_height)--z1; -draw (-c_width,1/6*c_height)--z2; -draw (-1/2*c_width,0)--z3; -showit; -endchar; - -beginchar("F",c_width#,c_height#,bt#); "Floating Line"; - -pickup pinsel; -draw (-c_width,0)--(0,0); -draw (-c_width,c_height)--(0,c_height); -showit; -endchar; - -%1/12->xs#/12, damit Steigung von FL und FH wie UV (JL,8.1.94) -beginchar(13,2*c_width#,c_height#,bt#); "Float-Low"; - -pickup pinsel; -draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0); -draw (-c_width,0)--(c_width,0); -showit; -endchar; - -beginchar(14,2*c_width#,c_height#,bt#); "Float-High"; - -pickup pinsel; -draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height); -draw (-c_width,c_height)--(c_width,c_height); -showit; -endchar; - -beginchar(15,2*c_width#,c_height#,bt#); "High-Float"; - -pickup pinsel; -draw (-c_width,c_height)--(c_width,c_height); -draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0); -showit; -endchar; - -beginchar(16,2*c_width#,c_height#,bt#); "Low-Float"; - -pickup pinsel; -draw (-c_width,0)--(c_width,0); -draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height); -showit; -endchar; - - -beginchar("-",c_width#/2,c_height#,bt#); "..."; - -pickup pencircle scaled p3_size; -draw (-c_width,-1/12*c_height)--(-c_width,13/12*c_height); -draw (-c_width/2-1,-1/12*c_height)--(-c_width/2-1,13/12*c_height); -showit; -endchar; - -beginchar("T",c_width#,1/6*c_height#,bt#); "TOP"; - -pickup pinsel; -draw (-c_width,1/12*c_height)--(-c_width,1/6*c_height)--(0,1/6*c_height); -showit; -endchar; - -beginchar("B",c_width#,1/6*c_height#,bt#); "BOTTOM"; - -pickup pinsel; -draw (-c_width,1/12*c_height)--(-c_width,0)--(0,0); -showit; -endchar; - -beginchar(8,3/2*c_width#,1/6*c_height#,bt#); "TOP-"; - -pickup pinsel; -draw (-c_width,1/12*c_height)--(-c_width,1/6*c_height)--(0,1/6*c_height); -pickup pencircle scaled p3_size; -draw (0+1,0)--(0+1,2/12*c_height); -draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height); -showit; -endchar; - -beginchar(9,3/2*c_width#,1/6*c_height#,bt#); "BOTTOM-"; - -pickup pinsel; -draw (-c_width,1/12*c_height)--(-c_width,0)--(0,0); -pickup pencircle scaled p3_size; -draw (0+1,0)--(0+1,2/12*c_height); -draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height); -showit; -endchar; - -beginchar(10,3/2*c_width#,1/6*c_height#,bt#); "top-"; - -pickup pinsel; -draw (-c_width,1/6*c_height)--(0,1/6*c_height); -pickup pencircle scaled p3_size; -draw (0+1,0)--(0+1,2/12*c_height); -draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height); -showit; -endchar; - -beginchar(11,3/2*c_width#,1/6*c_height#,bt#); "bottom-"; - -pickup pinsel; -draw (-c_width,0)--(0,0); -pickup pencircle scaled p3_size; -draw (0+1,0)--(0+1,2/12*c_height); -draw (1/2*c_width-1,0)--(1/2*c_width-1,2/12*c_height); -showit; -endchar; - -beginchar("t",c_width#,1/6*c_height#,bt#); - -pickup pinsel; -draw (-c_width,1/6*c_height)--(0,1/6*c_height); -showit; -endchar; - -beginchar("b",c_width#,1/6*c_height#,bt#); - -pickup pinsel; -draw (-c_width,0)--(0,0); -showit; -endchar; - -%Pfeil von 1/2 nach 7/8 der Breite vergr”žert (JL,8.1.94) -beginchar("A",c_width#,3/12*c_height#,0); "Arrow left"; - -pickup pencircle scaled p_size; -draw (-1/8*c_width,1/12*c_height)--(0,1/12*c_height); -fill (-1/8*c_width,2/12*c_height)--(-c_width,1/12*c_height)--(-1/8*c_width,0)--cycle; -showit; -endchar; - -beginchar("P",c_width#,3/12*c_height#,0); "Arrow right"; - -pickup pencircle scaled p_size; -draw (-c_width,1/12*c_height)--(-1/8*c_width,1/12*c_height); -fill (-7/8*c_width,2/12*c_height)--(0,1/12*c_height)--(-7/8*c_width,0)--cycle; -showit; -endchar; - -beginchar("a",c_width#,3/12*c_height#,0); "Arrow line"; - -pickup pencircle scaled p_size; -draw (-c_width,1/12*c_height)--(0,1/12*c_height); -showit; -endchar; - - -%dasselbe wie "U" -beginchar("X",c_width#,c_height#,bt#); "Unknown"; -pickup pinsel; -draw (-c_width,0)--(0,0); -draw (-c_width,c_height)--(0,c_height); - -pickup pencircle scaled p3_size; -draw (-c_width,5/6*c_height)--(-c_width/2,c_height); -draw (-c_width,c_height/2)--(0,5/6*c_height); -draw (-c_width,1/6*c_height)--(0,c_height/2); -draw (-c_width/2,0)--(0,1/6*c_height); -showit; -endchar; - -%Leerzeichen mit Punkten, damit nachtr„glich gezeichnet werden kann -%(JL,8.1.94) - -beginchar(".",c_width#,c_height#,bt#); "Leer"; -pickup pinsel; -fill (-c_width,0)--(-c_width+p2_size,0)-- - (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle; -fill (-c_width,c_height)--(-c_width+p2_size,c_height)-- - (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle; -showit; -endchar; - -beginchar("h",c_width#,c_height#,bt#); "High Level"; -pickup pinsel; -draw (-c_width,c_height)--(0,c_height); -fill (-c_width,0)--(-c_width+p2_size,0)-- - (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle; -showit; -endchar; - - -beginchar("l",c_width#,c_height#,bt#); "Low Level"; -pickup pinsel; -draw (-c_width,0)--(0,0); -fill (-c_width,c_height)--(-c_width+p2_size,c_height)-- - (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle; -showit; -endchar; - -beginchar(20,2*c_width#,c_height#,bt#); "High-Low"; -pickup pinsel; -draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0); -fill (-c_width,0)--(-c_width+p2_size,0)-- - (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle; -fill (0,c_height)--(p2_size,c_height)-- - (p2_size,c_height-p2_size)--(0,c_height-p2_size)--cycle; -showit; -endchar; - -beginchar(21,2*c_width#,c_height#,bt#); "Low-High"; -pickup pinsel; -draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height); -fill (0,0)--(p2_size,0)-- - (p2_size,p2_size)--(0,p2_size)--cycle; -fill (-c_width,c_height)--(-c_width+p2_size,c_height)-- - (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle; -showit; -endchar; - -beginchar("f",c_width#,c_height#,bt#); "Floating Line"; -pickup pinsel; -draw (-c_width,0)--(0,0); -draw (-c_width,c_height)--(0,c_height); -showit; -endchar; - -beginchar(33,2*c_width#,c_height#,bt#); "Float-Low"; -pickup pinsel; -draw (-c_width,c_height)--(-xs#/12*c_width,c_height)--(xs#/12*c_width,0); -draw (-c_width,0)--(c_width,0); -fill (0,c_height)--(p2_size,c_height)-- - (p2_size,c_height-p2_size)--(0,c_height-p2_size)--cycle; -showit; -endchar; - -beginchar(34,2*c_width#,c_height#,bt#); "Float-High"; -pickup pinsel; -draw (-c_width,0)--(-xs#/12*c_width,0)--(xs#/12*c_width,c_height); -draw (-c_width,c_height)--(c_width,c_height); -fill (0,0)--(p2_size,0)-- - (p2_size,p2_size)--(0,p2_size)--cycle; -showit; -endchar; - -beginchar(35,2*c_width#,c_height#,bt#); "High-Float"; -pickup pinsel; -draw (-c_width,c_height)--(c_width,c_height); -draw (-xs#/12*c_width,c_height)--(xs#/12*c_width,0)--(c_width,0); -fill (-c_width,0)--(-c_width+p2_size,0)-- - (-c_width+p2_size,p2_size)--(-c_width,p2_size)--cycle; -showit; -endchar; - -beginchar(36,2*c_width#,c_height#,bt#); "Low-Float"; -pickup pinsel; -draw (-c_width,0)--(c_width,0); -draw (-xs#/12*c_width,0)--(xs#/12*c_width,c_height)--(c_width,c_height); -fill (-c_width,c_height)--(-c_width+p2_size,c_height)-- - (-c_width+p2_size,c_height-p2_size)--(-c_width,c_height-p2_size)--cycle; -showit; -endchar; - - -% HX,LX,XH,XL und dasselbe mit U statt X sind eigtl. Pfusch -% vielleicht mal Zeichen fr machen... (JL) -ligtable "H":"L"=:0, "F"=:15, "V"=:15, "X"=:15; -ligtable "L":"H"=:1, "F"=:16, "V"=:16, "X"=:16; -ligtable "F":"L"=:13,"H"=:14; -ligtable "h":"l"=:20,"f"=:35; % Version mit Punkten zum Zeichnen (JL, 4.2.94) -ligtable "l":"h"=:21,"f"=:36; -ligtable "f":"l"=:33,"h"=:34; -ligtable "Z":"V"=:2, "U"=:4; -ligtable "V":"Z"=:3, "U"=:6, "X"=:12, "L"=:13, "H"=:14; -ligtable "U":"Z"=:5, "V"=:7, "X"=:7, "L"=:13, "H"=:14; % UX=:7 [UV] (JL, 8.1.94) -ligtable "X":"V"=:12,"U"=:6, "L"=:13, "H"=:14; % XU=:6 [VU] (JL, 8.1.94) -ligtable "T":"-"=:8; -ligtable "B":"-"=:9; -ligtable "t":"-"=:10; -ligtable "b":"-"=:11; - -end; - diff --git a/oldfiles/timing/timing.sty b/oldfiles/timing/timing.sty deleted file mode 100644 index 0bb8abd..0000000 --- a/oldfiles/timing/timing.sty +++ /dev/null @@ -1,309 +0,0 @@ -% timing.sty: Ludwig May/Jens Leilich 10.12.91 -% -% Dieses Style-File erleichtert den Umgang mit dem Timing-Font. -% -% Es stellt Kommandos zur Positionierung von einzelnen Elementen -% eines Timing-Diagramms in einer picture-Umgebung zur Verfuegung. -% -% -% Folgende Kommandos sind verfuegbar: -% -% Erweiterte picture-Umgebung -% \begin{timing}[Zeichensatz]{Randgroesse} -% \end{timing} -% Zeichensatz ist 1,2,1s,2s. Die Zahl gibt die Breite an, -% s bedeutet schr„ge Flanken. 2 ist default. -% -% Zeile mit Timingdiagramm -% \til{y-pos}{Zeichenkette} -% -% Label fuer Zeile -% \tin{y-pos}{Zeichenkette} -% -% Bemerkung -% \tnote{y-pos}{x-pos}{Zeichenkette} -% -% Pfeil nach rechts zeigend -% \rarw{y-pos}{x-pos}{laenge}{Zeichenkette} -% -% Pfeil nach links zeigend -% \larw{y-pos}{x-pos}{laenge}{Zeichenkette} -% -% Senkrechte Linie -% \sline{y1-pos}{x-pos}{y2-pos} -% -% Zeitmarken als Argument fuer \til -% \timingcounter{Markenabstand}{Startwert}{Endwert}{Intervall} -% Zeitmarken als Argument fuer \til nach Unterbrechung -% \conttimingcounter{Markenabstand}{Startwert}{Endwert}{Intervall} -% -% -% Abstandsfaktor fuer einzelne Zeilen -% \timescalefactor -% -% Evtl. n”tige Anpassung fuer Ausrichtung senkrechter Linien -% \timadjust -% -% -% Dieses Style-File und der dazugehoerige Zeichensatz wurde erstellt, -% um moeglichst einfach ein paar Timingdiagramme in meine Studienarbeit -% integrieren zu koennen. Da es in der vorliegenden Form meine -% Erwartungen vollstaendig erfuellt hat, haben ich aus Zeitgruenden keine -% grosse Ueberarbeitung durchgefuehrt. Vielleicht kann das jemand uebernehmen, -% der von der ganzen Materie mehr Ahnung hat. Ein Problem ist z.B. die -% ungenaue horizontale Ausrichtung der senkrechten Linien (ist irgendwie -% Druckertreiber abhaengig, evtl. MAX_DRIFT des Treibers auf 0 setzen). -% Da aber grosses Interesse an dem Style besteht, haben ich ihn mal in -% Umlauf gegeben. Wenn jemand Verbesserungen durchfuehrt, waeren ich an -% einer Rueckmeldung an folgende Adresse dankbar: -% -% Ludwig May -% Friedrichstrasse 23b -% 6100 Darmstadt -% -% Bitte keine Fragen stellen, ich habe fuer eine weitere Unterstuetzung -% weder Zeit noch ausreichend Gelegenheit. -% -% Ludwig May -% -% Ich habe Font und Style weiterentwickelt zu Lehrzwecken, da ich -% Elektrotechnik an BBS unterrichte. -% Verbesserungsvorschl„ge und Lob ;-) k”nnen auch an mich gerichtet -% werden. -% Jens Leilich, C/O BBS Technik I, Franz-Zang-Str. 3--7, 67059 Ludwigshafen -% Jens_Leilich @ lu.maus.de -% -\typeout{Timing Style, Ludwig May Jens Leilich .} -% -% -% Alle benoetigten Counter, Dimensionen und Boxen definieren -% -% -\newfont{\timon}{timing1 scaled 1000} -\newfont{\timtw}{timing2 scaled 1000} -\newfont{\timons}{timing1s scaled 1000} -\newfont{\timtws}{timing2s scaled 1000} -\newfont{\timbs}{cmr5 scaled 1000} -\newcount\counttime -\newdimen\timetmpdim -\newdimen\timehdrdim -\newcount\timetmpcnt -\newcount\timearwcnt -\newdimen\timeskipdim -\newdimen\timewidthdim -\newbox\timebox -\def\timescalefactor{2} -\def\timadjust{0.0pt} -% -% -% Neue Umgebung definieren -% -% -\def\timing{\@ifnextchar [{\@@timing}{\@@timing[2]}} - -\def\@@timing[#1]#2% -{ -\expandafter\def\csname tim@@1\endcsname{\let\tim\timon} -\expandafter\def\csname tim@@2\endcsname{\let\tim\timtw} -\expandafter\def\csname tim@@1s\endcsname{\let\tim\timons} -\expandafter\def\csname tim@@2s\endcsname{\let\tim\timtws} -\def\tim{% - \typeout{Timing font `#1' not defined, assumed 2. Use 1,2,1s,2s only!} - \timtw \let\tim\timtw} -\csname tim@@#1\endcsname -\tim -\timehdrdim=#2 -\advance\timehdrdim by 1em -% -% -% Lokale Befehle definieren -% -% -% -% Hilfroutine zum Zeichen von Pfeilen variabler Laenge -% -% -\newcommand{\timatail}[1]{ \mbox{ \tim - \counttime=2 - \ifnum##1>1 - \loop - a% - \ifnum\counttime<##1 \advance\counttime by 1 - \repeat - \fi -}} -% -% -% Hilfroutine zum Zeichen der Zeitmarkierung -% -% -\newcommand{\lb}[2]{{\tim\makebox[##1em][c]{\timbs##2}}} -% -% -% \timingcounter -% -% -\newcommand{\timingcounter}[4]{ \mbox{ \tim - \counttime=##1\divide\counttime by -2 - \hskip\counttime em - \hskip -1em - \counttime=##2 - \loop - \lb{##1}{\number\counttime} - \ifnum\counttime<##3 \advance\counttime by ##4 - \repeat -}} -% -% -% \conttimingcounter -% -% -\newcommand{\conttimingcounter}[4]{ \mbox{ \tim - \hskip 0.5em - \counttime=##2 - \loop - \lb{##1}{\number\counttime} - \ifnum\counttime<##3 \advance\counttime by ##4 - \repeat -}} -% -% -% \til -% -% -\newcommand{\til}[2]{ -\tim -\timetmpdim=##1ex -\timetmpdim=\timescalefactor\timetmpdim -% -% Maximale y-Groesse festhalten -% -\ifdim\timetmpdim>\timeskipdim - \global\timeskipdim=\timetmpdim -\fi -\timetmpcnt=\timetmpdim -\timetmpdim=\timehdrdim -\advance\timetmpdim by -\timadjust -\timearwcnt=\timetmpdim -\setbox\timebox=\hbox{##2} -% -% Maximale x-Groesse festhalten -% -\ifdim\wd\timebox>\timewidthdim - \global\timewidthdim=\wd\timebox -\fi -\put(\timearwcnt,-\timetmpcnt){\tim\makebox(0,0)[l]{\box\timebox}} -%\put(\timearwcnt,-\timetmpcnt){\tim\makebox(0,0)[l]{##2}} -} -% -% -% \tin -% -% -\newcommand{\tin}[2]{ -\tim -\timetmpdim=##1ex -\timetmpdim=\timescalefactor\timetmpdim -\timetmpcnt=\timetmpdim -\put(0,-\timetmpcnt){\makebox(0,0)[lb]{\rm##2}} -} -% -% -% \tnote -% -% -\newcommand{\tnote}[3]{ -\tim -\timetmpdim=##1ex -\advance\timetmpdim by -0.3pt -\timetmpdim=\timescalefactor\timetmpdim -\timetmpcnt=\timetmpdim -\timetmpdim=##2em -\advance\timetmpdim by \timehdrdim -\advance\timetmpdim by -1em -\timearwcnt=\timetmpdim -\put(\timearwcnt,-\timetmpcnt){\tim\makebox(0,0)[l]{\scriptsize\sf##3}} -} -% -% -% \larw -% -% -\newcommand{\larw}[4]{ -\tim -\timetmpdim=##1ex -\timetmpdim=\timescalefactor\timetmpdim -\timetmpcnt=\timetmpdim -\timetmpdim=##2em -\advance\timetmpdim by \timehdrdim -\timearwcnt=\timetmpdim -\put(\timearwcnt,-\timetmpcnt)% - {\makebox(0,0)[l]{\tiny\vbox{\tim\hbox{\hskip-1em\hbox to ##3em{\hss\timbs\strut##4\hfil}}\nointerlineskip\vskip-4pt\hbox{A\timatail{##3}}}}} -} -% -% -% \rarw -% -% -\newcommand{\rarw}[4]{ -\tim -\timetmpdim=##1ex -\timetmpdim=\timescalefactor\timetmpdim -\timetmpcnt=\timetmpdim -\timetmpdim=##2em -\advance\timetmpdim by \timehdrdim -\timearwcnt=\timetmpdim -\put(\timearwcnt,-\timetmpcnt)% - {\makebox(0,0)[l]{\tiny\vbox{\tim\hbox{\hskip-1em\hbox to ##3em{\hfil\timbs\strut##4\hss}}\nointerlineskip\vskip-4pt\hbox{\timatail{##3}P}}}} -} -% -% -% \sline -% -% -\newcommand{\sline}[3]{ -\tim -\timetmpdim=##1ex -\timetmpdim=\timescalefactor\timetmpdim -\timetmpcnt=\timetmpdim -\timetmpdim=##2em -\advance\timetmpdim by \timehdrdim -\advance\timetmpdim by -1em -\timearwcnt=\timetmpdim -\timetmpdim=##3ex -\advance \timetmpdim by -##1ex -\advance \timetmpdim by 0.09ex -\timetmpdim=\timescalefactor\timetmpdim -\counttime=\timetmpdim -\put(\timearwcnt,-\timetmpcnt)% - {\line(0,-1){\counttime}} -} -% -% -% Weitere Initialisierung -% -% -\timeskipdim=0pt -\timewidthdim=0pt -\unitlength 1sp -\begin{picture}(0,0) -\linethickness{0.4pt} -}% -% -% -% Ende der Umgebung definieren -% -% -\def\endtiming{ -\global\advance\timeskipdim by 15pt -\end{picture} -% -% Da picture(0,0) definiert wurde, wird jetzt die wirkliche Groesse durch -% ein \rule freigehalten. -% -\timeskipdim=1.0\timeskipdim -\timewidthdim=1.0\timewidthdim -\advance\timewidthdim by \timehdrdim -\rule{\timewidthdim}{0pt} -\rule[-\timeskipdim]{0pt}{\timeskipdim} -} diff --git a/oldfiles/timing/timing1.mf b/oldfiles/timing/timing1.mf deleted file mode 100644 index 64b42dc..0000000 --- a/oldfiles/timing/timing1.mf +++ /dev/null @@ -1,29 +0,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% TIMING1.MF -% -% Zeichensatz zum Darstellen von Zeitdiagrammen digitaler -% Schaltungen. -% Datei fr Zeichensatz mit ca. 1mm Breite -% -% Ludwig May, Dezember 1991 -% Jens Leilich, Žnderungen im Mai 1994 -% -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -mode_setup; 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-USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - - -entity trb_net16_api_active is - - generic ( - FIFO_TO_INT_DEPTH : integer := std_FIFO_DEPTH; -- direction to medium - FIFO_TO_APL_DEPTH : integer := std_FIFO_DEPTH; -- direction to application - SBUF_VERSION : integer := std_SBUF_VERSION; - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN : in std_logic; - - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT : out std_logic; - - - INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN : in std_logic; - - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_api_active_arch of trb_net16_api_active is - - component trb_net16_api_base is - generic ( - API_TYPE : integer := 1; -- type of api: 0 passive, 1 active - FIFO_TO_INT_DEPTH : integer := FIFO_TO_INT_DEPTH; - FIFO_TO_APL_DEPTH : integer := FIFO_TO_APL_DEPTH; - SBUF_VERSION : integer := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_IN : in std_logic; - - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - - - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - -begin - - BASE_API: trb_net16_api_base - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - SBUF_VERSION => SBUF_VERSION - ) - port map ( - CLK => CLK, - CLK_EN => CLK_EN, - RESET => RESET, - - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT, - INT_MASTER_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, - INT_MASTER_READ_IN => INT_INIT_READ_IN, - - INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_MASTER_DATA_IN => INT_INIT_DATA_IN, - INT_MASTER_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN, - INT_MASTER_READ_OUT => INT_INIT_READ_OUT, - - INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - - INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT, - INT_SLAVE_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, - INT_SLAVE_READ_IN => INT_REPLY_READ_IN, - - INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN, - INT_SLAVE_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, - INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT, - -- Status and control port - STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, - STAT_FIFO_TO_APL => STAT_FIFO_TO_APL - -- not needed now, but later - ); - -end architecture; diff --git a/oldfiles/trb_net16_api_passive.vhd b/oldfiles/trb_net16_api_passive.vhd deleted file mode 100644 index 75d9f5d..0000000 --- a/oldfiles/trb_net16_api_passive.vhd +++ /dev/null @@ -1,218 +0,0 @@ --- connection between the TRBNET and any application --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net16_api_passive is - - generic ( - FIFO_TO_INT_DEPTH : integer := std_FIFO_DEPTH; -- direction to medium - FIFO_TO_APL_DEPTH : integer := std_FIFO_DEPTH; -- direction to application - SBUF_VERSION : integer := std_SBUF_VERSION; - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN : in std_logic; - - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT : out std_logic; - - - INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN : in std_logic; - - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_api_passive_arch of trb_net16_api_passive is - - component trb_net16_api_base is - generic ( - API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_IN : in std_logic; - - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - - - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - -begin - - BASE_API: trb_net16_api_base - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - SBUF_VERSION => SBUF_VERSION - ) - port map ( - CLK => CLK, - CLK_EN => CLK_EN, - RESET => RESET, - - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT, - INT_MASTER_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT, - INT_MASTER_READ_IN => INT_REPLY_READ_IN, - - INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_MASTER_DATA_IN => INT_REPLY_DATA_IN, - INT_MASTER_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, - INT_MASTER_READ_OUT => INT_REPLY_READ_OUT, - - INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - - INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT, - INT_SLAVE_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT, - INT_SLAVE_READ_IN => INT_INIT_READ_IN, - - INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_SLAVE_DATA_IN => INT_INIT_DATA_IN, - INT_SLAVE_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN, - INT_SLAVE_READ_OUT => INT_INIT_READ_OUT, - -- Status and control port - STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, - STAT_FIFO_TO_APL => STAT_FIFO_TO_APL - -- not needed now, but later - ); - -end architecture; diff --git a/oldfiles/trb_net16_api_streaming.vhd b/oldfiles/trb_net16_api_streaming.vhd deleted file mode 100644 index 55f3ed0..0000000 --- a/oldfiles/trb_net16_api_streaming.vhd +++ /dev/null @@ -1,857 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - - -entity trb_net16_api_streaming is - generic( - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6; - FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SECURE_MODE_TO_APL : integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT : integer range 0 to 1 := c_YES; - APL_WRITE_ALL_WORDS: integer range 0 to 1 := c_NO - ); - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT : out std_logic; - - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN : in std_logic; - - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - - --apl init channel - APL_INIT_DATA_IN : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - APL_INIT_PACKET_NUM_IN : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_INIT_DATAREADY_IN : out std_logic; - - --apl reply sending - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN : in std_logic; - APL_READ_OUT : out std_logic; - APL_SHORT_TRANSFER_IN : in std_logic; - APL_DTYPE_IN : in std_logic_vector (3 downto 0); - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - APL_SEND_IN : in std_logic; - - -- reply receiving - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); - APL_DATAREADY_OUT : out std_logic; - APL_READ_IN : in std_logic; - - -- APL Control port - APL_RUN_OUT : out std_logic; - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - APL_LOOPBACK : in std_logic; - - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); -end entity; - - -architecture trb_net16_api_streaming_arch of trb_net16_api_streaming is - component trb_net16_dummy_fifo is - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic - ); - end component; - - component trb_net16_fifo is - generic ( - DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1) 64Bit packets - USE_VENDOR_CORES : integer := c_YES - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic - ); - end component; - - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); - end component; - - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := 0; - SECURE_MODE : integer range 0 to 1 := 0 - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these must be available when hold_trm goes low - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) - -- Status and control port - ); - end component; - - component trb_net_sbuf is - generic ( - DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; - VERSION: integer := SBUF_VERSION); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - - -- signals for the APL to INT fifo: - signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0); - signal fifo_to_int_write : std_logic; - signal fifo_to_int_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_int_packet_num_out : std_logic_vector(1 downto 0); - signal fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal fifo_to_int_read : std_logic; - signal fifo_to_int_full : std_logic; - signal fifo_to_int_empty : std_logic; - - -- signals for the INT to APL: - signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0); - signal fifo_to_apl_write : std_logic; - signal fifo_to_apl_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0); - signal fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal fifo_to_apl_read : std_logic; - signal fifo_to_apl_full : std_logic; - signal fifo_to_apl_empty : std_logic; - signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); - - signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal last_fifo_to_apl_read : std_logic; - signal last_fifo_to_int_read : std_logic; - - signal state_bits, state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0); --- signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic; - - signal next_INT_REPLY_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal next_INT_REPLY_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal next_INT_REPLY_DATAREADY_OUT: std_logic; - signal sbuf_free, sbuf_next_READ: std_logic; - signal reg_INT_REPLY_READ_OUT: std_logic; - signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; - signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0); - - type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); - signal out_select: OUTPUT_SELECT; - signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); - signal combined_header_F1, combined_header_F2, combined_header_F3, combined_header_F0 : std_logic_vector(15 downto 0); - signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3, combined_trailer_F0 : std_logic_vector(15 downto 0); - signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3, registered_trailer_F0 : std_logic_vector(15 downto 0); - signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0); - - signal update_registered_trailer: std_logic; - signal master_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - - type PAS_API_TO_APL_STATE_T is (sa_IDLE, sa_INACTIVE); - signal state_to_apl, next_state_to_apl : PAS_API_TO_APL_STATE_T; - - type state_to_int_t is ( INACTIVE, IDLE, SEND_SHORT, SEND_HEADER, RUNNING, SEND_TRAILER, SHUTDOWN); - signal state_to_int, next_state_to_int : state_to_int_t; - --- type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); --- signal current_state, next_state : API_STATE; - signal throw_away : std_logic; - signal fifo_to_apl_read_before : std_logic; - signal fifo_to_int_read_before : std_logic; - - signal sbuf_to_apl_next_READ : std_logic; - signal sbuf_to_apl_free : std_logic; - signal sbuf_apl_type_dataready : std_logic; - - signal master_start, master_end, slave_start, slave_end : std_logic; - signal master_running, slave_running : std_logic; - - signal buf_INT_REPLY_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal buf_INT_REPLY_DATAREADY_OUT : std_logic; - - signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic; - -begin - - APL_INIT_DATAREADY_IN <= INT_INIT_DATAREADY_IN; - APL_INIT_DATA_IN <= INT_INIT_DATA_IN; - APL_INIT_PACKET_NUM_IN <= INT_INIT_PACKET_NUM_IN; - INT_INIT_READ_OUT <= '1'; - ---------------------------------------- --- fifo to internal ---------------------------------------- - - FIFO_TO_INT: trb_net16_fifo - generic map ( - DEPTH => FIFO_TO_INT_DEPTH, - USE_VENDOR_CORES => USE_VENDOR_CORES) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_int_data_in, - PACKET_NUM_IN => fifo_to_int_packet_num_in, - WRITE_ENABLE_IN => fifo_to_int_write, - DATA_OUT => fifo_to_int_data_out, - PACKET_NUM_OUT => fifo_to_int_packet_num_out, - READ_ENABLE_IN => fifo_to_int_read, - FULL_OUT => fifo_to_int_full, - EMPTY_OUT => fifo_to_int_empty - ); - - STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); - STAT_FIFO_TO_INT(3) <= fifo_to_int_write; - STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_REPLY_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(7) <= buf_INT_REPLY_DATAREADY_OUT; - STAT_FIFO_TO_INT(8) <= INT_REPLY_READ_IN; - STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0); - STAT_FIFO_TO_INT(12) <= fifo_to_int_read; - STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before; - STAT_FIFO_TO_INT(14) <= fifo_to_int_full; - STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; - STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT; - STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free; - STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before; - STAT_FIFO_TO_INT(19) <= fifo_to_apl_read; - STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty; - STAT_FIFO_TO_INT(21) <= fifo_to_apl_write; - STAT_FIFO_TO_INT(24 downto 22) <= next_INT_REPLY_PACKET_NUM_OUT; - STAT_FIFO_TO_INT(25) <= next_INT_REPLY_DATAREADY_OUT; - STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int; - STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl; ---------------------------------------- --- fifo to apl ---------------------------------------- - - FIFO_TO_APL: trb_net16_fifo - generic map ( - DEPTH => FIFO_TO_APL_DEPTH, - USE_VENDOR_CORES => USE_VENDOR_CORES) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_apl_data_in, - PACKET_NUM_IN => fifo_to_apl_packet_num_in, - WRITE_ENABLE_IN => fifo_to_apl_write, - DATA_OUT => fifo_to_apl_data_out, - PACKET_NUM_OUT => fifo_to_apl_packet_num_out, - READ_ENABLE_IN => fifo_to_apl_read, - FULL_OUT => fifo_to_apl_full, - EMPTY_OUT => fifo_to_apl_empty - ); - - STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); - STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; - STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0); - STAT_FIFO_TO_APL(11) <= fifo_to_apl_read; - STAT_FIFO_TO_APL(14) <= fifo_to_apl_full; - STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty; - STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); - --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_APL(31 downto 16) <= (others => '0'); - STAT_FIFO_TO_APL(13) <= reg_INT_REPLY_READ_OUT; - STAT_FIFO_TO_APL(12) <= INT_REPLY_DATAREADY_IN; - STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; - ---------------------------------------- --- a sbuf (to_int direction) ---------------------------------------- - gen_int_sbuf : if SECURE_MODE_TO_INT = 1 generate - SBUF: trb_net16_sbuf - generic map ( - VERSION => SBUF_VERSION) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_INT_REPLY_DATAREADY_OUT, - COMB_next_READ_OUT => sbuf_next_READ, - COMB_READ_IN => '1', - COMB_DATA_IN => next_INT_REPLY_DATA_OUT, - COMB_PACKET_NUM_IN => next_INT_REPLY_PACKET_NUM_OUT, - SYN_DATAREADY_OUT => buf_INT_REPLY_DATAREADY_OUT, - SYN_DATA_OUT => INT_REPLY_DATA_OUT, - SYN_PACKET_NUM_OUT => buf_INT_REPLY_PACKET_NUM_OUT, - SYN_READ_IN => INT_REPLY_READ_IN - ); - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - sbuf_free <= '0'; - else - sbuf_free <= sbuf_next_READ or INT_REPLY_READ_IN; - end if; - end if; - end process; - end generate; - gen_int_nonsbuf : if SECURE_MODE_TO_INT = 0 generate - buf_INT_REPLY_DATAREADY_OUT <= next_INT_REPLY_DATAREADY_OUT; - INT_REPLY_DATA_OUT <= next_INT_REPLY_DATA_OUT; - buf_INT_REPLY_PACKET_NUM_OUT <= next_INT_REPLY_PACKET_NUM_OUT; - sbuf_free <= INT_REPLY_READ_IN; - end generate; -INT_REPLY_PACKET_NUM_OUT <= buf_INT_REPLY_PACKET_NUM_OUT; -INT_REPLY_DATAREADY_OUT <= buf_INT_REPLY_DATAREADY_OUT; ---------------------------------------- --- a sbuf (to_apl direction) ---------------------------------------- - gen_apl_sbuf : if SECURE_MODE_TO_APL = 1 generate - SBUF_TO_APL: trb_net16_sbuf - generic map ( - VERSION => SBUF_VERSION) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_APL_DATAREADY_OUT, - COMB_next_READ_OUT => sbuf_to_apl_next_READ, - COMB_READ_IN => '1', - COMB_DATA_IN => next_APL_DATA_OUT, - COMB_PACKET_NUM_IN => next_APL_PACKET_NUM_OUT, - SYN_DATAREADY_OUT => reg_APL_DATAREADY_OUT, - SYN_DATA_OUT => reg_APL_DATA_OUT, - SYN_PACKET_NUM_OUT => reg_APL_PACKET_NUM_OUT, - SYN_READ_IN => APL_READ_IN - ); - SBUF_TO_APL2: trb_net_sbuf - generic map ( - VERSION => SBUF_VERSION, - DATA_WIDTH => 3) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_APL_DATAREADY_OUT, - COMB_next_READ_OUT => open, - COMB_READ_IN => '1', - COMB_DATA_IN => next_APL_TYP_OUT, - SYN_DATAREADY_OUT => sbuf_apl_type_dataready, - SYN_DATA_OUT => buf_APL_TYP_OUT, - SYN_READ_IN => APL_READ_IN - ); - - reg_APL_TYP_OUT <= TYPE_ILLEGAL when sbuf_apl_type_dataready = '0' else buf_APL_TYP_OUT; - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - sbuf_to_apl_free <= '0'; - else - sbuf_to_apl_free <= sbuf_to_apl_next_READ; - end if; - end if; - end process; - end generate; - - gen_apl_nonsbuf : if SECURE_MODE_TO_APL = 0 generate - reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; - reg_APL_DATA_OUT <= next_APL_DATA_OUT; - reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; - reg_APL_TYP_OUT <= next_APL_TYP_OUT; - sbuf_to_apl_free <= APL_READ_IN; - end generate; - - next_APL_DATA_OUT <= fifo_to_apl_data_out; - next_APL_PACKET_NUM_OUT <= fifo_to_apl_long_packet_num_out; - next_APL_TYP_OUT <= current_fifo_to_apl_packet_type; - APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; - APL_DATA_OUT <= reg_APL_DATA_OUT; - APL_PACKET_NUM_OUT <= reg_APL_PACKET_NUM_OUT; - APL_TYP_OUT <= reg_APL_TYP_OUT; - APL_SEQNR_OUT <= sequence_counter; - - - ---------------------------------------- ---regenerate long packet numbers ---------------------------------------- - fifo_to_int_long_packet_num_out(2) <= fifo_to_int_packet_num_out(1); - fifo_to_int_long_packet_num_out(0) <= fifo_to_int_packet_num_out(0); - fifo_to_int_long_packet_num_out(1) <= not saved_fifo_to_int_long_packet_num_out(1) when last_fifo_to_int_read = '1' and not saved_fifo_to_int_long_packet_num_out(2) = '1' and saved_fifo_to_int_long_packet_num_out(0) = '1' else saved_fifo_to_int_long_packet_num_out(1); - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_fifo_to_int_long_packet_num_out <= (others => '0'); - elsif last_fifo_to_int_read = '1' then - saved_fifo_to_int_long_packet_num_out <= fifo_to_int_long_packet_num_out; - end if; - end if; - end process; - - - fifo_to_apl_long_packet_num_out(2) <= fifo_to_apl_packet_num_out(1); - fifo_to_apl_long_packet_num_out(0) <= fifo_to_apl_packet_num_out(0); - fifo_to_apl_long_packet_num_out(1) <= not saved_fifo_to_apl_long_packet_num_out(1) when last_fifo_to_apl_read = '1' and not saved_fifo_to_apl_long_packet_num_out(2) = '1' and saved_fifo_to_apl_long_packet_num_out(0) = '1' else saved_fifo_to_apl_long_packet_num_out(1); - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_fifo_to_apl_long_packet_num_out <= (others => '0'); - elsif last_fifo_to_apl_read = '1' then - saved_fifo_to_apl_long_packet_num_out <= fifo_to_apl_long_packet_num_out; - end if; - end if; - end process; - ---------------------------------------- --- save packet type ---------------------------------------- - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' or fifo_to_apl_long_packet_num_out = c_F3 then - saved_fifo_to_apl_packet_type <= TYPE_ILLEGAL; - elsif fifo_to_apl_long_packet_num_out = c_H0 then - saved_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0); - end if; - end if; - end process; - --create comb. real packet type - current_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0) when (fifo_to_apl_long_packet_num_out = c_H0) - else saved_fifo_to_apl_packet_type; - ---------------------------------------- --- select data for int direction ---------------------------------------- - - - process(current_combined_header, current_registered_trailer, current_data, out_select) - begin - case out_select is - when HDR => next_INT_REPLY_DATA_OUT <= current_combined_header; - when TRM => next_INT_REPLY_DATA_OUT <= current_registered_trailer; - when others => next_INT_REPLY_DATA_OUT <= current_data; - end case; - end process; - - - - process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1, - combined_header_F2, registered_trailer_F2, registered_trailer_F0, - combined_header_F3, registered_trailer_F3, combined_header_F0) - begin - case master_counter is - when c_F0 => - current_combined_header <= combined_header_F0; - current_registered_trailer <= registered_trailer_F0; - current_data <= fifo_to_int_data_out; - when c_F1 => - current_combined_header <= combined_header_F1; - current_registered_trailer <= registered_trailer_F1; - current_data <= fifo_to_int_data_out; - when c_F2 => - current_combined_header <= combined_header_F2; - current_registered_trailer <= registered_trailer_F2; - current_data <= fifo_to_int_data_out; - when c_F3 => - current_combined_header <= combined_header_F3; - current_registered_trailer <= registered_trailer_F3; - current_data <= fifo_to_int_data_out; - when others => - current_combined_header <= "0000000000000" & TYPE_HDR; - current_registered_trailer <= "0000000000000" & TYPE_TRM; - current_data <= "0000000000000" & TYPE_DAT; - end case; - end process; - - next_INT_REPLY_PACKET_NUM_OUT <= master_counter; - - MASTER_TRANSFER_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - master_counter <= c_H0; - elsif next_INT_REPLY_DATAREADY_OUT = '1' then - if master_counter = c_max_word_number then - master_counter <= (others => '0'); - else - master_counter <= master_counter + 1; - end if; - end if; - end if; - end process; - - ---------------------------------------- --- keep track of fifo read operations ---------------------------------------- - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - fifo_to_apl_read_before <= '0'; - else - last_fifo_to_apl_read <= fifo_to_apl_read; - if fifo_to_apl_read = '1' then - fifo_to_apl_read_before <= '1'; - elsif sbuf_to_apl_free = '1' or throw_away = '1' then - fifo_to_apl_read_before <= '0'; - end if; - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - fifo_to_int_read_before <= '0'; - else - last_fifo_to_int_read <= fifo_to_int_read; - if fifo_to_int_read = '1' then - fifo_to_int_read_before <= '1'; - elsif next_INT_REPLY_DATAREADY_OUT = '1' and master_counter /= "00" then --implies sbuf_free - fifo_to_int_read_before <= '0'; - end if; - end if; - end if; - end process; - - - ---------------------------------------- ---state machine for direction to APL ---------------------------------------- - to_apl : process(fifo_to_apl_full, reg_INT_REPLY_READ_OUT, INT_REPLY_DATAREADY_IN, fifo_to_apl_empty, - fifo_to_apl_long_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, - sbuf_to_apl_free, INT_REPLY_DATA_IN, INT_REPLY_PACKET_NUM_IN, - reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int ) - begin - reg_INT_REPLY_READ_OUT <= not fifo_to_apl_full; - fifo_to_apl_write <= reg_INT_REPLY_READ_OUT and INT_REPLY_DATAREADY_IN; - fifo_to_apl_read <= '0'; - next_APL_DATAREADY_OUT <= '0'; - next_state_to_apl <= state_to_apl; - throw_away <= '0'; - slave_start <= '0'; - slave_end <= '0'; - - case state_to_apl is - when sa_IDLE => - slave_start <= fifo_to_apl_write; - if APL_WRITE_ALL_WORDS = 0 then - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and not fifo_to_apl_long_packet_num_out(2) and sbuf_to_apl_free; - throw_away <= fifo_to_apl_long_packet_num_out(2); - else - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free; - end if; - fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away); - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = c_F3 and sbuf_to_apl_free = '1' then - next_state_to_apl <= sa_INACTIVE; - slave_end <= '1'; - end if; - when sa_INACTIVE => - if state_to_int = INACTIVE then - next_state_to_apl <= sa_IDLE; - end if; - end case; - end process; - ---------------------------------------- ---state machine for direction to INT ---------------------------------------- - to_int : process(state_to_int, APL_SHORT_TRANSFER_IN, APL_SEND_IN, slave_start, - master_counter, sbuf_free, fifo_to_int_empty, sequence_counter, fifo_to_int_read_before, - state_to_apl, master_start, fifo_was_not_empty) - begin - next_state_to_int <= state_to_int; - update_registered_trailer <= '0'; - out_select <= DAT; - next_INT_REPLY_DATAREADY_OUT <= '0'; - next_sequence_counter <= sequence_counter; - fifo_to_int_read <= '0'; - master_start <= '0'; - master_end <= '0'; - next_fifo_was_not_empty <= fifo_was_not_empty or not fifo_to_int_empty; - - case state_to_int is - when INACTIVE => - if slave_start = '1' then - next_state_to_int <= IDLE; - end if; - when IDLE => - next_fifo_was_not_empty <= '0'; - if APL_SEND_IN = '1' then - master_start <= '1'; - if APL_SHORT_TRANSFER_IN = '1' then - next_state_to_int <= SEND_SHORT; - else - next_state_to_int <= SEND_HEADER; - end if; - end if; - when SEND_SHORT => - if APL_SEND_IN = '0' then - update_registered_trailer <= '1'; - next_state_to_int <= SEND_TRAILER; - end if; - when SEND_HEADER => - out_select <= HDR; - next_INT_REPLY_DATAREADY_OUT <= sbuf_free; - if master_counter = c_F3 and sbuf_free = '1' then - next_state_to_int <= RUNNING; - end if; - when RUNNING => - fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); - next_INT_REPLY_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or master_counter(2)); - if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer - update_registered_trailer <= '1'; - if fifo_to_int_empty = '1' and master_counter = c_F3 and sbuf_free = '1' then - next_state_to_int <= SEND_TRAILER; -- immediate stop - else - next_state_to_int <= SHUTDOWN; -- send rest of data / padding - end if; - end if; - when SHUTDOWN => - fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and not master_counter(2); - next_INT_REPLY_DATAREADY_OUT <= sbuf_free and - ((fifo_to_int_read_before or master_counter(2)) or --write data from fifo - (fifo_to_int_empty and not master_counter(2))); --fill with padding words - if master_counter = c_F3 and fifo_to_int_empty = '1' and sbuf_free = '1' then - next_state_to_int <= SEND_TRAILER; - end if; - when SEND_TRAILER => - out_select <= TRM; - next_INT_REPLY_DATAREADY_OUT <= sbuf_free; - if master_counter = "11" and sbuf_free = '1' then - next_state_to_int <= INACTIVE; - next_sequence_counter <= sequence_counter +1; - master_end <= '1'; - end if; - end case; - end process; - - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - state_to_apl <= sa_IDLE; - state_to_int <= INACTIVE; - sequence_counter <= (others => '0'); - fifo_was_not_empty <= '0'; - else - state_to_apl <= next_state_to_apl; - state_to_int <= next_state_to_int; - sequence_counter <= next_sequence_counter; - fifo_was_not_empty <= next_fifo_was_not_empty; - end if; - end if; - end process; - - - ---------------------------------------- --- ---------------------------------------- - - --save target address for passive api - reg_hdr_f1: process(CLK) - begin - if rising_edge(CLK) then - if current_fifo_to_apl_packet_type = TYPE_HDR then - if fifo_to_apl_long_packet_num_out = c_F1 then - combined_header_F1 <= fifo_to_apl_data_out; - end if; - end if; - end if; - end process; - -- combine the next header - combined_header_F0 <= APL_MY_ADDRESS_IN; - combined_header_F2 <= (others => '0'); - combined_header_F3(15 downto 14) <= (others => '0'); -- LAY - combined_header_F3(13 downto 12) <= (others => '0'); -- VERS - combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR - combined_header_F3(3 downto 0) <= APL_DTYPE_IN; - combined_trailer_F0 <= (others => '0'); - combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16); - combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 0); - combined_trailer_F3(15 downto 14) <= (others => '0'); -- res. - combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS - combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR - combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN; - - -- connect Transmitter port - fifo_to_int_data_in <= APL_DATA_IN; - fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0); - fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full); - APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing - - -- connect receiver - fifo_to_apl_data_in <= INT_REPLY_DATA_IN; - fifo_to_apl_packet_num_in <= INT_REPLY_PACKET_NUM_IN(2) & INT_REPLY_PACKET_NUM_IN(0); - INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT; - - RUN_OUT_gen : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - APL_RUN_OUT <= '0'; - else - if slave_start = '1' then - APL_RUN_OUT <= '1'; - elsif slave_running = '0' and state_to_int = INACTIVE then - APL_RUN_OUT <= '0'; - end if; - end if; - end if; - end process; - - RUNNING_gen : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - master_running <= '0'; - slave_running <= '0'; - else - if master_start = '1' then - master_running <= '1'; - elsif master_end = '1' then - master_running <= '0'; - end if; - if slave_start = '1' then - slave_running <= '1'; - elsif slave_end = '1' then - slave_running <= '0'; - end if; - end if; - end if; - end process; - - REG3 : process(CLK) - begin - if rising_edge(CLK) then - if update_registered_trailer = '1' then - registered_trailer_F0 <= combined_trailer_F0; - registered_trailer_F1 <= combined_trailer_F1; - registered_trailer_F2 <= combined_trailer_F2; - registered_trailer_F3 <= combined_trailer_F3; - end if; - end if; - end process; - ---for simulation only - - - process(state_to_apl) - begin - case state_to_apl is - when sa_IDLE => state_bits_to_apl <= "000"; - when sa_INACTIVE => state_bits_to_apl <= "100"; - when others => state_bits_to_apl <= "111"; - end case; - end process; - process(state_to_int) - begin - case state_to_int is - when IDLE => state_bits_to_int <= "000"; - when SEND_HEADER => state_bits_to_int <= "001"; - when RUNNING => state_bits_to_int <= "010"; - when SHUTDOWN => state_bits_to_int <= "011"; - when SEND_SHORT => state_bits_to_int <= "100"; - when SEND_TRAILER => state_bits_to_int <= "101"; - when INACTIVE => state_bits_to_int <= "110"; - when others => state_bits_to_int <= "111"; - end case; - end process; - - -end architecture; diff --git a/oldfiles/trb_net16_bram_fifo.vhd b/oldfiles/trb_net16_bram_fifo.vhd deleted file mode 100644 index 4886c36..0000000 --- a/oldfiles/trb_net16_bram_fifo.vhd +++ /dev/null @@ -1,279 +0,0 @@ - ---------------------------------------------------------------------------- --- -- --- Module : fifoctlr_cc_v2.vhd Last Update: 01/07/05 -- --- -- --- Description : FifO controller top level. -- --- Implements a 511x36 FifO w/common read/write clocks. -- --- -- --- The following VHDL code implements a 511x36 FifO in a Virtex2 -- --- device. The inputs are a Clock, a Read Enable, a Write Enable, -- --- Write Data, and a FifO_gsr signal as an initial reset. The outputs -- --- are Read Data, Full, Empty, and the FifOcount outputs, which -- --- indicate how full the FifO is. -- --- -- --- Designer : Nick Camilleri -- --- -- --- Company : Xilinx, Inc. -- --- -- --- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY -- --- WHATSOEVER AND XILINX SPECifICALLY DISCLAIMS ANY -- --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR -- --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. -- --- THEY ARE ONLY INTendED TO BE USED BY XILINX -- --- CUSTOMERS, AND WITHIN XILINX DEVICES. -- --- -- --- Copyright (c) 2000 Xilinx, Inc. -- --- All rights reserved -- --- -- ---------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use work.trb_net_std.all; -library unisim; -use UNISIM.VComponents.all; - -entity trb_net16_bram_fifo is - port (clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - fifo_gsr_in: IN std_logic; - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifocount_out: OUT std_logic_vector(3 downto 0)); -end trb_net16_bram_fifo; - -architecture trb_net16_bram_fifo_arch of trb_net16_bram_fifo is - signal clock: std_logic; - signal read_enable: std_logic; - signal write_enable: std_logic; - signal fifo_gsr: std_logic; - signal read_data: std_logic_vector(17 downto 0) := "000000000000000000"; - signal write_data: std_logic_vector(17 downto 0); - signal full: std_logic; - signal empty: std_logic; - signal read_addr: std_logic_vector(9 downto 0) := "0000000000"; - signal write_addr: std_logic_vector(9 downto 0) := "0000000000"; - signal fcounter: std_logic_vector(9 downto 0) := "0000000000"; - signal read_allow: std_logic; - signal write_allow: std_logic; - signal fcnt_allow: std_logic; - signal fcntandout: std_logic_vector(3 downto 0); - signal ra_or_fcnt0: std_logic; - signal wa_or_fcnt0: std_logic; - signal emptyg: std_logic; - signal fullg: std_logic; - signal gnd_bus: std_logic_vector(17 downto 0); - signal gnd: std_logic; - signal pwr: std_logic; - signal read_after_write: std_logic; - signal read_after_empty: std_logic; - -component BUFG - port ( - I: IN std_logic; - O: OUT std_logic); -end component; - -component RAMB16_S18_S18 - port ( - ADDRA: IN std_logic_vector(9 downto 0); - ADDRB: IN std_logic_vector(9 downto 0); - DIA: IN std_logic_vector(15 downto 0); - DIB: IN std_logic_vector(15 downto 0); - DIPA: IN std_logic_vector(1 downto 0); - DIPB: IN std_logic_vector(1 downto 0); - WEA: IN std_logic; - WEB: IN std_logic; - CLKA: IN std_logic; - CLKB: IN std_logic; - SSRA: IN std_logic; - SSRB: IN std_logic; - ENA: IN std_logic; - ENB: IN std_logic; - DOA: OUT std_logic_vector(15 downto 0); - DOB: OUT std_logic_vector(15 downto 0); - DOPA: OUT std_logic_vector(1 downto 0); - DOPB: OUT std_logic_vector(1 downto 0)); -end component; - -begin - read_enable <= read_enable_in; - write_enable <= write_enable_in; - fifo_gsr <= fifo_gsr_in; - write_data <= write_data_in; - read_data_out <= read_data; - - full_out <= full; - gnd_bus <= "000000000000000000"; - gnd <= '0'; - pwr <= '1'; - empty_out <= (empty or read_after_write) and read_after_empty; - clock <= clock_in; - --------------------------------------------------------------------------- --- -- --- Block RAM instantiation for FifO. Module is 1024x18, of which one -- --- address location is sacrificed for the overall speed of the design. -- --- -- --------------------------------------------------------------------------- - -bram1: RAMB16_S18_S18 port map (ADDRA => read_addr, ADDRB => write_addr, - DIA => gnd_bus(17 downto 2), DIPA => gnd_bus(1 downto 0), - DIB => write_data(17 downto 2), DIPB => write_data(1 downto 0), - WEA => gnd, WEB => pwr, CLKA => clock, CLKB => clock, - SSRA => gnd, SSRB => gnd, ENA => read_allow, ENB => write_allow, - DOA => read_data(17 downto 2), DOPA => read_data(1 downto 0), - DOB => open, DOPB => open ); - ---------------------------------------------------------------- --- -- --- Set allow flags, which control the clock enables for -- --- read, write, and count operations. -- --- -- ---------------------------------------------------------------- - -write_allow <= write_enable AND NOT fullg; -read_allow <= (read_enable or read_after_write) AND NOT empty;-- ; -fcnt_allow <= write_allow XOR read_allow; -- and not read_after_write - -proc33: process (clock) -begin - if rising_edge(clock) then - if (fifo_gsr = '1') then - read_after_write <= '0'; - else - if empty = '1' and read_after_empty='1' and write_enable = '1' then - read_after_write <= '1'; - else - read_after_write <= '0'; - end if; - end if; - end if; -end process; - -process(clock) - begin - if rising_edge(clock) then - if fifo_gsr = '1' or (empty = '0' and emptyg = '1') then - read_after_empty <= empty; - elsif read_enable_in = '1' then - read_after_empty <= '1'; - end if; - end if; - end process; - ---------------------------------------------------------------- --- -- --- Empty flag is set on fifo_gsr (initial), or when on the -- --- next clock cycle, Write Enable is low, and either the -- --- FifOcount is equal to 0, or it is equal to 1 and Read -- --- Enable is high (about to go Empty). -- --- -- ---------------------------------------------------------------- - -ra_or_fcnt0 <= (read_allow OR NOT fcounter(0)); - -emptyg <= (not or_all(fcounter(9 downto 1)) AND ra_or_fcnt0) AND NOT write_allow; - -proc3: process (clock, fifo_gsr) -begin - if rising_edge(clock) then - if (fifo_gsr = '1') then - empty <= '1'; - else - empty <= emptyg; - end if; - end if; -end process proc3; - ---------------------------------------------------------------- --- -- --- Full flag is set on fifo_gsr (but it is cleared on the -- --- first valid clock edge after fifo_gsr is removed), or -- --- when on the next clock cycle, Read Enable is low, and -- --- either the FifOcount is equal to 3FF (hex), or it is -- --- equal to 3FE and the Write Enable is high (about to go -- --- Full). -- --- -- ---------------------------------------------------------------- - ---wa_or_fcnt0 <= (write_allow OR fcounter(0)); -wa_or_fcnt0 <= fcounter(0); -fullg <= (and_all(fcounter(9 downto 1)) AND wa_or_fcnt0 AND NOT read_allow); - -proc4: process (clock, fifo_gsr) -begin - if rising_edge(clock) then - if (fifo_gsr = '1') then - full <= '1'; - else - full <= fullg; - end if; - end if; -end process proc4; - ----------------------------------------------------------------- --- -- --- Generation of Read and Write address pointers. They now -- --- use binary counters, because it is simpler in simulation, -- --- and the previous LFSR implementation wasn't in the -- --- critical path. -- --- -- ----------------------------------------------------------------- - -proc5: process (clock, fifo_gsr) -begin - if rising_edge(clock) then - if (fifo_gsr = '1') then - read_addr <= (others => '0'); - elsif (read_allow = '1') then - read_addr <= read_addr + '1'; - end if; - end if; -end process proc5; - -proc6: process (clock, fifo_gsr) -begin - if rising_edge(clock) then - if (fifo_gsr = '1') then - write_addr <= "0000000000"; - elsif (write_allow = '1') then - write_addr <= write_addr + '1'; - end if; - end if; -end process proc6; - ----------------------------------------------------------------- --- -- --- Generation of FifOcount outputs. Used to determine how -- --- full FifO is, based on a counter that keeps track of how -- --- many words are in the FifO. Also used to generate Full -- --- and Empty flags. Only the upper four bits of the counter -- --- are sent outside the module. -- --- -- ----------------------------------------------------------------- - -proc7: process (clock, fifo_gsr) -begin - if rising_edge(clock) then - if (fifo_gsr = '1') then - fcounter <= "0000000000"; - elsif (fcnt_allow = '1') then - if (read_allow = '1') then -- and read_after_write = '0' - fcounter <= fcounter - '1'; - else - fcounter <= fcounter + '1'; - end if; - end if; - end if; -end process proc7; - -fifocount_out <= fcounter(9 downto 6); - -end architecture; - diff --git a/oldfiles/trb_net16_endpoint_1_trg_2_data_1_regio.vhd b/oldfiles/trb_net16_endpoint_1_trg_2_data_1_regio.vhd deleted file mode 100644 index 8aadcaa..0000000 --- a/oldfiles/trb_net16_endpoint_1_trg_2_data_1_regio.vhd +++ /dev/null @@ -1,960 +0,0 @@ --- the full endpoint for HADES: trg, data, data, regio - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - - - -entity trb_net16_endpoint_1_trg_2_api_1_regio is - generic ( - USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE); - IBUF_DEPTH : channel_config_t := (0,6,6,6); - FIFO_TO_INT_DEPTH : channel_config_t := (0,6,6,6); - FIFO_TO_APL_DEPTH : channel_config_t := (0,6,6,6); - IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; - INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); - REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); - SCTR_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers - SCTR_NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers - --standard values for output registers - SCTR_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); - --set to 0 for unused ctrl registers to save resources - SCTR_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; - --set to 0 for each unused bit in a register - SCTR_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); - --no data / address out? - SCTR_USE_DATA_PORT : integer := c_NO; - SCTR_USE_1WIRE_INTERFACE : integer := c_YES; - SCTR_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - SCTR_INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); - SCTR_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - SCTR_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - SCTR_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Media direction port - MED_DATAREADY_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - MED_STAT_OP : in std_logic_vector (15 downto 0); - MED_CTRL_OP : out std_logic_vector (15 downto 0); - - -- LVL1 trigger APL - LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - LVL1_GOT_TRIGGER_OUT : out std_logic; - LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0); - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; - LVL1_RELEASE_IN : in std_logic := '0'; - - -- IPU-Data Channel APL - IPUD_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000"; - IPUD_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00"; - IPUD_APL_DATAREADY_IN : in std_logic := '0'; - IPUD_APL_READ_OUT : out std_logic; - IPUD_APL_SHORT_TRANSFER_IN: in std_logic := '0'; - IPUD_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0"; - IPUD_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000"; - IPUD_APL_SEND_IN : in std_logic:= '0'; - IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000"; - IPUD_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - IPUD_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - IPUD_APL_TYP_OUT : out std_logic_vector (2 downto 0); - IPUD_APL_DATAREADY_OUT : out std_logic; - IPUD_APL_READ_IN : in std_logic:= '0'; - IPUD_APL_RUN_OUT : out std_logic; - IPUD_APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- LVL2-Data Channel APL - LVL2_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000"; - LVL2_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00"; - LVL2_APL_DATAREADY_IN : in std_logic := '0'; - LVL2_APL_READ_OUT : out std_logic; - LVL2_APL_SHORT_TRANSFER_IN: in std_logic := '0'; - LVL2_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0"; - LVL2_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000"; - LVL2_APL_SEND_IN : in std_logic:= '0'; - LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000"; - LVL2_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - LVL2_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - LVL2_APL_TYP_OUT : out std_logic_vector (2 downto 0); - LVL2_APL_DATAREADY_OUT : out std_logic; - LVL2_APL_READ_IN : in std_logic:= '0'; - LVL2_APL_RUN_OUT : out std_logic; - LVL2_APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - - -- Slow Control Data Port - SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - SCTR_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); - SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0) := (others => '0'); - SCTR_REGISTERS_OUT : out std_logic_vector(32*2**(SCTR_NUM_CTRL_REGS)-1 downto 0); - --following ports only used when using internal data port - SCTR_ADDR_OUT : out std_logic_vector(16-1 downto 0); - SCTR_READ_ENABLE_OUT : out std_logic; - SCTR_WRITE_ENABLE_OUT : out std_logic; - SCTR_DATA_OUT : out std_logic_vector(32-1 downto 0); - SCTR_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); - SCTR_DATAREADY_IN : in std_logic := '0'; - SCTR_NO_MORE_DATA_IN : in std_logic := '0'; - --IDRAM is used if no 1-wire interface, onewire used otherwise - SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); - SCTR_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); - SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; - SCTR_IDRAM_WR_IN : in std_logic := '0'; - SCTR_ONEWIRE_INOUT : inout std_logic; - --Additional r/w access to ctrl registers - SCTR_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); - SCTR_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0); - SCTR_EXT_REG_WRITE_IN : in std_logic := '0'; - SCTR_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0'); - -- Status - MPLEX_CTRL : in std_logic_vector (31 downto 0) := (others => '0'); - STAT_CTRL_INIT_BUFFER : in std_logic_vector (4*32-1 downto 0) := (others => '0'); - STAT_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); - STAT_GEN_1 : out std_logic_vector (31 downto 0); -- General Status - STAT_GEN_2 : out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0') - ); -end entity; - - - - - -architecture trb_net16_endpoint_1_trg_2_api_1_regio_arch of trb_net16_endpoint_1_trg_2_api_1_regio is - - component trb_net_onewire is - generic( - USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; - CLK_PERIOD : integer := 10 --clk period in ns - ); - port( - CLK : in std_logic; - RESET : in std_logic; - --connection to 1-wire interface - ONEWIRE : inout std_logic; - --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT: out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net16_regIO is - generic ( - REGISTER_WIDTH : integer range 32 to 32 := 32; - ADDRESS_WIDTH : integer range 8 to 16 := 16; - NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers - NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers - --standard values for output registers - INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := - (others => '0'); - --set to 0 for unused ctrl registers to save resources - USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; - --set to 0 for each unused bit in a register - USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := - (others => '1'); - USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Port to API - API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - API_SHORT_TRANSFER_OUT : out std_logic; - API_DTYPE_OUT : out std_logic_vector (3 downto 0); - API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - API_SEND_OUT : out std_logic; - API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); - -- Receiver port - API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_TYP_IN : in std_logic_vector (2 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - -- APL Control port - API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); - - --Port to write Unique ID - IDRAM_DATA_IN : in std_logic_vector(15 downto 0); - IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); - IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); - IDRAM_WR_IN : in std_logic; - MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - - --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); - --Custom Register in / out - REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); - REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); - --Internal Data Port - DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0); - DAT_READ_ENABLE_OUT : out std_logic; - DAT_WRITE_ENABLE_OUT: out std_logic; - DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0); - --Data input can only be used as reaction on read or write access. write operation should return data - --if successful - DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0); - DAT_DATAREADY_IN : in std_logic; - DAT_NO_MORE_DATA_IN : in std_logic; - --finish transmission, when reading from a fifo and it got empty - --Additional write access to ctrl registers - EXT_REG_DATA_IN : in std_logic_vector(31 downto 0); - EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0); - EXT_REG_WRITE_IN : in std_logic; - EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net16_iobuf is - generic ( - IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_ERROR_IN: in std_logic_vector (2 downto 0); - - - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN: in std_logic; - - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT: out std_logic; - - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); - CTRL_GEN: in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_api_base is - generic ( - API_TYPE : integer range 0 to 1 := c_API_ACTIVE; - FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; - FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted - APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in std_logic; -- - APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL_READ_IN: in std_logic; -- Read data word - - -- APL Control port - APL_RUN_OUT: out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_MASTER_DATAREADY_OUT: out std_logic; - INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_IN: in std_logic; - - INT_MASTER_DATAREADY_IN: in std_logic; - INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_OUT: out std_logic; - - - INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the SLAVE path) - INT_SLAVE_DATAREADY_OUT: out std_logic; - INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_IN: in std_logic; - - INT_SLAVE_DATAREADY_IN: in std_logic; - INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_OUT: out std_logic; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); - end component; - - - - component trb_net16_io_multiplexer is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); - MED_READ_IN: in STD_LOGIC; - - -- Internal direction port - INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); - end component; - - component trb_net16_term_buf is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic - ); - end component; - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := 0; - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr - -- Status and control port - ); - end component; -signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0); -signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0); - -signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0); -signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0); - -signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0); -signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0); - -signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0); -signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); -signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); -signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0); - --- for the connection to the multiplexer -signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0); -signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); -signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); -signal MED_IO_READ_OUT : std_logic_vector(3 downto 0); - -signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0); -signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); -signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); -signal MED_IO_READ_IN : std_logic_vector(7 downto 0); - -signal buf_APL_DATA_IN : std_logic_vector(3*c_DATA_WIDTH-1 downto 0); -signal buf_APL_PACKET_NUM_IN : std_logic_vector(3*c_NUM_WIDTH-1 downto 0); -signal buf_APL_DATAREADY_IN : std_logic_vector(2 downto 0); -signal buf_APL_READ_OUT : std_logic_vector(2 downto 0); -signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(2 downto 0); -signal buf_APL_DTYPE_IN : std_logic_vector(3*4-1 downto 0); -signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(3*32-1 downto 0); -signal buf_APL_SEND_IN : std_logic_vector(2 downto 0); -signal buf_APL_TARGET_ADDRESS_IN : std_logic_vector(3*16-1 downto 0); -signal buf_APL_DATA_OUT : std_logic_vector(3*c_DATA_WIDTH-1 downto 0); -signal buf_APL_PACKET_NUM_OUT : std_logic_vector(3*c_NUM_WIDTH-1 downto 0); -signal buf_APL_DATAREADY_OUT : std_logic_vector(2 downto 0); -signal buf_APL_READ_IN : std_logic_vector(2 downto 0); -signal buf_APL_TYP_OUT : std_logic_vector(3*3-1 downto 0); -signal buf_APL_RUN_OUT : std_logic_vector(2 downto 0); -signal buf_APL_SEQNR_OUT : std_logic_vector(3*8-1 downto 0); - -signal MY_ADDRESS : std_logic_vector(15 downto 0); - -signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0); -signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0); -signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); -signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0); -signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); -signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0); - -signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); - -signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); -signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); -signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); -signal buf_IDRAM_WR_IN : std_logic; - -begin - - MED_CTRL_OP(15) <= MED_STAT_OP(15); - MED_CTRL_OP(14 downto 0) <= (others => '0'); - - --Connections for data channel - genbuffers : for i in 0 to 3 generate - geniobuf: if USE_CHANNEL(i) = c_YES generate - IOBUF: trb_net16_iobuf - generic map ( - IBUF_DEPTH => IBUF_DEPTH(i), - IBUF_SECURE_MODE => IBUF_SECURE_MODE(i), - SBUF_VERSION => 0, - USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i), - USE_VENDOR_CORES => c_YES, - USE_CHECKSUM => cfg_USE_CHECKSUM(i), - INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i), - REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i) - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), - MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), - MED_INIT_READ_IN => MED_IO_READ_IN(i*2), - - MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), - MED_DATA_IN => MED_IO_DATA_IN, - MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, - MED_READ_OUT => MED_IO_READ_OUT(i), - MED_ERROR_IN => MED_ERROR_IN, - - MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), - MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), - - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), - - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), - - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), - - -- Status and control port - STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32), - STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32), - CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32), - STAT_CTRL_IBUF_BUFFER => buf_STAT_CTRL_INIT_BUFFER(32*(i+1)-1 downto i*32) - ); - genactapi : if API_TYPE(i) = c_API_ACTIVE and i /= 0 generate - DAT_ACTIVE_API: trb_net16_api_base - generic map ( - API_TYPE => API_TYPE(i), - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i), - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i), - FORCE_REPLY => cfg_FORCE_REPLY(i), - SBUF_VERSION => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - APL_DATAREADY_IN => buf_APL_DATAREADY_IN(i), - APL_READ_OUT => buf_APL_READ_OUT(i), - APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(i), - APL_DTYPE_IN => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4), - APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32), - APL_SEND_IN => buf_APL_SEND_IN(i), - APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((i+1)*16-1 downto i*16), - -- Receiver port - APL_DATA_OUT => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - APL_TYP_OUT => buf_APL_TYP_OUT((i+1)*3-1 downto i*3), - APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(i), - APL_READ_IN => buf_APL_READ_IN(i), - -- APL Control port - APL_RUN_OUT => buf_APL_RUN_OUT(i), - APL_MY_ADDRESS_IN => MY_ADDRESS, - APL_SEQNR_OUT => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8), - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), - INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), - INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), - INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i), - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), - INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i), - INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), - INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), - -- Status and control port - STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), - STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) - ); - end generate; - genpasapi : if API_TYPE(i) = c_API_PASSIVE and i /= 0 generate - constant j : integer := i-1; - begin - DAT_PASSIVE_API: trb_net16_api_base - generic map ( - API_TYPE => API_TYPE(i), - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i), - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i), - FORCE_REPLY => cfg_FORCE_REPLY(i), - SBUF_VERSION => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), - APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), - APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j), - APL_READ_OUT => buf_APL_READ_OUT(j), - APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j), - APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4), - APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32), - APL_SEND_IN => buf_APL_SEND_IN(j), - APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((j+1)*16-1 downto j*16), - -- Receiver port - APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), - APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), - APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3), - APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j), - APL_READ_IN => buf_APL_READ_IN(j), - -- APL Control port - APL_RUN_OUT => buf_APL_RUN_OUT(j), - APL_MY_ADDRESS_IN => MY_ADDRESS, - APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8), - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), - INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), - INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), - INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i), - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), - INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i), - INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), - INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), - -- Status and control port - STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), - STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) - ); - end generate; - gentrgapi : if i = 0 generate - apl_to_buf_INIT_DATAREADY(0) <= '0'; - apl_to_buf_INIT_DATA(15 downto 0) <= (others => '0'); - apl_to_buf_INIT_PACKET_NUM(1 downto 0) <= "00"; - buf_to_apl_REPLY_READ(0) <= '1'; - trglvl1 : trb_net16_term - generic map( - USE_APL_PORT => c_YES, - SECURE_MODE => std_TERM_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), - INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_READ_IN => apl_to_buf_REPLY_READ(i), - - INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), - INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_READ_OUT => buf_to_apl_INIT_READ(i), - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => LVL1_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => LVL1_SEQNR_OUT, - APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => LVL1_RELEASE_IN, - APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN - ); - end generate; - end generate; - gentermbuf: if USE_CHANNEL(i) = c_NO generate - termbuf: trb_net16_term_buf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), - MED_DATA_IN => MED_IO_DATA_IN, - MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, - MED_READ_OUT => MED_IO_READ_OUT(i), - - MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), - MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), - MED_INIT_READ_IN => MED_IO_READ_IN(i*2), - MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), - MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1) - ); - end generate; - end generate; - - - buf_APL_DATA_IN(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH) <= IPUD_APL_DATA_IN; - buf_APL_DATA_IN(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH) <= LVL2_APL_DATA_IN; - buf_APL_PACKET_NUM_IN(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH) <= IPUD_APL_PACKET_NUM_IN; - buf_APL_PACKET_NUM_IN(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH) <= LVL2_APL_PACKET_NUM_IN; - buf_APL_DATAREADY_IN(0) <= IPUD_APL_DATAREADY_IN; - buf_APL_DATAREADY_IN(1) <= LVL2_APL_DATAREADY_IN; - IPUD_APL_READ_OUT <= buf_APL_READ_OUT(0); - LVL2_APL_READ_OUT <= buf_APL_READ_OUT(1); - buf_APL_SHORT_TRANSFER_IN(0) <= IPUD_APL_SHORT_TRANSFER_IN; - buf_APL_SHORT_TRANSFER_IN(1) <= LVL2_APL_SHORT_TRANSFER_IN; - buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN; - buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN; - buf_APL_ERROR_PATTERN_IN(1*32-1 downto 0*32) <= IPUD_APL_ERROR_PATTERN_IN; - buf_APL_ERROR_PATTERN_IN(2*32-1 downto 1*32) <= LVL2_APL_ERROR_PATTERN_IN; - buf_APL_SEND_IN(0) <= IPUD_APL_SEND_IN; - buf_APL_SEND_IN(1) <= LVL2_APL_SEND_IN; - buf_APL_TARGET_ADDRESS_IN(1*16-1 downto 0*16) <= IPUD_APL_TARGET_ADDRESS_IN; - buf_APL_TARGET_ADDRESS_IN(2*16-1 downto 1*16) <= LVL2_APL_TARGET_ADDRESS_IN; - - IPUD_APL_DATA_OUT <= buf_APL_DATA_OUT(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH); - LVL2_APL_DATA_OUT <= buf_APL_DATA_OUT(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH); - IPUD_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH); - LVL2_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH); - IPUD_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(0); - LVL2_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(1); - buf_APL_READ_IN(0) <= IPUD_APL_READ_IN; - buf_APL_READ_IN(1) <= LVL2_APL_READ_IN; - IPUD_APL_TYP_OUT <= buf_APL_TYP_OUT(2 downto 0); - LVL2_APL_TYP_OUT <= buf_APL_TYP_OUT(5 downto 3); - - buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN; - buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN; - IPUD_APL_RUN_OUT <= buf_APL_RUN_OUT(0); - LVL2_APL_RUN_OUT <= buf_APL_RUN_OUT(1); - IPUD_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(1*8-1 downto 0*8); - LVL2_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(2*8-1 downto 1*8); - - gen_regio : if USE_CHANNEL(c_SLOW_CTRL_CHANNEL) = c_YES generate - regIO : trb_net16_regIO - generic map( - REGISTER_WIDTH => 32, - ADDRESS_WIDTH => 16, - NUM_STAT_REGS => SCTR_NUM_STAT_REGS, - NUM_CTRL_REGS => SCTR_NUM_CTRL_REGS, - --standard values for output registers - INIT_CTRL_REGS => SCTR_INIT_CTRL_REGS, - --set to 0 for unused ctrl registers to save resources - USED_CTRL_REGS => SCTR_USED_CTRL_REGS, - --set to 0 for each unused bit in a register - USED_CTRL_BITMASK => SCTR_USED_CTRL_BITMASK, - --no data / address out? - USE_DAT_PORT => SCTR_USE_DATA_PORT, - INIT_ADDRESS => SCTR_INIT_ADDRESS, - INIT_UNIQUE_ID => SCTR_INIT_UNIQUE_ID, - COMPILE_TIME => SCTR_COMPILE_TIME, - COMPILE_VERSION => SCTR_COMPILE_VERSION, - HARDWARE_VERSION => SCTR_HARDWARE_VERSION - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- Port to API - API_DATA_OUT => buf_APL_DATA_IN(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH), - API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH), - API_DATAREADY_OUT => buf_APL_DATAREADY_IN(2), - API_READ_IN => buf_APL_READ_OUT(2), - API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(2), - API_DTYPE_OUT => buf_APL_DTYPE_IN(3*4-1 downto 2*4), - API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN(3*32-1 downto 2*32), - API_SEND_OUT => buf_APL_SEND_IN(2), - API_TARGET_ADDRESS_OUT => buf_APL_TARGET_ADDRESS_IN(3*16-1 downto 2*16), - API_DATA_IN => buf_APL_DATA_OUT(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH), - API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH), - API_TYP_IN => buf_APL_TYP_OUT(3*3-1 downto 2*3), - API_DATAREADY_IN => buf_APL_DATAREADY_OUT(2), - API_READ_OUT => buf_APL_READ_IN(2), - API_RUN_IN => buf_APL_RUN_OUT(2), - API_SEQNR_IN => buf_APL_SEQNR_OUT(3*8-1 downto 2*8), - --Port to write Unique ID - IDRAM_DATA_IN => buf_IDRAM_DATA_IN, - IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT, - IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN, - IDRAM_WR_IN => buf_IDRAM_WR_IN, - MY_ADDRESS_OUT => MY_ADDRESS, - --Common Register in / out - COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, - COMMON_CTRL_REG_OUT => SCTR_COMMON_CTRL_REG_OUT, - --Custom Register in / out - REGISTERS_IN => SCTR_REGISTERS_IN, - REGISTERS_OUT => SCTR_REGISTERS_OUT, - --following ports only used when no internal register is accessed - DAT_ADDR_OUT => SCTR_ADDR_OUT, - DAT_READ_ENABLE_OUT => SCTR_READ_ENABLE_OUT, - DAT_WRITE_ENABLE_OUT => SCTR_WRITE_ENABLE_OUT, - DAT_DATA_OUT => SCTR_DATA_OUT, - DAT_DATA_IN => SCTR_DATA_IN, - DAT_DATAREADY_IN => SCTR_DATAREADY_IN, - DAT_NO_MORE_DATA_IN => SCTR_NO_MORE_DATA_IN, - EXT_REG_DATA_IN => SCTR_EXT_REG_DATA_IN, - EXT_REG_DATA_OUT => SCTR_EXT_REG_DATA_OUT, - EXT_REG_WRITE_IN => SCTR_EXT_REG_WRITE_IN, - EXT_REG_ADDR_IN => SCTR_EXT_REG_ADDR_IN, - STAT => SCTR_REGIO_STAT - ); - end generate; - - gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate - buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN; - buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN; - buf_IDRAM_WR_IN <= SCTR_IDRAM_WR_IN; - SCTR_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT; - SCTR_ONEWIRE_INOUT <= '0'; - buf_COMMON_STAT_REG_IN <= SCTR_COMMON_STAT_REG_IN; - end generate; - gen_1wire : if SCTR_USE_1WIRE_INTERFACE = 1 generate - buf_COMMON_STAT_REG_IN(19 downto 0) <= SCTR_COMMON_STAT_REG_IN(19 downto 0); - buf_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32) <= SCTR_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32); - - SCTR_IDRAM_DATA_OUT <= (others => '0'); - - onewire_interface : trb_net_onewire - generic map( - USE_TEMPERATURE_READOUT => c_YES, - CLK_PERIOD => 10 - ) - port map( - CLK => CLK, - RESET => RESET, - --connection to 1-wire interface - ONEWIRE => SCTR_ONEWIRE_INOUT, - --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT => buf_IDRAM_DATA_IN, - ADDR_OUT => buf_IDRAM_ADDR_IN, - WRITE_OUT=> buf_IDRAM_WR_IN, - TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20), - STAT => open - ); - end generate; - - - MPLEX: trb_net16_io_multiplexer - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - INT_DATAREADY_OUT => MED_IO_DATAREADY_IN, - INT_DATA_OUT => MED_IO_DATA_IN, - INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN, - INT_READ_IN => MED_IO_READ_OUT, - INT_DATAREADY_IN => MED_IO_DATAREADY_OUT, - INT_DATA_IN => MED_IO_DATA_OUT, - INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT, - INT_READ_OUT => MED_IO_READ_IN, - CTRL => MPLEX_CTRL - ); - - -buf_STAT_CTRL_INIT_BUFFER <= STAT_CTRL_INIT_BUFFER; -buf_CTRL_GEN <= CTRL_GEN; -STAT_GEN_1 <= (others => '0'); -STAT_GEN_2 <= (others => '0'); - -end architecture; - diff --git a/oldfiles/trb_net16_endpoint_2_trg.vhd b/oldfiles/trb_net16_endpoint_2_trg.vhd deleted file mode 100644 index a329354..0000000 --- a/oldfiles/trb_net16_endpoint_2_trg.vhd +++ /dev/null @@ -1,461 +0,0 @@ - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - - - -entity trb_net16_endpoint_2_trg is - generic ( - --channel numbers - LVL1_CHANNEL_NUM : integer := 0; - LVL2_CHANNEL_NUM : integer := 1; - --register error_pattern_in? - LVL1_SECURE_MODE : integer := std_TERM_SECURE_MODE; - LVL2_SECURE_MODE : integer := std_TERM_SECURE_MODE - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Media direction port - MED_DATAREADY_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - MED_STAT_OP : in std_logic_vector (15 downto 0); - MED_CTRL_OP : out std_logic_vector (15 downto 0); - - -- LVL1 trigger APL - LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - LVL1_GOT_TRIGGER_OUT : out std_logic; - LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0); - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - LVL1_RELEASE_IN : in std_logic; - - -- LVL2 trigger APL - LVL2_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - LVL2_GOT_TRIGGER_OUT : out std_logic; - LVL2_DTYPE_OUT : out std_logic_vector(3 downto 0); - LVL2_SEQNR_OUT : out std_logic_vector(7 downto 0); - LVL2_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - LVL2_RELEASE_IN : in std_logic - ); -end entity; - - - - - -architecture trb_net16_endpoint_2_trg_arch of trb_net16_endpoint_2_trg is - - - - component trb_net16_iobuf is - generic ( - IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_ERROR_IN: in std_logic_vector (2 downto 0); - - - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN: in std_logic; - - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT: out std_logic; - - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0); - CTRL_GEN: in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - - - - component trb_net16_io_multiplexer is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); - MED_READ_IN: in STD_LOGIC; - - -- Internal direction port - INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); - end component; - - component trb_net16_term_buf is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN: in std_logic; - - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN: in std_logic; - - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic - ); - end component; - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := 0; - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr - -- Status and control port - ); - end component; - constant channels : integer := 2**(c_MUX_WIDTH-1); -signal apl_to_buf_INIT_DATAREADY: std_logic_vector(channels-1 downto 0); -signal apl_to_buf_INIT_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0); -signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0); -signal apl_to_buf_INIT_READ : std_logic_vector(channels-1 downto 0); - -signal buf_to_apl_INIT_DATAREADY: std_logic_vector(channels-1 downto 0); -signal buf_to_apl_INIT_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0); -signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0); -signal buf_to_apl_INIT_READ : std_logic_vector(channels-1 downto 0); - -signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(channels-1 downto 0); -signal apl_to_buf_REPLY_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0); -signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0); -signal apl_to_buf_REPLY_READ : std_logic_vector(channels-1 downto 0); - -signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(channels-1 downto 0); -signal buf_to_apl_REPLY_DATA : std_logic_vector (channels*c_DATA_WIDTH-1 downto 0); -signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (channels*c_NUM_WIDTH-1 downto 0); -signal buf_to_apl_REPLY_READ : std_logic_vector(channels-1 downto 0); - --- for the connection to the multiplexer -signal MED_IO_DATAREADY_IN : std_logic_vector(channels-1 downto 0); -signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); -signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); -signal MED_IO_READ_OUT : std_logic_vector(channels-1 downto 0); - -signal MED_IO_DATAREADY_OUT : std_logic_vector(channels*2-1 downto 0); -signal MED_IO_DATA_OUT : std_logic_vector (channels*2*c_DATA_WIDTH-1 downto 0); -signal MED_IO_PACKET_NUM_OUT : std_logic_vector (channels*2*c_NUM_WIDTH-1 downto 0); -signal MED_IO_READ_IN : std_logic_vector(channels*2-1 downto 0); - -signal MY_ADDRESS : std_logic_vector(15 downto 0); - -signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (channels*32-1 downto 0); -signal buf_STAT_GEN : std_logic_vector(32*channels-1 downto 0); -signal buf_STAT_INIT_BUFFER : std_logic_vector(32*channels-1 downto 0); -signal buf_CTRL_GEN : std_logic_vector(32*channels-1 downto 0); -signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*channels-1 downto 0); -signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0); - -signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); - - -begin - - MED_CTRL_OP(15) <= MED_STAT_OP(15); - MED_CTRL_OP(14 downto 0) <= (others => '0'); - - --Connections for data channel - genbuffers : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate - geniobuf: if i = LVL1_CHANNEL_NUM or i = LVL2_CHANNEL_NUM generate - IOBUF: trb_net16_iobuf - generic map ( - IBUF_DEPTH => 0, - IBUF_SECURE_MODE => c_YES, - SBUF_VERSION => 0, - USE_ACKNOWLEDGE => c_NO, - USE_VENDOR_CORES => c_YES, - USE_CHECKSUM => c_NO, - INIT_CAN_SEND_DATA => c_NO, - REPLY_CAN_SEND_DATA => c_YES - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), - MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), - MED_INIT_READ_IN => MED_IO_READ_IN(i*2), - - MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), - MED_DATA_IN => MED_IO_DATA_IN, - MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, - MED_READ_OUT => MED_IO_READ_OUT(i), - MED_ERROR_IN => MED_ERROR_IN, - - MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), - MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), - - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), - - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), - - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), - - -- Status and control port - STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32), - STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32), - CTRL_GEN => (others => '0'), - STAT_CTRL_IBUF_BUFFER => (others => '0') - ); - - - genlvl1 : if i = LVL1_CHANNEL_NUM generate - apl_to_buf_INIT_DATAREADY(i) <= '0'; - apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); - apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= "00"; - buf_to_apl_REPLY_READ(i) <= '1'; - trglvl1 : trb_net16_term - generic map( - USE_APL_PORT => c_YES, - SECURE_MODE => LVL1_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), - INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_READ_IN => apl_to_buf_REPLY_READ(i), - - INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), - INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_READ_OUT => buf_to_apl_INIT_READ(i), - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => LVL1_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => LVL1_SEQNR_OUT, - APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => LVL1_RELEASE_IN, - APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN - ); - end generate; - genlvl2 : if i = LVL2_CHANNEL_NUM generate - apl_to_buf_INIT_DATAREADY(i) <= '0'; - apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); - apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= "00"; - buf_to_apl_REPLY_READ(i) <= '1'; - trglvl1 : trb_net16_term - generic map( - USE_APL_PORT => c_YES, - SECURE_MODE => LVL2_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), - INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_READ_IN => apl_to_buf_REPLY_READ(i), - - INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), - INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_READ_OUT => buf_to_apl_INIT_READ(i), - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => LVL2_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => LVL2_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => LVL2_SEQNR_OUT, - APL_GOT_TRM => LVL2_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => LVL2_RELEASE_IN, - APL_ERROR_PATTERN_IN => LVL2_ERROR_PATTERN_IN - ); - end generate; - end generate; - gentermbuf: if i /= LVL1_CHANNEL_NUM and i /= LVL2_CHANNEL_NUM generate - termbuf: trb_net16_term_buf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), - MED_DATA_IN => MED_IO_DATA_IN, - MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, - MED_READ_OUT => MED_IO_READ_OUT(i), - - MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), - MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), - MED_INIT_READ_IN => MED_IO_READ_IN(i*2), - MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), - MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1) - ); - end generate; - end generate; - - - MPLEX: trb_net16_io_multiplexer - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - INT_DATAREADY_OUT => MED_IO_DATAREADY_IN, - INT_DATA_OUT => MED_IO_DATA_IN, - INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN, - INT_READ_IN => MED_IO_READ_OUT, - INT_DATAREADY_IN => MED_IO_DATAREADY_OUT, - INT_DATA_IN => MED_IO_DATA_OUT, - INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT, - INT_READ_OUT => MED_IO_READ_IN, - CTRL => (others => '0') - ); - - -end architecture; - diff --git a/oldfiles/trb_net16_endpoint_2_trg_1_api.vhd b/oldfiles/trb_net16_endpoint_2_trg_1_api.vhd deleted file mode 100644 index f2b5d97..0000000 --- a/oldfiles/trb_net16_endpoint_2_trg_1_api.vhd +++ /dev/null @@ -1,990 +0,0 @@ - --- NOT UP TO DATE - - - - - - - - - - - - - - - - - - - - - - - - --- this is an trigger receiver combined with a passive api - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net16_endpoint_2_trg_1_api is - - generic ( - --api type for data channel - API_TYPE : integer range 0 to 1 := 0; - --Fifo for data channel - DAT_INIT_DEPTH : integer range 0 to 7 := 2; - DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here - DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1; - DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1; - --SBUF_DATA_VERSION : integer range 0 to 1 := 0; - --Fifo for TRG channel - TRG1_INIT_DEPTH : integer range 0 to 7 := 0; - TRG1_REPLY_DEPTH : integer range 0 to 7 := 0; - TRG1_SECURE_MODE : integer range 0 to 1 := 0; - TRG2_INIT_DEPTH : integer range 0 to 7 := 0; - TRG2_REPLY_DEPTH : integer range 0 to 7 := 0; - TRG2_SECURE_MODE : integer range 0 to 1 := 0; - --SBUF_TRG_VERSION : integer range 0 to 1 := 0; - --Multiplexer - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0; - TRG1_CHANNEL : integer range 0 to 3 := 0; --range 0 to 2**(MUX_WIDTH-1) - TRG2_CHANNEL : integer range 0 to 3 := 1; --range 0 to 2**(MUX_WIDTH-1) - DAT_CHANNEL : integer range 0 to 3 := 3; --range 0 to 2**(MUX_WIDTH-1) - --General - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_READ_IN: in std_logic; -- Media is reading - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - -- APL Transceiver port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in std_logic; -- - APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in std_logic; -- Release sending of the data - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL_READ_IN: in std_logic; -- Read data word - APL_RUN_OUT: out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0); - - -- TRG1 Receiver port - TRG1_GOT_TRIGGER_OUT : out std_logic; - TRG1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - TRG1_DTYPE_OUT : out std_logic_vector(3 downto 0); - TRG1_SEQNR_OUT : out std_logic_vector(7 downto 0); - TRG1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - TRG1_RELEASE_IN : in std_logic; - - -- TRG2 Receiver port - TRG2_GOT_TRIGGER_OUT : out std_logic; - TRG2_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - TRG2_DTYPE_OUT : out std_logic_vector(3 downto 0); - TRG2_SEQNR_OUT : out std_logic_vector(7 downto 0); - TRG2_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - TRG2_RELEASE_IN : in std_logic; - - -- Status and control port => for debugging - STAT_DAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_DAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_DAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_DAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_DAT_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_DAT_GEN: in std_logic_vector (31 downto 0); - CTRL_DAT_LOCKED: in std_logic_vector (31 downto 0); - STAT_DAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_DAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG1_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG1_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG1_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG1_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG1_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_TRG1_GEN: in std_logic_vector (31 downto 0); - CTRL_TRG1_LOCKED: in std_logic_vector (31 downto 0); - STAT_TRG1_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG1_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG2_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG2_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG2_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG2_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG2_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_TRG2_GEN: in std_logic_vector (31 downto 0); - CTRL_TRG2_LOCKED: in std_logic_vector (31 downto 0); - STAT_TRG2_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG2_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - STAT_MPLEX: out std_logic_vector(31 downto 0); - MPLEX_CTRL: in std_logic_vector (31 downto 0); - DAT_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - DAT_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_endpoint_2_trg_1_api_arch of trb_net16_endpoint_2_trg_1_api_endpoint is - - component trb_net16_iobuf is - - generic ( - INIT_DEPTH : integer := 1; - REPLY_DEPTH : integer := 1 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_INIT_READ_IN: in std_logic; - - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT: out std_logic; - - INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_api_base is - generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 1; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path - -- if set to 0, no buffer is used - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := 1; - SECURE_MODE : integer range 0 to 1 := 0 - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these must be available when hold_trm goes low - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - INT_READ_IN: in std_logic; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_READ_OUT: out std_logic; - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr - -- Status and control port - ); - end component; - - component trb_net16_io_multiplexer is - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_term_buf is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic - ); - end component; -signal apl_to_buf_DAT_INIT_DATAREADY: std_logic; -signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT_INIT_READ : std_logic; - -signal buf_to_apl_DAT_INIT_DATAREADY: std_logic; -signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT_INIT_READ : std_logic; - -signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic; -signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT_REPLY_READ : std_logic; - -signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic; -signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT_REPLY_READ : std_logic; - -signal apl_to_buf_TRG1_INIT_DATAREADY: std_logic; -signal apl_to_buf_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_INIT_READ : std_logic; - -signal buf_to_apl_TRG1_INIT_DATAREADY: std_logic; -signal buf_to_apl_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_INIT_READ : std_logic; - -signal apl_to_buf_TRG1_REPLY_DATAREADY: std_logic; -signal apl_to_buf_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_REPLY_READ : std_logic; - -signal buf_to_apl_TRG1_REPLY_DATAREADY: std_logic; -signal buf_to_apl_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_REPLY_READ : std_logic; - -signal apl_to_buf_TRG2_INIT_DATAREADY: std_logic; -signal apl_to_buf_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_INIT_READ : std_logic; - -signal buf_to_apl_TRG2_INIT_DATAREADY: std_logic; -signal buf_to_apl_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_INIT_READ : std_logic; - -signal apl_to_buf_TRG2_REPLY_DATAREADY: std_logic; -signal apl_to_buf_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_REPLY_READ : std_logic; - -signal buf_to_apl_TRG2_REPLY_DATAREADY: std_logic; -signal buf_to_apl_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_REPLY_READ : std_logic; - --- for the connection to the multiplexer -signal MED_DAT_INIT_DATAREADY_OUT : std_logic; -signal MED_DAT_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_INIT_READ_IN : std_logic; - -signal MED_DAT_INIT_DATAREADY_IN : std_logic; -signal MED_DAT_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_INIT_READ_OUT : std_logic; - -signal MED_DAT_REPLY_DATAREADY_OUT : std_logic; -signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_REPLY_READ_IN : std_logic; - -signal MED_DAT_REPLY_DATAREADY_IN : std_logic; -signal MED_DAT_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT_REPLY_READ_OUT : std_logic; - -signal MED_TRG1_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG1_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG1_INIT_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG1_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_READ_OUT : std_logic_vector(1 downto 0); - -signal MED_TRG1_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG1_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG1_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG1_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_READ_OUT : std_logic_vector(1 downto 0); - -signal MED_TRG2_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG2_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG2_INIT_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG2_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_READ_OUT : std_logic_vector(1 downto 0); - -signal MED_TRG2_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG2_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG2_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG2_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_READ_OUT : std_logic_vector(1 downto 0); - -signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -begin - - --Connections for data and trigger channel - genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate - gendat: if i = DAT_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT; - MED_DAT_INIT_READ_IN <= m_READ_IN(i*2); - MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_DAT_REPLY_READ_OUT; - end generate; - gentrg1: if i = TRG1_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_TRG1_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_TRG1_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG1_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG1_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG1_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG1_REPLY_PACKET_NUM_OUT; - MED_TRG1_INIT_READ_IN <= m_READ_IN(i*2); - MED_TRG1_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_TRG1_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_TRG1_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_TRG1_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_TRG1_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_TRG1_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_TRG1_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_TRG1_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_TRG1_REPLY_READ_OUT; - end generate; - gentrg1: if i = TRG2_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_TRG2_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_TRG2_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG2_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG2_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG2_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG2_REPLY_PACKET_NUM_OUT; - MED_TRG2_INIT_READ_IN <= m_READ_IN(i*2); - MED_TRG2_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_TRG2_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_TRG2_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_TRG2_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_TRG2_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_TRG2_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_TRG2_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_TRG2_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_TRG2_REPLY_READ_OUT; - end generate; - genelse: if i /= DAT_CHANNEL and i /= TRG1_CHANNEL and i /= TRG2_CHANNEL generate - termbuf: trb_net16_term_buf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_IN => m_READ_IN(i*2), - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) - ); - end generate; - end generate; - - gen_actapi: if API_TYPE = 1 generate - DAT_ACTIVE_API: trb_net16_api_base - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl - ); - end generate; - - gen_pasapi: if API_TYPE = 0 generate - DAT_PASSIVE_API: trb_net16_api_base - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => (others => '0'), - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl - ); - end generate; - -STAT_DAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); -STAT_DAT_api_control_signals(3) <= APL_WRITE_IN; -STAT_DAT_api_control_signals(4) <= APL_SEND_IN; -STAT_DAT_api_control_signals(7 downto 5) <= (others => '0'); -STAT_DAT_api_control_signals(10 downto 8) <= apl_to_buf_DAT_INIT_DATA(2 downto 0); -STAT_DAT_api_control_signals(11) <= apl_to_buf_DAT_INIT_DATAREADY; -STAT_DAT_api_control_signals(12) <= apl_to_buf_DAT_INIT_READ; -STAT_DAT_api_control_signals(31 downto 13) <= (others => '0'); - - - -DAT_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => DAT_INIT_DEPTH, - REPLY_DEPTH => DAT_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_DAT_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_DAT_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_DAT_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_DAT_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_DAT_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_DAT_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_DAT_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_DAT_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_DAT_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_DAT_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_DAT_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_DAT_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_DAT_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_DAT_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_DAT_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_DAT_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_DAT_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_DAT_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_DAT_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_DAT_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_DAT_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_DAT_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_DAT_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_DAT_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_DAT_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_DAT_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_DAT_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_DAT_GEN, - STAT_LOCKED => STAT_DAT_LOCKED, - STAT_INIT_BUFFER => STAT_DAT_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_DAT_REPLY_BUFFER, - CTRL_GEN => CTRL_DAT_GEN, - CTRL_LOCKED => CTRL_DAT_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_DAT_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_DAT_CTRL_REPLY_BUFFER - ); - - TRG1_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => TRG1_INIT_DEPTH, - REPLY_DEPTH => TRG1_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_TRG1_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_TRG1_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_TRG1_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_TRG1_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_TRG1_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_TRG1_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_TRG1_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_TRG1_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_TRG1_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_TRG1_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_TRG1_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_TRG1_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_TRG1_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_TRG1_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_TRG1_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_TRG1_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_TRG1_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_TRG1_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG1_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_TRG1_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_TRG1_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_TRG1_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG1_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_TRG1_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG1_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_TRG1_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG1_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_TRG1_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_TRG1_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_TRG1_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG1_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_TRG1_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_TRG1_GEN, - STAT_LOCKED => STAT_TRG1_LOCKED, - STAT_INIT_BUFFER => STAT_TRG1_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_TRG1_REPLY_BUFFER, - CTRL_GEN => CTRL_TRG1_GEN, - CTRL_LOCKED => CTRL_TRG1_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_TRG1_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_TRG1_CTRL_REPLY_BUFFER - ); - - TRG2_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => TRG2_INIT_DEPTH, - REPLY_DEPTH => TRG2_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_TRG2_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_TRG2_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_TRG2_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_TRG2_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_TRG2_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_TRG2_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_TRG2_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_TRG2_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_TRG2_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_TRG2_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_TRG2_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_TRG2_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_TRG2_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_TRG2_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_TRG2_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_TRG2_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_TRG2_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_TRG2_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG2_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_TRG2_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_TRG2_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_TRG2_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG2_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_TRG2_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG2_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_TRG2_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG2_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_TRG2_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_TRG2_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_TRG2_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG2_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_TRG2_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_TRG2_GEN, - STAT_LOCKED => STAT_TRG2_LOCKED, - STAT_INIT_BUFFER => STAT_TRG2_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_TRG2_REPLY_BUFFER, - CTRL_GEN => CTRL_TRG2_GEN, - CTRL_LOCKED => CTRL_TRG2_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_TRG2_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_TRG2_CTRL_REPLY_BUFFER - ); - - MPLEX: trb_net16_io_multiplexer - generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, - MUX_SECURE_MODE => MUX_SECURE_MODE - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, - INT_READ_IN =>m_READ_OUT, - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, - INT_READ_OUT =>m_READ_IN, - CTRL => MPLEX_CTRL - ); - - TRG1_INIT : trb_net16_term - generic map ( - FIFO_TERM_BUFFER_DEPTH => 0, - SECURE_MODE => TRG1_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => apl_to_buf_TRG1_REPLY_DATAREADY, - INT_DATA_OUT => apl_to_buf_TRG1_REPLY_DATA, - INT_PACKET_NUM_OUT => apl_to_buf_TRG1_REPLY_PACKET_NUM, - INT_READ_IN => apl_to_buf_TRG1_REPLY_READ, - INT_DATAREADY_IN => buf_to_apl_TRG1_INIT_DATAREADY, - INT_DATA_IN => buf_to_apl_TRG1_INIT_DATA, - INT_PACKET_NUM_IN => buf_to_apl_TRG1_INIT_PACKET_NUM, - INT_READ_OUT => buf_to_apl_TRG1_INIT_READ, - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => TRG1_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => TRG1_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => TRG1_SEQNR_OUT, - APL_GOT_TRM => TRG1_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => TRG1_RELEASE_IN, - APL_ERROR_PATTERN_IN => TRG1_ERROR_PATTERN_IN - -- Status and control port - ); - - TRG2_INIT : trb_net16_term - generic map ( - FIFO_TERM_BUFFER_DEPTH => 0, - SECURE_MODE => TRG2_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => apl_to_buf_TRG2_REPLY_DATAREADY, - INT_DATA_OUT => apl_to_buf_TRG2_REPLY_DATA, - INT_PACKET_NUM_OUT => apl_to_buf_TRG2_REPLY_PACKET_NUM, - INT_READ_IN => apl_to_buf_TRG2_REPLY_READ, - INT_DATAREADY_IN => buf_to_apl_TRG2_INIT_DATAREADY, - INT_DATA_IN => buf_to_apl_TRG2_INIT_DATA, - INT_PACKET_NUM_IN => buf_to_apl_TRG2_INIT_PACKET_NUM, - INT_READ_OUT => buf_to_apl_TRG2_INIT_READ, - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => TRG2_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => TRG2_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => TRG2_SEQNR_OUT, - APL_GOT_TRM => TRG2_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => TRG2_RELEASE_IN, - APL_ERROR_PATTERN_IN => TRG2_ERROR_PATTERN_IN - -- Status and control port - ); - -apl_to_buf_TRG1_INIT_DATAREADY <= '0'; -apl_to_buf_TRG1_INIT_DATA <= (others => '0'); -apl_to_buf_TRG1_INIT_PACKET_NUM <= (others => '0'); -buf_to_apl_TRG1_REPLY_READ <= '1'; - -apl_to_buf_TRG2_INIT_DATAREADY <= '0'; -apl_to_buf_TRG2_INIT_DATA <= (others => '0'); -apl_to_buf_TRG2_INIT_PACKET_NUM <= (others => '0'); -buf_to_apl_TRG2_REPLY_READ <= '1'; -end architecture; diff --git a/oldfiles/trb_net16_endpoint_2_trg_2_api.vhd b/oldfiles/trb_net16_endpoint_2_trg_2_api.vhd deleted file mode 100644 index a9b6466..0000000 --- a/oldfiles/trb_net16_endpoint_2_trg_2_api.vhd +++ /dev/null @@ -1,1245 +0,0 @@ - --- NOT UP TO DATE - - - - - - - - - - - - - - - - - - - - - - - - --- this is an trigger receiver combined with a passive api - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net16_endpoint_2_trg_2_api is - - generic ( - --api type for data channel - API1_TYPE : integer range 0 to 1 := 0; - API2_TYPE : integer range 0 to 1 := 0; - --Fifo for data channel - DAT1_INIT_DEPTH : integer range 0 to 7 := 2; - DAT1_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here - DAT1_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1; - DAT1_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1; - DAT2_INIT_DEPTH : integer range 0 to 7 := 2; - DAT2_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here - DAT2_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1; - DAT2_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1; - --SBUF_DATA_VERSION : integer range 0 to 1 := 0; - --Fifo for TRG channel - TRG1_INIT_DEPTH : integer range 0 to 7 := 0; - TRG1_REPLY_DEPTH : integer range 0 to 7 := 0; - TRG1_SECURE_MODE : integer range 0 to 1 := 0; - TRG2_INIT_DEPTH : integer range 0 to 7 := 0; - TRG2_REPLY_DEPTH : integer range 0 to 7 := 0; - TRG2_SECURE_MODE : integer range 0 to 1 := 0; - --SBUF_TRG_VERSION : integer range 0 to 1 := 0; - --Multiplexer - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0; - TRG1_CHANNEL : integer range 0 to 3 := 0; --range 0 to 2**(MUX_WIDTH-1) - TRG2_CHANNEL : integer range 0 to 3 := 1; --range 0 to 2**(MUX_WIDTH-1) - DAT1_CHANNEL : integer range 0 to 3 := 2; --range 0 to 2**(MUX_WIDTH-1) - DAT2_CHANNEL : integer range 0 to 3 := 3; --range 0 to 2**(MUX_WIDTH-1) - --General - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_READ_IN: in std_logic; -- Media is reading - MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - -- APL1 Transceiver port - APL1_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL1_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - APL1_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted - APL1_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full - APL1_SHORT_TRANSFER_IN: in std_logic; -- - APL1_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL1_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL1_SEND_IN: in std_logic; -- Release sending of the data - APL1_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL1_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - APL1_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL1_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL1_READ_IN: in std_logic; -- Read data word - APL1_RUN_OUT: out std_logic; -- Data transfer is running - APL1_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL1_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL1_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0); - - -- APL2 Transceiver port - APL2_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL2_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - APL2_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted - APL2_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full - APL2_SHORT_TRANSFER_IN: in std_logic; -- - APL2_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL2_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL2_SEND_IN: in std_logic; -- Release sending of the data - APL2_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL2_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - APL2_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL2_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out - APL2_READ_IN: in std_logic; -- Read data word - APL2_RUN_OUT: out std_logic; -- Data transfer is running - APL2_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL2_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL2_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0); - - -- TRG1 Receiver port - TRG1_GOT_TRIGGER_OUT : out std_logic; - TRG1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - TRG1_DTYPE_OUT : out std_logic_vector(3 downto 0); - TRG1_SEQNR_OUT : out std_logic_vector(7 downto 0); - TRG1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - TRG1_RELEASE_IN : in std_logic; - - -- TRG2 Receiver port - TRG2_GOT_TRIGGER_OUT : out std_logic; - TRG2_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - TRG2_DTYPE_OUT : out std_logic_vector(3 downto 0); - TRG2_SEQNR_OUT : out std_logic_vector(7 downto 0); - TRG2_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - TRG2_RELEASE_IN : in std_logic; - - -- Status and control port => for debugging - STAT_DAT2_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_DAT2_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_DAT2_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_DAT2_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_DAT2_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_DAT2_GEN: in std_logic_vector (31 downto 0); - CTRL_DAT2_LOCKED: in std_logic_vector (31 downto 0); - STAT_DAT2_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_DAT2_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG2_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG2_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG2_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_TRG2_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - STAT_TRG2_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_TRG2_GEN: in std_logic_vector (31 downto 0); - CTRL_TRG2_LOCKED: in std_logic_vector (31 downto 0); - STAT_TRG2_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_TRG2_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0); - STAT_MPLEX: out std_logic_vector(31 downto 0); - MPLEX_CTRL: in std_logic_vector (31 downto 0); - DAT1_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - DAT1_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - DAT2_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - DAT2_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end entity; - -architecture trb_net16_endpoint_2_trg_2_api_arch of trb_net16_endpoint_2_trg_2_api_endpoint is - - component trb_net16_iobuf is - - generic ( - INIT_DEPTH : integer := 1; - REPLY_DEPTH : integer := 1 - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_INIT_READ_IN: in std_logic; - - INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_INIT_READ_OUT: out std_logic; - - INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - INT_REPLY_READ_IN: in std_logic; - - INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_REPLY_READ_OUT: out std_logic; - - -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_api_base is - generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 1; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path - -- if set to 0, no buffer is used - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN : in std_logic; -- - APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN : in std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of - -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out - APL_READ_IN : in std_logic; -- Read data word - -- APL Control port - APL_RUN_OUT : out std_logic; -- Data transfer is running - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_MASTER_READ_IN : in std_logic; - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := 1; - SECURE_MODE : integer range 0 to 1 := 0 - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these must be available when hold_trm goes low - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - INT_READ_IN: in std_logic; - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - INT_READ_OUT: out std_logic; - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out std_logic_vector (7 downto 0); - APL_GOT_TRM: out std_logic; - APL_RELEASE_TRM: in std_logic; - APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr - -- Status and control port - ); - end component; - - component trb_net16_io_multiplexer is - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL: in std_logic_vector (31 downto 0); - STAT: out std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_term_buf is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; - MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; - MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; - MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic - ); - end component; -signal apl_to_buf_DAT1_INIT_DATAREADY: std_logic; -signal apl_to_buf_DAT1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT1_INIT_READ : std_logic; - -signal buf_to_apl_DAT1_INIT_DATAREADY: std_logic; -signal buf_to_apl_DAT1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT1_INIT_READ : std_logic; - -signal apl_to_buf_DAT1_REPLY_DATAREADY: std_logic; -signal apl_to_buf_DAT1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT1_REPLY_READ : std_logic; - -signal buf_to_apl_DAT1_REPLY_DATAREADY: std_logic; -signal buf_to_apl_DAT1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT1_REPLY_READ : std_logic; - -signal apl_to_buf_DAT2_INIT_DATAREADY: std_logic; -signal apl_to_buf_DAT2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT2_INIT_READ : std_logic; - -signal buf_to_apl_DAT2_INIT_DATAREADY: std_logic; -signal buf_to_apl_DAT2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT2_INIT_READ : std_logic; - -signal apl_to_buf_DAT2_REPLY_DATAREADY: std_logic; -signal apl_to_buf_DAT2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_DAT2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_DAT2_REPLY_READ : std_logic; - -signal buf_to_apl_DAT2_REPLY_DATAREADY: std_logic; -signal buf_to_apl_DAT2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_DAT2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_DAT2_REPLY_READ : std_logic; - -signal apl_to_buf_TRG1_INIT_DATAREADY: std_logic; -signal apl_to_buf_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_INIT_READ : std_logic; - -signal buf_to_apl_TRG1_INIT_DATAREADY: std_logic; -signal buf_to_apl_TRG1_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_INIT_READ : std_logic; - -signal apl_to_buf_TRG1_REPLY_DATAREADY: std_logic; -signal apl_to_buf_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG1_REPLY_READ : std_logic; - -signal buf_to_apl_TRG1_REPLY_DATAREADY: std_logic; -signal buf_to_apl_TRG1_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG1_REPLY_READ : std_logic; - -signal apl_to_buf_TRG2_INIT_DATAREADY: std_logic; -signal apl_to_buf_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_INIT_READ : std_logic; - -signal buf_to_apl_TRG2_INIT_DATAREADY: std_logic; -signal buf_to_apl_TRG2_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_INIT_READ : std_logic; - -signal apl_to_buf_TRG2_REPLY_DATAREADY: std_logic; -signal apl_to_buf_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal apl_to_buf_TRG2_REPLY_READ : std_logic; - -signal buf_to_apl_TRG2_REPLY_DATAREADY: std_logic; -signal buf_to_apl_TRG2_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0); -signal buf_to_apl_TRG2_REPLY_READ : std_logic; - --- for the connection to the multiplexer -signal MED_DAT1_INIT_DATAREADY_OUT : std_logic; -signal MED_DAT1_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT1_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT1_INIT_READ_IN : std_logic; - -signal MED_DAT1_INIT_DATAREADY_IN : std_logic; -signal MED_DAT1_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT1_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT1_INIT_READ_OUT : std_logic; - -signal MED_DAT1_REPLY_DATAREADY_OUT : std_logic; -signal MED_DAT1_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT1_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT1_REPLY_READ_IN : std_logic; - -signal MED_DAT1_REPLY_DATAREADY_IN : std_logic; -signal MED_DAT1_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT1_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT1_REPLY_READ_OUT : std_logic; - -signal MED_DAT2_INIT_DATAREADY_OUT : std_logic; -signal MED_DAT2_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT2_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT2_INIT_READ_IN : std_logic; - -signal MED_DAT2_INIT_DATAREADY_IN : std_logic; -signal MED_DAT2_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT2_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT2_INIT_READ_OUT : std_logic; - -signal MED_DAT2_REPLY_DATAREADY_OUT : std_logic; -signal MED_DAT2_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT2_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT2_REPLY_READ_IN : std_logic; - -signal MED_DAT2_REPLY_DATAREADY_IN : std_logic; -signal MED_DAT2_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); -signal MED_DAT2_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); -signal MED_DAT2_REPLY_READ_OUT : std_logic; - -signal MED_TRG1_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG1_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG1_INIT_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG1_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_INIT_READ_OUT : std_logic_vector(1 downto 0); - -signal MED_TRG1_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG1_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG1_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG1_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG1_REPLY_READ_OUT : std_logic_vector(1 downto 0); - -signal MED_TRG2_INIT_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG2_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG2_INIT_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG2_INIT_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_INIT_READ_OUT : std_logic_vector(1 downto 0); - -signal MED_TRG2_REPLY_DATAREADY_OUT : std_logic_vector(1 downto 0); -signal MED_TRG2_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_READ_IN : std_logic_vector(1 downto 0); - -signal MED_TRG2_REPLY_DATAREADY_IN : std_logic_vector(1 downto 0); -signal MED_TRG2_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2-1 downto 0); -signal MED_TRG2_REPLY_READ_OUT : std_logic_vector(1 downto 0); - -signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); - -begin - - --Connections for data and trigger channel - genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate - gendat1: if i = DAT1_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_DAT1_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_DAT1_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT1_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT1_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT1_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT1_REPLY_PACKET_NUM_OUT; - MED_DAT1_INIT_READ_IN <= m_READ_IN(i*2); - MED_DAT1_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_DAT1_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_DAT1_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_DAT1_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_DAT1_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_DAT1_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_DAT1_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_DAT1_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_DAT1_REPLY_READ_OUT; - end generate; - gendat2: if i = DAT2_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_DAT2_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_DAT2_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT2_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT2_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT2_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT2_REPLY_PACKET_NUM_OUT; - MED_DAT2_INIT_READ_IN <= m_READ_IN(i*2); - MED_DAT2_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_DAT2_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_DAT2_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_DAT2_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_DAT2_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_DAT2_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_DAT2_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_DAT2_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_DAT2_REPLY_READ_OUT; - end generate; - gentrg1: if i = TRG1_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_TRG1_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_TRG1_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG1_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG1_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG1_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG1_REPLY_PACKET_NUM_OUT; - MED_TRG1_INIT_READ_IN <= m_READ_IN(i*2); - MED_TRG1_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_TRG1_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_TRG1_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_TRG1_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_TRG1_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_TRG1_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_TRG1_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_TRG1_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_TRG1_REPLY_READ_OUT; - end generate; - gentrg1: if i = TRG2_CHANNEL generate - m_DATAREADY_OUT(i*2) <= MED_TRG2_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(i*2+1) <= MED_TRG2_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG2_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG2_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG2_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG2_REPLY_PACKET_NUM_OUT; - MED_TRG2_INIT_READ_IN <= m_READ_IN(i*2); - MED_TRG2_REPLY_READ_IN <= m_READ_IN(i*2+1); - MED_TRG2_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); - MED_TRG2_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_TRG2_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_TRG2_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_TRG2_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_TRG2_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); - m_READ_OUT(i*2) <= MED_TRG2_INIT_READ_OUT; - m_READ_OUT(i*2+1) <= MED_TRG2_REPLY_READ_OUT; - end generate; - genelse: if i /= DAT1_CHANNEL and i /= DAT2_CHANNEL and i /= TRG1_CHANNEL and i /= TRG2_CHANNEL generate - termbuf: trb_net16_term_buf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_IN => m_READ_IN(i*2), - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) - ); - end generate; - end generate; - - gen_actapi1: if API1_TYPE = 1 generate - DAT_ACTIVE_API1: trb_net16_api_base - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => DAT1_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT1_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL1_DATA_IN, - APL_PACKET_NUM_IN => APL1_PACKET_NUM_IN, - APL_WRITE_IN => APL1_WRITE_IN, - APL_FIFO_FULL_OUT => APL1_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL1_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL1_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL1_ERROR_PATTERN_IN, - APL_SEND_IN => APL1_SEND_IN, - APL_TARGET_ADDRESS_IN => APL1_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL1_DATA_OUT, - APL_PACKET_NUM_OUT=> APL1_PACKET_NUM_OUT, - APL_TYP_OUT => APL1_TYP_OUT, - APL_DATAREADY_OUT => APL1_DATAREADY_OUT, - APL_READ_IN => APL1_READ_IN, - -- APL Control port - APL_RUN_OUT => APL1_RUN_OUT, - APL_MY_ADDRESS_IN => APL1_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL1_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT1_INIT_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT1_INIT_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT1_INIT_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT1_INIT_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT1_INIT_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT1_INIT_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT1_INIT_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT1_INIT_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT1_REPLY_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT1_REPLY_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT1_REPLY_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT1_REPLY_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT1_REPLY_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT1_REPLY_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT1_REPLY_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT1_REPLY_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT1_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT1_api_stat_fifo_to_apl - ); - end generate; - - gen_pasapi1: if API1_TYPE = 0 generate - DAT_PASSIVE_API1: trb_net16_api_base - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => DAT1_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT1_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL1_DATA_IN, - APL_PACKET_NUM_IN => APL1_PACKET_NUM_IN, - APL_WRITE_IN => APL1_WRITE_IN, - APL_FIFO_FULL_OUT => APL1_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL1_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL1_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL1_ERROR_PATTERN_IN, - APL_SEND_IN => APL1_SEND_IN, - APL_TARGET_ADDRESS_IN => (others => '0'), - -- Receiver port - APL_DATA_OUT => APL1_DATA_OUT, - APL_PACKET_NUM_OUT=> APL1_PACKET_NUM_OUT, - APL_TYP_OUT => APL1_TYP_OUT, - APL_DATAREADY_OUT => APL1_DATAREADY_OUT, - APL_READ_IN => APL1_READ_IN, - -- APL Control port - APL_RUN_OUT => APL1_RUN_OUT, - APL_MY_ADDRESS_IN => APL1_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL1_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT1_REPLY_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT1_REPLY_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT1_REPLY_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT1_REPLY_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT1_REPLY_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT1_REPLY_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT1_REPLY_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT1_REPLY_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT1_INIT_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT1_INIT_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT1_INIT_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT1_INIT_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT1_INIT_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT1_INIT_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT1_INIT_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT1_INIT_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT1_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT1_api_stat_fifo_to_apl - ); - end generate; - -STAT_DAT1_api_control_signals(2 downto 0) <= APL1_DATA_IN(2 downto 0); -STAT_DAT1_api_control_signals(3) <= APL1_WRITE_IN; -STAT_DAT1_api_control_signals(4) <= APL1_SEND_IN; -STAT_DAT1_api_control_signals(7 downto 5) <= (others => '0'); -STAT_DAT1_api_control_signals(10 downto 8) <= apl_to_buf_DAT1_INIT_DATA(2 downto 0); -STAT_DAT1_api_control_signals(11) <= apl_to_buf_DAT1_INIT_DATAREADY; -STAT_DAT1_api_control_signals(12) <= apl_to_buf_DAT1_INIT_READ; -STAT_DAT1_api_control_signals(31 downto 13) <= (others => '0'); - - gen_actapi2: if API2_TYPE = 1 generate - DAT_ACTIVE_API1: trb_net16_api_base - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => DAT2_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT2_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL2_DATA_IN, - APL_PACKET_NUM_IN => APL2_PACKET_NUM_IN, - APL_WRITE_IN => APL2_WRITE_IN, - APL_FIFO_FULL_OUT => APL2_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL2_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL2_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL2_ERROR_PATTERN_IN, - APL_SEND_IN => APL2_SEND_IN, - APL_TARGET_ADDRESS_IN => APL2_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL2_DATA_OUT, - APL_PACKET_NUM_OUT=> APL2_PACKET_NUM_OUT, - APL_TYP_OUT => APL2_TYP_OUT, - APL_DATAREADY_OUT => APL2_DATAREADY_OUT, - APL_READ_IN => APL2_READ_IN, - -- APL Control port - APL_RUN_OUT => APL2_RUN_OUT, - APL_MY_ADDRESS_IN => APL2_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL2_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT2_INIT_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT2_INIT_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT2_INIT_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT2_INIT_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT2_INIT_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT2_INIT_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT2_INIT_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT2_INIT_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT2_REPLY_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT2_REPLY_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT2_REPLY_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT2_REPLY_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT2_REPLY_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT2_REPLY_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT2_REPLY_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT2_REPLY_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT2_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT2_api_stat_fifo_to_apl - ); - end generate; - - gen_pasapi2: if API2_TYPE = 0 generate - DAT_PASSIVE_API1: trb_net16_api_base - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => DAT2_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => DAT2_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL2_DATA_IN, - APL_PACKET_NUM_IN => APL2_PACKET_NUM_IN, - APL_WRITE_IN => APL2_WRITE_IN, - APL_FIFO_FULL_OUT => APL2_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL2_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL2_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL2_ERROR_PATTERN_IN, - APL_SEND_IN => APL2_SEND_IN, - APL_TARGET_ADDRESS_IN => (others => '0'), - -- Receiver port - APL_DATA_OUT => APL2_DATA_OUT, - APL_PACKET_NUM_OUT=> APL2_PACKET_NUM_OUT, - APL_TYP_OUT => APL2_TYP_OUT, - APL_DATAREADY_OUT => APL2_DATAREADY_OUT, - APL_READ_IN => APL2_READ_IN, - -- APL Control port - APL_RUN_OUT => APL2_RUN_OUT, - APL_MY_ADDRESS_IN => APL2_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL2_SEQNR_OUT, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT2_REPLY_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT2_REPLY_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT2_REPLY_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT2_REPLY_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT2_REPLY_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT2_REPLY_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT2_REPLY_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT2_REPLY_READ, - INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT2_INIT_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT2_INIT_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT2_INIT_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT2_INIT_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT2_INIT_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT2_INIT_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT2_INIT_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT2_INIT_READ, - -- Status and control port - STAT_FIFO_TO_INT => DAT2_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT2_api_stat_fifo_to_apl - ); - end generate; - -STAT_DAT2_api_control_signals(2 downto 0) <= APL2_DATA_IN(2 downto 0); -STAT_DAT2_api_control_signals(3) <= APL2_WRITE_IN; -STAT_DAT2_api_control_signals(4) <= APL2_SEND_IN; -STAT_DAT2_api_control_signals(7 downto 5) <= (others => '0'); -STAT_DAT2_api_control_signals(10 downto 8) <= apl_to_buf_DAT2_INIT_DATA(2 downto 0); -STAT_DAT2_api_control_signals(11) <= apl_to_buf_DAT2_INIT_DATAREADY; -STAT_DAT2_api_control_signals(12) <= apl_to_buf_DAT2_INIT_READ; -STAT_DAT2_api_control_signals(31 downto 13) <= (others => '0'); - -DAT1_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => DAT1_INIT_DEPTH, - REPLY_DEPTH => DAT1_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_DAT1_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_DAT1_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_DAT1_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_DAT1_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_DAT1_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_DAT1_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_DAT1_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_DAT1_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_DAT1_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_DAT1_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_DAT1_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_DAT1_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_DAT1_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_DAT1_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_DAT1_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_DAT1_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_DAT1_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_DAT1_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT1_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_DAT1_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_DAT1_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_DAT1_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT1_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_DAT1_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT1_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_DAT1_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT1_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_DAT1_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_DAT1_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_DAT1_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT1_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_DAT1_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_DAT1_GEN, - STAT_LOCKED => STAT_DAT1_LOCKED, - STAT_INIT_BUFFER => STAT_DAT1_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_DAT1_REPLY_BUFFER, - CTRL_GEN => CTRL_DAT1_GEN, - CTRL_LOCKED => CTRL_DAT1_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_DAT1_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_DAT1_CTRL_REPLY_BUFFER - ); - -DAT2_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => DAT2_INIT_DEPTH, - REPLY_DEPTH => DAT2_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_DAT2_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_DAT2_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_DAT2_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_DAT2_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_DAT2_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_DAT2_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_DAT2_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_DAT2_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_DAT2_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_DAT2_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_DAT2_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_DAT2_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_DAT2_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_DAT2_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_DAT2_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_DAT2_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_DAT2_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_DAT2_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT2_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_DAT2_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_DAT2_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_DAT2_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT2_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_DAT2_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT2_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_DAT2_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT2_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_DAT2_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_DAT2_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_DAT2_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT2_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_DAT2_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_DAT2_GEN, - STAT_LOCKED => STAT_DAT2_LOCKED, - STAT_INIT_BUFFER => STAT_DAT2_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_DAT2_REPLY_BUFFER, - CTRL_GEN => CTRL_DAT2_GEN, - CTRL_LOCKED => CTRL_DAT2_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_DAT2_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_DAT2_CTRL_REPLY_BUFFER - ); - - TRG1_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => TRG1_INIT_DEPTH, - REPLY_DEPTH => TRG1_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_TRG1_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_TRG1_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_TRG1_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_TRG1_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_TRG1_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_TRG1_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_TRG1_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_TRG1_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_TRG1_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_TRG1_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_TRG1_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_TRG1_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_TRG1_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_TRG1_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_TRG1_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_TRG1_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_TRG1_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_TRG1_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG1_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_TRG1_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_TRG1_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_TRG1_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG1_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_TRG1_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG1_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_TRG1_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG1_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_TRG1_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_TRG1_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_TRG1_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG1_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_TRG1_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_TRG1_GEN, - STAT_LOCKED => STAT_TRG1_LOCKED, - STAT_INIT_BUFFER => STAT_TRG1_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_TRG1_REPLY_BUFFER, - CTRL_GEN => CTRL_TRG1_GEN, - CTRL_LOCKED => CTRL_TRG1_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_TRG1_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_TRG1_CTRL_REPLY_BUFFER - ); - - TRG2_IOBUF: trb_net16_iobuf - generic map( - INIT_DEPTH => TRG2_INIT_DEPTH, - REPLY_DEPTH => TRG2_REPLY_DEPTH - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_TRG2_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_TRG2_INIT_DATA_OUT, - MED_INIT_PACKET_NUM_OUT => MED_TRG2_INIT_PACKET_NUM_OUT, - MED_INIT_READ_IN => MED_TRG2_INIT_READ_IN, - MED_INIT_DATAREADY_IN => MED_TRG2_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_TRG2_INIT_DATA_IN, - MED_INIT_PACKET_NUM_IN => MED_TRG2_INIT_PACKET_NUM_IN, - MED_INIT_READ_OUT => MED_TRG2_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - MED_REPLY_DATAREADY_OUT => MED_TRG2_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_TRG2_REPLY_DATA_OUT, - MED_REPLY_PACKET_NUM_OUT=> MED_TRG2_REPLY_PACKET_NUM_OUT, - MED_REPLY_READ_IN => MED_TRG2_REPLY_READ_IN, - MED_REPLY_DATAREADY_IN => MED_TRG2_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_TRG2_REPLY_DATA_IN, - MED_REPLY_PACKET_NUM_IN => MED_TRG2_REPLY_PACKET_NUM_IN, - MED_REPLY_READ_OUT => MED_TRG2_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_apl_TRG2_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_TRG2_INIT_DATA, - INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG2_INIT_PACKET_NUM, - INT_INIT_READ_IN => buf_to_apl_TRG2_INIT_READ, - INT_INIT_DATAREADY_IN => apl_to_buf_TRG2_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_TRG2_INIT_DATA, - INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG2_INIT_PACKET_NUM, - INT_INIT_READ_OUT => apl_to_buf_TRG2_INIT_READ, - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG2_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_TRG2_REPLY_DATA, - INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG2_REPLY_PACKET_NUM, - INT_REPLY_READ_IN => buf_to_apl_TRG2_REPLY_READ, - INT_REPLY_DATAREADY_IN => apl_to_buf_TRG2_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_TRG2_REPLY_DATA, - INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG2_REPLY_PACKET_NUM, - INT_REPLY_READ_OUT => apl_to_buf_TRG2_REPLY_READ, - -- Status and control port - STAT_GEN => STAT_TRG2_GEN, - STAT_LOCKED => STAT_TRG2_LOCKED, - STAT_INIT_BUFFER => STAT_TRG2_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_TRG2_REPLY_BUFFER, - CTRL_GEN => CTRL_TRG2_GEN, - CTRL_LOCKED => CTRL_TRG2_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_TRG2_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_TRG2_CTRL_REPLY_BUFFER - ); - - MPLEX: trb_net16_io_multiplexer - generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, - MUX_SECURE_MODE => MUX_SECURE_MODE - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN, - INT_READ_IN =>m_READ_OUT, - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT, - INT_READ_OUT =>m_READ_IN, - CTRL => MPLEX_CTRL - ); - - TRG1_INIT : trb_net16_term - generic map ( - FIFO_TERM_BUFFER_DEPTH => 0, - SECURE_MODE => TRG1_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => apl_to_buf_TRG1_REPLY_DATAREADY, - INT_DATA_OUT => apl_to_buf_TRG1_REPLY_DATA, - INT_PACKET_NUM_OUT => apl_to_buf_TRG1_REPLY_PACKET_NUM, - INT_READ_IN => apl_to_buf_TRG1_REPLY_READ, - INT_DATAREADY_IN => buf_to_apl_TRG1_INIT_DATAREADY, - INT_DATA_IN => buf_to_apl_TRG1_INIT_DATA, - INT_PACKET_NUM_IN => buf_to_apl_TRG1_INIT_PACKET_NUM, - INT_READ_OUT => buf_to_apl_TRG1_INIT_READ, - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => TRG1_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => TRG1_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => TRG1_SEQNR_OUT, - APL_GOT_TRM => TRG1_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => TRG1_RELEASE_IN, - APL_ERROR_PATTERN_IN => TRG1_ERROR_PATTERN_IN - -- Status and control port - ); - - TRG2_INIT : trb_net16_term - generic map ( - FIFO_TERM_BUFFER_DEPTH => 0, - SECURE_MODE => TRG2_SECURE_MODE - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => apl_to_buf_TRG2_REPLY_DATAREADY, - INT_DATA_OUT => apl_to_buf_TRG2_REPLY_DATA, - INT_PACKET_NUM_OUT => apl_to_buf_TRG2_REPLY_PACKET_NUM, - INT_READ_IN => apl_to_buf_TRG2_REPLY_READ, - INT_DATAREADY_IN => buf_to_apl_TRG2_INIT_DATAREADY, - INT_DATA_IN => buf_to_apl_TRG2_INIT_DATA, - INT_PACKET_NUM_IN => buf_to_apl_TRG2_INIT_PACKET_NUM, - INT_READ_OUT => buf_to_apl_TRG2_INIT_READ, - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => TRG2_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => TRG2_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => TRG2_SEQNR_OUT, - APL_GOT_TRM => TRG2_GOT_TRIGGER_OUT, - APL_RELEASE_TRM => TRG2_RELEASE_IN, - APL_ERROR_PATTERN_IN => TRG2_ERROR_PATTERN_IN - -- Status and control port - ); - -apl_to_buf_TRG1_INIT_DATAREADY <= '0'; -apl_to_buf_TRG1_INIT_DATA <= (others => '0'); -apl_to_buf_TRG1_INIT_PACKET_NUM <= (others => '0'); -buf_to_apl_TRG1_REPLY_READ <= '1'; - -apl_to_buf_TRG2_INIT_DATAREADY <= '0'; -apl_to_buf_TRG2_INIT_DATA <= (others => '0'); -apl_to_buf_TRG2_INIT_PACKET_NUM <= (others => '0'); -buf_to_apl_TRG2_REPLY_READ <= '1'; -end architecture; diff --git a/oldfiles/trb_net16_hub_streaming_port.vhd b/oldfiles/trb_net16_hub_streaming_port.vhd deleted file mode 100644 index e76593b..0000000 --- a/oldfiles/trb_net16_hub_streaming_port.vhd +++ /dev/null @@ -1,626 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - ---the first media interface is always the uplink & stream output! - -entity trb_net16_hub_streaming_port is - generic( - --hub control - HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL; - HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; - HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES); - USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES); - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - IBUF_SECURE_MODE : integer range 0 to 1 := c_YES; - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; - CLOCK_FREQUENCY : integer range 1 to 200 := 100; - USE_ONEWIRE : integer range 0 to 2 := c_YES; - BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; - --media interfaces - MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; - MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; - MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); - MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); - MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO) - ); - - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - --Media Interface - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0); - MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0); - - --Event information coming from CTS - CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); - CTS_CODE_OUT : out std_logic_vector (7 downto 0); - CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - CTS_START_READOUT_OUT : out std_logic; - - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_IN : in std_logic_vector (31 downto 0); - CTS_DATAREADY_IN : in std_logic; - CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM - CTS_READ_OUT : out std_logic; - CTS_LENGTH_IN : in std_logic_vector (15 downto 0); - CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - - -- Data from Frontends - FEE_DATA_OUT : out std_logic_vector (15 downto 0); - FEE_DATAREADY_OUT : out std_logic; - FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready - FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - FEE_BUSY_OUT : out std_logic; - - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - - COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs - COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs - ONEWIRE : inout std_logic; - ONEWIRE_MONITOR_IN : in std_logic; - ONEWIRE_MONITOR_OUT : out std_logic; - MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); - - --REGIO INTERFACE - REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); - REGIO_READ_ENABLE_OUT : out std_logic; - REGIO_WRITE_ENABLE_OUT : out std_logic; - REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); - REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); - REGIO_DATAREADY_IN : in std_logic := '0'; - REGIO_NO_MORE_DATA_IN : in std_logic := '0'; - REGIO_WRITE_ACK_IN : in std_logic := '0'; - REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; - REGIO_TIMEOUT_OUT : out std_logic; - - - --status and control ports - HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); - HUB_STAT_GEN : out std_logic_vector (31 downto 0); - MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); - MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); - STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs - STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs - --Debugging registers - STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging - CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging - ); -end entity; - - -architecture trb_net16_hub_streaming_arch of trb_net16_hub_streaming_port is - -constant mii : integer := MII_NUMBER-1; - -signal hub_init_dataready_out : std_logic_vector(3 downto 0); -signal hub_reply_dataready_out : std_logic_vector(3 downto 0); -signal hub_init_dataready_in : std_logic_vector(3 downto 0); -signal hub_reply_dataready_in : std_logic_vector(3 downto 0); - -signal hub_init_read_out : std_logic_vector(3 downto 0); -signal hub_reply_read_out : std_logic_vector(3 downto 0); -signal hub_init_read_in : std_logic_vector(3 downto 0); -signal hub_reply_read_in : std_logic_vector(3 downto 0); - -signal hub_init_data_out : std_logic_vector(48 downto 0); -signal hub_reply_data_out : std_logic_vector(48 downto 0); -signal hub_init_data_in : std_logic_vector(48 downto 0); -signal hub_reply_data_in : std_logic_vector(48 downto 0); - -signal hub_init_packet_num_out : std_logic_vector(9 downto 0); -signal hub_reply_packet_num_out : std_logic_vector(9 downto 0); -signal hub_init_packet_num_in : std_logic_vector(9 downto 0); -signal hub_reply_packet_num_in : std_logic_vector(9 downto 0); - -signal cts_init_data_out : std_logic_vector(15 downto 0); -signal cts_init_dataready_out : std_logic; -signal cts_init_packet_num_out : std_logic_vector(2 downto 0); -signal cts_init_read_in : std_logic; - -signal cts_reply_data_in : std_logic_vector(15 downto 0); -signal cts_reply_dataready_in : std_logic; -signal cts_reply_packet_num_in : std_logic_vector(2 downto 0); -signal cts_reply_read_out : std_logic; - -signal common_ctrl : std_logic_vector(std_COMCTRLREG*32-1 downto 0); -signal common_stat : std_logic_vector(std_COMSTATREG*32-1 downto 0); -signal my_address : std_logic_vector(15 downto 0); - -signal io_dataready_out : std_logic_vector(7 downto 0); -signal io_data_out : std_logic_vector(127 downto 0); -signal io_packet_num_out : std_logic_vector(23 downto 0); -signal io_read_in : std_logic_vector(7 downto 0); - -signal io_dataready_in : std_logic_vector(3 downto 0); -signal io_read_out : std_logic_vector(3 downto 0); -signal io_data_in : std_logic_vector(4*16-1 downto 0); -signal io_packet_num_in : std_logic_vector(4*3-1 downto 0); -signal io_error_in : std_logic_vector(2 downto 0); - -signal reset_i : std_logic; - -signal HUB_MED_CTRL_OP : std_logic_vector(mii*16-1 downto 0); -signal reset_i_mux_io : std_logic; - -signal hub_make_network_reset : std_logic; -signal hub_got_network_reset : std_logic; -signal timer_ticks : std_logic_vector(1 downto 0); -signal hub_ctrl_debug : std_logic_vector(31 downto 0); - -begin - ---------------------------------------------------------------------- --- Reset ---------------------------------------------------------------------- ---13: reset sequence received ---14: not connected ---15: send reset sequence - - SYNC_RESET_MUX_IO : process(CLK) - begin - if rising_edge(CLK) then - reset_i <= RESET; - reset_i_mux_io <= MED_STAT_OP(mii*16+14) or reset_i; - end if; - end process; - - ---generate media resync - gen_resync : for i in 0 to mii-1 generate - MED_CTRL_OP(13+i*16 downto i*16) <= (others => '0'); - MED_CTRL_OP(14+i*16) <= HUB_MED_CTRL_OP(14+i*16); - MED_CTRL_OP(15+i*16) <= hub_make_network_reset ; - end generate; - MED_CTRL_OP(13+mii*16 downto mii*16) <= (others => '0'); - MED_CTRL_OP(14+mii*16) <= '0'; - MED_CTRL_OP(15+mii*16) <= hub_make_network_reset; - - - hub_make_network_reset <= MED_STAT_OP(15) or MED_STAT_OP(15+mii*16); - ---------------------------------------------------------------------- --- Connecting I/O ---------------------------------------------------------------------- - - COMMON_CTRL_REGS <= common_ctrl; - COMMON_STAT_REGS <= common_stat; - MY_ADDRESS_OUT <= my_address; - - ---------------------------------------------------------------------- --- The Hub ---------------------------------------------------------------------- - - - THE_HUB : trb_net16_hub_base - generic map ( - --hub control - HUB_CTRL_CHANNELNUM => HUB_CTRL_CHANNELNUM, - HUB_CTRL_DEPTH => HUB_CTRL_DEPTH, - HUB_USED_CHANNELS => HUB_USED_CHANNELS, - USE_CHECKSUM => USE_CHECKSUM, - USE_VENDOR_CORES => USE_VENDOR_CORES, - IBUF_SECURE_MODE => IBUF_SECURE_MODE, - INIT_ADDRESS => INIT_ADDRESS, - INIT_UNIQUE_ID => INIT_UNIQUE_ID, - COMPILE_TIME => COMPILE_TIME, - INCLUDED_FEATURES => INCLUDED_FEATURES, - HARDWARE_VERSION => HARDWARE_VERSION, - HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, - USE_ONEWIRE => USE_ONEWIRE, - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - MII_NUMBER => mii, - MII_IBUF_DEPTH => MII_IBUF_DEPTH, - MII_IS_UPLINK => MII_IS_UPLINK, - MII_IS_DOWNLINK => MII_IS_DOWNLINK, - MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, - INIT_ENDPOINT_ID => INIT_ENDPOINT_ID, - INT_NUMBER => 3, - INT_CHANNELS => (0=>0,1=>1,2=>3,others=>0) - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - --Media interfacces - MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), - MED_DATA_OUT => med_data_out(mii*16-1 downto 0), - MED_PACKET_NUM_OUT=> med_packet_num_out(mii*3-1 downto 0), - MED_READ_IN => med_read_in(mii-1 downto 0), - MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), - MED_DATA_IN => med_data_in(mii*16-1 downto 0), - MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), - MED_READ_OUT => med_read_out(mii-1 downto 0), - MED_STAT_OP => med_stat_op(mii*16-1 downto 0), - MED_CTRL_OP => HUB_MED_CTRL_OP(mii*16-1 downto 0), - - INT_INIT_DATAREADY_OUT => hub_init_dataready_out, - INT_INIT_DATA_OUT => hub_init_data_out, - INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_out, - INT_INIT_READ_IN => hub_init_read_in, - INT_INIT_DATAREADY_IN => hub_init_dataready_in, - INT_INIT_DATA_IN => hub_init_data_in, - INT_INIT_PACKET_NUM_IN => hub_init_packet_num_in, - INT_INIT_READ_OUT => hub_init_read_out, - INT_REPLY_DATAREADY_OUT => hub_reply_dataready_out, - INT_REPLY_DATA_OUT => hub_reply_data_out, - INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_out, - INT_REPLY_READ_IN => hub_reply_read_in, - INT_REPLY_DATAREADY_IN => hub_reply_dataready_in, - INT_REPLY_DATA_IN => hub_reply_data_in, - INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_in, - INT_REPLY_READ_OUT => hub_reply_read_out, - --REGIO INTERFACE - REGIO_ADDR_OUT => REGIO_ADDR_OUT, - REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, - REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, - REGIO_DATA_OUT => REGIO_DATA_OUT, - REGIO_DATA_IN => REGIO_DATA_IN, - REGIO_DATAREADY_IN => REGIO_DATAREADY_IN, - REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, - REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, - REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, - REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, - TIMER_TICKS_OUT => timer_ticks, - ONEWIRE => ONEWIRE, - ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, - ONEWIRE_MONITOR_OUT=> ONEWIRE_MONITOR_OUT, - MY_ADDRESS_OUT => my_address, - COMMON_CTRL_REGS => common_ctrl, - COMMON_STAT_REGS => common_stat, - MPLEX_CTRL => (others => '0'), - CTRL_DEBUG => hub_ctrl_debug, - STAT_DEBUG => STAT_DEBUG - ); - - hub_ctrl_debug(2 downto 0) <= not io_error_in; - hub_ctrl_debug(31 downto 3) <= (others => '0'); - TIMER_TICKS_OUT <= timer_ticks; ---------------------------------------------------------------------- --- I/O Buffers ---------------------------------------------------------------------- - - THE_IOBUF_0 : trb_net16_iobuf - generic map( - IBUF_DEPTH => 6, - USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(0), - USE_CHECKSUM => cfg_USE_CHECKSUM(0), - INIT_CAN_SEND_DATA => c_YES, - INIT_CAN_RECEIVE_DATA => c_YES, - REPLY_CAN_SEND_DATA => c_YES, - REPLY_CAN_RECEIVE_DATA => c_YES - ) - port map( - -- Misc - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(0), - MED_INIT_DATA_OUT => io_data_out(15 downto 0), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(2 downto 0), - MED_INIT_READ_IN => io_read_in(0), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(1), - MED_REPLY_DATA_OUT => io_data_out(31 downto 16), - MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(5 downto 3), - MED_REPLY_READ_IN => io_read_in(1), - - MED_DATAREADY_IN => io_dataready_in(0), - MED_DATA_IN => io_data_in(15 downto 0), - MED_PACKET_NUM_IN => io_packet_num_in(2 downto 0), - MED_READ_OUT => io_read_out(0), - MED_ERROR_IN => io_error_in, - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => hub_init_dataready_in(0), - INT_INIT_DATA_OUT => hub_init_data_in(15 downto 0), - INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(2 downto 0), - INT_INIT_READ_IN => hub_init_read_out(0), - - INT_INIT_DATAREADY_IN => hub_init_dataready_out(0), - INT_INIT_DATA_IN => hub_init_data_out(15 downto 0), - INT_INIT_PACKET_NUM_IN => hub_init_packet_num_out(2 downto 0), - INT_INIT_READ_OUT => hub_init_read_in(0), - - INT_REPLY_DATAREADY_OUT => hub_reply_dataready_in(0), - INT_REPLY_DATA_OUT => hub_reply_data_in(15 downto 0), - INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_in(2 downto 0), - INT_REPLY_READ_IN => hub_reply_read_out(0), - - INT_REPLY_DATAREADY_IN => hub_reply_dataready_out(0), - INT_REPLY_DATA_IN => hub_reply_data_out(15 downto 0), - INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(2 downto 0), - INT_REPLY_READ_OUT => hub_reply_read_in(0), - - -- Status and control port - STAT_GEN => open, - STAT_IBUF_BUFFER => open, - CTRL_GEN => (others => '0'), - STAT_INIT_OBUF_DEBUG => open, - STAT_REPLY_OBUF_DEBUG => open, - TIMER_TICKS_IN => timer_ticks - ); - - - THE_IOBUF_1 : trb_net16_iobuf - generic map( - IBUF_DEPTH => 6, - USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1), - USE_CHECKSUM => cfg_USE_CHECKSUM(1), - INIT_CAN_SEND_DATA => c_YES, - INIT_CAN_RECEIVE_DATA => c_YES, - REPLY_CAN_SEND_DATA => c_YES, - REPLY_CAN_RECEIVE_DATA => c_YES - ) - port map( - -- Misc - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(2), - MED_INIT_DATA_OUT => io_data_out(47 downto 32), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6), - MED_INIT_READ_IN => io_read_in(2), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(3), - MED_REPLY_DATA_OUT => io_data_out(63 downto 48), - MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9), - MED_REPLY_READ_IN => io_read_in(3), - - MED_DATAREADY_IN => io_dataready_in(1), - MED_DATA_IN => io_data_in(31 downto 16), - MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3), - MED_READ_OUT => io_read_out(1), - MED_ERROR_IN => io_error_in, - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => cts_init_dataready_out, - INT_INIT_DATA_OUT => cts_init_data_out, - INT_INIT_PACKET_NUM_OUT => cts_init_packet_num_out, - INT_INIT_READ_IN => cts_init_read_in, - - INT_INIT_DATAREADY_IN => '0', - INT_INIT_DATA_IN => (others => '0'), - INT_INIT_PACKET_NUM_IN => (others => '0'), - INT_INIT_READ_OUT => open, - - INT_REPLY_DATAREADY_OUT => open, - INT_REPLY_DATA_OUT => open, - INT_REPLY_PACKET_NUM_OUT => open, - INT_REPLY_READ_IN => '1', - - INT_REPLY_DATAREADY_IN => cts_reply_dataready_in, - INT_REPLY_DATA_IN => cts_reply_data_in, - INT_REPLY_PACKET_NUM_IN => cts_reply_packet_num_in, - INT_REPLY_READ_OUT => cts_reply_read_out, - - -- Status and control port - STAT_GEN => open, - STAT_IBUF_BUFFER => open, - CTRL_GEN => (others => '0'), - STAT_INIT_OBUF_DEBUG => open, - STAT_REPLY_OBUF_DEBUG => open, - TIMER_TICKS_IN => timer_ticks - ); - - THE_IOBUF_2 : trb_net16_term_buf - port map ( - -- Misc - CLK => CLK , - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(4), - MED_INIT_DATA_OUT => io_data_out(79 downto 64), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(14 downto 12), - MED_INIT_READ_IN => io_read_in(4), - MED_REPLY_DATAREADY_OUT => io_dataready_out(5), - MED_REPLY_DATA_OUT => io_data_out(95 downto 80), - MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(17 downto 15), - MED_REPLY_READ_IN => io_read_in(5), - MED_DATAREADY_IN => io_dataready_in(2), - MED_DATA_IN => io_data_in(47 downto 32), - MED_PACKET_NUM_IN => io_packet_num_in(8 downto 6), - MED_READ_OUT => io_read_out(2) - ); - - THE_IOBUF_3 : trb_net16_iobuf - generic map( - IBUF_DEPTH => 6, - USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(3), - USE_CHECKSUM => cfg_USE_CHECKSUM(3), - INIT_CAN_SEND_DATA => c_YES, - INIT_CAN_RECEIVE_DATA => c_YES, - REPLY_CAN_SEND_DATA => c_YES, - REPLY_CAN_RECEIVE_DATA => c_YES - ) - port map( - -- Misc - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(6), - MED_INIT_DATA_OUT => io_data_out(111 downto 96), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(20 downto 18), - MED_INIT_READ_IN => io_read_in(6), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(7), - MED_REPLY_DATA_OUT => io_data_out(127 downto 112), - MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(23 downto 21), - MED_REPLY_READ_IN => io_read_in(7), - - MED_DATAREADY_IN => io_dataready_in(3), - MED_DATA_IN => io_data_in(63 downto 48), - MED_PACKET_NUM_IN => io_packet_num_in(11 downto 9), - MED_READ_OUT => io_read_out(3), - MED_ERROR_IN => io_error_in, - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => hub_init_dataready_in(2), - INT_INIT_DATA_OUT => hub_init_data_in(47 downto 32), - INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(8 downto 6), - INT_INIT_READ_IN => hub_init_read_out(2), - - INT_INIT_DATAREADY_IN => hub_init_dataready_out(2), - INT_INIT_DATA_IN => hub_init_data_out(47 downto 32), - INT_INIT_PACKET_NUM_IN => hub_init_packet_num_out(8 downto 6), - INT_INIT_READ_OUT => hub_init_read_in(2), - - INT_REPLY_DATAREADY_OUT => hub_reply_dataready_in(2), - INT_REPLY_DATA_OUT => hub_reply_data_in(47 downto 32), - INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_in(8 downto 6), - INT_REPLY_READ_IN => hub_reply_read_out(2), - - INT_REPLY_DATAREADY_IN => hub_reply_dataready_out(2), - INT_REPLY_DATA_IN => hub_reply_data_out(47 downto 32), - INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(8 downto 6), - INT_REPLY_READ_OUT => hub_reply_read_in(2), - - -- Status and control port - STAT_GEN => open, - STAT_IBUF_BUFFER => open, - CTRL_GEN => (others => '0'), - STAT_INIT_OBUF_DEBUG => open, - STAT_REPLY_OBUF_DEBUG => open, - TIMER_TICKS_IN => timer_ticks - ); - ---------------------------------------------------------------------- --- Multiplexer ---------------------------------------------------------------------- - MPLEX: trb_net16_io_multiplexer - port map ( - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_DATAREADY_IN(mii), - MED_DATA_IN => MED_DATA_IN(mii*16+15 downto mii*16), - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(mii*3+2 downto mii*3), - MED_READ_OUT => MED_READ_OUT(mii), - MED_DATAREADY_OUT => MED_DATAREADY_OUT(mii), - MED_DATA_OUT => MED_DATA_OUT(mii*16+15 downto mii*16), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(mii*3+2 downto mii*3), - MED_READ_IN => MED_READ_IN(mii), - INT_DATAREADY_OUT => io_dataready_in, - INT_DATA_OUT => io_data_in, - INT_PACKET_NUM_OUT => io_packet_num_in, - INT_READ_IN => io_read_out, - INT_DATAREADY_IN => io_dataready_out, - INT_DATA_IN => io_data_out, - INT_PACKET_NUM_IN => io_packet_num_out, - INT_READ_OUT => io_read_in, - CTRL => (others => '0'), - STAT => open - ); - io_error_in <= MED_STAT_OP(mii*16+2 downto mii*16+0); - ---------------------------------------------------------------------- --- IPU Channel ---------------------------------------------------------------------- - - hub_reply_data_in(31 downto 16) <= (others => '0'); - hub_reply_packet_num_in(5 downto 3) <= (others => '0'); - hub_reply_dataready_in(1) <= '0'; - hub_init_read_in(1) <= '1'; - - THE_STREAMING : trb_net16_api_ipu_streaming - port map( - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - - -- Internal direction port - - FEE_INIT_DATA_OUT => hub_init_data_in(31 downto 16), - FEE_INIT_DATAREADY_OUT => hub_init_dataready_in(1), - FEE_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(5 downto 3), - FEE_INIT_READ_IN => hub_init_read_out(1), - - FEE_REPLY_DATA_IN => hub_reply_data_out(31 downto 16), - FEE_REPLY_DATAREADY_IN => hub_reply_dataready_out(1), - FEE_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(5 downto 3), - FEE_REPLY_READ_OUT => hub_reply_read_in(1), - - CTS_INIT_DATA_IN => cts_init_data_out, - CTS_INIT_DATAREADY_IN => cts_init_dataready_out, - CTS_INIT_PACKET_NUM_IN => cts_init_packet_num_out, - CTS_INIT_READ_OUT => cts_init_read_in, - - CTS_REPLY_DATA_OUT => cts_reply_data_in, - CTS_REPLY_DATAREADY_OUT => cts_reply_dataready_in, - CTS_REPLY_PACKET_NUM_OUT => cts_reply_packet_num_in, - CTS_REPLY_READ_IN => cts_reply_read_out, - - --Event information coming from CTS - CTS_NUMBER_OUT => CTS_NUMBER_OUT, - CTS_CODE_OUT => CTS_CODE_OUT, - CTS_INFORMATION_OUT => CTS_INFORMATION_OUT, - CTS_READOUT_TYPE_OUT => CTS_READOUT_TYPE_OUT, - CTS_START_READOUT_OUT => CTS_START_READOUT_OUT, - - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_IN => CTS_DATA_IN, - CTS_DATAREADY_IN => CTS_DATAREADY_IN, - CTS_READOUT_FINISHED_IN => CTS_READOUT_FINISHED_IN, - CTS_READ_OUT => CTS_READ_OUT, - CTS_LENGTH_IN => CTS_LENGTH_IN, - CTS_STATUS_BITS_IN => CTS_STATUS_BITS_IN, - - -- Data from Frontends - FEE_DATA_OUT => FEE_DATA_OUT, - FEE_DATAREADY_OUT => FEE_DATAREADY_OUT, - FEE_READ_IN => FEE_READ_IN, - FEE_STATUS_BITS_OUT => FEE_STATUS_BITS_OUT, - FEE_BUSY_OUT => FEE_BUSY_OUT, - - MY_ADDRESS_IN => MY_ADDRESS_IN, - CTRL_SEQNR_RESET => common_ctrl(10) - - ); - --- STAT_DEBUG(0) <= cts_reply_dataready_in; --- STAT_DEBUG(1) <= cts_reply_read_out; --- STAT_DEBUG(2) <= cts_init_dataready_out; --- STAT_DEBUG(3) <= cts_reply_read_out; --- STAT_DEBUG(4) <= io_dataready_out(2); --- STAT_DEBUG(5) <= io_dataready_out(3); --- STAT_DEBUG(6) <= '0'; --- STAT_DEBUG(7) <= '0'; - - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_med_16_CC.vhd b/oldfiles/trb_net16_med_16_CC.vhd deleted file mode 100644 index 1023f55..0000000 --- a/oldfiles/trb_net16_med_16_CC.vhd +++ /dev/null @@ -1,384 +0,0 @@ --- A 16bit data interface between two devices using a common clock, 32 data lines and 4 control lines - - -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net16_med_16_CC is - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_VALID_OUT : out std_logic; - DATA_CTRL_OUT : out std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_VALID_IN : in std_logic; - DATA_CTRL_IN : in std_logic; - - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(63 downto 0) - ); - attribute syn_useioff : boolean; - attribute syn_useioff of DATA_OUT : signal is true; - attribute syn_useioff of DATA_VALID_OUT : signal is true; - attribute syn_useioff of DATA_CTRL_OUT : signal is true; - attribute syn_useioff of DATA_IN : signal is true; - attribute syn_useioff of DATA_VALID_IN : signal is true; - attribute syn_useioff of DATA_CTRL_IN : signal is true; - -end entity; - -architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is - - component signal_sync is - generic( - WIDTH : integer := 18; - DEPTH : integer := 3 - ); - port( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic_vector(WIDTH-1 downto 0); - D_OUT : out std_logic_vector(WIDTH-1 downto 0) - ); - end component; - - signal buf_DATA_IN : std_logic_vector(15 downto 0); - signal buf_DATA_VALID_IN : std_logic; - signal buf_DATA_CTRL_IN : std_logic; - - signal reg_DATA_IN : std_logic_vector(15 downto 0); - signal reg_DATA_VALID_IN : std_logic; - signal reg_DATA_CTRL_IN : std_logic; - - signal last_DATA_CTRL_IN : std_logic; - signal link_running : std_logic; - - signal buf_DATA_VALID_OUT : std_logic; - signal buf_DATA_CTRL_OUT : std_logic; - signal buf_DATA_OUT : std_logic_vector(15 downto 0); - signal PRESENT_SIG : std_logic; - signal led_counter : unsigned(18 downto 0); - - signal link_led : std_logic; - signal tx_led : std_logic; - signal rx_led : std_logic; - --signal resync : std_logic; - --signal resync_counter : unsigned(4 downto 0); - - signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal buf_MED_READ_OUT : std_logic; - signal buf_MED_DATAREADY_OUT : std_logic; - signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal buf_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); - - signal not_connected : std_logic; - signal resync_received: std_logic; - type link_state_t is (STARTUP, WAITING, WORKING, RESYNCING, RESYNC_WAIT); - signal link_state : link_state_t; - signal med_error : std_logic_vector(2 downto 0); - signal pattern_counter : unsigned(11 downto 0); - signal pattern_detected : std_logic; - signal state_bits : std_logic_vector(2 downto 0); - signal make_reset : std_logic; - - -begin - ------------------------ ---Receiver ------------------------ - - PROC_RX_INPUT : process(CLK) - begin - if rising_edge(CLK) then - buf_DATA_IN <= DATA_IN; - buf_DATA_VALID_IN <= DATA_VALID_IN; - buf_DATA_CTRL_IN <= DATA_CTRL_IN; - end if; - end process; - - THE_RX_SIGNAL_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 18 - ) - port map( - RESET => RESET, - D_IN(15 downto 0) => buf_DATA_IN, - D_IN(16) => buf_DATA_VALID_IN, - D_IN(17) => buf_DATA_CTRL_IN, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(15 downto 0) => reg_DATA_IN, - D_OUT(16) => reg_DATA_VALID_IN, - D_OUT(17) => reg_DATA_CTRL_IN - ); - - - PROC_RX_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - rx_counter <= c_H0; - elsif buf_MED_DATAREADY_OUT = '1' and CLK_EN = '1' then - if rx_counter = c_max_word_number then - rx_counter <= (others => '0'); - else - rx_counter <= rx_counter + 1; - end if; - end if; - end if; - end process; - - - buf_MED_PACKET_NUM_OUT <= rx_counter; - buf_MED_DATAREADY_OUT <= reg_DATA_VALID_IN and link_running; - buf_MED_DATA_OUT <= reg_DATA_IN; - buf_MED_READ_OUT <= link_running; - MED_READ_OUT <= buf_MED_READ_OUT; - - PROC_REG_MED_OUT : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - MED_DATA_OUT <= buf_MED_DATA_OUT; - MED_DATAREADY_OUT <= '0'; - MED_PACKET_NUM_OUT<= buf_MED_PACKET_NUM_OUT; - else - MED_DATA_OUT <= buf_MED_DATA_OUT; - MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - MED_PACKET_NUM_OUT<= buf_MED_PACKET_NUM_OUT; - end if; - end if; - end process; - - ------------------------ ---Link detection & Status & Control signals ------------------------ - - STAT_OP(2 downto 0) <= med_error; - STAT_OP(8 downto 3) <= (others => '0'); - STAT_OP(9) <= link_led; - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= '0'; - STAT_OP(13) <= make_reset; - STAT_OP(14) <= not_connected; - STAT_OP(15) <= resync_received; - - - PROC_LED : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' or not_connected = '1' then - led_counter <= (others => '0'); - rx_led <= '0'; - tx_led <= '0'; - link_led <= '0'; - else - led_counter <= led_counter + 1; - link_led <= link_running; - if led_counter(18) = '1' then - led_counter <= (others => '0'); - rx_led <= '0'; - tx_led <= '0'; - end if; - if buf_MED_DATAREADY_OUT = '1' then - rx_led <= '1'; - end if; - if MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then - tx_led <= '1'; - end if; - end if; - end if; - end process; - - - PROC_SIGNAL_DETECT_PREPARE : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - last_DATA_CTRL_IN <= '0'; - pattern_detected <= '0'; - elsif reg_DATA_VALID_IN = '0' then - last_DATA_CTRL_IN <= reg_DATA_CTRL_IN; - pattern_detected <= last_DATA_CTRL_IN xor reg_DATA_CTRL_IN; - end if; - end if; - end process; - - PROC_FSM : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - link_state <= STARTUP; - link_running <= '0'; - resync_received <= '0'; - not_connected <= '1'; - make_reset <= '0'; - else - case link_state is - when STARTUP => - med_error <= ERROR_NC; - link_running <= '0'; - not_connected <= '1'; - resync_received <= '0'; - if pattern_detected = '1' then - not_connected <= '0'; - link_state <= WAITING; - pattern_counter <= x"040"; - end if; - - when WAITING => - med_error <= ERROR_WAIT; - if pattern_detected = '1' and reg_DATA_VALID_IN = '0' then - pattern_counter <= pattern_counter + "1"; - elsif pattern_detected = '0' then - pattern_counter <= pattern_counter - x"40"; - end if; - if pattern_counter < x"040" then - link_state <= STARTUP; - elsif pattern_counter = x"FFF" then - link_state <= WORKING; - end if; - - when WORKING => - med_error <= ERROR_OK; - link_running <= '1'; --- if CTRL_OP(15) = '1' then --- link_state <= RESYNCING; --- resync_counter <= (others => '0'); --- link_running <= '0'; --- end if; --- if (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '1' and rx_counter /= c_H0) --- or (reg_DATA_VALID_IN = '1' and reg_DATA_CTRL_IN = '0' and rx_counter = c_H0) then --- resync_needed <= '1'; --- else --- resync_needed <= '0'; --- end if; - if reg_DATA_VALID_IN = '0' and reg_DATA_IN = x"FEFE" then - resync_received <= '1'; - else - resync_received <= '0'; - make_reset <= resync_received; - end if; - - if pattern_detected = '0' then - link_running <= '0'; - link_state <= STARTUP; - end if; - --- when RESYNCING => --- med_error <= ERROR_WAIT; --- resync <= '1'; --- if CTRL_OP(15) = '0' then --- resync <= '0'; --- link_state <= RESYNC_WAIT; --- end if; - - when RESYNC_WAIT => - med_error <= ERROR_WAIT; - if reg_DATA_VALID_IN = '0' and reg_DATA_IN = x"AAAA" then - link_state <= WAITING; - pattern_counter <= x"040"; - elsif pattern_detected = '0' then - link_state <= STARTUP; - end if; - - when others => - link_state <= STARTUP; - end case; - end if; - end if; - end process; - - state_bits <= "000" when link_state = STARTUP else - "001" when link_state = WAITING else - "010" when link_state = RESYNCING else - "011" when link_state = RESYNC_WAIT else - "100" when link_state = WORKING else "111"; - - ------------------------ ---Sender ------------------------ - - ---Generate tx signals - PROC_SEND_DATA : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_DATA_VALID_OUT <= '0'; - buf_DATA_CTRL_OUT <= '0'; - buf_DATA_OUT <= (others => '0'); - PRESENT_SIG <= '0'; - elsif CTRL_OP(15) = '1' then - buf_DATA_VALID_OUT <= '0'; - buf_DATA_CTRL_OUT <= not buf_DATA_CTRL_OUT; - buf_DATA_OUT <= x"FEFE"; - elsif MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then - buf_DATA_VALID_OUT <= '1'; - buf_DATA_OUT <= MED_DATA_IN; - if MED_PACKET_NUM_IN = c_H0 then - buf_DATA_CTRL_OUT <= '1'; - else - buf_DATA_CTRL_OUT <= '0'; - end if; - else - buf_DATA_OUT <= x"AAAA"; - buf_DATA_CTRL_OUT <= PRESENT_SIG; - buf_DATA_VALID_OUT <= '0'; - PRESENT_SIG <= not PRESENT_SIG; - end if; - end if; - end process; - ---Generate O-FF - PROC_OUTPUT : process(CLK) - begin - if rising_edge(CLK) then - DATA_VALID_OUT <= buf_DATA_VALID_OUT; - DATA_CTRL_OUT <= buf_DATA_CTRL_OUT; - DATA_OUT <= buf_DATA_OUT; - end if; - end process; - - - ------------------------ ---Debug ------------------------ - -STAT_DEBUG(15 downto 0) <= reg_DATA_IN; -STAT_DEBUG(16) <= reg_DATA_VALID_IN; -STAT_DEBUG(17) <= reg_DATA_CTRL_IN; -STAT_DEBUG(18) <= resync_received; -STAT_DEBUG(22 downto 19)<= std_logic_vector(pattern_counter(3 downto 0)); -STAT_DEBUG(23) <= '0'; -STAT_DEBUG(26 downto 24)<= state_bits; - -STAT_DEBUG(63 downto 27) <= (others => '0'); - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_med_16_IC.vhd b/oldfiles/trb_net16_med_16_IC.vhd deleted file mode 100644 index 33f3153..0000000 --- a/oldfiles/trb_net16_med_16_IC.vhd +++ /dev/null @@ -1,483 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; - -entity trb_net16_med_16_IC is - generic( - DATA_CLK_OUT_PHASE : std_logic := '1' - ); - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_VALID_OUT : out std_logic; - DATA_CTRL_OUT : out std_logic; - DATA_CLK_OUT : out std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_VALID_IN : in std_logic; - DATA_CTRL_IN : in std_logic; - DATA_CLK_IN : in std_logic; - - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(63 downto 0) - ); -end entity; - - - -architecture trb_net16_med_16_IC_arch of trb_net16_med_16_IC is - signal buf_DATA_IN : std_logic_vector(15 downto 0); - signal buf_DATA_VALID_IN : std_logic; - signal buf_DATA_CTRL_IN : std_logic; - signal reg_DATA_IN : std_logic_vector(15 downto 0); - signal reg_DATA_VALID_IN : std_logic; - signal reg_DATA_CTRL_IN : std_logic; - - signal rx_allow_qrx : std_logic; - signal rx_fifo_read : std_logic; - signal rx_fifo_write : std_logic; - signal rx_fifo_reset : std_logic; - signal rx_fifo_full : std_logic; - signal rx_fifo_empty : std_logic; - signal rx_fifo_valid_read : std_logic; - signal rx_fifo_dout : std_logic_vector(17 downto 0); - - signal rx_allow : std_logic; - signal tx_allow : std_logic; - - signal rx_counter : unsigned(2 downto 0); - - signal buf_MED_DATAREADY_OUT : std_logic; - signal buf_MED_DATA_OUT : std_logic_vector(15 downto 0); - signal buf_MED_READ_OUT : std_logic; - - signal buf_DATA_VALID_OUT : std_logic; - signal buf_DATA_CTRL_OUT : std_logic; - signal buf_DATA_OUT : std_logic_vector(15 downto 0); - - signal reg0_DATA_VALID_IN : std_logic; - signal reg0_DATA_CTRL_IN : std_logic; - signal reg0_DATA_IN : std_logic_vector(15 downto 0); - - signal med_error : std_logic_vector(2 downto 0); - signal link_led : std_logic; - signal link_running : std_logic; - signal tx_led : std_logic; - signal rx_led : std_logic; - signal make_reset : std_logic; - signal not_connected : std_logic; - signal resync_received : std_logic; - signal led_counter : unsigned(18 downto 0); - - signal state_bits : std_logic_vector(2 downto 0); - type link_state_t is (STARTUP, WAITING, WORKING, RESYNC_WAIT); - signal link_state : link_state_t; - signal pattern_detected_q : std_logic; - - signal pattern_counter : unsigned(11 downto 0); - signal pattern_detected : std_logic; - signal last_DATA_CTRL_IN : std_logic; - signal present_sig : std_logic; - - - signal rx_idle_pattern : std_logic; - signal rx_idle_pattern_q : std_logic; - signal rx_resync_pattern : std_logic; - signal rx_resync_pattern_q : std_logic; - signal pattern_valid : std_logic; - signal pattern_valid_q : std_logic; - - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of trb_net16_med_16_IC_arch : architecture is "media_interface_group"; - -begin - -------------------------------------------- --- RX Input -------------------------------------------- - - THE_INPUT_FF : process(DATA_CLK_IN) - begin - if falling_edge(DATA_CLK_IN) then - buf_DATA_IN <= DATA_IN; - buf_DATA_VALID_IN <= DATA_VALID_IN; - buf_DATA_CTRL_IN <= DATA_CTRL_IN; - end if; - end process; - - - THE_INPUT_SYNC : process(DATA_CLK_IN) - begin - if falling_edge(DATA_CLK_IN) then - reg0_DATA_IN <= buf_DATA_IN; - reg0_DATA_VALID_IN <= buf_DATA_VALID_IN; - reg0_DATA_CTRL_IN <= buf_DATA_CTRL_IN; - end if; - end process; - THE_INPUT_SYNC_2 : process(DATA_CLK_IN) - begin - if rising_edge(DATA_CLK_IN) then - reg_DATA_IN <= reg0_DATA_IN; - reg_DATA_VALID_IN <= reg0_DATA_VALID_IN; - reg_DATA_CTRL_IN <= reg0_DATA_CTRL_IN; - end if; - end process; - --- THE_INPUT_SYNC : signal_sync --- generic map( --- DEPTH => 1, --- WIDTH => 18 --- ) --- port map( --- RESET => RESET, --- D_IN(15 downto 0) => buf_DATA_IN, --- D_IN(16) => buf_DATA_VALID_IN, --- D_IN(17) => buf_DATA_CTRL_IN, --- CLK0 => DATA_CLK_IN, --- CLK1 => DATA_CLK_IN, --- D_OUT(15 downto 0) => reg_DATA_IN, --- D_OUT(16) => reg_DATA_VALID_IN, --- D_OUT(17) => reg_DATA_CTRL_IN --- ); - -------------------------------------------- --- RX Fifo -------------------------------------------- - - THE_RX_FIFO : trb_net_fifo_16bit_bram_dualport - port map( - read_clock_in => CLK, - write_clock_in => DATA_CLK_IN, - read_enable_in => rx_fifo_read, - write_enable_in => rx_fifo_write, - fifo_gsr_in => rx_fifo_reset, - write_data_in(15 downto 0) => reg_DATA_IN, - write_data_in(16) => reg_DATA_VALID_IN, - write_data_in(17) => reg_DATA_CTRL_IN, - read_data_out => rx_fifo_dout, - full_out => rx_fifo_full, - empty_out => rx_fifo_empty, - fifostatus_out => open, - valid_read_out => open, - almost_empty_out => open, - almost_full_out => open - ); - - rx_fifo_write <= reg_DATA_VALID_IN and rx_allow_qrx; - rx_fifo_reset <= RESET or not rx_allow_qrx; - rx_fifo_read <= rx_allow; - - -------------------------------------------- --- RX Output -------------------------------------------- - - PROC_RX_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - rx_counter <= unsigned(c_H0); - elsif buf_MED_DATAREADY_OUT = '1' and CLK_EN = '1' then - if rx_counter = unsigned(c_max_word_number) then - rx_counter <= (others => '0'); - else - rx_counter <= rx_counter + 1; - end if; - end if; - end if; - end process; - - PROC_RX_READ : process(CLK) - begin - if rising_edge(CLK) then - rx_fifo_valid_read <= rx_fifo_read and not rx_fifo_empty; - buf_MED_DATAREADY_OUT <= rx_fifo_valid_read; - buf_MED_DATA_OUT <= rx_fifo_dout(15 downto 0); - end if; - end process; - - - MED_DATA_OUT <= buf_MED_DATA_OUT; - MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - MED_PACKET_NUM_OUT <= std_logic_vector(rx_counter); - - -------------------------------------------- --- TX -------------------------------------------- - - - buf_MED_READ_OUT <= tx_allow; - MED_READ_OUT <= buf_MED_READ_OUT; - - - PROC_SEND_DATA : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_DATA_VALID_OUT <= '0'; - buf_DATA_CTRL_OUT <= '0'; - buf_DATA_OUT <= (others => '0'); - present_sig <= '0'; - elsif CTRL_OP(15) = '1' then - buf_DATA_VALID_OUT <= '0'; - buf_DATA_CTRL_OUT <= not buf_DATA_CTRL_OUT; - buf_DATA_OUT <= x"FEFE"; - elsif MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then - buf_DATA_VALID_OUT <= '1'; - buf_DATA_OUT <= MED_DATA_IN; - if MED_PACKET_NUM_IN = c_H0 then - buf_DATA_CTRL_OUT <= '1'; - else - buf_DATA_CTRL_OUT <= '0'; - end if; - else - buf_DATA_OUT <= x"AAAA"; - buf_DATA_CTRL_OUT <= present_sig; - buf_DATA_VALID_OUT <= '0'; - present_sig <= not present_sig; - end if; - end if; - end process; - - - THE_CLK_OUT : ddr_off - port map( - Clk => CLK, - Data(0) => not DATA_CLK_OUT_PHASE, - Data(1) => DATA_CLK_OUT_PHASE, - Q(0) => DATA_CLK_OUT - ); - - - PROC_DATA_OUTPUT : process(CLK) - begin - if rising_edge(CLK) then - DATA_VALID_OUT <= buf_DATA_VALID_OUT; - DATA_CTRL_OUT <= buf_DATA_CTRL_OUT; - DATA_OUT <= buf_DATA_OUT; - end if; - end process; - - -------------------------------------------- --- Link Control -------------------------------------------- - - PROC_SIGNAL_DETECT_PREPARE : process(DATA_CLK_IN) - begin - if rising_edge(DATA_CLK_IN) then - if RESET = '1' then - last_DATA_CTRL_IN <= '0'; - pattern_detected <= '0'; - pattern_valid <= '0'; - elsif reg_DATA_VALID_IN = '0' then - last_DATA_CTRL_IN <= reg_DATA_CTRL_IN; - pattern_detected <= last_DATA_CTRL_IN xor reg_DATA_CTRL_IN; - pattern_valid <= pattern_detected and not reg_DATA_VALID_IN; - end if; - end if; - end process; - - - PROC_FSM : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - link_state <= STARTUP; - link_running <= '0'; - resync_received <= '0'; - not_connected <= '1'; - make_reset <= '0'; - rx_allow <= '0'; - tx_allow <= '0'; - else - case link_state is - when STARTUP => - med_error <= ERROR_NC; - link_running <= '0'; - not_connected <= '1'; - resync_received <= '0'; - rx_allow <= '0'; - tx_allow <= '0'; - if pattern_detected_q = '1' then - not_connected <= '0'; - link_state <= WAITING; - pattern_counter <= x"040"; - end if; - - when WAITING => - med_error <= ERROR_WAIT; - if pattern_valid_q = '1' then - pattern_counter <= pattern_counter + "1"; - elsif pattern_detected_q = '0' then - pattern_counter <= pattern_counter - x"39"; - end if; - if pattern_counter < x"040" then - link_state <= STARTUP; - elsif pattern_counter = x"DFF" then - rx_allow <= '1'; - elsif pattern_counter = x"FFF" then - link_state <= WORKING; - tx_allow <= '1'; - end if; - - when WORKING => - med_error <= ERROR_OK; - link_running <= '1'; - if rx_resync_pattern_q = '1' then - resync_received <= '1'; - else - resync_received <= '0'; - make_reset <= resync_received; - end if; - - if pattern_detected_q = '0' then - link_running <= '0'; - link_state <= STARTUP; - end if; - - when RESYNC_WAIT => - med_error <= ERROR_WAIT; - if rx_idle_pattern_q = '1' then - link_state <= WAITING; - pattern_counter <= x"040"; - elsif pattern_detected_q = '0' then - link_state <= STARTUP; - end if; - - when others => - link_state <= STARTUP; - end case; - end if; - end if; - end process; - - state_bits <= "000" when link_state = STARTUP else - "001" when link_state = WAITING else - "011" when link_state = RESYNC_WAIT else - "100" when link_state = WORKING else "111"; - -------------------------------------------- --- Transfer RX status to sys clock domain -------------------------------------------- - - rx_idle_pattern <= '1' when reg_DATA_IN = x"AAAA" and reg_DATA_VALID_IN = '0' else '0'; - rx_resync_pattern <= '1' when reg_DATA_IN = x"FEFE" and reg_DATA_VALID_IN = '0' else '0'; - - - THE_SYNC_TO_SYS : signal_sync - generic map( - DEPTH => 3, - WIDTH => 4 - ) - port map( - RESET => RESET, - D_IN(0) => pattern_detected, - D_IN(1) => rx_idle_pattern, - D_IN(2) => rx_resync_pattern, - D_IN(3) => pattern_valid, - CLK0 => DATA_CLK_IN, - CLK1 => CLK, - D_OUT(0) => pattern_detected_q, - D_OUT(1) => rx_idle_pattern_q, - D_OUT(2) => rx_resync_pattern_q, - D_OUT(3) => pattern_valid_q - ); - - THE_SYNC_TO_RX : signal_sync - generic map( - DEPTH => 3, - WIDTH => 1 - ) - port map( - RESET => RESET, - D_IN(0) => rx_allow, - CLK0 => CLK, - CLK1 => DATA_CLK_IN, - D_OUT(0) => rx_allow_qrx - ); - - - - - -------------------------------------------- --- Link Status Information -------------------------------------------- - - PROC_LED : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' or not_connected = '1' then - led_counter <= (others => '0'); - rx_led <= '0'; - tx_led <= '0'; - link_led <= '0'; - else - led_counter <= led_counter + 1; - link_led <= link_running; - if led_counter(18) = '1' then - led_counter <= (others => '0'); - rx_led <= '0'; - tx_led <= '0'; - end if; - if buf_MED_DATAREADY_OUT = '1' then - rx_led <= '1'; - end if; - if MED_DATAREADY_IN = '1' and buf_MED_READ_OUT = '1' then - tx_led <= '1'; - end if; - end if; - end if; - end process; - - - STAT_OP(2 downto 0) <= med_error; - STAT_OP(8 downto 3) <= (others => '0'); - STAT_OP(9) <= link_led; - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= '0'; - STAT_OP(13) <= make_reset; - STAT_OP(14) <= not_connected; - STAT_OP(15) <= resync_received; - - -------------------------------------------- --- Debug -------------------------------------------- - STAT_DEBUG(0) <= reg_DATA_VALID_IN; - STAT_DEBUG(1) <= reg_DATA_CTRL_IN; - STAT_DEBUG(2) <= make_reset; - STAT_DEBUG(3) <= MED_DATAREADY_IN; - STAT_DEBUG(4) <= last_DATA_CTRL_IN; - STAT_DEBUG(5) <= buf_DATA_VALID_OUT; - STAT_DEBUG(6) <= buf_MED_READ_OUT; - STAT_DEBUG(7) <= resync_received; - STAT_DEBUG(15 downto 8) <= reg_DATA_IN(7 downto 0); - STAT_DEBUG(18 downto 16) <= state_bits; - STAT_DEBUG(31 downto 19) <= buf_DATA_OUT(12 downto 0); - - STAT_DEBUG(63 downto 32) <= (others => '0'); - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_med_16_SDR_OS.vhd b/oldfiles/trb_net16_med_16_SDR_OS.vhd deleted file mode 100644 index b716a46..0000000 --- a/oldfiles/trb_net16_med_16_SDR_OS.vhd +++ /dev/null @@ -1,477 +0,0 @@ ---media interface with 16 data lines, single data rate and oversampling of RX input ---oversampling running at 250 MHz - - - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net16_med_16_SDR_OS is - generic( - TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - - -- Media direction port - TX_DATA_OUT : out std_logic_vector (15 downto 0); - TX_CLK_OUT : out std_logic; - TX_CTRL_OUT : out std_logic_vector (3 downto 0); - RX_DATA_IN : in std_logic_vector (15 downto 0); - RX_CLK_IN : in std_logic; - RX_CTRL_IN : in std_logic_vector (3 downto 0); - - -- Status and control port - STAT_OP: out std_logic_vector (15 downto 0); - CTRL_OP: in std_logic_vector (15 downto 0); - - STAT: out std_logic_vector (31 downto 0); - CTRL: in std_logic_vector (31 downto 0) - ); -end entity; - -architecture trb_net16_med_16_SDR_OS_arch of trb_net16_med_16_SDR_OS is - component trb_net_clock_generator is - generic( - FREQUENCY_IN : real; - FREQUENCY_OUT : real; - CLOCK_MULT : integer range 1 to 32; - CLOCK_DIV : integer range 1 to 32; - CLKIN_DIVIDE_BY_2 : boolean; - CLKIN_PERIOD : real - ); - port( - RESET : in std_logic; - CLK_IN : in std_logic; - CLK_OUT : out std_logic; - LOCKED : out std_logic - ); - end component; - - component trb_net_fifo_16bit_bram_dualport is - generic( - USE_STATUS_FLAGS : integer := c_YES - ); - port ( - read_clock_in: IN std_logic; - write_clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0); - valid_read_out: OUT std_logic; - almost_empty_out:OUT std_logic; - almost_full_out :OUT std_logic - ); - end component; - - component dualdatarate_flipflop is - --1 clock, no CE, PRE for Lattice SCM - generic( - WIDTH : integer := 1 - ); - port( - C0 : in std_logic; - C1 : in std_logic; - CE : in std_logic; - CLR : in std_logic; - D0 : in std_logic_vector(WIDTH-1 downto 0); - D1 : in std_logic_vector(WIDTH-1 downto 0); - PRE : in std_logic; - Q : out std_logic_vector(WIDTH-1 downto 0) - ); - end component; - - signal RECV_CLK, recv_clk_locked : std_logic; - signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic; - signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(3 downto 0); - signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(15 downto 0); - - signal rx_datavalid : std_logic; - signal rx_first_packet : std_logic; - signal rx_reset : std_logic; - signal rx_parity : std_logic; - signal rx_parity_match : std_logic; - - signal rx_fifo_read_enable : std_logic; - signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic; - signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0); - signal rx_fifo_data_out : std_logic_vector(17 downto 0); - signal rx_fifo_full : std_logic; - signal rx_fifo_empty : std_logic; - signal rx_fifostatus_out : std_logic_vector(3 downto 0); - signal rx_valid_read_out : std_logic; - signal rx_almost_empty_out : std_logic; - signal rx_almost_full_out : std_logic; - - - signal buf_INT_DATAREADY_OUT : std_logic; - - signal rx_packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal wait_for_startup : std_logic; - signal wait_for_startup_slow : std_logic; - signal rx_CLK_counter : std_logic_vector(4 downto 0); - signal rx_clock_detect : std_logic; - - signal med_reset : std_logic; - - signal tx_datavalid, tx_first_packet, tx_reset, tx_parity : std_logic; - signal buf_INT_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal buf_INT_READ_OUT : std_logic; - signal tx_clock_enable : std_logic; - signal next_tx_reset : std_logic; - signal buf_tx_reset : std_logic; - signal buf_tx_clk : std_logic; - signal recv_clk_real_locked : std_logic; - signal locked_counter : std_logic_vector(19 downto 0); - - signal led_counter : std_logic_vector(18 downto 0); - signal send_resync_counter : std_logic_vector(11 downto 0); - signal send_resync : std_logic; - signal rx_led, tx_led, link_led : std_logic; - signal med_error : std_logic_vector(2 downto 0); - signal trbnet_reset : std_logic; -begin - - ---Transmitter (full speed only) -------------------------- - INT_READ_OUT <= buf_INT_READ_OUT; - buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset; - - TX_DATA_OUT <= buf_INT_DATA_IN; - TX_CTRL_OUT(0) <= tx_datavalid; - TX_CTRL_OUT(1) <= tx_first_packet; - TX_CTRL_OUT(2) <= tx_reset; - TX_CTRL_OUT(3) <= tx_parity; - - tx_clock_enable <= not RESET; - - next_tx_reset <= CTRL_OP(15) or (recv_clk_real_locked and wait_for_startup_slow); - - - process(CLK) - begin - if rising_edge(CLK) then - TX_CLK_OUT <= buf_tx_clk; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - tx_datavalid <= '0'; - tx_reset <= '1'; - buf_tx_reset <= '1'; - buf_INT_DATA_IN <= (others => '0'); - tx_first_packet <= '0'; - tx_parity <= '0'; - buf_tx_clk <= '0'; - else - buf_INT_DATA_IN <= INT_DATA_IN; - tx_datavalid <= INT_DATAREADY_IN and buf_INT_READ_OUT; - if INT_PACKET_NUM_IN = c_H0 then - tx_first_packet <= '1'; - else - tx_first_packet <= '0'; - end if; - tx_reset <= buf_tx_reset; - buf_tx_reset <= next_tx_reset; - tx_parity <= xor_all(INT_DATA_IN); - buf_tx_clk <= not buf_tx_clk; - end if; - end if; - end process; - - - ---Receiver -------------------------- - RECV_CLOCK_GEN : trb_net_clock_generator - generic map( - FREQUENCY_IN => 100.0, - FREQUENCY_OUT => 200.0, - CLOCK_MULT => 2, - CLOCK_DIV => 1, - CLKIN_DIVIDE_BY_2 => false, - CLKIN_PERIOD => 10.0 - ) - port map( - RESET => RESET, - CLK_IN => CLK, - CLK_OUT => RECV_CLK, - LOCKED => recv_clk_locked - ); - -process(CLK) - begin - if rising_edge(CLK) then - if recv_clk_locked = '0' then - locked_counter <= (others => '0'); - recv_clk_real_locked <= '0'; - else - if locked_counter /= x"0000F" then - locked_counter <= locked_counter + 1; - else - recv_clk_real_locked <= '1'; - end if; - end if; - end if; - end process; - - RX_INPUT_REG : process(RECV_CLK) - begin - if rising_edge(RECV_CLK) then - reg_RX_CLK <= RX_CLK_IN; - reg_RX_CTRL <= RX_CTRL_IN; - reg_RX_DATA <= RX_DATA_IN; - end if; - end process; - - RX_REG : process(RECV_CLK, recv_clk_real_locked) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' then - buf_RX_CTRL <= (others => '0'); - buf_RX_CLK <= '0'; - last_RX_CLK <= '0'; - buf_RX_DATA <= (others => '0'); - else - buf_RX_CLK <= reg_RX_CLK; - buf_RX_DATA <= reg_RX_DATA; - buf_RX_CTRL <= reg_RX_CTRL; - last_RX_CLK <= buf_RX_CLK; - end if; - end if; - end process; - - rx_datavalid <= buf_RX_CTRL(0); - rx_first_packet <= buf_RX_CTRL(1); - rx_reset <= buf_RX_CTRL(2); - rx_parity <= buf_RX_CTRL(3); - - rx_parity_match <= '1' when rx_parity = xor_all(buf_RX_DATA) else '0'; - next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid; - next_rx_fifo_data_in <= rx_first_packet & rx_parity_match & buf_RX_DATA; - - reg_fifo_in : process(RECV_CLK) - begin - if rising_edge(RECV_CLK) then - rx_fifo_write_enable <= next_rx_fifo_write_enable; - rx_fifo_data_in <= next_rx_fifo_data_in; - end if; - end process; - - RX_FIFO : trb_net_fifo_16bit_bram_dualport - port map( - read_clock_in => CLK, - write_clock_in => RECV_CLK, - read_enable_in => rx_fifo_read_enable, - write_enable_in => rx_fifo_write_enable, - fifo_gsr_in => med_reset, - write_data_in => rx_fifo_data_in, - read_data_out => rx_fifo_data_out, - full_out => rx_fifo_full, - empty_out => rx_fifo_empty, - fifostatus_out => rx_fifostatus_out, - valid_read_out => rx_valid_read_out, - almost_empty_out => rx_almost_empty_out, - almost_full_out => rx_almost_full_out - ); - - rx_fifo_read_enable <= INT_READ_IN; - - INT_DATA_OUT <= rx_fifo_data_out(15 downto 0); - INT_PACKET_NUM_OUT <= rx_packet_counter; - INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - - packet_counter_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - rx_packet_counter <= "100"; - elsif buf_INT_DATAREADY_OUT = '1' then - if rx_packet_counter = c_max_word_number then - rx_packet_counter <= (others => '0'); - else - rx_packet_counter <= rx_packet_counter + 1; - end if; - end if; - end if; - end process; - - - rx_dataready_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - buf_INT_DATAREADY_OUT <= '0'; - else - buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty; - end if; - end if; - end process; - - ---monitor link -------------------------- - process(CLK) - begin - if rising_edge(CLK) then - wait_for_startup_slow <= wait_for_startup; - end if; - end process; - - process(RECV_CLK, recv_clk_real_locked,med_reset) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then - wait_for_startup <= '1'; - elsif rx_reset = '1' and recv_clk_locked = '1' then - wait_for_startup <= '0'; - end if; - end if; - end process; - - - ERROR_OUT_gen : process(CLK) - begin - if rising_edge(CLK) then - if recv_clk_real_locked = '0' or rx_clock_detect = '0' then - med_error <= ERROR_NC; - elsif (buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(16) = '0') then --Parity error - med_error <= ERROR_ENCOD; - elsif (rx_packet_counter /= "100" and buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(17) = '1') then - med_error <= ERROR_FATAL; --Counter error - else - med_error <= ERROR_OK; - end if; - end if; - end process; - - - rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '0'; - elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '1'; - elsif rx_CLK_counter /= 31 then - rx_CLK_counter <= rx_CLK_counter + 1; - elsif rx_CLK_counter = 31 then - rx_clock_detect <= '0'; - end if; - end if; - end process; - - ---STAT & CTRL Ports -------------------------- - ---LED - link_led <= rx_clock_detect and not wait_for_startup_slow; - - process(CLK) - begin - if rising_edge(CLK) then - if led_counter(18) = '1' then - led_counter <= (others => '0'); - else - led_counter <= led_counter + 1; - end if; - if rx_fifo_empty = '0' then - rx_led <= '1'; - elsif led_counter(18) = '1' then - rx_led <= '0'; - end if; - if tx_datavalid = '1' then - tx_led <= '1'; - elsif led_counter(18) = '1' then - tx_led <= '0'; - end if; - end if; - end process; - - - STAT_OP(2 downto 0) <= med_error; - STAT_OP(8 downto 3) <= (others => '0'); - STAT_OP(9) <= link_led; - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= '0'; - STAT_OP(13) <= trbnet_reset; - STAT_OP(14) <= rx_clock_detect; - STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0'; - - STAT(12) <= rx_parity_match; - STAT(11) <= RECV_CLK; - STAT(10) <= recv_clk_real_locked; - STAT(9) <= rx_reset; - STAT(8) <= buf_RX_CLK xor last_RX_CLK; - STAT(7) <= recv_clk_locked; - STAT(6) <= wait_for_startup; - STAT(5) <= rx_first_packet; - STAT(4) <= buf_tx_clk; --not or_all(INT_PACKET_NUM_IN); --tx_first_packet; - STAT(3) <= rx_datavalid; - STAT(2) <= next_tx_reset; - STAT(1) <= buf_RX_CLK; - - STAT(13) <= or_all(rx_fifostatus_out); - STAT(14) <= rx_valid_read_out; - STAT(15) <= rx_almost_empty_out; - STAT(16) <= rx_almost_full_out; - STAT(31 downto 17) <= (others => '0'); - - med_reset <= RESET or send_resync; - trbnet_reset <= rx_reset or not recv_clk_real_locked; - - ---detect resync - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - send_resync <= '0'; - send_resync_counter <= (others => '0'); - else - if not (send_resync_counter = 0) then - send_resync_counter <= send_resync_counter + 1; - end if; - if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then - send_resync <= '1'; - send_resync_counter <= send_resync_counter + 1; - end if; - if send_resync_counter = x"00F" then - send_resync <= '0'; - end if; - end if; - end if; - end process; - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_med_8_DDR_OS.vhd b/oldfiles/trb_net16_med_8_DDR_OS.vhd deleted file mode 100644 index 2b47211..0000000 --- a/oldfiles/trb_net16_med_8_DDR_OS.vhd +++ /dev/null @@ -1,491 +0,0 @@ ---media interface with 16 data lines, single data rate and oversampling of RX input ---oversampling running at 250 MHz - - - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net16_med_8_DDR_OS is - generic( - TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - - -- Media direction port - TX_DATA_OUT : out std_logic_vector (7 downto 0); - TX_CLK_OUT : out std_logic; - TX_CTRL_OUT : out std_logic_vector (1 downto 0); - RX_DATA_IN : in std_logic_vector (7 downto 0); - RX_CLK_IN : in std_logic; - RX_CTRL_IN : in std_logic_vector (1 downto 0); - - -- Status and control port - STAT_OP: out std_logic_vector (15 downto 0); - CTRL_OP: in std_logic_vector (15 downto 0); - - STAT: out std_logic_vector (31 downto 0); - CTRL: in std_logic_vector (31 downto 0) - ); -end entity; - -architecture trb_net16_med_8_DDR_OS_arch of trb_net16_med_8_DDR_OS is - - component trb_net_clock_generator is - generic( - FREQUENCY_IN : real; - FREQUENCY_OUT : real; - CLOCK_MULT : integer range 1 to 32; - CLOCK_DIV : integer range 1 to 32; - CLKIN_DIVIDE_BY_2 : boolean; - CLKIN_PERIOD : real - ); - port( - RESET : in std_logic; - CLK_IN : in std_logic; - CLK_OUT : out std_logic; - LOCKED : out std_logic - ); - end component; - - component trb_net_fifo_16bit_bram_dualport is - generic( - USE_STATUS_FLAGS : integer := c_YES - ); - port ( - read_clock_in: IN std_logic; - write_clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0); - valid_read_out: OUT std_logic; - almost_empty_out:OUT std_logic; - almost_full_out :OUT std_logic - ); - end component; - - component signal_sync is - generic( - WIDTH : integer := 1; -- - DEPTH : integer := 3 - ); - port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output - ); - end component; - - signal RECV_CLK, recv_clk_locked : std_logic; - signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic; - signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(1 downto 0); - signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(7 downto 0); - - signal rx_datavalid : std_logic; - signal rx_reset : std_logic; - - signal rx_fifo_read_enable : std_logic; - signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic; - signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0); - signal rx_fifo_data_out : std_logic_vector(17 downto 0); - signal rx_fifo_full : std_logic; - signal rx_fifo_empty : std_logic; - signal rx_fifostatus_out : std_logic_vector(3 downto 0); - signal rx_valid_read_out : std_logic; - signal rx_almost_empty_out : std_logic; - signal rx_almost_full_out : std_logic; - signal saved_fifo_data_out : std_logic_vector(7 downto 0); - - signal buf_INT_DATAREADY_OUT : std_logic; - - signal rx_packet_counter : std_logic_vector(3 downto 0); - signal wait_for_startup : std_logic; - signal wait_for_startup_slow : std_logic; - signal rx_CLK_counter : std_logic_vector(4 downto 0); - signal rx_clock_detect : std_logic; - - signal med_reset : std_logic; - - signal tx_datavalid, tx_first_packet, tx_reset, tx_parity : std_logic; - signal buf_INT_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal buf_INT_READ_OUT : std_logic; - signal tx_clock_enable : std_logic; - signal next_tx_reset : std_logic; - signal buf_tx_reset : std_logic; - signal buf_tx_clk : std_logic; - signal recv_clk_real_locked : std_logic; - signal locked_counter : std_logic_vector(19 downto 0); - - signal led_counter : std_logic_vector(18 downto 0); - signal rx_led, tx_led, link_led : std_logic; - signal med_error : std_logic_vector(2 downto 0); - - signal tx_data : std_logic_vector(7 downto 0); - signal tx_word_waiting : std_logic; - signal tx_data_buffer : std_logic_vector(7 downto 0); - signal next_recv_clk_locked : std_logic; - signal recv_clk_real_locked_q : std_logic; -begin - - ---Transmitter (full speed only) -------------------------- - INT_READ_OUT <= buf_INT_READ_OUT; - - - - process(CLK) - begin - if rising_edge(CLK) then - TX_CLK_OUT <= buf_tx_clk; - TX_DATA_OUT <= tx_data; - TX_CTRL_OUT(0) <= tx_datavalid; - TX_CTRL_OUT(1) <= buf_tx_reset; - end if; - end process; - - - process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - buf_tx_reset <= '1'; - buf_tx_clk <= '0'; - else - buf_tx_reset <= (recv_clk_real_locked_q and wait_for_startup_slow); - buf_tx_clk <= not buf_tx_clk; - end if; - end if; - end process; - - - process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - tx_datavalid <= '0'; - buf_INT_DATA_IN <= (others => '0'); - buf_INT_READ_OUT <= '0'; - tx_data <= (others => '0'); - tx_word_waiting <= '0'; - else - if tx_word_waiting = '1' then - tx_data <= tx_data_buffer; - tx_datavalid <= '1'; - buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset; - tx_word_waiting <= '0'; - elsif INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then - tx_data <= INT_DATA_IN(15 downto 8); - tx_data_buffer <= INT_DATA_IN(7 downto 0); - tx_datavalid <= '1'; - tx_word_waiting <= '1'; - buf_INT_READ_OUT <= '0'; - else - tx_datavalid <= '0'; - buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset; - end if; - end if; - end if; - end process; - - - ---Receiver -------------------------- - RECV_CLOCK_GEN : trb_net_clock_generator - generic map( - FREQUENCY_IN => 100.0, - FREQUENCY_OUT => 200.0, - CLOCK_MULT => 2, - CLOCK_DIV => 1, - CLKIN_DIVIDE_BY_2 => false, - CLKIN_PERIOD => 10.0 - ) - port map( - RESET => RESET, - CLK_IN => CLK, - CLK_OUT => RECV_CLK, - LOCKED => recv_clk_locked - ); - --- THE_SYNC_TO_CLK : signal_sync --- generic map( --- DEPTH => 2, --- WIDTH => 1 --- ) --- port map( --- RESET => RESET, --- D_IN(0) => next_recv_clk_locked, --- CLK0 => CLK, --- CLK1 => CLK, --- D_OUT(0) => recv_clk_locked --- ); - - THE_SYNC_TO_CLK_0 : signal_sync - generic map( - DEPTH => 3, - WIDTH => 1 - ) - port map( - RESET => RESET, - D_IN(0) => recv_clk_real_locked, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => recv_clk_real_locked_q - ); - -process(CLK) - begin - if rising_edge(RECV_CLK) then - if recv_clk_locked = '0' then - locked_counter <= (others => '0'); - recv_clk_real_locked <= '0'; - else - if locked_counter /= x"0000F" then - locked_counter <= locked_counter + 1; - else - recv_clk_real_locked <= '1'; - end if; - end if; - end if; - end process; - - RX_INPUT_REG : process(RECV_CLK) - begin - if rising_edge(RECV_CLK) then - reg_RX_CLK <= RX_CLK_IN; - reg_RX_CTRL <= RX_CTRL_IN; - reg_RX_DATA <= RX_DATA_IN; - end if; - end process; - - RX_REG : process(RECV_CLK, recv_clk_real_locked) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' then - buf_RX_CTRL <= (others => '0'); - buf_RX_CLK <= '0'; - last_RX_CLK <= '0'; - buf_RX_DATA <= (others => '0'); - else - buf_RX_CLK <= reg_RX_CLK; - buf_RX_DATA <= reg_RX_DATA; - buf_RX_CTRL <= reg_RX_CTRL; - last_RX_CLK <= buf_RX_CLK; - end if; - end if; - end process; - - rx_datavalid <= buf_RX_CTRL(0); - rx_reset <= buf_RX_CTRL(1); - - next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid; - next_rx_fifo_data_in <= x"00" & '0' & '0' & buf_RX_DATA; - - reg_fifo_in : process(RECV_CLK) - begin - if rising_edge(RECV_CLK) then - rx_fifo_write_enable <= next_rx_fifo_write_enable; - rx_fifo_data_in <= next_rx_fifo_data_in; - end if; - end process; - - RX_FIFO : trb_net_fifo_16bit_bram_dualport - port map( - read_clock_in => CLK, - write_clock_in => RECV_CLK, - read_enable_in => rx_fifo_read_enable, - write_enable_in => rx_fifo_write_enable, - fifo_gsr_in => med_reset, - write_data_in => rx_fifo_data_in, - read_data_out => rx_fifo_data_out, - full_out => rx_fifo_full, - empty_out => rx_fifo_empty, - fifostatus_out => rx_fifostatus_out, - valid_read_out => rx_valid_read_out, - almost_empty_out => rx_almost_empty_out, - almost_full_out => rx_almost_full_out - ); - - rx_fifo_read_enable <= INT_READ_IN; - - proc_rx_dataoutput : process(CLK) - begin - if rising_edge(CLK) then - INT_DATA_OUT <= saved_fifo_data_out(7 downto 0) & rx_fifo_data_out(7 downto 0); - INT_PACKET_NUM_OUT <= rx_packet_counter(3 downto 1); - INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - end if; - end process; - - packet_counter_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - rx_packet_counter <= "0111"; - elsif rx_fifo_read_enable = '1' and rx_fifo_empty = '0' then - if rx_packet_counter = c_max_word_number & '1' then - rx_packet_counter <= (others => '0'); - else - rx_packet_counter <= rx_packet_counter + 1; - end if; - end if; - end if; - end process; - - - rx_dataready_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - buf_INT_DATAREADY_OUT <= '0'; - saved_fifo_data_out <= (others => '0'); - else - buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty and not rx_packet_counter(0); - if rx_fifo_read_enable = '1' and rx_fifo_empty = '0' and rx_packet_counter(0) = '1' then - saved_fifo_data_out <= rx_fifo_data_out(7 downto 0); - end if; - end if; - end if; - end process; - - ---monitor link -------------------------- - - THE_SYNCTOCLK : signal_sync - generic map( - DEPTH => 3, - WIDTH => 1 - ) - port map( - RESET => RESET, - D_IN(0) => wait_for_startup, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => wait_for_startup_slow - ); - - - process(RECV_CLK, recv_clk_real_locked,med_reset) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then - wait_for_startup <= '1'; - elsif rx_reset = '1' and recv_clk_real_locked = '1' then -- - wait_for_startup <= '0'; - end if; - end if; - end process; - - - ERROR_OUT_gen : process(CLK) - begin - if rising_edge(CLK) then - if recv_clk_real_locked = '0' or rx_clock_detect = '0' then -- or wait_for_startup_slow = '1' - med_error <= ERROR_NC; - else - med_error <= ERROR_OK; - end if; - end if; - end process; - - - rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '0'; - elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '1'; - elsif rx_CLK_counter /= 31 then - rx_CLK_counter <= rx_CLK_counter + 1; - elsif rx_CLK_counter = 31 then - rx_clock_detect <= '0'; - end if; - end if; - end process; - - ---STAT & CTRL Ports -------------------------- - ---LED - link_led <= rx_clock_detect and not wait_for_startup_slow; - - process(CLK) - begin - if rising_edge(CLK) then - if led_counter(18) = '1' then - led_counter <= (others => '0'); - else - led_counter <= led_counter + 1; - end if; - if rx_fifo_empty = '0' then - rx_led <= '1'; - elsif led_counter(18) = '1' then - rx_led <= '0'; - end if; - if tx_datavalid = '1' then - tx_led <= '1'; - elsif led_counter(18) = '1' then - tx_led <= '0'; - end if; - end if; - end process; - - - STAT_OP(2 downto 0) <= med_error; - STAT_OP(8 downto 3) <= (others => '0'); - STAT_OP(9) <= link_led; - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= '0'; - STAT_OP(13) <= '0'; --trbnet_reset; - STAT_OP(14) <= rx_clock_detect; - STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0'; - - - STAT(7 downto 0) <= buf_RX_DATA; - STAT(9 downto 8) <= buf_RX_CTRL; - STAT(10) <= buf_RX_CLK; - STAT(11) <= wait_for_startup_slow; - STAT(12) <= rx_fifo_empty; - STAT(13) <= rx_fifo_read_enable; - STAT(14) <= rx_fifo_write_enable; - STAT(15) <= rx_clock_detect; - STAT(31 downto 16) <= (others => '0'); - - med_reset <= RESET; --- trbnet_reset <= rx_reset or not recv_clk_real_locked; - - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_med_8_SDR_OS.vhd b/oldfiles/trb_net16_med_8_SDR_OS.vhd deleted file mode 100644 index 613d27b..0000000 --- a/oldfiles/trb_net16_med_8_SDR_OS.vhd +++ /dev/null @@ -1,405 +0,0 @@ - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net16_med_8_SDR_OS is - generic( - TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - - -- Media direction port - TX_DATA_OUT : out std_logic_vector (7 downto 0); - TX_CLK_OUT : out std_logic; - TX_CTRL_OUT : out std_logic_vector (1 downto 0); - RX_DATA_IN : in std_logic_vector (7 downto 0); - RX_CLK_IN : in std_logic; - RX_CTRL_IN : in std_logic_vector (1 downto 0); - - -- Status and control port - STAT_OP: out std_logic_vector (15 downto 0); - CTRL_OP: in std_logic_vector (15 downto 0); - - STAT: out std_logic_vector (31 downto 0); - CTRL: in std_logic_vector (31 downto 0) - ); -end entity; - -architecture trb_net16_med_8_SDR_OS_arch of trb_net16_med_8_SDR_OS is - - component trb_net_fifo_16bit_bram_dualport is - generic( - USE_STATUS_FLAGS : integer := c_YES - ); - port ( - read_clock_in: IN std_logic; - write_clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0); - valid_read_out: OUT std_logic; - almost_empty_out:OUT std_logic; - almost_full_out :OUT std_logic - ); - end component; - - component signal_sync is - generic( - WIDTH : integer := 1; -- - DEPTH : integer := 3 - ); - port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output - ); - end component; - - signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic; - signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(1 downto 0); - signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(7 downto 0); - - signal rx_datavalid : std_logic; - signal rx_reset : std_logic; - signal rx_fifo_read_enable : std_logic; - signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic; - signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0); - signal rx_fifo_data_out : std_logic_vector(17 downto 0); - signal rx_fifo_empty : std_logic; - signal rx_packet_counter : std_logic_vector(3 downto 0); - signal rx_CLK_counter : std_logic_vector(4 downto 0); - signal rx_clock_detect : std_logic; - - - signal saved_fifo_data_out : std_logic_vector(7 downto 0); - - signal med_reset : std_logic; - - signal tx_datavalid : std_logic; - signal buf_INT_READ_OUT : std_logic; - signal buf_INT_DATAREADY_OUT : std_logic; - signal buf_tx_reset : std_logic; - signal buf_tx_clk : std_logic; - - signal led_counter : std_logic_vector(18 downto 0); - signal rx_led, tx_led, link_led : std_logic; - signal med_error : std_logic_vector(2 downto 0); - - signal tx_data : std_logic_vector(7 downto 0); - signal tx_word_waiting : std_logic; - signal tx_data_buffer : std_logic_vector(7 downto 0); - signal last_rx_fifo_read_enable : std_logic; - signal last_rx_fifo_empty : std_logic; - signal buf_tx_half_clk : std_logic; - signal rx_active : std_logic; - signal tx_active : std_logic; - signal rx_fifo_reset : std_logic; - signal active_counter : std_logic_vector(15 downto 0); - -begin - - med_reset <= RESET; - - - ---Transmitter -------------------------- - INT_READ_OUT <= buf_INT_READ_OUT; - - - - process(CLK) - begin - if rising_edge(CLK) then - TX_CLK_OUT <= buf_tx_half_clk; - TX_DATA_OUT <= tx_data; - TX_CTRL_OUT(0) <= tx_datavalid; - TX_CTRL_OUT(1) <= buf_tx_reset; - end if; - end process; - - - process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - buf_tx_reset <= '1'; - buf_tx_clk <= '0'; - buf_tx_half_clk <= '0'; - else - buf_tx_reset <= not tx_active; - buf_tx_clk <= not buf_tx_clk; - if buf_tx_clk = '1' then - buf_tx_half_clk <= not buf_tx_half_clk; - end if; - end if; - end if; - end process; - - - process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' or tx_active = '0' then - tx_datavalid <= '0'; - buf_INT_READ_OUT <= '0'; - tx_data <= (others => '0'); - tx_word_waiting <= '0'; - else - buf_INT_READ_OUT <= '0'; - if buf_tx_half_clk = '0' and buf_tx_clk = '0' then - if tx_word_waiting = '1' then - tx_data <= tx_data_buffer; - tx_datavalid <= '1'; - tx_word_waiting <= '0'; - elsif INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then - tx_data <= INT_DATA_IN(15 downto 8); - tx_data_buffer <= INT_DATA_IN(7 downto 0); - tx_datavalid <= '1'; - tx_word_waiting <= '1'; - else - tx_datavalid <= '0'; - end if; - elsif buf_tx_half_clk = '1' and buf_tx_clk = '1' then - buf_INT_READ_OUT <= not tx_word_waiting and tx_active; - end if; - end if; - end if; - end process; - - - ---Receiver -------------------------- - - RX_INPUT_REG : process(CLK) - begin - if rising_edge(CLK) then - reg_RX_CLK <= RX_CLK_IN; - reg_RX_CTRL <= RX_CTRL_IN; - reg_RX_DATA <= RX_DATA_IN; - end if; - end process; - - RX_REG : process(CLK) - begin - if rising_edge(CLK) then - buf_RX_CLK <= reg_RX_CLK; - buf_RX_DATA <= reg_RX_DATA; - buf_RX_CTRL <= reg_RX_CTRL; - last_RX_CLK <= buf_RX_CLK; - end if; - end process; - - rx_datavalid <= buf_RX_CTRL(0); - rx_reset <= buf_RX_CTRL(1); - - next_rx_fifo_write_enable <= (buf_RX_CLK and not last_RX_CLK) and rx_datavalid and rx_active; - next_rx_fifo_data_in <= x"00" & '0' & '0' & buf_RX_DATA; - - reg_fifo_in : process(CLK) - begin - if rising_edge(CLK) then - rx_fifo_write_enable <= next_rx_fifo_write_enable; - rx_fifo_data_in <= next_rx_fifo_data_in; - end if; - end process; - - RX_FIFO : trb_net_fifo_16bit_bram_dualport - port map( - read_clock_in => CLK, - write_clock_in => CLK, - read_enable_in => rx_fifo_read_enable, - write_enable_in => rx_fifo_write_enable, - fifo_gsr_in => rx_fifo_reset, - write_data_in => rx_fifo_data_in, - read_data_out => rx_fifo_data_out, - full_out => open, - empty_out => rx_fifo_empty, - fifostatus_out => open, - valid_read_out => open, - almost_empty_out => open, - almost_full_out => open - ); - - rx_fifo_reset <= med_reset or not rx_active; - rx_fifo_read_enable <= INT_READ_IN; - - proc_rx_dataoutput : process(CLK) - begin - if rising_edge(CLK) then - INT_DATA_OUT <= saved_fifo_data_out(7 downto 0) & rx_fifo_data_out(7 downto 0); - INT_PACKET_NUM_OUT <= rx_packet_counter(3 downto 1); - INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - - last_rx_fifo_read_enable <= rx_fifo_read_enable; - last_rx_fifo_empty <= rx_fifo_empty; - end if; - end process; - - packet_counter_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - rx_packet_counter <= "0111"; - elsif rx_fifo_read_enable = '1' and rx_fifo_empty = '0' then - if rx_packet_counter = c_max_word_number & '1' then - rx_packet_counter <= (others => '0'); - else - rx_packet_counter <= rx_packet_counter + 1; - end if; - end if; - end if; - end process; - - - rx_dataready_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - buf_INT_DATAREADY_OUT <= '0'; - saved_fifo_data_out <= (others => '0'); - else - buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty and not rx_packet_counter(0); - if last_rx_fifo_read_enable = '1' and last_rx_fifo_empty = '0' and rx_packet_counter(0) = '0' then - saved_fifo_data_out <= rx_fifo_data_out(7 downto 0); - end if; - end if; - end if; - end process; - - ---monitor link -------------------------- - - - ERROR_OUT_gen : process(CLK) - begin - if rising_edge(CLK) then - if rx_clock_detect = '0' or rx_active = '0' then - med_error <= ERROR_NC; - else - med_error <= ERROR_OK; - end if; - end if; - end process; - - - rx_clk_detect_counter: process (CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '0'; - elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '1'; - elsif rx_CLK_counter /= 31 then - rx_CLK_counter <= rx_CLK_counter + 1; - elsif rx_CLK_counter = 31 then - rx_clock_detect <= '0'; - end if; - end if; - end process; - - proc_active : process(CLK) - begin - if rising_edge(CLK) then - if rx_clock_detect = '0' then - active_counter <= (others => '0'); - elsif active_counter < x"FFFF" then - active_counter <= active_counter + 1; - end if; - if active_counter > x"8000" then - rx_active <= '1'; - else - rx_active <= '0'; - end if; - if active_counter = x"FFFF" then - tx_active <= '1'; - else - tx_active <= '0'; - end if; - end if; - end process; - ---STAT & CTRL Ports -------------------------- - ---LED - link_led <= rx_clock_detect and rx_active and tx_active; - - process(CLK) - begin - if rising_edge(CLK) then - if led_counter(18) = '1' then - led_counter <= (others => '0'); - else - led_counter <= led_counter + 1; - end if; - if rx_fifo_empty = '0' then - rx_led <= '1'; - elsif led_counter(18) = '1' then - rx_led <= '0'; - end if; - if tx_datavalid = '1' then - tx_led <= '1'; - elsif led_counter(18) = '1' then - tx_led <= '0'; - end if; - end if; - end process; - - - STAT_OP(2 downto 0) <= med_error; - STAT_OP(8 downto 3) <= (others => '0'); - STAT_OP(9) <= link_led; - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= '0'; - STAT_OP(13) <= '0'; --trbnet_reset; - STAT_OP(14) <= not rx_clock_detect; - STAT_OP(15) <= not rx_active; - - - STAT(7 downto 0) <= buf_RX_DATA; - STAT(9 downto 8) <= buf_RX_CTRL; - STAT(10) <= buf_RX_CLK; - STAT(11) <= '0'; - STAT(12) <= rx_fifo_empty; - STAT(13) <= rx_fifo_read_enable; - STAT(14) <= rx_fifo_write_enable; - STAT(15) <= rx_clock_detect; - STAT(23 downto 16) <= tx_data; - STAT(24) <= tx_datavalid; - STAT(31 downto 25) <= (others => '0'); - - - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_med_8_SDR_sync.vhd b/oldfiles/trb_net16_med_8_SDR_sync.vhd deleted file mode 100644 index 08976e7..0000000 --- a/oldfiles/trb_net16_med_8_SDR_sync.vhd +++ /dev/null @@ -1,456 +0,0 @@ ---media interface with 16 data lines, single data rate and oversampling of RX input ---oversampling running at 250 MHz - - - -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net16_med_8_SDR_sync is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - - -- Media direction port - TX_DATA_OUT : out std_logic_vector (15 downto 0); - TX_CTRL_OUT : out std_logic_vector (3 downto 0); - RX_DATA_IN : in std_logic_vector (15 downto 0); - RX_CTRL_IN : in std_logic_vector (3 downto 0); - - -- Status and control port - STAT_OP: out std_logic_vector (15 downto 0); - CTRL_OP: in std_logic_vector (15 downto 0); - - STAT: out std_logic_vector (31 downto 0); - CTRL: in std_logic_vector (31 downto 0) - ); -end entity; - -architecture trb_net16_med_8_SDR_sync_arch of trb_net16_med_8_SDR_sync is - - component trb_net_fifo_16bit_bram_dualport is - generic( - USE_STATUS_FLAGS : integer := c_YES - ); - port ( - read_clock_in: IN std_logic; - write_clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0); - valid_read_out: OUT std_logic; - almost_empty_out:OUT std_logic; - almost_full_out :OUT std_logic - ); - end component; - - component dualdatarate_flipflop is - --1 clock, no CE, PRE for Lattice SCM - generic( - WIDTH : integer := 1 - ); - port( - C0 : in std_logic; - C1 : in std_logic; - CE : in std_logic; - CLR : in std_logic; - D0 : in std_logic_vector(WIDTH-1 downto 0); - D1 : in std_logic_vector(WIDTH-1 downto 0); - PRE : in std_logic; - Q : out std_logic_vector(WIDTH-1 downto 0) - ); - end component; - - signal RECV_CLK, recv_clk_locked : std_logic; - signal reg_RX_CLK, buf_RX_CLK, last_RX_CLK : std_logic; - signal reg_RX_CTRL, buf_RX_CTRL : std_logic_vector(3 downto 0); - signal reg_RX_DATA, buf_RX_DATA : std_logic_vector(15 downto 0); - - signal rx_datavalid : std_logic; - signal rx_first_packet : std_logic; - signal rx_reset : std_logic; - signal rx_parity : std_logic; - signal rx_parity_match : std_logic; - - signal rx_fifo_read_enable : std_logic; - signal rx_fifo_write_enable, next_rx_fifo_write_enable: std_logic; - signal rx_fifo_data_in, next_rx_fifo_data_in : std_logic_vector(17 downto 0); - signal rx_fifo_data_out : std_logic_vector(17 downto 0); - signal rx_fifo_full : std_logic; - signal rx_fifo_empty : std_logic; - signal rx_fifostatus_out : std_logic_vector(3 downto 0); - signal rx_valid_read_out : std_logic; - signal rx_almost_empty_out : std_logic; - signal rx_almost_full_out : std_logic; - - - signal buf_INT_DATAREADY_OUT : std_logic; - - signal rx_packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal wait_for_startup : std_logic; - signal wait_for_startup_slow : std_logic; - signal rx_CLK_counter : std_logic_vector(4 downto 0); - signal rx_clock_detect : std_logic; - - signal med_reset : std_logic; - - signal tx_datavalid, tx_first_packet, tx_reset, tx_parity : std_logic; - signal buf_INT_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal buf_INT_READ_OUT : std_logic; - signal tx_clock_enable : std_logic; - signal next_tx_reset : std_logic; - signal buf_tx_reset : std_logic; - signal buf_tx_clk : std_logic; - signal recv_clk_real_locked : std_logic; - signal locked_counter : std_logic_vector(19 downto 0); - - signal led_counter : std_logic_vector(18 downto 0); - signal send_resync_counter : std_logic_vector(11 downto 0); - signal send_resync : std_logic; - signal rx_led, tx_led, link_led : std_logic; - signal med_error : std_logic_vector(2 downto 0); - signal trbnet_reset : std_logic; -begin - - ---Transmitter (full speed only) -------------------------- - INT_READ_OUT <= buf_INT_READ_OUT; - buf_INT_READ_OUT <= not wait_for_startup_slow and not buf_tx_reset; - - TX_DATA_OUT <= buf_INT_DATA_IN; - TX_CTRL_OUT(0) <= tx_datavalid; - TX_CTRL_OUT(1) <= tx_first_packet; - TX_CTRL_OUT(2) <= tx_reset; - TX_CTRL_OUT(3) <= tx_parity; - - tx_clock_enable <= not RESET; - - next_tx_reset <= CTRL_OP(15) or (recv_clk_real_locked and wait_for_startup_slow); - - - process(CLK) - begin - if rising_edge(CLK) then - TX_CLK_OUT <= buf_tx_clk; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - tx_datavalid <= '0'; - tx_reset <= '1'; - buf_tx_reset <= '1'; - buf_INT_DATA_IN <= (others => '0'); - tx_first_packet <= '0'; - tx_parity <= '0'; - buf_tx_clk <= '0'; - else - buf_INT_DATA_IN <= INT_DATA_IN; - tx_datavalid <= INT_DATAREADY_IN and buf_INT_READ_OUT; - if INT_PACKET_NUM_IN = c_H0 then - tx_first_packet <= '1'; - else - tx_first_packet <= '0'; - end if; - tx_reset <= buf_tx_reset; - buf_tx_reset <= next_tx_reset; - tx_parity <= xor_all(INT_DATA_IN); - buf_tx_clk <= not buf_tx_clk; - end if; - end if; - end process; - - - ---Receiver -------------------------- - RECV_CLOCK_GEN : trb_net_clock_generator - generic map( - FREQUENCY_IN => 100.0, - FREQUENCY_OUT => 200.0, - CLOCK_MULT => 2, - CLOCK_DIV => 1, - CLKIN_DIVIDE_BY_2 => false, - CLKIN_PERIOD => 10.0 - ) - port map( - RESET => RESET, - CLK_IN => CLK, - CLK_OUT => RECV_CLK, - LOCKED => recv_clk_locked - ); - -process(CLK) - begin - if rising_edge(CLK) then - if recv_clk_locked = '0' then - locked_counter <= (others => '0'); - recv_clk_real_locked <= '0'; - else - if locked_counter /= x"0000F" then - locked_counter <= locked_counter + 1; - else - recv_clk_real_locked <= '1'; - end if; - end if; - end if; - end process; - - RX_INPUT_REG : process(RECV_CLK) - begin - if rising_edge(RECV_CLK) then - reg_RX_CLK <= RX_CLK_IN; - reg_RX_CTRL <= RX_CTRL_IN; - reg_RX_DATA <= RX_DATA_IN; - end if; - end process; - - RX_REG : process(RECV_CLK, recv_clk_real_locked) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' then - buf_RX_CTRL <= (others => '0'); - buf_RX_CLK <= '0'; - last_RX_CLK <= '0'; - buf_RX_DATA <= (others => '0'); - else - buf_RX_CLK <= reg_RX_CLK; - buf_RX_DATA <= reg_RX_DATA; - buf_RX_CTRL <= reg_RX_CTRL; - last_RX_CLK <= buf_RX_CLK; - end if; - end if; - end process; - - rx_datavalid <= buf_RX_CTRL(0); - rx_first_packet <= buf_RX_CTRL(1); - rx_reset <= buf_RX_CTRL(2); - rx_parity <= buf_RX_CTRL(3); - - rx_parity_match <= '1' when rx_parity = xor_all(buf_RX_DATA) else '0'; - next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid; - next_rx_fifo_data_in <= rx_first_packet & rx_parity_match & buf_RX_DATA; - - reg_fifo_in : process(RECV_CLK) - begin - if rising_edge(RECV_CLK) then - rx_fifo_write_enable <= next_rx_fifo_write_enable; - rx_fifo_data_in <= next_rx_fifo_data_in; - end if; - end process; - - RX_FIFO : trb_net_fifo_16bit_bram_dualport - port map( - read_clock_in => CLK, - write_clock_in => RECV_CLK, - read_enable_in => rx_fifo_read_enable, - write_enable_in => rx_fifo_write_enable, - fifo_gsr_in => med_reset, - write_data_in => rx_fifo_data_in, - read_data_out => rx_fifo_data_out, - full_out => rx_fifo_full, - empty_out => rx_fifo_empty, - fifostatus_out => rx_fifostatus_out, - valid_read_out => rx_valid_read_out, - almost_empty_out => rx_almost_empty_out, - almost_full_out => rx_almost_full_out - ); - - rx_fifo_read_enable <= INT_READ_IN; - - INT_DATA_OUT <= rx_fifo_data_out(15 downto 0); - INT_PACKET_NUM_OUT <= rx_packet_counter; - INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - - packet_counter_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - rx_packet_counter <= "100"; - elsif buf_INT_DATAREADY_OUT = '1' then - if rx_packet_counter = c_max_word_number then - rx_packet_counter <= (others => '0'); - else - rx_packet_counter <= rx_packet_counter + 1; - end if; - end if; - end if; - end process; - - - rx_dataready_p : process(CLK) - begin - if rising_edge(CLK) then - if med_reset = '1' then - buf_INT_DATAREADY_OUT <= '0'; - else - buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty; - end if; - end if; - end process; - - ---monitor link -------------------------- - process(CLK) - begin - if rising_edge(CLK) then - wait_for_startup_slow <= wait_for_startup; - end if; - end process; - - process(RECV_CLK, recv_clk_real_locked,med_reset) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then - wait_for_startup <= '1'; - elsif rx_reset = '1' and recv_clk_locked = '1' then - wait_for_startup <= '0'; - end if; - end if; - end process; - - - ERROR_OUT_gen : process(CLK) - begin - if rising_edge(CLK) then - if recv_clk_real_locked = '0' or rx_clock_detect = '0' then - med_error <= ERROR_NC; - elsif (buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(16) = '0') then --Parity error - med_error <= ERROR_ENCOD; - elsif (rx_packet_counter /= "100" and buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(17) = '1') then - med_error <= ERROR_FATAL; --Counter error - else - med_error <= ERROR_OK; - end if; - end if; - end process; - - - rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked) - begin - if rising_edge(RECV_CLK) then - if recv_clk_real_locked = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '0'; - elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '1'; - elsif rx_CLK_counter /= 31 then - rx_CLK_counter <= rx_CLK_counter + 1; - elsif rx_CLK_counter = 31 then - rx_clock_detect <= '0'; - end if; - end if; - end process; - - ---STAT & CTRL Ports -------------------------- - ---LED - link_led <= rx_clock_detect and not wait_for_startup_slow; - - process(CLK) - begin - if rising_edge(CLK) then - if led_counter(18) = '1' then - led_counter <= (others => '0'); - else - led_counter <= led_counter + 1; - end if; - if rx_fifo_empty = '0' then - rx_led <= '1'; - elsif led_counter(18) = '1' then - rx_led <= '0'; - end if; - if tx_datavalid = '1' then - tx_led <= '1'; - elsif led_counter(18) = '1' then - tx_led <= '0'; - end if; - end if; - end process; - - - STAT_OP(2 downto 0) <= med_error; - STAT_OP(8 downto 3) <= (others => '0'); - STAT_OP(9) <= link_led; - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= '0'; - STAT_OP(13) <= trbnet_reset; - STAT_OP(14) <= rx_clock_detect; - STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0'; - - STAT(12) <= rx_parity_match; - STAT(11) <= RECV_CLK; - STAT(10) <= recv_clk_real_locked; - STAT(9) <= rx_reset; - STAT(8) <= buf_RX_CLK xor last_RX_CLK; - STAT(7) <= recv_clk_locked; - STAT(6) <= wait_for_startup; - STAT(5) <= rx_first_packet; - STAT(4) <= buf_tx_clk; --not or_all(INT_PACKET_NUM_IN); --tx_first_packet; - STAT(3) <= rx_datavalid; - STAT(2) <= next_tx_reset; - STAT(1) <= buf_RX_CLK; - - STAT(13) <= or_all(rx_fifostatus_out); - STAT(14) <= rx_valid_read_out; - STAT(15) <= rx_almost_empty_out; - STAT(16) <= rx_almost_full_out; - STAT(31 downto 17) <= (others => '0'); - - med_reset <= RESET or send_resync; - trbnet_reset <= rx_reset or not recv_clk_real_locked; - - ---detect resync - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - send_resync <= '0'; - send_resync_counter <= (others => '0'); - else - if not (send_resync_counter = 0) then - send_resync_counter <= send_resync_counter + 1; - end if; - if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then - send_resync <= '1'; - send_resync_counter <= send_resync_counter + 1; - end if; - if send_resync_counter = x"00F" then - send_resync <= '0'; - end if; - end if; - end if; - end process; - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net16_med_tlk.vhd b/oldfiles/trb_net16_med_tlk.vhd deleted file mode 100644 index 414e14f..0000000 --- a/oldfiles/trb_net16_med_tlk.vhd +++ /dev/null @@ -1,573 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -LIBRARY unisim; -USE UNISIM.VComponents.all; -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; - - -entity trb_net16_med_tlk is - port ( - RESET : in std_logic; - CLK : in std_logic; - TLK_CLK : in std_logic; - TLK_ENABLE : out std_logic; - TLK_LCKREFN : out std_logic; - TLK_LOOPEN : out std_logic; - TLK_PRBSEN : out std_logic; - TLK_RXD : in std_logic_vector(15 downto 0); - TLK_RX_CLK : in std_logic; - TLK_RX_DV : in std_logic; - TLK_RX_ER : in std_logic; - TLK_TXD : out std_logic_vector(15 downto 0); - TLK_TX_EN : out std_logic; - TLK_TX_ER : out std_logic; - SFP_LOS : in std_logic; - SFP_TX_DIS : out std_logic; - MED_DATAREADY_IN : in std_logic; - MED_READ_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - STAT : out std_logic_vector (63 downto 0); - STAT_MONITOR : out std_logic_vector ( 100 downto 0); - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0) - --connect STAT(0) to LED - ); -end trb_net16_med_tlk; - -architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is - - signal fifo_din_a : std_logic_vector(17 downto 0); - signal fifo_dout_a : std_logic_vector(17 downto 0); - signal fifo_wr_en_a : std_logic; - signal fifo_rd_en_a : std_logic; - signal fifo_empty_a : std_logic; - signal fifo_full_a : std_logic; - signal fifo_din_m : std_logic_vector(17 downto 0); - signal fifo_dout_m : std_logic_vector(17 downto 0); - signal fifo_rd_en_m : std_logic; - signal fifo_wr_en_m : std_logic; - signal fifo_empty_m : std_logic; - signal fifo_full_m : std_logic; - signal fifo_valid_read_m, fifo_valid_read_a : std_logic; - signal fifo_almost_full_m, fifo_almost_full_a : std_logic; - signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic; - - - signal fifo_reset : std_logic; - signal fifo_status_a : std_logic_vector(3 downto 0); - signal fifo_status_m : std_logic_vector(3 downto 0); - signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal buf_MED_READ_OUT : std_logic; - signal buf_MED_DATAREADY_OUT : std_logic; - signal rx_allow : std_logic; - signal tx_allow : std_logic; - signal internal_reset : std_logic; - - - signal reg_RXD : std_logic_vector(15 downto 0); - signal reg_RX_DV : std_logic; - signal reg_RX_ER : std_logic; - signal reg_TXD : std_logic_vector(15 downto 0); - signal reg_TX_EN : std_logic; - signal reg_TX_ER : std_logic; - - signal TLK_CLK_neg : std_logic; - signal CLK_FB_Out, FB_CLK : std_logic; - - type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_TX_ALLOW, WORKING); - signal current_state, next_state : tlk_state_t; - signal next_tx_allow, next_rx_allow : std_logic:='1'; - signal counter, next_counter : std_logic_vector(28 downto 0); - signal next_internal_reset : std_logic; - signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0); - signal state_bits : std_logic_vector(2 downto 0); - signal counter_reset : std_logic; - - signal reg_SFP_LOS : std_logic; - - signal send_reset : std_logic; - signal make_reset : std_logic; - signal send_reset_counter : std_logic_vector(6 downto 0); - signal send_reset_q : std_logic; - signal make_reset_q : std_logic; - signal sending_reset: std_logic; - - signal buf_RESET_TRBNET_OUT : std_logic; - - signal led_counter : std_logic_vector(18 downto 0); - signal rx_led, tx_led, link_led : std_logic; - - signal comb_fifo_wr_en_a : std_logic; - signal comb_fifo_din_a : std_logic_vector(17 downto 0); - -begin - - TLK_ENABLE <= not RESET; - TLK_LCKREFN <= '1'; - TLK_PRBSEN <= '0'; - TLK_LOOPEN <= '0'; - SFP_TX_DIS <= RESET; - - - - ---------------------------------------------- ---Receiver FIFO ---------------------------------------------- - - FIFO_OPT_TO_MED: trb_net_fifo_16bit_bram_dualport - generic map( - USE_STATUS_FLAGS => c_NO - ) - port map( - read_clock_in => CLK, - write_clock_in => TLK_RX_CLK, - read_enable_in => fifo_rd_en_a, - write_enable_in => fifo_wr_en_a, - fifo_gsr_in => fifo_reset, - write_data_in => fifo_din_a, - read_data_out => fifo_dout_a, - full_out => fifo_full_a, - empty_out => fifo_empty_a, - fifostatus_out => fifo_status_a, - valid_read_out => fifo_valid_read_a, - almost_empty_out=> fifo_almost_empty_a, - almost_full_out => fifo_almost_full_a - ); - - fifo_rd_en_a <= rx_allow; - fifo_reset <= internal_reset; - - - buf_MED_READ_OUT <= tx_allow; - buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_dout_a(17) and rx_allow; - - - PROC_PACKET_COUNTER : process(CLK) - begin - if rising_edge(CLK) then - if internal_reset = '1' or buf_RESET_TRBNET_OUT = '1' then - buf_MED_PACKET_NUM_OUT <= c_H0; - elsif buf_MED_DATAREADY_OUT = '1' then - if buf_MED_PACKET_NUM_OUT = c_max_word_number then - buf_MED_PACKET_NUM_OUT <= (others => '0'); - else - buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; - end if; - end if; - end if; - end process; - - REG_MED_OUTPUTS : process(CLK) - begin - if rising_edge(CLK) then - MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; - MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - MED_DATA_OUT <= fifo_dout_a(15 downto 0); - MED_READ_OUT <= buf_MED_READ_OUT; - end if; - end process; - - - - REG_RX_FIFO_INPUTS : process(TLK_RX_CLK) - begin - if rising_edge(TLK_RX_CLK) then - fifo_wr_en_a <= (reg_RX_DV and not reg_RX_ER) and rx_allow; - fifo_din_a <= reg_RX_ER & reg_RX_DV & reg_RXD; - end if; - end process; - - SYNC_TLK_RX_INPUT : process(TLK_RX_CLK) - begin - if rising_edge(TLK_RX_CLK) then - reg_RXD <= TLK_RXD; - reg_RX_DV <= TLK_RX_DV; - reg_RX_ER <= TLK_RX_ER; - end if; - end process; - - - ---------------------------------------------- ---Detect Reset (Error Propagation) ---------------------------------------------- - - - process(TLK_RX_CLK) - begin - if rising_edge(TLK_RX_CLK) then - if RESET = '1' then - send_reset_counter <= (others => '0'); - send_reset <= '0'; - make_reset <= '0'; - else - if reg_RX_DV = '1' and reg_RX_ER = '1' and send_reset_counter(5) = '0' then - send_reset_counter <= send_reset_counter + 1; - elsif reg_RX_ER = '0' then - send_reset_counter <= (others => '0'); - end if; - if send_reset = '1' and reg_RX_ER = '0' then --do reset - make_reset <= '1'; - send_reset <= '0'; - elsif send_reset_counter(5) = '1' and reg_RX_ER = '1' then --send reset - send_reset <= '1'; - make_reset <= '0'; - else - send_reset <= '0'; - make_reset <= '0'; - end if; - end if; - end if; - end process; - - SYNC_SEND_RESET : signal_sync - generic map( - WIDTH => 2, - DEPTH => 2 - ) - port map( - RESET => RESET, - CLK0 => CLK, - CLK1 => CLK, - D_IN(0) => send_reset, - D_IN(1) => make_reset, - D_OUT(0) => send_reset_q, - D_OUT(1) => make_reset_q - ); - - SYNC_SENDING_RESET : signal_sync - generic map( - WIDTH => 1, - DEPTH => 2 - ) - port map( - RESET => RESET, - CLK0 => TLK_CLK_neg, - CLK1 => TLK_CLK_neg, - D_IN(0) => CTRL_OP(15), - D_OUT(0) => sending_reset - ); - - - SYNC_SFP_LOS : signal_sync - generic map( - WIDTH => 1, - DEPTH => 2 - ) - port map( - RESET => RESET, - CLK0 => CLK, - CLK1 => CLK, - D_IN(0) => SFP_LOS, - D_OUT(0) => reg_SFP_LOS - ); - ---------------------------------------------- ---A DCM - not really used ---------------------------------------------- - -U_DCM_Transmitter: DCM --no_sim-- - generic map( --no_sim-- - CLKIN_PERIOD => 10.00, -- 30.30ns--no_sim-- - STARTUP_WAIT => FALSE,--no_sim-- - PHASE_SHIFT => 0,--no_sim-- - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",--no_sim-- - CLKOUT_PHASE_SHIFT => "FIXED"--no_sim-- - )--no_sim-- - port map (--no_sim-- - CLKIN => TLK_CLK,--no_sim-- - CLKFB => FB_CLK,--no_sim-- - DSSEN => '0',--no_sim-- - PSINCDEC => '0',--no_sim-- - PSEN => '0',--no_sim-- - PSCLK => '0',--no_sim-- - RST => RESET,--no_sim-- - CLK0 => CLK_FB_Out, -- for feedback--no_sim-- - CLK90=> open,--no_sim-- - LOCKED => open--no_sim-- - );--no_sim-- --- -U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg);--no_sim-- -U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim-- ---sim--TLK_CLK_neg <= not TLK_CLK; - - - ---------------------------------------------- ---TX FIFO ---------------------------------------------- - - FIFO_MED_TO_OPT: trb_net_fifo_16bit_bram_dualport - generic map( - USE_STATUS_FLAGS => c_NO - ) - port map( - read_clock_in => TLK_CLK_neg, - write_clock_in => CLK, - read_enable_in => fifo_rd_en_m, - write_enable_in => fifo_wr_en_m, - fifo_gsr_in => fifo_reset, - write_data_in => fifo_din_m, - read_data_out => fifo_dout_m, - valid_read_out => fifo_valid_read_m, - full_out => fifo_full_m, - empty_out => fifo_empty_m, - fifostatus_out => fifo_status_m, - almost_empty_out=> fifo_almost_empty_m, - almost_full_out => fifo_almost_full_m - ); - - - - REG_TLK_TX_OUT : process(TLK_CLK_neg) - begin - if rising_edge(TLK_CLK_neg) then - TLK_TX_EN <= reg_TX_EN; - TLK_TX_ER <= reg_TX_ER; - TLK_TXD <= reg_TXD; - end if; - end process; - - REG_TLK_TX_buffers : process(TLK_CLK_neg) - begin - if rising_edge(TLK_CLK_neg) then - reg_TXD <= fifo_dout_m(15 downto 0); - reg_TX_ER <= sending_reset; - reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or sending_reset; - end if; - end process; - - PROC_TX_FIFO_INPUT : process(CLK) - begin - if rising_edge(CLK) then - fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT); - fifo_din_m <= MED_PACKET_NUM_IN(2) & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN; - end if; - end process; - - fifo_rd_en_m <= tx_allow; - - - - - ---------------------------------------------- ---Link State Machine ---------------------------------------------- - - medium_states : process(current_state, tx_allow, rx_allow, internal_reset, MED_READ_IN, - reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter, make_reset_q) - begin - next_state <= current_state; - next_tx_allow <= tx_allow; - next_rx_allow <= rx_allow; - next_internal_reset <= internal_reset; - next_counter <= counter + 1; - counter_reset <= reg_RX_ER and not reg_RX_DV; - next_MED_ERROR_OUT <= buf_MED_ERROR_OUT; - - case current_state is - when RESETTING => - next_MED_ERROR_OUT <= ERROR_NC; - next_internal_reset <= '1'; - next_rx_allow <= '0'; - next_tx_allow <= '0'; - counter_reset <= '0'; - if counter(16) = '1' then - counter_reset <= '1'; - next_state <= WAIT_FOR_RX_LOCK; - next_internal_reset <= '0'; - end if; - when WAIT_FOR_RX_LOCK => - next_internal_reset <= '0'; - if counter(28) = '1' then - counter_reset <= '1'; - next_rx_allow <= '1'; - next_state <= WAIT_FOR_TX_ALLOW; - end if; - when WAIT_FOR_TX_ALLOW => - next_MED_ERROR_OUT <= ERROR_WAIT; - next_internal_reset <= '0'; - if counter(28) = '1' then - next_tx_allow <= '1'; - next_state <= WORKING; - end if; - when WORKING => - next_MED_ERROR_OUT <= ERROR_OK; - next_tx_allow <= '1'; - next_rx_allow <= '1'; - next_internal_reset <= '0'; - end case; - if reg_RX_ER = '1' and reg_RX_DV = '0' and internal_reset = '0' then - next_rx_allow <= '0'; - next_tx_allow <= '0'; - next_state <= WAIT_FOR_RX_LOCK; - next_MED_ERROR_OUT <= ERROR_WAIT; - end if; - if MED_READ_IN = '0' then - next_MED_ERROR_OUT <= ERROR_NC; - end if; - if make_reset_q = '1' or reg_SFP_LOS = '1' then - next_state <= RESETTING; - next_MED_ERROR_OUT <= ERROR_NC; - counter_reset <= '1'; - end if; - end process; - - process(current_state) - begin - case current_state is - when RESETTING => state_bits <= "000"; - when WAIT_FOR_RX_LOCK => state_bits <= "001"; - when WAIT_FOR_TX_ALLOW => state_bits <= "011"; - when WORKING => state_bits <= "100"; - when others => state_bits <= "111"; - end case; - end process; - - - - states_reg : process(CLK) - begin - if rising_edge(CLK) then - tx_allow <= next_tx_allow; - rx_allow <= next_rx_allow; - end if; - end process; - - states_reg_counter : process(CLK) - begin - if rising_edge(CLK) then - if counter_reset = '1' then - counter <= (others => '0'); - else - counter <= next_counter; - end if; - end if; - end process; - - states_reg_2 : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_state <= RESETTING;--no_sim-- ---sim-- current_state <= WORKING; - internal_reset <= '1'; - buf_MED_ERROR_OUT <= ERROR_NC; - else - current_state <= next_state; - internal_reset <= next_internal_reset; - buf_MED_ERROR_OUT <= next_MED_ERROR_OUT; - end if; - end if; - end process; - - - - - ---------------------------------------------- ---STAT_OP & LED ---------------------------------------------- - process(CLK) - begin - if rising_edge(CLK) then - if led_counter(18) = '1' then - led_counter <= (others => '0'); - else - led_counter <= led_counter + 1; - end if; - if buf_med_dataready_out = '1' then - rx_led <= '1'; - elsif led_counter(18) = '1' then - rx_led <= '0'; - end if; - - if MED_DATAREADY_IN = '1' then - tx_led <= '1'; - elsif led_counter(18) = '1' then - tx_led <= '0'; - end if; - - end if; - end process; - - link_led <= (counter(24) or tx_allow) and not reg_sfp_los; - - stat_op(2 downto 0) <= buf_MED_ERROR_OUT; - stat_op(8 downto 3) <= (others => '0'); -- unused - stat_op(9) <= link_led; - stat_op(10) <= rx_led; --rx led - stat_op(11) <= tx_led; --tx led - stat_op(12) <= '0'; -- unused - stat_op(13) <= make_reset_q; - stat_op(14) <= reg_SFP_LOS or make_reset_q; -- reset out - stat_op(15) <= send_reset_q; -- protocol error - ---------------------------------------------- ---Debugging ---------------------------------------------- - - - STAT(0) <= counter(24) or tx_allow; - STAT(1) <= rx_allow; - STAT(2) <= tx_allow; - STAT(3) <= fifo_wr_en_a; - STAT(4) <= fifo_rd_en_a; - STAT(5) <= fifo_empty_a; - STAT(6) <= fifo_rd_en_m; - STAT(7) <= fifo_empty_m; - STAT(8) <= fifo_full_a; - STAT(9) <= fifo_full_m; - STAT(10)<= fifo_dout_m(14); - STAT(11)<= fifo_dout_a(14); - STAT(12)<= fifo_din_a(14); --- STAT(11)<= last_fifo_rd_en_a; - STAT(13) <= internal_reset; - STAT(14) <= reg_RX_DV; - STAT(15) <= reg_RX_ER; - STAT(31 downto 16) <= reg_RXD; - STAT(32) <= fifo_valid_read_m; - STAT(33) <= fifo_valid_read_a; - STAT(36 downto 34) <= state_bits; - STAT(40 downto 37) <= fifo_status_a; - STAT(44 downto 41) <= fifo_status_m; - STAT(48 downto 45) <= fifo_dout_m(3 downto 0); - STAT(50 downto 49) <= fifo_dout_m(17 downto 16); - STAT(54 downto 51) <= fifo_din_a(3 downto 0); - STAT(56 downto 55) <= fifo_din_a(17 downto 16); - STAT(57) <= make_reset; - STAT(58) <= send_reset; - STAT(59) <= TLK_CLK_neg; - STAT(60) <= fifo_wr_en_m; - STAT(63 downto 61) <= send_reset_counter(2 downto 0); - --STAT(63 downto 57) <= (others => '0'); - - STAT_MONITOR(17 downto 0) <= fifo_din_a; - STAT_MONITOR(18) <= fifo_almost_full_m; - STAT_MONITOR(19) <= fifo_almost_full_a; - STAT_MONITOR(20) <= fifo_almost_empty_m; - STAT_MONITOR(21) <= fifo_almost_empty_a; - STAT_MONITOR(37 downto 22) <= CTRL_OP; - STAT_MONITOR(45 downto 38) <= (others => '0'); - STAT_MONITOR(46) <= reg_TX_ER; - STAT_MONITOR(47) <= reg_TX_EN; - STAT_MONITOR(63 downto 48) <= reg_TXD; - STAT_MONITOR(81 downto 64) <= fifo_din_a; -- RX_ER & RX_DV & RX_DATA - STAT_MONITOR(88 downto 82) <= send_reset_counter; - STAT_MONITOR(100 downto 89) <= (others => '0'); - - - - -end architecture; diff --git a/oldfiles/trb_net16_rx_packets.vhd b/oldfiles/trb_net16_rx_packets.vhd deleted file mode 100755 index a585c00..0000000 --- a/oldfiles/trb_net16_rx_packets.vhd +++ /dev/null @@ -1,440 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; ---use work.trb_net_components.all; - -entity trb_net16_rx_packets is -port( - -- Resets - RESET_IN : in std_logic; - QUAD_RST_IN : in std_logic; - -- data stream from SerDes - CLK_IN : in std_logic; -- SerDes RX clock - RX_ALLOW_IN : in std_logic; - RX_DATA_IN : in std_logic_vector(7 downto 0); - RX_K_IN : in std_logic; - -- media interface - SYSCLK_IN : in std_logic; -- 100MHz master clock - MED_DATA_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - -- reset handling - SEND_RESET_WORDS_OUT : out std_logic; - MAKE_TRBNET_RESET_OUT : out std_logic; - -- Status signals - PACKET_TIMEOUT_OUT : out std_logic; - -- Debug signals - BSM_OUT : out std_logic_vector(3 downto 0); - DBG_OUT : out std_logic_vector(15 downto 0) -); -end entity trb_net16_rx_packets; - - -architecture behavioral of trb_net16_rx_packets is - --- components -component trb_net_fifo_8bit_16bit_bram_dualport is -port( - READ_CLOCK_IN : in std_logic; - WRITE_CLOCK_IN : in std_logic; - READ_ENABLE_IN : in std_logic; - WRITE_ENABLE_IN : in std_logic; - FIFO_GSR_IN : in std_logic; - WRITE_DATA_IN : in std_logic_vector(7 downto 0); - READ_DATA_OUT : out std_logic_vector(15 downto 0); - FULL_OUT : out std_logic; - EMPTY_OUT : out std_logic; - WCNT_OUT : out std_logic_vector(9 downto 0); - RCNT_OUT : out std_logic_vector(8 downto 0) -); -end component trb_net_fifo_8bit_16bit_bram_dualport; - --- State description: --- --- IDLE: wait for any data to be written into the FIFO --- RD1 : first word prefetch --- RD2 : first word output reg, second word prefetch, wait state for full packet in FIFO --- RDI : generates initial dataready_out, wait state for handshake of first data word --- RD3 : second word output reg, third word prefetch, wait state for handshake of second data word --- RD4 : third word output reg, fourth word prefetch, wait state for handshake of third data word --- RD5 : fourth word output reg, fifth word prefetch, wait state for handshake of forth data word --- => decision: continous data stream or stalling as FIFO runs empty! --- RDO : fifth word output reg, wait state for handshake of fifth data word, can also resume transmission --- if new data is available in FIFO --- RDW : fifth word output reg, first word prefetch, wait state for handshake of fifth data word, --- continue data stream or stall if for complete packet - --- state declarations -type STATES is (IDLE, RD1, RD2, RDI, RD3, RD4, RD5, RDO, RDW, TOC, CLEAN); -signal CURRENT_STATE, NEXT_STATE: STATES; - --- normal signals -signal bsm_x : std_logic_vector(3 downto 0); -signal bsm : std_logic_vector(3 downto 0); -signal update_x : std_logic; -signal med_dataready_x : std_logic; -signal med_dataready : std_logic; -signal med_data : std_logic_vector(15 downto 0); - -signal buf_rx_data : std_logic_vector(7 downto 0); -signal buf_rx_k : std_logic; - -signal fifo_wr_en : std_logic; -signal fifo_rd_en_x : std_logic; -signal fifo_wr_data : std_logic_vector(7 downto 0); -signal fifo_rd_data : std_logic_vector(15 downto 0); -signal fifo_reset : std_logic; -signal fifo_rcnt_stdlv : std_logic_vector(8 downto 0); -signal fifo_rcnt : unsigned(8 downto 0); -signal fifo_rst_x : std_logic; -signal fifo_rst : std_logic; - -signal rx_counter : unsigned(2 downto 0); - -signal is_idle_word : std_logic; -signal rx_starting : std_logic; -signal send_reset_words : std_logic; -signal make_trbnet_reset : std_logic; -signal reset_word_cnt : unsigned(4 downto 0); - -signal timeout_ctr : unsigned(9 downto 0); -signal rst_toc_x : std_logic; -signal rst_toc : std_logic; -signal ce_toc_x : std_logic; -signal ce_toc : std_logic; -signal toc_done_x : std_logic; -signal toc_done : std_logic; - -signal debug : std_logic_vector(15 downto 0); - -begin - ----------------------------------------------------------------------- --- FIFO write process ----------------------------------------------------------------------- -THE_WRITE_RX_FIFO_PROC: process( CLK_IN ) -begin - if( rising_edge(CLK_IN) ) then - buf_rx_data <= RX_DATA_IN; - buf_rx_k <= RX_K_IN; - if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then - fifo_wr_en <= '0'; - is_idle_word <= '1'; - rx_starting <= '1'; - else - fifo_wr_data <= buf_rx_data; - if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then - fifo_wr_en <= '1'; - else - fifo_wr_en <= '0'; - end if; - if ( buf_rx_k = '1' ) then - is_idle_word <= '1'; - rx_starting <= '0'; - elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then - is_idle_word <= '0'; - end if; - end if; - end if; -end process THE_WRITE_RX_FIFO_PROC; - ----------------------------------------------------------------------- --- TRBnet reset handling ----------------------------------------------------------------------- -THE_CNT_RESET_PROC: process( CLK_IN ) -begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - reset_word_cnt <= (others => '0'); - else - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - if( (buf_rx_data = x"FE") and (buf_rx_k = '1') ) then - if( reset_word_cnt(4) = '0' ) then - reset_word_cnt <= reset_word_cnt + 1; - else - send_reset_words <= '1'; - end if; - else - reset_word_cnt <= (others => '0'); - make_trbnet_reset <= reset_word_cnt(4); - end if; - end if; - end if; -end process; - ----------------------------------------------------------------------- --- the RX FIFO itself ----------------------------------------------------------------------- -THE_RX_FIFO: trb_net_fifo_8bit_16bit_bram_dualport -port map( - READ_CLOCK_IN => SYSCLK_IN, - WRITE_CLOCK_IN => CLK_IN, - READ_ENABLE_IN => fifo_rd_en_x, - WRITE_ENABLE_IN => fifo_wr_en, - FIFO_GSR_IN => fifo_reset, - WRITE_DATA_IN => fifo_wr_data, - READ_DATA_OUT => fifo_rd_data, - FULL_OUT => open, - EMPTY_OUT => open, - WCNT_OUT => open, -- not needed - RCNT_OUT => fifo_rcnt_stdlv -); - -fifo_reset <= RESET_IN or QUAD_RST_IN or not RX_ALLOW_IN or fifo_rst; - -fifo_rcnt <= unsigned(fifo_rcnt_stdlv); - ----------------------------------------------------------------------- --- RX packet state machine ----------------------------------------------------------------------- --- state registers -STATE_MEM: process( SYSCLK_IN ) -begin - if( rising_edge(SYSCLK_IN) ) then - if( RESET_IN = '1' ) then - CURRENT_STATE <= IDLE; - med_dataready <= '0'; - ce_toc <= '0'; - rst_toc <= '0'; - fifo_rst <= '0'; - bsm <= (others => '0'); - else - CURRENT_STATE <= NEXT_STATE; - med_dataready <= med_dataready_x; - ce_toc <= ce_toc_x; - rst_toc <= rst_toc_x; - fifo_rst <= fifo_rst_x; - bsm <= bsm_x; - end if; - end if; -end process STATE_MEM; - --- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, fifo_rcnt, MED_READ_IN, med_dataready, toc_done ) -begin - NEXT_STATE <= IDLE; -- avoid latches - fifo_rd_en_x <= '0'; - med_dataready_x <= '0'; - update_x <= '0'; - ce_toc_x <= '0'; - rst_toc_x <= '0'; - fifo_rst_x <= '0'; - case CURRENT_STATE is - when IDLE => if( fifo_rcnt > 0 ) then - -- we have at least one data word in FIFO, so we prefetch it - NEXT_STATE <= RD1; - fifo_rd_en_x <= '1'; - ce_toc_x <= '1'; - else - NEXT_STATE <= IDLE; - end if; - when RD1 => if ( fifo_rcnt > 1 ) then -- was 0 - -- second data word is available in FIFO, so we prefetch it and - -- forward the first word to the output register - NEXT_STATE <= RD2; - fifo_rd_en_x <= '1'; - update_x <= '1'; - ce_toc_x <= '1'; - elsif( toc_done = '1' ) then - NEXT_STATE <= TOC; - rst_toc_x <= '1'; - fifo_rst_x <= '1'; - else - NEXT_STATE <= RD1; - ce_toc_x <= '1'; - end if; - when RD2 => if ( fifo_rcnt > 2 ) then - -- at least all three missing words in FIFO... so we go ahead and notify full packet availability - NEXT_STATE <= RDI; - med_dataready_x <= '1'; - rst_toc_x <= '1'; - elsif( toc_done = '1' ) then - NEXT_STATE <= TOC; - rst_toc_x <= '1'; - fifo_rst_x <= '1'; - else - NEXT_STATE <= RD2; - ce_toc_x <= '1'; - end if; - when RDI => med_dataready_x <= '1'; - if( MED_READ_IN = '1' ) then - -- first word of packet has been transfered, update output register and prefetch next data word - NEXT_STATE <= RD3; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RDI; - end if; - when RD3 => med_dataready_x <= '1'; - if( MED_READ_IN = '1' ) then - -- second word of packet has been transfered, update output register and prefetch next data word - NEXT_STATE <= RD4; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RD3; - end if; - when RD4 => med_dataready_x <= '1'; - -- third word of packet has been transfered, update output register and prefetch next data word - if( MED_READ_IN = '1' ) then - NEXT_STATE <= RD5; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RD4; - end if; - when RD5 => med_dataready_x <= '1'; - -- DANGER. This is the key state for decisions here. - -- There are many ways to do it the wrong way, depending on the FIFO fill level. - if ( (MED_READ_IN = '1') and (fifo_rcnt < 3) ) then -- was 2, changed due to RCNT latency - -- fourth word of packet has been transfered, and FIFO has not seen any new packet word. - -- so we update output register only, no prefetch - NEXT_STATE <= RDO; - update_x <= '1'; - elsif( (MED_READ_IN = '1') and (fifo_rcnt > 2) ) then -- was 1, changed due to RCNT latency - -- fourth word of packet DONE, new packet data already in the FIFO - -- so we can prefetch on data word already and update the output register - NEXT_STATE <= RDW; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RD5; - end if; - when RDO => if ( (MED_READ_IN = '1') and (fifo_rcnt = 0) ) then - -- last word of packet has been transfered, and no new data words to handle. - -- we keep the last transfered word in the output register and wait for new packets to arrive. - NEXT_STATE <= IDLE; - elsif( (MED_READ_IN = '1') and (fifo_rcnt > 0) ) then - -- last word of packet has been transfered, and a new packet data available. - -- so we enter the prefetch phase again. - NEXT_STATE <= RD1; - fifo_rd_en_x <= '1'; - else - NEXT_STATE <= RDO; - med_dataready_x <= '1'; - end if; - when RDW => if ( (MED_READ_IN = '1') and (fifo_rcnt > 3) ) then - -- last word of packet has been transfered, complete packet in FIFO, so we can go ahead. - NEXT_STATE <= RDI; - fifo_rd_en_x <= '1'; - update_x <= '1'; - med_dataready_x <= '1'; - elsif( (MED_READ_IN = '1') and (fifo_rcnt < 4 ) ) then - -- last word of packet has been transfered, but new packet not complete yet. - NEXT_STATE <= RD2; - fifo_rd_en_x <= '1'; - update_x <= '1'; - else - NEXT_STATE <= RDW; - med_dataready_x <= '1'; - end if; - when TOC => NEXT_STATE <= CLEAN; - fifo_rst_x <= '1'; - when CLEAN => NEXT_STATE <= IDLE; - - when others => NEXT_STATE <= IDLE; - end case; -end process STATE_TRANSFORM; - --- just for debugging -THE_DECODE_PROC: process( NEXT_STATE ) -begin - case NEXT_STATE is - when IDLE => bsm_x <= x"0"; - when RD1 => bsm_x <= x"1"; - when RD2 => bsm_x <= x"2"; - when RDI => bsm_x <= x"3"; - when RD3 => bsm_x <= x"4"; - when RD4 => bsm_x <= x"5"; - when RD5 => bsm_x <= x"6"; - when RDO => bsm_x <= x"7"; - when RDW => bsm_x <= x"8"; - when TOC => bsm_x <= x"9"; - when CLEAN => bsm_x <= x"a"; - when others => bsm_x <= x"f"; - end case; -end process THE_DECODE_PROC; - -THE_SYNC_PROC: process( SYSCLK_IN ) -begin - if( rising_edge(SYSCLK_IN) ) then - if( update_x = '1' ) then - med_data <= fifo_rd_data; - end if; - end if; -end process THE_SYNC_PROC; - ----------------------------------------------------------------------- --- RX packet counter ----------------------------------------------------------------------- -THE_RX_PACKETS_PROC: process( SYSCLK_IN ) -begin - if( rising_edge(SYSCLK_IN) ) then - if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then - rx_counter <= unsigned(c_H0); - else - if( (med_dataready = '1') and (MED_READ_IN = '1') ) then -- modified - if( rx_counter = unsigned(c_max_word_number) ) then - rx_counter <= (others => '0'); - else - rx_counter <= rx_counter + 1; - end if; - end if; - end if; - end if; -end process THE_RX_PACKETS_PROC; - ----------------------------------------------------------------------- --- Timeout counter ----------------------------------------------------------------------- -THE_TOC_PROC: process( SYSCLK_IN ) -begin - if( rising_edge(SYSCLK_IN) ) then - toc_done <= toc_done_x; - if ( (RESET_IN = '1') or (rst_toc = '1') ) then - timeout_ctr <= (others => '0'); - elsif( (ce_toc = '1') and (toc_done = '0') ) then - timeout_ctr <= timeout_ctr + 1; - end if; - end if; -end process THE_TOC_PROC; - -toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" ) else '0'; - ----------------------------------------------------------------------- --- Debug signals ----------------------------------------------------------------------- -debug(15 downto 13) <= (others => '0'); -debug(12 downto 4) <= fifo_rcnt_stdlv; -debug(3) <= toc_done; -debug(2) <= ce_toc; -debug(1) <= rst_toc; -debug(0) <= fifo_rst; - ---debug(15 downto 8) <= fifo_rcnt_stdlv(7 downto 0); ---debug(7 downto 2) <= (others => '0'); ---debug(1) <= update_x; ---debug(0) <= fifo_rd_en_x; - ----------------------------------------------------------------------- --- Output signals ----------------------------------------------------------------------- -SEND_RESET_WORDS_OUT <= send_reset_words; -MAKE_TRBNET_RESET_OUT <= make_trbnet_reset; -PACKET_TIMEOUT_OUT <= fifo_rst; - -MED_DATAREADY_OUT <= med_dataready; -MED_DATA_OUT <= med_data; -MED_PACKET_NUM_OUT <= std_logic_vector(rx_counter); - -BSM_OUT <= bsm; -DBG_OUT <= debug; - -end behavioral; \ No newline at end of file diff --git a/oldfiles/trb_net_18_to_16_converter.vhd b/oldfiles/trb_net_18_to_16_converter.vhd deleted file mode 100644 index 467251a..0000000 --- a/oldfiles/trb_net_18_to_16_converter.vhd +++ /dev/null @@ -1,299 +0,0 @@ - ------------------------------------ ---D18 data structure --- XXXXXXXX0+++++++ 00 --- 1+++++++2+++++++ 01 --- 3+++++++4+++++++ 10 --- 5+++++++6+++++++ 11 ------------------------------------- ---X unused, / error+parity, + data ------------------------------------- - - - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_18_to_16_converter is - generic ( VERSION : integer := 0); --Version of included sbufs - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - D18_DATAREADY_IN: in STD_LOGIC; - D18_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0); - D18_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - D18_READ_OUT: out STD_LOGIC; - - D16_DATAREADY_OUT: out STD_LOGIC; - D16_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - D16_READ_IN: in STD_LOGIC; - D16_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0); - - D18_DATAREADY_OUT: out STD_LOGIC; - D18_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0); - D18_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - D18_READ_IN: in STD_LOGIC; - - D16_DATAREADY_IN: in STD_LOGIC; - D16_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - D16_READ_OUT: out STD_LOGIC; - D16_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0) - ); -end entity; - -architecture trb_net_18_to_16_converter_arch of trb_net_18_to_16_converter is - component trb_net_sbuf - generic (DATA_WIDTH : integer := 16; - VERSION: integer := 0); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - -- the COMB_next_READ_OUT should be connected via comb. logic to a register - -- to provide COMB_READ_IN (feedback path with 1 cycle delay) - -- The "REAL" READ_OUT can be constructed in the comb via COMB_next_READ_ - -- OUT and the READ_IN: If one of these is ='1', no problem to read in next - -- step. - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - -- Port to synchronous output. - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - -- Status and control port - STAT_BUFFER: out STD_LOGIC - ); - end component; - -signal dbuf18_comb_dataready_in : std_logic; -signal dbuf18_next_read_out : std_logic; -signal dbuf18_comb_read_in : std_logic; -signal dbuf18_comb_data_in, buf_D16_DATA_OUT : std_logic_vector(17 downto 0); -signal dbuf18_status : std_logic_vector(31 downto 0); -signal buffer_dbuf18_comb_data_in : std_logic_vector(7 downto 0); -signal next_buffer_dbuf18_comb_data_in : std_logic_vector(7 downto 0); -signal next_buf_D18_READ_OUT, buf_D18_READ_OUT : std_logic; -signal D18_PACKET4, last_D18_PACKET4 : std_logic; - - -signal dbuf16_comb_dataready_in : std_logic; -signal dbuf16_next_read_out : std_logic; -signal dbuf16_comb_read_in : std_logic; -signal dbuf16_comb_data_in, buf_D18_data_out : std_logic_vector(17 downto 0); -signal dbuf16_status : std_logic_vector(31 downto 0); -signal buffer_dbuf16_comb_data_in : std_logic_vector(7 downto 0); -signal next_buffer_dbuf16_comb_data_in : std_logic_vector(7 downto 0); -signal next_buf_D16_READ_OUT, buf_D16_READ_OUT : std_logic; -signal D16_packet, next_D16_packet : std_logic_vector(1 downto 0); -signal last_dbuf18_next_read_out : std_logic; - - -begin - ------------------------------------------------------------ ---Direction 18 to 16 ------------------------------------------------------------ - - - -next_buf_D18_READ_OUT <= dbuf18_next_read_out;--and not D18_PACKET4; -D18_READ_OUT <= buf_D18_READ_OUT; - - D18to16 : process(buffer_dbuf18_comb_data_in, dbuf18_comb_data_in, last_D18_PACKET4, - buf_D18_READ_OUT, D18_DATAREADY_IN, D18_PACKET_NUM_IN, D18_DATA_IN, - last_dbuf18_next_read_out) - variable newdata : std_logic; - begin - dbuf18_comb_dataready_in <= '0'; - next_buffer_dbuf18_comb_data_in <= buffer_dbuf18_comb_data_in; - dbuf18_comb_data_in <= dbuf18_comb_data_in; - D18_PACKET4 <= '0'; - - - if buf_D18_READ_OUT = '1' and D18_DATAREADY_IN = '1' then - newdata := '1'; - else - newdata := '0'; - end if; - - - if ((D18_PACKET_NUM_IN /= "00" and newdata = '1') or last_D18_PACKET4 = '1') then - dbuf18_comb_dataready_in <= '1'; - end if; - - - if newdata = '1' and D18_PACKET_NUM_IN /= "00" then - dbuf18_comb_data_in(7 downto 0) <= D18_DATA_IN(15 downto 8); - else - dbuf18_comb_data_in(7 downto 0) <= D18_DATA_IN(15 downto 8);--(others => '0'); - end if; - - if newdata = '1' or last_D18_PACKET4 = '1' then - dbuf18_comb_data_in(15 downto 8) <= buffer_dbuf18_comb_data_in(7 downto 0); - if last_D18_PACKET4 = '0' then - dbuf18_comb_data_in(17 downto 16) <= D18_PACKET_NUM_IN - 1; - else - dbuf18_comb_data_in(17 downto 16) <= "11"; - end if; - else - dbuf18_comb_data_in(15 downto 8) <= (others => '0'); - dbuf18_comb_data_in(17 downto 16) <= "00"; - end if; - - - if (D18_PACKET_NUM_IN = "11" and newdata = '1') or (last_D18_PACKET4 = '1' and last_dbuf18_next_read_out = '0') then - D18_PACKET4 <= '1'; - end if; - - if newdata = '1' then - next_buffer_dbuf18_comb_data_in <= D18_DATA_IN(7 downto 0); - end if; - - - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buffer_dbuf18_comb_data_in <= (others => '0'); - last_D18_PACKET4 <= '0'; - buf_D18_READ_OUT <= '0'; - last_dbuf18_next_read_out <= '0'; - else - buffer_dbuf18_comb_data_in <= next_buffer_dbuf18_comb_data_in; - last_D18_PACKET4 <= D18_PACKET4; - buf_D18_READ_OUT <= next_buf_D18_READ_OUT; - last_dbuf18_next_read_out <= dbuf18_next_read_out; - end if; - end if; - end process; - - - DBUF18 : trb_net_sbuf --dbuf from 18Bit to 16Bit - generic map(DATA_WIDTH => 18, VERSION => VERSION) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => dbuf18_comb_dataready_in, - COMB_next_READ_OUT => dbuf18_next_read_out, - COMB_READ_IN => last_dbuf18_next_read_out, - COMB_DATA_IN => dbuf18_comb_data_in, - -- Port to synchronous output. - SYN_DATAREADY_OUT => D16_DATAREADY_OUT, - SYN_DATA_OUT => buf_D16_DATA_OUT, - SYN_READ_IN => D16_READ_IN, - -- Status and control port - STAT_BUFFER => dbuf18_status(0) - ); - -D16_DATA_OUT <= buf_D16_DATA_OUT(15 downto 0); -D16_PACKET_NUM_OUT <= buf_D16_DATA_OUT(17 downto 16); - - - - ------------------------------------------------------------ ---Direction 16 to 18 ------------------------------------------------------------ - -next_buf_D16_READ_OUT <= dbuf16_next_read_out; -D16_READ_OUT <= buf_D16_READ_OUT; -dbuf16_comb_data_in(15 downto 8) <= (others => '0'); - D16to18 : process(buffer_dbuf16_comb_data_in, dbuf16_comb_data_in, - buf_D16_READ_OUT, D16_DATAREADY_IN, D16_DATA_IN, D16_PACKET_NUM_IN) - variable newdata : std_logic; - begin - - if buf_D16_READ_OUT = '1' and D16_DATAREADY_IN = '1' then - newdata := '1'; - else - newdata := '0'; - end if; - - dbuf16_comb_dataready_in <= newdata; - --next_buffer_dbuf16_comb_data_in <= buffer_dbuf16_comb_data_in; - --dbuf16_comb_data_in <= dbuf16_comb_data_in; - - dbuf16_comb_data_in(17 downto 16) <= D16_PACKET_NUM_IN; - - if newdata = '1' then - dbuf16_comb_data_in(7 downto 0) <= D16_DATA_IN(15 downto 8); - else - dbuf16_comb_data_in(7 downto 0) <= (others => '0'); - end if; - - if newdata = '1' then - if D16_PACKET_NUM_IN = "11" then - next_buffer_dbuf16_comb_data_in <= (others => '0'); - else - next_buffer_dbuf16_comb_data_in <= D16_DATA_IN(7 downto 0); - end if; - else - next_buffer_dbuf16_comb_data_in <= buffer_dbuf16_comb_data_in; - end if; - end process; - - process(CLK, RESET) - begin - if RESET = '1' then - buffer_dbuf16_comb_data_in <= (others => '0'); - --D16_packet <= "00"; - buf_D16_READ_OUT <= '0'; - elsif rising_edge(CLK) then - buffer_dbuf16_comb_data_in <= next_buffer_dbuf16_comb_data_in; - --D16_packet <= next_D16_packet; - buf_D16_READ_OUT <= next_buf_D16_READ_OUT; - else - buffer_dbuf16_comb_data_in <= buffer_dbuf16_comb_data_in; - --D16_packet <= D16_packet; - buf_D16_READ_OUT <= buf_D16_READ_OUT; - end if; - end process; - - - DBUF16 : trb_net_sbuf --dbuf from 16Bit to 18Bit - generic map(DATA_WIDTH => 18, VERSION => VERSION) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => dbuf16_comb_dataready_in, - COMB_next_READ_OUT => dbuf16_next_read_out, - COMB_READ_IN => dbuf16_comb_read_in, - COMB_DATA_IN => dbuf16_comb_data_in, - -- Port to synchronous output. - SYN_DATAREADY_OUT => D18_DATAREADY_OUT, - SYN_DATA_OUT => buf_D18_data_out, - SYN_READ_IN => D18_READ_IN, - -- Status and control port - STAT_BUFFER => dbuf16_status(0) - ); - -D18_DATA_OUT <= buf_D18_data_out(15 downto 0); -D18_PACKET_NUM_OUT <= buf_D18_data_out(17 downto 16); - - dbuf16_read_in_gen : process(CLK, RESET) - begin - if RESET = '1' then - dbuf16_comb_read_in <= '0'; - elsif rising_edge(CLK) then - dbuf16_comb_read_in <= dbuf16_next_read_out; - else - dbuf16_comb_read_in <= dbuf16_comb_read_in; - end if; - end process; - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net_55_to_18_converter.vhd b/oldfiles/trb_net_55_to_18_converter.vhd deleted file mode 100644 index 40b89fe..0000000 --- a/oldfiles/trb_net_55_to_18_converter.vhd +++ /dev/null @@ -1,229 +0,0 @@ ---this is a converter from 64/55 Bit to 18 Bit format. ---It's just a quick hack and should not be used in the final network ---for example, no packet number check is implemented and one cycle is wasted - - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_55_to_18_converter is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - D55_DATA_IN : in std_logic_vector(55 downto 0); - D55_DATAREADY_IN : in std_logic; - D55_READ_OUT : out std_logic; - - D18_DATA_OUT : out std_logic_vector(15 downto 0); - D18_PACKET_NUM_OUT : out std_logic_vector(1 downto 0); - D18_DATAREADY_OUT : out std_logic; - D18_READ_IN : in std_logic; - - D55_DATA_OUT : out std_logic_vector(55 downto 0); - D55_DATAREADY_OUT : out std_logic; - D55_READ_IN : in std_logic; - - D18_DATA_IN : in std_logic_vector(15 downto 0); - D18_PACKET_NUM_IN : in std_logic_vector(1 downto 0); - D18_DATAREADY_IN : in std_logic; - D18_READ_OUT : out std_logic - ); -end entity; - - -architecture trb_net_55_to_18_converter_arch of trb_net_55_to_18_converter is - - - -type CONV_STATE is (IDLE, FIRST, SECOND, THIRD, LAST); -signal D55to18_state, next_D55to18_state : CONV_STATE; -signal D18to55_state, next_D18to55_state : CONV_STATE; - -signal next_D55_READ_OUT, buf_D55_READ_OUT : std_logic; -signal next_D18_DATAREADY_OUT, buf_D18_DATAREADY_OUT : std_logic; -signal next_D18_PACKET_NUM_OUT, buf_D18_PACKET_NUM_OUT : std_logic_vector(1 downto 0); -signal next_D18_DATA_OUT, buf_D18_DATA_OUT : std_logic_vector(15 downto 0); - - -signal next_D18_READ_OUT, buf_D18_READ_OUT : std_logic; -signal next_D55_DATAREADY_OUT, buf_D55_DATAREADY_OUT : std_logic; -signal next_dataread55, dataread55 : std_logic; - --data from 55 read and waiting to be written - -signal next_buf_D55_DATA_IN, buf_D55_DATA_IN : std_logic_vector(55 downto 0); -signal next_D55_DATA_OUT, buf_D55_DATA_OUT : std_logic_vector(55 downto 0); - --databuffer for both directions -begin ------------------------------------------------------------ ---Direction 18 to 55 ------------------------------------------------------------ - - D18to55_fsm : process(D55_READ_IN, buf_D55_DATAREADY_OUT, buf_D18_READ_OUT, D18_DATAREADY_IN, - D18to55_state, buf_D55_DATA_OUT, D18_DATA_IN) - variable dataisread18, dataisread55 : std_logic; - begin - next_D55_DATA_OUT <= buf_D55_DATA_OUT; - next_D18to55_state <= D18to55_state; - next_D18_READ_OUT <= '1'; - next_D55_DATAREADY_OUT <= '0'; - - dataisread55 := D55_READ_IN AND buf_D55_DATAREADY_OUT; - dataisread18 := buf_D18_READ_OUT AND D18_DATAREADY_IN; - - - case D18to55_state is - when IDLE => - if(dataisread18 = '1') then - next_D55_DATA_OUT(55 downto 48) <= D18_DATA_IN(7 downto 0); - next_D18to55_state <= FIRST; - end if; - when FIRST => - if(dataisread18 = '1') then - next_D55_DATA_OUT(47 downto 32) <= D18_DATA_IN; - next_D18to55_state <= SECOND; - end if; - when SECOND => - if(dataisread18 = '1') then - next_D55_DATA_OUT(31 downto 16) <= D18_DATA_IN; - next_D18to55_state <= THIRD; - end if; - when THIRD => - if(dataisread18 = '1') then - next_D55_DATA_OUT(15 downto 0) <= D18_DATA_IN; - next_D55_DATAREADY_OUT <= '1'; - next_D18to55_state <= LAST; - next_D18_READ_OUT <= '0'; - end if; - when LAST => - if(dataisread55 = '1') then - next_D55_DATA_OUT <= (others => '0'); - next_D55_DATAREADY_OUT <= '0'; - next_D18to55_state <= IDLE; - else - next_D18_READ_OUT <= '0'; - next_D55_DATAREADY_OUT <= '1'; - end if; - end case; - end process; - - D18to55_fsm_reg : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_D55_DATA_OUT <= (others => '0'); - D18to55_state <= IDLE; - buf_D55_DATAREADY_OUT <= '0'; - buf_D18_READ_OUT <= '0'; - else - buf_D55_DATA_OUT <= next_D55_DATA_OUT; - D18to55_state <= next_D18to55_state; - buf_D55_DATAREADY_OUT <= next_D55_DATAREADY_OUT; - buf_D18_READ_OUT <= next_D18_READ_OUT; - end if; - end if; - end process; - -D55_DATA_OUT <= buf_D55_DATA_OUT; -D55_DATAREADY_OUT <= buf_D55_DATAREADY_OUT; -D18_READ_OUT <= buf_D18_READ_OUT; - ------------------------------------------------------------ ---Direction 55 to 18 ------------------------------------------------------------ - D55to18_fsm : process(buf_D18_DATA_OUT, buf_D18_PACKET_NUM_OUT, buf_D18_DATAREADY_OUT, - D18_READ_IN, D55_DATA_IN, D55_DATAREADY_IN, D55to18_state, - buf_D55_READ_OUT, buf_D55_DATA_IN, dataread55) - variable dataisread18, dataisread55 : std_logic; - begin - next_D18_DATA_OUT <= buf_D18_DATA_OUT; - next_D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT; - next_D55to18_state <= D55to18_state; - next_D55_READ_OUT <= '0'; - next_buf_D55_DATA_IN <= buf_D55_DATA_IN; - - dataisread18 := D18_READ_IN AND buf_D18_DATAREADY_OUT; - dataisread55 := D55_DATAREADY_IN AND buf_D55_READ_OUT; - - if(dataisread18 = '1') then - next_D18_DATAREADY_OUT <= '0'; - else - next_D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT; - end if; - - - case D55to18_state is - when IDLE => - if (dataisread18 = '1' OR buf_D18_DATAREADY_OUT = '0') then - next_D55_READ_OUT <= '1'; - if dataisread55 = '1' then - next_buf_D55_DATA_IN(55 downto 0) <= D55_DATA_IN(55 downto 0); - next_D55_READ_OUT <= '0'; - next_D18_DATA_OUT(7 downto 0) <= D55_DATA_IN(55 downto 48); - next_D18_DATA_OUT(15 downto 8) <= (others => '0'); - next_D18_PACKET_NUM_OUT <= "00"; - next_D18_DATAREADY_OUT <= '1'; - next_D55to18_state <= FIRST; - end if; - end if; - when FIRST => - if(dataisread18 = '1') then - next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(47 downto 32); - next_D18_DATAREADY_OUT <= '1'; - next_D18_PACKET_NUM_OUT <= "01"; - next_D55to18_state <= SECOND; - end if; - when SECOND => - if(dataisread18 = '1') then - next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(31 downto 16); - next_D18_DATAREADY_OUT <= '1'; - next_D18_PACKET_NUM_OUT <= "10"; - next_D55to18_state <= THIRD; - end if; - when THIRD => - if(dataisread18 = '1') then - next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(15 downto 0); - next_D18_DATAREADY_OUT <= '1'; - next_D18_PACKET_NUM_OUT <= "11"; - next_D55to18_state <= IDLE; - next_D55_READ_OUT <= '1'; - end if; - when others => - next_D55to18_state <= IDLE; - end case; - end process; - - D55to18_fsm_reg : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_D18_DATA_OUT <= (others => '0'); - buf_D55_DATA_IN <= (others => '0'); - buf_D55_READ_OUT <= '0'; - buf_D18_DATAREADY_OUT <= '0'; - buf_D18_PACKET_NUM_OUT <= "00"; - D55to18_state <= IDLE; - else - buf_D18_DATA_OUT <= next_D18_DATA_OUT; - buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT; - buf_D55_READ_OUT <= next_D55_READ_OUT; - buf_D55_DATA_IN <= next_buf_D55_DATA_IN; - buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT; - D55to18_state <= next_D55to18_state; - end if; - end if; - end process; - -D18_DATA_OUT <= buf_D18_DATA_OUT; -D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT; -D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT; -D55_READ_OUT <= buf_D55_READ_OUT; - - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net_64_to_18_converter.vhd b/oldfiles/trb_net_64_to_18_converter.vhd deleted file mode 100644 index 69a8265..0000000 --- a/oldfiles/trb_net_64_to_18_converter.vhd +++ /dev/null @@ -1,229 +0,0 @@ ---this is a converter from 64/55 Bit to 18 Bit format. ---It's just a quick hack and should not be used in the final network ---for example, no packet number check is implemented and one cycle is wasted - - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_64_to_18_converter is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - D55_DATA_IN : in std_logic_vector(50 downto 0); - D55_DATAREADY_IN : in std_logic; - D55_READ_OUT : out std_logic; - - D18_DATA_OUT : out std_logic_vector(15 downto 0); - D18_PACKET_NUM_OUT : out std_logic_vector(1 downto 0); - D18_DATAREADY_OUT : out std_logic; - D18_READ_IN : in std_logic; - - D55_DATA_OUT : out std_logic_vector(50 downto 0); - D55_DATAREADY_OUT : out std_logic; - D55_READ_IN : in std_logic; - - D18_DATA_IN : in std_logic_vector(15 downto 0); - D18_PACKET_NUM_IN : in std_logic_vector(1 downto 0); - D18_DATAREADY_IN : in std_logic; - D18_READ_OUT : out std_logic - ); -end entity; - - -architecture trb_net_64_to_18_converter_arch of trb_net_64_to_18_converter is - - - -type CONV_STATE is (IDLE, FIRST, SECOND, THIRD, LAST); -signal D55to18_state, next_D55to18_state : CONV_STATE; -signal D18to55_state, next_D18to55_state : CONV_STATE; - -signal next_D55_READ_OUT, buf_D55_READ_OUT : std_logic; -signal next_D18_DATAREADY_OUT, buf_D18_DATAREADY_OUT : std_logic; -signal next_D18_PACKET_NUM_OUT, buf_D18_PACKET_NUM_OUT : std_logic_vector(1 downto 0); -signal next_D18_DATA_OUT, buf_D18_DATA_OUT : std_logic_vector(15 downto 0); - - -signal next_D18_READ_OUT, buf_D18_READ_OUT : std_logic; -signal next_D55_DATAREADY_OUT, buf_D55_DATAREADY_OUT : std_logic; -signal next_dataread55, dataread55 : std_logic; - --data from 55 read and waiting to be written - -signal next_buf_D55_DATA_IN, buf_D55_DATA_IN : std_logic_vector(50 downto 0); -signal next_D55_DATA_OUT, buf_D55_DATA_OUT : std_logic_vector(50 downto 0); - --databuffer for both directions -begin ------------------------------------------------------------ ---Direction 18 to 55 ------------------------------------------------------------ - - D18to55_fsm : process(D55_READ_IN, buf_D55_DATAREADY_OUT, buf_D18_READ_OUT, D18_DATAREADY_IN, - D18to55_state, buf_D55_DATA_OUT, D18_DATA_IN) - variable dataisread18, dataisread55 : std_logic; - begin - next_D55_DATA_OUT <= buf_D55_DATA_OUT; - next_D18to55_state <= D18to55_state; - next_D18_READ_OUT <= '1'; - next_D55_DATAREADY_OUT <= '0'; - - dataisread55 := D55_READ_IN AND buf_D55_DATAREADY_OUT; - dataisread18 := buf_D18_READ_OUT AND D18_DATAREADY_IN; - - - case D18to55_state is - when IDLE => - if(dataisread18 = '1') then - next_D55_DATA_OUT(50 downto 48) <= D18_DATA_IN(2 downto 0); - next_D18to55_state <= FIRST; - end if; - when FIRST => - if(dataisread18 = '1') then - next_D55_DATA_OUT(47 downto 32) <= D18_DATA_IN; - next_D18to55_state <= SECOND; - end if; - when SECOND => - if(dataisread18 = '1') then - next_D55_DATA_OUT(31 downto 16) <= D18_DATA_IN; - next_D18to55_state <= THIRD; - end if; - when THIRD => - if(dataisread18 = '1') then - next_D55_DATA_OUT(15 downto 0) <= D18_DATA_IN; - next_D55_DATAREADY_OUT <= '1'; - next_D18to55_state <= LAST; - next_D18_READ_OUT <= '0'; - end if; - when LAST => - if(dataisread55 = '1') then - next_D55_DATA_OUT <= (others => '0'); - next_D55_DATAREADY_OUT <= '0'; - next_D18to55_state <= IDLE; - else - next_D18_READ_OUT <= '0'; - next_D55_DATAREADY_OUT <= '1'; - end if; - end case; - end process; - - D18to55_fsm_reg : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_D55_DATA_OUT <= (others => '0'); - D18to55_state <= IDLE; - buf_D55_DATAREADY_OUT <= '0'; - buf_D18_READ_OUT <= '0'; - else - buf_D55_DATA_OUT <= next_D55_DATA_OUT; - D18to55_state <= next_D18to55_state; - buf_D55_DATAREADY_OUT <= next_D55_DATAREADY_OUT; - buf_D18_READ_OUT <= next_D18_READ_OUT; - end if; - end if; - end process; - -D55_DATA_OUT <= buf_D55_DATA_OUT; -D55_DATAREADY_OUT <= buf_D55_DATAREADY_OUT; -D18_READ_OUT <= buf_D18_READ_OUT; - ------------------------------------------------------------ ---Direction 55 to 18 ------------------------------------------------------------ - D55to18_fsm : process(buf_D18_DATA_OUT, buf_D18_PACKET_NUM_OUT, buf_D18_DATAREADY_OUT, - D18_READ_IN, D55_DATA_IN, D55_DATAREADY_IN, D55to18_state, - buf_D55_READ_OUT, buf_D55_DATA_IN, dataread55) - variable dataisread18, dataisread55 : std_logic; - begin - next_D18_DATA_OUT <= buf_D18_DATA_OUT; - next_D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT; - next_D55to18_state <= D55to18_state; - next_D55_READ_OUT <= '0'; - next_buf_D55_DATA_IN <= buf_D55_DATA_IN; - - dataisread18 := D18_READ_IN AND buf_D18_DATAREADY_OUT; - dataisread55 := D55_DATAREADY_IN AND buf_D55_READ_OUT; - - if(dataisread18 = '1') then - next_D18_DATAREADY_OUT <= '0'; - else - next_D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT; - end if; - - - case D55to18_state is - when IDLE => - if (dataisread18 = '1' OR buf_D18_DATAREADY_OUT = '0') then - next_D55_READ_OUT <= '1'; - if dataisread55 = '1' then - next_buf_D55_DATA_IN(50 downto 0) <= D55_DATA_IN(50 downto 0); - next_D55_READ_OUT <= '0'; - next_D18_DATA_OUT(2 downto 0) <= D55_DATA_IN(50 downto 48); - next_D18_DATA_OUT(15 downto 3) <= (others => '0'); - next_D18_PACKET_NUM_OUT <= "00"; - next_D18_DATAREADY_OUT <= '1'; - next_D55to18_state <= FIRST; - end if; - end if; - when FIRST => - if(dataisread18 = '1') then - next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(47 downto 32); - next_D18_DATAREADY_OUT <= '1'; - next_D18_PACKET_NUM_OUT <= "01"; - next_D55to18_state <= SECOND; - end if; - when SECOND => - if(dataisread18 = '1') then - next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(31 downto 16); - next_D18_DATAREADY_OUT <= '1'; - next_D18_PACKET_NUM_OUT <= "10"; - next_D55to18_state <= THIRD; - end if; - when THIRD => - if(dataisread18 = '1') then - next_D18_DATA_OUT(15 downto 0) <= buf_D55_DATA_IN(15 downto 0); - next_D18_DATAREADY_OUT <= '1'; - next_D18_PACKET_NUM_OUT <= "11"; - next_D55to18_state <= IDLE; - next_D55_READ_OUT <= '1'; - end if; - when others => - next_D55to18_state <= IDLE; - end case; - end process; - - D55to18_fsm_reg : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_D18_DATA_OUT <= (others => '0'); - buf_D55_DATA_IN <= (others => '0'); - buf_D55_READ_OUT <= '0'; - buf_D18_DATAREADY_OUT <= '0'; - buf_D18_PACKET_NUM_OUT <= "00"; - D55to18_state <= IDLE; - else - buf_D18_DATA_OUT <= next_D18_DATA_OUT; - buf_D18_DATAREADY_OUT <= next_D18_DATAREADY_OUT; - buf_D55_READ_OUT <= next_D55_READ_OUT; - buf_D55_DATA_IN <= next_buf_D55_DATA_IN; - buf_D18_PACKET_NUM_OUT <= next_D18_PACKET_NUM_OUT; - D55to18_state <= next_D55to18_state; - end if; - end if; - end process; - -D18_DATA_OUT <= buf_D18_DATA_OUT; -D18_DATAREADY_OUT <= buf_D18_DATAREADY_OUT; -D18_PACKET_NUM_OUT <= buf_D18_PACKET_NUM_OUT; -D55_READ_OUT <= buf_D55_READ_OUT; - - -end architecture; \ No newline at end of file diff --git a/oldfiles/trb_net_active_api.vhd b/oldfiles/trb_net_active_api.vhd deleted file mode 100644 index ef6c0b0..0000000 --- a/oldfiles/trb_net_active_api.vhd +++ /dev/null @@ -1,203 +0,0 @@ --- connection between the TRBNET and any application --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_active_api is - - generic (FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - -- not needed now, but later - ); -end trb_net_active_api; - -architecture trb_net_active_api_arch of trb_net_active_api is - - component trb_net_base_api is - generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Internal direction port - -- the ports with active or passive in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - INT_MASTER_DATAREADY_OUT: out STD_LOGIC; - INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_MASTER_READ_IN: in STD_LOGIC; - - INT_MASTER_DATAREADY_IN: in STD_LOGIC; - INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_MASTER_READ_OUT: out STD_LOGIC; - - INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT: out STD_LOGIC; - INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_SLAVE_READ_IN: in STD_LOGIC; - - INT_SLAVE_DATAREADY_IN: in STD_LOGIC; - INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_SLAVE_READ_OUT: out STD_LOGIC; - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - -- not needed now, but later - ); - end component; - -begin - - ACTIVE_API: trb_net_base_api - generic map ( - API_TYPE => 1, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH - ) - port map ( - CLK => CLK, - CLK_EN => CLK_EN, - RESET => RESET, - - APL_DATA_IN => APL_DATA_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - APL_DATA_OUT => APL_DATA_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT, - INT_MASTER_READ_IN => INT_INIT_READ_IN, - - INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_MASTER_DATA_IN => INT_INIT_DATA_IN, - INT_MASTER_READ_OUT => INT_INIT_READ_OUT, - - INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - - INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT, - INT_SLAVE_READ_IN => INT_REPLY_READ_IN, - - INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN, - INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT, - -- Status and control port - STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, - STAT_FIFO_TO_APL => STAT_FIFO_TO_APL - -- not needed now, but later - ); - -end trb_net_active_api_arch; diff --git a/oldfiles/trb_net_active_apimbuf.vhd b/oldfiles/trb_net_active_apimbuf.vhd deleted file mode 100644 index 1bb8346..0000000 --- a/oldfiles/trb_net_active_apimbuf.vhd +++ /dev/null @@ -1,467 +0,0 @@ --- an active api together with an iobuf - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_active_apimbuf is - - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3; -- or the replyibuf - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0); - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -END trb_net_active_apimbuf; - -architecture trb_net_active_apimbuf_arch of trb_net_active_apimbuf is - -component trb_net_iobuf is - - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3); -- or the replyibuf - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading - - MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading - - MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0) - ); -END component; - -component trb_net_active_api is - - generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end component; - -component trb_net_io_multiplexer is - - generic (BUS_WIDTH : integer := 56; - MULT_WIDTH : integer := 5); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - -- highest bits are mult. - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - MED_READ_IN: in STD_LOGIC; - - -- Internal direction port - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); -END component; - -signal apl_to_buf_INIT_DATAREADY: STD_LOGIC; -signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal apl_to_buf_INIT_READ : STD_LOGIC; - -signal buf_to_apl_INIT_DATAREADY: STD_LOGIC; -signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal buf_to_apl_INIT_READ : STD_LOGIC; - -signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC; -signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal apl_to_buf_REPLY_READ : STD_LOGIC; - -signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC; -signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal buf_to_apl_REPLY_READ : STD_LOGIC; - --- for the connection to the multiplexer -signal MED_INIT_DATAREADY_OUT : STD_LOGIC; -signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_IN : STD_LOGIC; - -signal MED_INIT_DATAREADY_IN : STD_LOGIC; -signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_OUT : STD_LOGIC; - -signal MED_REPLY_DATAREADY_OUT : STD_LOGIC; -signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_IN : STD_LOGIC; - -signal MED_REPLY_DATAREADY_IN : STD_LOGIC; -signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_OUT : STD_LOGIC; - -signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0); -signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0); -signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0); - -signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0); -signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0); -signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0); - -begin - - m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT; - m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT; - m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT; - MED_INIT_READ_IN <= m_READ_IN(0); - MED_REPLY_READ_IN <= m_READ_IN(1); - - MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0); - MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1); - MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0); - MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51); - m_READ_OUT(0) <= MED_INIT_READ_OUT; - m_READ_OUT(1) <= MED_REPLY_READ_OUT; - - - ACTIVE_API: trb_net_active_api - - generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH) - - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - -- connect via private signals - - INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, - INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA, - INT_INIT_READ_IN => apl_to_buf_INIT_READ, - - INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, - INT_INIT_DATA_IN => buf_to_apl_INIT_DATA, - INT_INIT_READ_OUT => buf_to_apl_INIT_READ, - - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT =>apl_to_buf_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA, - INT_REPLY_READ_IN => apl_to_buf_REPLY_READ, - - INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, - INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA, - INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ, - - -- Status and control port - STAT_FIFO_TO_INT => api_stat_fifo_to_int, - STAT_FIFO_TO_APL => api_stat_fifo_to_apl - ); - -STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); -STAT_api_control_signals(3) <= APL_WRITE_IN; -STAT_api_control_signals(4) <= APL_SEND_IN; -STAT_api_control_signals(7 downto 5) <= (others => '0'); -STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0); -STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY; -STAT_api_control_signals(12) <= apl_to_buf_INIT_READ; -STAT_api_control_signals(31 downto 13) <= (others => '0'); - - - -IOBUF: trb_net_iobuf - - generic map (INIT_DEPTH => INIT_DEPTH, - REPLY_DEPTH => REPLY_DEPTH) - - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, - MED_INIT_READ_IN => MED_INIT_READ_IN, - - MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_INIT_DATA_IN, - MED_INIT_READ_OUT => MED_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - - MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, - MED_REPLY_READ_IN => MED_REPLY_READ_IN, - - MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, - MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, - INT_INIT_READ_IN => buf_to_apl_INIT_READ, - - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, - INT_INIT_READ_OUT => apl_to_buf_INIT_READ, - - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, - - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, - - -- Status and control port - STAT_GEN => STAT_GEN, - STAT_LOCKED => STAT_LOCKED, - STAT_INIT_BUFFER => STAT_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, - CTRL_GEN => CTRL_GEN, - CTRL_LOCKED => CTRL_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER - ); - - MPLEX: trb_net_io_multiplexer - generic map (BUS_WIDTH => 52, - MULT_WIDTH => 1) - port map ( - CLK => CLK, - RESET => RESET , - CLK_EN => CLK_EN, - - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_READ_OUT => MED_READ_OUT, - - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_READ_IN => MED_READ_IN, - - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_READ_IN =>m_READ_OUT, - - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_READ_OUT =>m_READ_IN, - - CTRL => MPLEX_CTRL - - ); - -end trb_net_active_apimbuf_arch; - diff --git a/oldfiles/trb_net_apimbuf_fast_lvds.vhd b/oldfiles/trb_net_apimbuf_fast_lvds.vhd deleted file mode 100644 index 4a4df49..0000000 --- a/oldfiles/trb_net_apimbuf_fast_lvds.vhd +++ /dev/null @@ -1,512 +0,0 @@ ------------------------------------------------------------------------------- --- --- This is a combination of the fast 8bit lvds interface and an active or --- passive api, selectable with generic "API_TYPE" --- ------------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - - - -entity trb_net_apimbuf_fast_lvds is - generic ( - API_TYPE : integer range 0 to 1 := 0 --0: passive, 1: active api - ); - port( - CLK : in std_logic; - RESET : in std_logic; - API_RESET : in std_logic; - CLK_EN : in std_logic; - - --LVDS - LVDS_IN : in std_logic_vector(15 downto 0); - LVDS_OUT : out std_logic_vector(15 downto 0); - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and Control registers - API_STAT_GEN: out std_logic_vector(31 downto 0); - API_STAT_LOCKED: out std_logic_vector(31 downto 0); - API_STAT_INIT_BUFFER: out std_logic_vector(31 downto 0); - API_STAT_REPLY_BUFFER: out std_logic_vector(31 downto 0); - API_STAT_control_signals: out std_logic_vector(31 downto 0); - STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0); - LVDS_STAT: out std_logic_vector(31 downto 0); - LVDS_CTRL: in std_logic_vector(31 downto 0); - MPLEX_CTRL: in std_logic_vector(31 downto 0) - ); -end entity; - - -architecture trb_net_apimbuf_fast_lvds_arch of trb_net_apimbuf_fast_lvds is - component trb_net_55_to_18_converter is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - D55_DATA_IN : in std_logic_vector(55 downto 0); - D55_DATAREADY_IN : in std_logic; - D55_READ_OUT : out std_logic; - - D18_DATA_OUT : out std_logic_vector(15 downto 0); - D18_PACKET_NUM_OUT : out std_logic_vector(1 downto 0); - D18_DATAREADY_OUT : out std_logic; - D18_READ_IN : in std_logic; - - D55_DATA_OUT : out std_logic_vector(55 downto 0); - D55_DATAREADY_OUT : out std_logic; - D55_READ_IN : in std_logic; - - D18_DATA_IN : in std_logic_vector(15 downto 0); - D18_PACKET_NUM_IN : in std_logic_vector(1 downto 0); - D18_DATAREADY_IN : in std_logic; - D18_READ_OUT : out std_logic - ); - end component; - - component trb_net_active_apimbuf is - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3; -- or the replyibuf - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0); - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net_passive_apimbuf is - generic ( - INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3; -- or the replyibuf - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and control port - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0); - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); - end component; - - - component trb_net_med_8bit_fast is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- 1st part: from the medium to the internal logic (trbnet) - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - INT_PACKET_NR_OUT: out STD_LOGIC_VECTOR(1 downto 0); - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- 2nd part: from the internal logic (trbnet) to the medium - INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media - INT_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - INT_PACKET_NR_IN : in STD_LOGIC_VECTOR(1 downto 0); - INT_READ_OUT: out STD_LOGIC; -- offered word is read - INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Media direction port - -- in this case for the cable => 32 lines in total - MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word - MED_TRANSMISSION_CLK_OUT: out STD_LOGIC; - MED_CARRIER_OUT: out STD_LOGIC; - MED_PARITY_OUT: out STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (12 downto 0); -- Data word - MED_TRANSMISSION_CLK_IN: in STD_LOGIC; - MED_CARRIER_IN: in STD_LOGIC; - MED_PARITY_IN: in STD_LOGIC; - -- Status and control port => this never can hurt - STAT: out STD_LOGIC_VECTOR (31 downto 0); - CTRL: in STD_LOGIC_VECTOR (31 downto 0) - ); - end component; - - ------------------------------------------------------------------------ ---media interface signals ------------------------------------------------------------------------ - signal LVDS_INT_DATAREADY_OUT : std_logic; - signal LVDS_INT_DATA_OUT : std_logic_vector(15 downto 0); - signal LVDS_INT_READ_IN : std_logic; - signal LVDS_INT_ERROR_IN : std_logic_vector(2 downto 0); - signal LVDS_INT_DATAREADY_IN : std_logic; - signal LVDS_INT_DATA_IN : std_logic_vector(15 downto 0); - signal LVDS_INT_READ_OUT : std_logic; - signal LVDS_INT_ERROR_OUT : std_logic_vector(2 downto 0); - signal LVDS_MED_DATA_OUT : std_logic_vector(12 downto 0); - signal LVDS_MED_TRANSMISSION_CLK_OUT : std_logic; - signal LVDS_MED_CARRIER_OUT : std_logic; - signal LVDS_MED_PARITY_OUT : std_logic; - signal LVDS_MED_DATA_IN : std_logic_vector(12 downto 0); - signal LVDS_MED_TRANSMISSION_CLK_IN : std_logic; - signal LVDS_MED_CARRIER_IN : std_logic; - signal LVDS_MED_PARITY_IN : std_logic; - signal LVDS_INT_PACKET_NUM_OUT : std_logic_vector(1 downto 0); - signal LVDS_INT_PACKET_NUM_IN : std_logic_vector(1 downto 0); - - - ------------------------------------------------------------------------ ---API signals ------------------------------------------------------------------------ - signal API_MED_DATAREADY_OUT : std_logic; - signal API_MED_DATA_OUT : std_logic_vector(51 downto 0); - signal API_MED_READ_IN : std_logic; - signal API_MED_ERROR_IN : std_logic_vector(2 downto 0); - signal API_MED_DATAREADY_IN : std_logic; - signal API_MED_DATA_IN : std_logic_vector(51 downto 0); - signal API_MED_READ_OUT : std_logic; - signal API_MED_ERROR_OUT : std_logic_vector(2 downto 0); - signal API_ctrl : std_logic_vector(31 downto 0); - signal C5518_D55_DATA_IN, C5518_D55_DATA_OUT : std_logic_vector(55 downto 0); - ------------------------------------------------------------------------ ---Control signals ------------------------------------------------------------------------ - - - -begin - - ------------------------------------------------------------------------ ---the media interface ------------------------------------------------------------------------ - lvds: trb_net_med_8bit_fast - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - INT_DATAREADY_OUT => LVDS_INT_DATAREADY_OUT, - INT_DATA_OUT => LVDS_INT_DATA_OUT, - INT_PACKET_NR_OUT => LVDS_INT_PACKET_NUM_OUT, - INT_READ_IN => LVDS_INT_READ_IN, - INT_ERROR_OUT => LVDS_INT_ERROR_OUT, - INT_DATAREADY_IN => LVDS_INT_DATAREADY_IN, - INT_DATA_IN => LVDS_INT_DATA_IN, - INT_PACKET_NR_IN => LVDS_INT_PACKET_NUM_IN, - INT_READ_OUT => LVDS_INT_READ_OUT, - INT_ERROR_IN => LVDS_INT_ERROR_IN, - - MED_DATA_OUT => LVDS_MED_DATA_OUT, - MED_TRANSMISSION_CLK_OUT => LVDS_MED_TRANSMISSION_CLK_OUT, - MED_CARRIER_OUT => LVDS_MED_CARRIER_OUT, - MED_PARITY_OUT => LVDS_MED_PARITY_OUT, - MED_DATA_IN => LVDS_MED_DATA_IN, - MED_TRANSMISSION_CLK_IN => LVDS_MED_TRANSMISSION_CLK_IN, - MED_CARRIER_IN => LVDS_MED_CARRIER_IN, - MED_PARITY_IN => LVDS_MED_PARITY_IN, - STAT => LVDS_STAT, - CTRL => LVDS_CTRL - ); - - LVDS_OUT(7 downto 0) <= LVDS_MED_DATA_OUT(7 downto 0); - LVDS_OUT(10) <= C5518_D55_DATA_OUT(48); - LVDS_OUT(9) <= LVDS_INT_DATA_OUT(0); - LVDS_OUT(8) <= LVDS_INT_DATAREADY_OUT; - LVDS_OUT(11) <= LVDS_MED_DATA_OUT(11) and not API_RESET; - LVDS_OUT(12) <= LVDS_MED_DATA_OUT(12); - LVDS_OUT(13) <= LVDS_MED_TRANSMISSION_CLK_OUT; - LVDS_OUT(14) <= LVDS_MED_CARRIER_OUT; - LVDS_OUT(15) <= LVDS_MED_PARITY_OUT; - LVDS_MED_DATA_IN <= LVDS_IN(12 downto 0); - LVDS_MED_TRANSMISSION_CLK_IN <= LVDS_IN(13); - LVDS_MED_CARRIER_IN <= LVDS_IN(14); - LVDS_MED_PARITY_IN <= LVDS_IN(15); - - ------------------------------------------------------------------------ ---bus width converter ------------------------------------------------------------------------ - C5518 : trb_net_55_to_18_converter - port map( - -- Misc - CLK => CLK, - RESET => API_RESET, - CLK_EN => CLK_EN, - - D55_DATA_IN => C5518_D55_DATA_IN, - D55_DATAREADY_IN => API_MED_DATAREADY_OUT, - D55_READ_OUT => API_MED_READ_IN, - - D18_DATA_OUT => LVDS_INT_DATA_IN, - D18_PACKET_NUM_OUT => LVDS_INT_PACKET_NUM_IN, - D18_DATAREADY_OUT => LVDS_INT_DATAREADY_IN, - D18_READ_IN => LVDS_INT_READ_OUT, - - D55_DATA_OUT => C5518_D55_DATA_OUT, - D55_DATAREADY_OUT => API_MED_DATAREADY_IN, - D55_READ_IN => API_MED_READ_OUT, - - D18_DATA_IN => LVDS_INT_DATA_OUT, - D18_PACKET_NUM_IN => LVDS_INT_PACKET_NUM_OUT, - D18_DATAREADY_IN => LVDS_INT_DATAREADY_OUT, - D18_READ_OUT => LVDS_INT_READ_IN - ); - - C5518_D55_DATA_IN(51 downto 0) <= API_MED_DATA_OUT; - C5518_D55_DATA_IN(55 downto 52) <= "0000"; - API_MED_DATA_IN <= C5518_D55_DATA_OUT(51 downto 0); - ------------------------------------------------------------------------ ---API ------------------------------------------------------------------------ - - apigenact : if API_TYPE = 1 generate - API: trb_net_active_apimbuf - generic map ( - FIFO_TERM_BUFFER_DEPTH => 3) - port map ( - CLK => CLK, - RESET => API_RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - -- Media direction - MED_DATAREADY_OUT => API_MED_DATAREADY_OUT, - MED_DATA_OUT => API_MED_DATA_OUT, - MED_READ_IN => API_MED_READ_IN, - MED_ERROR_IN => LVDS_INT_ERROR_OUT, - MED_DATAREADY_IN => API_MED_DATAREADY_IN, - MED_DATA_IN => API_MED_DATA_IN, - MED_READ_OUT => API_MED_READ_OUT, - - CTRL_LOCKED => (others => '0'), - CTRL_GEN => (others => '0'), - - STAT_GEN => API_STAT_GEN, - STAT_LOCKED => API_STAT_LOCKED, - STAT_INIT_BUFFER => API_STAT_INIT_BUFFER, - STAT_REPLY_BUFFER => API_STAT_REPLY_BUFFER, - STAT_api_control_signals => API_STAT_control_signals, - STAT_MPLEX => STAT_MPLEX, - STAT_CTRL_INIT_BUFFER => (others => '0'), - STAT_CTRL_REPLY_BUFFER => (others => '0'), - MPLEX_CTRL => MPLEX_CTRL, - API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT, - API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL - ); - end generate; - - apigenpas : if API_TYPE = 0 generate - API: trb_net_passive_apimbuf - generic map ( - FIFO_TERM_BUFFER_DEPTH => 3) - port map ( - CLK => CLK, - RESET => API_RESET, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_SEQNR_OUT => APL_SEQNR_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - -- Media direction - MED_DATAREADY_OUT => API_MED_DATAREADY_OUT, - MED_DATA_OUT => API_MED_DATA_OUT, - MED_READ_IN => API_MED_READ_IN, - MED_ERROR_IN => API_MED_ERROR_IN, - MED_DATAREADY_IN => API_MED_DATAREADY_IN, - MED_DATA_IN => API_MED_DATA_IN, - MED_READ_OUT => API_MED_READ_OUT, - - CTRL_LOCKED => (others => '0'), - CTRL_GEN => (others => '0'), - - STAT_GEN => API_STAT_GEN, - STAT_LOCKED => API_STAT_LOCKED, - STAT_INIT_BUFFER => API_STAT_INIT_BUFFER, - STAT_REPLY_BUFFER => API_STAT_REPLY_BUFFER, - STAT_api_control_signals => API_STAT_control_signals, - STAT_MPLEX => STAT_MPLEX, - STAT_CTRL_INIT_BUFFER => (others => '0'), - STAT_CTRL_REPLY_BUFFER => (others => '0'), - MPLEX_CTRL => MPLEX_CTRL, - API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT, - API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL - ); - end generate; - -end architecture; - - - - - - - diff --git a/oldfiles/trb_net_base_api.vhd b/oldfiles/trb_net_base_api.vhd deleted file mode 100644 index 09b4b87..0000000 --- a/oldfiles/trb_net_base_api.vhd +++ /dev/null @@ -1,722 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_base_api is - - generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - INT_MASTER_DATAREADY_OUT: out STD_LOGIC; - INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_MASTER_READ_IN: in STD_LOGIC; - - INT_MASTER_DATAREADY_IN: in STD_LOGIC; - INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_MASTER_READ_OUT: out STD_LOGIC; - - - INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT: out STD_LOGIC; - INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_SLAVE_READ_IN: in STD_LOGIC; - - INT_SLAVE_DATAREADY_IN: in STD_LOGIC; - INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_SLAVE_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - -- not needed now, but later - - ); -end entity trb_net_base_api; - - - -architecture trb_net_base_api_arch of trb_net_base_api is - component trb_net_fifo is - generic ( - WIDTH : integer := 8; -- FIFO word width - DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1) - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - end component; - - component trb_net_dummy_fifo is - generic (WIDTH : integer := 8); -- Depth of the FIFO, 2^(n+1) - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - end component; - - component trb_net_sbuf is - generic (DATA_WIDTH : integer := 56; - VERSION: integer := 1); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - -- Port to synchronous output. - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - -- Status and control port - STAT_BUFFER: out STD_LOGIC - ); - end component; - - - - component trb_net_term is - generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of the master - -- path, if set to 0 no buffer is used at all - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_DATAREADY_IN: in STD_LOGIC; - INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - APL_GOT_TRM: out STD_LOGIC; - APL_HOLD_TRM: in STD_LOGIC; - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0) -- My own address (temporary solution!!!) - -- Status and control port - -- not needed now, but later - ); - end component; - - -- signals for the APL to INT fifo: - signal fifo_to_int_data_in : std_logic_vector(47 downto 0); - signal fifo_to_int_write : std_logic; - signal fifo_to_int_data_out : std_logic_vector(47 downto 0); - signal fifo_to_int_read : std_logic; - signal fifo_to_int_full : std_logic; - signal fifo_to_int_empty : std_logic; - - -- signals for the INT to APL: - signal fifo_to_apl_data_in : std_logic_vector(50 downto 0); - signal fifo_to_apl_write : std_logic; - signal fifo_to_apl_data_out : std_logic_vector(50 downto 0); - signal fifo_to_apl_read : std_logic; - signal fifo_to_apl_full : std_logic; - signal fifo_to_apl_empty : std_logic; - - -- signals for the test buffer - signal fifo_term_buffer_data_in : std_logic_vector(50 downto 0); - signal fifo_term_buffer_write : std_logic; - signal fifo_term_buffer_data_out : std_logic_vector(50 downto 0); - signal fifo_term_buffer_read : std_logic; - signal fifo_term_buffer_full : std_logic; - signal fifo_term_buffer_empty : std_logic; - - signal state_bits : std_logic_vector(2 downto 0); - type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); - type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); - signal current_state, next_state : API_STATE; - signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; - signal slave_running, next_slave_running : std_logic; - - signal combined_header: std_logic_vector(47 downto 0); --stored in sbuf - -- , registered_header, next_registered_header: std_logic_vector(47 downto 0); - --signal update_registered_header: std_logic; - signal combined_trailer, registered_trailer, next_registered_trailer: std_logic_vector(47 downto 0); - signal update_registered_trailer: std_logic; - signal tb_registered_trailer, tb_next_registered_trailer: std_logic_vector(47 downto 0); - signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0); - - signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); - signal next_INT_MASTER_DATA_OUT: std_logic_vector(50 downto 0); - signal next_INT_MASTER_DATAREADY_OUT: std_logic; - signal sbuf_free, sbuf_next_READ: std_logic; - signal next_INT_SLAVE_READ_OUT, reg_INT_SLAVE_READ_OUT: std_logic; - signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; - signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0); - signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); - - type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); - signal out_select: OUTPUT_SELECT; - -begin - ---------------------------------------- --- termination for active api ---------------------------------------- - --- gen_term: if API_TYPE = 1 generate - TrbNetTerm: trb_net_term - generic map(FIFO_TERM_BUFFER_DEPTH => 0) - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => INT_SLAVE_DATAREADY_OUT, - INT_DATA_OUT => INT_SLAVE_DATA_OUT, - INT_READ_IN => INT_SLAVE_READ_IN, - INT_DATAREADY_IN => INT_MASTER_DATAREADY_IN, - INT_DATA_IN => INT_MASTER_DATA_IN, - INT_READ_OUT => INT_MASTER_READ_OUT, - APL_HOLD_TRM => '0', - APL_DTYPE_IN => (others => '0'), - APL_ERROR_PATTERN_IN => (others => '0'), - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN - ); --- end generate; - --- gen_noterm: if API_TYPE = 0 generate --- INT_SLAVE_READ_OUT <= '0'; --- --- end generate; - ---------------------------------------- --- fifo to internal ---------------------------------------- - - CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate - FIFO_TO_INT: trb_net_fifo - generic map ( - WIDTH => 48, - DEPTH => FIFO_TO_INT_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_int_data_in, - WRITE_ENABLE_IN => fifo_to_int_write, - DATA_OUT => fifo_to_int_data_out, - READ_ENABLE_IN => fifo_to_int_read, - FULL_OUT => fifo_to_int_full, - EMPTY_OUT => fifo_to_int_empty - ); - end generate; - - CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate - FIFO_TO_INT: trb_net_dummy_fifo - generic map ( - WIDTH => 48) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_int_data_in, - WRITE_ENABLE_IN => fifo_to_int_write, - DATA_OUT => fifo_to_int_data_out, - READ_ENABLE_IN => fifo_to_int_read, - FULL_OUT => fifo_to_int_full, - EMPTY_OUT => fifo_to_int_empty - ); - end generate CHECK_BUFFER4; - - STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0); - STAT_FIFO_TO_INT(3) <= fifo_to_int_write; - STAT_FIFO_TO_INT(10 downto 8) <= fifo_to_int_data_out(2 downto 0); - STAT_FIFO_TO_INT(11) <= fifo_to_int_read; - STAT_FIFO_TO_INT(14) <= fifo_to_int_full; - STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; - STAT_FIFO_TO_INT(7 downto 4) <= (others => '0'); - STAT_FIFO_TO_INT(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_INT(28 downto 16) <= (others => '0'); - STAT_FIFO_TO_INT(31 downto 29) <= state_bits; ---------------------------------------- --- fifo to apl ---------------------------------------- - - CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate - FIFO_TO_APL: trb_net_fifo - generic map ( - WIDTH => 51, - DEPTH => FIFO_TO_APL_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_apl_data_in, - WRITE_ENABLE_IN => fifo_to_apl_write, - DATA_OUT => fifo_to_apl_data_out, - READ_ENABLE_IN => fifo_to_apl_read, - FULL_OUT => fifo_to_apl_full, - EMPTY_OUT => fifo_to_apl_empty - ); - end generate CHECK_BUFFER5; - - CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate - FIFO_TO_APL: trb_net_dummy_fifo - generic map ( - WIDTH => 51) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_to_apl_data_in, - WRITE_ENABLE_IN => fifo_to_apl_write, - DATA_OUT => fifo_to_apl_data_out, - READ_ENABLE_IN => fifo_to_apl_read, - FULL_OUT => fifo_to_apl_full, - EMPTY_OUT => fifo_to_apl_empty - ); - end generate CHECK_BUFFER6; - - STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); - STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; - STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0); - STAT_FIFO_TO_APL(11) <= fifo_to_apl_read; - STAT_FIFO_TO_APL(14) <= fifo_to_apl_full; - STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty; - STAT_FIFO_TO_APL(7 downto 4) <= (others => '0'); - --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_APL(31 downto 16) <= (others => '0'); - STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT; - STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN; - STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT; - ---------------------------------------- --- a sbuf on the active channel ---------------------------------------- - - ACTIVE_SBUF: trb_net_sbuf - generic map ( - DATA_WIDTH => 51, - VERSION => 0) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_INT_MASTER_DATAREADY_OUT, - COMB_next_READ_OUT => sbuf_next_READ, - COMB_READ_IN => '1', - COMB_DATA_IN => next_INT_MASTER_DATA_OUT, - SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT, - SYN_DATA_OUT => INT_MASTER_DATA_OUT, - SYN_READ_IN => INT_MASTER_READ_IN - ); - - - - --sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle - sbuf_free <= sbuf_next_READ; - next_registered_trailer <= combined_trailer; - --next_registered_header <= combined_header; - next_APL_DATA_OUT <= fifo_to_apl_data_out(DWORD_POSITION); - next_APL_TYP_OUT <= fifo_to_apl_data_out(TYPE_POSITION); - - ---------------------------------------- --- select data for int direction ---------------------------------------- - process (out_select, combined_header, registered_trailer, - fifo_to_int_data_out, combined_trailer) - begin - if out_select = HDR then - next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; - next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= combined_header; - elsif out_select = TRM then - next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= registered_trailer; - elsif out_select = TRM_COMB then - next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= combined_trailer; - else - next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; - next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; - end if; - end process; - - ---------------------------------------- --- the state machine ---------------------------------------- --- gen_active_fsm : if API_TYPE = 1 generate - STATE_COMB : process(current_state, APL_SEND_IN, combined_header, - INT_MASTER_READ_IN, APL_WRITE_IN, fifo_to_int_empty, - fifo_to_int_data_out, combined_trailer, slave_running, - next_registered_trailer, fifo_to_int_data_out, - fifo_to_apl_empty, INT_SLAVE_DATAREADY_IN, - reg_INT_SLAVE_READ_OUT,fifo_to_apl_read, - reg_APL_DATAREADY_OUT, fifo_to_apl_data_out, - reg_APL_DATAREADY_OUT, APL_READ_IN, sbuf_free, - reg_APL_TYP_OUT, APL_SHORT_TRANSFER_IN, fifo_to_apl_full) - begin -- process - next_state <= MY_ERROR; - next_INT_MASTER_DATAREADY_OUT <= '0'; - out_select <= DAT; - update_registered_trailer <= '0'; - fifo_to_int_read <= '0'; - next_INT_SLAVE_READ_OUT <= '0'; - fifo_to_apl_write <= '0'; - next_APL_DATAREADY_OUT <= '0'; - fifo_to_apl_read <= '0'; - next_slave_running <= slave_running; - next_sequence_counter <= sequence_counter; - ------------------------------------------------------------------------------- - -- IDLE - ------------------------------------------------------------------------------- - if current_state = IDLE then - if APL_SEND_IN = '1' then - if APL_SHORT_TRANSFER_IN = '1' and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' then - next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN - next_INT_MASTER_DATAREADY_OUT <= '0'; - update_registered_trailer <= '1'; -- moved from SEND_SHORT - else -- normal transfer, prepare the header - next_state <= SEND_HEADER; - out_select <= HDR; - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; -- next word will be a header - else - next_state <= IDLE; - end if; -- APL_SEND_IN - ------------------------------------------------------------------------------- - -- SEND_SHORT - ------------------------------------------------------------------------------- - elsif current_state = SEND_SHORT then - next_state <= SEND_SHORT; - if APL_SEND_IN = '0' then -- terminate the transfer - next_state <= SEND_TRAILER; - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= TRM; - end if; - ------------------------------------------------------------------------------- - -- SEND_HEADER - ------------------------------------------------------------------------------- - elsif current_state = SEND_HEADER then - if sbuf_free = '1' then -- kill current header - next_state <= RUNNING; - if fifo_to_int_empty = '1' then - next_INT_MASTER_DATAREADY_OUT <= '0'; - else - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= DAT; - fifo_to_int_read <= '1'; - end if; -- fifo_to_int_empty - else - next_state <= SEND_HEADER; - end if; - ------------------------------------------------------------------------------- - -- RUNNING - ------------------------------------------------------------------------------- - elsif current_state = RUNNING then - if APL_SEND_IN = '0' then -- terminate the transfer - if fifo_to_int_empty = '1' then -- immediate stop - next_state <= SEND_TRAILER; - update_registered_trailer <= '1'; - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= TRM_COMB; - else - next_state <= SHUTDOWN; - update_registered_trailer <= '1'; - if sbuf_free = '1' then - -- data words have to be prepared - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= DAT; - fifo_to_int_read <= '1'; - end if; -- fifo_to_int_empty = '0' - end if; - else -- APL_SEND_IN: still running - next_state <= RUNNING; - if fifo_to_int_empty = '0' and sbuf_free = '1' then - -- data words have to be prepared - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= DAT; - fifo_to_int_read <= '1'; - end if; -- fifo_to_int_empty = '0' - end if; - ------------------------------------------------------------------------------- - -- SHUTDOWN: Empty the pipe - ------------------------------------------------------------------------------- - elsif current_state = SHUTDOWN then - next_state <= SHUTDOWN; - if fifo_to_int_empty = '0' and sbuf_free = '1' then - -- data words have to be prepared - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= DAT; - fifo_to_int_read <= '1'; - elsif sbuf_free = '1' then - -- we are done - next_state <= SEND_TRAILER; - next_INT_MASTER_DATAREADY_OUT <= '1'; - out_select <= TRM; - end if; - ------------------------------------------------------------------------------- - -- SEND_TRAILER - ------------------------------------------------------------------------------- - elsif current_state = SEND_TRAILER then - if sbuf_free = '1' then -- kill current trailer - next_state <= WAITING; - out_select <= TRM; - next_INT_MASTER_DATAREADY_OUT <= '0'; - next_slave_running <= '0'; - else - next_state <= SEND_TRAILER; - end if; - ------------------------------------------------------------------------------- - -- WAITING => for the answer or a request - ------------------------------------------------------------------------------- - elsif current_state = WAITING then - next_state <= WAITING; - -- here we have to supply the receiver port - -- part 1: connection to network - if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then - next_INT_SLAVE_READ_OUT <= '1'; - end if; - if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then - fifo_to_apl_write <= '1'; -- use fifo as the pipe - end if; - - -- part 2: connection to apl --- if fifo_to_apl_empty = '0' then - if fifo_to_apl_empty = '0' and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') then --is this really correct???? - next_APL_DATAREADY_OUT <= '1'; - end if; -- read/no read - - if reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1' then - -- valid read - fifo_to_apl_read <= '1'; - if (reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR) then - next_slave_running <= '1'; - end if; - if reg_APL_TYP_OUT = TYPE_TRM and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') then --fifo_to_apl_read = '1' - next_state <= IDLE; - next_sequence_counter <= sequence_counter +1; - end if; - end if; - -- MISSING: SEQNR check - -- OPEN QUESTION: Address matching? makes sense for a reply transfer? - end if; -- end state switch - end process; --- end generate; - - - ---------------------------------------- --- ---------------------------------------- - - -- combine the next header - combined_header(F1_POSITION) <= APL_MY_ADDRESS_IN; - combined_header(F2_POSITION) <= APL_TARGET_ADDRESS_IN; - combined_header(15 downto 14) <= (others => '0'); -- LAY - combined_header(13 downto 12) <= (others => '0'); -- VERS - combined_header(11 downto 4) <= sequence_counter; -- SEQNR - combined_header(3 downto 0) <= APL_DTYPE_IN; - combined_trailer(F1_POSITION) <= APL_ERROR_PATTERN_IN(31 downto 16); - combined_trailer(F2_POSITION) <= APL_ERROR_PATTERN_IN(15 downto 0); - combined_trailer(15 downto 14) <= (others => '0'); -- res. - combined_trailer(13 downto 12) <= (others => '0'); -- VERS - combined_trailer(11 downto 4) <= sequence_counter; -- SEQNR - combined_trailer(3 downto 0) <= APL_DTYPE_IN; - -- this is not very consequent, find a better solution the be independent - -- with the range - - -- connect Transmitter port - fifo_to_int_data_in <= APL_DATA_IN; - fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full) when (current_state = IDLE or - current_state = SEND_HEADER or - current_state = RUNNING) - - else '0'; - - - APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing - - - INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_DATAREADY_OUT <= '0'; - reg_APL_DATA_OUT <= (others => '0'); - reg_APL_TYP_OUT <= (others => '0'); - else - reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; - reg_APL_DATA_OUT <= next_APL_DATA_OUT; - reg_APL_TYP_OUT <= next_APL_TYP_OUT; - end if; - end if; - end process; - - - -- connect receiver - fifo_to_apl_data_in <= INT_SLAVE_DATA_IN; - --- this has to be registered! --- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; --- reg_APL_DATA_OUT <= next_APL_DATA_OUT; --- reg_APL_TYP_OUT <= next_APL_TYP_OUT; - - APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; - APL_DATA_OUT <= reg_APL_DATA_OUT; - APL_TYP_OUT <= reg_APL_TYP_OUT; --- APL_RUN_OUT <= '0' when ((current_state = IDLE )) - APL_RUN_OUT <= '0' when ((current_state = IDLE and API_TYPE = 1) - or (slave_running = '0' and API_TYPE = 0)) - else '1'; - APL_SEQNR_OUT <= sequence_counter; - ---removed and put into main state machine --- generate the sequence counter --- -- combinatorial part --- SEQNR_COMB : process(sequence_counter, current_state, next_state) --- begin --- if current_state = WAITING and next_state = IDLE then --- next_sequence_counter <= sequence_counter+1; --- else --- next_sequence_counter <= sequence_counter; --- end if; --- end process; - - - - CLK_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - sequence_counter <= (others => '0'); - reg_INT_SLAVE_READ_OUT <= '0'; - if API_TYPE = 1 then - current_state <= IDLE; - else - current_state <= WAITING; - end if; - slave_running <= '0'; - tb_current_state <= IDLE; - tb_registered_trailer <= (others => '0'); - tb_registered_target <= ILLEGAL_ADRESS; - elsif CLK_EN = '1' then - sequence_counter <= next_sequence_counter; - reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; - current_state <= next_state; - slave_running <= next_slave_running; - tb_current_state <= tb_next_state; - tb_registered_trailer <= tb_next_registered_trailer; - tb_registered_target <= tb_next_registered_target; - else - sequence_counter <= sequence_counter; - reg_INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; - current_state <= current_state; - slave_running <= slave_running; - tb_current_state <= tb_current_state; - tb_registered_trailer <= tb_registered_trailer; - tb_registered_target <= tb_registered_target; - end if; - end if; - end process; - - REG3 : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - registered_trailer <= (others => '0'); - elsif update_registered_trailer = '1' then - registered_trailer <= next_registered_trailer; - else - registered_trailer <= registered_trailer; - end if; - end if; - end process; - -process(current_state) - begin - case current_state is - when IDLE => state_bits <= "000"; - when SEND_HEADER => state_bits <= "001"; - when RUNNING => state_bits <= "010"; - when SHUTDOWN => state_bits <= "011"; - when SEND_SHORT => state_bits <= "100"; - when SEND_TRAILER => state_bits <= "101"; - when WAITING => state_bits <= "110"; - when others => state_bits <= "111"; - end case; - end process; - - - -end architecture trb_net_base_api_arch; - - - diff --git a/oldfiles/trb_net_endpoint_3ch.vhd b/oldfiles/trb_net_endpoint_3ch.vhd deleted file mode 100644 index da6f3ae..0000000 --- a/oldfiles/trb_net_endpoint_3ch.vhd +++ /dev/null @@ -1,582 +0,0 @@ --- this is the final endpoint to be used --- It has 3 channels - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_endpoint_3ch is - - -- per channel we have the following generics: - -- 1.) APIX_FIFO_TO_INT_DEPTH - -- 2.) APIX_FIFO_TO_APL_DEPTH - -- 3.) APIX_TYPE (0=active, 1=passive, 99=dummy) - -- 4.) APIX_INIT_DEPTH - -- 5.) APIX_REPLY_DEPTH - -- 6.) APIX_CHANNEL_NUMBER - - -- The dummy APL can be used for debugging - -- In this case, the API lines are use only for sniffing - -- and the input lines can be driven to any value - -- with one exeption: - -- if APL_SEND_IN = '0' the dummy APL will be resetted - - generic ( - - API1_FIFO_TO_INT_DEPTH: integer := 3; - API1_FIFO_TO_APL_DEPTH: integer := 3; - API1_TYPE : integer := 0; - API1_INIT_DEPTH : integer := 3; - API1_REPLY_DEPTH : integer := 3; - API1_CHANNEL_NUMBER : integer := 0; - - API2_FIFO_TO_INT_DEPTH: integer := 3; - API2_FIFO_TO_APL_DEPTH: integer := 3; - API2_TYPE : integer := 0; - API2_INIT_DEPTH : integer := 3; - API2_REPLY_DEPTH : integer := 3; - API2_CHANNEL_NUMBER : integer := 1; - - API3_FIFO_TO_INT_DEPTH: integer := 3; - API3_FIFO_TO_APL_DEPTH: integer := 3; - API3_TYPE : integer := 0; - API3_INIT_DEPTH : integer := 3; - API3_REPLY_DEPTH : integer := 3; - API3_CHANNEL_NUMBER : integer := 2 - - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - ---------------------------------------------------------------------------- - -- API1 - ---------------------------------------------------------------------------- - -- APL Transmitter port - APL1_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL1_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL1_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL1_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL1_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL1_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL1_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL1_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL1_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL1_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL1_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL1_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL1_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL1_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - ---------------------------------------------------------------------------- - -- API2 - ---------------------------------------------------------------------------- - -- APL Transmitter port - APL2_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL2_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL2_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL2_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL2_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL2_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL2_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL2_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL2_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL2_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL2_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL2_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL2_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL2_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - ---------------------------------------------------------------------------- - -- API3 - ---------------------------------------------------------------------------- - -- APL Transmitter port - APL3_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL3_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL3_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL3_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL3_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL3_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL3_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL3_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL3_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL3_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL3_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL3_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL3_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL3_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - - ---------------------------------------------------------------------------- - -- Common API stuff - ---------------------------------------------------------------------------- - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); - - -- IOBUF ports missing -> Later (BUGBUG) - - APL_GOT_TRM : out STD_LOGIC_VECTOR (15 downto 0); --pattern from the - --unused TERMs - APL_HOLD_TRM: in STD_LOGIC_VECTOR (15 downto 0); --put to "0" - - --------------------------------------------------------------------------- - -- Media direction port (directly to be connected to MII) - --------------------------------------------------------------------------- - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - MED_MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0) - ); -END trb_net_endpoint_3ch; - -architecture trb_net_endpoint_3ch_arch of trb_net_endpoint_3ch is - - component trb_net_io_multiplexer is - - generic (BUS_WIDTH : integer := 56; - MULT_WIDTH : integer := 5); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - -- highest bits are mult. - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - MED_READ_IN: in STD_LOGIC; - - -- Internal direction port - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); -END component; - -component trb_net_active_apimbuf is - - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3; -- or the replyibuf - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0) - ); -END component; - -component trb_net_term_mbuf is - - generic (FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - APL_GOT_TRM: out STD_LOGIC; - - APL_HOLD_TRM: in STD_LOGIC; - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0) - ); -END component; - --- for the connection to the multiplexer -signal MED_INIT_DATAREADY_OUT : STD_LOGIC; -signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_IN : STD_LOGIC; - -signal MED_INIT_DATAREADY_IN : STD_LOGIC; -signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_OUT : STD_LOGIC; - -signal MED_REPLY_DATAREADY_OUT : STD_LOGIC; -signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_IN : STD_LOGIC; - -signal MED_REPLY_DATAREADY_IN : STD_LOGIC; -signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_OUT : STD_LOGIC; - -signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (15 downto 0); -signal m_DATA_OUT : STD_LOGIC_VECTOR (831 downto 0); -signal m_READ_IN : STD_LOGIC_VECTOR (15 downto 0); - -signal m_DATAREADY_IN : STD_LOGIC_VECTOR (15 downto 0); -signal m_DATA_IN : STD_LOGIC_VECTOR (831 downto 0); -signal m_READ_OUT : STD_LOGIC_VECTOR (15 downto 0); - -begin - - --- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT; --- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT; --- m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT; --- m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT; --- MED_INIT_READ_IN <= m_READ_IN(0); --- MED_REPLY_READ_IN <= m_READ_IN(1); - --- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0); --- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1); --- MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0); --- MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51); --- m_READ_OUT(0) <= MED_INIT_READ_OUT; --- m_READ_OUT(1) <= MED_REPLY_READ_OUT; - - G1: for channel in 0 to 15 generate -------------------------------------------------------------------------------- --- loop over the channels -------------------------------------------------------------------------------- - GEN_API1: if not (channel = API1_CHANNEL_NUMBER) - and not (channel = API2_CHANNEL_NUMBER) - and not (channel = API3_CHANNEL_NUMBER) - generate - -- make the term - TERM: trb_net_term_mbuf - - generic map (FIFO_TERM_BUFFER_DEPTH => 0 ) - port map ( - -- Misc - CLK => CLK, - RESET => RESET , - CLK_EN => CLK_EN, - -- Media direction port - MED_DATAREADY_OUT => m_DATAREADY_OUT(channel), - MED_DATA_OUT => m_DATA_OUT(channel*52+51 downto channel*52), - MED_READ_IN => m_READ_IN(channel), - - MED_DATAREADY_IN => m_DATAREADY_IN(channel), - MED_DATA_IN => m_DATA_IN(channel*52+51 downto channel*52), - MED_READ_OUT => m_READ_OUT(channel), - MED_ERROR_IN => (others => '0'), - - APL_GOT_TRM => APL_GOT_TRM(channel), - - APL_HOLD_TRM => APL_HOLD_TRM(channel), - APL_DTYPE_IN => (others => '0'), - APL_ERROR_PATTERN_IN => (others => '0'), - - CTRL_GEN => (others => '0'), - CTRL_LOCKED => (others => '0'), - STAT_CTRL_INIT_BUFFER => (others => '0'), - STAT_CTRL_REPLY_BUFFER=> (others => '0'), - - MPLEX_CTRL => APL_MPLEX_CTRL ); - end generate; - end generate; - - MPLEX: trb_net_io_multiplexer - generic map (BUS_WIDTH => 56, - MULT_WIDTH => 4) - port map ( - CLK => CLK, - RESET => RESET , - CLK_EN => CLK_EN, - - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_READ_OUT => MED_READ_OUT, - - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_READ_IN => MED_READ_IN, - - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_READ_IN =>m_READ_OUT, - - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_READ_OUT =>m_READ_IN, - - CTRL => MED_MPLEX_CTRL - ); - -API1: trb_net_active_apimbuf - - generic map (INIT_DEPTH => API1_INIT_DEPTH, - REPLY_DEPTH => API1_REPLY_DEPTH, - FIFO_TO_INT_DEPTH => API1_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => API1_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_DATAREADY_OUT => m_DATAREADY_OUT(API1_CHANNEL_NUMBER), - MED_DATA_OUT => m_DATA_OUT(API1_CHANNEL_NUMBER*52+51 downto API1_CHANNEL_NUMBER*52), - MED_READ_IN => m_READ_IN(API1_CHANNEL_NUMBER), - - MED_DATAREADY_IN => m_DATAREADY_IN(API1_CHANNEL_NUMBER), - MED_DATA_IN => m_DATA_IN(API1_CHANNEL_NUMBER*52+51 downto API1_CHANNEL_NUMBER*52), - MED_READ_OUT => m_READ_OUT(API1_CHANNEL_NUMBER), - MED_ERROR_IN => (others => '0'), - - -- APL Transmitter port - APL_DATA_IN => APL1_DATA_IN, - APL_WRITE_IN => APL1_WRITE_IN, - APL_FIFO_FULL_OUT => APL1_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL1_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL1_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL1_ERROR_PATTERN_IN, - APL_SEND_IN => APL1_SEND_IN, - APL_TARGET_ADDRESS_IN => APL1_TARGET_ADDRESS_IN, - - -- Receiver port - APL_DATA_OUT => APL1_DATA_OUT, - APL_TYP_OUT => APL1_TYP_OUT, - APL_DATAREADY_OUT => APL1_DATAREADY_OUT, - APL_READ_IN => APL1_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL1_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL1_SEQNR_OUT, - - CTRL_GEN => (others => '0'), - CTRL_LOCKED => (others => '0'), - STAT_CTRL_INIT_BUFFER => (others => '0'), - STAT_CTRL_REPLY_BUFFER=> (others => '0'), - MPLEX_CTRL => APL_MPLEX_CTRL - ); - -API2: trb_net_active_apimbuf - - generic map (INIT_DEPTH => API2_INIT_DEPTH, - REPLY_DEPTH => API2_REPLY_DEPTH, - FIFO_TO_INT_DEPTH => API2_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => API2_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_DATAREADY_OUT => m_DATAREADY_OUT(API2_CHANNEL_NUMBER), - MED_DATA_OUT => m_DATA_OUT(API2_CHANNEL_NUMBER*52+51 downto API2_CHANNEL_NUMBER*52), - MED_READ_IN => m_READ_IN(API2_CHANNEL_NUMBER), - - MED_DATAREADY_IN => m_DATAREADY_IN(API2_CHANNEL_NUMBER), - MED_DATA_IN => m_DATA_IN(API2_CHANNEL_NUMBER*52+51 downto API2_CHANNEL_NUMBER*52), - MED_READ_OUT => m_READ_OUT(API2_CHANNEL_NUMBER), - MED_ERROR_IN => (others => '0'), - - -- APL Transmitter port - APL_DATA_IN => APL2_DATA_IN, - APL_WRITE_IN => APL2_WRITE_IN, - APL_FIFO_FULL_OUT => APL2_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL2_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL2_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL2_ERROR_PATTERN_IN, - APL_SEND_IN => APL2_SEND_IN, - APL_TARGET_ADDRESS_IN => APL2_TARGET_ADDRESS_IN, - - -- Receiver port - APL_DATA_OUT => APL2_DATA_OUT, - APL_TYP_OUT => APL2_TYP_OUT, - APL_DATAREADY_OUT => APL2_DATAREADY_OUT, - APL_READ_IN => APL2_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL2_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL2_SEQNR_OUT, - - CTRL_GEN => (others => '0'), - CTRL_LOCKED => (others => '0'), - STAT_CTRL_INIT_BUFFER => (others => '0'), - STAT_CTRL_REPLY_BUFFER=> (others => '0'), - MPLEX_CTRL => APL_MPLEX_CTRL - ); - -API3: trb_net_active_apimbuf - - generic map (INIT_DEPTH => API3_INIT_DEPTH, - REPLY_DEPTH => API3_REPLY_DEPTH, - FIFO_TO_INT_DEPTH => API3_FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => API3_FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - - port map( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_DATAREADY_OUT => m_DATAREADY_OUT(API3_CHANNEL_NUMBER), - MED_DATA_OUT => m_DATA_OUT(API3_CHANNEL_NUMBER*52+51 downto API3_CHANNEL_NUMBER*52), - MED_READ_IN => m_READ_IN(API3_CHANNEL_NUMBER), - - MED_DATAREADY_IN => m_DATAREADY_IN(API3_CHANNEL_NUMBER), - MED_DATA_IN => m_DATA_IN(API3_CHANNEL_NUMBER*52+51 downto API3_CHANNEL_NUMBER*52), - MED_READ_OUT => m_READ_OUT(API3_CHANNEL_NUMBER), - MED_ERROR_IN => (others => '0'), - - -- APL Transmitter port - APL_DATA_IN => APL3_DATA_IN, - APL_WRITE_IN => APL3_WRITE_IN, - APL_FIFO_FULL_OUT => APL3_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL3_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL3_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL3_ERROR_PATTERN_IN, - APL_SEND_IN => APL3_SEND_IN, - APL_TARGET_ADDRESS_IN => APL3_TARGET_ADDRESS_IN, - - -- Receiver port - APL_DATA_OUT => APL3_DATA_OUT, - APL_TYP_OUT => APL3_TYP_OUT, - APL_DATAREADY_OUT => APL3_DATAREADY_OUT, - APL_READ_IN => APL3_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL3_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL3_SEQNR_OUT, - - CTRL_GEN => (others => '0'), - CTRL_LOCKED => (others => '0'), - STAT_CTRL_INIT_BUFFER => (others => '0'), - STAT_CTRL_REPLY_BUFFER=> (others => '0'), - MPLEX_CTRL => APL_MPLEX_CTRL - ); - - -end trb_net_endpoint_3ch_arch; - diff --git a/oldfiles/trb_net_fanout_hub.vhd b/oldfiles/trb_net_fanout_hub.vhd deleted file mode 100644 index 5f6f73e..0000000 --- a/oldfiles/trb_net_fanout_hub.vhd +++ /dev/null @@ -1,400 +0,0 @@ - --- This is to be rewritten before it can be fully used. It is not approbriate --- to use full apis in a hub - rewriting every header takes way too much time --- and too much buffers - ---LIMITATIONS: --------------- --- long transfers are not transmitted, since the addresses do not match! --- no check for fifo_full on active apis --- seqnr are not synchronized --- all outputs must be connected - - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_fanout_hub is - generic( - OUTPUT_PORTS : integer range 1 to 8 := 4 - ); - port( - CLK: in std_logic; - CLK_EN: in std_logic; - RESET: in std_logic; - - - STAT: out std_logic_vector(31 downto 0) - ); -end entity; - - -architecture trb_net_fanout_hub_arch of trb_net_fanout_hub is - -component trb_net_passive_apimbuf is - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3; -- or the replyibuf - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); - end component; - -component trb_net_active_apimbuf is - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3; -- or the replyibuf - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); - end component; - - - -type logic_1_array is array (OUTPUT_PORTS downto 0) of std_logic; -type vector_3_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(2 downto 0); -type vector_4_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(3 downto 0); -type vector_8_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(7 downto 0); -type vector_16_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(15 downto 0); -type vector_32_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(31 downto 0); -type vector_48_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(47 downto 0); -type vector_52_array is array (OUTPUT_PORTS downto 0) of std_logic_vector(51 downto 0); - ---(0) of each array is the passive input api ---(x) all others are the active output apis - - -signal MED_DATAREADY_OUT : logic_1_array; -signal MED_DATA_OUT: vector_52_array; -signal MED_READ_IN: logic_1_array; -signal MED_DATAREADY_IN: logic_1_array; -signal MED_DATA_IN: vector_52_array; -signal MED_READ_OUT: logic_1_array; -signal MED_ERROR_IN: vector_3_array; -signal APL_DATA_IN: vector_48_array; -signal APL_WRITE_IN: logic_1_array; -signal APL_FIFO_FULL_OUT: logic_1_array; -signal APL_SHORT_TRANSFER_IN:logic_1_array; -signal APL_DTYPE_IN: vector_4_array; -signal APL_ERROR_PATTERN_IN: vector_32_array; -signal APL_SEND_IN: logic_1_array; -signal APL_TARGET_ADDRESS_IN:vector_16_array; -signal APL_DATA_OUT: vector_48_array; -signal APL_TYP_OUT: vector_3_array; -signal APL_DATAREADY_OUT: logic_1_array; -signal APL_READ_IN: logic_1_array; -signal APL_RUN_OUT: logic_1_array; -signal APL_MY_ADDRESS_IN: vector_16_array; -signal APL_SEQNR_OUT: vector_8_array; -signal STAT_GEN: vector_32_array; -signal STAT_LOCKED: vector_32_array; -signal STAT_INIT_BUFFER: vector_32_array; -signal STAT_REPLY_BUFFER: vector_32_array; -signal STAT_api_control_signals: vector_32_array; -signal CTRL_GEN: vector_32_array; -signal CTRL_LOCKED: vector_32_array; -signal STAT_CTRL_INIT_BUFFER: vector_32_array; -signal STAT_CTRL_REPLY_BUFFER: vector_32_array; -signal MPLEX_CTRL: vector_32_array; -signal API_STAT_FIFO_TO_INT: vector_32_array; -signal API_STAT_FIFO_TO_APL: vector_32_array; - -signal this_APL_RUN_OUT, last_APL_RUN_OUT : logic_1_array; -signal APL_RUN_OUT_fallen, next_APL_RUN_OUT_fallen : logic_1_array; -signal next_APL_SEND_IN : logic_1_array; - - - -begin - ---------------------------------------- ---generate all apis ---------------------------------------- - - output_api: for i in 1 to OUTPUT_PORTS generate - output_api: trb_net_active_apimbuf - --no generic map, using defaults - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_OUT => MED_DATAREADY_OUT(i), - MED_DATA_OUT => MED_DATA_OUT(i), - MED_READ_IN => MED_READ_IN(i), - MED_DATAREADY_IN => MED_DATAREADY_IN(i), - MED_DATA_IN => MED_DATA_IN(i), - MED_READ_OUT => MED_READ_OUT(i), - MED_ERROR_IN => MED_ERROR_IN(i), - APL_DATA_IN => APL_DATA_IN(1), - APL_WRITE_IN => APL_WRITE_IN(1), - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(i), - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(1), - APL_DTYPE_IN => APL_DTYPE_IN(1), - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(1), - APL_SEND_IN => APL_SEND_IN(1), - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(1), - APL_DATA_OUT => APL_DATA_OUT(i), - APL_TYP_OUT => APL_TYP_OUT(i), - APL_DATAREADY_OUT => APL_DATAREADY_OUT(i), - APL_READ_IN => APL_READ_IN(1), - APL_RUN_OUT => APL_RUN_OUT(i), - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(1), - APL_SEQNR_OUT => APL_SEQNR_OUT(i), - STAT_GEN => STAT_GEN(i), - STAT_LOCKED => STAT_LOCKED(i), - STAT_INIT_BUFFER => STAT_INIT_BUFFER(i), - STAT_REPLY_BUFFER => STAT_REPLY_BUFFER(i), - STAT_api_control_signals => STAT_api_control_signals(i), - CTRL_GEN => CTRL_GEN(i), - CTRL_LOCKED => CTRL_LOCKED(i), - STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER(i), - STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER(i), - MPLEX_CTRL => MPLEX_CTRL(i), - API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT(i), - API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL(i) - ); - end generate; - - - input_api: trb_net_passive_apimbuf - --no generic map, using defaults - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_OUT => MED_DATAREADY_OUT(0), - MED_DATA_OUT => MED_DATA_OUT(0), - MED_READ_IN => MED_READ_IN(0), - MED_DATAREADY_IN => MED_DATAREADY_IN(0), - MED_DATA_IN => MED_DATA_IN(0), - MED_READ_OUT => MED_READ_OUT(0), - MED_ERROR_IN => MED_ERROR_IN(0), - --- - APL_DATA_IN => APL_DATA_IN(0), - APL_WRITE_IN => APL_WRITE_IN(0), - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(0), - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(0), - APL_DTYPE_IN => APL_DTYPE_IN(0), - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN(0), - APL_SEND_IN => APL_SEND_IN(0), - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN(0), - APL_DATA_OUT => APL_DATA_OUT(0), - APL_TYP_OUT => APL_TYP_OUT(0), - APL_DATAREADY_OUT => APL_DATAREADY_OUT(0), - APL_READ_IN => APL_READ_IN(0), - APL_RUN_OUT => APL_RUN_OUT(0), - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(0), - APL_SEQNR_OUT => APL_SEQNR_OUT(0), - --- - STAT_GEN => STAT_GEN(0), - STAT_LOCKED => STAT_LOCKED(0), - STAT_INIT_BUFFER => STAT_INIT_BUFFER(0), - STAT_REPLY_BUFFER => STAT_REPLY_BUFFER(0), - STAT_api_control_signals => STAT_api_control_signals(0), - CTRL_GEN => CTRL_GEN(0), - CTRL_LOCKED => CTRL_LOCKED(0), - STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER(0), - STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER(0), - MPLEX_CTRL => MPLEX_CTRL(0), - API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT(0), - API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL(0) - ); - - - - - APL_DATA_IN(1) <= (others => '0'); - APL_SHORT_TRANSFER_IN(1) <= '1'; - APL_SHORT_TRANSFER_IN(0) <= '1'; - APL_ERROR_PATTERN_IN(1) <= APL_DATA_OUT(0)(47 downto 16); - APL_WRITE_IN(1) <= '0'; - APL_WRITE_IN(0) <= '0'; - - APL_DTYPE_IN(1) <= APL_DATA_OUT(0)(3 downto 0); - APL_SEND_IN(1) <= APL_DATAREADY_OUT(0); - APL_TARGET_ADDRESS_IN(1) <= (others => '0'); - APL_READ_IN(1) <= '1'; - APL_READ_IN(0) <= '1'; - APL_MY_ADDRESS_IN(1) <= (others => '0'); - ---merge all errorpatterns -------------------------- - process(APL_DATA_OUT) - variable tmp : std_logic_vector(31 downto 0); - begin - tmp := (others => '0'); - for i in 1 to OUTPUT_PORTS loop - tmp := tmp or APL_DATA_OUT(i)(47 downto 16); - end loop; - APL_ERROR_PATTERN_IN(0) <= tmp; - end process; - - ---check for falling run_out for all output apis ------------------------------------------------ - process(last_APL_RUN_OUT, this_APL_RUN_OUT, APL_RUN_OUT_fallen) - variable tmp : std_logic; - begin - next_APL_RUN_OUT_fallen <= APL_RUN_OUT_fallen; - next_APL_SEND_IN(0) <= '0'; - for i in 1 to OUTPUT_PORTS loop - if last_APL_RUN_OUT(i)= '1' and this_APL_RUN_OUT(i) = '0' then - next_APL_RUN_OUT_fallen(i) <= '1'; - end if; - end loop; - tmp := '1'; - for i in 1 to OUTPUT_PORTS loop - tmp := tmp and APL_RUN_OUT_fallen(i); - end loop; - if tmp = '1' then - next_APL_SEND_IN(0) <= '1'; - next_APL_RUN_OUT_fallen <= (others => '0'); - end if; - end process; - - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - this_APL_RUN_OUT <= (others => '0'); - last_APL_RUN_OUT <= (others => '0'); - APL_RUN_OUT_fallen <= (others => '0'); - APL_SEND_IN(0) <= '0'; - else - this_APL_RUN_OUT <= APL_RUN_OUT; - last_APL_RUN_OUT <= this_APL_RUN_OUT; - APL_RUN_OUT_fallen <= next_APL_RUN_OUT_fallen; - APL_SEND_IN(0) <= next_APL_SEND_IN(0); - end if; - end if; - end process; - - -end architecture; - - - diff --git a/oldfiles/trb_net_fifo_arch.vhd b/oldfiles/trb_net_fifo_arch.vhd deleted file mode 100644 index 91fb10d..0000000 --- a/oldfiles/trb_net_fifo_arch.vhd +++ /dev/null @@ -1,197 +0,0 @@ --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo - --- taken example from xapp256, but rewritten most of the parts --- output fully synchonized with a "look-ahead" logic - -library ieee; - -use ieee.std_logic_1164.all; -USE ieee.std_logic_signed.ALL; -USE IEEE.numeric_std.ALL; -use work.trb_net_std.all; - - -architecture arch_trb_net_fifo of trb_net_fifo is - component trb_net16_bram_fifo is - port (clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - fifo_gsr_in: IN std_logic; - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifocount_out: OUT std_logic_vector(3 downto 0)); - end component; - - component shift_lut_x16 - generic ( - ADDRESS_WIDTH : integer := 0 - ); - port ( - D : in std_logic; - CE : in std_logic; - CLK : in std_logic; - A : in std_logic_vector (ADDRESS_WIDTH+3 downto 0); - Q : out std_logic - ); - end component; - - signal current_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0); - signal next_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0); - signal real_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0); - signal current_DOUT : std_logic_vector(WIDTH -1 downto 0); - signal next_DOUT : std_logic_vector(WIDTH -1 downto 0); - - signal current_FULL, next_FULL : std_logic; - signal current_EMPTY, next_EMPTY : std_logic; - signal do_shift, do_shift_internal : std_logic; - signal fifocount : std_logic_vector(3 downto 0); - -begin - - gen_shiftreg : if DEPTH /= 8 or WIDTH /= 18 or FORCE_LUT = 1 generate - - FULL_OUT <= current_FULL; - EMPTY_OUT <= current_EMPTY; - do_shift <= do_shift_internal and CLK_EN; - - - -- generate the shift registers - - inst_SRLC256E_MACRO : for i in 0 to (WIDTH - 1) generate - U1 : shift_lut_x16 - generic map ( - ADDRESS_WIDTH => DEPTH - 3 - ) - port map ( - D => DATA_IN(i), - CE => do_shift, - CLK => CLK, - A => real_ADDRESS_SRL(DEPTH downto 0), - Q => next_DOUT(i)); - end generate; - - reg_counter: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_ADDRESS_SRL <= (others => '0'); - elsif CLK_EN = '1' then - current_ADDRESS_SRL <= next_ADDRESS_SRL; - else - current_ADDRESS_SRL <= current_ADDRESS_SRL; - end if; - end if; - end process; - - -- adress logic - comb_counter: process(WRITE_ENABLE_IN, READ_ENABLE_IN, current_ADDRESS_SRL, - current_EMPTY, current_FULL) - begin - do_shift_internal <= WRITE_ENABLE_IN and not current_FULL; - next_ADDRESS_SRL <= current_ADDRESS_SRL; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; - - -- no activity - if WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '0' then - next_ADDRESS_SRL <= current_ADDRESS_SRL; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; - -- read from FIFO - elsif WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '1' then - if current_EMPTY = '0' then - next_ADDRESS_SRL <= current_ADDRESS_SRL - 1; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 2; - end if; - -- write into FIFO - elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '0' then - if current_FULL = '0' then - next_ADDRESS_SRL <= current_ADDRESS_SRL + 1; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; - end if; - -- read and write can be done in all cases - elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '1' then - next_ADDRESS_SRL <= current_ADDRESS_SRL; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 2; - end if; - end process; - - - -- registered read from FIFO - reg_output: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_DOUT <= (others => '0'); - elsif CLK_EN = '1' then - if current_EMPTY = '1' or real_ADDRESS_SRL(DEPTH+1) = '1' then - current_DOUT <= DATA_IN; - else - current_DOUT <= next_DOUT; - end if; - end if; - end if; - end process; - - -- Comparator Block - next_FULL <= next_ADDRESS_SRL(DEPTH+1); - -- Empty flag is generated when reading from the last location - next_EMPTY <= '1' when (next_ADDRESS_SRL(DEPTH+1 downto 0) = 0) else '0'; - - reg_empty: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_EMPTY <= '1'; - current_FULL <= '0'; - elsif CLK_EN = '1' then - current_EMPTY <= next_EMPTY; - current_FULL <= next_FULL; - else - current_EMPTY <= current_EMPTY; - current_FULL <= current_FULL; - end if; - end if; - end process; - - FULL_OUT <= current_FULL; - EMPTY_OUT <= current_EMPTY; - DATA_OUT <= current_DOUT; - - - -- generate the real depth which is at least 3 - -- 0 -> 2 - -- 1 -> 4 - -- 2 -> 8 - -- 3 -> 16 - CHECK_DEPTH1: if DEPTH>=3 generate - DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); - end generate; - CHECK_DEPTH2: if DEPTH<3 generate - DEPTH_OUT <= x"03"; - end generate; - end generate; - - - - gen_BRAM : if (DEPTH = 8 and WIDTH = 18) and FORCE_LUT = 0 generate - bram_fifo:trb_net16_bram_fifo - port map ( - clock_in => CLK, - read_enable_in => READ_ENABLE_IN, - write_enable_in => WRITE_ENABLE_IN, - write_data_in => DATA_IN, - fifo_gsr_in => RESET, - read_data_out => DATA_OUT, - full_out => FULL_OUT, - empty_out => EMPTY_OUT, - fifocount_out => fifocount - ); - - DEPTH_OUT <= (others => '1'); - end generate; - - -end arch_trb_net_fifo; - - diff --git a/oldfiles/trb_net_ibuf.vhd b/oldfiles/trb_net_ibuf.vhd deleted file mode 100644 index 9105560..0000000 --- a/oldfiles/trb_net_ibuf.vhd +++ /dev/null @@ -1,299 +0,0 @@ --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_ibuf is - - generic (DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1) - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Internal direction port - INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Status and control port - STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0); - STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0) - ); -end trb_net_ibuf; - -architecture trb_net_ibuf_arch of trb_net_ibuf is - -component trb_net_fifo is - - generic (WIDTH : integer := 8; -- FIFO word width - DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1) - - port (CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - -end component; - - component trb_net_sbuf is - - generic (DATA_WIDTH : integer := 56; - VERSION: integer := 0); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - -- Port to synchronous output. - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - -- Status and control port - STAT_BUFFER: out STD_LOGIC - ); - end component; - -signal fifo_data_in : std_logic_vector(50 downto 0); -signal fifo_data_out : std_logic_vector(50 downto 0); -signal fifo_write, fifo_read : std_logic; -signal fifo_full, fifo_empty : std_logic; -signal fifo_depth : std_logic_vector(7 downto 0); - -signal next_read_out, reg_read_out : std_logic; - -signal got_ack_internal, reg_ack_internal : std_logic; --should be raised for 1 cycle when ack - --arrived -signal is_locked, got_locked,release_locked : std_logic; -signal got_eob_out, reg_eob_out: std_logic; -signal sbuf_free, comb_next_read: std_logic; -signal tmp_INT_DATAREADY_OUT: std_logic; -signal tmp_INT_DATA_OUT: std_logic_vector(50 downto 0); -signal current_last_header, next_last_header : std_logic_vector(50 downto 0); - -type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR); -signal current_error_state, next_error_state : ERROR_STATE; - -signal next_rec_buffer_size_out, current_rec_buffer_size_out - : std_logic_vector(3 downto 0); -- buffer size control - - begin - - FIFO: trb_net_fifo - generic map ( - WIDTH => 51, - DEPTH => DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_data_in, - WRITE_ENABLE_IN => fifo_write, - DATA_OUT => fifo_data_out, - READ_ENABLE_IN => fifo_read, - FULL_OUT => fifo_full, - EMPTY_OUT => fifo_empty, - DEPTH_OUT => fifo_depth - ); - - fifo_data_in <= MED_DATA_IN; - --- this process controls the writing of the media into the fifo - FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN, - fifo_full, is_locked, current_rec_buffer_size_out, - current_error_state, reg_read_out) - begin -- process - got_ack_internal <= '0'; - next_read_out <= '0'; - fifo_write <= '0'; - next_rec_buffer_size_out <= current_rec_buffer_size_out; - next_error_state <= current_error_state; - - if MED_DATAREADY_IN = '1' and reg_read_out= '1' then - if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then - -- BUGBUG: this causes trouble if the IBUF is full -> ack sent even if buffer overflow - got_ack_internal <= '1'; - if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then - next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION); - end if; - -- elsif fifo_full = '0' and is_locked = '0' then - elsif fifo_full = '0' then -- still ACKs may come even when locked - fifo_write <= '1'; - next_read_out <= '1'; - elsif fifo_full = '1' then - next_error_state <= GOT_OVERFLOW_ERROR; - elsif is_locked = '1' then - next_error_state <= GOT_LOCKED_ERROR; - end if; -- end TYPE - end if; -- end MED_DATAREADY_IN - if fifo_full = '0' then -- and is_locked = '0' then - next_read_out <= '1'; - end if; - end process; - - MED_READ_OUT <= reg_read_out; - - reg_buffer: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_rec_buffer_size_out <= (others => '0'); - reg_ack_internal <= '0'; - reg_read_out <= '0'; - current_error_state <= IDLE; - elsif CLK_EN = '1' then - current_rec_buffer_size_out <= next_rec_buffer_size_out; - reg_ack_internal <= got_ack_internal; - reg_read_out <= next_read_out; - current_error_state <= next_error_state; - else - current_rec_buffer_size_out <= current_rec_buffer_size_out; - reg_ack_internal <= reg_ack_internal; - reg_read_out <= reg_read_out; - current_error_state <= current_error_state; - end if; - end if; - end process; - - - - SBUF: trb_net_sbuf - generic map (DATA_WIDTH => 51, Version => 0) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => tmp_INT_DATAREADY_OUT, - COMB_next_READ_OUT => comb_next_read, - COMB_READ_IN => '1', - COMB_DATA_IN => tmp_INT_DATA_OUT, - SYN_DATAREADY_OUT => INT_DATAREADY_OUT, - SYN_DATA_OUT => INT_DATA_OUT, - SYN_READ_IN => INT_READ_IN - ); - - sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed - --- this process controls what will be forwarded to the internal point - DATA_OUT : process (INT_HEADER_IN, fifo_data_out, - current_last_header, INT_READ_IN, - release_locked, is_locked, sbuf_free, fifo_empty) - begin - -- tmp_INT_DATA_OUT <= (others => '1'); - tmp_INT_DATA_OUT <= fifo_data_out; - tmp_INT_DATAREADY_OUT <= '0'; - got_eob_out <= '0'; - fifo_read <= '0'; - got_locked <= is_locked; - next_last_header <= current_last_header; - - if fifo_empty = '0' then - if sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_DAT then - -- next data word can be registered - tmp_INT_DATAREADY_OUT <= '1'; - fifo_read <= '1'; - elsif sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_TRM then - got_eob_out <= '1'; --exactly when buffer is killed - tmp_INT_DATAREADY_OUT <= '1'; - if release_locked = '0' then - got_locked <= '1'; - end if; - fifo_read <= '1'; - elsif sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_HDR then - next_last_header <= fifo_data_out; - tmp_INT_DATAREADY_OUT <= '1'; - fifo_read <= '1'; - elsif fifo_data_out(TYPE_POSITION) = TYPE_EOB then - fifo_read <= '1'; - got_eob_out <= '1'; - tmp_INT_DATAREADY_OUT <= '0'; - -- this should happen only one CLK cycle - end if; - else - tmp_INT_DATAREADY_OUT <= '0'; - end if; - end process; - ---BUGBUG HDR retransmit needed - -release_locked <= CTRL_LOCKED(0); -STAT_LOCKED(0) <= is_locked; -STAT_LOCKED(15 downto 1) <= (others => '0'); - -reg_locked: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - is_locked <= '0'; - reg_eob_out <= '0'; - current_last_header <= (others => '0'); - elsif CLK_EN = '1' then - if release_locked = '1' then - is_locked <= '0'; - else - is_locked <= got_locked; - end if; - reg_eob_out <= got_eob_out; - current_last_header <= next_last_header; - else - is_locked <= is_locked; - reg_eob_out <= reg_eob_out; - current_last_header <= current_last_header; - end if; - end if; - end process; - - - --- make STAT_BUFFER - STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0)-1); --divide by 2, since 2 - --buffers have to be stored - STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out; - STAT_BUFFER(8) <= reg_eob_out; - STAT_BUFFER(9) <= reg_ack_internal; - - MAKE_ERROR_BITS : process(current_error_state) - begin - if current_error_state = IDLE then - STAT_BUFFER(11 downto 10) <= "00"; - elsif current_error_state = GOT_OVERFLOW_ERROR then - STAT_BUFFER(11 downto 10) <= "01"; - elsif current_error_state = GOT_LOCKED_ERROR then - STAT_BUFFER(11 downto 10) <= "10"; - else - STAT_BUFFER(11 downto 10) <= "11"; - end if; - end process; - - STAT_BUFFER(31 downto 12) <= (others => '0'); - -end trb_net_ibuf_arch; - diff --git a/oldfiles/trb_net_io_multiplexer.vhd b/oldfiles/trb_net_io_multiplexer.vhd deleted file mode 100644 index ab0bdcb..0000000 --- a/oldfiles/trb_net_io_multiplexer.vhd +++ /dev/null @@ -1,248 +0,0 @@ --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_io_multiplexer is - --- generic (BUS_WIDTH : integer := 56; --- MULT_WIDTH : integer := 5); - generic (BUS_WIDTH : integer := 16; - MULT_WIDTH : integer := 1); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - -- highest bits are mult. - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - MED_READ_IN: in STD_LOGIC; - - -- Internal direction port - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); -end trb_net_io_multiplexer; - -architecture trb_net_io_multiplexer_arch of trb_net_io_multiplexer is - - component trb_net_pattern_gen is - - generic (MULT_WIDTH : integer := 3); - - port( - INPUT_IN : in STD_LOGIC_VECTOR (MULT_WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0) - ); - end component; - - component trb_net16_sbuf is - generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); - end component; - - component trb_net_priority_arbiter is - - generic (WIDTH : integer := 16); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - - ENABLE : in std_logic; - CTRL: in STD_LOGIC_VECTOR (31 downto 0) - ); - end component; - - signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0); - signal next_demux_dr, next_demux_dr_tmp: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0); --- signal demux_read: STD_LOGIC; -- buffer is read out and killed - signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC; --- signal sbuf_stat: STD_LOGIC_VECTOR (2*(2**MULT_WIDTH)-1 downto 0); - - signal tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0); - signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MULT_WIDTH)-1 downto 0); - signal mux_read, mux_enable, mux_next_READ: STD_LOGIC; - signal current_mux_buffer: STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - - - - begin - - -------------------------------------------------------------------------------- --- DEMUX ------------------------------------------------------------------------------- - -- the simpler part is the demux - - G1: for i in 0 to 2**MULT_WIDTH-1 generate - DEMUX_SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => BUS_WIDTH-MULT_WIDTH, VERSION => 0) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_demux_dr(i), - COMB_next_READ_OUT => demux_next_READ(i), - COMB_READ_IN => current_demux_READ(i), - COMB_DATA_IN => MED_DATA_IN (BUS_WIDTH-MULT_WIDTH-1 downto 0), - SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i), - SYN_DATA_OUT => INT_DATA_OUT ((BUS_WIDTH-MULT_WIDTH)*(i+1)-1 downto (BUS_WIDTH-MULT_WIDTH)*(i)), - SYN_READ_IN => INT_READ_IN(i) - ); - end generate; - - STAT(2 downto 0) <= MED_DATA_IN(50 downto 48); - - MED_READ_OUT <= current_MED_READ_OUT; - - comb_demux : process (next_demux_dr_tmp, demux_next_READ, INT_READ_IN, - MED_DATAREADY_IN, current_MED_READ_OUT) - begin -- process - next_demux_dr <= (others => '0'); - current_demux_READ <= (others => '0'); - -- generate the READ_OUT - next_MED_READ_OUT <= and_all(demux_next_READ or INT_READ_IN); - -- (follow instruction on sbuf) - - current_demux_READ <= (others => '0'); - if current_MED_READ_OUT = '1' then - current_demux_READ <= (others => '1'); - end if; - if current_MED_READ_OUT = '1' and MED_DATAREADY_IN = '1' then - next_demux_dr <= next_demux_dr_tmp; --enable DR on the sbufs - end if; - end process; - --- define next DRx - DEFDR: trb_net_pattern_gen - generic map (MULT_WIDTH => MULT_WIDTH) - port map ( - INPUT_IN => MED_DATA_IN(BUS_WIDTH-1 downto (BUS_WIDTH-MULT_WIDTH)), - RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case - ); - - sync_demux : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_MED_READ_OUT <= '0'; - elsif CLK_EN = '1' then - current_MED_READ_OUT <= next_MED_READ_OUT; - else - current_MED_READ_OUT <= current_MED_READ_OUT; - end if; - end if; - end process; - - -------------------------------------------------------------------------------- --- MUX part with arbitration scheme -------------------------------------------------------------------------------- -ARBITER: trb_net_priority_arbiter - generic map (WIDTH => 2**MULT_WIDTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - INPUT_IN => INT_DATAREADY_IN, - RESULT_OUT => tmp_INT_READ_OUT, - ENABLE => mux_enable, - CTRL => CTRL - ); - --- process (tmp_tmp_INT_READ_OUT, mux_enable) --- begin --- if mux_enable = '1' then --- tmp_INT_READ_OUT <= tmp_tmp_INT_READ_OUT; --- else --- tmp_INT_READ_OUT <= (others => '0'); --- end if; --- end process; - --- <= so I have to gate it once more -INT_READ_OUT <= tmp_INT_READ_OUT; - - - - MUX_SBUF: trb_net_sbuf - generic map (DATA_WIDTH => BUS_WIDTH, VERSION => 0) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => mux_read, - COMB_next_READ_OUT => mux_next_READ, - COMB_READ_IN => '1', - COMB_DATA_IN => current_mux_buffer, - SYN_DATAREADY_OUT => MED_DATAREADY_OUT, - SYN_DATA_OUT => MED_DATA_OUT, - SYN_READ_IN => MED_READ_IN - ); - -process (tmp_INT_READ_OUT, INT_DATA_IN) - begin - current_mux_buffer <= (others => '0'); - for i in 0 to 2**MULT_WIDTH-1 loop - if tmp_INT_READ_OUT(i) = '1' then - current_mux_buffer(BUS_WIDTH-MULT_WIDTH-1 downto 0) - <= INT_DATA_IN((BUS_WIDTH-MULT_WIDTH)*(i+1)-1 downto (BUS_WIDTH-MULT_WIDTH)*(i)); - current_mux_buffer(BUS_WIDTH-1 downto BUS_WIDTH-MULT_WIDTH) <= conv_std_logic_vector(i, MULT_WIDTH); - end if; - end loop; - end process; - - mux_enable <= (mux_next_READ); -- or MED_READ_IN - mux_read <= or_all(tmp_INT_READ_OUT and INT_DATAREADY_IN); - -end trb_net_io_multiplexer_arch; - diff --git a/oldfiles/trb_net_iobuf.vhd b/oldfiles/trb_net_iobuf.vhd deleted file mode 100644 index bf2f95c..0000000 --- a/oldfiles/trb_net_iobuf.vhd +++ /dev/null @@ -1,419 +0,0 @@ --- main working horse for the trbnet --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIOBUF - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_iobuf is - - generic ( - SWITCH_OFF_BUFFER_CHECK : integer := 0; - --switching off erroneous output buffer counter. MUST ONLY be - --used for short transfers!!!! - INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3); -- or the replyibuf - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading - - MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading - - MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0) - ); -END trb_net_iobuf; - -architecture trb_net_iobuf_arch of trb_net_iobuf is - - component trb_net_ibuf is - - generic (DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1) - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Internal direction port - INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Status and control port - STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0); - STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0) - ); - END component; - - component trb_net_term_ibuf is - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Internal direction port - INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Status and control port - STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0); - STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0) - ); - END component; - - component trb_net_obuf is - generic ( - DATA_COUNT_WIDTH : integer := 4; - SWITCH_OFF_BUFFER_CHECK : integer := 0 - --switching off erroneous output buffer counter. MUST ONLY be - --used for short transfers!!!! - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; - -- Internal direction port - INT_DATAREADY_IN: in STD_LOGIC; - INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; - -- Status and control port - STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0); - STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); - CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0) - ); - END component; - - -- internal signals for the INITIBUF - signal INITIBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed! - signal INITIBUF_stat_locked, INITIBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0); - signal INITIBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0); - - -- internal signals for the REPLYIBUF - signal REPLYIBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed! - signal REPLYIBUF_stat_locked, REPLYIBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0); - signal REPLYIBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0); - - -- internal signals for the INITOBUF - signal INITOBUF_stat_locked, INITOBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0); - signal INITOBUF_stat_buffer, INITOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0); - - -- internal signals for the REPLYOBUF - signal REPLYOBUF_stat_locked, REPLYOBUF_ctrl_locked: STD_LOGIC_VECTOR (15 downto 0); - signal REPLYOBUF_stat_buffer, REPLYOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0); - --- locking control - signal INIT_IS_LOCKED, REPLY_IS_LOCKED: STD_LOGIC; - signal next_INIT_IS_LOCKED, next_REPLY_IS_LOCKED: STD_LOGIC; - - begin - - GEN_IBUF: if INIT_DEPTH>0 generate - - INITIBUF : trb_net_ibuf - generic map ( - DEPTH => INIT_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_DATA_IN => MED_INIT_DATA_IN, - MED_READ_OUT => MED_INIT_READ_OUT, - MED_ERROR_IN => MED_INIT_ERROR_IN, - INT_HEADER_IN => '0', - INT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_DATA_OUT => INT_INIT_DATA_OUT, - INT_READ_IN => INT_INIT_READ_IN, - INT_ERROR_OUT => INITIBUF_error, - STAT_LOCKED(15 downto 0) => INITIBUF_stat_locked, - CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked, - STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer - ); - - REPLYIBUF : trb_net_ibuf - generic map ( - DEPTH => REPLY_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_DATA_IN => MED_REPLY_DATA_IN, - MED_READ_OUT => MED_REPLY_READ_OUT, - MED_ERROR_IN => MED_REPLY_ERROR_IN, - INT_HEADER_IN => INT_REPLY_HEADER_IN, - INT_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_DATA_OUT => INT_REPLY_DATA_OUT, - INT_READ_IN => INT_REPLY_READ_IN, - INT_ERROR_OUT => REPLYIBUF_error, - STAT_LOCKED(15 downto 0) => REPLYIBUF_stat_locked, - CTRL_LOCKED(15 downto 0) => REPLYIBUF_ctrl_locked, - STAT_BUFFER(31 downto 0) => REPLYIBUF_stat_buffer - ); - - end generate; - - GEN_TERM_IBUF: if INIT_DEPTH=0 generate - - INITIBUF : trb_net_term_ibuf - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_DATA_IN => MED_INIT_DATA_IN, - MED_READ_OUT => MED_INIT_READ_OUT, - MED_ERROR_IN => MED_INIT_ERROR_IN, - INT_HEADER_IN => '0', - INT_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_DATA_OUT => INT_INIT_DATA_OUT, - INT_READ_IN => INT_INIT_READ_IN, - INT_ERROR_OUT => INITIBUF_error, - STAT_LOCKED(15 downto 0) => INITIBUF_stat_locked, - CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked, - STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer - ); - - REPLYIBUF : trb_net_term_ibuf - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_DATA_IN => MED_REPLY_DATA_IN, - MED_READ_OUT => MED_REPLY_READ_OUT, - MED_ERROR_IN => MED_REPLY_ERROR_IN, - INT_HEADER_IN => INT_REPLY_HEADER_IN, - INT_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_DATA_OUT => INT_REPLY_DATA_OUT, - INT_READ_IN => INT_REPLY_READ_IN, - INT_ERROR_OUT => REPLYIBUF_error, - STAT_LOCKED(15 downto 0) => REPLYIBUF_stat_locked, - CTRL_LOCKED(15 downto 0) => REPLYIBUF_ctrl_locked, - STAT_BUFFER(31 downto 0) => REPLYIBUF_stat_buffer - ); - - end generate; - - INITOBUF : trb_net_obuf - generic map ( - DATA_COUNT_WIDTH => 16, - SWITCH_OFF_BUFFER_CHECK => SWITCH_OFF_BUFFER_CHECK - --switching off erroneous output buffer counter. MUST ONLY be - --used for short transfers!!!! - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, - MED_DATA_OUT => MED_INIT_DATA_OUT, - MED_READ_IN => MED_INIT_READ_IN, - INT_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_DATA_IN => INT_INIT_DATA_IN, - INT_READ_OUT => INT_INIT_READ_OUT, - STAT_LOCKED(15 downto 0) => INITOBUF_stat_locked, - CTRL_LOCKED(15 downto 0) => INITOBUF_ctrl_locked, - STAT_BUFFER(31 downto 0) => INITOBUF_stat_buffer, - CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer - ); - - REPLYOBUF : trb_net_obuf - generic map ( - DATA_COUNT_WIDTH => 16, - SWITCH_OFF_BUFFER_CHECK => SWITCH_OFF_BUFFER_CHECK - --switching off erroneous output buffer counter. MUST ONLY be - --used for short transfers!!!! - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - MED_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, - MED_DATA_OUT => MED_REPLY_DATA_OUT, - MED_READ_IN => MED_REPLY_READ_IN, - INT_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_DATA_IN => INT_REPLY_DATA_IN, - INT_READ_OUT => INT_REPLY_READ_OUT, - STAT_LOCKED(15 downto 0) => REPLYOBUF_stat_locked, - CTRL_LOCKED(15 downto 0) => REPLYOBUF_ctrl_locked, - STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer, - CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer - ); - --- build the registers according to the wiki page - STAT_INIT_BUFFER(11 downto 0) <= INITIBUF_stat_buffer(11 downto 0); - STAT_INIT_BUFFER(15 downto 14) <= INITOBUF_stat_buffer(1 downto 0); - STAT_INIT_BUFFER(31 downto 16) <= INITOBUF_stat_buffer(31 downto 16); - STAT_REPLY_BUFFER(11 downto 0) <= REPLYIBUF_stat_buffer(11 downto 0); - STAT_REPLY_BUFFER(15 downto 14) <= REPLYOBUF_stat_buffer(1 downto 0); - STAT_REPLY_BUFFER(31 downto 16) <= REPLYOBUF_stat_buffer(31 downto 16); - --- build the CTRL register of the OBUFs - INITOBUF_ctrl_buffer(9 downto 0) <= INITIBUF_stat_buffer(9 downto 0); - INITOBUF_ctrl_buffer(31 downto 10) <= (others => '0'); - REPLYOBUF_ctrl_buffer(9 downto 0) <= REPLYIBUF_stat_buffer(9 downto 0); - REPLYOBUF_ctrl_buffer(31 downto 10) <= (others => '0'); - - STAT_LOCKED(0) <= INIT_IS_LOCKED; - STAT_LOCKED(1) <= REPLY_IS_LOCKED; - STAT_LOCKED(31 downto 2) <= (others => '0'); - - REPLYOBUF_ctrl_locked(15 downto 2) <= (others => '0'); - REPLYIBUF_ctrl_locked(15 downto 2) <= (others => '0'); - INITOBUF_ctrl_locked(15 downto 2) <= (others => '0'); - INITIBUF_ctrl_locked(15 downto 2) <= (others => '0'); - - -- comb part of the locking control -comb_locked : process (INIT_IS_LOCKED, REPLY_IS_LOCKED, INITIBUF_stat_locked, - REPLYOBUF_stat_locked, REPLYIBUF_stat_locked, - INITOBUF_stat_locked, CTRL_LOCKED) - - begin -- process - next_INIT_IS_LOCKED <= INIT_IS_LOCKED; - next_REPLY_IS_LOCKED <= REPLY_IS_LOCKED; - REPLYOBUF_ctrl_locked(1 downto 0) <= (others => '0'); - REPLYIBUF_ctrl_locked(1 downto 0) <= (others => '0'); - INITOBUF_ctrl_locked(1 downto 0) <= (others => '0'); - INITIBUF_ctrl_locked(1 downto 0) <= (others => '0'); - - if REPLY_IS_LOCKED = '1' then - -- listen to INITOBUF - if INITOBUF_stat_locked(0) = '1' or CTRL_LOCKED(1) = '1' then - next_REPLY_IS_LOCKED <= '0'; - REPLYIBUF_ctrl_locked(0) <= '1'; - else - next_REPLY_IS_LOCKED <= '1'; - end if; - else - -- listen to REPLYIBUF itself - if REPLYIBUF_stat_locked(0) = '1' then - next_REPLY_IS_LOCKED <= '1'; - INITOBUF_ctrl_locked(0) <= '1'; - else - next_REPLY_IS_LOCKED <= '0'; - end if; - end if; - - if INIT_IS_LOCKED = '1' then - -- listen to REPLYOBUF - if REPLYOBUF_stat_locked(0) = '1' or CTRL_LOCKED(0) = '1' then - next_INIT_IS_LOCKED <= '0'; - INITIBUF_ctrl_locked(0) <= '1'; - else - next_INIT_IS_LOCKED <= '1'; - end if; - else - -- listen to INITIBUF itself - if INITIBUF_stat_locked(0) = '1' then - next_INIT_IS_LOCKED <= '1'; - REPLYOBUF_ctrl_locked(0) <= '1'; - else - next_INIT_IS_LOCKED <= '0'; - - end if; - end if; - - end process; - - reg_locked: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - INIT_IS_LOCKED <= '0'; - REPLY_IS_LOCKED <= '1'; - elsif CLK_EN = '1' then - INIT_IS_LOCKED <= next_INIT_IS_LOCKED; - REPLY_IS_LOCKED <= next_REPLY_IS_LOCKED; - else - INIT_IS_LOCKED <= INIT_IS_LOCKED; - REPLY_IS_LOCKED <= REPLY_IS_LOCKED; - end if; - end if; - end process; - - - - -end trb_net_iobuf_arch; - diff --git a/oldfiles/trb_net_med_13bit_slow.vhd b/oldfiles/trb_net_med_13bit_slow.vhd deleted file mode 100755 index 23a09e0..0000000 --- a/oldfiles/trb_net_med_13bit_slow.vhd +++ /dev/null @@ -1,563 +0,0 @@ ---This entity provides data transfer (64bit) via a smaller (16bit) Bus ---with three bits for debugging (13bit data + 3bit control) ---first 56bit via Bus are for dataword, transmitted Bits 64 downto 56 Bits ---are for debugging - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.trb_net_std.all; - -entity trb_net_med_13bit_slow is -generic( - TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only! - ); - - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Internal direction port (MII) - -- do not change this interface!!! - -- 1st part: from the medium to the internal logic (trbnet) - INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media - --and ready to be read out (the IOBUF MUST read) - INT_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- 2nd part: from the internal logic (trbnet) to the medium - INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media - INT_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; -- offered word is read - INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- (end do not change this interface!!!) - - - -- Media direction port - -- in this case for the cable => 32 lines in total - MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word - --(incl. debugging errorbits) - MED_TRANSMISSION_CLK_OUT: out STD_LOGIC; - MED_CARRIER_OUT: out STD_LOGIC; - MED_PARITY_OUT: out STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (12 downto 0); -- Data word - MED_TRANSMISSION_CLK_IN: in STD_LOGIC; - MED_CARRIER_IN: in STD_LOGIC; - MED_PARITY_IN: in STD_LOGIC; - - -- Status and control port => this never can hurt - STAT: out STD_LOGIC_VECTOR (31 downto 0); - --STAT(0): Busy reading from media - --STAT(1): Busy writing to media - --STAT(31 downto 28): packets_in (mod 16) - --STAT(27 downto 24): packets_out (mod 16) - --STAT(11 downto 8): INT2MED state - --STAT(15 downto 12): MED2INT state - - CTRL: in STD_LOGIC_VECTOR (31 downto 0) - --CTRL(24..31) -> lvds-data(63 downto 56) via lvds - --once for each packet - - ); -end trb_net_med_13bit_slow; - -architecture trb_net_med_13bit_slow_arch of trb_net_med_13bit_slow is - signal INT2MED_state, next_INT2MED_state : std_logic_vector (3 downto 0); - - type MED2INT_STATE_t is (IDLE, RECV2, RECV3, RECV4, RECV5); - signal MED2INT_state, next_MED2INT_state: MED2INT_STATE_t; - - signal DAT_MED2INT, next_DAT_MED2INT :std_logic_vector(51 downto 0); - signal buf_INT_DATA_IN, next_buf_INT_DATA_IN :std_logic_vector(55 downto 0); - - signal next_INT_DATA_OUT, buf_INT_DATA_OUT: std_logic_vector(55 downto 0); - signal next_buf_MED_DATA_OUT, buf_MED_DATA_OUT: std_logic_vector(12 downto 0); - signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT: std_logic; - signal next_buf_INT_READ_OUT, buf_INT_READ_OUT: std_logic; - - signal buf_MED_TRANSMISSION_CLK_OUT: std_logic; - signal buf_MED_CARRIER_OUT, next_MED_CARRIER_OUT: STD_LOGIC; - signal buf_MED_PARITY_OUT, next_MED_PARITY_OUT: STD_LOGIC; - signal my_error,next_my_error : std_logic_vector(2 downto 0); - signal fatal_error, media_not_connected : std_logic; - signal next_media_not_connected : std_logic; - signal transmission_clk_Counter : std_logic_vector(4 downto 0); - signal next_transmission_clk_Counter : std_logic_vector(4 downto 0); - signal next_TRANSMISSION_CLK: std_logic; - signal buf_CTRL, next_STAT, buf_STAT : std_logic_vector(31 downto 0); - signal next_RECV_STAT, RECV_STAT : std_logic_vector(8 downto 0); - - signal last_TRCLK, this_TRCLK: std_logic; - signal CLK_counter,next_CLK_counter: std_logic_vector(7 downto 0); - - signal packets_in_counter, next_packets_in_counter: std_logic_vector(7 downto 0); - signal packets_in_compl_counter, next_packets_in_compl_counter: std_logic_vector(3 downto 0); - signal packets_out_counter, next_packets_out_counter: std_logic_vector(3 downto 0); - - signal last_MED_TRANSMISSION_CLK_IN : std_logic; - signal reg_MED_DATA_IN : std_logic_vector(12 downto 0); - signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic; - signal reg_MED_PARITY_IN : std_logic; - signal med2int_state_sig :std_logic_vector(2 downto 0); - -begin -INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; -INT_DATA_OUT <= buf_INT_DATA_OUT(55 downto 0); -INT_ERROR_OUT <= my_error; -INT_READ_OUT <= buf_INT_READ_OUT; -STAT <= buf_STAT; - -MED_DATA_OUT(12 downto 0) <= buf_MED_DATA_OUT; -MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; -MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; -MED_PARITY_OUT <= buf_MED_PARITY_OUT; - - ---TODO: --------------------------------- -fatal_error <= '0'; - - - ---Status word --------------------------------- -gen_STAT_WORD: process(MED2INT_state,INT2MED_state,buf_INT_DATAREADY_OUT,RECV_STAT,buf_STAT) - begin - next_STAT <= (others => '0'); - if MED2INT_state = IDLE then - next_STAT(0) <= '0'; - else - next_STAT(0) <= '1'; - end if; - if INT2MED_state = 0 then - next_STAT(1) <= '0'; - else - next_STAT(1) <= '1'; - end if; - next_STAT(11 downto 8) <= INT2MED_state; - --next_STAT(15 downto 12) <= MED2INT_state; - next_STAT(16) <= media_not_connected; - next_STAT(31 downto 24) <= packets_in_counter; - --next_STAT(27 downto 24) <= packets_in_compl_counter; - if buf_INT_DATAREADY_OUT = '1' then - next_STAT(24 downto 16) <= RECV_STAT(8 downto 0); - else - next_STAT(24 downto 16) <= buf_STAT(24 downto 16); - end if; - end process; - -STAT_reg: process (CLK,RESET) - begin - if RESET = '1' then - buf_STAT <= (others => '0'); - elsif rising_edge(CLK) then - buf_STAT <= next_STAT; - else - buf_STAT <= buf_STAT; - end if; - end process; - - ---CTRL register --------------------------------- -CTRL_reg: process (CLK,RESET) - begin - if RESET = '1' then - buf_CTRL <= (others => '0'); - elsif rising_edge(CLK) then - buf_CTRL <= CTRL; - --buf_CTRL(31 downto 24) <= packets_in_counter; - --buf_CTRL(27 downto 24) <= packets_in_compl_counter; - else - buf_CTRL <= buf_CTRL; - end if; - end process; - - - ---My error bits --------------------------------- -gen_my_error: process(media_not_connected,fatal_error) - begin - if media_not_connected = '1' then - next_my_error <= "100"; - elsif fatal_error = '1' then - next_my_error <= "011"; - else - next_my_error <= "000"; - end if; - end process; - - -reg_my_error: process(CLK,RESET) - begin - if RESET = '1' then - my_error <= "000"; - elsif rising_edge(CLK) then - my_error <= next_my_error; - else - my_error <= my_error; - end if; - end process; - - ---Transmission clock generator --------------------------------- -trans_clk_counter: process (transmission_clk_Counter, buf_MED_TRANSMISSION_CLK_OUT) - begin - if transmission_clk_Counter = (TRANSMISSION_CLOCK_DIVIDER/2) - 1 then - next_transmission_clk_Counter <= (others => '0'); - next_TRANSMISSION_CLK <= not buf_MED_TRANSMISSION_CLK_OUT; - else - next_transmission_clk_Counter <= transmission_clk_Counter + 1; - next_TRANSMISSION_CLK <= buf_MED_TRANSMISSION_CLK_OUT; - end if; - end process; - - -trans_clk_counter_reg: process (CLK,RESET) - begin - if RESET = '1' then - transmission_clk_Counter <= (others => '0'); - buf_MED_TRANSMISSION_CLK_OUT <= '0'; - elsif rising_edge(CLK) then - transmission_clk_Counter <= next_transmission_clk_Counter; - buf_MED_TRANSMISSION_CLK_OUT <= next_TRANSMISSION_CLK; - else - transmission_clk_Counter <= transmission_clk_Counter; - buf_MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; - end if; - end process; - - - ---Transmission Clock detection --------------------------------- -trans_clk_reg: process (RESET,CLK) - begin - if RESET = '1' then - last_TRCLK <= '0'; - this_TRCLK <= '0'; - CLK_counter <= (others => '0'); - media_not_connected <= '0'; - elsif rising_edge(CLK) then - last_TRCLK <= this_TRCLK; - this_TRCLK <= MED_TRANSMISSION_CLK_IN; - CLK_counter <= next_CLK_counter; - media_not_connected <= next_media_not_connected; - else - last_TRCLK <= last_TRCLK; - this_TRCLK <= this_TRCLK; - CLK_counter <= CLK_counter; - media_not_connected <= media_not_connected; - end if; - end process; - - - -transCLK_counter: process (this_TRCLK, last_TRCLK, CLK_counter, - buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, - buf_MED_PARITY_OUT, buf_CTRL) - begin - next_media_not_connected <= '0'; - if last_TRCLK = '0' and this_TRCLK = '1' then - next_CLK_counter <= (others => '0'); - elsif CLK_counter = 255 then - next_media_not_connected <= '1'; - next_CLK_counter <= CLK_counter; - else - next_CLK_counter <= CLK_counter + 1; - end if; - end process; - - - - ---INT to MED direction --------------------------------- -INT2MED_fsm: process(buf_INT_DATA_IN,INT2MED_state, - INT_DATAREADY_IN, INT_DATA_IN, buf_INT_READ_OUT, - next_TRANSMISSION_CLK, buf_MED_TRANSMISSION_CLK_OUT, buf_MED_DATA_OUT, - buf_MED_CARRIER_OUT, buf_MED_PARITY_OUT, buf_CTRL) - variable tmp: std_logic_vector(12 downto 0); -begin - next_INT2MED_state <= "0000"; - next_buf_MED_DATA_OUT <= buf_MED_DATA_OUT; - next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; - next_MED_PARITY_OUT <= buf_MED_PARITY_OUT; - next_buf_INT_DATA_IN <= buf_INT_DATA_IN; - next_buf_INT_READ_OUT <= buf_INT_READ_OUT; - - next_packets_out_counter <= packets_out_counter; - case INT2MED_state is - when "0000" => - if INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then - --generate data word to transmit - next_buf_INT_DATA_IN(55 downto 0) <= INT_DATA_IN(55 downto 0); - next_INT2MED_state <= "0001"; - next_buf_INT_READ_OUT <= '0'; - next_packets_out_counter <= packets_out_counter + 1; - else - next_buf_INT_READ_OUT <= '1'; - next_MED_CARRIER_OUT <= '0'; - next_MED_PARITY_OUT <= '0'; - end if; - when "0001" => - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(12 downto 0); - next_MED_CARRIER_OUT <= '1'; - next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(12 downto 0)); - next_INT2MED_state <= "0010"; - else - next_INT2MED_state <= "0001"; - end if; - when "0010" => - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(25 downto 13); - next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(25 downto 13)); - next_INT2MED_state <= "0100"; - else - next_INT2MED_state <= "0010"; - end if; - when "0100" => - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(38 downto 26); - next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(38 downto 26)); - next_INT2MED_state <= "0110"; - else - next_INT2MED_state <= "0100"; - end if; - when "0110" => - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT(12 downto 0) <= buf_INT_DATA_IN(51 downto 39); - next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN(51 downto 39)); - next_INT2MED_state <= "1000"; - else - next_INT2MED_state <= "0110"; - end if; - when "1000" => - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - - tmp(3 downto 0) := buf_INT_DATA_IN(55 downto 52); - tmp(11 downto 4) := buf_CTRL(31 downto 24); - tmp(12) := buf_CTRL(0); - - next_buf_MED_DATA_OUT <= tmp; - next_MED_PARITY_OUT <= xor_all(tmp); - next_INT2MED_state <= "1110"; - else - next_INT2MED_state <= "1000"; - end if; - when "1110" => - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_INT2MED_state <= "0000"; - next_MED_CARRIER_OUT <= '0'; - next_buf_MED_DATA_OUT <= (others => '0'); - else - next_INT2MED_state <= "1110"; - end if; - when others => - next_INT2MED_state <= "0000"; - end case; -end process; - - -INT2MED_fsm_reg: process(CLK,RESET) - begin - if RESET='1' then - buf_MED_DATA_OUT <= (others => '0'); - INT2MED_state <= "0000"; - buf_INT_DATA_IN <= (others => '0'); - buf_INT_READ_OUT <= '0'; - buf_MED_CARRIER_OUT <= '0'; - buf_MED_PARITY_OUT <= '0'; - packets_out_counter <= (others => '0'); - elsif rising_edge(CLK) then - INT2MED_state <= next_INT2MED_state; - buf_INT_DATA_IN <= next_buf_INT_DATA_IN; - buf_INT_READ_OUT <= next_buf_INT_READ_OUT; - buf_MED_DATA_OUT(12 downto 0) <= next_buf_MED_DATA_OUT(12 downto 0); - buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT; - buf_MED_PARITY_OUT <= next_MED_PARITY_OUT; - packets_out_counter <= next_packets_out_counter; - else - buf_MED_DATA_OUT <= buf_MED_DATA_OUT; - buf_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; - buf_MED_PARITY_OUT <= buf_MED_PARITY_OUT; - INT2MED_state <= INT2MED_state; - buf_INT_READ_OUT <= buf_INT_READ_OUT; - buf_INT_DATA_IN <= buf_INT_DATA_IN; - packets_out_counter <= packets_out_counter; - end if; - end process; - - - - - - - - - - - - - - - ---MED to INT direction --------------------------------- - -MED2INT_fsm: process(reg_MED_PARITY_IN,MED2INT_state,CLK,reg_MED_DATA_IN,DAT_MED2INT, - reg_MED_TRANSMISSION_CLK_IN,reg_MED_CARRIER_IN,INT_READ_IN, RECV_STAT, - media_not_connected,buf_INT_DATAREADY_OUT, buf_INT_DATA_OUT, last_MED_TRANSMISSION_CLK_IN - ) - begin - next_DAT_MED2INT <= DAT_MED2INT; - next_INT_DATA_OUT <= buf_INT_DATA_OUT; - next_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - next_MED2INT_state <= IDLE; - next_RECV_STAT <= RECV_STAT; - next_packets_in_counter <= packets_in_counter; - next_packets_in_compl_counter <= packets_in_compl_counter; - - case MED2INT_state is - when IDLE => - if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then - next_MED2INT_state <= RECV2; - next_DAT_MED2INT(12 downto 0) <= reg_MED_DATA_IN(12 downto 0); - end if; - when RECV2 => - if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then - next_MED2INT_state <= RECV3; - next_DAT_MED2INT(25 downto 13) <= reg_MED_DATA_IN(12 downto 0); - else - next_MED2INT_state <= RECV2; - end if; - when RECV3 => - if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then - next_MED2INT_state <= RECV4; - next_DAT_MED2INT(38 downto 26) <= reg_MED_DATA_IN(12 downto 0); - else - next_MED2INT_state <= RECV3; - end if; - when RECV4 => - if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then - next_MED2INT_state <= RECV5; - next_DAT_MED2INT(51 downto 39) <= reg_MED_DATA_IN(12 downto 0); - else - next_MED2INT_state <= RECV4; - end if; - when RECV5 => - if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '1' then - next_INT_DATA_OUT(51 downto 0) <= DAT_MED2INT(51 downto 0); - next_INT_DATA_OUT(55 downto 52) <= reg_MED_DATA_IN(3 downto 0); - next_RECV_STAT <= reg_MED_DATA_IN(12 downto 4); - next_INT_DATAREADY_OUT <= '1'; - next_MED2INT_state <= IDLE; - next_packets_in_counter <= packets_in_counter + 1; - else - next_MED2INT_state <= RECV5; - end if; - when others => - next_MED2INT_state <= IDLE; - end case; - - --clear dataready when read - if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then - next_INT_DATAREADY_OUT <= '0'; - next_INT_DATA_OUT <= (others => '0'); - end if; - - --check parity - if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' then - if(xor_all(reg_MED_DATA_IN(12 downto 0)) /= reg_MED_PARITY_IN) then - next_MED2INT_state <= IDLE; - end if; - end if; - - --reset on Carrier low --- if reg_MED_TRANSMISSION_CLK_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_CARRIER_IN = '0' then --- next_MED2INT_state <= IDLE; --- end if; - - --reset on not connected - if media_not_connected = '1' then - next_MED2INT_state <= IDLE; - end if; - end process; - - -process(MED2INT_state) -begin - case MED2INT_state is - when IDLE => med2int_state_sig <= "000"; - when RECV2 => med2int_state_sig <= "001"; - when RECV3 => med2int_state_sig <= "010"; - when RECV4 => med2int_state_sig <= "011"; - when RECV5 => med2int_state_sig <= "100"; - end case; -end process; - - -MED2INT_fsm_reg: process(CLK,RESET) - begin - if RESET='1' then - MED2INT_state <= IDLE; - buf_INT_DATAREADY_OUT <= '0'; - DAT_MED2INT <= (others => '0'); - buf_INT_DATA_OUT <= (others => '0'); - RECV_STAT <= (others => '0'); - packets_in_counter <= (others => '0'); - packets_in_compl_counter <= (others => '0'); - last_MED_TRANSMISSION_CLK_IN <= '1'; - elsif rising_edge(CLK) then - DAT_MED2INT <= next_DAT_MED2INT; - MED2INT_state <= next_MED2INT_state; - buf_INT_DATA_OUT <= next_INT_DATA_OUT; - buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT; - RECV_STAT <= next_RECV_STAT; - packets_in_counter <= next_packets_in_counter; - packets_in_compl_counter <= next_packets_in_compl_counter; - last_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN; - else - buf_INT_DATA_OUT <= buf_INT_DATA_OUT; - MED2INT_state <= MED2INT_state; - buf_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - DAT_MED2INT <= DAT_MED2INT; - RECV_STAT <= RECV_STAT; - packets_in_counter <= packets_in_counter; - packets_in_compl_counter <= packets_in_compl_counter; - last_MED_TRANSMISSION_CLK_IN <= last_MED_TRANSMISSION_CLK_IN; - end if; - end process; - -LVDS_IN_reg: process(CLK, RESET) - begin - if RESET='1' then - reg_MED_TRANSMISSION_CLK_IN <= '0'; - reg_MED_CARRIER_IN <= '0'; - reg_MED_PARITY_IN <= '0'; - reg_MED_DATA_IN <= (others => '0'); - elsif rising_edge(CLK) then - reg_MED_TRANSMISSION_CLK_IN <= MED_TRANSMISSION_CLK_IN; - reg_MED_CARRIER_IN <= MED_CARRIER_IN; - reg_MED_PARITY_IN <= MED_PARITY_IN; - reg_MED_DATA_IN <= MED_DATA_IN; - else - reg_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN; - reg_MED_CARRIER_IN <= reg_MED_CARRIER_IN; - reg_MED_PARITY_IN <= reg_MED_PARITY_IN; - reg_MED_DATA_IN <= reg_MED_DATA_IN; - end if; - end process; - - -end trb_net_med_13bit_slow_arch; - diff --git a/oldfiles/trb_net_med_32lvds.vhd b/oldfiles/trb_net_med_32lvds.vhd deleted file mode 100644 index ca1bc9e..0000000 --- a/oldfiles/trb_net_med_32lvds.vhd +++ /dev/null @@ -1,51 +0,0 @@ --- media interface for the 32 lvds lines (16 in each direction) --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/NewTriggerBusMedia - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_med_32lvds is - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Internal direction port (MII) - -- do not change this interface!!! - -- 1st part: from the medium to the internal logic (trbnet) - INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media - --and ready to be read out - INT_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- 2nd part: from the internal logic (trbnet) to the medium - INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read) - INT_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- (end do not change this interface!!!) - - - -- Media direction port - -- in this case for the cable => 32 lines in total - MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word - MED_TRANSMISSION_CLK_OUT: out STD_LOGIC; - MED_CARRIER_OUT: out STD_LOGIC; - MED_PARITY_OUT: out STD_LOGIC; - MED_DATA_IN: out STD_LOGIC_VECTOR (12 downto 0); -- Data word - MED_TRANSMISSION_CLK_IN: out STD_LOGIC; - MED_CARRIER_IN: out STD_LOGIC; - MED_PARITY_IN: out STD_LOGIC; - - -- Status and control port => this never can hurt - STAT: out STD_LOGIC_VECTOR (31 downto 0); - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - ); -END trb_net_med_32lvds; diff --git a/oldfiles/trb_net_med_8bit_fast.vhd b/oldfiles/trb_net_med_8bit_fast.vhd deleted file mode 100644 index 7f73599..0000000 --- a/oldfiles/trb_net_med_8bit_fast.vhd +++ /dev/null @@ -1,567 +0,0 @@ ---This entity provides data transfer of 55Bit in 4 16Bit packets via a 16Bit Bus ---with 8Bit data width plus 4 control Bits. ---data is repacked to have 8 spare Bits in the end of each word instead on the ---beginning. These Bits may be used for data integrity check later. ---The remaining four Bits on the LVDS cable are free to use at moment but should ---be reserved. - -------------------------------------------------- ---format on LVDS: 0-7 Data --- 8-10 free --- 11 "handshake" --- 12 first packet indicator --- 13 transmission clock --- 14 carrier --- 15 parity(0-7) -------------------------------------------------- - --- "handshake": if this is low, you can not send, if it goes down during a transfer, --- then probably some data is lost - ---Please check the timing report for setup/hold-errors on the receiving ports ---In case of an error, adjust the PHASE_SHIFT of the DCM. A change of one unit ---results in a shift of (CLK_PERIOD/256) ---If the timing seems to be correct but the trbnet trb_net doesn't react, try ---shifting the clock by 180 degrees. - ---Version with spare bits at end, using 18_to16 was 1.8 --- --- Constraints for timing on hadcom dev board: --- NET "LVDS_IN<13>" TNM_NET = LVDS_IN_CLK_GRP; --- TIMESPEC "TS_LVDS_IN" = PERIOD LVDS_IN_CLK_GRP 10 ns HIGH 50 %; --- INST "LVDS_IN<*>" TNM = "IN_DDR"; --- INST "LVDS_OUT<*>" TNM = "OUT_DDR"; --- INST lvds1/buf_MED_IN_fal* TNM = "falling_reg"; --- TIMEGRP "OUT_DDR" OFFSET = OUT 8 ns AFTER "CLK_IN"; --- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 BEFORE "LVDS_IN<13>"; --- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 BEFORE "LVDS_IN<13>" TIMEGRP "falling_reg"; - - ---Constraints for timing on acromag: --- #Constraints for LVDS --- NET "IO59_29P" TNM_NET = LVDS_IN_CLK_GRP; --- TIMESPEC "TS_LVDS_IN" = PERIOD LVDS_IN_CLK_GRP 10 ns HIGH 50 %; --- --- INST "io*_*p" TNM = "IN_DDR"; --- INST "io*_*n" TNM = "OUT_DDR"; --- INST trbnetendpoint1/lvds1/buf_MED_IN_fal* TNM = "falling_reg"; --- --- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 ns BEFORE "IO59_29P"; --- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 ns BEFORE "IO59_29P" TIMEGRP "falling_reg"; --- TIMEGRP "OUT_DDR" OFFSET = OUT 6.7 ns AFTER "FPGA_CLK"; - - - - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use UNISIM.VComponents.all; -library work; -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_med_8bit_fast is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- 1st part: from the medium to the internal logic (trbnet) - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - INT_PACKET_NR_OUT: out STD_LOGIC_VECTOR (1 downto 0); - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- 2nd part: from the internal logic (trbnet) to the medium - INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media - INT_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - INT_PACKET_NR_IN: in STD_LOGIC_VECTOR (1 downto 0); - INT_READ_OUT: out STD_LOGIC; -- offered word is read - INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- Media direction port - -- in this case for the cable => 32 lines in total - MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word - MED_TRANSMISSION_CLK_OUT: out STD_LOGIC; - MED_CARRIER_OUT: out STD_LOGIC; - MED_PARITY_OUT: out STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (12 downto 0); -- Data word - MED_TRANSMISSION_CLK_IN: in STD_LOGIC; - MED_CARRIER_IN: in STD_LOGIC; - MED_PARITY_IN: in STD_LOGIC; - - -- Status and control port => this never can hurt - - STAT: out STD_LOGIC_VECTOR(31 downto 0); - --31-16 show the current lvds data output (two times eight bit) - CTRL: in STD_LOGIC_VECTOR (31 downto 0) - ); -end entity; - -architecture trb_net_med_8bit_fast_arch of trb_net_med_8bit_fast is - -component dualdatarate_flipflop - generic( - WIDTH : integer := 1 - ); - port( - C0 : in std_logic; - C1 : in std_logic; - CE : in std_logic; - CLR : in std_logic; - D0 : in std_logic_vector(WIDTH-1 downto 0); - D1 : in std_logic_vector(WIDTH-1 downto 0); - PRE : in std_logic; - Q : out std_logic_vector(WIDTH-1 downto 0) - ); -end component; - - -component trb_net_fifo_16bit_bram_dualport - port (read_clock_in: IN std_logic; - write_clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; --reset - write_data_in: IN std_logic_vector(17 downto 0); - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0) - ); -end component trb_net_fifo_16bit_bram_dualport; - - - component trb_net_sbuf - generic (DATA_WIDTH : integer := 16; - VERSION: integer := 0); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - -- Port to synchronous output. - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - -- Status and control port - STAT_BUFFER: out STD_LOGIC - ); - end component; - - component FDDRCPE - port ( - Q : out STD_ULOGIC; - C0 : in STD_ULOGIC; - C1 : in STD_ULOGIC; - CE : in STD_ULOGIC; - CLR : in STD_ULOGIC; - D0 : in STD_ULOGIC; - D1 : in STD_ULOGIC; - PRE : in STD_ULOGIC); - end component; - -signal CLK_TRANS : std_logic; -signal fifo_data_in, next_fifo_data_in : std_logic_vector(17 downto 0); -signal fifo_data_out : std_logic_vector(17 downto 0); -signal fifo_full_out, fifo_empty_out : std_logic; -signal fifo_status_out : std_logic_vector(3 downto 0); -signal fifo_write_enable, next_fifo_write_enable : std_logic; -signal fifo_read_enable, last_fifo_read_enable : std_logic; - -signal buf_MED_PARITY_OUT : std_logic; -signal buf_MED_CARRIER_OUT : std_logic; -signal buf_MED_TRANSMISSION_CLK_OUT : std_logic; -signal buf_MED_TRANSMISSION_CLK_IN : std_logic; -signal buf_MED_DATA_OUT : std_logic_vector(12 downto 0); -signal buf_MED_IN_fal : std_logic_vector(15 downto 0); -signal buf_MED_IN : std_logic_vector(31 downto 0); - -signal buf_INT_DATA_OUT : std_logic_vector(17 downto 0); -signal buf_INT_DATAREADY_OUT : std_logic; -signal next_int_packet_nr_out, buf_int_packet_nr_out : std_logic_vector(1 downto 0); -signal next_send_data_byte1, send_data_byte1 : std_logic_vector(7 downto 0); -signal next_send_data_byte2, send_data_byte2 : std_logic_vector(7 downto 0); -signal next_send_data_byte1_parity, send_data_byte1_parity : std_logic; -signal next_send_data_byte2_parity, send_data_byte2_parity : std_logic; -signal next_send_dataready, send_dataready : std_logic; -signal next_send_packet1, send_packet1 : std_logic; -signal fifo_data_ready : std_logic; - -signal buf_int_error_out, next_INT_ERROR_OUT : std_logic_vector(2 downto 0); -signal buf_INT_READ_OUT : std_logic; -signal FB_CLK, CLK_FB_Out, CLK_RECV_Out : std_logic; -signal sbuff_status : std_logic; -signal sbuff_next_read_out : std_logic; -signal buf_comb_data_in : std_logic_vector(17 downto 0); - -signal DCM_LOCKED, RESET_RECV, next_RESET_RECV : std_logic; -begin - ------------------------------------------------------------------------ --- Fifo for incoming data ------------------------------------------------------------------------ - LVDS_FIFO1 : trb_net_fifo_16bit_bram_dualport - port map( - read_clock_in => CLK, - write_clock_in => CLK_TRANS, - read_enable_in => fifo_read_enable, - write_enable_in => fifo_write_enable, - fifo_gsr_in => RESET_RECV, - write_data_in => fifo_data_in, - read_data_out => fifo_data_out, - full_out => fifo_full_out, - empty_out => fifo_empty_out, - fifostatus_out => fifo_status_out - ); - - - - ------------------------------------------------------------------------ --- Getting clock from LVDS ------------------------------------------------------------------------ - - -U_DCM_RECV: DCM - generic map( - CLKIN_PERIOD => 10.00, -- 30.30ns - STARTUP_WAIT => FALSE, - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", - PHASE_SHIFT => 70, - CLKOUT_PHASE_SHIFT => "FIXED" - ) - port map ( - CLKIN => MED_TRANSMISSION_CLK_IN, - CLKFB => FB_CLK, - DSSEN => '0', - PSINCDEC => '0', - PSEN => '0', - PSCLK => '0', - RST => RESET, - CLK0 => CLK_FB_Out, -- for feedback - CLK180=> CLK_RECV_Out, - LOCKED => DCM_LOCKED - ); --- -U3_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); ---U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS); -CLK_TRANS <= FB_CLK; - ------------------------------------------------------------------------ --- Preparing incoming data for fifo ------------------------------------------------------------------------ - - recv : process(buf_MED_IN) - begin - next_fifo_data_in(7 downto 0) <= buf_MED_IN(7 downto 0); - next_fifo_data_in(15 downto 8) <= buf_MED_IN(23 downto 16); - next_fifo_data_in(17) <= ((buf_MED_IN(15) xnor xor_all(buf_MED_IN(7 downto 0))) or not buf_MED_IN(14)) and - ((buf_MED_IN(31) xnor xor_all(buf_MED_IN(23 downto 16))) or not buf_MED_IN(30)); - --parity check - next_fifo_data_in(16) <= buf_MED_IN(12); --first packet - next_fifo_write_enable <= buf_MED_IN(14); --carrier - end process; - - - recv_reg : process(CLK_TRANS, RESET_RECV) - begin - if RESET_RECV = '1' then - fifo_write_enable <= '0'; - fifo_data_in(15 downto 0) <= (others => '0'); - fifo_data_in(17) <= '0'; - elsif rising_edge(CLK_TRANS) then - fifo_write_enable <= next_fifo_write_enable; - fifo_data_in <= next_fifo_data_in; - else - fifo_write_enable <= fifo_write_enable; - fifo_data_in <= fifo_data_in; - end if; - end process; - ------------------------------------------------------------------------ --- Reading data from LVDS ------------------------------------------------------------------------ - - - lvds_reg_rising : process(CLK_TRANS, RESET_RECV) - begin - if RESET_RECV = '1' then - buf_MED_IN(31 downto 0) <= (others => '0'); - elsif rising_edge(CLK_TRANS) then - buf_MED_IN(14) <= MED_CARRIER_IN; - buf_MED_IN(15) <= MED_PARITY_IN; - buf_MED_IN(13) <= '0'; - buf_MED_IN(12 downto 0) <= MED_DATA_IN; - buf_MED_IN(31 downto 16) <= buf_MED_IN_fal; - else - buf_MED_IN <= buf_MED_IN; - end if; - end process; - - lvds_reg_falling : process(CLK_TRANS, RESET_RECV) - begin - if RESET_RECV = '1' then - buf_MED_IN_fal(15 downto 0) <= (others => '0'); - elsif falling_edge(CLK_TRANS) and MED_CARRIER_IN = '1' then - buf_MED_IN_fal(14) <= MED_CARRIER_IN; - buf_MED_IN_fal(15) <= MED_PARITY_IN; - buf_MED_IN_fal(13) <= '1'; - buf_MED_IN_fal(12 downto 0) <= MED_DATA_IN; - else - buf_MED_IN_fal <= buf_MED_IN_fal; - end if; - end process; - ------------------------------------------------------------------------ --- Reading data from fifo, offering to INT ------------------------------------------------------------------------ - - process(sbuff_next_read_out, fifo_empty_out, last_fifo_read_enable, - fifo_data_out, buf_int_packet_nr_out, DCM_LOCKED) - begin - fifo_read_enable <= sbuff_next_read_out and not fifo_empty_out; - next_int_error_out <= ERROR_OK; - - if last_fifo_read_enable = '1' and fifo_data_out(16) = '1' then - next_int_packet_nr_out <= "00"; - elsif last_fifo_read_enable = '1' then - next_int_packet_nr_out <= buf_int_packet_nr_out + 1; - else - next_int_packet_nr_out <= buf_int_packet_nr_out; - end if; - - if last_fifo_read_enable = '1' then - --next_int_data_out <= fifo_data_out(15 downto 0); - --next_int_dataready_out <= '1'; - - if fifo_data_out(17) = '0' then - next_int_error_out <= ERROR_FATAL; - else - next_int_error_out <= ERROR_OK; - end if; - if fifo_data_out(16) = '1' and buf_int_packet_nr_out /= "11" then - next_int_error_out <= ERROR_ENCOD; - end if; - end if; - if DCM_LOCKED = '0' then --without a locked clock -> no transmission possible - next_int_error_out <= ERROR_NC; - end if; - end process; - - process(CLK,RESET_RECV) - begin - if rising_edge(CLK) then - if RESET_RECV = '1' then - last_fifo_read_enable <= '0'; - buf_int_error_out <= ERROR_NC; - buf_int_packet_nr_out <= "00"; - else - last_fifo_read_enable <= fifo_read_enable; - buf_int_error_out <= next_int_error_out; - buf_int_packet_nr_out <= next_int_packet_nr_out; - end if; - end if; - end process; - -buf_comb_data_in(15 downto 0) <= fifo_data_out(15 downto 0); -buf_comb_data_in(17 downto 16) <= next_int_packet_nr_out; - - - SBUF_fifo_to_int : trb_net_sbuf - generic map(DATA_WIDTH => 18, VERSION => 0) - port map ( - CLK => CLK, - RESET => RESET_RECV, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => last_fifo_read_enable, - COMB_next_READ_OUT => sbuff_next_read_out, - COMB_READ_IN => '1', - COMB_DATA_IN => buf_comb_data_in, - -- Port to synchronous output. - SYN_DATAREADY_OUT => buf_INT_DATAREADY_OUT, - SYN_DATA_OUT => buf_INT_DATA_OUT, - SYN_READ_IN => INT_READ_IN, - -- Status and control port - STAT_BUFFER => sbuff_status - ); - - -INT_DATA_OUT <= buf_int_data_out(15 downto 0); -INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; -INT_PACKET_NR_OUT <= buf_int_data_out(17 downto 16); -INT_ERROR_OUT <= buf_int_error_out; - - ------------------------------------------------------------------------ --- Sending data ------------------------------------------------------------------------ - -buf_INT_READ_OUT <= not RESET_RECV; -INT_READ_OUT <= buf_INT_READ_OUT; ---RESET_RECV <= RESET or not DCM_LOCKED or not MED_DATA_IN(11); - - process(RESET,DCM_LOCKED,MED_DATA_IN(11)) - begin - if DCM_LOCKED = '0' or not MED_DATA_IN(11) = '1' then - next_RESET_RECV <= '1'; - else - next_RESET_RECV <= '0'; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - RESET_RECV <= '1'; - else - RESET_RECV <= next_RESET_RECV; - end if; - end if; - end process; - - - process(INT_DATAREADY_IN, INT_DATA_IN, INT_PACKET_NR_IN, buf_INT_READ_OUT, - send_data_byte1, send_data_byte2, send_packet1) - begin - - next_send_dataready <= '0'; - next_send_data_byte1 <= (others => '0'); --send_data_byte1; - next_send_data_byte2 <= (others => '0'); --send_data_byte2; - next_send_data_byte1_parity <= '0'; --send_data_byte1_parity; - next_send_data_byte2_parity <= '0'; --send_data_byte2_parity; - next_send_packet1 <= '0'; - if INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then - if INT_PACKET_NR_IN = "00" and send_packet1 = '0' then - next_send_packet1 <= '1'; - else - next_send_packet1 <= '0'; - end if; - next_send_data_byte1 <= INT_DATA_IN(15 downto 8); - next_send_data_byte2 <= INT_DATA_IN(7 downto 0); - next_send_dataready <= '1'; - next_send_data_byte2_parity <= xor_all(INT_DATA_IN(7 downto 0)); - next_send_data_byte1_parity <= xor_all(INT_DATA_IN(15 downto 8)); - end if; - end process; - - process(CLK, RESET_RECV) - begin - if rising_edge(CLK) then - if RESET_RECV = '1' then - send_data_byte1 <= (others => '0'); - send_data_byte2 <= (others => '0'); - send_data_byte1_parity <= '0'; - send_data_byte2_parity <= '0'; - send_dataready <= '0'; - send_packet1 <= '0'; - else - send_data_byte1 <= next_send_data_byte1 after 1 ns; - send_data_byte2 <= next_send_data_byte2 after 1 ns; - send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns; - send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns; - send_dataready <= next_send_dataready after 1 ns; - send_packet1 <= next_send_packet1 after 1 ns; - end if; - end if; - end process; - -ddr_ff_dat : dualdatarate_flipflop - generic map( - WIDTH => 8 - ) - port map( - Q => buf_MED_DATA_OUT(7 downto 0), - C0 => CLK, - C1 => not CLK, - CE => '1', - CLR => '0', - D0 => send_data_byte2, - D1 => send_data_byte1, - PRE => '0' - ); - -ddr_ff_parity : dualdatarate_flipflop - generic map( - WIDTH => 1 - ) - port map( - Q(0) => buf_MED_PARITY_OUT, - C0 => CLK, - C1 => not CLK, - CE => '1', - CLR => '0', - D0(0) => send_data_byte2_parity, - D1(0) => send_data_byte1_parity, - PRE => '0' - ); - -ddr_ff_clk : dualdatarate_flipflop - generic map( - WIDTH => 1 - ) - port map( - Q(0) => buf_MED_TRANSMISSION_CLK_OUT, - C0 => CLK, - C1 => not CLK, - CE => '1', - CLR => '0', - D0(0) => '1', - D1(0) => '0', - PRE => '0' - ); - - process(CLK, RESET_RECV) - begin - if RESET_RECV = '1' then - buf_MED_DATA_OUT(12) <= '0'; - buf_MED_CARRIER_OUT <= '0'; - elsif falling_edge(CLK) then - buf_MED_DATA_OUT(12) <= send_packet1; - buf_MED_CARRIER_OUT <= send_dataready; - else - buf_MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12); - buf_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; - end if; - end process; - -buf_MED_DATA_OUT(11 downto 8) <= "0000"; - ------------------------------------------------------------------------ --- Output generation ------------------------------------------------------------------------ -STAT(23 downto 16) <= send_data_byte1; -STAT(31 downto 24) <= send_data_byte2; -STAT(15 downto 0) <= (others => '0'); - -MED_PARITY_OUT <= buf_MED_PARITY_OUT; -MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; -MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; -MED_DATA_OUT(8 downto 0) <= buf_MED_DATA_OUT(8 downto 0); -MED_DATA_OUT(9) <= RESET_RECV; -MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12); - ---MED_DATA_OUT(8) <= '0'; ---MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12); ---MED_DATA_OUT(9 downto 8) <= buf_int_packet_nr_out; ---MED_DATA_OUT(11 downto 10) <= CONV_PACKET_NR_OUT; ---MED_DATA_OUT(9) <= CLK_TRANS; ---MED_DATA_OUT(8) <= buf_MED_TRANSMISSION_CLK_IN; -MED_DATA_OUT(10) <= fifo_data_in(0); -MED_DATA_OUT(11) <= (DCM_LOCKED);-- or (fifo_data_in(17) and not RESET_RECV); --- MED_DATA_OUT(10) <= CLK_TRANS; --- MED_DATA_OUT(11) <= fifo_write_enable; - -end architecture; - diff --git a/oldfiles/trb_net_med_8bit_slow.vhd b/oldfiles/trb_net_med_8bit_slow.vhd deleted file mode 100644 index 5e39da8..0000000 --- a/oldfiles/trb_net_med_8bit_slow.vhd +++ /dev/null @@ -1,411 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net_med_8bit_slow is - generic( - TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only! - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Internal direction port (MII) - INT_DATAREADY_OUT : out STD_LOGIC; - INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in STD_LOGIC; - INT_DATAREADY_IN : in STD_LOGIC; - INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out STD_LOGIC; - -- Media direction port - MED_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0); - MED_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0); - -- Status and control port - STAT: out STD_LOGIC_VECTOR (31 downto 0); - --STAT(5 downto 2): Debug bits in - - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0) - ); -end entity trb_net_med_8bit_slow; - -architecture trb_net_med_8bit_slow_arch of trb_net_med_8bit_slow is - - signal buf_INT_DATA_IN, next_buf_INT_DATA_IN :std_logic_vector(7 downto 0); - - signal next_INT_DATA_OUT, buf_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal next_INT_PACKET_NUM_OUT, buf_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT: std_logic; - signal buf_INT_READ_OUT: std_logic; - signal reg_MED_FIRST_PACKET_IN : std_logic; - signal next_buf_MED_DATA_OUT, buf_MED_DATA_OUT: std_logic_vector(7 downto 0); - signal buf_MED_TRANSMISSION_CLK_OUT: std_logic; - signal buf_MED_CARRIER_OUT, next_MED_CARRIER_OUT: STD_LOGIC; - signal buf_MED_PARITY_OUT, next_MED_PARITY_OUT: STD_LOGIC; - signal buf_MED_FIRST_PACKET_OUT, next_MED_FIRST_PACKET_OUT : std_logic; - signal my_error : std_logic_vector(2 downto 0); - signal fatal_error, media_not_connected : std_logic; - signal next_media_not_connected : std_logic; - signal transmission_clk_Counter : std_logic_vector(4 downto 0); - signal next_transmission_clk_Counter : std_logic_vector(4 downto 0); - signal next_TRANSMISSION_CLK: std_logic; - signal buf_STAT : std_logic_vector(31 downto 0); - - signal last_TRCLK, this_TRCLK: std_logic; - signal CLK_counter,next_CLK_counter: std_logic_vector(7 downto 0); - - signal last_MED_TRANSMISSION_CLK_IN : std_logic; - signal last_MED_FIRST_PACKET_IN : std_logic; - signal reg_MED_DATA_IN : std_logic_vector(11 downto 0); - signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic; - signal reg_MED_PARITY_IN : std_logic; - signal recv_counter : std_logic_vector(3 downto 0); - signal transmission_running, next_transmission_running : std_logic; - signal buf_MED_DATA_IN, next_buf_MED_DATA_IN : std_logic_vector(7 downto 0); - - signal led_counter : std_logic_vector(18 downto 0); - signal send_resync_counter : std_logic_vector(11 downto 0); - signal send_resync : std_logic; - signal rx_led, tx_led, link_led : std_logic; - signal trbnet_reset : std_logic; - - -begin - INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - INT_DATA_OUT <= buf_INT_DATA_OUT; - INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; - INT_READ_OUT <= buf_INT_READ_OUT; - STAT <= buf_STAT; - - buf_STAT(1 downto 0) <= (others => '0'); - buf_STAT(5 downto 2) <= MED_DATA_IN(11 downto 8); - buf_STAT(18 downto 6)<= (others => '0'); - buf_STAT(31 downto 19) <= reg_MED_PARITY_IN & reg_MED_CARRIER_IN & reg_MED_TRANSMISSION_CLK_IN & reg_MED_FIRST_PACKET_IN & reg_MED_DATA_IN(11) & reg_MED_DATA_IN(7 downto 0); - - - MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT; - MED_DATA_OUT(10 downto 8) <= (others => '0'); - MED_DATA_OUT(11) <= (not reset or send_resync); - MED_DATA_OUT(12) <= buf_MED_FIRST_PACKET_OUT; - MED_DATA_OUT(13) <= buf_MED_TRANSMISSION_CLK_OUT; - MED_DATA_OUT(14) <= buf_MED_CARRIER_OUT; - MED_DATA_OUT(15) <= buf_MED_PARITY_OUT; - - ---LED & Stat_OP - STAT_OP(2 downto 0) <= my_error; - STAT_OP(8 downto 3) <= (others => '0'); - STAT_OP(9) <= link_led; - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= '0'; - STAT_OP(13) <= not reg_MED_DATA_IN(11) and not last_MED_TRANSMISSION_CLK_IN and reg_MED_TRANSMISSION_CLK_IN and reg_MED_CARRIER_IN; - STAT_OP(14) <= (not reg_MED_DATA_IN(11) and reg_MED_CARRIER_IN) or media_not_connected; - STAT_OP(15) <= (not reg_MED_DATA_IN(11) and not last_MED_TRANSMISSION_CLK_IN and reg_MED_TRANSMISSION_CLK_IN and reg_MED_CARRIER_IN) or media_not_connected; - - link_led <= reg_MED_DATA_IN(11); - - process(CLK) - begin - if rising_edge(CLK) then - if reset = '1' then - led_counter <= (others => '0'); - rx_led <= '0'; - tx_led <= '0'; - else - if led_counter(18) = '1' then - led_counter <= (others => '0'); - else - led_counter <= led_counter + 1; - end if; - if reg_MED_CARRIER_IN = '1' then - rx_led <= '1'; - elsif led_counter(18) = '1' then - rx_led <= '0'; - end if; - if next_MED_CARRIER_OUT = '1' then - tx_led <= '1'; - elsif led_counter(18) = '1' then - tx_led <= '0'; - end if; - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - send_resync <= '0'; - send_resync_counter <= (others => '0'); - else - if not (send_resync_counter = 0) then - send_resync_counter <= send_resync_counter + 1; - end if; - if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then - send_resync <= '1'; - send_resync_counter <= send_resync_counter + 1; - end if; - if send_resync_counter = x"00F" then - send_resync <= '0'; - end if; - end if; - end if; - end process; - - --TODO: - -------------------------------- - fatal_error <= '0'; - - --My error bits - -------------------------------- - reg_my_error: process(CLK,RESET) - begin - if rising_edge(CLK) then - if RESET = '1' or media_not_connected = '1' or MED_DATA_IN(11) = '0' then - my_error <= ERROR_NC; - elsif fatal_error = '1' or (INT_READ_IN = '0' and buf_INT_DATAREADY_OUT = '1') then - my_error <= ERROR_FATAL; - else - my_error <= ERROR_OK; - end if; - end if; - end process; - - - --Transmission clock generator - -------------------------------- - trans_clk_counter: process (transmission_clk_Counter, buf_MED_TRANSMISSION_CLK_OUT) - begin - if transmission_clk_Counter = (TRANSMISSION_CLOCK_DIVIDER/2) - 1 then - next_transmission_clk_Counter <= (others => '0'); - next_TRANSMISSION_CLK <= not buf_MED_TRANSMISSION_CLK_OUT; - else - next_transmission_clk_Counter <= transmission_clk_Counter + 1; - next_TRANSMISSION_CLK <= buf_MED_TRANSMISSION_CLK_OUT; - end if; - end process; - - - trans_clk_counter_reg: process (CLK,RESET) - begin - if RESET = '1' then - transmission_clk_Counter <= (others => '0'); - buf_MED_TRANSMISSION_CLK_OUT <= '0'; - elsif rising_edge(CLK) then - transmission_clk_Counter <= next_transmission_clk_Counter; - buf_MED_TRANSMISSION_CLK_OUT <= next_TRANSMISSION_CLK; - else - transmission_clk_Counter <= transmission_clk_Counter; - buf_MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; - end if; - end process; - - - - --Transmission Clock detection - -------------------------------- - trans_clk_reg: process (RESET,CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - last_TRCLK <= '0'; - this_TRCLK <= '0'; - CLK_counter <= (others => '0'); - media_not_connected <= '0'; - else - last_TRCLK <= this_TRCLK; - this_TRCLK <= reg_MED_TRANSMISSION_CLK_IN; - CLK_counter <= next_CLK_counter; - media_not_connected <= next_media_not_connected; - end if; - end if; - end process; - - - - transCLK_counter: process (this_TRCLK, last_TRCLK, CLK_counter, - buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, - buf_MED_PARITY_OUT) - begin - next_media_not_connected <= '0'; - if RESET = '1' then - next_CLK_counter <= x"1F"; - elsif last_TRCLK = '0' and this_TRCLK = '1' then - next_CLK_counter <= (others => '0'); - elsif CLK_counter = 31 then - next_media_not_connected <= '1'; - next_CLK_counter <= CLK_counter; - else - next_CLK_counter <= CLK_counter + 1; - end if; - end process; - - - - - --INT to MED direction - -------------------------------- - INT2MED_fsm: process(buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, buf_MED_PARITY_OUT, buf_INT_DATA_IN, - transmission_running, buf_MED_FIRST_PACKET_OUT, next_TRANSMISSION_CLK, - buf_MED_TRANSMISSION_CLK_OUT, INT_DATAREADY_IN, INT_DATA_IN, - buf_INT_READ_OUT, INT_PACKET_NUM_IN) - begin - next_buf_MED_DATA_OUT <= buf_MED_DATA_OUT; - next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; - next_MED_PARITY_OUT <= buf_MED_PARITY_OUT; - next_buf_INT_DATA_IN <= buf_INT_DATA_IN; - next_transmission_running <= transmission_running; - next_MED_FIRST_PACKET_OUT <= buf_MED_FIRST_PACKET_OUT; - buf_INT_READ_OUT <= '0'; - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' and transmission_running = '0' then - next_MED_CARRIER_OUT <= '0'; - end if; - if(INT_DATAREADY_IN = '1' and transmission_running = '0') then - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT <= INT_DATA_IN(15 downto 8); - next_buf_INT_DATA_IN <= INT_DATA_IN(7 downto 0); - next_MED_CARRIER_OUT <= '1'; - next_MED_PARITY_OUT <= xor_all(INT_DATA_IN(15 downto 8)); - next_transmission_running <= '1'; - buf_INT_READ_OUT <= '1'; - if INT_PACKET_NUM_IN = c_H0 then - next_MED_FIRST_PACKET_OUT <= '1'; - else - next_MED_FIRST_PACKET_OUT <= '0'; - end if; - end if; - elsif transmission_running = '1' then - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT <= buf_INT_DATA_IN; - next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN); - next_transmission_running <= '0'; - end if; - end if; - if send_resync = '1' then - next_MED_CARRIER_OUT <= '1'; - end if; - end process; - - - INT2MED_fsm_reg: process(CLK,RESET) - begin - if rising_edge(CLK) then - if RESET='1' then - buf_MED_DATA_OUT <= (others => '0'); - buf_INT_DATA_IN <= (others => '0'); - buf_MED_CARRIER_OUT <= '0'; - buf_MED_PARITY_OUT <= '0'; - buf_MED_FIRST_PACKET_OUT <= '0'; - transmission_running <= '0'; - else - buf_INT_DATA_IN <= next_buf_INT_DATA_IN; - buf_MED_DATA_OUT <= next_buf_MED_DATA_OUT; - buf_MED_FIRST_PACKET_OUT <= next_MED_FIRST_PACKET_OUT; - buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT; - buf_MED_PARITY_OUT <= next_MED_PARITY_OUT; - transmission_running <= next_transmission_running; - end if; - end if; - end process; - - - - - - - - - - - - - - - - --MED to INT direction - -------------------------------- - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - recv_counter <= "0111"; - elsif reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then - if recv_counter = "1001" then - recv_counter <= "0000"; - else - recv_counter <= recv_counter + 1; - end if; - last_MED_FIRST_PACKET_IN <= reg_MED_FIRST_PACKET_IN; - if reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0' then - recv_counter <= "1000"; - end if; - end if; - end if; - end process; - - - - MED2INT_fsm: process(buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT, buf_MED_DATA_IN, last_MED_TRANSMISSION_CLK_IN, - reg_MED_TRANSMISSION_CLK_IN, reg_MED_DATA_IN, recv_counter, INT_READ_IN, reg_MED_CARRIER_IN, - buf_INT_PACKET_NUM_OUT, reg_MED_FIRST_PACKET_IN, last_MED_FIRST_PACKET_IN) - begin - next_INT_DATA_OUT <= buf_INT_DATA_OUT; - next_INT_DATAREADY_OUT <= '0'; --buf_INT_DATAREADY_OUT; - next_buf_MED_DATA_IN <= buf_MED_DATA_IN; - next_INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; - --- if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then --- next_INT_DATAREADY_OUT <= '0'; --- end if; - - if reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then - if recv_counter(0) = '1' or (reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0') then - next_buf_MED_DATA_IN <= reg_MED_DATA_IN(7 downto 0); - else - next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN(7 downto 0); - next_INT_DATA_OUT(15 downto 8) <= buf_MED_DATA_IN; - next_INT_PACKET_NUM_OUT <= recv_counter(3 downto 1); - next_INT_DATAREADY_OUT <= '1'; - end if; - end if; - end process; - - - MED2INT_fsm_reg: process(CLK) - begin - if rising_edge(CLK) then - if RESET='1' then - buf_INT_DATAREADY_OUT <= '0'; - last_MED_TRANSMISSION_CLK_IN <= '1'; - else - buf_INT_DATA_OUT <= next_INT_DATA_OUT; - buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT; - last_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN; - buf_MED_DATA_IN <= next_buf_MED_DATA_IN; - buf_INT_PACKET_NUM_OUT <= next_INT_PACKET_NUM_OUT; - end if; - end if; - end process; - - LVDS_IN_reg: process(CLK) - begin - if rising_edge(CLK) then - reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13); - reg_MED_CARRIER_IN <= MED_DATA_IN(14); - reg_MED_PARITY_IN <= MED_DATA_IN(15); - reg_MED_DATA_IN <= MED_DATA_IN(11 downto 0); - reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12); - end if; - end process; - -end architecture; - diff --git a/oldfiles/trb_net_med_tlkx501.vhd b/oldfiles/trb_net_med_tlkx501.vhd deleted file mode 100644 index 55a1640..0000000 --- a/oldfiles/trb_net_med_tlkx501.vhd +++ /dev/null @@ -1,47 +0,0 @@ --- media interface for the 32 lvds lines (16 in each direction) --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/NewTriggerBusMedia - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_med_tlkx501 is - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Internal direction port (MII) - -- do not change this interface!!! - -- 1st part: from the medium to the internal logic (trbnet) - INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media - --and ready to be read out - INT_DATA_OUT: out STD_LOGIC_VECTOR (55 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- 2nd part: from the internal logic (trbnet) to the medium - INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read) - INT_DATA_IN: in STD_LOGIC_VECTOR (55 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- (end do not change this interface!!!) - - - -- Media direction port - -- marek, please add the lines you need here (the real output pins) - -- subcomponents like counters, egde detect etc - -- should be renamed to trb_net_XXX to avoid naming conflics - -- - -- - - -- Status and control port => this never can hurt - STAT: out STD_LOGIC_VECTOR (31 downto 0); - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - ); -END trb_net_med_tlkx501; diff --git a/oldfiles/trb_net_obuf.vhd b/oldfiles/trb_net_obuf.vhd deleted file mode 100644 index 2c3ca51..0000000 --- a/oldfiles/trb_net_obuf.vhd +++ /dev/null @@ -1,330 +0,0 @@ --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetOBUF - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_obuf is - generic ( - DATA_COUNT_WIDTH : integer := 4; - SWITCH_OFF_BUFFER_CHECK : integer := 0 - --switching off erroneous output buffer counter. MUST ONLY be - --used for short transfers!!!! - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; - -- Internal direction port - INT_DATAREADY_IN: in STD_LOGIC; - INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; - -- Status and control port - STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0); - STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); - CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0) - ); -end trb_net_obuf; - -architecture trb_net_obuf_arch of trb_net_obuf is - - component trb_net_sbuf is - generic (DATA_WIDTH : integer := 56; - VERSION : integer := 0); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - -- Port to synchronous output. - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - -- Status and control port - STAT_BUFFER: out STD_LOGIC - ); - end component; - - signal current_output_buffer : STD_LOGIC_VECTOR (50 downto 0); - signal current_ACK_word, current_EOB_word, current_DATA_word, current_NOP_word : - STD_LOGIC_VECTOR (50 downto 0); - signal comb_dataready, comb_next_read, comb_read ,sbuf_free: STD_LOGIC; - signal reg_INT_READ_OUT , next_INT_READ_OUT:STD_LOGIC; - - signal next_SEND_ACK_IN, reg_SEND_ACK_IN : STD_LOGIC; - signal sent_ACK, sent_EOB, sent_DATA : STD_LOGIC; - - signal CURRENT_DATA_COUNT, next_DATA_COUNT : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0); --- signal max_DATA_COUNT, next_max_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0); - signal max_DATA_COUNT_minus_one, next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0); - signal max_DATA_COUNT_minus_two, next_max_DATA_COUNT_minus_two : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0); - signal tmp_next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (15 downto 0); - signal tmp_next_max_DATA_COUNT_minus_two : STD_LOGIC_VECTOR (15 downto 0); - signal TRANSMITTED_BUFFERS, next_TRANSMITTED_BUFFERS : STD_LOGIC_VECTOR (1 downto 0); - signal increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS : STD_LOGIC; - - signal SEND_BUFFER_SIZE_IN : STD_LOGIC_VECTOR (3 downto 0); - signal REC_BUFFER_SIZE_IN : STD_LOGIC_VECTOR (3 downto 0); - signal SEND_ACK_IN : STD_LOGIC; - signal GOT_ACK_IN : STD_LOGIC; - - signal is_locked, got_locked,release_locked : std_logic; - - -- type BUFFER_STATE is (BUFFER_IDLE, BUFFER_SEND_ACK, BUFFER_SEND_EOB, BUFFER_SEND_DATA, BUFFER_BLOCKED); - - - begin - - SBUF: trb_net_sbuf - generic map (DATA_WIDTH => 51, VERSION => 0) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => comb_dataready, - COMB_next_READ_OUT => comb_next_read, - COMB_READ_IN => comb_read, - COMB_DATA_IN => current_output_buffer, - SYN_DATAREADY_OUT => MED_DATAREADY_OUT, - SYN_DATA_OUT => MED_DATA_OUT, - SYN_READ_IN => MED_READ_IN - ); - - decrease_TRANSMITTED_BUFFERS <= GOT_ACK_IN; - comb_read <= '1'; - INT_READ_OUT <= reg_INT_READ_OUT; --- sbuf_free <= comb_next_read or MED_READ_IN; --sbuf killed - sbuf_free <= comb_next_read; - - COMB_NEXT_TRANSFER : process(current_NOP_word, MED_READ_IN, comb_next_read, - CURRENT_DATA_COUNT,reg_SEND_ACK_IN,reg_INT_READ_OUT, - INT_DATAREADY_IN, INT_DATA_IN, sent_ACK, sent_EOB, - current_ACK_word,current_EOB_word, sbuf_free, sent_data, - max_DATA_COUNT_minus_two,next_DATA_COUNT, - next_TRANSMITTED_BUFFERS) - begin - current_output_buffer <= current_NOP_word; - next_INT_READ_OUT <= '1'; - increase_TRANSMITTED_BUFFERS <= '0'; - next_DATA_COUNT <= CURRENT_DATA_COUNT; - next_SEND_ACK_IN <= reg_SEND_ACK_IN; - comb_dataready <= '0'; --- The read of data words have highest priority if this was prepared - if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then - current_output_buffer <= INT_DATA_IN; - comb_dataready <= '1'; --I hope sbuf can store - if INT_DATA_IN(TYPE_POSITION) = TYPE_TRM then --TRM means EOB - next_DATA_COUNT <= (others => '0'); - increase_TRANSMITTED_BUFFERS <= '1'; - else - next_DATA_COUNT <= CURRENT_DATA_COUNT +1; - end if; --- If we are not able to fill ACK or EOB now, we have to stop activity - if (sent_ACK = '1' or sent_EOB = '1' ) then - next_INT_READ_OUT <= '0'; - if sent_ACK = '1' then --BUGBUG: next_SEND_ACK_IN should be a - --counter (2 may arrive) - next_SEND_ACK_IN <= '1'; - end if; - end if; --- Otherwise we fill the gap - elsif sent_ACK = '1' and sbuf_free = '1' then - current_output_buffer <= current_ACK_word; - next_SEND_ACK_IN <= '0'; - comb_dataready <= '1'; - next_INT_READ_OUT <= '0'; --stop activity to be on the safe side - elsif sent_ACK = '1' and sbuf_free = '0' then - next_SEND_ACK_IN <= '1'; - elsif sent_EOB = '1' and sbuf_free = '1' then - current_output_buffer <= current_EOB_word; - next_DATA_COUNT <= (others => '0'); - increase_TRANSMITTED_BUFFERS <= '1'; - comb_dataready <= '1'; - next_INT_READ_OUT <= '0'; --stop activity to be on the safe side - end if; - ---finally, block data read if the rec buffer is full - if sent_data = '0' or - ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0))) - and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' ) --and INT_DATA_IN(TYPE_POSITION) = TYPE_TRM - --long version of (next_count = max_count-1) - or (next_TRANSMITTED_BUFFERS(1) = '1' and SWITCH_OFF_BUFFER_CHECK = 0) - then - next_INT_READ_OUT <= '0'; - end if; ---In any case: if sbuf not free, then we stop data taking - if sbuf_free = '0' then - next_INT_READ_OUT <= '0'; - end if; - - end process; - - - REG : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_SEND_ACK_IN <= '0'; - CURRENT_DATA_COUNT <= (others => '0'); - reg_INT_READ_OUT <= '0'; - elsif CLK_EN = '1' then - reg_SEND_ACK_IN <= next_SEND_ACK_IN; - CURRENT_DATA_COUNT <= next_DATA_COUNT; - reg_INT_READ_OUT <= next_INT_READ_OUT; - else - reg_SEND_ACK_IN <= reg_SEND_ACK_IN; - CURRENT_DATA_COUNT <= CURRENT_DATA_COUNT; - reg_INT_READ_OUT <= reg_INT_READ_OUT; - end if; - end if; - end process; - - -- buffer registers - STAT_BUFFER(1 downto 0) <= TRANSMITTED_BUFFERS; - STAT_BUFFER(15 downto 2) <= (others => '0'); - STAT_BUFFER(31 downto 16) <= CURRENT_DATA_COUNT; - SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0); - REC_BUFFER_SIZE_IN <= CTRL_BUFFER(7 downto 4); - SEND_ACK_IN <= CTRL_BUFFER(8); - GOT_ACK_IN <= CTRL_BUFFER(9); - - -- build the words and the internal data readys - current_ACK_word(TYPE_POSITION) <= TYPE_ACK; - current_ACK_word(47 downto 20) <= (others => '0'); - current_ACK_word(BUFFER_SIZE_POSITION) <= SEND_BUFFER_SIZE_IN; - current_ACK_word(15 downto 0) <= (others => '0'); - sent_ACK <= SEND_ACK_IN or reg_SEND_ACK_IN; - - current_EOB_word(TYPE_POSITION) <= TYPE_EOB; - current_EOB_word(47 downto 0) <= (others => '0'); - gen_sent_EOB : process (CURRENT_DATA_COUNT, max_DATA_COUNT_minus_one) - begin - if (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one) then - sent_EOB <= '1'; - else - sent_EOB <= '0'; - end if; - end process; - - current_NOP_word(TYPE_POSITION) <= TYPE_ILLEGAL; - current_NOP_word(47 downto 0) <= (others => '0'); - - current_DATA_word(50 downto 0) <= INT_DATA_IN; - sent_DATA <= '1' when (TRANSMITTED_BUFFERS(1) = '0' or SWITCH_OFF_BUFFER_CHECK = 1) else '0'; - --- generate max_DATA_COUNT, comb. operation which should be registered --- next_max_DATA_COUNT <= "0000000000000100" when REC_BUFFER_SIZE_IN="0001" else --- "0000000000001000" when REC_BUFFER_SIZE_IN="0010" else --- "0000000000010000" when REC_BUFFER_SIZE_IN="0011" else --- "0000000000100000" when REC_BUFFER_SIZE_IN="0100" else --- "0000000000000010"; - tmp_next_max_DATA_COUNT_minus_one <= "0000000000000011" when REC_BUFFER_SIZE_IN="0001" else - "0000000000000111" when REC_BUFFER_SIZE_IN="0010" else - "0000000000001111" when REC_BUFFER_SIZE_IN="0011" else - "0000000000011111" when REC_BUFFER_SIZE_IN="0100" else - "0000000000000001"; - tmp_next_max_DATA_COUNT_minus_two <= "0000000000000010" when REC_BUFFER_SIZE_IN="0001" else - "0000000000000110" when REC_BUFFER_SIZE_IN="0010" else - "0000000000001110" when REC_BUFFER_SIZE_IN="0011" else - "0000000000011110" when REC_BUFFER_SIZE_IN="0100" else - "0000000000000000"; - next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0) <= tmp_next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0); - next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0) <= tmp_next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0); --- next_max_DATA_COUNT <= 2 ** (REC_BUFFER_SIZE_IN + 1); - -- BUGBUG via pattern_gen - - reg_max_DATA_COUNT : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - max_DATA_COUNT_minus_one(0) <= '1'; - max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1) <= (others => '0'); - max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0) <= (others => '0'); - else - max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one; - max_DATA_COUNT_minus_two <= next_max_DATA_COUNT_minus_two; - end if; - end if; - end process; - - --- increase and decrease transmitted buffers - comb_TRANSMITTED_BUFFERS : process (increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS) - begin - if (increase_TRANSMITTED_BUFFERS = '1' and decrease_TRANSMITTED_BUFFERS = '0') then - next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS +1; - elsif (increase_TRANSMITTED_BUFFERS = '0' and decrease_TRANSMITTED_BUFFERS = '1') then - next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS -1; - else - next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS; - end if; - end process; - - reg_TRANSMITTED_BUFFERS : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - TRANSMITTED_BUFFERS <= "00"; - elsif CLK_EN = '1' then - TRANSMITTED_BUFFERS <= next_TRANSMITTED_BUFFERS; - else - TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS; - end if; - end if; - end process; - - - --locking control - comb_locked : process (MED_READ_IN, current_output_buffer, release_locked, is_locked) - - begin -- process - got_locked <= is_locked; - - if MED_READ_IN = '1' then - if current_output_buffer(TYPE_POSITION) = TYPE_TRM and release_locked = '0' then - got_locked <= '1'; - elsif release_locked = '1' then - got_locked <= '0'; - end if; - elsif release_locked = '1' then - got_locked <= '0'; - end if; -- MED_READ_IN - end process; - - release_locked <= CTRL_LOCKED(0); - STAT_LOCKED(0) <= is_locked; - STAT_LOCKED(15 downto 1) <= (others => '0'); - - reg_locked: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - is_locked <= '0'; - elsif CLK_EN = '1' then - is_locked <= got_locked; - else - is_locked <= is_locked; - end if; - end if; - end process; - - -end trb_net_obuf_arch; - diff --git a/oldfiles/trb_net_old_to_new.vhd b/oldfiles/trb_net_old_to_new.vhd deleted file mode 100644 index f59a7ba..0000000 --- a/oldfiles/trb_net_old_to_new.vhd +++ /dev/null @@ -1,284 +0,0 @@ --- this is an apl, connecting the old trigger bus to the new system -------------------------------------------------------------------------------- --- Title : trb_net_old_to_new --- Project : HADES trigger new net -------------------------------------------------------------------------------- --- File : trb_net_old_to_new.vhd --- Author : Tiago Perez (tiago.perez@uni-giessen.de) --- Created : 2007/01/12 --- Last modified : 2007/02/26 T. Perez -------------------------------------------------------------------------------- --- Description : Interace between "old" and "new" trigger nets --- -------------------------------------------------------------------------------- --- Modification history : --- 2007/01/12 : created --- L12TrigBusInterface is driven only with the main clock. This --- used to be 40MHz in "OLD" DTU but now is around 10 times faster. --- I am not sure how "sharp" are the edges of T and TS in the --- trigger bus, but now, samplig at ca. 400MHz we may sample T and --- TS sereval times while falling and still not set. We should --- chek the quality and "sharpness" of the Triggerbus with a scope --- and eventually downscale the main clock to sample slower. --- 2007/02/26: T. Perez (tiago.perez@uni-giessen.de) --- Change FSM so that all outouts are registered. OUTPUTS are --- decoded from the next_state to avoid losing CLK cycles. There --- is an external counter to do the sendig procedure. -------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - -entity trb_net_old_to_new is - generic (TRIGGER_LEVEL : integer := 1); -- either 1 or 2 - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_OUT : out std_logic_vector (47 downto 0); -- Data word "application to network" - APL_WRITE_OUT : out std_logic; -- Data word is valid and should be transmitted - APL_FIFO_FULL_IN : in std_logic; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_OUT : out std_logic; -- - APL_DTYPE_OUT : out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_OUT : out std_logic; -- Release sending of the data - APL_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_IN : in std_logic_vector (47 downto 0); -- Data word "network to application" - APL_TYP_IN : in std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_IN : in std_logic; -- Data word is valid and might be read out - APL_READ_OUT : out std_logic; -- Read data word - - -- APL Control port - APL_RUN_IN : in std_logic; -- Data transfer is running - APL_SEQNR_IN : in std_logic_vector (7 downto 0); - - -- the OLD trigger bus - OLD_T : in std_logic; -- trigger signal - -- used to strobe the trigger code - OLD_TS : in std_logic; -- trigger strobe --- used to strobe the trigger tag and further --- trigger data nibbles (e.g. trigger priority) - - OLD_TD : in std_logic_vector (3 downto 0); -- trigger data lines --- transmit the trigger data nibbles - OLD_TB : out std_logic; -- trigger busy --- wired-or signal, that indicates busy state of one or more DTUs - OLD_TE : out std_logic -- trigger error --- wired-or signal, that indicates error state of one or more DTUs ---Ts0..1 trigger spare lines ---free for future purposes ---not connected because useless - - - ); -end trb_net_old_to_new; - -architecture behavioral of trb_net_old_to_new is - - -- reconstruct the LVL1 or LVL2 trigger - -- for LVL1: Ignore the BEGRUN and ENDRUN triggers - -- (please use the generic to check if we have LVL1 or 2) - - -- compare to the SEQNR, do not forget the offset by one for LVL1 - -- if a tigger tag mismatch occures, raise the error line - - -- feel free to add debug registers - - -- COMPONENTS - -- OLD TRIGGER INTERFACE - component L12TrigBusInterface - port ( - TSTR : in std_logic; - DSTR : in std_logic; - DIN : in std_logic_vector(3 downto 0); - BSY : out std_logic; - ERR : out std_logic; - RES : in std_logic; - CLK : in std_logic; - DVAL : out std_logic; - TRIGTAG : out std_logic_vector(7 downto 0); - TRIGCODE : out std_logic_vector(3 downto 0); - TRIGTAG_MISMATCH : in std_logic; - BUSY : in std_logic); - end component; - - -- SIGNALS - signal TRIGTAG_i, TRIGTAG_ii : std_logic_vector(7 downto 0); - signal TRIGCODE_i : std_logic_vector(3 downto 0); - signal DVAL_i : std_logic; - signal TRIGTAG_MISMATCH_reg : std_logic; - - type State_Type is (idle, check_code, compare, send, error_1); - signal present_state, next_state : State_Type; - signal do_send_cnt : unsigned(2 downto 0); - - -begin - APL_DATA_OUT(7 downto 0) <= TRIGTAG_ii; - ----------------------------------------------------------------------------- - -- FIX NON USED OUTPUTS - ----------------------------------------------------------------------------- - APL_DATA_OUT(47 downto 8) <= (others => '0'); - APL_WRITE_OUT <= '0'; - - APL_SHORT_TRANSFER_OUT <= '1'; -- short transfer TRUE - APL_ERROR_PATTERN_OUT <= (others => '0'); - APL_TARGET_ADDRESS_OUT <= (others => '0'); - - ----------------------------------------------------------------------------- - -- COMPONENTS - ----------------------------------------------------------------------------- - BusInterfaceOld : L12TrigBusInterface - port map ( - TSTR => OLD_T, - DSTR => OLD_TS, - DIN => OLD_TD, - BSY => OLD_TB, - ERR => OLD_TE, - RES => RESET, - CLK => CLK, - DVAL => DVAL_i, - TRIGTAG => TRIGTAG_i, - TRIGCODE => TRIGCODE_i, - TRIGTAG_MISMATCH => TRIGTAG_MISMATCH_reg, - BUSY => APL_RUN_IN); - - ----------------------------------------------------------------------------- - -- DIFF LVL1/LVL2 - ----------------------------------------------------------------------------- - -- filter BEGRUN out - -- CHANGE: TRIGTAG=TRIGTAG-1 - GEN_L1 : if TRIGGER_LEVEL = 1 generate - process (CLK, RESET, CLK_EN, TRIGTAG_i) - begin -- process S - if RESET = '1' then - TRIGTAG_ii <= (others => '0'); - elsif CLK'event and CLK = '1' and CLK_EN = '1' then - TRIGTAG_ii <= TRIGTAG_i - 1; - end if; - end process; - end generate GEN_L1; - - -- Register TRIGTAG - GEN_L2 : if TRIGGER_LEVEL = 2 generate - process (CLK, RESET, CLK_EN, TRIGTAG_i) - begin -- process S - if RESET = '1' then - TRIGTAG_ii <= (others => '0'); - elsif CLK'event and CLK = '1' and CLK_EN = '1' then - TRIGTAG_ii <= TRIGTAG_i; - end if; - end process; - end generate GEN_L2; - - ----------------------------------------------------------------------------- - -- FSM - ----------------------------------------------------------------------------- - -- purpose: Register the STATE of the FSM - -- type : Sequential - -- inputs : CLK, RESET, next_state - -- output : next_state - state_clocked : process (CLK, RESET, CLK_EN) - begin -- process state_clocked - if RESET = '1' then -- asynchronous reset (active high) - present_state <= idle; - elsif CLK'event and CLK = '1' and CLK_EN = '1' then -- rising clock edge - present_state <= next_state; - end if; - end process state_clocked; - - -- purpose: Calculates the next_state of the FSM. - -- type : combinational - -- inputs : present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, APL_RUN_IN - -- outputs: next_state - FSM : process (present_state, DVAL_i, TRIGTAG_ii, APL_SEQNR_IN, TRIGCODE_i, do_send_cnt) - begin -- process FSM - next_state <= present_state; - case present_state is - when idle => - if DVAL_i = '1' then - next_state <= check_code; - end if; - when check_code => - -- Check for BEGIN_RUN - if TRIGCODE_i = x"d" then - next_state <= idle; - else - next_state <= compare; - end if; - when compare => - if TRIGTAG_ii = APL_SEQNR_IN then - next_state <= send; - else - next_state <= error_1; - end if; - when send => - if do_send_cnt = 5 then - --if APL_RUN_IN = '1' then - next_state <= idle; - end if; - when others => null; - end case; - end process FSM; - - -- purpose: decode and register the output signals of FSM - -- type : sequentia - -- inputs : next_state - -- outputs: TRIGTAG - decode_output : process (CLK, RESET, CLK_EN, next_state, do_send_cnt) - begin -- process decode_output - if RESET = '1' then - TRIGTAG_MISMATCH_reg <= '0'; - APL_SEND_OUT <= '0'; - APL_READ_OUT <= '0'; - - APL_DTYPE_OUT <= (others => '0'); - elsif CLK'event and CLK = '1' and CLK_EN = '1' then - TRIGTAG_MISMATCH_reg <= '0'; - APL_SEND_OUT <= '0'; - APL_READ_OUT <= '0'; - - APL_DTYPE_OUT <= (others => '0'); - - case next_state is - when idle => - --when check_code => - - when compare => - APL_DTYPE_OUT <= TRIGCODE_i; - - when send => - APL_DTYPE_OUT <= TRIGCODE_i; - if do_send_cnt = 1 then - APL_SEND_OUT <= '1'; - end if; - if (do_send_cnt = 3) or (do_send_cnt = 4) then - APL_READ_OUT <= '1'; - end if; - when error_1 => - TRIGTAG_MISMATCH_reg <= '1'; - when others => null; - end case; - end if; - end process decode_output; - - send_counter : process (CLK, RESET, present_state) - begin -- process send - if RESET = '1' or present_state = idle then -- asynchronous reset (active low) - do_send_cnt <= (others => '0'); - elsif CLK'event and CLK = '1' and present_state = send then -- rising clock edge - do_send_cnt <= do_send_cnt+1; - end if; - end process send_counter; - -end behavioral; - diff --git a/oldfiles/trb_net_passive_api.vhd b/oldfiles/trb_net_passive_api.vhd deleted file mode 100644 index da5a119..0000000 --- a/oldfiles/trb_net_passive_api.vhd +++ /dev/null @@ -1,203 +0,0 @@ --- connection between the TRBNET and any application --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_passive_api is - - generic (FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - -- not needed now, but later - ); -end trb_net_passive_api; - -architecture trb_net_passive_api_arch of trb_net_passive_api is - - component trb_net_base_api is - generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Internal direction port - -- the ports with active or passive in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - INT_MASTER_DATAREADY_OUT: out STD_LOGIC; - INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_MASTER_READ_IN: in STD_LOGIC; - - INT_MASTER_DATAREADY_IN: in STD_LOGIC; - INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_MASTER_READ_OUT: out STD_LOGIC; - - INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_SLAVE_DATAREADY_OUT: out STD_LOGIC; - INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_SLAVE_READ_IN: in STD_LOGIC; - - INT_SLAVE_DATAREADY_IN: in STD_LOGIC; - INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_SLAVE_READ_OUT: out STD_LOGIC; - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - -- not needed now, but later - ); - end component; - -begin - - PASSIVE_API: trb_net_base_api - generic map ( - API_TYPE => 0, - FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => 0 - ) - port map ( - CLK => CLK, - CLK_EN => CLK_EN, - RESET => RESET, - - APL_DATA_IN => APL_DATA_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_SEND_IN => APL_SEND_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - APL_DATA_OUT => APL_DATA_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT, - INT_MASTER_READ_IN => INT_REPLY_READ_IN, - - INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_MASTER_DATA_IN => INT_REPLY_DATA_IN, - INT_MASTER_READ_OUT => INT_REPLY_READ_OUT, - - INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - - INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT, - INT_SLAVE_READ_IN => INT_INIT_READ_IN, - - INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_SLAVE_DATA_IN => INT_INIT_DATA_IN, - INT_SLAVE_READ_OUT => INT_INIT_READ_OUT, - -- Status and control port - STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, - STAT_FIFO_TO_APL => STAT_FIFO_TO_APL - -- not needed now, but later - ); - -end trb_net_passive_api_arch; diff --git a/oldfiles/trb_net_passive_apimbuf.vhd b/oldfiles/trb_net_passive_apimbuf.vhd deleted file mode 100644 index 7372352..0000000 --- a/oldfiles/trb_net_passive_apimbuf.vhd +++ /dev/null @@ -1,479 +0,0 @@ --- an active api together with an iobuf - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_passive_apimbuf is - - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3; -- or the replyibuf - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 1 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_Send_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_api_control_signals: out std_logic_vector(31 downto 0); - STAT_MPLEX: out STD_LOGIC_VECTOR(31 downto 0); - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); - API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end trb_net_passive_apimbuf; - -architecture trb_net_passive_apimbuf_arch of trb_net_passive_apimbuf is - -component trb_net_iobuf is - - generic (SWITCH_OFF_BUFFER_CHECK : integer := 0; - --switching off erroneous output buffer counter. MUST ONLY be - --used for short transfers!!!! - INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3); -- or the replyibuf - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading - - MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading - - MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0) - ); -end component; - -component trb_net_passive_api is - - generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_Send_IN: in STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out - APL_READ_IN: in STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) - ); -end component; - -component trb_net_io_multiplexer is - - generic (BUS_WIDTH : integer := 56; - MULT_WIDTH : integer := 5); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - -- highest bits are mult. - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - MED_READ_IN: in STD_LOGIC; - - -- Internal direction port - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); -end component; - -signal apl_to_buf_INIT_DATAREADY: STD_LOGIC; -signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal apl_to_buf_INIT_READ : STD_LOGIC; - -signal buf_to_apl_INIT_DATAREADY: STD_LOGIC; -signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal buf_to_apl_INIT_READ : STD_LOGIC; - -signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC; -signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal apl_to_buf_REPLY_READ : STD_LOGIC; - -signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC; -signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal buf_to_apl_REPLY_READ : STD_LOGIC; - --- for the connection to the multiplexer -signal MED_INIT_DATAREADY_OUT : STD_LOGIC; -signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_IN : STD_LOGIC; - -signal MED_INIT_DATAREADY_IN : STD_LOGIC; -signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_OUT : STD_LOGIC; - -signal MED_REPLY_DATAREADY_OUT : STD_LOGIC; -signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_IN : STD_LOGIC; - -signal MED_REPLY_DATAREADY_IN : STD_LOGIC; -signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_OUT : STD_LOGIC; - -signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0); -signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0); -signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0); - -signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0); -signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0); -signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0); - -begin - - m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT; - m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT; - m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT; - MED_INIT_READ_IN <= m_READ_IN(0); - MED_REPLY_READ_IN <= m_READ_IN(1); - - MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0); - MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1); - MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0); - MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51); - m_READ_OUT(0) <= MED_INIT_READ_OUT; - m_READ_OUT(1) <= MED_REPLY_READ_OUT; - - - PASSIVE_API: trb_net_passive_api - - generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, - FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH) - - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN, - APL_WRITE_IN => APL_WRITE_IN, - APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, - APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - APL_Send_IN => APL_Send_IN, - APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, - - -- Receiver port - APL_DATA_OUT => APL_DATA_OUT, - APL_TYP_OUT => APL_TYP_OUT, - APL_DATAREADY_OUT => APL_DATAREADY_OUT, - APL_READ_IN => APL_READ_IN, - - -- APL Control port - APL_RUN_OUT => APL_RUN_OUT, - APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, - APL_SEQNR_OUT => APL_SEQNR_OUT, - - -- Internal direction port - -- connect via private signals - - INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, - INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA, - INT_INIT_READ_IN => apl_to_buf_INIT_READ, - - INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, - INT_INIT_DATA_IN => buf_to_apl_INIT_DATA, - INT_INIT_READ_OUT => buf_to_apl_INIT_READ, - - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT =>apl_to_buf_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA, - INT_REPLY_READ_IN => apl_to_buf_REPLY_READ, - - INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, - INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA, - INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ, - - -- Status and control port - STAT_FIFO_TO_INT => api_stat_fifo_to_int, - STAT_FIFO_TO_APL => api_stat_fifo_to_apl - ); - -STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); -STAT_api_control_signals(3) <= APL_WRITE_IN; -STAT_api_control_signals(4) <= APL_Send_IN; -STAT_api_control_signals(7 downto 5) <= (others => '0'); -STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0); -STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY; -STAT_api_control_signals(12) <= apl_to_buf_INIT_READ; -STAT_api_control_signals(13) <= MED_INIT_DATAREADY_IN; -STAT_api_control_signals(14) <= MED_REPLY_DATAREADY_IN; -STAT_api_control_signals(15) <= MED_REPLY_DATA_IN(48); -STAT_api_control_signals(16) <= MED_REPLY_DATA_IN(50); - -STAT_api_control_signals(31 downto 17) <= (others => '0'); - - - -IOBUF: trb_net_iobuf - - generic map (SWITCH_OFF_BUFFER_CHECK => 0, - --switching off erroneous output buffer counter. MUST ONLY be - --used for short transfers!!!! - INIT_DEPTH => INIT_DEPTH, - REPLY_DEPTH => REPLY_DEPTH) - - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, - MED_INIT_READ_IN => MED_INIT_READ_IN, - - MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_INIT_DATA_IN, - MED_INIT_READ_OUT => MED_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - - MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, - MED_REPLY_READ_IN => MED_REPLY_READ_IN, - - MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, - MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, - INT_INIT_READ_IN => buf_to_apl_INIT_READ, - - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, - INT_INIT_READ_OUT => apl_to_buf_INIT_READ, - - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, - - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, - - -- Status and control port - STAT_GEN => STAT_GEN, - STAT_LOCKED => STAT_LOCKED, - STAT_INIT_BUFFER => STAT_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, - CTRL_GEN => CTRL_GEN, - CTRL_LOCKED => CTRL_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER - ); - - MPLEX: trb_net_io_multiplexer - generic map (BUS_WIDTH => 52, - MULT_WIDTH => 1) - port map ( - CLK => CLK, - RESET => RESET , - CLK_EN => CLK_EN, - - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_READ_OUT => MED_READ_OUT, - - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_READ_IN => MED_READ_IN, - - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_READ_IN =>m_READ_OUT, - - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_READ_OUT =>m_READ_IN, - - CTRL => MPLEX_CTRL, - STAT => STAT_MPLEX - - ); - -end trb_net_passive_apimbuf_arch; - diff --git a/oldfiles/trb_net_priority_encoder_simple.vhd b/oldfiles/trb_net_priority_encoder_simple.vhd deleted file mode 100644 index 687dc85..0000000 --- a/oldfiles/trb_net_priority_encoder_simple.vhd +++ /dev/null @@ -1,40 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; - -entity trb_net_priority_encoder_simple is - generic ( - WIDTH : integer := 8 - ); - port ( - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT : out STD_LOGIC_VECTOR (WIDTH-1 downto 0) - ); -end entity; - -architecture trb_net_priority_encoder_simple_arch of trb_net_priority_encoder_simple is - - signal fixed_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); - - begin - fixed_pattern(0) <= INPUT_IN(0); - F1: for i in 1 to WIDTH-1 generate - process(INPUT_IN) - begin - if INPUT_IN(i) = '1' and INPUT_IN(i-1 downto 0) = 0 then - fixed_pattern(i) <= '1'; - else - fixed_pattern(i) <= '0'; - end if; - end process; - end generate; - - RESULT_OUT <= fixed_pattern; - - -end architecture; - diff --git a/oldfiles/trb_net_term.vhd b/oldfiles/trb_net_term.vhd deleted file mode 100644 index 0e5d4e3..0000000 --- a/oldfiles/trb_net_term.vhd +++ /dev/null @@ -1,257 +0,0 @@ --- this is just a terminator, which auto-answers requests --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetTerm - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_term is - - generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - - INT_DATAREADY_IN: in STD_LOGIC; - INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - APL_GOT_TRM: out STD_LOGIC; - - APL_HOLD_TRM: in STD_LOGIC; - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - - APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0) -- My own address (temporary solution!!!) - -- Status and control port - - -- not needed now, but later - - ); -END trb_net_term; - -architecture trb_net_term_arch of trb_net_term is - -component trb_net_fifo is - generic (WIDTH : integer := 8; -- FIFO word width - DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1) - - port (CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - - end component; - --- signals for the test buffer -signal next_APL_DTYPE_OUT, reg_APL_DTYPE_OUT: std_logic_vector(3 downto 0); -signal next_APL_ERROR_PATTERN_OUT, reg_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0); -signal next_APL_SEQNR_OUT, reg_APL_SEQNR_OUT: std_logic_vector(7 downto 0); -signal next_APL_GOT_TRM, reg_APL_GOT_TRM: std_logic; - -signal fifo_term_buffer_data_in : std_logic_vector(50 downto 0); -signal fifo_term_buffer_write : std_logic; -signal fifo_term_buffer_data_out : std_logic_vector(50 downto 0); -signal fifo_term_buffer_read : std_logic; -signal fifo_term_buffer_full : std_logic; -signal fifo_term_buffer_empty : std_logic; - -type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); -signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; - --- signal combined_header, registered_header, next_registered_header: std_logic_vector(47 downto 0); --- signal combined_trailer, registered_trailer, next_registered_trailer: std_logic_vector(47 downto 0); - signal tb_registered_trailer, tb_next_registered_trailer: std_logic_vector(47 downto 0); - signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0); - --- signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); --- signal next_INT_INIT_DATA_OUT: std_logic_vector(50 downto 0); --- signal next_INT_INIT_DATAREADY_OUT: std_logic; --- signal sbuf_free, sbuf_next_READ: std_logic; - signal next_INT_REPLY_READ_OUT, reg_INT_REPLY_READ_OUT: std_logic; --- signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; --- signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0); --- signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); - -begin - - -CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate - FIFO_TERM_BUFFER: trb_net_fifo - generic map ( - WIDTH => 51, - DEPTH => FIFO_TERM_BUFFER_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_term_buffer_data_in, - WRITE_ENABLE_IN => fifo_term_buffer_write, - DATA_OUT => fifo_term_buffer_data_out, - READ_ENABLE_IN => fifo_term_buffer_read, - FULL_OUT => fifo_term_buffer_full, - EMPTY_OUT => fifo_term_buffer_empty - ); -end generate CHECK_BUFFER1; -CHECK_BUFFER2: if FIFO_TERM_BUFFER_DEPTH =0 generate - fifo_term_buffer_empty <= '1'; - fifo_term_buffer_full <= '0'; - fifo_term_buffer_data_out <= (others => '0'); - -end generate CHECK_BUFFER2; - - APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; - APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; - APL_GOT_TRM <= reg_APL_GOT_TRM; - - - FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_DATA_IN, - INT_DATAREADY_IN, tb_next_registered_trailer, - tb_registered_trailer, - fifo_term_buffer_empty, fifo_term_buffer_data_out, - INT_READ_IN, tb_registered_target, - reg_APL_DTYPE_OUT, reg_APL_ERROR_PATTERN_OUT, - reg_APL_SEQNR_OUT, reg_APL_GOT_TRM,APL_MY_ADDRESS_IN, - APL_HOLD_TRM, APL_DTYPE_IN, APL_ERROR_PATTERN_IN) - begin -- process - INT_READ_OUT <= '0'; - fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_ILLEGAL; - fifo_term_buffer_data_in(DWORD_POSITION) <= (others => '0'); - fifo_term_buffer_write <= '0'; - tb_next_state <= MY_ERROR; - tb_next_registered_trailer <= tb_registered_trailer; - tb_next_registered_target <= tb_registered_target; - fifo_term_buffer_read<= '0'; - INT_DATAREADY_OUT <= '0'; - INT_DATA_OUT(DWORD_POSITION) <= (others => '0'); - INT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; - next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; - next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; - next_APL_GOT_TRM <= reg_APL_GOT_TRM; ------------------------------------------------------------------------ --- IDLE ------------------------------------------------------------------------ - if tb_current_state = IDLE then - INT_READ_OUT <= '1'; -- I always can read - tb_next_state <= IDLE; - if INT_DATA_IN(TYPE_POSITION) = TYPE_HDR and INT_DATAREADY_IN = '1' then - -- switch source and target adress - fifo_term_buffer_data_in(SOURCE_POSITION) <= INT_DATA_IN(TARGET_POSITION); - fifo_term_buffer_data_in(TARGET_POSITION) <= INT_DATA_IN(SOURCE_POSITION); - fifo_term_buffer_data_in(F3_POSITION) <= INT_DATA_IN(F3_POSITION); - fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_HDR; - tb_next_registered_target <= INT_DATA_IN(TARGET_POSITION); - if fifo_term_buffer_full = '0' and (INT_DATA_IN(TARGET_POSITION) = APL_MY_ADDRESS_IN - or INT_DATA_IN(TARGET_POSITION) = BROADCAST_ADRESS) then - fifo_term_buffer_write <= '1'; - else - fifo_term_buffer_write <= '0'; - end if; - elsif INT_DATA_IN(TYPE_POSITION) = TYPE_DAT and INT_DATAREADY_IN = '1' then - fifo_term_buffer_data_in <= INT_DATA_IN; - if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN - or tb_registered_target = BROADCAST_ADRESS) then - fifo_term_buffer_write <= '1'; - else - fifo_term_buffer_write <= '0'; - end if; - elsif INT_DATA_IN(TYPE_POSITION) = TYPE_TRM and INT_DATAREADY_IN = '1' then - --tb_next_registered_trailer <= INT_INIT_DATA_IN(DWORD_POSITION); - --keep trailer for later use - -- in addition, write out some debug info - next_APL_DTYPE_OUT <= INT_DATA_IN(DTYPE_POSITION); - next_APL_ERROR_PATTERN_OUT <= INT_DATA_IN(ERRORPATTERN_POSITION); - next_APL_SEQNR_OUT <= INT_DATA_IN(SEQNR_POSITION); - next_APL_GOT_TRM <= '1'; - tb_next_state <= RUNNING; - end if; ------------------------------------------------------------------------ --- RUNNING ------------------------------------------------------------------------ - elsif tb_current_state = RUNNING then - tb_next_state <= RUNNING; - if fifo_term_buffer_empty = '0' then -- Have buffered stuff - INT_DATAREADY_OUT <= '1'; - INT_DATA_OUT <= fifo_term_buffer_data_out; - if (INT_READ_IN = '1') then - fifo_term_buffer_read <= '1'; - end if; - elsif APL_HOLD_TRM = '1' then - tb_next_state <= RUNNING; --hold the line - else - tb_next_state <= SEND_TRAILER; - tb_next_registered_trailer(DTYPE_POSITION) <= APL_DTYPE_IN; - tb_next_registered_trailer(ERRORPATTERN_POSITION) <= APL_ERROR_PATTERN_IN; - tb_next_registered_trailer(SEQNR_POSITION) <= reg_APL_SEQNR_OUT; - tb_next_registered_trailer(15 downto 12) <= (others => '0'); - end if; -- Have buffered stuff ------------------------------------------------------------------------ --- TRAILER ------------------------------------------------------------------------ - elsif tb_current_state = SEND_TRAILER then - tb_next_state <= SEND_TRAILER ; - INT_DATAREADY_OUT <= '1'; - INT_DATA_OUT(DWORD_POSITION) <= tb_registered_trailer; - INT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - if (INT_READ_IN = '1') then - tb_next_state <= IDLE; - tb_next_registered_target <= ILLEGAL_ADRESS; - next_APL_GOT_TRM <= '0'; - end if; - end if; -- tb_current_state switch - end process; - -CLK_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - tb_current_state <= IDLE; - tb_registered_trailer <= (others => '0'); - tb_registered_target <= ILLEGAL_ADRESS; - reg_APL_DTYPE_OUT <= (others => '0'); - reg_APL_ERROR_PATTERN_OUT <= (others => '0'); - reg_APL_SEQNR_OUT <= (others => '0'); - reg_APL_GOT_TRM <= '0'; - else - tb_current_state <= tb_next_state; - tb_registered_trailer <= tb_next_registered_trailer; - tb_registered_target <= tb_next_registered_target; - reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT; - reg_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT; - reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT; - reg_APL_GOT_TRM <= next_APL_GOT_TRM; - end if; - end if; - end process; - -end trb_net_term_arch; diff --git a/oldfiles/trb_net_term_ibuf.vhd b/oldfiles/trb_net_term_ibuf.vhd deleted file mode 100644 index 6aee069..0000000 --- a/oldfiles/trb_net_term_ibuf.vhd +++ /dev/null @@ -1,216 +0,0 @@ --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF --- This has in principle the same output ports, but internally --- it keeps only the TRM words --- EOB are killed --- ACK are regognized --- all other words (HDR, DAT) are not stored - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_term_ibuf is - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Internal direction port - INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits - -- Status and control port - STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0); - STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0) - ); -end trb_net_term_ibuf; - -architecture trb_net_term_ibuf_arch of trb_net_term_ibuf is - - component trb_net_sbuf is - - generic (DATA_WIDTH : integer := 56; - VERSION : integer := 1); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - -- Port to synchronous output. - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - -- Status and control port - STAT_BUFFER: out STD_LOGIC - ); - end component; - - -signal got_ack_internal, reg_ack_internal : std_logic; --should be raised for 1 cycle when ack - --arrived -signal is_locked, got_locked,release_locked : std_logic; -signal got_eob_out, reg_eob_out: std_logic; -signal sbuf_free, comb_next_read: std_logic; -signal tmp_INT_DATAREADY_OUT: std_logic; -signal tmp_INT_DATA_OUT: std_logic_vector(50 downto 0); - -type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR); -signal current_error_state, next_error_state : ERROR_STATE; - -signal next_rec_buffer_size_out, current_rec_buffer_size_out : std_logic_vector(3 downto 0); - -- buffer size control - - begin - - --- this process controls the writing of the media into the fifo - FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN, - is_locked, current_rec_buffer_size_out, - current_error_state, release_locked, - sbuf_free) - begin -- process - got_ack_internal <= '0'; - next_rec_buffer_size_out <= current_rec_buffer_size_out; - next_error_state <= current_error_state; - tmp_INT_DATA_OUT <= (others => '1'); - tmp_INT_DATAREADY_OUT <= '0'; - got_eob_out <= '0'; - got_locked <= is_locked; - - if MED_DATAREADY_IN = '1' then -- data word offered - if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then - got_ack_internal <= '1'; - if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then - next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION); - end if; - elsif MED_DATA_IN(TYPE_POSITION) = TYPE_TRM then - got_eob_out <= '1'; --exactly when buffer is killed - tmp_INT_DATA_OUT <= MED_DATA_IN; - tmp_INT_DATAREADY_OUT <= '1'; - if release_locked = '0' then - got_locked <= '1'; - end if; - elsif MED_DATA_IN(TYPE_POSITION) = TYPE_EOB then - got_eob_out <= '1'; - tmp_INT_DATAREADY_OUT <= '0'; - -- this should happen only one CLK cycle - elsif sbuf_free = '0' then - next_error_state <= GOT_OVERFLOW_ERROR; - elsif is_locked = '1' then - next_error_state <= GOT_LOCKED_ERROR; - end if; -- end TYPE - end if; -- end MED_DATAREADY_IN - end process; - - MED_READ_OUT <= '1'; -- I always can read - -reg_buffer: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_rec_buffer_size_out <= (others => '0'); - reg_ack_internal <= '0'; - current_error_state <= IDLE; - elsif CLK_EN = '1' then - current_rec_buffer_size_out <= next_rec_buffer_size_out; - reg_ack_internal <= got_ack_internal; - current_error_state <= next_error_state; - else - current_rec_buffer_size_out <= current_rec_buffer_size_out; - reg_ack_internal <= reg_ack_internal; - current_error_state <= current_error_state; - end if; - end if; - end process; - - - - SBUF: trb_net_sbuf - generic map (DATA_WIDTH => 51, VERSION => 0) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => tmp_INT_DATAREADY_OUT, - COMB_next_READ_OUT => comb_next_read, - COMB_READ_IN => '1', - COMB_DATA_IN => tmp_INT_DATA_OUT, - SYN_DATAREADY_OUT => INT_DATAREADY_OUT, - SYN_DATA_OUT => INT_DATA_OUT, - SYN_READ_IN => INT_READ_IN - ); - - sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed - - release_locked <= CTRL_LOCKED(0); - STAT_LOCKED(0) <= is_locked; - STAT_LOCKED(15 downto 1) <= (others => '0'); - - reg_locked: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - is_locked <= '0'; - reg_eob_out <= '0'; - elsif CLK_EN = '1' then - if release_locked = '1' then - is_locked <= '0'; - else - is_locked <= got_locked; - end if; - reg_eob_out <= got_eob_out; - else - is_locked <= is_locked; - reg_eob_out <= reg_eob_out; - end if; - end if; - end process; - - - --- make STAT_BUFFER --- STAT_BUFFER(3 downto 0) <= (fifo_depth(3 downto 0)-1); --divide by 2, since 2 - --buffers have to be stored - STAT_BUFFER(3 downto 0) <= "0111"; --always "biggest fifo" - STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out; - - STAT_BUFFER(8) <= reg_eob_out; - STAT_BUFFER(9) <= reg_ack_internal; - - MAKE_ERROR_BITS : process(current_error_state) - begin - if current_error_state = IDLE then - STAT_BUFFER(11 downto 10) <= "00"; - elsif current_error_state = GOT_OVERFLOW_ERROR then - STAT_BUFFER(11 downto 10) <= "01"; - elsif current_error_state = GOT_LOCKED_ERROR then - STAT_BUFFER(11 downto 10) <= "10"; - else - STAT_BUFFER(11 downto 10) <= "11"; - end if; - end process; - - STAT_BUFFER(31 downto 12) <= (others => '0'); - -end trb_net_term_ibuf_arch; - diff --git a/oldfiles/trb_net_term_mbuf.vhd b/oldfiles/trb_net_term_mbuf.vhd deleted file mode 100644 index a327f1d..0000000 --- a/oldfiles/trb_net_term_mbuf.vhd +++ /dev/null @@ -1,412 +0,0 @@ --- an active api together with an iobuf - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - ---Entity decalaration for clock generator -entity trb_net_term_mbuf is - - generic (FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_IN: in STD_LOGIC; -- Media is reading - - MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word - MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - APL_GOT_TRM: out STD_LOGIC; - - APL_HOLD_TRM: in STD_LOGIC; - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - - -- Status and control port => just coming from the iobuf for debugging - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0) - ); -END trb_net_term_mbuf; - -architecture trb_net_term_mbuf_arch of trb_net_term_mbuf is - -component trb_net_iobuf is - - generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if - -- the initibuf - REPLY_DEPTH : integer := 3); -- or the replyibuf - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading - - MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading - - MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits - - -- Internal direction port - - INT_INIT_DATAREADY_OUT: out STD_LOGIC; - INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_IN: in STD_LOGIC; - - INT_INIT_DATAREADY_IN: in STD_LOGIC; - INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_INIT_READ_OUT: out STD_LOGIC; - - INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last - -- header (only for the reply path) - INT_REPLY_DATAREADY_OUT: out STD_LOGIC; - INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_IN: in STD_LOGIC; - - INT_REPLY_DATAREADY_IN: in STD_LOGIC; - INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_REPLY_READ_OUT: out STD_LOGIC; - - -- Status and control port - STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status - CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); - CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); - STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0) - ); -END component; - -component trb_net_term is - - generic (FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- Internal direction port - -- This is just a clone from trb_net_iobuf - - INT_DATAREADY_OUT: out STD_LOGIC; - INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_IN: in STD_LOGIC; - - INT_DATAREADY_IN: in STD_LOGIC; - INT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_READ_OUT: out STD_LOGIC; - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); - APL_GOT_TRM: out STD_LOGIC; - - APL_HOLD_TRM: in STD_LOGIC; - APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0) -- see NewTriggerBusNetworkDescr - - - -- Status and control port - - -- not needed now, but later - - ); -END component; - -component trb_net_io_multiplexer is - - generic (BUS_WIDTH : integer := 56; - MULT_WIDTH : integer := 5); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - -- highest bits are mult. - MED_READ_OUT: out STD_LOGIC; - - MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); - MED_READ_IN: in STD_LOGIC; - - -- Internal direction port - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); - - -- Status and control port - CTRL: in STD_LOGIC_VECTOR (31 downto 0); - STAT: out STD_LOGIC_VECTOR (31 downto 0) - ); -END component; - -signal apl_to_buf_INIT_DATAREADY: STD_LOGIC; -signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal apl_to_buf_INIT_READ : STD_LOGIC; - -signal buf_to_apl_INIT_DATAREADY: STD_LOGIC; -signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal buf_to_apl_INIT_READ : STD_LOGIC; - -signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC; -signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal apl_to_buf_REPLY_READ : STD_LOGIC; - -signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC; -signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); -signal buf_to_apl_REPLY_READ : STD_LOGIC; - --- for the connection to the multiplexer -signal MED_INIT_DATAREADY_OUT : STD_LOGIC; -signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_IN : STD_LOGIC; - -signal MED_INIT_DATAREADY_IN : STD_LOGIC; -signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_INIT_READ_OUT : STD_LOGIC; - -signal MED_REPLY_DATAREADY_OUT : STD_LOGIC; -signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_IN : STD_LOGIC; - -signal MED_REPLY_DATAREADY_IN : STD_LOGIC; -signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); -signal MED_REPLY_READ_OUT : STD_LOGIC; - -signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0); -signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0); -signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0); - -signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0); -signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0); -signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0); - -begin - - m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT; - m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT; - m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT; - MED_INIT_READ_IN <= m_READ_IN(0); - MED_REPLY_READ_IN <= m_READ_IN(1); - - MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0); - MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1); - MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0); - MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51); - m_READ_OUT(0) <= MED_INIT_READ_OUT; - m_READ_OUT(1) <= MED_REPLY_READ_OUT; - - - TERM_INIT: trb_net_term - - generic map (FIFO_TERM_BUFFER_DEPTH => 0) - - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - -- "mini" APL, just to see the triggers coming in - APL_DTYPE_OUT => APL_DTYPE_OUT, - APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT, - APL_SEQNR_OUT => APL_SEQNR_OUT, - APL_GOT_TRM => APL_GOT_TRM, - - APL_HOLD_TRM => APL_HOLD_TRM, - APL_DTYPE_IN => APL_DTYPE_IN, - APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, - - -- Internal direction port - -- connect via private signals - - INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, - INT_DATA_OUT => apl_to_buf_INIT_DATA, - INT_READ_IN => apl_to_buf_INIT_READ, - - INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, - INT_DATA_IN => buf_to_apl_INIT_DATA, - INT_READ_OUT => buf_to_apl_INIT_READ - - -- Status and control port - -- not needed now, but later - ); - -TERM_REPLY: trb_net_term - - generic map (FIFO_TERM_BUFFER_DEPTH => 0) - - port map ( - -- Misc - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - - -- "mini" APL, just to see the triggers coming in - - APL_HOLD_TRM => '0', - APL_DTYPE_IN => (others => '0'), - APL_ERROR_PATTERN_IN => (others => '0'), - - -- Internal direction port - -- connect via private signals - - INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, - INT_DATA_OUT => apl_to_buf_REPLY_DATA, - INT_READ_IN => apl_to_buf_REPLY_READ, - - INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, - INT_DATA_IN => buf_to_apl_REPLY_DATA, - INT_READ_OUT => buf_to_apl_REPLY_READ - -- Status and control port - -- not needed now, but later - ); - -IOBUF: trb_net_iobuf - - generic map (INIT_DEPTH => 0, - REPLY_DEPTH => 0) - - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, - MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, - MED_INIT_READ_IN => MED_INIT_READ_IN, - - MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, - MED_INIT_DATA_IN => MED_INIT_DATA_IN, - MED_INIT_READ_OUT => MED_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), - - MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, - MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, - MED_REPLY_READ_IN => MED_REPLY_READ_IN, - - MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, - MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, - MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, - INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, - INT_INIT_READ_IN => buf_to_apl_INIT_READ, - - INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, - INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, - INT_INIT_READ_OUT => apl_to_buf_INIT_READ, - - INT_REPLY_HEADER_IN => '0', - INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, - INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, - INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, - - INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, - INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, - INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, - - -- Status and control port - STAT_GEN => STAT_GEN, - STAT_LOCKED => STAT_LOCKED, - STAT_INIT_BUFFER => STAT_INIT_BUFFER, - STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, - CTRL_GEN => CTRL_GEN, - CTRL_LOCKED => CTRL_LOCKED, - STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, - STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER - ); - - MPLEX: trb_net_io_multiplexer - generic map (BUS_WIDTH => 52, - MULT_WIDTH => 1) - port map ( - CLK => CLK, - RESET => RESET , - CLK_EN => CLK_EN, - - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_READ_OUT => MED_READ_OUT, - - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_READ_IN => MED_READ_IN, - - INT_DATAREADY_OUT => m_DATAREADY_IN, - INT_DATA_OUT =>m_DATA_IN, - INT_READ_IN =>m_READ_OUT, - - INT_DATAREADY_IN =>m_DATAREADY_OUT, - INT_DATA_IN =>m_DATA_OUT, - INT_READ_OUT =>m_READ_IN, - - CTRL => MPLEX_CTRL - - ); - -end trb_net_term_mbuf_arch; - diff --git a/oldfiles/trb_net_trigger_reader.vhd b/oldfiles/trb_net_trigger_reader.vhd deleted file mode 100644 index df697a4..0000000 --- a/oldfiles/trb_net_trigger_reader.vhd +++ /dev/null @@ -1,291 +0,0 @@ ------------------------------------------------------------------------------- --- --- This is a trigger reading application with interrupt signal generation --- --- ------------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; -use work.trb_net_std.all; - - -entity trb_net_trigger_reader is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_OUT: out STD_LOGIC; -- - APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - -- Receiver port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out - APL_READ_OUT: out STD_LOGIC; -- Read data word - -- APL Control port - APL_RUN_IN: in STD_LOGIC; -- Data transfer is running - --APL_MY_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0); - - INTERNAL_TIME_OUT: out std_logic_vector(31 downto 0); - - TRB_INTERRUPT_OUT: out std_logic_vector(7 downto 0); - TRB_TRIGGER_NUM_OUT: out std_logic_vector(7 downto 0); - TRB_TRIGGER_TIME_OUT: out std_logic_vector(31 downto 0); - TRB_TRIGGER_DATAREADY: out std_logic; - TRB_TRIGGER_NUM_READ: in std_logic; - TRB_TRIGGER_TIME_READ: in std_logic; - TRB_TRIGGER_READ_ERROR: out std_logic; - - STAT_TRIGGER_READER: out std_logic_vector(31 downto 0) - ); -end entity; - - - -architecture trb_net_trigger_reader_arch of trb_net_trigger_reader is - - - component trb_net_fifo is - generic ( - WIDTH : integer := 48; -- FIFO word width - DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1) - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - end component; - - signal buf_APL_READ_OUT : std_logic; - signal buf_APL_DATA_OUT : std_logic_vector(47 downto 0); - signal buf_APL_WRITE_OUT: std_logic; - signal buf_APL_SEND_OUT, next_APL_SEND_OUT: std_logic; - signal buf_APL_ERROR_PATTERN_OUT, next_APL_ERROR_PATTERN_OUT: std_logic_vector(31 downto 0); - signal count_fifo: std_logic; - - signal fifo_data_in, next_fifo_data_in, fifo_data_out : std_logic_vector(39 downto 0); - signal fifo_write_enable_in, next_fifo_write_enable_in : std_logic; - signal fifo_read, next_fifo_read : std_logic; - signal fifo_empty_out : std_logic; - - signal buf_TRB_TRIGGER_NUM_OUT : std_logic_vector(7 downto 0); - signal buf_TRB_TRIGGER_TIME_OUT: std_logic_vector(31 downto 0); - - signal last_TRB_TRIGGER_NUM_READ, last_TRB_TRIGGER_TIME_READ : std_logic; - signal trigger_num_is_read, next_trigger_num_is_read: std_logic; - signal trigger_time_is_read, next_trigger_time_is_read: std_logic; - signal buf_TRB_TRIGGER_READ_ERROR, next_TRB_TRIGGER_READ_ERROR: std_logic; - - signal next_STAT_TRIGGER_READER, buf_STAT_TRIGGER_READER : std_logic_vector(31 downto 0); - signal timecounter, next_timecounter : std_logic_vector(31 downto 0); - signal clkcounter, next_clkcounter : std_logic_vector(6 downto 0); - --counter for us-timer - begin - - - ------------------------------------------ --- fifo for trigger data ------------------------------------------ - TRB_TRIGGER_DATAREADY <= not fifo_empty_out; - - trigger_fifo : trb_net_fifo - generic map( - WIDTH => 40, - DEPTH => 3 - ) - port map( - CLK => CLK, - CLK_EN => CLK_EN, - RESET => RESET, - DATA_IN => fifo_data_in, - WRITE_ENABLE_IN => fifo_write_enable_in, - DATA_OUT => fifo_data_out, - READ_ENABLE_IN => fifo_read, - FULL_OUT => open, - EMPTY_OUT => fifo_empty_out, - DEPTH_OUT => open - ); - - ------------------------------------------ --- detect and answer triggers ------------------------------------------ - process(APL_DATA_IN, APL_TYP_IN, APL_DATAREADY_IN, buf_APL_READ_OUT, timecounter, APL_SEQNR_IN) - begin - next_fifo_write_enable_in <= '0'; - next_fifo_data_in <= (others => '0'); - next_APL_SEND_OUT <= '0'; - if APL_TYP_IN = TYPE_TRM and APL_DATAREADY_IN = '1' and buf_APL_READ_OUT = '1' then - next_fifo_data_in(7 downto 0) <= APL_SEQNR_IN; - next_fifo_data_in(39 downto 8)<= timecounter; - next_fifo_write_enable_in <= '1'; - next_APL_SEND_OUT <= '1'; - next_APL_ERROR_PATTERN_OUT <= x"00000000"; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - fifo_data_in <= (others => '0'); - fifo_write_enable_in <= '0'; - buf_APL_SEND_OUT <= next_APL_SEND_OUT; - buf_APL_ERROR_PATTERN_OUT <= (others => '0'); - --buf_STAT_TRIGGER_READER <= (others => '0'); - else - fifo_data_in <= next_fifo_data_in; - fifo_write_enable_in <= next_fifo_write_enable_in; - buf_APL_SEND_OUT <= next_APL_SEND_OUT; - buf_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT; - --buf_STAT_TRIGGER_READER <= next_STAT_TRIGGER_READER; - end if; - end if; - end process; - -buf_STAT_TRIGGER_READER(1) <= fifo_write_enable_in; -buf_STAT_TRIGGER_READER(2) <= fifo_read; - -STAT_TRIGGER_READER <= buf_STAT_TRIGGER_READER; - ---------------------------------------- --- prepare trigger fifodata for readout ---------------------------------------- - - buf_TRB_TRIGGER_NUM_OUT <= fifo_data_out(7 downto 0); - buf_TRB_TRIGGER_TIME_OUT <= fifo_data_out(39 downto 8); - - - process(TRB_TRIGGER_NUM_READ, TRB_TRIGGER_TIME_READ, trigger_num_is_read, - trigger_time_is_read, buf_TRB_TRIGGER_READ_ERROR, last_TRB_TRIGGER_NUM_READ, - last_TRB_TRIGGER_TIME_READ, fifo_empty_out) - begin - next_trigger_num_is_read <= trigger_num_is_read; - next_trigger_time_is_read <= trigger_time_is_read; - fifo_read <= '0'; - next_TRB_TRIGGER_READ_ERROR <= '0'; - - if trigger_num_is_read = '1' and trigger_time_is_read = '1' then - next_trigger_num_is_read <= '0'; - next_trigger_time_is_read <= '0'; - fifo_read <= '1'; - next_TRB_TRIGGER_READ_ERROR <= buf_TRB_TRIGGER_READ_ERROR; - end if; - - if TRB_TRIGGER_NUM_READ = '1' then - next_TRB_TRIGGER_READ_ERROR <= '0'; - if trigger_num_is_read = '1' then - next_TRB_TRIGGER_READ_ERROR <= '1'; - end if; - next_trigger_num_is_read <= '1'; - end if; - - if TRB_TRIGGER_TIME_READ = '1' then - next_TRB_TRIGGER_READ_ERROR <= '0'; - if trigger_time_is_read = '1' then - next_TRB_TRIGGER_READ_ERROR <= '1'; - end if; - next_trigger_time_is_read <= '1'; - end if; - - if fifo_empty_out = '1' then - next_TRB_TRIGGER_READ_ERROR <= '1'; - end if; - end process; - - - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then --- last_TRB_TRIGGER_NUM_READ <= '0'; --- last_TRB_TRIGGER_TIME_READ <= '0'; - buf_TRB_TRIGGER_READ_ERROR <= '0'; - trigger_num_is_read <= '0'; - trigger_time_is_read <= '0'; --- fifo_read <= '0'; - else --- last_TRB_TRIGGER_NUM_READ <= TRB_TRIGGER_NUM_READ; --- last_TRB_TRIGGER_TIME_READ <= TRB_TRIGGER_TIME_READ; - buf_TRB_TRIGGER_READ_ERROR <= next_TRB_TRIGGER_READ_ERROR; - trigger_num_is_read <= next_trigger_num_is_read; - trigger_time_is_read <= next_trigger_time_is_read; --- fifo_read <= next_fifo_read; - end if; - end if; - end process; - - ------------------------------------------ --- Generate internal 32Bit timer @ 1 MHz ------------------------------------------ - - process(clkcounter, timecounter) - begin - next_clkcounter <= clkcounter + 1; - next_timecounter <= timecounter; - if(clkcounter = 98) then - next_clkcounter <= (others => '0'); - next_timecounter <= timecounter + 1; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - clkcounter <= (others => '0'); - timecounter <= (others => '0'); - else - clkcounter <= next_clkcounter; - timecounter <= next_timecounter; - end if; - end if; - end process; - - - - ------------------------------------------ --- Output generation ------------------------------------------ - APL_DATA_OUT <= (others => '0'); - APL_READ_OUT <= buf_APL_READ_OUT; - APL_WRITE_OUT <= '0'; - APL_SEND_OUT <= buf_APL_SEND_OUT; - APL_ERROR_PATTERN_OUT <= buf_APL_ERROR_PATTERN_OUT; - APL_TARGET_ADDRESS_OUT <= x"0001"; - APL_DTYPE_OUT <= "0000"; - APL_SHORT_TRANSFER_OUT <= '1'; - buf_APL_READ_OUT <= '1'; - - TRB_TRIGGER_NUM_OUT <= buf_TRB_TRIGGER_NUM_OUT; - TRB_TRIGGER_TIME_OUT <= buf_TRB_TRIGGER_TIME_OUT; - TRB_TRIGGER_READ_ERROR <= buf_TRB_TRIGGER_READ_ERROR; - - INTERNAL_TIME_OUT <= timecounter; - -end architecture; diff --git a/oldfiles/trb_net_trigger_sender.vhd b/oldfiles/trb_net_trigger_sender.vhd deleted file mode 100644 index a0ce4d1..0000000 --- a/oldfiles/trb_net_trigger_sender.vhd +++ /dev/null @@ -1,115 +0,0 @@ --- this is a dummy apl, just sending short transfers / triggers - - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net_trigger_sender is - generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"0002" - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" - APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted - APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full - APL_SHORT_TRANSFER_OUT: out STD_LOGIC; -- - APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr - APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr - APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data - APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of - -- the target (only for active APIs) - - -- Receiver port - APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" - APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM - APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out - APL_READ_OUT: out STD_LOGIC; -- Read data word - - -- APL Control port - APL_RUN_IN: in STD_LOGIC; -- Data transfer is running --- APL_MY_ADDRESS_OUT: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) - APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0) - - ); -end trb_net_trigger_sender; - -architecture trb_net_trigger_sender_arch of trb_net_trigger_sender is - - type SENDER_STATE is (IDLE, RUNNING, MY_ERROR); - signal current_state, next_state : SENDER_STATE; - signal next_counter, counter : std_logic_vector(23 downto 0); - signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(23 downto 0); - signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic; - signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; - - begin - - APL_READ_OUT <= '1'; --just read, do not check - APL_DTYPE_OUT <= x"1"; - APL_ERROR_PATTERN_OUT <= x"00000100"; - APL_TARGET_ADDRESS_OUT <= x"0000"; - --APL_DATA_OUT <= reg_counter; - APL_SHORT_TRANSFER_OUT <= '1'; - APL_WRITE_OUT <= '0'; - APL_DATA_OUT <= (others => '0'); - - SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, counter, APL_RUN_IN, RESET) - begin -- process - next_APL_SEND_OUT <= '0'; - next_state <= MY_ERROR; - next_counter <= counter + 1; -------------------------------------------------------------------------- --- IDLE -------------------------------------------------------------------------- - if current_state = IDLE then - if APL_RUN_IN = '0' and counter(7 downto 0) = 0 then - next_state <= RUNNING; - next_APL_SEND_OUT <= '1'; - else - next_state <= IDLE; - end if; ------------------------------------------------------------------------ --- RUNNING ------------------------------------------------------------------------ - elsif current_state = RUNNING then - next_state <= RUNNING; - if APL_RUN_IN = '1' then - next_state <= IDLE; - --else - -- next_state <= RUNNING; - end if; - end if; -- end state switch - end process; - -APL_SEND_OUT <= buf_APL_SEND_OUT; - - CLK_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_state <= IDLE; - buf_APL_SEND_OUT <= '0'; - counter <= (others => '0'); - elsif CLK_EN = '1' then - current_state <= next_state; - buf_APL_SEND_OUT <= next_APL_SEND_OUT; - counter <= next_counter; - else - current_state <= current_state; - buf_APL_SEND_OUT <= buf_APL_SEND_OUT; - counter <= counter; - end if; - end if; - end process; - -end trb_net_trigger_sender_arch; diff --git a/oldfiles/trbnetendpoint.vhd b/oldfiles/trbnetendpoint.vhd deleted file mode 100644 index 70b49c1..0000000 --- a/oldfiles/trbnetendpoint.vhd +++ /dev/null @@ -1,117 +0,0 @@ --------------------------------------------------------------------------------- --- The standard endpoint for all devices, like DTU, MU etc. --- The idea is to be independent from the "user" --- --- The endpoint works like a RAM --- Memory Map: --- --- 0x000 - 0x0FF global registers --- --- 0x100 - 0x1FF 16 sender ENDOBUFs (each 16 addresses) --- --- 0x200 - 0x2FF 16 receiver ENDIBUFs (each 16 addresses) --- --- for each ENDBUF, Adress 0x0 is the FIFO itself --- 0x1 is the status register --- 0x2 is the control register ---------------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - ---Entity decalaration for clock generator -entity TRBNETENDPOINT is port( - RESET : in std_logic; - clk: in std_logic; ---pin connections ------------------------------------------------------- - RD: in STD_LOGIC; -- Read strobe - WR: in STD_LOGIC; -- Write strobe - -- for a single transfer, the strobes MUST NOT be longer - -- then one cycle (already sync signals) - DATA_OUT: out STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus - DATA_IN : in STD_LOGIC_VECTOR (31 downto 0) ; -- I/O Bus - ADDRESS: in STD_LOGIC_VECTOR (11 downto 0) -- Adress lines for the - -- given space - ); -END TRBNETENDPOINT; - -architecture arch_TRBNETENDPOINT of TRBNETENDPOINT is - - component FIFO is - generic (WIDTH : integer := 8; -- FIFO word width - DEPTH : integer := 8); -- Depth of the FIFO - - port (DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Out put data - CLK : in std_logic; -- System Clock - RESET : in std_logic; -- System global Reset - RE : in std_logic; -- Read Enable - WE : in std_logic; -- Write Enable - FULL : buffer std_logic; -- Full Flag - EMPTY : buffer std_logic); -- Empty Flag - end component; - - signal DATA_FIFO1 : STD_LOGIC_VECTOR(31 downto 0); - signal DATA_FIFO2 : STD_LOGIC_VECTOR(31 downto 0); - - signal WE1 : STD_LOGIC; - signal WE2 : STD_LOGIC; - -begin -- arch_TRBNETENRPOINT - - FIFO1: FIFO - generic map ( - WIDTH => 32, - DEPTH => 8 - ) - port map ( - Data_in => DATA_IN, - Data_out => DATA_FIFO1, - clk => clk, - Reset => RESET, - WE => WE1, - RE => '0' - ); - - FIFO2: FIFO - generic map ( - WIDTH => 32, - DEPTH => 8 - ) - port map ( - Data_in => DATA_IN, - Data_out => DATA_FIFO2, - clk => clk, - Reset => RESET, - WE => WE2, - RE => '0' - ); - - -process (CLK) -begin -- process - if CLK'event and CLK = '1' then -- rising clock edge - if RD = '1' and ADDRESS(2) = '1' then - DATA_OUT <= DATA_FIFO1; - --DATA_OUT <= x"affeaffe"; - end if; - if RD = '1' and ADDRESS(2) = '0' then - --DATA_OUT <= x"deadface"; - DATA_OUT <= DATA_FIFO2; - end if; - if WR = '1' and ADDRESS(2) = '1' then - WE1 <= '1'; - else - WE1 <= '0'; - end if; - if WR = '1' and ADDRESS(2) = '0' then - WE2 <= '1'; - else - WE2 <= '0'; - end if; - end if; -end process; - -end arch_TRBNETENDPOINT; diff --git a/oldfiles/vulom3/beam_ramp.vhd b/oldfiles/vulom3/beam_ramp.vhd deleted file mode 100644 index c28fcd4..0000000 --- a/oldfiles/vulom3/beam_ramp.vhd +++ /dev/null @@ -1,259 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 26/6/07 --- Design Name: vulom3 --- Module Name: beam_ramp - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: Programmable delayer and shaper for beam signal --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity beam_ramp is - port ( clk_300MHz : in std_logic; - clk_50MHz : in std_logic; - input : in std_logic; - output_inhibit : out std_logic; - output_external : out std_logic; - delay_value : in std_logic_vector(7 downto 0); - width_value_inhibit : in std_logic_vector(7 downto 0); - width_value_external : in std_logic_vector(7 downto 0) - ); -end beam_ramp; - -architecture Behavioral of beam_ramp is - -signal count_ck : std_logic_vector(23 downto 0); -signal clk_10Hz : std_logic; -signal input_r, input_q, output_s_inhibit, output_s_external : std_logic; -signal count_delay, count_width_inhibit, count_width_external : std_logic_vector(7 downto 0); -type state_type is (reset, del, wid); -signal state : state_type; - - - -begin - - ck: process(clk_50MHz) - begin - if rising_edge(clk_50MHz) then - if count_ck = x"2625a0" then --2,5e6 - count_ck <= x"000000"; - clk_10Hz <= not clk_10Hz; - else - count_ck <= count_ck + 1; - end if; - - output_inhibit <= output_s_inhibit; - output_external <= output_s_external; - - end if; - end process; - - latch: process(clk_300MHz) - begin - if rising_edge(clk_300MHz) then - if input_r = '1' then - input_q <= '0'; - elsif input = '1' then - input_q <= '1'; - end if; - - end if; - end process; - - fsm : process(clk_10Hz) - begin - if rising_edge(clk_10Hz) then - case (state) is - - when reset => - input_r <= '0'; - count_delay <=delay_value; - count_width_inhibit <= width_value_inhibit; - count_width_external <= width_value_external + width_value_inhibit; - if input_q = '0' then - state <= reset; - else - state <= del; - end if; - --- when reset => --- input_r <= '0'; --- count_delay <=delay_value; --- count_width_inhibit <= width_value_inhibit + 1; --- count_width_external <= width_value_external + 1; --- if input_q = '0' then --- state <= reset; --- else --- state <= del; --- end if; - - when del => - if count_delay = x"00" then - state <= wid; - else - count_delay <= count_delay - 1; - state <= del; - end if; - - when wid => - input_r <= '1'; - if (count_width_inhibit = x"00" and count_width_external = x"00") then - output_s_inhibit <= '0'; - output_s_external <= '0'; - state <= reset; - elsif count_width_external = x"00" then - output_s_inhibit <= '1'; - output_s_external <= '0'; - count_width_inhibit <= count_width_inhibit - 1; - state <= wid; - elsif count_width_inhibit = x"00" then - output_s_inhibit <= '0'; - output_s_external <= '1'; - count_width_external <= count_width_external - 1; - state <= wid; - else - output_s_inhibit <= '1'; - output_s_external <= '1'; - count_width_inhibit <= count_width_inhibit - 1; - count_width_external <= count_width_external - 1; - state <= wid; - end if; - - when others => - state <= reset; - - end case; - end if; - end process; - - - -end Behavioral; - - - - - - - ---entity beam_ramp is --- port ( clk_300MHz : in std_logic; --- clk_50MHz : in std_logic; --- input : in std_logic; --- output_inhibit : out std_logic; --- output_external : out std_logic; --- delay_value : in std_logic_vector(7 downto 0); --- width_value_inhibit : in std_logic_vector(7 downto 0); --- width_value_external : in std_logic_vector(7 downto 0) --- ); ---end beam_ramp; --- ---architecture Behavioral of beam_ramp is --- ---signal count_ck : std_logic_vector(24 downto 0); ---signal clk_10Hz : std_logic; ---signal input_r, input_q, output_s_inhibit, output_s_external : std_logic; ---signal count_delay, count_width_inhibit, count_width_external : std_logic_vector(7 downto 0); ---type state_type is (reset, del, wid); ---signal state : state_type; --- --- --- ---begin --- --- ck: process(clk_50MHz) --- begin --- if rising_edge(clk_50MHz) then --- count_ck <= count_ck + 1; --- clk_10Hz <= count_ck(22); --- --- output_inhibit <= output_s_inhibit; --- output_external <= output_s_external; --- --- end if; --- end process; --- --- latch: process(clk_300MHz) --- begin --- if rising_edge(clk_300MHz) then --- if input_r = '1' then --- input_q <= '0'; --- elsif input = '1' then --- input_q <= '1'; --- end if; --- --- end if; --- end process; --- --- fsm : process(clk_10Hz) --- begin --- if rising_edge(clk_10Hz) then --- case (state) is --- --- when reset => --- input_r <= '0'; --- count_delay <=delay_value; --- count_width_inhibit <= width_value_inhibit + 1; --- count_width_external <= width_value_external + 1; --- if input_q = '0' then --- state <= reset; --- else --- state <= del; --- end if; --- --- when del => --- if count_delay = x"00" then --- state <= wid; --- else --- count_delay <= count_delay - 1; --- state <= del; --- end if; --- --- when wid => --- input_r <= '1'; --- if (count_width_inhibit = x"00" and count_width_external = x"00") then --- output_s_inhibit <= '0'; --- output_s_external <= '0'; --- state <= reset; --- elsif count_width_external = x"00" then --- output_s_inhibit <= '1'; --- output_s_external <= '0'; --- count_width_inhibit <= count_width_inhibit - 1; --- state <= wid; --- elsif count_width_inhibit = x"00" then --- output_s_inhibit <= '0'; --- output_s_external <= '1'; --- count_width_external <= count_width_external - 1; --- state <= wid; --- else --- output_s_inhibit <= '1'; --- output_s_external <= '1'; --- count_width_inhibit <= count_width_inhibit - 1; --- count_width_external <= count_width_external - 1; --- state <= wid; --- end if; --- --- when others => --- state <= reset; --- --- end case; --- end if; --- end process; --- --- --- ---end Behavioral; \ No newline at end of file diff --git a/oldfiles/vulom3/bus_data_com5.vhd b/oldfiles/vulom3/bus_data_com5.vhd deleted file mode 100644 index e1f18a5..0000000 --- a/oldfiles/vulom3/bus_data_com5.vhd +++ /dev/null @@ -1,766 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 09:54:15 07/11/2007 --- Design Name: vulom3 --- Module Name: bus_data_com4 - Behavioral --- Project Name: triggerbox --- Target Devices: XC4VLX25-10SF363 --- Tool versions: --- Description: Data communication to TRB --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: Whole datastream with 16 bit summer usead as error check --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity bus_data_com5 is - PORT( - clk_300MHz : in std_logic; - clk_100MHz : in std_logic; - gts_pulse : in std_logic; - cal_trigger : in std_logic; - bus_busy : in std_logic; -- not used - bus_ack : in std_logic; - bus_retx : in std_logic; - latch : in std_logic_vector(6 downto 0); - latch_dsc : in std_logic_vector(6 downto 0); - scaler_pti1 : in std_logic_vector(31 downto 0); - scaler_pti2 : in std_logic_vector(31 downto 0); - scaler_pti3 : in std_logic_vector(31 downto 0); - scaler_pti4 : in std_logic_vector(31 downto 0); - scaler_pti5 : in std_logic_vector(31 downto 0); - scaler_ts : in std_logic_vector(31 downto 0); - scaler_vs : in std_logic_vector(31 downto 0); - scaler_dead : in std_logic_vector(31 downto 0); - bus_inhibit : out std_logic; - dtu_inhibit : out std_logic; - ecl_bus_data : out std_logic_vector(1 downto 0); - ecl_bus_clk : out std_logic; - com_run : in std_logic; - dtu_bus_t : out std_logic; - dtu_bus_ts : out std_logic; - dtu_bus_td : out std_logic_vector (3 downto 0); - DTU_CODE_SELECT : in std_logic_vector(4 downto 0); - out_inhibit : in std_logic; - cal_inhibit : in std_logic; - DEBUG_REG_01 : out std_logic_vector(15 downto 0); - TRB_BUSY_ENABLE : in std_logic - ); - -end bus_data_com5; - -architecture Behavioral of bus_data_com5 is -signal count : integer range 0 to 300 := 0; -signal tag_counter_trb, tag_counter_dtu : std_logic_vector(15 downto 0):=x"0000"; -signal cal_trigger_s, cal_trigger_d1, cal_trigger_pulse, cal_trigger_pulse_d, bus_busy_s, bus_busy_d1 : std_logic := '0'; -type state_type_a is (ready, start_sequence_0, start_sequence_1, start_sequence_2, start_sequence_3, - start_sequence_4, start_sequence_5, start_sequence_6, start_sequence_7, - normal_code_0, normal_code_1, calib_code_0, calib_code_1, - xfer_0, xfer_0alter, xfer_1, xfer_2, xfer_3, xfer_4, xfer_5, xfer_6, - xfer_7, xfer_8, xfer_9, xfer_10, xfer_11, xfer_12, xfer_13, xfer_14, xfer_15, - wait_for_busy, hold_busy); -signal state_a : state_type_a; -type state_type_b is (tag, latches, scalers_0, scalers_1, scalers_2, scalers_3, scalers_4, scalers_5, - scalers_6, scalers_7, scalers_8, scalers_9, scalers_10, scalers_11, scalers_12, - scalers_13, scalers_14, scalers_15, checksum_0, checksum_1, finished); -signal state_b : state_type_b; -type state_type_c is (idle, begin_run_0, begin_run_1, end_run_0, end_run_1, norm_event_0, norm_event_1, - calib_event_0, calib_event_1, tag_low_0, tag_low_1, tag_high_0, tag_high_1, - tag_prio_0, tag_prio_1, wait_last, count_incr, wait_for_trb); -signal state_c : state_type_c; - -signal xfer_buffer : std_logic_vector(15 downto 0):=x"0000"; -signal latch_s, latch_dsc_s : std_logic_vector(6 downto 0):="0000000"; -signal gts_trb_r, gts_trb_q, gts_q_d, gts_dtu_r, gts_dtu_q : std_logic := '0'; -signal checksum : std_logic_vector(31 downto 0):=x"00000000"; -signal scaler_pti1_s, scaler_pti2_s, scaler_pti3_s, scaler_pti4_s, scaler_pti5_s, scaler_ts_s, - scaler_vs_s, scaler_dead_s : std_logic_vector(31 downto 0); -signal com_run_s, trb_run, trb_run_s, bus_ack_s, bus_retx_s : std_logic:='0'; -signal ack_accu, retx_accu : std_logic_vector(3 downto 0); -signal gts_from_trb, cal_trigger_from_trb : std_logic:='0'; -signal trb_go_norm, trb_go_norm_s, trb_go_calib, trb_go_calib_s, trb_finished : std_logic; -signal dtu_start : std_logic; -signal dtu_code : std_logic_vector(3 downto 0); -signal prepared_code : std_logic_vector(3 downto 0); -begin - delay : process(clk_100MHz) - begin - if rising_edge(clk_100MHz) then - scaler_pti1_s <= scaler_pti1; - scaler_pti2_s <= scaler_pti2; - scaler_pti3_s <= scaler_pti3; - scaler_pti4_s <= scaler_pti4; - scaler_pti5_s <= scaler_pti5; - scaler_ts_s <= scaler_ts; - scaler_vs_s <= scaler_vs; - scaler_dead_s <= scaler_dead; - latch_s <= latch; - latch_dsc_s <= latch_dsc; - bus_busy_s <= bus_busy; - bus_ack_s <= bus_ack; - bus_retx_s <= bus_retx; - end if; - end process; - input_gts : process(clk_300MHz) - begin - if rising_edge(clk_300MHz) then - if gts_dtu_r = '1' then --gts latch for trb bus - gts_dtu_q <= '0'; - elsif gts_pulse = '1' then - gts_dtu_q <= '1'; - end if; - dtu_inhibit <= (not com_run) or dtu_start; --- dtu_inhibit <= dtu_start; - end if; - end process; - input_cal : process(clk_100MHz) - begin - if rising_edge(clk_100MHz) then - cal_trigger_s <= cal_trigger; - cal_trigger_d1 <= cal_trigger_s; - cal_trigger_pulse <= cal_trigger_s and not cal_trigger_d1 and not out_inhibit; - end if; - end process; ----------------------------------------------------------------------- TRB comm - fsm : process(clk_100MHz) --TX lenght: 3.1-3.2 µs - begin - if rising_edge(clk_100MHz) then - if com_run = '0' then - state_a <= ready; - else - case state_a is - when ready => - DEBUG_REG_01(4 downto 0) <= "00001"; - ecl_bus_data <= "00"; - ecl_bus_clk <= '0'; - bus_inhibit <= '0'; - trb_finished <= '1'; - trb_go_norm_s <= trb_go_norm; - trb_go_calib_s <= trb_go_calib; - if (trb_go_norm or trb_go_calib) = '1' then - state_a <= start_sequence_0; - else state_a <= ready; - end if; ----------------------------- - when start_sequence_0 => - DEBUG_REG_01(4 downto 0) <= "00010"; - trb_finished <= '0'; - bus_inhibit <= '1'; - ecl_bus_data <= "01"; - ecl_bus_clk <= '0'; - ack_accu <= "0000"; - retx_accu <= "0000"; - state_a <= start_sequence_1; - when start_sequence_1 => - DEBUG_REG_01(4 downto 0) <= "00011"; - gts_trb_r <= '1'; - ecl_bus_clk <= '1'; - state_a <= start_sequence_2; - when start_sequence_2 => - DEBUG_REG_01(4 downto 0) <= "00100"; - ecl_bus_data <= "10"; - ecl_bus_clk <= '0'; - state_a <= start_sequence_3; - when start_sequence_3 => - DEBUG_REG_01(4 downto 0) <= "00101"; - ecl_bus_clk <= '1'; - state_a <= start_sequence_4; - when start_sequence_4 => - DEBUG_REG_01(4 downto 0) <= "00110"; - ecl_bus_data <= "01"; - ecl_bus_clk <= '0'; - state_a <= start_sequence_5; - when start_sequence_5 => - DEBUG_REG_01(4 downto 0) <= "00111"; - ecl_bus_clk <= '1'; - state_a <= start_sequence_6; - when start_sequence_6 => - DEBUG_REG_01(4 downto 0) <= "01000"; - ecl_bus_data <= "10"; - ecl_bus_clk <= '0'; - state_a <= start_sequence_7; - when start_sequence_7 => - DEBUG_REG_01(4 downto 0) <= "01001"; - ecl_bus_clk <= '1'; - if trb_go_norm_s = '1' then - state_a <= normal_code_0; - elsif trb_go_calib_s = '1' then - state_a <= calib_code_0; - else state_a <= ready; - end if; ----------------------------------------------- - when normal_code_0 => - DEBUG_REG_01(4 downto 0) <= "01010"; - ecl_bus_data <= "01"; - ecl_bus_clk <= '0'; - state_a <= normal_code_1; - when normal_code_1 => - DEBUG_REG_01(4 downto 0) <= "01011"; - checksum <= x"00000001"; - ecl_bus_clk <= '1'; - state_a <= xfer_0; - when calib_code_0 => - DEBUG_REG_01(4 downto 0) <= "01100"; - ecl_bus_data <= "11"; - ecl_bus_clk <= '0'; - state_a <= calib_code_1; - when calib_code_1 => - DEBUG_REG_01(4 downto 0) <= "01101"; - checksum <= x"00000003"; - ecl_bus_clk <= '1'; - state_a <= xfer_0; ---------------------------------------------------- - when xfer_0 => - DEBUG_REG_01(4 downto 0) <= "01110"; - checksum <= checksum + xfer_buffer; - ecl_bus_data <= xfer_buffer(1 downto 0); - ecl_bus_clk <= '0'; - state_a <= xfer_1; - when xfer_0alter => - DEBUG_REG_01(4 downto 0) <= "01111"; - ecl_bus_data <= xfer_buffer(1 downto 0); - ecl_bus_clk <= '0'; - state_a <= xfer_1; - when xfer_1 => - DEBUG_REG_01(4 downto 0) <= "10000"; - ecl_bus_clk <= '1'; - state_a <= xfer_2; - when xfer_2 => - DEBUG_REG_01(4 downto 0) <= "10001"; - ecl_bus_data <= xfer_buffer(3 downto 2); - ecl_bus_clk <= '0'; - state_a <= xfer_3; - when xfer_3 => - DEBUG_REG_01(4 downto 0) <= "10010"; - ecl_bus_clk <= '1'; - state_a <= xfer_4; - when xfer_4 => - DEBUG_REG_01(4 downto 0) <= "10011"; - ecl_bus_data <= xfer_buffer(5 downto 4); - ecl_bus_clk <= '0'; - state_a <= xfer_5; - when xfer_5 => - DEBUG_REG_01(4 downto 0) <= "10100"; - ecl_bus_clk <= '1'; - state_a <= xfer_6; - when xfer_6 => - DEBUG_REG_01(4 downto 0) <= "10101"; - ecl_bus_data <= xfer_buffer(7 downto 6); - ecl_bus_clk <= '0'; - state_a <= xfer_7; - when xfer_7 => - DEBUG_REG_01(4 downto 0) <= "10110"; - ecl_bus_clk <= '1'; - state_a <= xfer_8; - when xfer_8 => - DEBUG_REG_01(4 downto 0) <= "10111"; - ecl_bus_data <= xfer_buffer(9 downto 8); - ecl_bus_clk <= '0'; - state_a <= xfer_9; - when xfer_9 => - DEBUG_REG_01(4 downto 0) <= "11000"; - ecl_bus_clk <= '1'; - state_a <= xfer_10; - when xfer_10 => - DEBUG_REG_01(4 downto 0) <= "11001"; - ecl_bus_data <= xfer_buffer(11 downto 10); - ecl_bus_clk <= '0'; - state_a <= xfer_11; - - when xfer_11 => - DEBUG_REG_01(4 downto 0) <= "11010"; - ecl_bus_clk <= '1'; - state_a <= xfer_12; - when xfer_12 => - DEBUG_REG_01(4 downto 0) <= "11011"; - ecl_bus_data <= xfer_buffer(13 downto 12); - ecl_bus_clk <= '0'; - state_a <= xfer_13; - when xfer_13 => - DEBUG_REG_01(4 downto 0) <= "11100"; - ecl_bus_clk <= '1'; - state_a <= xfer_14; - when xfer_14 => - DEBUG_REG_01(4 downto 0) <= "11101"; - ecl_bus_data <= xfer_buffer(15 downto 14); - ecl_bus_clk <= '0'; - state_a <= xfer_15; - when xfer_15 => - DEBUG_REG_01(4 downto 0) <= "11110"; - ecl_bus_clk <= '1'; - state_a <= xfer_6; - if state_b = checksum_0 then - state_a <= xfer_0alter; - elsif state_b = checksum_1 then - state_a <= xfer_0alter; - elsif state_b = finished then - state_a <= wait_for_busy; - else state_a <= xfer_0; - end if; ------------------------------------------------------ - when wait_for_busy => - DEBUG_REG_01(4 downto 0) <= "11110"; - ecl_bus_clk <= '0'; - ecl_bus_data <= "00"; - state_a <= hold_busy; - when hold_busy => - DEBUG_REG_01(4 downto 0) <= "11111"; - if bus_ack_s = '0' and ack_accu /= "0000" then --ack accumulator - ack_accu <= ack_accu - 1; - elsif bus_ack_s = '1' and ack_accu /= "1111" then - ack_accu <= ack_accu + 1; - end if; - if bus_retx_s = '0' and retx_accu /= "0000" then --retransmit accumulator - retx_accu <= retx_accu - 1; - elsif bus_retx_s = '1' and retx_accu /= "1111" then - retx_accu <= retx_accu + 1; - end if; - if retx_accu = 10 then - state_a <= start_sequence_0; - elsif (ack_accu = 10 or com_run = '0') or TRB_BUSY_ENABLE = '0' then - state_a <= ready; - else state_a <= hold_busy; - end if; ---------------------------------------------------------------------- - when others => - DEBUG_REG_01(4 downto 0) <= "00000"; - state_a <= ready; - end case; - end if; - end if; - end process; - fsm2 : process(clk_100MHz) - begin - if rising_edge(clk_100MHz) then - if com_run = '0' then - state_b <= tag; - else - case state_b is - when tag => - DEBUG_REG_01(9 downto 5) <= "00001"; - xfer_buffer <= tag_counter_dtu - 1; - if state_a = xfer_13 then - state_b <= latches; - else state_b <= tag; - end if; - when latches => - DEBUG_REG_01(9 downto 5) <= "00010"; - xfer_buffer <= '0' & latch_dsc_s & '0' & latch_s; - if state_a = xfer_13 then - state_b <= scalers_0; - else state_b <= latches; - end if; - when scalers_0 => - DEBUG_REG_01(9 downto 5) <= "00011"; - xfer_buffer <= scaler_pti1_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_1; - else state_b <= scalers_0; - end if; - when scalers_1 => - DEBUG_REG_01(9 downto 5) <= "00100"; - xfer_buffer <= scaler_pti1_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_2; - else state_b <= scalers_1; - end if; - when scalers_2 => - DEBUG_REG_01(9 downto 5) <= "00101"; - xfer_buffer <= scaler_pti2_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_3; - else state_b <= scalers_2; - end if; - when scalers_3 => - DEBUG_REG_01(9 downto 5) <= "00110"; - xfer_buffer <= scaler_pti2_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_4; - else state_b <= scalers_3; - end if; - when scalers_4 => - DEBUG_REG_01(9 downto 5) <= "00111"; - xfer_buffer <= scaler_pti3_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_5; - else state_b <= scalers_4; - end if; - when scalers_5 => - DEBUG_REG_01(9 downto 5) <= "01000"; - xfer_buffer <= scaler_pti3_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_6; - else state_b <= scalers_5; - end if; - when scalers_6 => - DEBUG_REG_01(9 downto 5) <= "01001"; - xfer_buffer <= scaler_pti4_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_7; - else state_b <= scalers_6; - end if; - when scalers_7 => - DEBUG_REG_01(9 downto 5) <= "01010"; - xfer_buffer <= scaler_pti4_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_8; - else state_b <= scalers_7; - end if; - when scalers_8 => - DEBUG_REG_01(9 downto 5) <= "01011"; - xfer_buffer <= scaler_pti5_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_9; - else state_b <= scalers_8; - end if; - when scalers_9 => - DEBUG_REG_01(9 downto 5) <= "01100"; - xfer_buffer <= scaler_pti5_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_10; - else state_b <= scalers_9; - end if; - when scalers_10 => - DEBUG_REG_01(9 downto 5) <= "01110"; - xfer_buffer <= scaler_ts_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_11; - else state_b <= scalers_10; - end if; - when scalers_11 => - DEBUG_REG_01(9 downto 5) <= "01111"; - xfer_buffer <= scaler_ts_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_12; - else state_b <= scalers_11; - end if; - when scalers_12 => - DEBUG_REG_01(9 downto 5) <= "10000"; - xfer_buffer <= scaler_vs_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_13; - else state_b <= scalers_12; - end if; - when scalers_13 => - DEBUG_REG_01(9 downto 5) <= "10001"; - xfer_buffer <= scaler_vs_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_14; - else state_b <= scalers_13; - end if; - when scalers_14 => - DEBUG_REG_01(9 downto 5) <= "10010"; - xfer_buffer <= scaler_dead_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_15; - else state_b <= scalers_14; - end if; - when scalers_15 => - DEBUG_REG_01(9 downto 5) <= "10011"; - xfer_buffer <= scaler_dead_s(31 downto 16); - if state_a = xfer_13 then - state_b <= checksum_0; - else state_b <= scalers_15; - end if; - when checksum_0 => - DEBUG_REG_01(9 downto 5) <= "10101"; - xfer_buffer <= checksum(15 downto 0); - if state_a = xfer_13 then - state_b <= checksum_1; - else state_b <= checksum_0; - end if; - when checksum_1 => - DEBUG_REG_01(9 downto 5) <= "10110"; - xfer_buffer <= checksum(31 downto 16); - if state_a = xfer_13 then - state_b <= finished; - else state_b <= checksum_1; - end if; - when finished => - DEBUG_REG_01(9 downto 5) <= "10111"; - xfer_buffer <= x"0000"; - if state_a = wait_for_busy then - state_b <= tag; - else state_b <= finished; - end if; - when others => - DEBUG_REG_01(9 downto 5) <= "00000"; - state_b <= tag; - end case; - end if; - end if; - end process; ----------------------------------------------------------------------- DTU comm - PREPARE_CODE_FOR_DTU: process (clk_100MHz) - begin -- process PREPARE_CODE_FOR_DTU - if rising_edge(clk_100MHz) then - if com_run_s = '0' then - prepared_code <= x"d"; - elsif com_run_s = '1' and cal_inhibit = '0' then - prepared_code <= dtu_code; - elsif com_run_s = '1' and cal_inhibit = '1' then - prepared_code <= x"9"; - else - prepared_code <= dtu_code; - end if; - end if; - end process PREPARE_CODE_FOR_DTU; - DTU_CODE_CHANGE : process (clk_100MHz) - begin -- process DTU_CODE_CHANGE - if rising_edge (clk_100MHz) then - if DTU_CODE_SELECT(4) = '0' then - dtu_code <= x"1"; - else - dtu_code <= DTU_CODE_SELECT(3 downto 0); - end if; - end if; - end process DTU_CODE_CHANGE; - fsm3 : process(clk_100MHz) --TX lenght: 470 ns + wait time (currently 2.5 µs total) - begin - if rising_edge(clk_100MHz) then - if com_run = '0' then - state_c <= idle; - com_run_s <= '0'; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"d"; - count <= 0; - trb_go_norm <= '0'; - trb_go_calib <= '0'; - gts_dtu_r <= '0'; - dtu_start <= '0'; - else - -- implemented default value - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; --- dtu_bus_td <= x"d"; - dtu_bus_td <= prepared_code; - case state_c is - when idle => - DEBUG_REG_01(14 downto 10)<= "00001"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; --- dtu_bus_td <= x"d"; - count <= 0; - trb_go_norm <= '0'; - trb_go_calib <= '0'; - gts_dtu_r <= '0'; - dtu_start <= '0'; --- com_run_s <= com_run; --- if com_run = '1' and com_run_s = '0' then - if com_run = '1' and com_run_s = '0' then - state_c <= begin_run_0; --- elsif com_run = '0' and com_run_s = '1' then --- state_c <= end_run_0; - elsif gts_dtu_q = '1' and com_run = '1' then - state_c <= norm_event_0; - elsif cal_trigger_pulse = '1' and com_run = '1' then - state_c <= calib_event_0; - else state_c <= idle; - end if; ------------------------------------- - when begin_run_0 => - DEBUG_REG_01(14 downto 10)<= "00010"; - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"d"; - -- trb_go_norm <= '1'; - tag_counter_dtu <= x"0000"; - com_run_s <= '1'; - dtu_start <= '1'; - count <= count + 1; - if count = 4+5 then - state_c <= begin_run_1; - else state_c <= begin_run_0; - end if; - when begin_run_1 => - DEBUG_REG_01(14 downto 10)<= "00011"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"d"; - count <= count + 1; - if count = 9+10 then - state_c <= tag_low_0; - else state_c <= begin_run_1; - end if; -------------------------------------- - when end_run_0 => - DEBUG_REG_01(14 downto 10)<= "00100"; - trb_run_s <= '0'; - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"e"; - count <= count + 1; - if count = 4+5 then - state_c <= end_run_1; - else state_c <= end_run_0; - end if; - when end_run_1 => - DEBUG_REG_01(14 downto 10)<= "00101"; - trb_run <= '0'; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 9+10 then - state_c <= tag_low_0; - else state_c <= end_run_1; - end if; --------------------------------------- - when norm_event_0 => - DEBUG_REG_01(14 downto 10)<= "00110"; - trb_go_norm <= '1'; - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= dtu_code;-- "1"; - count <= count + 1; - if count = 4+5 then - state_c <= norm_event_1; - else state_c <= norm_event_0; - end if; - when norm_event_1 => - DEBUG_REG_01(14 downto 10)<= "00111"; - trb_go_norm <= '0'; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= dtu_code; - count <= count + 1; - if count = 9+10 then - state_c <= tag_low_0; - else state_c <= norm_event_1; - end if; ---------------------------------------- - when calib_event_0 => - DEBUG_REG_01(14 downto 10)<= "01000"; - trb_go_calib <= '1'; - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"9"; - count <= count + 1; - if count = 4+5 then - state_c <= calib_event_1; - else state_c <= calib_event_0; - end if; - when calib_event_1 => - DEBUG_REG_01(14 downto 10)<= "01001"; - trb_go_calib <= '0'; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"9"; - count <= count + 1; - if count = 9+10 then - state_c <= tag_low_0; - else state_c <= calib_event_1; - end if; ---------------------------------------------------------- - when tag_low_0 => - DEBUG_REG_01(14 downto 10)<= "01010"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '1'; - dtu_bus_td <= tag_counter_dtu(3 downto 0); - count <= count + 1; - if count = 14+15 then - state_c <= tag_low_1; - else state_c <= tag_low_0; - end if; - when tag_low_1 => - DEBUG_REG_01(14 downto 10)<= "01011"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= tag_counter_dtu(3 downto 0); - count <= count + 1; - if count = 19+20 then - state_c <= tag_high_0; - else state_c <= tag_low_1; - end if; - when tag_high_0 => - DEBUG_REG_01(14 downto 10)<= "01100"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '1'; - dtu_bus_td <= tag_counter_dtu(7 downto 4); - count <= count + 1; - if count = 24+25 then - state_c <= tag_high_1; - else state_c <= tag_high_0; - end if; - when tag_high_1 => - DEBUG_REG_01(14 downto 10)<= "01101"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= tag_counter_dtu(7 downto 4); - count <= count + 1; - if count = 29+30 then - state_c <= tag_prio_0; - else state_c <= tag_high_1; - end if; - when tag_prio_0 => - DEBUG_REG_01(14 downto 10)<= "01110"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '1'; - dtu_bus_td <= tag_counter_dtu(7 downto 4); - count <= count + 1; - if count = 34+35 then - state_c <= tag_prio_1; - else state_c <= tag_prio_0; - end if; - when tag_prio_1 => - DEBUG_REG_01(14 downto 10)<= "01111"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - dtu_bus_td <= tag_counter_dtu(7 downto 4); - if count = 39+40 then - state_c <= wait_last; - else state_c <= tag_prio_1; - end if; - when wait_last => - DEBUG_REG_01(14 downto 10)<= "10000"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; --- dtu_bus_td <= "0000"; - count <= count + 1; - if count = 244 then --change this to increase wait time (44 default) - state_c <= wait_for_trb; - else state_c <= wait_last; - end if; - when wait_for_trb => - DEBUG_REG_01(14 downto 10)<= "10001"; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; --- dtu_bus_td <= "0000"; - if trb_finished = '1' or dtu_start = '1' then - state_c <= count_incr; - else state_c <= wait_for_trb; - end if; - when count_incr => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; --- dtu_bus_td <= "0000"; - DEBUG_REG_01(14 downto 10)<= "10010"; - gts_dtu_r <= '1'; - tag_counter_dtu <= tag_counter_dtu + 1; - state_c <= idle; - when others => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; --- dtu_bus_td <= "0000"; - DEBUG_REG_01(14 downto 10)<= "00000"; - state_c <= idle; - end case; - end if; - end if; - end process; -end Behavioral; diff --git a/oldfiles/vulom3/clocking.vhd b/oldfiles/vulom3/clocking.vhd deleted file mode 100644 index 7c22363..0000000 --- a/oldfiles/vulom3/clocking.vhd +++ /dev/null @@ -1,168 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. --------------------------------------------------------------------------------- --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version : 9.1.03i --- \ \ Application : xaw2vhdl --- / / Filename : clocking.vhd --- /___/ /\ Timestamp : 02/25/2008 15:07:58 --- \ \ / \ --- \___\/\___\ --- ---Command: xaw2vhdl-intstyle /home/davide/Fpga_projects/vulom3/clocking.xaw -st clocking.vhd ---Design Name: clocking ---Device: xc4vlx25-10sf363 --- --- Module clocking --- Generated by Xilinx Architecture Wizard --- Written for synthesis tool: XST - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.numeric_std.ALL; -library UNISIM; -use UNISIM.Vcomponents.ALL; - -entity clocking is - port ( CLKIN_IN : in std_logic; - CLKDV_OUT : out std_logic; - CLKFX_OUT : out std_logic; - CLKIN_IBUFG_OUT : out std_logic; - CLK0_OUT : out std_logic; - LOCKED_OUT : out std_logic); -end clocking; - -architecture BEHAVIORAL of clocking is - signal CLKDV_BUF : std_logic; - signal CLKFB_IN : std_logic; - signal CLKFX_BUF : std_logic; - signal CLKIN_IBUFG : std_logic; - signal CLK0_BUF : std_logic; - signal GND_BIT : std_logic; - signal GND_BUS_7 : std_logic_vector (6 downto 0); - signal GND_BUS_16 : std_logic_vector (15 downto 0); - component BUFG - port ( I : in std_logic; - O : out std_logic); - end component; - - component IBUFG - port ( I : in std_logic; - O : out std_logic); - end component; - - -- Period Jitter (unit interval) for block DCM_ADV_INST = 0.044 UI - -- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.146 ns - component DCM_ADV - generic( CLK_FEEDBACK : string := "1X"; - CLKDV_DIVIDE : real := 2.0; - CLKFX_DIVIDE : integer := 1; - CLKFX_MULTIPLY : integer := 4; - CLKIN_DIVIDE_BY_2 : boolean := FALSE; - CLKIN_PERIOD : real := 10.0; - CLKOUT_PHASE_SHIFT : string := "NONE"; - DCM_AUTOCALIBRATION : boolean := TRUE; - DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; - DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; - DFS_FREQUENCY_MODE : string := "LOW"; - DLL_FREQUENCY_MODE : string := "LOW"; - DUTY_CYCLE_CORRECTION : boolean := TRUE; - FACTORY_JF : bit_vector := x"F0F0"; - PHASE_SHIFT : integer := 0; - STARTUP_WAIT : boolean := FALSE; - SIM_DEVICE : string := "VIRTEX4"); - port ( CLKIN : in std_logic; - CLKFB : in std_logic; - DADDR : in std_logic_vector (6 downto 0); - DI : in std_logic_vector (15 downto 0); - DWE : in std_logic; - DEN : in std_logic; - DCLK : in std_logic; - RST : in std_logic; - PSEN : in std_logic; - PSINCDEC : in std_logic; - PSCLK : in std_logic; - CLK0 : out std_logic; - CLK90 : out std_logic; - CLK180 : out std_logic; - CLK270 : out std_logic; - CLKDV : out std_logic; - CLK2X : out std_logic; - CLK2X180 : out std_logic; - CLKFX : out std_logic; - CLKFX180 : out std_logic; - DRDY : out std_logic; - DO : out std_logic_vector (15 downto 0); - LOCKED : out std_logic; - PSDONE : out std_logic); - end component; - -begin - GND_BIT <= '0'; - GND_BUS_7(6 downto 0) <= "0000000"; - GND_BUS_16(15 downto 0) <= "0000000000000000"; - CLKIN_IBUFG_OUT <= CLKIN_IBUFG; - CLK0_OUT <= CLKFB_IN; - CLKDV_BUFG_INST : BUFG - port map (I=>CLKDV_BUF, - O=>CLKDV_OUT); - - CLKFX_BUFG_INST : BUFG - port map (I=>CLKFX_BUF, - O=>CLKFX_OUT); - - CLKIN_IBUFG_INST : IBUFG - port map (I=>CLKIN_IN, - O=>CLKIN_IBUFG); - - CLK0_BUFG_INST : BUFG - port map (I=>CLK0_BUF, - O=>CLKFB_IN); - - DCM_ADV_INST : DCM_ADV - generic map( CLK_FEEDBACK => "1X", - CLKDV_DIVIDE => 2.0, - CLKFX_DIVIDE => 1, - CLKFX_MULTIPLY => 3, - CLKIN_DIVIDE_BY_2 => FALSE, - CLKIN_PERIOD => 10.000, - CLKOUT_PHASE_SHIFT => "NONE", - DCM_AUTOCALIBRATION => TRUE, - DCM_PERFORMANCE_MODE => "MAX_SPEED", - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", - DFS_FREQUENCY_MODE => "HIGH", - DLL_FREQUENCY_MODE => "LOW", - DUTY_CYCLE_CORRECTION => TRUE, - FACTORY_JF => x"F0F0", - PHASE_SHIFT => 0, - STARTUP_WAIT => FALSE) - port map (CLKFB=>CLKFB_IN, - CLKIN=>CLKIN_IBUFG, - DADDR(6 downto 0)=>GND_BUS_7(6 downto 0), - DCLK=>GND_BIT, - DEN=>GND_BIT, - DI(15 downto 0)=>GND_BUS_16(15 downto 0), - DWE=>GND_BIT, - PSCLK=>GND_BIT, - PSEN=>GND_BIT, - PSINCDEC=>GND_BIT, - RST=>GND_BIT, - CLKDV=>CLKDV_BUF, - CLKFX=>CLKFX_BUF, - CLKFX180=>open, - CLK0=>CLK0_BUF, - CLK2X=>open, - CLK2X180=>open, - CLK90=>open, - CLK180=>open, - CLK270=>open, - DO=>open, - DRDY=>open, - LOCKED=>LOCKED_OUT, - PSDONE=>open); - -end BEHAVIORAL; - - diff --git a/oldfiles/vulom3/compile_vulom3.pl b/oldfiles/vulom3/compile_vulom3.pl deleted file mode 100755 index 2e70115..0000000 --- a/oldfiles/vulom3/compile_vulom3.pl +++ /dev/null @@ -1,143 +0,0 @@ -#!/usr/bin/perl -########################################### -# Script file to run the flow -# -########################################### -# -# Command line for synplify_pro -# - - -use FileHandle; - - -$ENV{LM_LICENSE_FILE}="1709\@hadeb05"; - - - -$PLD_DEVICE="xc4vlx25-10-sf363"; -$TOPNAME="vlogic_1"; - - - -#set -e -#set -o errexit - -system("env| grep LM_"); - -#$c="/opt/Synplicity/fpga_861/bin/synplify_pro -batch $TOPNAME"."_syn.prj"; -#$c="/opt/Synplicity/fpga_8804/bin/synplify_pro -batch $TOPNAME"."_syn.prj"; -#$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; -$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; -#$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj"); -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -my $fh = new FileHandle("; -$fh -> close; - -#if ($r) { -#$c="cat $TOPNAME.srr"; -#system($c); -#exit 129; -#} - -foreach (@a) -{ - if(/\@E:/) - { - $c="cat $TOPNAME.srr"; - system($c); - print "bdabdhsadbhjasdhasldhbas"; - exit 129; - } -} -# -# Command line to synthesize -# - -#chdir ".."; -#$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr"; -#execute($c); -#chdir "workdir"; - -# -# Command line for ngdbuild -# -#$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf ../$TOPNAME.ngc $TOPNAME.ngd"; -$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf -sd ../ $TOPNAME.edf $TOPNAME.ngd"; -execute($c); -# -# Command line for fpgafit -# -$c="map -xe n -logic_opt on -retiming on -timing -power off -equivalent_register_removal on -detail -u -p $PLD_DEVICE -cm speed -pr b -k 4 -c 100 -tx off -intstyle xflow -o $TOPNAME"."_map.ncd $TOPNAME.ngd $TOPNAME.pcf"; -execute($c); - -# -# Command line for Place & Route -# - -$c="par -w -intstyle xflow -pl high -rl high -xe n -t 1 $TOPNAME"."_map.ncd $TOPNAME.ncd $TOPNAME.pcf"; -execute($c); - -# -# Command line for genarate programming file (.bit) -# - - -foreach (<$TOPNAME"."_pad.txt>) { - @a=split (/\s*\|\s*/,$_); - if( ($a[2] ne "" && - $a[2] ne "Signal Name") && - $a[13] ne "LOCATED" - ) - { - print "error, pins were assigned automatically:\n$_\n"; - exit; - } -} - -print "_pad.txt tested for automatically assigned pins\n"; - -#$c="bitgen -w -intstyle ise -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No $TOPNAME"; -$c="bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No $TOPNAME.ncd"; - -execute($c); -# -# Command line for generate .stapl file -# - -$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch_vulom3.txt"; - -execute($c); - - -#ssh depc152 'cd ~/files/vhdl/xilinx; . ~/bin/xilinx_setup; XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch conf_xilinx_impact.txt ' - -# -#to download file on ETRAX chip -# - -#$c="lftp root:pass@hades18;put RPCBoardContrller;exit"; -#execute($c) - -chdir ".."; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/oldfiles/vulom3/delay.vhd b/oldfiles/vulom3/delay.vhd deleted file mode 100644 index dda2a8a..0000000 --- a/oldfiles/vulom3/delay.vhd +++ /dev/null @@ -1,60 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 7/3/07 --- Design Name: vulom3 --- Module Name: delay - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: 16 clock cycle programmable delayer --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---library UNISIM; ---use UNISIM.VComponents.all; - -entity delay is port ( - clk : in std_logic; - to_be_delayed : in std_logic; - delay_value : in std_logic_vector(3 downto 0); - delayed_pulse : out std_logic); -end delay; - -architecture Behavioral of delay is -signal shift : std_logic_vector (15 downto 0) := x"0000"; - -begin - - process (clk) - begin - if rising_edge(clk) then - shift <= shift (14 downto 0) & to_be_delayed; - - case delay_value is - when "0000" => delayed_pulse <= shift(0); - when "0001" => delayed_pulse <= shift(1); - when "0010" => delayed_pulse <= shift(2); - when "0011" => delayed_pulse <= shift(3); - when "0100" => delayed_pulse <= shift(4); - when "0101" => delayed_pulse <= shift(5); - when "0110" => delayed_pulse <= shift(6); - when "0111" => delayed_pulse <= shift(7); - when "1000" => delayed_pulse <= shift(8); - when "1001" => delayed_pulse <= shift(9); - when "1010" => delayed_pulse <= shift(10); - when "1011" => delayed_pulse <= shift(11); - when "1100" => delayed_pulse <= shift(12); - when "1101" => delayed_pulse <= shift(13); - when "1110" => delayed_pulse <= shift(14); - when "1111" => delayed_pulse <= shift(15); - when others => delayed_pulse <= 'X'; - end case; - end if; - end process; - -end Behavioral; diff --git a/oldfiles/vulom3/downscale.vhd b/oldfiles/vulom3/downscale.vhd deleted file mode 100644 index 43aea9e..0000000 --- a/oldfiles/vulom3/downscale.vhd +++ /dev/null @@ -1,74 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 7/3/07 --- Design Name: vulom3 --- Module Name: downscale - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: 2^16 programmable divider with output shaper --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.vcomponents.all; ---library UNISIM; ---use UNISIM.VComponents.all; - -entity downscale is port ( - disable : in std_logic; - to_be_downscaled : in std_logic; - downscale_value : in std_logic_vector(3 downto 0); - clk : in std_logic; - downscaled : out std_logic); -end downscale; - -architecture Behavioral of downscale is -signal reset, internal, to_be_downscaled_d : std_logic := '0'; -signal accu : std_logic_vector (15 downto 0) := x"0000"; - -begin - - process(clk) - begin - if rising_edge(clk) then - if disable = '0' then - to_be_downscaled_d <= to_be_downscaled; - else to_be_downscaled_d <= '0'; - end if; - - if to_be_downscaled_d = '1' then - accu <= accu + 1; - end if; - - case downscale_value is - when "0000" => reset <= to_be_downscaled_d; --bypass - when "0001" => reset <= accu(0); - when "0010" => reset <= accu(1); - when "0011" => reset <= accu(2); - when "0100" => reset <= accu(3); - when "0101" => reset <= accu(4); - when "0110" => reset <= accu(5); - when "0111" => reset <= accu(6); - when "1000" => reset <= accu(7); - when "1001" => reset <= accu(8); - when "1010" => reset <= accu(9); - when "1011" => reset <= accu(10); - when "1100" => reset <= accu(11); - when "1101" => reset <= accu(12); - when "1110" => reset <= accu(13); - when "1111" => reset <= accu(14); - when others => reset <= 'X'; - end case; - - internal <= reset; - downscaled <= (not internal) and reset; - end if; - end process; - -end Behavioral; diff --git a/oldfiles/vulom3/eco_delay.vhd b/oldfiles/vulom3/eco_delay.vhd deleted file mode 100644 index 5cae31e..0000000 --- a/oldfiles/vulom3/eco_delay.vhd +++ /dev/null @@ -1,51 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 17:03:24 03/27/2007 --- Design Name: vulom3 --- Module Name: eco_delay - Behavioral --- Project Name: triggerbox --- Target Devices: XC4VLX25-10SF363 --- Tool versions: --- Description: Fixed delayer with fixed output pulse shaper --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---library UNISIM; ---use UNISIM.VComponents.all; - -entity eco_delay is port ( - clk : in std_logic; - signal_in : in std_logic; - signal_out : out std_logic); -end eco_delay; - -architecture Behavioral of eco_delay is -signal chain : std_logic_vector(31 downto 0); -signal internal : std_logic; -signal signal_out_s : std_logic:='0'; - -begin - - signal_out <= signal_out_s; - - process (clk) - begin - if rising_edge(clk) then - internal <= signal_in; - chain <= (chain (30 downto 0) & (not internal and signal_in)); - - if (chain(15) = '1') then - signal_out_s <= '1'; - elsif (chain(15) = '0' and chain(27) ='1') then - signal_out_s <= '0'; - end if; - end if; - end process; - -end Behavioral; - diff --git a/oldfiles/vulom3/impact_batch_vulom3.txt b/oldfiles/vulom3/impact_batch_vulom3.txt deleted file mode 100644 index 5e3fdc1..0000000 --- a/oldfiles/vulom3/impact_batch_vulom3.txt +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bs -setMode -bs -setCable -port stapl -file "../trigger_box1.stapl" -addDevice -p 1 -file "vlogic_1.bit" -Program -p 1 -defaultVersion 0 -quit \ No newline at end of file diff --git a/oldfiles/vulom3/new_downscale_ck.vhd b/oldfiles/vulom3/new_downscale_ck.vhd deleted file mode 100644 index 1165d24..0000000 --- a/oldfiles/vulom3/new_downscale_ck.vhd +++ /dev/null @@ -1,128 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 7/3/07 --- Design Name: vulom3 --- Module Name: new_downscale_ck - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: Provides clock downscale, plus calibration and inhibit signals --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---library UNISIM; ---use UNISIM.VComponents.all; - -entity new_downscale_ck is port ( - downscale_value : in std_logic_vector(3 downto 0); - clk : in std_logic; - downscaled : out std_logic; - output_disable : in std_logic; - global_inhibit : in std_logic; - scaler_reset : out std_logic; - cal_inhibit : out std_logic; - cal_trigger : out std_logic); -end new_downscale_ck; - -architecture Behavioral of new_downscale_ck is -signal accu_1 : std_logic_vector(21 downto 0); -signal accu_3 : std_logic_vector(15 downto 0); -signal accu_4 : std_logic_vector(15 downto 0); -signal count, count_d, clk_10kHz : std_logic; -signal accu_2 : std_logic_vector(15 downto 0); -signal delay_1, delay_2 : std_logic; - - -begin - - process(clk) --pulser - begin - if rising_edge(clk) then - accu_1 <= accu_1 + 1; - case downscale_value is - when "0000" => count <= accu_1(6); - when "0001" => count <= accu_1(7); - when "0010" => count <= accu_1(8); - when "0011" => count <= accu_1(9); - when "0100" => count <= accu_1(10); - when "0101" => count <= accu_1(11); - when "0110" => count <= accu_1(12); - when "0111" => count <= accu_1(13); - when "1000" => count <= accu_1(14); - when "1001" => count <= accu_1(15); - when "1010" => count <= accu_1(16); - when "1011" => count <= accu_1(17); - when "1100" => count <= accu_1(18); - when "1101" => count <= accu_1(19); - when "1110" => count <= accu_1(20); - when "1111" => count <= accu_1(21); - when others => count <= 'X'; - end case; - count_d <= count; - downscaled <= (not count_d) and count; - end if; - end process; - process(clk) --10 kHz clock generator - begin - if rising_edge(clk) then - if accu_2 = x"3a97" then - accu_2 <= x"0000"; - clk_10kHz <= not clk_10kHz; - else - accu_2 <= accu_2 + 1; - end if; - end if; - end process; - process(clk_10kHz) --calibration pulse - begin - if rising_edge(clk_10kHz) then - if accu_3 = x"0000" then - scaler_reset <= '1'; - accu_3 <= accu_3 + 1; - elsif accu_3 = x"0001" then - scaler_reset <= '0'; - accu_3 <= accu_3 + 1; - elsif accu_3 = x"0002" then - scaler_reset <= '0'; - accu_3 <= accu_3 + 1; - elsif accu_3 = x"270f" then --10e3 - scaler_reset <= '0'; - accu_3 <= x"0000"; - else accu_3 <= accu_3 + 1; - end if; - end if; - end process; - process(clk_10kHz) --calibration pulse - begin - if rising_edge(clk_10kHz) then - if accu_4 = x"0000" and global_inhibit = '0' then - cal_inhibit <= not output_disable; - cal_trigger <= '0'; - accu_4 <= accu_4 + 1; - elsif accu_4 = x"0000" and global_inhibit = '1' then - cal_inhibit <= not output_disable; - cal_trigger <= '0'; - accu_4 <= accu_4; - elsif accu_4 = x"0001" then - cal_inhibit <= not output_disable; - cal_trigger <= not output_disable; - accu_4 <= accu_4 + 1; - elsif accu_4 = x"0002" then - cal_inhibit <= '0'; - cal_trigger <= '0'; - accu_4 <= accu_4 + 1; - elsif accu_4 = x"270f" then --10e3 - cal_inhibit <= '0'; - cal_trigger <= '0'; - accu_4 <= x"0000"; - else accu_4 <= accu_4 + 1; - end if; - end if; - end process; - -end Behavioral; diff --git a/oldfiles/vulom3/one_clock_long.vhd b/oldfiles/vulom3/one_clock_long.vhd deleted file mode 100644 index bf79b3e..0000000 --- a/oldfiles/vulom3/one_clock_long.vhd +++ /dev/null @@ -1,48 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 7/3/07 --- Design Name: vulom3 --- Module Name: one_clock_long - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: One clock cycle pulse shaper --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.vcomponents.all; - -entity one_clock_long is port ( - clk : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); -end one_clock_long; - -architecture Behavioral of one_clock_long is -signal internal, signal_in_s : std_logic; - -begin - - process (clk) - begin - if rising_edge(clk) then - signal_in_s <= signal_in; - - if en_clk = '0' then - pulse <= '0'; - else - internal <= signal_in_s; - pulse <= (not internal) and signal_in_s; - end if; - end if; - end process; - -end Behavioral; - diff --git a/oldfiles/vulom3/one_clock_long_test.vhd b/oldfiles/vulom3/one_clock_long_test.vhd deleted file mode 100644 index 2c7ed35..0000000 --- a/oldfiles/vulom3/one_clock_long_test.vhd +++ /dev/null @@ -1,96 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 09:54:36 03/13/2007 --- Design Name: one_clock_long --- Module Name: /home/davide/fuffa/one_clock_long_test.vhd --- Project Name: fuffa --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: one_clock_long --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY one_clock_long_test_vhd IS -END one_clock_long_test_vhd; - -ARCHITECTURE behavior OF one_clock_long_test_vhd IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT one_clock_long - PORT( - clk : IN std_logic; - en_clk : IN std_logic; - signal_in : IN std_logic; - pulse : OUT std_logic - ); - END COMPONENT; - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL en_clk : std_logic := '0'; - SIGNAL signal_in : std_logic := '0'; - - --Outputs - SIGNAL pulse : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: one_clock_long PORT MAP( - clk => clk, - en_clk => en_clk, - signal_in => signal_in, - pulse => pulse - ); - - tb : PROCESS - BEGIN - - clk <= '1'; - wait for 1.42 ns; - clk <= '0'; - wait for 1.42 ns; - - END PROCESS; - - stim : process - begin - en_clk <= '1'; - signal_in <= '0'; - wait for 12.78 ns; - signal_in <= '1'; - wait for 14.2 ns; - signal_in <= '0'; - wait for 14.2 ns; - signal_in <= '1'; - wait for 1.42 ns; - signal_in <= '0'; - wait for 14.2 ns; - signal_in <= '1'; - wait for 14.2 ns; - signal_in <= '0'; - wait; - end process; - -END; \ No newline at end of file diff --git a/oldfiles/vulom3/scaler.vhd b/oldfiles/vulom3/scaler.vhd deleted file mode 100644 index f709a22..0000000 --- a/oldfiles/vulom3/scaler.vhd +++ /dev/null @@ -1,59 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 8/3/07 --- Design Name: vulom3 --- Module Name: scaler - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: 20 bit counter with reset --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity scaler is - Port ( clk : in std_logic; - input_pulse : in std_logic; - scaler_reset : in std_logic; - scaler_value : out std_logic_vector(19 downto 0)); -end scaler; - -architecture Behavioral of scaler is -signal scaled : std_logic_vector(19 downto 0) := x"00000"; - -begin -process(clk) -begin - if rising_edge(clk) then - if scaler_reset = '1' then - scaled <= x"00000"; - elsif (input_pulse = '1' and scaler_reset = '0') then - scaled <= scaled + 1; - end if; - end if; - - --- if rising_edge(clk) then --- if (input_pulse = '1' and scaler_reset = '0') then --- scaled <= scaled + 1; --- elsif scaler_reset = '1' then --- scaled <= x"00000"; --- end if; --- end if; - -scaler_value <= scaled; - -end process; - - -end Behavioral; diff --git a/oldfiles/vulom3/scaler_s.vhd b/oldfiles/vulom3/scaler_s.vhd deleted file mode 100644 index dfefdad..0000000 --- a/oldfiles/vulom3/scaler_s.vhd +++ /dev/null @@ -1,68 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 8/3/07 --- Design Name: vulom3 --- Module Name: scaler_s - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: 32 bit counter with reset --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---library UNISIM; ---use UNISIM.VComponents.all; - -entity scaler_s is port ( - clk_300MHz : in std_logic; - clk_100MHz : in std_logic; - input_pulse : in std_logic; - scaler_reset : in std_logic; - scaler_value : out std_logic_vector(31 downto 0)); -end scaler_s; - -architecture Behavioral of scaler_s is -signal scaled : std_logic_vector(31 downto 0) := x"00000000"; -signal r, q : std_logic; -signal input_pulse_d, shaped_input, scaler_reset_d, shaped_reset : std_logic; - -begin - - process(clk_300MHz) - begin - if rising_edge(clk_300MHz) then - input_pulse_d <= input_pulse; - shaped_input <= input_pulse and not input_pulse_d; -- 1 ck shaper - - if r = '1' then -- flip-flop - q <= '0'; - elsif shaped_input = '1' then - q <= '1'; - end if; - end if; - end process; - - process(clk_100MHz) - begin - if rising_edge(clk_100MHz) then - scaler_reset_d <= scaler_reset; -- 1 ck shaper - shaped_reset <= scaler_reset and not scaler_reset_d; - - if shaped_reset = '1' then - scaled <= x"00000000"; - scaler_value <= scaled; - elsif r = '1' then - r <= '0'; - elsif q = '1' then - scaled <= scaled + 1; - r <= '1'; - end if; - end if; - end process; - -end Behavioral; diff --git a/oldfiles/vulom3/set_width.vhd b/oldfiles/vulom3/set_width.vhd deleted file mode 100644 index 070698e..0000000 --- a/oldfiles/vulom3/set_width.vhd +++ /dev/null @@ -1,69 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 8/3/07 --- Design Name: vulom3 --- Module Name: set_width - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: 16 clock cycle programmable pulse shaper --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.vcomponents.all; - -entity set_width is port ( - clk : in std_logic; - to_be_set : in std_logic; - width_value : in std_logic_vector(3 downto 0); - width_adjusted_pulse : out std_logic); -end set_width; - -architecture Behavioral of set_width is -signal reset, to_be_set_delayed, q : std_logic; -signal shift :std_logic_vector (15 downto 0); - -begin - - process (clk) - begin - - if rising_edge(clk) then - shift <= shift (14 downto 0) & to_be_set; - to_be_set_delayed <= to_be_set; - - case width_value is - when "0000" => reset <= shift(0); - when "0001" => reset <= shift(1); - when "0010" => reset <= shift(2); - when "0011" => reset <= shift(3); - when "0100" => reset <= shift(4); - when "0101" => reset <= shift(5); - when "0110" => reset <= shift(6); - when "0111" => reset <= shift(7); - when "1000" => reset <= shift(8); - when "1001" => reset <= shift(9); - when "1010" => reset <= shift(10); - when "1011" => reset <= shift(11); - when "1100" => reset <= shift(12); - when "1101" => reset <= shift(13); - when "1110" => reset <= shift(14); - when "1111" => reset <= shift(15); - when others => reset <= 'X'; - end case; - - if (to_be_set_delayed = '0' and reset ='1') then - width_adjusted_pulse <= '0'; - elsif (to_be_set_delayed = '1' and reset ='0') then - width_adjusted_pulse <= '1'; - end if; - end if; - end process; - -end Behavioral; diff --git a/oldfiles/vulom3/set_width_special.vhd b/oldfiles/vulom3/set_width_special.vhd deleted file mode 100644 index adebea9..0000000 --- a/oldfiles/vulom3/set_width_special.vhd +++ /dev/null @@ -1,83 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 8/3/07 --- Design Name: vulom3 --- Module Name: set_width_special - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: 16 clock cycle programmable pulse shaper specific for output --- (it can handle pulses wider than 1 ck cycle) --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.vcomponents.all; - -entity set_width_special is port ( - clk : in std_logic; - to_be_set : in std_logic; - width_value : in std_logic_vector(3 downto 0); - width_adjusted_pulse : out std_logic); -end set_width_special; - -architecture Behavioral of set_width_special is -signal reset_timing_signal, clocked_timing_signal : std_logic; -signal timing_signal_counter : std_logic_vector(5 downto 0); -signal start_pulse, end_pulse : std_logic; -signal during_pulse, to_be_set_synch, to_be_set_synch_delayed : std_logic; - -begin - - SYNCH_TO_BE_SET: process (CLK) - begin - if rising_edge(CLK) then - to_be_set_synch <= to_be_set; - to_be_set_synch_delayed <= to_be_set_synch; - end if; - end process SYNCH_TO_BE_SET; - MAKE_START: process (CLK) - begin - if rising_edge(CLK) then - if to_be_set_synch_delayed = '0' and to_be_set_synch = '1' then - start_pulse <= '1'; - end_pulse <= '0'; - elsif to_be_set_synch_delayed = '1' and to_be_set_synch = '0' then - start_pulse <= '0'; - end_pulse <= '1'; - else - start_pulse <= '0'; - end_pulse <= '0'; - end if; - end if; - end process MAKE_START; - DURING_PULSE_PROC: process (CLK) - begin - if rising_edge(CLK) then - if start_pulse = '1' then - during_pulse <= '1'; - elsif timing_signal_counter(5) = '1' then - during_pulse <= '0'; - end if; - end if; - end process DURING_PULSE_PROC; - - - PULSER_LENGHT_COUNTER: process (CLK) - begin - if rising_edge(CLK) then - if during_pulse = '1' then - timing_signal_counter <= timing_signal_counter + 1; - elsif start_pulse = '1' then - timing_signal_counter <= (others => '0'); - else - timing_signal_counter <= timing_signal_counter; - end if; - end if; - end process PULSER_LENGHT_COUNTER; - width_adjusted_pulse <= during_pulse;--to_be_set or during_pulse; -end Behavioral; diff --git a/oldfiles/vulom3/trig_box1.vhd b/oldfiles/vulom3/trig_box1.vhd deleted file mode 100644 index 194ef61..0000000 --- a/oldfiles/vulom3/trig_box1.vhd +++ /dev/null @@ -1,960 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 9/3/07 --- Design Name: vulom3 --- Module Name: trig_box1 - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: Triggerbox --- NOTE (1): To enable TOF/MDC part comment lines (a) and (b) and uncomment (c) --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.Vcomponents.ALL; - -entity trig_box1 is - port (clk_50MHz : in std_logic; - clk_300MHz : in std_logic; - clk_100MHz : in std_logic; - ECL : in std_logic_vector(16 downto 1); - ECO : out std_logic_vector(16 downto 1); - IOO : in std_logic_vector(16 downto 1); - TIN : out std_logic_vector(16 downto 1); - LEMIN : in std_logic_vector(2 downto 1); - LEMOU : out std_logic_vector(2 downto 1); - INPUT_ENABLE : in std_logic_vector(7 downto 1); - DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_1 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_2 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_3 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_4 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_5 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0); - DELAY_REGISTER_TS : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0); - DELAY_REGISTER_VS : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0); - BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); --(4) enables branch, (3 downto 0) is the width value - WIDTH_OUTPUT : in std_logic_vector(3 downto 0); - MUX_SELECTOR_1 : in std_logic_vector(3 downto 0); - MUX_SELECTOR_2 : in std_logic_vector(3 downto 0); - OR_ON_OFF : in std_logic_vector(7 downto 0); - SCALER_PTI1 : out std_logic_vector(31 downto 0); - SCALER_PTI2 : out std_logic_vector(31 downto 0); - SCALER_PTI3 : out std_logic_vector(31 downto 0); - SCALER_PTI4 : out std_logic_vector(31 downto 0); - SCALER_PTI5 : out std_logic_vector(31 downto 0); - SCALER_TS : out std_logic_vector(31 downto 0); - SCALER_VS : out std_logic_vector(31 downto 0); - SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); -- x"yz" y= mdc channel select, z= tof channel select - SCALER_MDC : out std_logic_vector(31 downto 0); - SCALER_TOF : out std_logic_vector(31 downto 0); - SCALER_RESET : in std_logic_vector(7 downto 0); - PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0); - DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0); - WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0); - WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0); - SCALER_DEAD : out std_logic_vector(31 downto 0); - TS_GATING_DISABLE : in std_logic_vector(7 downto 1); - SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_MUX1 : out std_logic_vector(31 downto 0); - SCALER_MUX2 : out std_logic_vector(31 downto 0); - DTU_CODE_SELECT : in std_logic_vector(4 downto 0); - CAL_TRIGGER_DISABLE : in std_logic; - COM_RUN : in std_logic; - DTU_ERROR : inout std_logic; - hpv : inout std_logic_vector(15 downto 0); - hpw : inout std_logic_vector(15 downto 0); - DEBUG_REG_00 : out std_logic_vector(31 downto 0); - TRB_BUSY_ENABLE : in std_logic - ); -end trig_box1; - - -architecture RTL of trig_box1 is - -component ONE_CLOCK_LONG port ( - clk : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); -end component; - -component DELAY port ( - clk : in std_logic; - to_be_delayed : in std_logic; - delay_value : in std_logic_vector(3 downto 0); - delayed_pulse : out std_logic); -end component; - -component DOWNSCALE port ( - clk : in std_logic; - disable : in std_logic; - to_be_downscaled : in std_logic; - downscale_value : in std_logic_vector(3 downto 0); - downscaled : out std_logic); -end component; - -component SET_WIDTH port ( - clk : in std_logic; - to_be_set : in std_logic; - width_value : in std_logic_vector(3 downto 0); - width_adjusted_pulse : out std_logic); -end component; - -component SET_WIDTH_special port ( - clk : in std_logic; - to_be_set : in std_logic; - width_value : in std_logic_vector(3 downto 0); - width_adjusted_pulse : out std_logic); -end component; - -component SCALER port ( - clk : in std_logic; - input_pulse : in std_logic; - scaler_reset : in std_logic; - scaler_value : out std_logic_vector(19 downto 0)); -end component; - -component SCALER_S port ( - clk_300MHz : in std_logic; - clk_100MHz : in std_logic; - input_pulse : in std_logic; - scaler_reset : in std_logic; - scaler_value : out std_logic_vector(31 downto 0)); -end component; - -component ECO_DELAY port ( - clk : in std_logic; - signal_in : in std_logic; - signal_out : out std_logic); -end component; - -COMPONENT new_downscale_ck -PORT( - downscale_value : IN std_logic_vector(3 downto 0); - clk : IN std_logic; - downscaled : OUT std_logic; - output_disable : IN std_logic; - global_inhibit : in std_logic; - scaler_reset : OUT std_logic; - cal_inhibit : OUT std_logic; - cal_trigger : OUT std_logic - ); -END COMPONENT; - -COMPONENT beam_ramp -PORT( - clk_300MHz : IN std_logic; - clk_50MHz : IN std_logic; - input : IN std_logic; - delay_value : IN std_logic_vector(7 downto 0); - width_value_inhibit : IN std_logic_vector(7 downto 0); - width_value_external : IN std_logic_vector(7 downto 0); - output_inhibit : OUT std_logic; - output_external : OUT std_logic - ); -END COMPONENT; - -COMPONENT bus_data_com5 -PORT( - clk_300MHz : IN std_logic; - clk_100MHz : IN std_logic; - gts_pulse : IN std_logic; - cal_trigger : IN std_logic; - bus_busy : IN std_logic; --not used - bus_ack : in std_logic; - bus_retx : in std_logic; - latch : IN std_logic_vector(6 downto 0); - latch_dsc : IN std_logic_vector(6 downto 0); - scaler_pti1 : IN std_logic_vector(31 downto 0); - scaler_pti2 : IN std_logic_vector(31 downto 0); - scaler_pti3 : IN std_logic_vector(31 downto 0); - scaler_pti4 : IN std_logic_vector(31 downto 0); - scaler_pti5 : IN std_logic_vector(31 downto 0); - scaler_ts : IN std_logic_vector(31 downto 0); - scaler_vs : IN std_logic_vector(31 downto 0); - scaler_dead : IN std_logic_vector(31 downto 0); - bus_inhibit : OUT std_logic; - dtu_inhibit : out std_logic; - ecl_bus_data : OUT std_logic_vector(1 downto 0); - ecl_bus_clk : OUT std_logic; - com_run : IN std_logic; - dtu_bus_t : out std_logic; - dtu_bus_ts : out std_logic; - dtu_bus_td : out std_logic_vector (3 downto 0); - DTU_CODE_SELECT : in std_logic_vector(4 downto 0); - DEBUG_REG_01 : out std_logic_vector(15 downto 0); - cal_inhibit : in std_logic; - out_inhibit : in std_logic; - TRB_BUSY_ENABLE : in std_logic - ); -END COMPONENT; - - -signal PTI1_ONE_CLOCK, PTI1_DELAYED, PTI1_READY, PTI1_DOWNSCALED, PTI1_SELF_COIN : std_logic; -signal PTI2_ONE_CLOCK, PTI2_DELAYED, PTI2_READY, PTI2_DOWNSCALED, PTI2_SELF_COIN : std_logic; -signal PTI3_ONE_CLOCK, PTI3_DELAYED, PTI3_READY, PTI3_DOWNSCALED, PTI3_SELF_COIN : std_logic; -signal PTI4_ONE_CLOCK, PTI4_DELAYED, PTI4_READY, PTI4_DOWNSCALED, PTI4_SELF_COIN : std_logic; -signal PTI5_ONE_CLOCK, PTI5_DELAYED, PTI5_READY, PTI5_DOWNSCALED, PTI5_SELF_COIN : std_logic; -signal TS_ONE_CLOCK, TS_DELAYED, TS_READY, dead, TS_SELF_COIN : std_logic; -signal VS_ONE_CLOCKS, VS_DELAYED, VS_READY, VS_WIDTH_SET, VS_SELF_COIN : std_logic; -signal CLOCK_DOWNSCALED, CLOCK_READY : std_logic; -signal cal_inhibit, cal_trigger, out_inhibit, beam_inhibit, bus_inhibit : std_logic; -signal GLOBAL_TIMING_SIGNAL_OUT, OR_out : std_logic; -signal PTI1_and_GTS, PTI2_and_GTS, PTI3_and_GTS, PTI4_and_GTS, PTI5_and_GTS : std_logic; -signal lemin_s, lemin_s1, mux_out : std_logic_vector(1 downto 0); -signal mdc_tof_or, mdc_tof_or_width_set, tof_or, tof_or_delayed, tof_mult_2, tof_mult_2_one, mdc_tof_trigger, mdc_tof_trigger_width_set : std_logic; -signal eco_s, eco_out : std_logic_vector(16 downto 1); -signal tof_one_clock, tof_del, tof_s, tof_s1, mdc_s, mdc_s1 : std_logic_vector(5 downto 0); -signal tof_mux, mdc_mux, pti5_mux, ts_mux, mdc_one_clock : std_logic; -signal scaler_pti1_count, scaler_pti2_count, scaler_pti3_count, scaler_pti4_count, scaler_pti5_count, - scaler_ts_count, scaler_vs_count, scaler_dead_count : std_logic_vector(31 downto 0); -signal self_coin_delay_1, self_coin_delay_2, self_coin_delay_3, self_coin_delay_4, self_coin_delay_5 : std_logic_vector(3 downto 0); -signal scaler_reset_internal : std_logic; -signal dtu_bus_t, dtu_bus_ts, dtu_bus_tb_s, dtu_inhibit : std_logic; -signal dtu_bus_td : std_logic_vector(3 downto 0); -signal GTS_to_databus, CAL_to_databus : std_logic; - -begin - --------------------------------------------------------------ONE CLOCK LONG -one1: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => INPUT_ENABLE(1), - signal_in => IOO(1), - pulse => PTI1_ONE_CLOCK); - -one2: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => INPUT_ENABLE(2), - signal_in => IOO(2), - pulse => PTI2_ONE_CLOCK); - -one3: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => INPUT_ENABLE(3), - signal_in => IOO(3), - pulse => PTI3_ONE_CLOCK); - -one4: ONE_CLOCK_LONG port map ( --Directly connected to the OR of TOF, so ECL input n°4 is unused - clk => clk_300MHz, - en_clk => INPUT_ENABLE(4), - signal_in => tof_or, - pulse => PTI4_ONE_CLOCK); - -one5: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => INPUT_ENABLE(5), - signal_in => IOO(5), - pulse => PTI5_ONE_CLOCK); - -one6: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => INPUT_ENABLE(6), - signal_in => IOO(6), - pulse => TS_ONE_CLOCK); - -one7: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => INPUT_ENABLE(7), - signal_in => IOO(7), - pulse => VS_ONE_CLOCKS); - -one_mdc: ONE_CLOCK_LONG port map ( --used only for scaler - clk => clk_300MHz, - en_clk => '1', - signal_in => mdc_mux, - pulse => mdc_one_clock); - -tof_generate_oneclock : for i in 9 to 14 generate - one_tof: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => '1', --tof always enabled - signal_in => ECL(i), - pulse => tof_one_clock(i-9)); -end generate; ---------------------------------------------- -multiplicity: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => '1', - signal_in => tof_mult_2, - pulse => tof_mult_2_one); ---------------------------------------------- -one_ck: ONE_CLOCK_LONG port map ( - clk => clk_300MHz, - en_clk => '1', - signal_in => CLOCK_DOWNSCALED, - pulse => CLOCK_READY); - --------------------------------------------------------------------------DELAY -del1: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI1_ONE_CLOCK, - delay_value => DELAY_REGISTER_1(3 downto 0), - delayed_pulse => PTI1_DELAYED); - -del2: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI2_ONE_CLOCK, - delay_value => DELAY_REGISTER_2(3 downto 0), - delayed_pulse => PTI2_DELAYED); - -del3: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI3_ONE_CLOCK, - delay_value => DELAY_REGISTER_3(3 downto 0), - delayed_pulse => PTI3_DELAYED); - -del4: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI4_ONE_CLOCK, - delay_value => DELAY_REGISTER_4(3 downto 0), - delayed_pulse => PTI4_DELAYED); - -del5: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => pti5_mux, - delay_value => DELAY_REGISTER_5(3 downto 0), - delayed_pulse => PTI5_DELAYED); - -del6: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => ts_mux, - delay_value => DELAY_REGISTER_TS(3 downto 0), - delayed_pulse => TS_DELAYED); - -del7: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => VS_ONE_CLOCKS, - delay_value => DELAY_REGISTER_VS(3 downto 0), - delayed_pulse => VS_DELAYED); - -self_coin_delay_1 <= '0' & WIDTH_REGISTER_1(3 downto 1); --automatic delay = width / 2 -self_coin_delay_2 <= '0' & WIDTH_REGISTER_2(3 downto 1); -self_coin_delay_3 <= '0' & WIDTH_REGISTER_3(3 downto 1); -self_coin_delay_4 <= '0' & WIDTH_REGISTER_4(3 downto 1); -self_coin_delay_5 <= '0' & WIDTH_REGISTER_5(3 downto 1); - -del1_self: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI1_DOWNSCALED, - delay_value => self_coin_delay_1, - delayed_pulse => PTI1_SELF_COIN); - -del2_self: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI2_DOWNSCALED, - delay_value => self_coin_delay_2, - delayed_pulse => PTI2_SELF_COIN); - -del3_self: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI3_DOWNSCALED, - delay_value => self_coin_delay_3, - delayed_pulse => PTI3_SELF_COIN); - -del4_self: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI4_DOWNSCALED, - delay_value => self_coin_delay_4, - delayed_pulse => PTI4_SELF_COIN); - -del5_self: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => PTI5_DOWNSCALED, - delay_value => self_coin_delay_5, - delayed_pulse => PTI5_SELF_COIN); - -tof_generate_delay : for t in 0 to 5 generate - del_tof: DELAY port map ( - clk => clk_300MHz, - to_be_delayed => tof_one_clock(t), - delay_value => DELAY_REGISTER_4(3 downto 0), - delayed_pulse => tof_del(t)); -end generate; - --------------------------------------------------------------------------SCALER -scal1: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, --PTI1÷5 before inhibit - input_pulse => PTI1_DELAYED, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI1_count); - -scal2: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => PTI2_DELAYED, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI2_count); - -scal3: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => PTI3_DELAYED, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI3_count); - -scal4: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => PTI4_DELAYED, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI4_count); - -scal5: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => PTI5_DELAYED, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI5_count); - -scal1a: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, --PTI1÷5 after inhibit - input_pulse => eco_s(9), - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI1_ACCEPTED); - -scal2a: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => eco_s(10), - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI2_ACCEPTED); - -scal3a: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => eco_s(11), - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI3_ACCEPTED); - -scal4a: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => eco_s(12), - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI4_ACCEPTED); - -scal5a: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => eco_s(13), - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_PTI5_ACCEPTED); - -scalts: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, --TS, VS and dead - input_pulse => TS_DELAYED, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_TS_count); - -scalvs: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => VS_DELAYED, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_VS_count); - -scaldead: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => dead, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_DEAD_count); - -scalmdc: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, --MDC and TOF - input_pulse => mdc_one_clock, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_MDC); - -scaltof: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => tof_mux, - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_TOF); - -scalmux1: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => mux_out(0), - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_MUX1); - -scalmux2: SCALER_S port map ( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - input_pulse => mux_out(1), - scaler_reset => scaler_reset_internal, - scaler_value => SCALER_MUX2); - ----------------------------------------------------------------------------DOWNSCALE -dwsc1: DOWNSCALE port map ( - clk => clk_300MHz, - disable => out_inhibit, - to_be_downscaled => PTI1_DELAYED, - downscale_value => DOWNSCALE_REGISTER_1(3 downto 0), - downscaled => PTI1_DOWNSCALED); - -dwsc2: DOWNSCALE port map ( - clk => clk_300MHz, - disable => out_inhibit, - to_be_downscaled => PTI2_DELAYED, - downscale_value => DOWNSCALE_REGISTER_2(3 downto 0), - downscaled => PTI2_DOWNSCALED); - -dwsc3: DOWNSCALE port map ( - clk => clk_300MHz, - disable => out_inhibit, - to_be_downscaled => PTI3_DELAYED, - downscale_value => DOWNSCALE_REGISTER_3(3 downto 0), - downscaled => PTI3_DOWNSCALED); - -dwsc4: DOWNSCALE port map ( - clk => clk_300MHz, - disable => out_inhibit, - to_be_downscaled => PTI4_DELAYED, - downscale_value => DOWNSCALE_REGISTER_4(3 downto 0), - downscaled => PTI4_DOWNSCALED); - -dwsc5: DOWNSCALE port map ( - clk => clk_300MHz, - disable => out_inhibit, - to_be_downscaled => PTI5_DELAYED, - downscale_value => DOWNSCALE_REGISTER_5(3 downto 0), - downscaled => PTI5_DOWNSCALED); - -dwscts: DOWNSCALE port map ( - clk => clk_300MHz, - disable => out_inhibit, - to_be_downscaled => TS_DELAYED, - downscale_value => DOWNSCALE_REGISTER_TS(3 downto 0), - downscaled => TS_READY); - -dwscvs: DOWNSCALE port map ( - clk => clk_300MHz, - disable => out_inhibit, - to_be_downscaled => VS_DELAYED, - downscale_value => DOWNSCALE_REGISTER_VS(3 downto 0), - downscaled => VS_READY); - --------------------------------------------------------------------------------WIDTH -setw1: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => PTI1_DOWNSCALED, - width_value => WIDTH_REGISTER_1(3 downto 0), - width_adjusted_pulse => PTI1_READY); - -setw2: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => PTI2_DOWNSCALED, - width_value => WIDTH_REGISTER_2(3 downto 0), - width_adjusted_pulse => PTI2_READY); - -setw3: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => PTI3_DOWNSCALED, - width_value => WIDTH_REGISTER_3(3 downto 0), - width_adjusted_pulse => PTI3_READY); - -setw4: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => PTI4_DOWNSCALED, - width_value => WIDTH_REGISTER_4(3 downto 0), - width_adjusted_pulse => PTI4_READY); - -setw5: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => PTI5_DOWNSCALED, - width_value => WIDTH_REGISTER_5(3 downto 0), - width_adjusted_pulse => PTI5_READY); - -setw7: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => VS_DELAYED, - width_value => WIDTH_REGISTER_VS(3 downto 0), - width_adjusted_pulse => VS_WIDTH_SET); - ---*/*/*///*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ --READ NOTE 1) -mdc_tof_trigger_width_set <= '1'; --(a) ---*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/* - -setw_mdc_tof_trigger: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => mdc_tof_or, - width_value => BRANCH_EN_with_MDC_TOF_WIDTH(3 downto 0), --- width_adjusted_pulse => mdc_tof_trigger_width_set); --(c) - width_adjusted_pulse => open); --(b) - -setwout: SET_WIDTH_special port map ( - clk => clk_300MHz, - to_be_set => GLOBAL_TIMING_SIGNAL_OUT, - width_value => x"6", -- fixed to 20 ns - width_adjusted_pulse => LEMOU(1)); - -------------------------------------------------------------------------------------------OUTPUT -delaygen1 : for i in 1 to 7 generate - delay_out : ECO_DELAY port map ( - clk => clk_300MHz, - signal_in => eco_s(i), - signal_out => eco_out(i)); -end generate; - -ECO(7 downto 1) <= eco_out(7 downto 1); - -setmux1: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => mux_out(0), - width_value => "0010", - width_adjusted_pulse => ECO(8)); - -delaygen2 : for i in 9 to 15 generate - delay_out : ECO_DELAY port map ( - clk => clk_300MHz, - signal_in => eco_s(i), - signal_out => eco_out(i)); -end generate; - -ECO(15 downto 9) <= eco_out(15 downto 9); - -setmux2: SET_WIDTH port map ( - clk => clk_300MHz, - to_be_set => mux_out(1), - width_value => "0010", - width_adjusted_pulse => ECO(16)); - -Inst_new_downscale_ck: new_downscale_ck PORT MAP( - downscale_value => DOWNSCALE_REGISTER_CLOCK(3 downto 0), - clk => clk_300MHz, - output_disable => CAL_TRIGGER_DISABLE, - scaler_reset => scaler_reset_internal, - downscaled => CLOCK_DOWNSCALED, - global_inhibit => out_inhibit, - cal_inhibit => cal_inhibit, - cal_trigger => cal_trigger); - - -LEMOU(2) <= out_inhibit;--OR_out;-- GLOBAL_TIMING_SIGNAL_OUT; --Now calib pulse is coming out from lemo n°1, this output is unused - -Inst_beam_ramp: beam_ramp PORT MAP( - clk_300MHz => clk_300MHz, - clk_50MHz => clk_50MHz, - input => lemin_s(1), - output_inhibit => beam_inhibit, - output_external => TIN(12), - delay_value => DELAY_REGISTER_BEAM, - width_value_inhibit => WIDTH_INHIBIT_REGISTER_BEAM, - width_value_external => WIDTH_EXTERNAL_REGISTER_BEAM); - ---------------BUS COMMUNICATION - -Inst_bus_data_com5: bus_data_com5 PORT MAP( - clk_300MHz => clk_300MHz, - clk_100MHz => clk_100MHz, - gts_pulse => GTS_to_databus, - cal_trigger => cal_trigger, - bus_busy => IOO(16), --not used - bus_ack => IOO(15), - bus_retx => IOO(14), - latch => eco_out(7 downto 1), - latch_dsc => eco_out(15 downto 9), - scaler_pti1 => scaler_pti1_count, - scaler_pti2 => scaler_pti2_count, - scaler_pti3 => scaler_pti3_count, - scaler_pti4 => scaler_pti4_count, - scaler_pti5 => scaler_pti5_count, - scaler_ts => scaler_ts_count, - scaler_vs => scaler_vs_count, - scaler_dead => scaler_dead_count, - bus_inhibit => bus_inhibit, - dtu_inhibit => dtu_inhibit, - ecl_bus_data => TIN(11 downto 10), - ecl_bus_clk => open,--TIN(9), - com_run => com_run, - dtu_bus_t => dtu_bus_t, - dtu_bus_ts => dtu_bus_ts, - dtu_bus_td => dtu_bus_td, - DTU_CODE_SELECT => DTU_CODE_SELECT, - DEBUG_REG_01 => DEBUG_REG_00(15 downto 0), - cal_inhibit => cal_inhibit, - out_inhibit => out_inhibit, - TRB_BUSY_ENABLE => TRB_BUSY_ENABLE - ); - - --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ - hpv(14) <= not dtu_bus_t; --This is a "firmware patch": the VME connector - hpw(14) <= not dtu_bus_ts; --for DTU is reversed (mistake in pcb layout) so - hpw(10) <= not dtu_bus_td(3); --all the I/Os must be inverted - hpv(10) <= not dtu_bus_td(2); - hpw(12) <= not dtu_bus_td(1); - hpv(12) <= not dtu_bus_td(0); - hpw(8) <= 'Z'; - ---------------------- - hpv(15) <= dtu_bus_ts; --With this connections all the DTU signals are - hpv(11) <= dtu_bus_td(3); --on one debug socket (hplv or hplw) that can conveniently - hpv(13) <= dtu_bus_td(1); --plugged to a logic analyzer. Be aware though, some signals - hpv(9) <= '0'; --are inverted - hpv(7 downto 0) <= x"00"; --unused - - hpw(15) <= dtu_bus_t; - hpw(11) <= dtu_bus_td(2); - hpw(13) <= dtu_bus_td(0); - hpw(9) <= '0'; - hpw(7 downto 0) <= x"00"; --unused - --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ - - SCALER_PTI1 <= SCALER_PTI1_count; - SCALER_PTI2 <= SCALER_PTI2_count; - SCALER_PTI3 <= SCALER_PTI3_count; - SCALER_PTI4 <= SCALER_PTI4_count; - SCALER_PTI5 <= SCALER_PTI5_count; - SCALER_TS <= SCALER_TS_count; - SCALER_VS <= SCALER_VS_count; - SCALER_dead <= SCALER_dead_count; - -TIN(16 downto 13) <= "0000"; - ---------------PTI5 & TS mux - -mdc_tof_mux: process(clk_300MHz) -begin - if rising_edge(clk_300MHz) then - --- case tof_one_clock is --multiplicity 2 detector - case ecl(14 downto 9) is --multiplicity 2 detector - when "000011" => tof_mult_2 <= '1'; - when "000101" => tof_mult_2 <= '1'; - when "001001" => tof_mult_2 <= '1'; - when "010001" => tof_mult_2 <= '1'; - when "100001" => tof_mult_2 <= '1'; - when "000110" => tof_mult_2 <= '1'; - when "001010" => tof_mult_2 <= '1'; - when "010010" => tof_mult_2 <= '1'; - when "100010" => tof_mult_2 <= '1'; - when "001100" => tof_mult_2 <= '1'; - when "010100" => tof_mult_2 <= '1'; - when "100100" => tof_mult_2 <= '1'; - when "011000" => tof_mult_2 <= '1'; - when "101000" => tof_mult_2 <= '1'; - when "110000" => tof_mult_2 <= '1'; - when others => tof_mult_2 <= '0'; - end case; - - case PTI5_TS_ALTERNATIVE(4) is - when '0' => pti5_mux <= PTI5_ONE_CLOCK; - when '1' => pti5_mux <= tof_mult_2_one; - when others => pti5_mux <= 'X'; - end case; - - case PTI5_TS_ALTERNATIVE(0) is - when '0' => ts_mux <= TS_ONE_CLOCK; - when '1' => ts_mux <= tof_or; - when others => ts_mux <= 'X'; - end case; - end if; -end process mdc_tof_mux; - ---------------MDC & TOF scaler mux - -pti5_ts_mux: process(clk_300MHz) -begin - if rising_edge(clk_300MHz) then - case SCALER_MDC_TOF_SELECT(7 downto 4) is - when x"0" => mdc_mux <= mdc_s1(0); - when x"1" => mdc_mux <= mdc_s1(1); - when x"2" => mdc_mux <= mdc_s1(2); - when x"3" => mdc_mux <= mdc_s1(3); - when x"4" => mdc_mux <= mdc_s1(4); - when x"5" => mdc_mux <= mdc_s1(5); - when others => mdc_mux <= '0'; - end case; - - case SCALER_MDC_TOF_SELECT(3 downto 0) is - when x"0" => tof_mux <= tof_one_clock(0); - when x"1" => tof_mux <= tof_one_clock(1); - when x"2" => tof_mux <= tof_one_clock(2); - when x"3" => tof_mux <= tof_one_clock(3); - when x"4" => tof_mux <= tof_one_clock(4); - when x"5" => tof_mux <= tof_one_clock(5); - when others => tof_mux <= '0'; - end case; - end if; -end process pti5_ts_mux; - --------------- TOF & MDC logic - -tof_mdc_logic: process(clk_300Mhz) -begin - if rising_edge(clk_300MHz) then - - mdc_s <= ECL(6 downto 1); - tof_s <= ECL(14 downto 9); - mdc_s1 <= mdc_s; - tof_s1 <= tof_s; - - mdc_tof_or <= (((tof_del(0) and not mdc_s1(0)) or (tof_del(1) and not mdc_s1(1)) or - (tof_del(2) and not mdc_s1(2)) or (tof_del(3) and not mdc_s1(3)) or - (tof_del(4) and not mdc_s1(4)) or (tof_del(5) and not mdc_s1(5))) - and BRANCH_EN_with_MDC_TOF_WIDTH(4)); - - tof_or <= (ecl(9) or ecl(10) or ecl(11) or ecl(12) or ecl(13) or ecl(14)); - - end if; -end process tof_mdc_logic; - --------------- Final AND-OR logic function - -logic: process(clk_300MHz) -begin - if rising_edge(clk_300MHz) then - - -------------------------------------- GATE SELECT SINGLE - - PTI1_and_GTS <= ((PTI1_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(1)) - or (PTI1_SELF_COIN and TS_GATING_DISABLE(1))); - PTI2_and_GTS <= ((PTI2_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(2)) - or (PTI2_SELF_COIN and TS_GATING_DISABLE(2))); - PTI3_and_GTS <= ((PTI3_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(3)) - or (PTI3_SELF_COIN and TS_GATING_DISABLE(3))); - PTI4_and_GTS <= ((PTI4_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(4)) - or (PTI4_SELF_COIN and TS_GATING_DISABLE(4))); - PTI5_and_GTS <= ((PTI5_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(5)) - or (PTI5_SELF_COIN and TS_GATING_DISABLE(5))); - - OR_out <= (PTI1_and_GTS and OR_ON_OFF(0)) or - (PTI2_and_GTS and OR_ON_OFF(1)) or - (PTI3_and_GTS and OR_ON_OFF(2)) or - (PTI4_and_GTS and OR_ON_OFF(3)) or - (PTI5_and_GTS and OR_ON_OFF(4)) or - (TS_READY and OR_ON_OFF(5)) or - (VS_READY and OR_ON_OFF(6)) or - (CLOCK_READY and OR_ON_OFF(7)); - - lemin_s <= LEMIN; - lemin_s1 <= lemin_s; - dtu_bus_tb_s <= not hpv(8); --dtu trigger busy - - dead <= TS_DELAYED and (not out_inhibit); - - out_inhibit <= lemin_s1(0) or beam_inhibit or bus_inhibit or dtu_inhibit;-- - --or dtu_bus_tb_s;-- - --or (not com_run); - TIN(9) <= cal_trigger; - GLOBAL_TIMING_SIGNAL_OUT <= (OR_out and (not out_inhibit) and (not cal_inhibit)); --- and not out_inhibit) or (OR_out and (not out_inhibit) and (not cal_inhibit)); - GTS_to_databus <= OR_out and not out_inhibit and not cal_inhibit; - - - end if; -end process logic; -DEBUG_REG_00(31 downto 29) <= OR_out & out_inhibit & cal_inhibit; -DEBUG_REG_00(28 downto 24) <= lemin_s1(0) & beam_inhibit & bus_inhibit & dtu_inhibit & dtu_bus_tb_s; ----------------- Outputs - -assign: process(clk_300MHz) -begin - if rising_edge(clk_300MHz) then - - eco_s(1) <= PTI1_DELAYED; -- Latches before downscale - eco_s(2) <= PTI2_DELAYED; - eco_s(3) <= PTI3_DELAYED; - eco_s(4) <= PTI4_DELAYED; - eco_s(5) <= PTI5_DELAYED; - eco_s(6) <= TS_DELAYED; - eco_s(7) <= VS_DELAYED; --- ECO(8) is mux 0 - eco_s(9) <= (OR_ON_OFF(0) and ((PTI1_DOWNSCALED and TS_GATING_DISABLE(1)) - or (PTI1_and_GTS and not TS_GATING_DISABLE(1)))); - eco_s(10) <= (OR_ON_OFF(1) and ((PTI2_DOWNSCALED and TS_GATING_DISABLE(2)) - or (PTI2_and_GTS and not TS_GATING_DISABLE(2)))); - eco_s(11) <= (OR_ON_OFF(2) and ((PTI3_DOWNSCALED and TS_GATING_DISABLE(3)) - or (PTI3_and_GTS and not TS_GATING_DISABLE(3)))); - eco_s(12) <= (OR_ON_OFF(3) and ((PTI4_DOWNSCALED and TS_GATING_DISABLE(4)) - or (PTI4_and_GTS and not TS_GATING_DISABLE(4)))); - eco_s(13) <= (OR_ON_OFF(4) and ((PTI5_DOWNSCALED and TS_GATING_DISABLE(5)) - or (PTI5_and_GTS and not TS_GATING_DISABLE(5)))); - - eco_s(14) <= TS_READY and OR_ON_OFF(5); - eco_s(15) <= VS_READY and OR_ON_OFF(6); --- ECO(16) is mux 1 - ------------------ Multiplexers - - case MUX_SELECTOR_1 is --0x5c - - when "0000" => mux_out(0) <= PTI1_DELAYED; --0 - when "0001" => mux_out(0) <= PTI2_DELAYED; - when "0010" => mux_out(0) <= PTI3_DELAYED; --2 - when "0011" => mux_out(0) <= PTI4_DELAYED; - when "0100" => mux_out(0) <= PTI5_DELAYED; --4 - when "0101" => mux_out(0) <= TS_DELAYED; - when "0110" => mux_out(0) <= VS_DELAYED; --6 - when "0111" => mux_out(0) <= PTI1_and_GTS; - when "1000" => mux_out(0) <= PTI2_and_GTS; --8 - when "1001" => mux_out(0) <= PTI3_and_GTS; - when "1010" => mux_out(0) <= PTI4_and_GTS; --a - when "1011" => mux_out(0) <= PTI5_and_GTS; - when "1100" => mux_out(0) <= TS_READY; --c - when "1101" => mux_out(0) <= VS_READY; - when "1110" => mux_out(0) <= OR_out; --e - when "1111" => mux_out(0) <= GLOBAL_TIMING_SIGNAL_OUT; - when others => mux_out(0) <= 'X'; - - end case; - - - case MUX_SELECTOR_2 is --0x60 - - when "0000" => mux_out(1) <= PTI1_DELAYED; --0 - when "0001" => mux_out(1) <= PTI2_DELAYED; - when "0010" => mux_out(1) <= PTI3_DELAYED; --2 - when "0011" => mux_out(1) <= PTI4_DELAYED; - when "0100" => mux_out(1) <= PTI5_DELAYED; --4 - when "0101" => mux_out(1) <= TS_DELAYED; - when "0110" => mux_out(1) <= VS_DELAYED; --6 - when "0111" => mux_out(1) <=tof_mux; --PTI1_READY; - when "1000" => mux_out(1) <='0'; --PTI2_READY; --8 - when "1001" => mux_out(1) <='0'; --PTI3_READY; - when "1010" => mux_out(1) <='0'; --PTI4_READY; --a - when "1011" => mux_out(1) <=mdc_tof_trigger_width_set;--PTI5_READY; - when "1100" => mux_out(1) <= TS_READY; --c - when "1101" => mux_out(1) <= VS_READY; - when "1110" => mux_out(1) <= CLOCK_READY; --e - when "1111" => mux_out(1) <=mdc_mux; --VS_WIDTH_SET; - when others => mux_out(1) <= 'X'; - - end case; - - end if; -end process assign; - -end RTL; diff --git a/oldfiles/vulom3/trigger_box1.stapl b/oldfiles/vulom3/trigger_box1.stapl deleted file mode 100644 index 0bf6624..0000000 --- a/oldfiles/vulom3/trigger_box1.stapl +++ /dev/null @@ -1,3106 +0,0 @@ -NOTE "CREATOR" "Xilinx iMPACT Software"; -NOTE "DATE" "2008/04/28"; -NOTE "STAPL_VERSION" "JESD71"; -NOTE "ALG_VERSION" "1"; -NOTE "DEVICE" "UNSPECIFIED"; -NOTE "CHECKSUM" "UNSPECIFIED"; -NOTE "IDCODE" "UNSPECIFIED"; -NOTE "USERCODE" "UNSPECIFIED"; -NOTE "TARGET" "UNSPECIFIED"; -NOTE "STACK_DEPTH" "4"; -NOTE "MAX_FREQ" "1000000"; -ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC; -DATA MAINDATA; -INTEGER I = 0; -INTEGER D = 0; -ENDDATA; -PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA; -BOOLEAN X = 0; -IRSTOP IDLE; -DRSTOP IDLE; -STATE RESET IDLE; -POSTIR 0 ; -PREIR 0 ; -POSTDR 0 ; -PREDR 0 ; -POSTIR 0 ; -PREIR 0 ; -PREDR 0 ; -POSTDR 0 ; -' //Loading device with 'idcode' instruction. -IRSCAN 10, $03c9 - ; -DRSCAN 32, $00000000 -, COMPARE $f167c093 -, $0fffffff -, X; -IF (!X) THEN GOTO F; -POSTIR 0 ; -PREIR 0 ; -POSTDR 0 ; -PREDR 0 ; -POSTIR 0 ; -PREIR 0 ; -POSTDR 0 ; -PREDR 0 ; -POSTIR 0 ; -PREIR 0 ; -PREDR 0 ; -POSTDR 0 ; -' //Loading device with 'idcode' instruction. -IRSCAN 10, $03c9 - ; -DRSCAN 32, $00000000 -, COMPARE $f167c093 -, $0fffffff -, X; -IF (!X) THEN GOTO F; -' //Loading device with 'bypass' instruction. -IRSCAN 10, $03ff - ; -' // Loading device with a `jprogram` instruction. -IRSCAN 10, $03cb - ; -D = 1; -WAIT D CYCLES; -' // Loading device with a `bypass` instruction. -IRSCAN 10, $03ff - ; -D = 21000; -WAIT D CYCLES; -' // Loading device with a `cfg_in` instruction. -IRSCAN 10, $03c5 - ; -D = 100000; -WAIT D CYCLES; -' // Check init_complete in ircapture. -' //Loading device with 'Bypass' instruction. -IRSCAN 10, $03ff -, COMPARE $0010 -, $0010 -, X; -IF (!X) THEN GOTO F; -' STATE RESET; -' // Loading device with a `cfg_in` instruction. -IRSCAN 10, $03c5 -, COMPARE $0000 -, $0000 -, X; -IF (!X) THEN GOTO F; -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes a data shift of more than 16K bits -' which might exceed the capacity of your run-time environment. -' WARNING: This STAPL file describes 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-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ -@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@l4600 -00wojIsF60G0020000K40000WXC0C0m40000WW4088204210YW009G0W280m04QCcX4IQWXO -0C0040800O22m0020G0000WcuW160G00000W10A82030000QqtloCC0W0040000ivEy30_@V - ; -' // Loading device with a `jstart` instruction. -IRSCAN 10, $03cc - ; -D = 12; -WAIT D CYCLES; -' //Loading device with 'bypass' instruction. -IRSCAN 10, $03ff - ; -' //Loading device with 'bypass' instruction. -IRSCAN 10, $03ff - ; -POSTIR 0 ; -PREIR 0 ; -PREDR 0 ; -POSTDR 0 ; -POSTIR 0 ; -PREIR 0 ; -PREDR 0 ; -POSTDR 0 ; -' // Loading device with a `jstart` instruction. -IRSCAN 10, $03cc - ; -D = 12; -WAIT D CYCLES; -' // Loading device with a `cfg_in` instruction. -IRSCAN 10, $03c5 - ; -DRSCAN 224, $0000000000000000200000008001000c0000000466aa9955ffffffff - ; -' //Checking done pin status. -' //Loading device with 'Bypass' instruction. -IRSCAN 10, $03ff -, COMPARE $0021 -, $0020 -, X; -IF (!X) THEN GOTO F; -POSTIR 0 ; -PREIR 0 ; -POSTDR 0 ; -PREDR 0 ; -IRSCAN 10, $03ff - ; -DRSCAN 1, $00 - ; - -SUCCESS: -PRINT "Successful File Execution."; -EXIT 0; - -F: -PRINT "File Execution Failure."; -EXIT 16; - -ENDPROC; - -DATA TMPDATA; -INTEGER TMP_DELAY; -ENDDATA; - -PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA; -TMP_DELAY = D / 100; -TMP_DELAY = TMP_DELAY * 25; -D = D + TMP_DELAY; -ENDPROC; - -PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA; -TMP_DELAY = D * 25; -TMP_DELAY = TMP_DELAY / 100; -D = D + TMP_DELAY; -ENDPROC; - -PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY; -IF D > 2500 THEN CALL ADJUST_BIG_DELAY; -IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY; -ENDPROC; - -CRC 324E; diff --git a/oldfiles/vulom3/ulogic.vhd b/oldfiles/vulom3/ulogic.vhd deleted file mode 100644 index cfb8306..0000000 --- a/oldfiles/vulom3/ulogic.vhd +++ /dev/null @@ -1,333 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Davide Leoni --- --- Create Date: 5/4/07 --- Design Name: vulom3 --- Module Name: ulogic - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: VME address encoder and decoder, I/O ECL configuration --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -entity ulogic is port ( - RESET : in std_logic; - CK50 : in std_logic; - CK300 : in std_logic; - CK100 : in std_logic; - LEMOU : out std_logic_vector(2 downto 1); -- - LEMIN : in std_logic_vector(2 downto 1); -- - TIN : out std_logic_vector(16 downto 1); - EN : out std_logic_vector(4 downto 1); - ECO : out std_logic_vector(16 downto 1); - ECL : in std_logic_vector(16 downto 1); - IOO : in std_logic_vector(16 downto 1); - FLED_T : out std_logic_vector(6 downto 1); ------------------------------- VME interface ------------------------------------- - U_AD_REG : in std_logic_vector(21 downto 2); - U_DAT_IN : in std_logic_vector(31 downto 0); - U_DATA_O : out std_logic_vector(31 downto 0); - OECSR : in std_logic; - CKCSR : in std_logic; - HPV : inout std_logic_vector(15 downto 0); - HPW : inout std_logic_vector(15 downto 0) - ); -end ulogic; -architecture RTL of ulogic is -signal ckcsro : std_logic_vector (35 downto 0); -- write clock for registers -signal oecsro : std_logic_vector (35 downto 0); -- read enable for registers -signal hplx : std_logic_vector (7 downto 0); -- data register for logic analyzer -signal INPUT_ENABLE : std_logic_vector(7 downto 1); -signal downscale_register_1, downscale_register_2, downscale_register_3,downscale_register_4, downscale_register_5, downscale_register_ts, downscale_register_vs, downscale_register_clock : std_logic_vector(3 downto 0); --15 -signal delay_register_1, delay_register_2, delay_register_3, delay_register_4, delay_register_5, delay_register_ts, delay_register_vs : std_logic_vector(3 downto 0); -signal width_register_1, width_register_2, width_register_3, width_register_4, width_register_5, width_register_ts, width_register_vs, width_output : std_logic_vector(3 downto 0); -signal scaler_pti1, scaler_pti2, scaler_pti3, scaler_pti4, scaler_pti5, scaler_ts, scaler_vs, scaler_mdc, scaler_tof, scaler_dead, scaler_pti1_accepted, scaler_pti2_accepted, scaler_pti3_accepted, scaler_pti4_accepted, scaler_pti5_accepted, scaler_ts_accepted, scaler_vs_accepted, scaler_mux1, scaler_mux2 : std_logic_vector(31 downto 0); -signal scaler_reset, scaler_mdc_tof_select : std_logic_vector(7 downto 0); -signal or_on_off : std_logic_vector(7 downto 0); -signal ts_gating_disable : std_logic_vector(7 downto 1); -signal pti5_ts_alternative, delay_register_beam, width_inhibit_register_beam, width_external_register_beam : std_logic_vector(7 downto 0); -signal mux_selector_1, mux_selector_2 : std_logic_vector(3 downto 0); -signal branch_en_with_mdc_tof_width, dtu_code_select_i: std_logic_vector(4 downto 0); ---signal u_data_o_s : std_logic_vector(31 downto 0); -signal cal_trigger_disable, com_run, dtu_error : std_logic; -signal debug_1 : std_logic_vector(31 downto 0); -signal trb_busy_enable : std_logic; -component trig_box1 - port (CLK_50MHZ : in std_logic; - CLK_300MHz : in std_logic; - CLK_100MHz : in std_logic; - ECL : in std_logic_vector(16 downto 1); - ECO : out std_logic_vector(16 downto 1); - IOO : in std_logic_vector(16 downto 1); - TIN : out std_logic_vector(16 downto 1); - LEMIN : in std_logic_vector(2 downto 1); - LEMOU : out std_logic_vector(2 downto 1); - INPUT_ENABLE : in std_logic_vector(7 downto 1); - DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0); --15 - DELAY_REGISTER_1 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0); --4 - DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_2 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_3 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_4 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_5 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0); - DELAY_REGISTER_TS : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0); - DELAY_REGISTER_VS : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0); - BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); - WIDTH_OUTPUT : in std_logic_vector(3 downto 0); - MUX_SELECTOR_1 : in std_logic_vector(3 downto 0); - MUX_SELECTOR_2 : in std_logic_vector(3 downto 0); - OR_ON_OFF : in std_logic_vector(7 downto 0); - SCALER_PTI1 : out std_logic_vector(31 downto 0); - SCALER_PTI2 : out std_logic_vector(31 downto 0); - SCALER_PTI3 : out std_logic_vector(31 downto 0); - SCALER_PTI4 : out std_logic_vector(31 downto 0); - SCALER_PTI5 : out std_logic_vector(31 downto 0); - SCALER_TS : out std_logic_vector(31 downto 0); - SCALER_VS : out std_logic_vector(31 downto 0); - SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); - SCALER_MDC : out std_logic_vector(31 downto 0); - SCALER_TOF : out std_logic_vector(31 downto 0); - SCALER_RESET : in std_logic_vector(7 downto 0); - PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0); - DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0); - WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0); - WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0); - SCALER_DEAD : out std_logic_vector(31 downto 0); - TS_GATING_DISABLE : in std_logic_vector(7 downto 1); - SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_MUX1 : out std_logic_vector(31 downto 0); - SCALER_MUX2 : out std_logic_vector(31 downto 0); - DTU_CODE_SELECT : in std_logic_vector(4 downto 0); - CAL_TRIGGER_DISABLE : in std_logic; - COM_RUN : in std_logic; - DTU_ERROR : out std_logic; - HPV : inout std_logic_vector(15 downto 0); - HPW : inout std_logic_vector(15 downto 0); - DEBUG_REG_00 : out std_logic_vector(31 downto 0); - TRB_BUSY_ENABLE : in std_logic - ); -end component; -begin - trgb_1 : trig_box1 port map ( - CLK_50MHz => CK50, - CLK_300MHz => CK300, - CLK_100MHz => CK100, - ECL => ECL, - ECO => ECO, - IOO => IOO, - TIN => TIN, - LEMIN => LEMIN, - LEMOU => LEMOU, - INPUT_ENABLE => INPUT_ENABLE, - DOWNSCALE_REGISTER_1 => downscale_register_1, - DELAY_REGISTER_1 => delay_register_1, - WIDTH_REGISTER_1 => width_register_1, - DOWNSCALE_REGISTER_2 => downscale_register_2, - DELAY_REGISTER_2 => delay_register_2, - WIDTH_REGISTER_2 => width_register_2, - DOWNSCALE_REGISTER_3 => downscale_register_3, - DELAY_REGISTER_3 => delay_register_3, - WIDTH_REGISTER_3 => width_register_3, - DOWNSCALE_REGISTER_4 => downscale_register_4, - DELAY_REGISTER_4 => delay_register_4, - WIDTH_REGISTER_4 => width_register_4, - DOWNSCALE_REGISTER_5 => downscale_register_5, - DELAY_REGISTER_5 => delay_register_5, - WIDTH_REGISTER_5 => width_register_5, - DOWNSCALE_REGISTER_TS => downscale_register_ts, - DELAY_REGISTER_TS => delay_register_ts, - WIDTH_REGISTER_TS => width_register_ts, - DOWNSCALE_REGISTER_VS => downscale_register_vs, - DELAY_REGISTER_VS => delay_register_vs, - WIDTH_REGISTER_VS => width_register_vs, - DOWNSCALE_REGISTER_CLOCK => downscale_register_clock, - BRANCH_EN_with_MDC_TOF_WIDTH => branch_en_with_mdc_tof_width, - WIDTH_OUTPUT => width_output, - MUX_SELECTOR_1 => mux_selector_1, - MUX_SELECTOR_2 => mux_selector_2, - OR_ON_OFF => or_on_off, - SCALER_PTI1 => scaler_pti1, - SCALER_PTI2 => scaler_pti2, - SCALER_PTI3 => scaler_pti3, - SCALER_PTI4 => scaler_pti4, - SCALER_PTI5 => scaler_pti5, - SCALER_TS => scaler_ts, - SCALER_VS => scaler_vs, - SCALER_MDC_TOF_SELECT => scaler_mdc_tof_select, - SCALER_MDC => scaler_mdc, - SCALER_TOF => scaler_tof, - SCALER_RESET => scaler_reset, - PTI5_TS_ALTERNATIVE => pti5_ts_alternative, - DELAY_REGISTER_BEAM => delay_register_beam, - WIDTH_INHIBIT_REGISTER_BEAM => width_inhibit_register_beam, - WIDTH_EXTERNAL_REGISTER_BEAM => width_external_register_beam, - SCALER_DEAD => scaler_dead, - TS_GATING_DISABLE => ts_gating_disable, - SCALER_PTI1_ACCEPTED => scaler_pti1_accepted, - SCALER_PTI2_ACCEPTED => scaler_pti2_accepted, - SCALER_PTI3_ACCEPTED => scaler_pti3_accepted, - SCALER_PTI4_ACCEPTED => scaler_pti4_accepted, - SCALER_PTI5_ACCEPTED => scaler_pti5_accepted, - SCALER_TS_ACCEPTED => scaler_ts_accepted, - SCALER_VS_ACCEPTED => scaler_vs_accepted, - SCALER_MUX1 => scaler_mux1, - SCALER_MUX2 => scaler_mux2, - DTU_CODE_SELECT => dtu_code_select_i, - CAL_TRIGGER_DISABLE => cal_trigger_disable, - COM_RUN => com_run, - DTU_ERROR => dtu_error, - HPV => HPV, - HPW => HPW, - DEBUG_REG_00 => debug_1, - TRB_BUSY_ENABLE => trb_busy_enable - ); ----------------------I/O ecl port settings and led configuration --------------------------------- --- tin(16 downto 9) <= (others => '0'); - EN(4 downto 1) <= "1011"; --- en(2) <= '1'; -- I/O channel 9 to 16 is an output if 0 --- tin(8 downto 1) <= (others => '0'); --- en(1) <= '1'; -- I/O channel 1 to 8 is an output if 0 - FLED_T(5 downto 1) <= not INPUT_ENABLE(5 downto 1); -- input LEDs -------------------------------decoder for data registers ----------------------------------------- - process(CK50) - begin - if rising_edge(CK50) then - if CKCSR = '1' then --read from VME bus - case (U_AD_REG(17 downto 2)) is - when x"0000" => delay_register_1 <= U_DAT_IN(3 downto 0); - when x"0001" => delay_register_2 <= U_DAT_IN(3 downto 0); - when x"0002" => delay_register_3 <= U_DAT_IN(3 downto 0); - when x"0003" => delay_register_4 <= U_DAT_IN(3 downto 0); - when x"0004" => delay_register_5 <= U_DAT_IN(3 downto 0); - when x"0005" => delay_register_ts <= U_DAT_IN(3 downto 0); - when x"0006" => delay_register_vs <= U_DAT_IN(3 downto 0); - when x"0007" => downscale_register_1 <= U_DAT_IN(3 downto 0); - when x"0008" => downscale_register_2 <= U_DAT_IN(3 downto 0); - when x"0009" => downscale_register_3 <= U_DAT_IN(3 downto 0); - when x"000a" => downscale_register_4 <= U_DAT_IN(3 downto 0); - when x"000b" => downscale_register_5 <= U_DAT_IN(3 downto 0); - when x"000c" => downscale_register_ts <= U_DAT_IN(3 downto 0); - when x"000d" => downscale_register_vs <= U_DAT_IN(3 downto 0); - when x"000e" => downscale_register_clock <= U_DAT_IN(3 downto 0); - when x"000f" => width_register_1 <= U_DAT_IN(3 downto 0); - when x"0010" => width_register_2 <= U_DAT_IN(3 downto 0); - when x"0011" => width_register_3 <= U_DAT_IN(3 downto 0); - when x"0012" => width_register_4 <= U_DAT_IN(3 downto 0); - when x"0013" => width_register_5 <= U_DAT_IN(3 downto 0); - when x"0014" => width_register_ts <= U_DAT_IN(3 downto 0); - when x"0015" => width_register_vs <= U_DAT_IN(3 downto 0); - when x"0016" => or_on_off <= U_DAT_IN(7 downto 0); - when x"0017" => mux_selector_1 <= U_DAT_IN(3 downto 0); - when x"0018" => mux_selector_2 <= U_DAT_IN(3 downto 0); - -- scalers must not be written by command - when x"0020" => input_enable <= U_DAT_IN(6 downto 0); - when x"0021" => width_output <= U_DAT_IN(3 downto 0); - when x"0022" => com_run <= U_DAT_IN(0); - when x"0023" => scaler_reset <= U_DAT_IN(7 downto 0); - when x"0024" => branch_en_with_mdc_tof_width <= U_DAT_IN(4 downto 0); - when x"0025" => scaler_mdc_tof_select <= U_DAT_IN(7 downto 0); - -- scalers must not be written by command - when x"0028" => pti5_ts_alternative <= U_DAT_IN(7 downto 0); - when x"0029" => delay_register_beam <= U_DAT_IN(7 downto 0); - when x"002a" => width_inhibit_register_beam <= U_DAT_IN(7 downto 0); - when x"002b" => width_external_register_beam <= U_DAT_IN(7 downto 0); - when x"002c" => ts_gating_disable <= U_DAT_IN(6 downto 0); - -- scalers must not be written by command - when x"0037" => cal_trigger_disable <= U_DAT_IN(0); - when x"0038" => dtu_error <= U_DAT_IN(0); - when x"0039" => dtu_code_select_i <= U_DAT_IN(4 downto 0); - when x"0041" => trb_busy_enable <= U_DAT_IN(0); - when others => null; - end case; - elsif OECSR = '1' then --write to VME bus - case (U_AD_REG(17 downto 2)) is - when x"0000" => U_DATA_O <= x"0000000" & delay_register_1; - when x"0001" => U_DATA_O <= x"0000000" & delay_register_2; - when x"0002" => U_DATA_O <= x"0000000" & delay_register_3; - when x"0003" => U_DATA_O <= x"0000000" & delay_register_4; - when x"0004" => U_DATA_O <= x"0000000" & delay_register_5; - when x"0005" => U_DATA_O <= x"0000000" & delay_register_ts; - when x"0006" => U_DATA_O <= x"0000000" & delay_register_vs; - when x"0007" => U_DATA_O <= x"0000000" & downscale_register_1; - when x"0008" => U_DATA_O <= x"0000000" & downscale_register_2; - when x"0009" => U_DATA_O <= x"0000000" & downscale_register_3; - when x"000a" => U_DATA_O <= x"0000000" & downscale_register_4; - when x"000b" => U_DATA_O <= x"0000000" & downscale_register_5; - when x"000c" => U_DATA_O <= x"0000000" & downscale_register_ts; - when x"000d" => U_DATA_O <= x"0000000" & downscale_register_vs; - when x"000e" => U_DATA_O <= x"0000000" & downscale_register_clock; - when x"000f" => U_DATA_O <= x"0000000" & width_register_1; - when x"0010" => U_DATA_O <= x"0000000" & width_register_2; - when x"0011" => U_DATA_O <= x"0000000" & width_register_3; - when x"0012" => U_DATA_O <= x"0000000" & width_register_4; - when x"0013" => U_DATA_O <= x"0000000" & width_register_5; - when x"0014" => U_DATA_O <= x"0000000" & width_register_ts; - when x"0015" => U_DATA_O <= x"0000000" & width_register_vs; - when x"0016" => U_DATA_O <= x"000000" & or_on_off; - when x"0017" => U_DATA_O <= x"0000000" & mux_selector_1; - when x"0018" => U_DATA_O <= x"0000000" & mux_selector_2; - when x"0019" => U_DATA_O <= scaler_pti1; - when x"001a" => U_DATA_O <= scaler_pti2; - when x"001b" => U_DATA_O <= scaler_pti3; - when x"001c" => U_DATA_O <= scaler_pti4; - when x"001d" => U_DATA_O <= scaler_pti5; - when x"001e" => U_DATA_O <= scaler_ts; - when x"001f" => U_DATA_O <= scaler_vs; - when x"0020" => U_DATA_O <= x"000000" & '0' & input_enable; - when x"0021" => U_DATA_O <= x"0000000" & width_output; - when x"0022" => U_DATA_O <= x"0000000" & "000" & com_run; - when x"0023" => U_DATA_O <= x"000000" & scaler_reset; - when x"0024" => U_DATA_O <= x"000000" & "000" & branch_en_with_mdc_tof_width; - when x"0025" => U_DATA_O <= x"000000" & scaler_mdc_tof_select; - when x"0026" => U_DATA_O <= scaler_mdc; - when x"0027" => U_DATA_O <= scaler_tof; - when x"0028" => U_DATA_O <= x"000000" & pti5_ts_alternative; - when x"0029" => U_DATA_O <= x"000000" & delay_register_beam; - when x"002a" => U_DATA_O <= x"000000" & width_inhibit_register_beam; - when x"002b" => U_DATA_O <= x"000000" & width_external_register_beam; - when x"002c" => U_DATA_O <= x"000000" & '0' & ts_gating_disable; --b0 - when x"002d" => U_DATA_O <= scaler_dead; - when x"002e" => U_DATA_O <= scaler_pti1_accepted; - when x"002f" => U_DATA_O <= scaler_pti2_accepted; - when x"0030" => U_DATA_O <= scaler_pti3_accepted; - when x"0031" => U_DATA_O <= scaler_pti4_accepted; - when x"0032" => U_DATA_O <= scaler_pti5_accepted; - when x"0033" => U_DATA_O <= scaler_ts_accepted; - when x"0034" => U_DATA_O <= scaler_vs_accepted; - when x"0035" => U_DATA_O <= scaler_mux1; - when x"0036" => U_DATA_O <= scaler_mux2; - when x"0037" => U_DATA_O <= x"0000000" & "000" & cal_trigger_disable; - when x"0038" => U_DATA_O <= x"0000000" & "000" & dtu_error; - when x"0039" => U_DATA_O <= x"000000" & "000" & dtu_code_select_i; - when x"0040" => U_DATA_O <= debug_1; - when x"0041" => U_DATA_O <= x"0000000" & "000" & trb_busy_enable; - when others => null; - end case; - end if; - end if; - end process; -end rtl; diff --git a/oldfiles/vulom3/vlogic_1.prj b/oldfiles/vulom3/vlogic_1.prj deleted file mode 100644 index c25b735..0000000 --- a/oldfiles/vulom3/vlogic_1.prj +++ /dev/null @@ -1,15 +0,0 @@ -vhdl work "set_width_special.vhd" -vhdl work "set_width.vhd" -vhdl work "scaler_s.vhd" -vhdl work "one_clock_long.vhd" -vhdl work "new_downscale_ck.vhd" -vhdl work "eco_delay.vhd" -vhdl work "downscale.vhd" -vhdl work "delay.vhd" -vhdl work "bus_data_com5.vhd" -vhdl work "beam_ramp.vhd" -vhdl work "trig_box1.vhd" -vhdl work "vmelogic.vhd" -vhdl work "ulogic.vhd" -vhdl work "clocking.vhd" -vhdl work "vlogic_1.vhd" diff --git a/oldfiles/vulom3/vlogic_1.sdc b/oldfiles/vulom3/vlogic_1.sdc deleted file mode 100644 index 95e2f2a..0000000 --- a/oldfiles/vulom3/vlogic_1.sdc +++ /dev/null @@ -1,57 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/marek/vulom3/vlogic_1.sdc -# Written on Mon Apr 28 11:36:24 2008 -# by Synplify Pro, Version 9.0.1 Scope Editor - -# -# Collections -# - -# -# Clocks -# - -define_clock {p:vlogic_1|CKFPL} -name {p:vlogic_1|CKFPL} -freq 110 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 5 -route 0 -define_clock {n:beam_ramp|clk_10Hz} -name {n:beam_ramp|clk_10Hz} -period 1000 -clockgroup Autoconstr_clkgroup_3 -rise 0 -fall 0.5 -route 0 -define_clock {n:CLKDV_BUFG_INST|CLKDV_OUT} -name {n:CLKDV_BUFG_INST|CLKDV_OUT} -freq 55 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 10 -route 0 -define_clock {n:CLKFX_BUFG_INST|CLKFX_OUT} -name {n:CLKFX_BUFG_INST|CLKFX_OUT} -freq 330 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 1.5 -route 0 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# - -# -# Registers -# - -# -# Multi-Cycle Paths -# - -# -# False Paths -# - -# -# Max Delay Paths -# - -# -# Attributes -# - -# -# I/O Standards -# - -# -# Compile Points -# - -# -# Other -# diff --git a/oldfiles/vulom3/vlogic_1.ucf b/oldfiles/vulom3/vlogic_1.ucf deleted file mode 100644 index 3e37e67..0000000 --- a/oldfiles/vulom3/vlogic_1.ucf +++ /dev/null @@ -1,249 +0,0 @@ -NET "AD<0>" LOC = "V16" | IOSTANDARD = "LVTTL"; -NET "AD<1>" LOC = "V15" | IOSTANDARD = "LVTTL"; -NET "AD<2>" LOC = "V6" | IOSTANDARD = "LVTTL"; -NET "AD<3>" LOC = "V5" | IOSTANDARD = "LVTTL"; -NET "AD<4>" LOC = "T14" | IOSTANDARD = "LVTTL"; -NET "AD<5>" LOC = "U13" | IOSTANDARD = "LVTTL"; -NET "AD<6>" LOC = "U8" | IOSTANDARD = "LVTTL"; -NET "AD<7>" LOC = "T7" | IOSTANDARD = "LVTTL"; -NET "AD<8>" LOC = "V13" | IOSTANDARD = "LVTTL"; -NET "AD<9>" LOC = "V12" | IOSTANDARD = "LVTTL"; -NET "AD<10>" LOC = "V9" | IOSTANDARD = "LVTTL"; -NET "AD<11>" LOC = "V8" | IOSTANDARD = "LVTTL"; -NET "AD<12>" LOC = "U12" | IOSTANDARD = "LVTTL"; -NET "AD<13>" LOC = "V11" | IOSTANDARD = "LVTTL"; -NET "AD<14>" LOC = "V10" | IOSTANDARD = "LVTTL"; -NET "AD<15>" LOC = "U9" | IOSTANDARD = "LVTTL"; -NET "AD<16>" LOC = "W13" | IOSTANDARD = "LVTTL"; -NET "AD<17>" LOC = "W12" | IOSTANDARD = "LVTTL"; -NET "AD<18>" LOC = "Y5" | IOSTANDARD = "LVTTL"; -NET "AD<19>" LOC = "W5" | IOSTANDARD = "LVTTL"; -NET "AD<20>" LOC = "Y12" | IOSTANDARD = "LVTTL"; -NET "AD<21>" LOC = "Y11" | IOSTANDARD = "LVTTL"; -NET "AD<22>" LOC = "Y6" | IOSTANDARD = "LVTTL"; -NET "AD<23>" LOC = "W6" | IOSTANDARD = "LVTTL"; -NET "AD<24>" LOC = "W11" | IOSTANDARD = "LVTTL"; -NET "AD<25>" LOC = "W10" | IOSTANDARD = "LVTTL"; -NET "AD<26>" LOC = "Y7" | IOSTANDARD = "LVTTL"; -NET "AD<27>" LOC = "W7" | IOSTANDARD = "LVTTL"; -NET "AD<28>" LOC = "Y10" | IOSTANDARD = "LVTTL"; -NET "AD<29>" LOC = "Y9" | IOSTANDARD = "LVTTL"; -NET "AD<30>" LOC = "W9" | IOSTANDARD = "LVTTL"; -NET "AD<31>" LOC = "W8" | IOSTANDARD = "LVTTL"; -NET "AI<0>" LOC = "L19" | IOSTANDARD = "LVTTL"; -NET "AI<1>" LOC = "M19" | IOSTANDARD = "LVTTL"; -NET "ASI" LOC = "R17" | IOSTANDARD = "LVTTL"; -NET "BERR" LOC = "U16" | IOSTANDARD = "LVTTL"; -NET "BERRO" LOC = "V20" | IOSTANDARD = "LVTTL"; -NET "BLTACK" LOC = "U17" | IOSTANDARD = "LVTTL"; -NET "CAIV" LOC = "R19" | IOSTANDARD = "LVTTL"; -NET "CKFNL" LOC = "B7" | IOSTANDARD = "LVTTL"; -NET "CKFPL" LOC = "A7" | IOSTANDARD = "LVTTL"; -NET "CON<0>" LOC = "F18" | IOSTANDARD = "LVTTL"; -NET "CON<1>" LOC = "E18" | IOSTANDARD = "LVTTL"; -NET "CON<2>" LOC = "C18" | IOSTANDARD = "LVTTL"; -NET "CON<3>" LOC = "C19" | IOSTANDARD = "LVTTL"; -NET "CON<4>" LOC = "F16" | IOSTANDARD = "LVTTL"; -NET "CON<5>" LOC = "F17" | IOSTANDARD = "LVTTL"; -NET "CON<6>" LOC = "D19" | IOSTANDARD = "LVTTL"; -NET "CON<7>" LOC = "E19" | IOSTANDARD = "LVTTL"; -NET "CON<8>" LOC = "G16" | IOSTANDARD = "LVTTL"; -NET "CON<9>" LOC = "G17" | IOSTANDARD = "LVTTL"; -NET "CON<10>" LOC = "E20" | IOSTANDARD = "LVTTL"; -NET "CON<11>" LOC = "F20" | IOSTANDARD = "LVTTL"; -NET "CON<12>" LOC = "H16" | IOSTANDARD = "LVTTL"; -NET "CON<13>" LOC = "H17" | IOSTANDARD = "LVTTL"; -NET "CON<14>" LOC = "F19" | IOSTANDARD = "LVTTL"; -NET "CON<15>" LOC = "G19" | IOSTANDARD = "LVTTL"; -NET "DI<0>" LOC = "N17" | IOSTANDARD = "LVTTL"; -NET "DI<1>" LOC = "N18" | IOSTANDARD = "LVTTL"; -NET "DI<2>" LOC = "N19" | IOSTANDARD = "LVTTL"; -NET "DI<3>" LOC = "P16" | IOSTANDARD = "LVTTL"; -NET "DI<4>" LOC = "P17" | IOSTANDARD = "LVTTL"; -NET "DI<5>" LOC = "P19" | IOSTANDARD = "LVTTL"; -NET "DI<6>" LOC = "P20" | IOSTANDARD = "LVTTL"; -#NET "DOUT_LCD" LOC = "M16" | IOSTANDARD = "LVTTL"; -NET "DS0I" LOC = "T19" | IOSTANDARD = "LVTTL"; -NET "DS1I" LOC = "T20" | IOSTANDARD = "LVTTL"; -NET "ECL<1>" LOC = "B15" | IOSTANDARD = "LVTTL"; -NET "ECL<2>" LOC = "A15" | IOSTANDARD = "LVTTL"; -NET "ECL<3>" LOC = "A16" | IOSTANDARD = "LVTTL"; -NET "ECL<4>" LOC = "B16" | IOSTANDARD = "LVTTL"; -NET "ECL<5>" LOC = "C15" | IOSTANDARD = "LVTTL"; -NET "ECL<6>" LOC = "C16" | IOSTANDARD = "LVTTL"; -NET "ECL<7>" LOC = "B17" | IOSTANDARD = "LVTTL"; -NET "ECL<8>" LOC = "C17" | IOSTANDARD = "LVTTL"; -NET "ECL<9>" LOC = "D16" | IOSTANDARD = "LVTTL"; -NET "ECL<10>" LOC = "E16" | IOSTANDARD = "LVTTL"; -NET "ECL<11>" LOC = "A18" | IOSTANDARD = "LVTTL"; -NET "ECL<12>" LOC = "B18" | IOSTANDARD = "LVTTL"; -NET "ECL<13>" LOC = "D17" | IOSTANDARD = "LVTTL"; -NET "ECL<14>" LOC = "D18" | IOSTANDARD = "LVTTL"; -NET "ECL<15>" LOC = "B19" | IOSTANDARD = "LVTTL"; -NET "ECL<16>" LOC = "C20" | IOSTANDARD = "LVTTL"; -NET "ECO<1>" LOC = "A5" | IOSTANDARD = "LVTTL"; -NET "ECO<2>" LOC = "B5" | IOSTANDARD = "LVTTL"; -NET "ECO<3>" LOC = "C6" | IOSTANDARD = "LVTTL"; -NET "ECO<4>" LOC = "C5" | IOSTANDARD = "LVTTL"; -NET "ECO<5>" LOC = "B4" | IOSTANDARD = "LVTTL"; -NET "ECO<6>" LOC = "C4" | IOSTANDARD = "LVTTL"; -NET "ECO<7>" LOC = "D5" | IOSTANDARD = "LVTTL"; -NET "ECO<8>" LOC = "E5" | IOSTANDARD = "LVTTL"; -NET "ECO<9>" LOC = "A3" | IOSTANDARD = "LVTTL"; -NET "ECO<10>" LOC = "B3" | IOSTANDARD = "LVTTL"; -NET "ECO<11>" LOC = "D4" | IOSTANDARD = "LVTTL"; -NET "ECO<12>" LOC = "D3" | IOSTANDARD = "LVTTL"; -NET "ECO<13>" LOC = "B2" | IOSTANDARD = "LVTTL"; -NET "ECO<14>" LOC = "C1" | IOSTANDARD = "LVTTL"; -NET "ECO<15>" LOC = "F3" | IOSTANDARD = "LVTTL"; -NET "ECO<16>" LOC = "E3" | IOSTANDARD = "LVTTL"; -NET "EN<1>" LOC = "M20" | IOSTANDARD = "LVTTL"; -NET "EN<2>" LOC = "L20" | IOSTANDARD = "LVTTL"; -NET "EN<3>" LOC = "M17" | IOSTANDARD = "LVTTL"; -NET "EN<4>" LOC = "M18" | IOSTANDARD = "LVTTL"; -NET "FLED<1>" LOC = "H20" | IOSTANDARD = "LVTTL"; -NET "FLED<2>" LOC = "J15" | IOSTANDARD = "LVTTL"; -NET "FLED<3>" LOC = "J16" | IOSTANDARD = "LVTTL"; -NET "FLED<4>" LOC = "H18" | IOSTANDARD = "LVTTL"; -NET "FLED<5>" LOC = "H19" | IOSTANDARD = "LVTTL"; -NET "FLED<6>" LOC = "G20" | IOSTANDARD = "LVTTL"; -NET "HPV<0>" LOC = "H1" | IOSTANDARD = "LVTTL" | SLEW = SLOW ; -NET "HPV<1>" LOC = "G1" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<2>" LOC = "J6" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<3>" LOC = "J5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<4>" LOC = "H3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<5>" LOC = "H2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<6>" LOC = "K5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<7>" LOC = "K4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<8>" LOC = "K1" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<9>" LOC = "J2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<10>" LOC = "L5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<11>" LOC = "L4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<12>" LOC = "K3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<13>" LOC = "K2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<14>" LOC = "M4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPV<15>" LOC = "M3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; -NET "HPW<0>" LOC = "C3" | IOSTANDARD = "LVTTL"; -NET "HPW<1>" LOC = "C2" | IOSTANDARD = "LVTTL"; -NET "HPW<2>" LOC = "F5" | IOSTANDARD = "LVTTL"; -NET "HPW<3>" LOC = "F4" | IOSTANDARD = "LVTTL"; -NET "HPW<4>" LOC = "D2" | IOSTANDARD = "LVTTL"; -NET "HPW<5>" LOC = "E2" | IOSTANDARD = "LVTTL"; -NET "HPW<6>" LOC = "G5" | IOSTANDARD = "LVTTL"; -NET "HPW<7>" LOC = "G4" | IOSTANDARD = "LVTTL"; -NET "HPW<8>" LOC = "E1" | IOSTANDARD = "LVTTL"; -NET "HPW<9>" LOC = "F1" | IOSTANDARD = "LVTTL"; -NET "HPW<10>" LOC = "H5" | IOSTANDARD = "LVTTL"; -NET "HPW<11>" LOC = "H4" | IOSTANDARD = "LVTTL"; -NET "HPW<12>" LOC = "F2" | IOSTANDARD = "LVTTL"; -NET "HPW<13>" LOC = "G2" | IOSTANDARD = "LVTTL"; -NET "HPW<14>" LOC = "J4" | IOSTANDARD = "LVTTL"; -NET "HPW<15>" LOC = "J3" | IOSTANDARD = "LVTTL"; -NET "IACKII" LOC = "T15" | IOSTANDARD = "LVTTL"; -NET "IACKOU" LOC = "U15" | IOSTANDARD = "LVTTL"; -NET "IOO<1>" LOC = "B12" | IOSTANDARD = "LVTTL"; -NET "IOO<2>" LOC = "A11" | IOSTANDARD = "LVTTL"; -NET "IOO<3>" LOC = "A10" | IOSTANDARD = "LVTTL"; -NET "IOO<4>" LOC = "B9" | IOSTANDARD = "LVTTL"; -NET "IOO<5>" LOC = "C11" | IOSTANDARD = "LVTTL"; -NET "IOO<6>" LOC = "B11" | IOSTANDARD = "LVTTL"; -NET "IOO<7>" LOC = "B10" | IOSTANDARD = "LVTTL"; -NET "IOO<8>" LOC = "C10" | IOSTANDARD = "LVTTL"; -NET "IOO<9>" LOC = "B13" | IOSTANDARD = "LVTTL"; -NET "IOO<10>" LOC = "A13" | IOSTANDARD = "LVTTL"; -NET "IOO<11>" LOC = "A8" | IOSTANDARD = "LVTTL"; -NET "IOO<12>" LOC = "B8" | IOSTANDARD = "LVTTL"; -NET "IOO<13>" LOC = "B14" | IOSTANDARD = "LVTTL"; -NET "IOO<14>" LOC = "A14" | IOSTANDARD = "LVTTL"; -NET "IOO<15>" LOC = "B6" | IOSTANDARD = "LVTTL"; -NET "IOO<16>" LOC = "A6" | IOSTANDARD = "LVTTL"; -NET "IRBLO" LOC = "V19" | IOSTANDARD = "LVTTL"; -NET "LEMIN<1>" LOC = "R4" | IOSTANDARD = "LVTTL"; -NET "LEMIN<2>" LOC = "R3" | IOSTANDARD = "LVTTL"; -NET "LEMOU<1>" LOC = "T2" | IOSTANDARD = "LVTTL"; -NET "LEMOU<2>" LOC = "T1" | IOSTANDARD = "LVTTL"; -NET "OAIV" LOC = "R20" | IOSTANDARD = "LVTTL"; -NET "PRES" LOC = "U19" | IOSTANDARD = "LVTTL"; -NET "RES<1>" LOC = "T18" | IOSTANDARD = "LVTTL"; -NET "RES<2>" LOC = "U18" | IOSTANDARD = "LVTTL"; -NET "SAD<0>" LOC = "M1" | IOSTANDARD = "LVTTL"; -NET "SAD<1>" LOC = "L1" | IOSTANDARD = "LVTTL"; -NET "SAD<2>" LOC = "M6" | IOSTANDARD = "LVTTL"; -NET "SAD<3>" LOC = "M5" | IOSTANDARD = "LVTTL"; -NET "SAD<4>" LOC = "M2" | IOSTANDARD = "LVTTL"; -NET "SAD<5>" LOC = "L2" | IOSTANDARD = "LVTTL"; -NET "SAD<6>" LOC = "N5" | IOSTANDARD = "LVTTL"; -NET "SAD<7>" LOC = "N4" | IOSTANDARD = "LVTTL"; -NET "SAD<8>" LOC = "N3" | IOSTANDARD = "LVTTL"; -NET "SAD<9>" LOC = "N2" | IOSTANDARD = "LVTTL"; -NET "SAD<10>" LOC = "P5" | IOSTANDARD = "LVTTL"; -NET "SAD<11>" LOC = "P4" | IOSTANDARD = "LVTTL"; -NET "SAD<12>" LOC = "P2" | IOSTANDARD = "LVTTL"; -NET "SAD<13>" LOC = "P1" | IOSTANDARD = "LVTTL"; -NET "SAD<14>" LOC = "R2" | IOSTANDARD = "LVTTL"; -NET "SAD<15>" LOC = "R1" | IOSTANDARD = "LVTTL"; -NET "SAD<16>" LOC = "R6" | IOSTANDARD = "LVTTL"; -NET "SAD<17>" LOC = "R5" | IOSTANDARD = "LVTTL"; -NET "SCS" LOC = "V18" | IOSTANDARD = "LVTTL"; -NET "SDA<0>" LOC = "U3" | IOSTANDARD = "LVTTL"; -NET "SDA<1>" LOC = "U2" | IOSTANDARD = "LVTTL"; -NET "SDA<2>" LOC = "T4" | IOSTANDARD = "LVTTL"; -NET "SDA<3>" LOC = "T3" | IOSTANDARD = "LVTTL"; -NET "SDA<4>" LOC = "T6" | IOSTANDARD = "LVTTL"; -NET "SDA<5>" LOC = "U6" | IOSTANDARD = "LVTTL"; -NET "SDA<6>" LOC = "V2" | IOSTANDARD = "LVTTL"; -NET "SDA<7>" LOC = "V1" | IOSTANDARD = "LVTTL"; -NET "SDA<8>" LOC = "U5" | IOSTANDARD = "LVTTL"; -NET "SDA<9>" LOC = "U4" | IOSTANDARD = "LVTTL"; -NET "SDA<10>" LOC = "W3" | IOSTANDARD = "LVTTL"; -NET "SDA<11>" LOC = "W2" | IOSTANDARD = "LVTTL"; -NET "SDA<12>" LOC = "Y4" | IOSTANDARD = "LVTTL"; -NET "SDA<13>" LOC = "W4" | IOSTANDARD = "LVTTL"; -NET "SDA<14>" LOC = "V4" | IOSTANDARD = "LVTTL"; -NET "SDA<15>" LOC = "V3" | IOSTANDARD = "LVTTL"; -NET "SOE" LOC = "V17" | IOSTANDARD = "LVTTL"; -NET "SWE" LOC = "W17" | IOSTANDARD = "LVTTL"; -NET "TIN<1>" LOC = "F15" | IOSTANDARD = "LVTTL"; -NET "TIN<2>" LOC = "E15" | IOSTANDARD = "LVTTL"; -NET "TIN<3>" LOC = "E6" | IOSTANDARD = "LVTTL"; -NET "TIN<4>" LOC = "F6" | IOSTANDARD = "LVTTL"; -NET "TIN<5>" LOC = "D15" | IOSTANDARD = "LVTTL"; -NET "TIN<6>" LOC = "E14" | IOSTANDARD = "LVTTL"; -NET "TIN<7>" LOC = "E7" | IOSTANDARD = "LVTTL"; -NET "TIN<8>" LOC = "D6" | IOSTANDARD = "LVTTL"; -NET "TIN<9>" LOC = "D13" | IOSTANDARD = "LVTTL"; -NET "TIN<10>" LOC = "C13" | IOSTANDARD = "LVTTL"; -NET "TIN<11>" LOC = "C8" | IOSTANDARD = "LVTTL"; -NET "TIN<12>" LOC = "D8" | IOSTANDARD = "LVTTL"; -NET "TIN<13>" LOC = "D12" | IOSTANDARD = "LVTTL"; -NET "TIN<14>" LOC = "C12" | IOSTANDARD = "LVTTL"; -NET "TIN<15>" LOC = "C9" | IOSTANDARD = "LVTTL"; -NET "TIN<16>" LOC = "D9" | IOSTANDARD = "LVTTL"; -NET "WRDIS" LOC = "N16" | IOSTANDARD = "LVTTL"; -NET "WRI" LOC = "R18" | IOSTANDARD = "LVTTL"; -#NET "CKFNL" TNM_NET = CKFNL; -#TIMESPEC TS_CKFNL = PERIOD "CKFNL" 100 MHz; -NET "CKFPL" TNM_NET = CKFPL; -TIMESPEC TS_CKFPL = PERIOD "CKFPL" 100 MHz; - - -#NET "ulg_1/trgb_1/Inst_beam_ramp/clk_10Hz" TNM_NET=ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz ; -#TIMESPEC TS_ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz = PERIOD "ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz" 1 MHz;# Generated by Xilinx Architecture Wizard -# --- UCF Template Only --- -# Cut and paste these attributes into the project's UCF file, if desired -#INST DCM_ADV_INST CLK_FEEDBACK = 1X; -#INST DCM_ADV_INST CLKDV_DIVIDE = 2.0; -#INST DCM_ADV_INST CLKFX_DIVIDE = 1; -#INST DCM_ADV_INST CLKFX_MULTIPLY = 3; -#INST DCM_ADV_INST CLKIN_DIVIDE_BY_2 = FALSE; -#INST DCM_ADV_INST CLKIN_PERIOD = 10.000; -#INST DCM_ADV_INST CLKOUT_PHASE_SHIFT = NONE; -#INST DCM_ADV_INST DCM_AUTOCALIBRATION = TRUE; -#INST DCM_ADV_INST DCM_PERFORMANCE_MODE = MAX_SPEED; -#INST DCM_ADV_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; -#INST DCM_ADV_INST DFS_FREQUENCY_MODE = HIGH; -#INST DCM_ADV_INST DLL_FREQUENCY_MODE = LOW; -#INST DCM_ADV_INST DUTY_CYCLE_CORRECTION = TRUE; -#INST DCM_ADV_INST FACTORY_JF = F0F0; -#INST DCM_ADV_INST PHASE_SHIFT = 0; -#INST DCM_ADV_INST STARTUP_WAIT = FALSE; diff --git a/oldfiles/vulom3/vlogic_1.vhd b/oldfiles/vulom3/vlogic_1.vhd deleted file mode 100644 index c21450d..0000000 --- a/oldfiles/vulom3/vlogic_1.vhd +++ /dev/null @@ -1,272 +0,0 @@ --------------------------------------------------------------------------------- --- Company: GSI --- Engineer: Jan Hoffman, Davide Leoni --- --- Create Date: 8/8/07 --- Design Name: vulom3 --- Module Name: vlogic_1 - Behavioral --- Project Name: triggerbox --- Target Device: XC4VLX25-10SF363 --- Tool versions: --- Description: Top module, DCM, display, LEDs, VME signals --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -Library UNISIM; -use UNISIM.vcomponents.all; - -entity vlogic_1 is - port ( ---............................. VME Signals ............................................ - AD : inout std_logic_vector(31 downto 0); -- VME Address-Data bus - AMI : in std_logic_vector(5 downto 0); -- VME Address modifier internal - ASI : in std_logic; -- Address strobe - WRI : in std_logic; -- write - BERR : in std_logic; -- bus error for chain block transfer - BERRO : out std_logic; -- bus error for chain block transfer - DS0I : in std_logic; -- data strobe - DS1I : in std_logic; -- data strobe - IACKII : in std_logic; -- interrupt acknowledge chain - IACKOU : out std_logic; -- interrupt acknowledge chain - IRBLO : out std_logic; -- interrupt 4 output to VME or BLACK output --- MON : in std_logic_vector(7 downto 0); -- VME module number connected to hex. switch VN2 .. VN1 ---............................. Buffer/Register Controll Signals ............................................ - CAIV : out std_logic; -- Address buffer clock signal Int->VME - OAIV : out std_logic; -- Address buffer OE Int->VME ---............................. Front panel Controll Signals ............................................ - ECO : inout std_logic_vector(16 downto 1); --signals to ECL output(1 is the lower connector of ECL OUT) - EN : out std_logic_vector(4 downto 1); -- ECL enable (EN1 for ch. 1-8, EN2 for ch. 9-16) - ECL : in std_logic_vector(16 downto 1); -- signals from ECL input (1 is at the lower connector of ECL IN) - IOO : in std_logic_vector(16 downto 1); -- signals ioo from ECL I/O (1 is at the lower connector) - TIN : inout std_logic_vector(16 downto 1); -- output signals to ECL I/O (1 is at the lower connector) - LEMIN : in std_logic_vector(2 downto 1); -- signals from LEMO upper - LEMOU : out std_logic_vector(2 downto 1); -- signals to LEMO lower ---............................. SRAM Controll Signals ............................................ - SAD : out std_logic_vector(17 downto 0); -- address - SDA : inout std_logic_vector(15 downto 0); -- data - SCS : out std_logic; - SOE : out std_logic; - SWE : out std_logic; ---............................. DISPLAY and LED Controll Signals ............................................ - DI : inout std_logic_vector(6 downto 0); - AI : out std_logic_vector(1 downto 0); -- display address ( use 1 and 2 only, 0 and 3 can't be seen) - WRDIS : out std_logic; -- display write - FLED : out std_logic_vector(6 downto 1); -- Front panel LED ---............................. Euroball Readot Signals ............................................ --- PASSO : over HPV or HPW --- RENI : over HPV or HPW - BLTACK : in std_logic; ---............................. System Signals ............................................ - PRES : in std_logic; -- reset positive from reset IC --- SRESI : in std_logic; -- reset from VME - RES : in std_logic_vector(2 downto 1); -- reset from CPLD - CKFNL : in std_logic; -- Diff 100 MHz ck neg - CKFPL : in std_logic; -- Diff 100 MHz ck pos - CON : inout std_logic_vector(15 downto 0); -- Connection between PROG and vlogic_1 - HPV : inout std_logic_vector(15 downto 0); -- Logic analyzer signals - HPW : inout std_logic_vector(15 downto 0) -- Logic analyzer signals - ); -end vlogic_1; -architecture rtl of vlogic_1 is -component clocking -port( - CLKIN_IN : IN std_logic; - CLKDV_OUT : OUT std_logic; - CLKFX_OUT : OUT std_logic; - CLKIN_IBUFG_OUT : OUT std_logic; - CLK0_OUT : OUT std_logic; - LOCKED_OUT : OUT std_logic - ); -end component; -component ulogic port ( - RESET : in std_logic; - CK50 : in std_logic; - CK300 : in std_logic; - CK100 : in std_logic; - LEMOU : out std_logic_vector(2 downto 1); - LEMIN : in std_logic_vector(2 downto 1); - TIN : out std_logic_vector(16 downto 1); - ECO : out std_logic_vector(16 downto 1); - ECL : in std_logic_vector(16 downto 1); - IOO : in std_logic_vector(16 downto 1); - EN : out std_logic_vector(4 downto 1); - FLED_T: out std_logic_vector(6 downto 1); -- to front panel LEDs ---............................. vme interface .................... - U_AD_REG : in std_logic_vector(21 downto 2); - U_DAT_IN : in std_logic_vector(31 downto 0); - U_DATA_O : out std_logic_vector(31 downto 0); - OECSR, CKCSR : in std_logic; - HPV : inout std_logic_vector(15 downto 0); - HPW : inout std_logic_vector(15 downto 0) - ); -end component; - -component vmelogic port ( - ASIS :in std_logic; -- - DSR :in std_logic; -- - AD :inout std_logic_vector(31 downto 0); - AD_REG :inout std_logic_vector(31 downto 0); - WRI :in std_logic; - AMI :in std_logic_vector(5 downto 0); - CKCSR :out std_logic; -- clock data into csr - OECSR :out std_logic; -- output data from csr to VME - CON :inout std_logic_vector(15 downto 0); - HPLB :out std_logic_vector(15 downto 0); - CK50 :in std_logic - ); -end component; -signal reset : std_logic; -signal count : std_logic_vector (23 downto 0); -signal counth : std_logic_vector (27 downto 0); -signal counf : std_logic_vector (7 downto 0); ------------------------------------------------------------------------------------------------- -signal tri_dat : std_logic_vector (15 downto 0); -- trigger bus level data -signal led_out : std_logic_vector (4 downto 1); -- 4 LEDs, on piggy -signal lemo_dat : std_logic_vector (15 downto 0); -- 4 bit data from LEMO input -signal enable, oecsr, ckcsr, asis, dsr : std_logic; -- enable internal data bus to outside of fpga -signal mres, sta_dis : std_logic; -- internal acknowledge -signal din, dadis : std_logic_vector (31 downto 0); -- internal data bus, CSR --------------------------------------------------------------------------------------------------- -signal en_trcnt : std_logic; -constant tr_cnt_dat : std_logic_vector(7 downto 0) := x"20"; -signal tr_cnt : std_logic_vector(7 downto 0); -signal u_ad_reg : std_logic_vector(21 downto 2); -signal u_dat_in, u_data_o, ad_reg, pdone :std_logic_vector(31 downto 0); -signal dis_out :std_logic_vector (1 downto 0); -signal fled_t : std_logic_vector(6 downto 1); --- -signal hp : std_logic_vector (3 downto 0); -- states of flash machine -signal hplb : std_logic_vector (15 downto 0); -- -signal prova, to_LED6, SOFT_RESET : std_logic; ----------------------------- -signal rst, clk2x, clk0, ck50, ck300, ck100, locked : std_logic; -- internal acknowledge -------------------------------------------------------------------------------- -signal clk : std_logic; -begin - -- CLK ---------------------------------------------------------------------- --- IBUFGDS_CLK : IBUFGDS --- generic map ( --- IOSTANDARD => "LVDS_25_DCI") --- port map ( --- O => clk,--CLK, --- I => CKFPL, --- IB => CKFNL -- Diff_n clock buffer input (connect to top-level port) --- ); - Inst_clocking : clocking port map( - CLKIN_IN => CKFPL, - CLKDV_OUT => ck50, --50MHz clock - CLKFX_OUT => ck300, --300MHz clock - CLKIN_IBUFG_OUT => open, - CLK0_OUT => ck100, --100MHz clock - LOCKED_OUT => to_led6); - ulg_1 : ulogic port map ( - RESET => reset, - CK50 => CK50, - CK300 => CK300, - CK100 => CK100, - LEMIN => LEMIN, - LEMOU => LEMOU, - TIN => TIN, - EN => EN, - ECO => ECO, - ECL => ECL, - IOO => IOO, - FLED_T => fled_t, - U_AD_REG => u_ad_reg, - U_DAT_IN => u_dat_in, - U_DATA_O => u_data_o, - OECSR => oecsr, - CKCSR => ckcsr, - HPV => HPV, - HPW => HPW - ); - vme_1 : vmelogic port map ( - ASIS => asis, - DSR => dsr, - AD => ad, - AD_REG => ad_reg, - WRI => WRI, - AMI => AMI, - CKCSR => ckcsr, - OECSR => oecsr, - CON => CON, - HPLB => hplb, - CK50 => ck50); ---------------------------------------------------------------------------------------------- ---...............................RESET signal............................................ - reset <= PRES or res(1); -- or not SRESI; -- PRES active high from power IC, - -- SRESI active low from VME ----------------------------------PANEL LED--------------------------------------------------- - process (ck50) - begin - if rising_edge(ck50) then - FLED(6) <= not to_led6; --led on if pll is working - FLED(5 downto 1) <= fled_t(5 downto 1); --leds on if inputs enabled - end if; - end process; ---............................... signals to/from CPLD ....................................... - mres <= '1'; ---............................... display ....................................... - process (ck50) - begin - if (ck50'event and ck50 = '1') then - count <= count + 1; - end if; - end process; - process (count(4)) - begin - if rising_edge(count(4)) then - WRDIS <= count(5); - if count(6) = '0' then - AI <= "01"; - DI <= CONV_STD_LOGIC_VECTOR(51, 7); -- 33h "3" ascii - else - AI <= "10"; - DI <= CONV_STD_LOGIC_VECTOR(51, 7); -- 32h "2" ascii - end if; - end if; - end process; ---............................. VME Signals ............................................ - BERRO <= '1'; -- H means inactive - IACKOU <= IACKII; -- interrupt acknowledge chain --- SRESI -- system reset - process(ck50, asi, ds0i, ds1i) - begin - if (ck50'event and ck50 = '1') then - asis <= not asi; - dsr <= not ds0i and not ds1i; -- synchronized DS input from VME - end if; - end process; ---------------------------- VME address buffer control signals ------------------------------- - CAIV <= '1'; -- clock for address register internal<-VME, disabled - OAIV <= '1'; -- OE for address register internal<-VME, disabled - u_ad_reg <= ad_reg(21 downto 2); - u_dat_in <= ad; ------------------------ DATA MULTIPLEXER for OUTPUT to VME ------------------------------------------- - process(ck50) - begin - if (ck50'event and ck50 = '1') then - if (oecsr = '1') then - din <= u_data_o; -- data to VME over AD bus --- elsif (dis_out(1)='1') then din <= dadis; -- display data over AD bus not necessary with vulom3 /*/*/*/*/*/ - else - din <= (others => '0'); - end if; - end if; - end process; - enable <= oecsr; --or dis_out(1); -- address and data bus output not necessary with vulom3 /*/*/*/*/*/ - AD <= din when enable = '1' else (others => 'Z'); ------------------------------------ end of VME ----------------------------------------------- -------------------------------------------------------------------------------- --- * UNUSED @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Unused Signals @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ---------------------------------------------------------------------------------- - IRBLO <= '1'; - SCS <= '1'; - SOE <= '0'; - SWE <= '0'; - SAD <= (others => '0'); --- con(15 downto 7) <= b"000000000"; -end rtl; diff --git a/oldfiles/vulom3/vlogic_1_syn.prj b/oldfiles/vulom3/vlogic_1_syn.prj deleted file mode 100644 index 6f6c43c..0000000 --- a/oldfiles/vulom3/vlogic_1_syn.prj +++ /dev/null @@ -1,76 +0,0 @@ -#-- Synplicity, Inc. -#-- Version 9.0 -#-- Project file /home/marek/vulom3/vlogic_1_syn.prj -#-- Written on Mon Apr 28 11:33:20 2008 - - -#add_file options -add_file -vhdl -lib work "vlogic_1.vhd" -add_file -vhdl -lib work "clocking.vhd" -add_file -vhdl -lib work "ulogic.vhd" -add_file -vhdl -lib work "vmelogic.vhd" -add_file -vhdl -lib work "trig_box1.vhd" -add_file -vhdl -lib work "one_clock_long.vhd" -add_file -vhdl -lib work "delay.vhd" -add_file -vhdl -lib work "downscale.vhd" -add_file -vhdl -lib work "set_width.vhd" -add_file -vhdl -lib work "set_width_special.vhd" -add_file -vhdl -lib work "scaler.vhd" -add_file -vhdl -lib work "scaler_s.vhd" -add_file -vhdl -lib work "eco_delay.vhd" -add_file -vhdl -lib work "new_downscale_ck.vhd" -add_file -vhdl -lib work "beam_ramp.vhd" -add_file -vhdl -lib work "bus_data_com5.vhd" -add_file -constraint "vlogic_1.sdc" - - -#implementation: "workdir" -impl -add workdir -type fpga - -#device options -set_option -technology VIRTEX4 -set_option -part XC4VLX15 -set_option -package SF363 -set_option -speed_grade -10 - -#compilation/mapping options -set_option -default_enum_encoding default -set_option -resource_sharing 1 -set_option -use_fsm_explorer 1 -set_option -top_module "vlogic_1" - -#map options -set_option -frequency 110.000 -set_option -run_prop_extract 0 -set_option -fanout_limit 100 -set_option -disable_io_insertion 0 -set_option -pipe 1 -set_option -update_models_cp 1 -set_option -verification_mode 0 -set_option -retiming 1 -set_option -no_sequential_opt 0 -set_option -fixgatedclocks 3 -set_option -fixgeneratedclocks 3 - - -#sequential_optimizations options -set_option -symbolic_fsm_compiler 1 - -#simulation options -set_option -write_verilog 0 -set_option -write_vhdl 0 - -#VIF options -set_option -write_vif 1 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "workdir/vlogic_1.edf" - -# -#implementation attributes - -set_option -synthesis_onoff_pragma 0 -impl -active "workdir" diff --git a/oldfiles/vulom3/vmelogic.vhd b/oldfiles/vulom3/vmelogic.vhd deleted file mode 100644 index 7e1e9bc..0000000 --- a/oldfiles/vulom3/vmelogic.vhd +++ /dev/null @@ -1,247 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; --- --- vme_1: vmelogic port map (asis=>asis, dsr=>dsr, ad=>ad, wri=>wri, ami=>ami, mon=>mon, con=>con, xxx=>xxx, - - entity vmelogic is - port (asis :in std_logic; -- - dsr :in std_logic; -- - ad :inout std_logic_vector(31 downto 0); - ad_reg :inout std_logic_vector(31 downto 0); - wri :in std_logic; - ami :in std_logic_vector(5 downto 0); --- mon :in std_logic_vector(7 downto 0); - ckcsr :out std_logic; -- clock data into csr - oecsr :out std_logic; -- output data from csr to VME - con :inout std_logic_vector(15 downto 0); - hplb :out std_logic_vector(15 downto 0); - ck50 :in std_logic - ); -end vmelogic; --- -architecture RTL of vmelogic is -------------------------------------------------------------------------------------------- -------------------------------- vme signals ----------------------------------------------- -signal ckad : std_logic; -- clock for internal address register -signal stda : std_logic; -- start data phase state machine -signal wrs : std_logic; -- synchronized VME WRITE -signal ack_csr : std_logic; -- internal acknowledge csr -signal ack_hpi : std_logic; -- internal acknowledge hpi -signal ack_fsh : std_logic; -- internal acknowledge flash -signal ack_vr : std_logic; -- internal acknowledge vram 32 -signal aph_sta, dph_sta : std_logic_vector (3 downto 0); -- states of aph machine -signal enable : std_logic; -- enable internal data bus to outside of fpga ---signal vafsh : std_logic_vector (3 downto 0); -- vme address phase outputs for flash ---signal va64 : std_logic_vector (3 downto 0); -- vme data phase for VRAM64 (dual port ram) -signal vdcsr : std_logic_vector (3 downto 0); -- vme data phase outputs for external vme buffer register -signal amr : std_logic_vector (5 downto 0); -- internal address modifier register for VME address -signal int_res : std_logic_vector (23 downto 22); -- internal address register for VME address -signal sel_rnd : std_logic; -- FLASH, CSR, HPI, DPRAM random access -signal sel_bt32 : std_logic; -- DPRAM BT 32 access ---signal sel_bt64 : std_logic; -- DPRAM BT 64 access -signal selcsr : std_logic; -- CSR selected -signal selflsh : std_logic; -- FLASH selected -signal ad_co : std_logic_vector (1 downto 0); -- vme address phase outputs for: stda = start data phase... -signal csr_o : std_logic_vector (1 downto 0); -- vme data phase outputs for csr -signal pr_ou : std_logic_vector (1 downto 0); -- priority encoder outputs -signal tr_ou : std_logic_vector (15 downto 0); -- priority encoder outputs -signal vram : std_logic; -- vram1 or vram2 32/64 bit selected -signal vulom_sel : std_logic; -signal ckcsro : std_logic_vector (1 downto 0); -- internal CSR -signal oecsro : std_logic_vector (1 downto 0); -- internal CSR -signal din,csrr0,csrr1 : std_logic_vector (31 downto 0); -- internal data bus, CSR ------------------- VME address modifier ------------------------------ -constant am_f :std_logic_vector(5 downto 0) := b"001111";--AM543210=001111 ext. Extended supervisory block transfer -constant am_e :std_logic_vector(5 downto 0) := b"001110";--AM543210=001110 ext. supervisory program access -constant am_d :std_logic_vector(5 downto 0) := b"001101";--AM543210=001101 ext. Extended supervisory data access -constant am_a :std_logic_vector(5 downto 0) := b"001010";--AM543210=001010 ext. Extended non-privileged program access -constant am_b :std_logic_vector(5 downto 0) := b"001011";--AM543210=001011 ext. Extended non-privileged block transfer -constant am_9 :std_logic_vector(5 downto 0) := b"001001";--AM543210=001001 ext. Extended non-privileged data access -constant am_8 :std_logic_vector(5 downto 0) := b"001000";--AM543210=001000 ext. Extended non-privileged 64-bit block transfer -constant am_1b :std_logic_vector(5 downto 0) := b"011011";--AM543210=011011 ext. Eurogram Readout -constant am_29 :std_logic_vector(5 downto 0) := b"101001";--AM543210=101001 ext. Direct Configuration of FPGA ------------------- VME addresses -------------------------------------- -constant csr_ad :std_logic_vector(3 downto 2) := b"00";----vmeaddr=XX00 0000 - XX00 000C ---constant sram_ad :std_logic_vector(3 downto 2) := x"01";----vmeaddr=XX40 0000 - XX40 FFFC --- ............... vme address phase state machine, states declaration ......................... -type vme_adr_typ is (va00,va01,va02,va03,va04,va05,va0b); -- va06,va07,va08,va09,va0a, -signal vme_adr, vme_anx : vme_adr_typ; --- ............... vme data phase state machine for CSR ......................... -signal st_csr_drd : std_logic; -- start state machine for CSR read -signal st_csr_dwr : std_logic; -- start state machine for CSR write -type vmdacs_typ is (vc00,vc01,vc02,vc03,vc04,vc05,vc06,vc07,vc08,vc09,vc0a,vc0b,vc0c,vc0d,vc0e); -signal vmdacs, vmdacs_nx : vmdacs_typ; - ------------------------------------------------------------------------------------------- -begin ---- BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------ ---.......................................................................................... ---...................... VME address phase state machine ....................... - process (vme_adr,asis) -- states are - va00,va01,va02,va03,va04,va05,va06,va07,va08 - begin -- ad_co[]=stda,ckad - case vme_adr is - when va00 => ad_co <= b"00"; aph_sta <= x"0"; - if asis ='1' then vme_anx <= va01; - else vme_anx <= va00; - end if; - when va01 => ad_co <= b"00"; aph_sta <= x"1"; - if asis ='1' then vme_anx <= va02; - else vme_anx <= va00; - end if; - when va02 => vme_anx <= va03; ad_co <= b"00"; aph_sta <= x"2"; - when va03 => vme_anx <= va04; ad_co <= b"00"; aph_sta <= x"3"; - when va04 => vme_anx <= va05; ad_co <= b"01"; aph_sta <= x"4"; - when va05 => vme_anx <= va0b; ad_co <= b"11"; aph_sta <= x"5"; - when va0b => ad_co <= b"10"; aph_sta <= x"6"; - if asis ='1' then vme_anx <= va0b; - else vme_anx <= va00; - end if; - end case; - end process; --- ............................ clock for address phase state machine ................................ - process(ck50) begin -- 50 MHz clock - if (ck50'EVENT AND ck50 = '1') then - vme_adr <= vme_anx; - end if; - end process ; --- .............................. synchronize outputs .................................. - process(ck50) begin - if (ck50'EVENT AND ck50 = '1') then - stda <= ad_co(1); -- start data phase (low=address phase - high =data phase) - ckad <= ad_co(0); -- ckad = clock for internal address register - end if; - end process ; -----................... end of VME address phase state machine ................... --- ----................... save VME address into FPGA internal address register ................... - process(ck50, ckad) - begin - if (ck50'EVENT AND ck50 = '1') then - if ckad = '1' then - ad_reg <= ad; wrs <= wri; amr <= ami; - end if; - end if; - end process; - int_res <= ad_reg(23 downto 22); -- internal resources ---.................. select SAM4 module = compare address register with hex switch ............... - --- process(ck50)--, ad, mon) --- begin --- if (ck50'EVENT AND ck50 = '1') then --- if (ad_reg(31 downto 24) = mon) then -- VN2 31...28, VN1 27...24 --*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ --- vulom_sel <= '1'; --- else vulom_sel <= '0'; --- end if; --- end if; --- end process; ---.................. compare address register and address modifier ............................. - process(ck50, ad_reg, amr) - begin - if (ck50'event and ck50 ='1') then - if ((ad_reg(1 downto 0) = b"00") and (con(7) = '1')) then --(amr = am_9 or amr = am_d) and vulom_sel = '1' then - sel_rnd <= '1'; -- CSR random access - else sel_rnd <= '0'; - end if; - if ((ad_reg(1 downto 0) = b"00") and (con(8) = '1')) then --(amr = am_b) and vulom_sel = '1' then - sel_bt32 <= '1'; -- BT 32 bit access - else sel_bt32 <= '0'; - end if; - end if; - end process; --- * CSR0 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ DATA PHASE for CSR @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ---................................ comparator for CSR ....................................... - process(ck50, dsr, stda, wrs, int_res, sel_rnd) - begin - if (ck50'event and ck50 ='1') then - if (dsr='1' and stda='1' and wrs='1' and int_res=csr_ad and sel_rnd='1') then st_csr_drd <= '1'; -- CSR sta-ma - else st_csr_drd <= '0'; - end if; - if (dsr='1' and stda='1' and wrs='0' and int_res=csr_ad and sel_rnd='1') then st_csr_dwr <= '1'; -- CSR sta-ma - else st_csr_dwr <= '0'; - end if; - if (int_res=csr_ad and sel_rnd='1') then selcsr <= '1'; -- CSR selected - else selcsr <= '0'; - end if; - end if; - end process; --- csr_o[]=ckcsr,oecsr, vdcsr[]=odvi,cdvi,odiv,cdiv - process (vmdacs, dsr, st_csr_dwr, st_csr_drd) -- states are - vc00,vc01,vc02,vc03,vc04,vc05,vc06,vc07,vc08 - begin --- csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; - case vmdacs is - when vc00 => csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"0"; - if st_csr_drd ='1' then vmdacs_nx <= vc01; - elsif st_csr_dwr ='1' then vmdacs_nx <= vc08; - else - vmdacs_nx <= vc00; - end if; --- ---............................. read csr ................................ - when vc01 => vmdacs_nx <= vc02; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"1"; - when vc02 => vmdacs_nx <= vc03; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"2"; - when vc03 => vmdacs_nx <= vc04; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"3"; - when vc04 => vmdacs_nx <= vc05; csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='1'; dph_sta <= x"4"; - when vc05 => vmdacs_nx <= vc06; csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='1'; dph_sta <= x"5"; - when vc06 => csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='0'; dph_sta <= x"6"; - if dsr ='1' then vmdacs_nx <= vc06; - else vmdacs_nx <= vc07; - end if; - when vc07 => vmdacs_nx <= vc00; csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"7"; ---............................. write csr ................................ - when vc08 => vmdacs_nx <= vc09; csr_o <= b"10"; vdcsr <= b"0011"; ack_csr <='1'; dph_sta <= x"8"; - when vc09 => vmdacs_nx <= vc0a; csr_o <= b"10"; vdcsr <= b"0011"; ack_csr <='1'; dph_sta <= x"9"; - when vc0a => vmdacs_nx <= vc0b; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"a"; - when vc0b => vmdacs_nx <= vc0c; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"b"; - when vc0c => vmdacs_nx <= vc0d; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"c"; - when vc0d => csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='0'; dph_sta <= x"d"; - if dsr ='1' then vmdacs_nx <= vc0d; - else vmdacs_nx <= vc0e; - end if; - when vc0e => vmdacs_nx <= vc00; csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"e"; - end case; - end process; --- ............................ clock for vmedacs state machine ................................ - process(ck50) begin - if (ck50'EVENT AND ck50 = '1') then - vmdacs <= vmdacs_nx; - end if; - end process ; --- .............................. synchronize outputs .................................. - process(ck50) begin - if (ck50'EVENT AND ck50 = '1') then --- csr_o = ckcsr,oecsr, - ckcsr <= csr_o(1); -- clock data into csr - oecsr <= csr_o(0); -- output data from csr to VME - end if; - end process ; ---------------------------- VME control signals ------------------------------- --- vdbuf = odvi,cdvi,odiv,cdiv - process(ck50,vdcsr,ack_csr,ack_hpi) - begin - if (ck50'event and ck50 ='1') then - if (selcsr='1') then - con(4) <= vdcsr(3); -- odvi = OE for data register VME->internal - con(3) <= vdcsr(2); -- cdvi = clock for data register VME->internal - con(2) <= vdcsr(1); -- odiv = OE for data register internal->VME - con(1) <= vdcsr(0); -- cdiv = clock for data register internal->VME - con(0) <= ack_csr; -- acknowledge from csr - else - con(4) <= '1'; con(3) <= '1'; con(2) <= '1'; con(1) <= '1'; con(0) <= '1'; -- inactive - end if; - end if; - end process; ----------------------------------------------------------------------------------- --- hplb <= (others =>'0'); - hplb(0) <= asis; - hplb(1) <= ckad; - hplb(2) <= st_csr_drd; - hplb(3) <= st_csr_dwr; - hplb(6 downto 4) <= aph_sta(2 downto 0); - hplb(7) <= ack_csr; - hplb(11 downto 8) <= vdcsr; - hplb(15 downto 12) <= dph_sta; - -end RTL; \ No newline at end of file diff --git a/optical_link/compile_hub.pl b/optical_link/compile_hub.pl deleted file mode 100755 index d282c54..0000000 --- a/optical_link/compile_hub.pl +++ /dev/null @@ -1,189 +0,0 @@ -#!/usr/bin/perl -########################################### -# Script file to run the flow -# -########################################### -# -# Command line for synplify_pro -# - - -use FileHandle; - - -use Data::Dumper; - -use warnings; -use strict; - - -$ENV{LM_LICENSE_FILE}="1710\@cronos.e12.physik.tu-muenchen.de"; - -my $synplify_path = '/opt/Synplicity/syn_96L2/synplify_linux/bin/'; - -$ENV{'SYNPLIFY'}="/opt/Synplicity/syn_96L2/synplify_linux/"; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; - - -my $base = "/opt/lattice/ispLEVER7.2/isptools"; - -my $FAMILYNAME="LatticeSCM"; -my $PLD_DEVICE="LFSCM3GA25EP1"; -my $PACKAGE="FFBGA1020"; - -my $TOPNAME="hub"; - -my $t=time; - -my $fh = new FileHandle(">version.vhd"); - -die "could not open file" if (! defined $fh); - -print $fh <close; - - -#set -e -#set -o errexit - -system("env| grep LM_"); -#$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; -#$c="/opt/Synplicity/syn_96L2/synplify_linux/bin/synpwrap_pro.sh -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; -#execute($c); -#$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; -#$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj"); -#$r=execute($c, "do_not_exit" ); - -my $c="$synplify_path/synpwrap -Pro -prj $TOPNAME"."_syn.prj"; -my $r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME.srr"); -my @a = <$fh>; -$fh -> close; - -#if ($r) { -#$c="cat $TOPNAME.srr"; -#system($c); -#exit 129; -#} - -foreach (@a) -{ - if( /\@E:/ || /\@E\|/ ) - { - $c="cat $TOPNAME.srr"; - system($c); - print "bdabdhsadbhjasdhasldhbas"; - exit 129; - } -} -#if (0){ - -#$c=("/opt/lattice/isplever7.0/isptools/ispcpld/bin/checkini -err=automake.err /opt/lattice/isplever7.0/isptools/ispcpld/config/or5s00.ini"); - - -#$c=("/opt/lattice/isplever7.0/isptools/ispcpld/bin/edfin -i hub.edf -jhd hub.jhd -log hub.log -dev orca -lbp \"/opt/lattice/isplever7.0/isptools/ispfpga/data\""); - -#$c=("/opt/lattice/isplever7.0//ispfpga/bin/lin/lci2prf -oc hub.lct -log hub.log ../hub.lpf"); - -#$c=("export FOUNDRY=\"/opt/lattice/isplever7.0//ispfpga\""); - -#$c=("export LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH:/opt/lattice/isplever7.0//ispfpga/bin/lin\""); - -$c= qq|$base/ispfpga/bin/lin/edif2ngd -l "$FAMILYNAME" -d "$PLD_DEVICE" "$TOPNAME.edf" "$TOPNAME.ngo"|; -execute($c); - -$c=qq|$base/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$base/ispfpga/bin/lin/ngdbuild -a "$FAMILYNAME" -d "$PLD_DEVICE" -p "$base/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$base/ispfpga/bin/lin/map -a "$FAMILYNAME" -p "$PLD_DEVICE" -t "$PACKAGE" -s 5 "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); -#execute($c); - -$c=qq|$base/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "$TOPNAME| . "_mpar.rpt" . qq|" -log "$TOPNAME| . "_mpar.log" . qq|" -p "$TOPNAME.p2t" -f "$TOPNAME.p3t" "$tpmap.ncd" "$TOPNAME.ncd"|; -execute($c); - - -# TWR Timing Report -#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|; -$c=qq|$base/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); -$c=qq|$base/ispfpga/bin/lin/trce -c -v 5 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - - - -$c=("$base/ispfpga/bin/lin/bitgen -w \"hub.ncd\" -f \"hub.t2b\" \"hub.prf\""); -execute($c); -#$c=(". ~/bin/ispvm17"); -#execute($c); - -$c=q| perl -ne '$in=1 if(/Report Summary/); print if($in==1); $in=0 if(/All preferences were met./)' | . "$TOPNAME.twr.setup"; -execute($c); - -chdir ".."; - -$c=("cat version.vhd | grep VERSION_NUMBER_TIME"); -execute($c); - -$c=q!cat version.vhd | perl -ne '($r)=grep(/VERSION_NUMBER_TIME/, $_); if($r) {($n)=$r=~/(\d+);/; printf("%x\n",$n);} '!; -execute($c); - - -#$c=(". ~/bin/ispvm17"); - -#$c=("ispvm -infile hub_1.xcf -outfiletype -stp"); -#execute($c); - -#$c=("perl -i -ne 'print unless(/!/)' hub_1.svf"); -#execute($c); -#$c=("impact -batch impact_batch_hub.txt"); -#execute($c); -#$c=("scp hub_chain.stapl hadaq\@hadeb05:/var/diskless/etrax_fs/"); -#execute($c); - -#} -#$c=("impact -batch impact_batch_hub.txt"); - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/optical_link/f_divider.vhd b/optical_link/f_divider.vhd deleted file mode 100644 index 50133b9..0000000 --- a/optical_link/f_divider.vhd +++ /dev/null @@ -1,174 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_arith.all; -use IEEE.STD_LOGIC_unsigned.all; - - -entity f_divider is - - generic( - cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. -- - ); - - port ( - clk : in std_logic; - ena_cnt : in std_logic; - f_div : out std_logic - ); - -end f_divider; - - - -architecture arch_f_divider of f_divider is - - function How_many_Bits (int : integer) return integer is - variable i, tmp : integer; - begin - tmp := int; - i := 0; - while tmp > 0 loop - tmp := tmp / 2; - i := i + 1; - end loop; - return i; - end How_many_bits; - - - --+ - --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? | - --+ - constant c_counter_width : integer := How_many_Bits(cnt - 2); - - --+ ---------------------------------------------------------------------------------------------+ - --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" | - --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne | - --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. | - --+ ---------------------------------------------------------------------------------------------+ - signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1); - - --+ ---------------------------------------------------------------------------------------------+ - --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem | - --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. | - --+ ---------------------------------------------------------------------------------------------+ - constant c_ld_value : integer := cnt - 2; - -begin - p_f_divider : process (clk) - begin - if clk'event and clk = '1' then - if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen -- - s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length); - elsif ena_cnt = '1' then - if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter -- - s_counter <= s_counter - 1; -- subtrahieren. -- - end if; - end if; - end if; - end process p_f_divider; - - f_div <= s_counter(s_counter'high); - -end arch_f_divider; - - - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; - - ---library synplify; ---use synplify.attributes.all; - - -entity edge_to_pulse is - - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - -end edge_to_pulse; - -architecture arch_edge_to_pulse of edge_to_pulse is - signal signal_sync : std_logic; - signal old_sync : std_logic; - type state is (idle, high, wait_for_low); -- state - signal current_state, next_state : state; - -begin -- arch_edge_to_pulse - - fsm : process (clock) - begin -- process fsm - if rising_edge(clock) then -- rising clock edge - if en_clk = '1' then - current_state <= next_state; - signal_sync <= signal_in; - end if; - end if; - end process fsm; - - - fsm_comb : process (current_state, signal_sync) - begin -- process fsm_comb - pulse <= '0'; - case current_state is - when idle => - pulse <= '0'; - if signal_sync = '1' then - next_state <= high; - else - next_state <= idle; - end if; - when high => - pulse <= '1'; - next_state <= wait_for_low; --- when wait_for_low_1 => --- pulse <= '1'; --- next_state <= wait_for_low; - when wait_for_low => - pulse <= '0'; - if signal_sync = '0' then - next_state <= idle; - else - next_state <= wait_for_low; - end if; - when others => - next_state <= idle; - end case; - end process fsm_comb; - - -end arch_edge_to_pulse; - - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package support is - - component f_divider - generic ( - cnt : integer); - port ( - clk : in std_logic; - ena_cnt : in std_logic; - f_div : out std_logic); - end component; - - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - - -end support; - diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd deleted file mode 100644 index 9df7a23..0000000 --- a/optical_link/flexi_PCS_channel_synch.vhd +++ /dev/null @@ -1,876 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; -use work.trb_net_std.all; -use work.trb_net16_hub_func.all; - -entity flexi_PCS_channel_synch is - generic ( - SYSTEM : positive); - port ( - RESET : in std_logic; - SYSTEM_CLK : in std_logic; - --to and from media - TX_CLK : in std_logic; - RX_CLK : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : out std_logic_vector(15 downto 0); - TX_K : out std_logic_vector(1 downto 0); - MEDIA_STATUS : in std_logic_vector(15 downto 0); - MEDIA_CONTROL : out std_logic_vector(15 downto 0); - --to and from trbnet - --to media - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector(15 downto 0); - MED_READ_OUT : out std_logic; - --from media - MED_DATA_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - --trbnet control and status - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_STAT_OP : out std_logic_vector(15 downto 0); - MED_CTRL_OP : in std_logic_vector(15 downto 0); --debug - LINK_DEBUG : out std_logic_vector(31 downto 0) - ); -end flexi_PCS_channel_synch; - -architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is - - component flexi_PCS_fifo_EBR - port ( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(17 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic - ); - end component; - - component ecp2m_link_fifo - port ( - Data : in std_logic_vector(17 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(17 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic - ); - end component; - --keep fifos as small as possible, remember but low prioriority - --disable transmition during synch - component up_down_counter - generic ( - NUMBER_OF_BITS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic; - DOWN_IN : in std_logic); - end component; - - component edge_to_pulse - port ( - CLOCK : in std_logic; - EN_CLK : in std_logic; - SIGNAL_IN : in std_logic; - PULSE : out std_logic); - end component; - - component cross_clk - port ( - WrAddress : in std_logic_vector(2 downto 0); - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - WE : in std_logic; - WrClockEn : in std_logic; - RdAddress : in std_logic_vector(2 downto 0); - RdClock : in std_logic; - RdClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(31 downto 0)); - end component; - - component trbv2_cross_clk - port ( - addra : in std_logic_vector(2 downto 0); - addrb : in std_logic_vector(2 downto 0); - clka : in std_logic; - clkb : in std_logic; - dina : in std_logic_vector(31 downto 0); - dinb : in std_logic_vector(31 downto 0); - douta : out std_logic_vector(31 downto 0); - doutb : out std_logic_vector(31 downto 0); - wea : in std_logic; - web : in std_logic); - end component; - - component trbv2_link_fifo - port ( - din : IN std_logic_VECTOR(17 downto 0); - rd_clk : IN std_logic; - rd_en : IN std_logic; - rst : IN std_logic; - wr_clk : IN std_logic; - wr_en : IN std_logic; - almost_empty : OUT std_logic; - almost_full : OUT std_logic; - dout : OUT std_logic_VECTOR(17 downto 0); - empty : OUT std_logic; - full : OUT std_logic); - end component; - - type SYNC_MACHINE is (FIRST_DUMMY_STATE, START_COUNTER, RESYNC0, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, WAIT_3, NORMAL_OPERATION_1, NORMAL_OPERATION_2); - signal SYNC_CURRENT, SYNC_NEXT : SYNC_MACHINE; --- attribute syn_enum_encoding : string; --- attribute syn_enum_encoding of SYNC_MACHINE : type is "safe"; --- attribute syn_enum_encoding of SYNC_MACHINE : type is "sequential"; - - signal fsm_debug_register : std_logic_vector(3 downto 0); - signal resync_counter_up :std_logic; - signal resync_counter_clr :std_logic; - signal resync_counter : std_logic_vector(31 downto 0); - signal cv_i : std_logic_vector(1 downto 0); - signal cv_or : std_logic; - signal cv_counter : std_logic_vector(15 downto 0); - signal rx_rst_i : std_logic; - signal rxd_synch_i : std_logic_vector(15 downto 0); - signal rxd_synch_synch_i : std_logic_vector(15 downto 0); - signal rx_k_synch_i : std_logic_vector(1 downto 0); - signal rx_k_synch_synch_i : std_logic_vector(1 downto 0); - signal fifo_data_in : std_logic_vector(17 downto 0); - signal fifo_data_out : std_logic_vector(17 downto 0); - signal fifo_wr_en : std_logic; - signal fifo_rd_en : std_logic; - signal fifo_rst : std_logic; - signal fifo_full : std_logic; - signal fifo_almost_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal start_counter_1 : std_logic_vector(31 downto 0); - signal start_counter_2 : std_logic_vector(31 downto 0); - signal fifo_rd_pulse : std_logic; - signal fifo_rd_cnt : std_logic_vector(15 downto 0); - signal fifo_wr_cnt : std_logic_vector(15 downto 0); - signal not_fifo_empty : std_logic; - - ----------------------------------------------------------------------------- - -- fifo to optical link - ----------------------------------------------------------------------------- - signal data_valid_out_i : std_logic; - signal fifo_opt_not_empty : std_logic; - signal fifo_opt_empty : std_logic; - signal fifo_opt_empty_synch : std_logic; - signal data_opt_in : std_logic_vector(17 downto 0); - signal txd_fifo_out : std_logic_vector(17 downto 0); - signal fifo_opt_full : std_logic; - signal fifo_opt_almost_empty : std_logic; - signal fifo_opt_almost_full : std_logic; - signal not_clk : std_logic; - signal txd_synch_i : std_logic_vector(15 downto 0); - signal tx_k_i : std_logic; - signal fifo_opt_empty_synch_synch : std_logic; - signal fifo_rd_en_hub : std_logic; --- constant SYSTEM : Integer := 1; - signal wait_for_write_up : std_logic; - signal wait_for_write_counter : std_logic_vector(28 downto 0); - signal link_reset_counter : std_logic_vector(2 downto 0); - signal link_reset_counter_clr : std_logic; - signal link_reset_counter_up : std_logic; - signal link_reset_out : std_logic; - signal med_error_out_i : std_logic_vector(2 downto 0); - signal fifo_rst_fsm : std_logic; - signal fsm_debug_register_fsm: std_logic_vector(3 downto 0); - signal rx_rst_fsm : std_logic; - signal resync_counter_up_fsm : std_logic; - signal resync_counter_clr_fsm : std_logic; - signal wait_for_write_up_fsm : std_logic; - signal MED_READ_OUT_fsm : std_logic; - signal diod_counter : std_logic_vector(28 downto 0); - signal cv_counter_reset : std_logic; - signal rx_comma : std_logic_vector(1 downto 0); - signal rx_comma_synch : std_logic_vector(1 downto 0); - - --crossing clk memory - signal cross_wraddress_i : std_logic_vector(2 downto 0); - signal cross_data_i : std_logic_vector(31 downto 0); - signal cross_rdaddress_i : std_logic_vector(2 downto 0); - signal cross_q_i : std_logic_vector(31 downto 0); - signal rx_comma_synch_err : std_logic; - signal lost_connection_count : std_logic_vector(15 downto 0); - -begin - - --reset from link - RESET_FROM_LINK: process (RX_CLK, RESET) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - link_reset_counter_up <= '0'; - elsif rxd_synch_i = x"ffff" and link_reset_counter < 5 then - link_reset_counter_up <= '1'; - else - link_reset_counter_up <= '0'; - end if; - end if; - end process RESET_FROM_LINK; - - SET_RESET: process (SYSTEM_CLK, RESET) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - link_reset_out <= '0'; - elsif link_reset_counter = 5 then - link_reset_out <= '1'; - else - link_reset_out <= '0'; - end if; - end if; - end process SET_RESET; - - RESET_LINK_ERROR_COUNTER: process (RX_CLK, RESET) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - link_reset_counter_clr <= '0'; - elsif link_reset_counter = 3 then - link_reset_counter_clr <= link_reset_out or RESET; - elsif link_reset_counter < 3 and rxd_synch_i /= x"ffff" then - link_reset_counter_clr <= '1'; - else - link_reset_counter_clr <= '0'; - end if; - end if; - end process RESET_LINK_ERROR_COUNTER; - - LINK_RESET_COUNTER_INST: up_down_counter - generic map ( - NUMBER_OF_BITS => 3) - port map ( - CLK => RX_CLK, - RESET => link_reset_counter_clr, - COUNT_OUT => link_reset_counter, - UP_IN => link_reset_counter_up, - DOWN_IN => '0'); - - -- STAT_OP(15) <= link_reset_out; - --link - - MED_STAT_OP(2 downto 0) <= med_error_out_i; - SEND_ERROR: process (SYSTEM_CLK, RESET,SYNC_CURRENT) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - med_error_out_i <= ERROR_NC; - elsif SYNC_CURRENT = NORMAL_OPERATION_1 or SYNC_CURRENT = NORMAL_OPERATION_2 then - med_error_out_i <= ERROR_OK; - elsif SYNC_CURRENT = WAIT_1 or SYNC_CURRENT = WAIT_2 then - med_error_out_i <= ERROR_WAIT; - else - med_error_out_i <= ERROR_NC; - end if; - end if; - end process SEND_ERROR; - MED_STAT_OP(15 downto 10) <= (others => '0'); - MED_STAT_OP(8 downto 3) <= (others => '0'); - - PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - packet_number <= "011"; - elsif fifo_rd_en = '1' then - if packet_number = c_max_word_number then - packet_number <= "000"; - else - packet_number <= packet_number + 1; - end if; - end if; - end if; - end process PACKET_NUM; - MED_PACKET_NUM_OUT <= packet_number; - - LINK_STATUS : process (SYSTEM_CLK,RESET) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - RX_RST <= '0'; - LINK_DEBUG(15 downto 0) <= (others => '0'); - else - RX_RST <= rx_rst_i; - LINK_DEBUG(3 downto 0) <= fsm_debug_register_fsm; - LINK_DEBUG(7 downto 4) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full;--fifo_almost_full & - --'0'; - LINK_DEBUG(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); -- LINK_DEBUG(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); - LINK_DEBUG(31 downto 16) <= fifo_data_out(3 downto 0) & lost_connection_count(7 downto 0) & '0' & rx_comma_synch & MEDIA_STATUS(0) ; - end if; - end if; - end process LINK_STATUS; - -- LINK_DEBUG(31 downto 16) <= fifo_data_in(15 downto 0); - - ----------------------------------------------------------------------------- - -- data from hub to link - ----------------------------------------------------------------------------- - - - CROSS_WR_ADDRESS: process (RX_CLK, RESET) - begin - if rising_edge (RX_CLK) then - if RESET = '1' then - cross_wraddress_i <= "000"; - else - cross_wraddress_i <= cross_wraddress_i + 1; - end if; - end if; - end process CROSS_WR_ADDRESS; - - CROSS_RD_ADDRESS: process (SYSTEM_CLK, RESET) - begin - if rising_edge (SYSTEM_CLK) then - if RESET = '1' then - cross_rdaddress_i <= "000"; - else - cross_rdaddress_i <= cross_rdaddress_i + 1; - end if; - end if; - end process CROSS_RD_ADDRESS; - - cross_data_i <= x"0000000" & "00" & rx_comma; - - data_opt_in <= "00" & MED_DATA_IN; - - SYSTEM_SCM_MEMa: if SYSTEM=1 generate - CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR - port map ( - Data => data_opt_in, - WrClock => SYSTEM_CLK, - RdClock => TX_CLK, - WrEn => MED_DATAREADY_IN, - RdEn => fifo_opt_not_empty, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => txd_fifo_out, - Empty => fifo_opt_empty, - Full => fifo_opt_full, - AlmostEmpty => fifo_opt_almost_empty, - AlmostFull => fifo_opt_almost_full - ); - - CROSS_CLK_DPMEM: cross_clk - port map ( - WrAddress => cross_wraddress_i, - Data => cross_data_i, - WrClock => RX_CLK, - WE => '1', - WrClockEn => '1', - RdAddress => cross_rdaddress_i, - RdClock => SYSTEM_CLK, - RdClockEn => '1', - Reset => Reset, - Q => cross_q_i); - - end generate SYSTEM_SCM_MEMa; - - SYSTEM_ECP2_MEMa: if SYSTEM=2 generate - CHANNEL_FIFO_TO_OPT: ecp2m_link_fifo - port map ( - Data => data_opt_in, - WrClock => SYSTEM_CLK, - RdClock => TX_CLK, - WrEn => MED_DATAREADY_IN, - RdEn => fifo_opt_not_empty, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => txd_fifo_out, - Empty => fifo_opt_empty, - Full => fifo_opt_full, - AlmostEmpty => fifo_opt_almost_empty, - AlmostFull => fifo_opt_almost_full - ); - end generate SYSTEM_ECP2_MEMa; - - SYSTEMT_TRBv2_MEMa: if SYSTEM=6 generate - - CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo - port map ( - din => data_opt_in, - rd_clk => TX_CLK, - rd_en => fifo_opt_not_empty, - rst => fifo_rst, - wr_clk => SYSTEM_CLK, - wr_en => MED_DATAREADY_IN, - almost_empty => fifo_opt_almost_empty, - almost_full => fifo_opt_almost_full, - dout => txd_fifo_out, - empty => fifo_opt_empty, - full => fifo_opt_full); - - TRBv2_CROSS_CLK_INST: trbv2_cross_clk - port map ( - addra => cross_wraddress_i, - addrb => cross_rdaddress_i, - clka => RX_CLK, - clkb => SYSTEM_CLK, - dina => cross_data_i, - dinb => x"00000000", - douta => open, - doutb => cross_q_i, - wea => '1', - web => '0'); - - end generate SYSTEMT_TRBv2_MEMa; - - DATA_SEND_TO_LINK: process (TX_CLK, RESET, MED_DATAREADY_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch) - begin - if rising_edge(TX_CLK) then - if RESET = '1' then - tx_k_i <= '0'; - txd_synch_i <= (others => '0'); - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then - tx_k_i <= '0'; - txd_synch_i <= txd_fifo_out(15 downto 0); - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - else - tx_k_i <= '1'; - txd_synch_i <= x"c5bc"; - fifo_opt_empty_synch <= fifo_opt_empty; - fifo_opt_empty_synch_synch <= fifo_opt_empty_synch; - fifo_opt_not_empty <= not fifo_opt_empty; - end if; - end if; - end process DATA_SEND_TO_LINK; - - SYNC_DATA : process (TX_CLK) - begin - if rising_edge(TX_CLK) then - TXD <= txd_synch_i; - TX_K(0) <= tx_k_i; - TX_K(1) <= '0'; - end if; - end process SYNC_DATA; - - ----------------------------------------------------------------------------- - -- from link to hub - ----------------------------------------------------------------------------- - SYSTEM_SCM_MEMb: if SYSTEM=1 generate - CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR - port map ( - Data => fifo_data_in, - WrClock => RX_CLK, - RdClock => SYSTEM_CLK, - WrEn => fifo_wr_en, - RdEn => fifo_rd_en, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => fifo_data_out, - Empty => fifo_empty, - Full => fifo_full, - AlmostEmpty => fifo_almost_empty, - AlmostFull => fifo_almost_full - ); - end generate SYSTEM_SCM_MEMb; - - SYSTEM_ECP2_MEMb: if SYSTEM=2 generate - CHANNEL_FIFO_TO_FPGA: ecp2m_link_fifo - port map ( - Data => fifo_data_in, - WrClock => RX_CLK, - RdClock => SYSTEM_CLK, - WrEn => fifo_wr_en, - RdEn => fifo_rd_en, - Reset => fifo_rst, - RPReset => fifo_rst, - Q => fifo_data_out, - Empty => fifo_empty, - Full => fifo_full, - AlmostEmpty => fifo_almost_empty, - AlmostFull => fifo_almost_full - ); - end generate SYSTEM_ECP2_MEMb; - - SYSTEM_TRBv2: if SYSTEM=6 generate - - CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo - port map ( - din => fifo_data_in, - rd_clk => SYSTEM_CLK, - rd_en => fifo_rd_en, - rst => fifo_rst, - wr_clk => RX_CLK, - wr_en => fifo_wr_en, - almost_empty => fifo_almost_empty, - almost_full => fifo_almost_full, - dout => fifo_data_out, - empty => fifo_empty, - full => fifo_full); - - end generate SYSTEM_TRBv2; - - not_fifo_empty <= not fifo_empty; - RD_FIFO_PULSE: edge_to_pulse - port map ( - clock => SYSTEM_CLK, - en_clk => '1', - signal_in => not_fifo_empty, - pulse => fifo_rd_pulse); - - READING_THE_FIFO: process (SYSTEM_CLK, RESET, fifo_rd_pulse,MED_READ_IN,fifo_empty,data_valid_out_i) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - data_valid_out_i <= '0'; - fifo_rd_en_hub <= '0'; - elsif fifo_rd_pulse = '1' then - data_valid_out_i <= '1'; - fifo_rd_en_hub <= MED_READ_IN; - elsif MED_READ_IN = '1' and fifo_empty = '1' and data_valid_out_i = '1' then - data_valid_out_i <= '0'; - fifo_rd_en_hub <= '0'; - elsif data_valid_out_i = '1' and fifo_empty = '0' then - data_valid_out_i <= '1'; - fifo_rd_en_hub <= MED_READ_IN; - end if; - end if; - end process READING_THE_FIFO; - - MED_DATAREADY_OUT <= data_valid_out_i; - fifo_rd_en <= (fifo_rd_en_hub and (not fifo_empty)) or fifo_rd_pulse; - MED_DATA_OUT <= fifo_data_out(15 downto 0); - - VALID_DATA_SEND_TO_API: process (RX_CLK, RESET) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - rxd_synch_i <= (others => '0'); - rxd_synch_synch_i <= rxd_synch_i; - rx_k_synch_i <= "00"; - rx_k_synch_synch_i <= rx_k_synch_i; - else - rxd_synch_i <= RXD; - rxd_synch_synch_i <= rxd_synch_i; - rx_k_synch_i <= RX_K; - rx_k_synch_synch_i <= rx_k_synch_i; - end if; - end if; - end process VALID_DATA_SEND_TO_API; - - - - SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNC_CURRENT) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - fifo_data_in <= (others => '0'); - elsif SYNC_CURRENT = NORMAL_OPERATION_2 and CV="00" then - fifo_data_in <= '0' & (not RX_K(0)) & RXD; - fifo_wr_en <= not RX_K(0); - elsif SYNC_CURRENT = NORMAL_OPERATION_1 and CV="00" then - fifo_data_in <= '0' & (not RX_K(1)) & RXD(7 downto 0) & rxd_synch_i(15 downto 8); - fifo_wr_en <= not rx_k_synch_i(1); - else - fifo_data_in <= (others => '0'); - fifo_wr_en <= '0'; - end if; - end if; - end process SHIFT_OR_NOT_DATA_IN; - - SAVE_COMA: process (RX_CLK, RESET) - begin - if rising_edge(RX_CLK) then - if RESET = '1' then - rx_comma <= "00"; - elsif (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' and cv_i = "00" then - rx_comma <= "01"; - elsif (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' and cv_i = "00" then - rx_comma <= "10"; - elsif cv_i /= "00" then - rx_comma <= "11"; - else - rx_comma <= "00"; - end if; - end if; - end process SAVE_COMA; - - - SYNC_CLOCK : process (SYSTEM_CLK, RESET) - begin - if rising_edge (SYSTEM_CLK) then - if RESET = '1' then - SYNC_CURRENT <= FIRST_DUMMY_STATE;--no_sim -- ---sim-- SYNC_CURRENT <= NORMAL_OPERATION_2; - cv_i <= (others => '0'); - fifo_rst <= '1'; - fsm_debug_register <= "1111"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '1'; - wait_for_write_up <= '0'; - MED_READ_OUT <= '0'; - rx_comma_synch <= "00"; - else - SYNC_CURRENT <= SYNC_NEXT; - cv_i <= CV; - fifo_rst <= fifo_rst_fsm; - fsm_debug_register <= fsm_debug_register_fsm; - rx_rst_i <= rx_rst_fsm; - resync_counter_up <= resync_counter_up_fsm; - resync_counter_clr <= resync_counter_clr_fsm; - wait_for_write_up <= wait_for_write_up_fsm; - MED_READ_OUT <= MED_READ_OUT_fsm; - rx_comma_synch <= cross_q_i(1 downto 0); - end if; - end if; - end process SYNC_CLOCK; - - SYNC_FSM : process(SYNC_CURRENT) - begin - fifo_rst_fsm <= '0'; - fsm_debug_register_fsm <= "1111"; - rx_rst_fsm <= '0'; - resync_counter_up_fsm <= '1'; - resync_counter_clr_fsm <= '0'; - wait_for_write_up_fsm <= '0'; - MED_READ_OUT_fsm <= '0'; - SYNC_NEXT <= RESYNC0; - - case (SYNC_CURRENT) is - --check the sfp, pll lock and so on - -- all counters are are only reset in state START_COUNTER - - when FIRST_DUMMY_STATE => - resync_counter_up_fsm <= '0'; - fsm_debug_register_fsm <= "0001"; - SYNC_NEXT <= START_COUNTER; - - when START_COUNTER => - fsm_debug_register_fsm <= "0010"; - resync_counter_up_fsm <= '0'; - resync_counter_clr_fsm <= '1'; - fifo_rst_fsm <= '1'; - SYNC_NEXT <= RESYNC0; - - when RESYNC0 => - fsm_debug_register_fsm <= "0011"; - resync_counter_up_fsm <= '0'; - if MEDIA_STATUS(0) = '1' then - SYNC_NEXT <= START_COUNTER; - elsif rx_comma_synch = "01" or rx_comma_synch = "10" then - SYNC_NEXT <= WAIT_1; - else - SYNC_NEXT <= RESYNC1; - end if; - --SYNC_NEXT <= RESYNC1; - - when RESYNC1 => - fsm_debug_register_fsm <= "0100"; - rx_rst_fsm <= '1'; - if resync_counter(9) = '1' then - SYNC_NEXT <= RESYNC2; - else - SYNC_NEXT <= RESYNC1; - end if; - - when RESYNC2 => -- just waiting - fsm_debug_register_fsm <= "0101"; - if resync_counter(18) = '1' then --at least 400us - SYNC_NEXT <= RESYNC3; - else - SYNC_NEXT <= RESYNC2; - end if; - - when RESYNC3 => -- check for comma - fsm_debug_register_fsm <= "0110"; - if rx_comma_synch = "01" or rx_comma_synch = "10" then - SYNC_NEXT <= WAIT_2;--no_sim-- ---sim-- SYNC_NEXT <= NORMAL_OPERATION_2; - else - SYNC_NEXT <= START_COUNTER; - end if; - - when WAIT_1 => -- wait for comma - fsm_debug_register_fsm <= "0111"; - if resync_counter(28) = '1' then - SYNC_NEXT <= WAIT_3; - elsif resync_counter(27) = '1' and (rx_comma_synch = "00" or rx_comma_synch = "11") then - SYNC_NEXT <= START_COUNTER; - else - SYNC_NEXT <= WAIT_1; - end if; - - when WAIT_3 => - fsm_debug_register_fsm <= "1001"; - wait_for_write_up_fsm <= '1'; - if wait_for_write_counter(28)='1' and rx_comma_synch = "01" then - SYNC_NEXT <= NORMAL_OPERATION_2; - elsif wait_for_write_counter(28)='1' and rx_comma_synch = "10" then - SYNC_NEXT <= NORMAL_OPERATION_1; - elsif rx_comma_synch = "11" then - SYNC_NEXT <= START_COUNTER; - else - SYNC_NEXT <= WAIT_3; - end if; - - when NORMAL_OPERATION_1 => ---sim-- fifo_rst <=RESET; - fsm_debug_register_fsm <= "1010"; - resync_counter_up_fsm <= '0'; - MED_READ_OUT_fsm <= '1'; - if rx_comma_synch = "11" then --- if MEDIA_STATUS(0) = '1' then - - SYNC_NEXT <= START_COUNTER; - else - SYNC_NEXT <= NORMAL_OPERATION_1; - end if; - - when NORMAL_OPERATION_2 => ---sim-- fifo_rst <=RESET; - fsm_debug_register_fsm <= "1011"; - resync_counter_up_fsm <= '0'; - MED_READ_OUT_fsm <= '1'; - if rx_comma_synch = "11" then --- if MEDIA_STATUS(0) = '1' then - SYNC_NEXT <= START_COUNTER; - else - SYNC_NEXT <= NORMAL_OPERATION_2; - end if; - - - when others => - fsm_debug_register_fsm <= "0000"; - SYNC_NEXT <= START_COUNTER; - - end case; - end process SYNC_FSM; - - LED_FOR_LINK: process (SYSTEM_CLK) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - MED_STAT_OP(9) <= '1'; - elsif fsm_debug_register < 9 and fsm_debug_register > 3 then - MED_STAT_OP(9) <= diod_counter(23); - elsif fsm_debug_register = 9 then - MED_STAT_OP(9) <= diod_counter(26); - elsif fsm_debug_register > 9 then - MED_STAT_OP(9) <= '0'; - else - MED_STAT_OP(9) <= '1'; - end if; - end if; - end process LED_FOR_LINK; - - DIOD_COUNTER_INST: up_down_counter - generic map ( - NUMBER_OF_BITS => 29) - port map ( - CLK => SYSTEM_CLK, - RESET => '0', - COUNT_OUT => diod_counter, - UP_IN => '1', - DOWN_IN => '0'); - - WAIT_FOR_SENDING: up_down_counter - generic map ( - NUMBER_OF_BITS => 29) - port map ( - CLK => SYSTEM_CLK, - RESET => resync_counter_clr, - COUNT_OUT => wait_for_write_counter, - UP_IN => wait_for_write_up, - DOWN_IN => '0'); - - RESYNC_COUNTER_INST: up_down_counter - generic map ( - NUMBER_OF_BITS => 32) - port map ( - CLK => SYSTEM_CLK, - RESET => resync_counter_clr, - COUNT_OUT => resync_counter, - UP_IN => resync_counter_up, - DOWN_IN => '0'); - - cv_or <= cv_i(0) or cv_i(1); - - CV_COUNTER_INST: up_down_counter - generic map ( - NUMBER_OF_BITS => 16) - port map ( - CLK => RX_CLK, - RESET => RESET, - COUNT_OUT => cv_counter, - UP_IN => cv_or, - DOWN_IN => '0'); - SYNCH_ERR_COUNT : process (SYSTEM_CLK, RESET) - begin - if rising_edge(SYSTEM_CLK) then - if RESET = '1' then - rx_comma_synch_err <= '0'; - elsif SYNC_CURRENT = NORMAL_OPERATION_1 or SYNC_CURRENT = NORMAL_OPERATION_2 then - rx_comma_synch_err <= rx_comma_synch(1) and rx_comma_synch(0); - else - rx_comma_synch_err <= '0'; - end if; - end if; - end process SYNCH_ERR_COUNT; - - LINK_CONECTION_LOST_COUNTER: up_down_counter - generic map ( - NUMBER_OF_BITS => 16) - port map ( - CLK => RX_CLK, - RESET => RESET, - COUNT_OUT => lost_connection_count, - UP_IN => rx_comma_synch_err, - DOWN_IN => '0'); - - WRITE_COUNTER: up_down_counter - generic map ( - NUMBER_OF_BITS => 16) - port map ( - CLK => SYSTEM_CLK, - RESET => RESET, - COUNT_OUT => fifo_wr_cnt, - UP_IN => fifo_wr_en, - DOWN_IN => '0'); - - READ_COUNTER: up_down_counter - generic map ( - NUMBER_OF_BITS => 16) - port map ( - CLK => SYSTEM_CLK, - RESET => RESET, - COUNT_OUT => fifo_rd_cnt, - UP_IN => MED_DATAREADY_IN, - DOWN_IN => '0'); - -end flexi_PCS_channel_synch; - diff --git a/optical_link/flexi_PCS_fifo_EBR.vhd b/optical_link/flexi_PCS_fifo_EBR.vhd deleted file mode 100644 index 5fbed36..0000000 --- a/optical_link/flexi_PCS_fifo_EBR.vhd +++ /dev/null @@ -1,180 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) --- Module Version: 4.2 ---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_EBR -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e - --- Tue Nov 27 10:58:36 2007 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library SCM; -use SCM.COMPONENTS.all; --- synopsys translate_on - -entity flexi_PCS_fifo_EBR is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end flexi_PCS_fifo_EBR; - -architecture Structure of flexi_PCS_fifo_EBR is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal Empty_int: std_logic; - signal Full_int: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component FIFO16KA - -- synopsys translate_off - generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); - FULLPOINTER : in std_logic_vector(14 downto 0); - AFPOINTER1 : in std_logic_vector(14 downto 0); - AEPOINTER1 : in std_logic_vector(14 downto 0); - AFPOINTER : in std_logic_vector(14 downto 0); - AEPOINTER : in std_logic_vector(14 downto 0); - CSDECODE_R : in std_logic_vector(1 downto 0); - CSDECODE_W : in std_logic_vector(1 downto 0); - RESETMODE : in String; REGMODE : in String; - DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; - DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; - DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; - DI12: in std_logic; DI13: in std_logic; - DI14: in std_logic; DI15: in std_logic; - DI16: in std_logic; DI17: in std_logic; - DI18: in std_logic; DI19: in std_logic; - DI20: in std_logic; DI21: in std_logic; - DI22: in std_logic; DI23: in std_logic; - DI24: in std_logic; DI25: in std_logic; - DI26: in std_logic; DI27: in std_logic; - DI28: in std_logic; DI29: in std_logic; - DI30: in std_logic; DI31: in std_logic; - DI32: in std_logic; DI33: in std_logic; - DI34: in std_logic; DI35: in std_logic; - FULLI: in std_logic; CSW0: in std_logic; - CSW1: in std_logic; EMPTYI: in std_logic; - CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic; - RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic; - RST: in std_logic; RPRST: in std_logic; - DO0: out std_logic; DO1: out std_logic; - DO2: out std_logic; DO3: out std_logic; - DO4: out std_logic; DO5: out std_logic; - DO6: out std_logic; DO7: out std_logic; - DO8: out std_logic; DO9: out std_logic; - DO10: out std_logic; DO11: out std_logic; - DO12: out std_logic; DO13: out std_logic; - DO14: out std_logic; DO15: out std_logic; - DO16: out std_logic; DO17: out std_logic; - DO18: out std_logic; DO19: out std_logic; - DO20: out std_logic; DO21: out std_logic; - DO22: out std_logic; DO23: out std_logic; - DO24: out std_logic; DO25: out std_logic; - DO26: out std_logic; DO27: out std_logic; - DO28: out std_logic; DO29: out std_logic; - DO30: out std_logic; DO31: out std_logic; - DO32: out std_logic; DO33: out std_logic; - DO34: out std_logic; DO35: out std_logic; - EF: out std_logic; AEF: out std_logic; AFF: out std_logic; - FF: out std_logic); - end component; - attribute FULLPOINTER1 : string; - attribute FULLPOINTER : string; - attribute AFPOINTER1 : string; - attribute AFPOINTER : string; - attribute AEPOINTER1 : string; - attribute AEPOINTER : string; - attribute RESETMODE : string; - attribute REGMODE : string; - attribute CSDECODE_R : string; - attribute CSDECODE_W : string; - attribute DATA_WIDTH_R : string; - attribute DATA_WIDTH_W : string; - attribute FULLPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111000001"; - attribute FULLPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111100001"; - attribute AFPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101000001"; - attribute AFPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101100001"; - attribute AEPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101111111"; - attribute AEPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101011111"; - attribute RESETMODE of flexi_PCS_fifo_EBR_0_0 : label is "ASYNC"; - attribute REGMODE of flexi_PCS_fifo_EBR_0_0 : label is "NOREG"; - attribute CSDECODE_R of flexi_PCS_fifo_EBR_0_0 : label is "0b11"; - attribute CSDECODE_W of flexi_PCS_fifo_EBR_0_0 : label is "0b11"; - attribute DATA_WIDTH_R of flexi_PCS_fifo_EBR_0_0 : label is "36"; - attribute DATA_WIDTH_W of flexi_PCS_fifo_EBR_0_0 : label is "36"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - flexi_PCS_fifo_EBR_0_0: FIFO16KA - -- synopsys translate_off - generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", - AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001", - AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", - CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), - DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), - DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), - DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), - DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, - DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, - DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, - DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, - DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, - DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, - FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, - EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, - WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, - RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, - DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, - DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, - DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), - DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), - DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), - DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), - DO33=>Q(15), DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, - AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int); - - Empty <= Empty_int; - Full <= Full_int; -end Structure; - --- synopsys translate_off -library SCM; -configuration Structure_CON of flexi_PCS_fifo_EBR is - for Structure - for all:VHI use entity SCM.VHI(V); end for; - for all:VLO use entity SCM.VLO(V); end for; - for all:FIFO16KA use entity SCM.FIFO16KA(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/optical_link/flexi_PCS_fifo_LUT.vhd b/optical_link/flexi_PCS_fifo_LUT.vhd deleted file mode 100644 index 8a06336..0000000 --- a/optical_link/flexi_PCS_fifo_LUT.vhd +++ /dev/null @@ -1,1167 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) --- Module Version: 4.2 ---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_LUT -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 8 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe 3 -pf 6 -e - --- Fri Nov 23 08:28:34 2007 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library SCM; -use SCM.COMPONENTS.all; --- synopsys translate_on - -entity flexi_PCS_fifo_LUT is - port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; - AlmostFull: out std_logic); -end flexi_PCS_fifo_LUT; - -architecture Structure of flexi_PCS_fifo_LUT is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal wptr_3: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal rptr_3: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co1: std_logic; - signal wcount_3: std_logic; - signal co0: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co1_1: std_logic; - signal rcount_3: std_logic; - signal co0_1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_2: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_2: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal iae_setcount_0: std_logic; - signal iae_setcount_1: std_logic; - signal iae_setcount_2: std_logic; - signal iae_setcount_3: std_logic; - signal co1_2: std_logic; - signal ae_setcount_3: std_logic; - signal co0_4: std_logic; - signal rden_i: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r1: std_logic; - signal ae_setcount_0: std_logic; - signal ae_setcount_1: std_logic; - signal co0_5: std_logic; - signal wcount_r2: std_logic; - signal ae_set_cmp_clr: std_logic; - signal ae_setcount_2: std_logic; - signal ae_set_cmp_set: std_logic; - signal ae_set_d: std_logic; - signal ae_set_d_c: std_logic; - signal iaf_setcount_0: std_logic; - signal iaf_setcount_1: std_logic; - signal iaf_setcount_2: std_logic; - signal iaf_setcount_3: std_logic; - signal co1_3: std_logic; - signal af_setcount_3: std_logic; - signal co0_6: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w1: std_logic; - signal af_setcount_0: std_logic; - signal af_setcount_1: std_logic; - signal co0_7: std_logic; - signal rcount_w2: std_logic; - signal af_set_cmp_clr: std_logic; - signal af_setcount_2: std_logic; - signal af_set_cmp_set: std_logic; - signal af_set: std_logic; - signal af_set_c: std_logic; - signal rdataout17: std_logic; - signal rdataout16: std_logic; - signal rdataout15: std_logic; - signal rdataout14: std_logic; - signal rdataout13: std_logic; - signal rdataout12: std_logic; - signal rdataout11: std_logic; - signal rdataout10: std_logic; - signal rdataout9: std_logic; - signal rdataout8: std_logic; - signal rdataout7: std_logic; - signal rdataout6: std_logic; - signal rdataout5: std_logic; - signal rdataout4: std_logic; - signal rdataout3: std_logic; - signal rdataout2: std_logic; - signal rdataout1: std_logic; - signal rdataout0: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal wren_i: std_logic; - signal scuba_vhi: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component DPR16X2 - -- synopsys translate_off - generic (INITVAL : in String; GSR : in String); - -- synopsys translate_on - port (DI0: in std_logic; DI1: in std_logic; - WAD3: in std_logic; WAD2: in std_logic; - WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic; - WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic; - RAD2: in std_logic; RAD1: in std_logic; - RAD0: in std_logic; WDO0: out std_logic; - WDO1: out std_logic; RDO0: out std_logic; - RDO1: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component FADD2 - port (A1: in std_logic; A0: in std_logic; B1: in std_logic; - B0: in std_logic; CI: in std_logic; COUT1: out std_logic; - COUT0: out std_logic; S1: out std_logic; - S0: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic; - CO: out std_logic; NC1: out std_logic; NC0: out std_logic); - end component; - component AGEB2 - port (A1: in std_logic; A0: in std_logic; B1: in std_logic; - B0: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - attribute GSR : string; - attribute initval : string; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x0410"; - attribute initval of LUT4_6 : label is "0x1004"; - attribute initval of LUT4_5 : label is "0x0140"; - attribute initval of LUT4_4 : label is "0x4001"; - attribute initval of LUT4_3 : label is "0x13c8"; - attribute initval of LUT4_2 : label is "0x2004"; - attribute initval of LUT4_1 : label is "0x4c32"; - attribute initval of LUT4_0 : label is "0x8001"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute GSR of fifo_pfu_0_0 : label is "ENABLED"; - attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_1 : label is "ENABLED"; - attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_2 : label is "ENABLED"; - attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_3 : label is "ENABLED"; - attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_4 : label is "ENABLED"; - attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_5 : label is "ENABLED"; - attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_6 : label is "ENABLED"; - attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_7 : label is "ENABLED"; - attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000"; - attribute GSR of fifo_pfu_0_8 : label is "ENABLED"; - attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t8: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t7: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t6: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t5: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t4: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t3: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t2: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t1: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t0: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_0); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_0); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x13c8") - -- synopsys translate_on - port map (AD3=>ae_setcount_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>rptr_3, DO0=>ae_set_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x2004") - -- synopsys translate_on - port map (AD3=>ae_setcount_3, AD2=>rcount_3, AD1=>w_gcount_r23, - AD0=>rptr_3, DO0=>ae_set_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4c32") - -- synopsys translate_on - port map (AD3=>af_setcount_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>wptr_3, DO0=>af_set_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8001") - -- synopsys translate_on - port map (AD3=>af_setcount_3, AD2=>wcount_3, AD1=>r_gcount_w23, - AD0=>wptr_3, DO0=>af_set_cmp_clr); - - FF_69: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_57: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_49: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_48: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_47: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_46: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_45: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(0)); - - FF_44: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(1)); - - FF_43: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(2)); - - FF_42: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(3)); - - FF_41: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(4)); - - FF_40: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(5)); - - FF_39: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(6)); - - FF_38: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(7)); - - FF_37: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(8)); - - FF_36: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(9)); - - FF_35: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(10)); - - FF_34: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(11)); - - FF_33: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(12)); - - FF_32: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(13)); - - FF_31: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(14)); - - FF_30: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(15)); - - FF_29: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(16)); - - FF_28: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>Q(17)); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_11: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_9: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_0); - - FF_8: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_1); - - FF_7: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_2, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>ae_setcount_2); - - FF_6: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iae_setcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>ae_setcount_3); - - FF_5: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ae_set_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - FF_4: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_0); - - FF_3: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>af_setcount_1); - - FF_2: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_2); - - FF_1: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>af_setcount_3); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); - - w_gctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0, - NC1=>iwcount_1, NC0=>iwcount_0); - - w_gctr_1: CU2 - port map (CI=>co0, PC1=>wcount_3, PC0=>wcount_2, CO=>co1, - NC1=>iwcount_3, NC0=>iwcount_2); - - r_gctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_1, - NC1=>ircount_1, NC0=>ircount_0); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_1, - NC1=>ircount_3, NC0=>ircount_2); - - empty_cmp_0: AGEB2 - port map (A1=>rcount_1, A0=>rcount_0, B1=>wcount_r1, - B0=>w_g2b_xor_cluster_0, CI=>rden_i, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A1=>empty_cmp_set, A0=>rcount_2, B1=>empty_cmp_clr, - B0=>wcount_r2, CI=>co0_2, GE=>empty_d_c); - - a0: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>empty_d_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>empty_d); - - full_cmp_0: AGEB2 - port map (A1=>wcount_1, A0=>wcount_0, B1=>rcount_w1, - B0=>r_g2b_xor_cluster_0, CI=>wren_i, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A1=>full_cmp_set, A0=>wcount_2, B1=>full_cmp_clr, - B0=>rcount_w2, CI=>co0_3, GE=>full_d_c); - - a1: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>full_d_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>full_d); - - ae_set_ctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>ae_setcount_1, PC0=>ae_setcount_0, - CO=>co0_4, NC1=>iae_setcount_1, NC0=>iae_setcount_0); - - ae_set_ctr_1: CU2 - port map (CI=>co0_4, PC1=>ae_setcount_3, PC0=>ae_setcount_2, - CO=>co1_2, NC1=>iae_setcount_3, NC0=>iae_setcount_2); - - ae_set_cmp_0: AGEB2 - port map (A1=>ae_setcount_1, A0=>ae_setcount_0, B1=>wcount_r1, - B0=>w_g2b_xor_cluster_0, CI=>rden_i, GE=>co0_5); - - ae_set_cmp_1: AGEB2 - port map (A1=>ae_set_cmp_set, A0=>ae_setcount_2, - B1=>ae_set_cmp_clr, B0=>wcount_r2, CI=>co0_5, GE=>ae_set_d_c); - - a2: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>ae_set_d_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>ae_set_d); - - af_set_ctr_0: CU2 - port map (CI=>scuba_vhi, PC1=>af_setcount_1, PC0=>af_setcount_0, - CO=>co0_6, NC1=>iaf_setcount_1, NC0=>iaf_setcount_0); - - af_set_ctr_1: CU2 - port map (CI=>co0_6, PC1=>af_setcount_3, PC0=>af_setcount_2, - CO=>co1_3, NC1=>iaf_setcount_3, NC0=>iaf_setcount_2); - - af_set_cmp_0: AGEB2 - port map (A1=>af_setcount_1, A0=>af_setcount_0, B1=>rcount_w1, - B0=>r_g2b_xor_cluster_0, CI=>wren_i, GE=>co0_7); - - af_set_cmp_1: AGEB2 - port map (A1=>af_set_cmp_set, A0=>af_setcount_2, - B1=>af_set_cmp_clr, B0=>rcount_w2, CI=>co0_7, GE=>af_set_c); - - a3: FADD2 - port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, - B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open, - S1=>open, S0=>af_set); - - fifo_pfu_0_0: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(16), DI1=>Data(17), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout16, RDO1=>rdataout17); - - fifo_pfu_0_1: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(14), DI1=>Data(15), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout14, RDO1=>rdataout15); - - fifo_pfu_0_2: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(12), DI1=>Data(13), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout12, RDO1=>rdataout13); - - fifo_pfu_0_3: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(10), DI1=>Data(11), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout10, RDO1=>rdataout11); - - fifo_pfu_0_4: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(8), DI1=>Data(9), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout8, RDO1=>rdataout9); - - fifo_pfu_0_5: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(6), DI1=>Data(7), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout6, RDO1=>rdataout7); - - fifo_pfu_0_6: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(4), DI1=>Data(5), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout4, RDO1=>rdataout5); - - fifo_pfu_0_7: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(2), DI1=>Data(3), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout2, RDO1=>rdataout3); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - fifo_pfu_0_8: DPR16X2 - -- synopsys translate_off - generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") - -- synopsys translate_on - port map (DI0=>Data(0), DI1=>Data(1), WAD3=>scuba_vlo, - WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, - WPE=>wren_i, WCK=>WrClock, RAD3=>scuba_vlo, RAD2=>rptr_2, - RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open, - RDO0=>rdataout0, RDO1=>rdataout1); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library SCM; -configuration Structure_CON of flexi_PCS_fifo_LUT is - for Structure - for all:DPR16X2 use entity SCM.DPR16X2(V); end for; - for all:ROM16X1 use entity SCM.ROM16X1(V); end for; - for all:AND2 use entity SCM.AND2(V); end for; - for all:OR2 use entity SCM.OR2(V); end for; - for all:XOR2 use entity SCM.XOR2(V); end for; - for all:INV use entity SCM.INV(V); end for; - for all:VHI use entity SCM.VHI(V); end for; - for all:VLO use entity SCM.VLO(V); end for; - for all:FADD2 use entity SCM.FADD2(V); end for; - for all:CU2 use entity SCM.CU2(V); end for; - for all:AGEB2 use entity SCM.AGEB2(V); end for; - for all:FD1P3BX use entity SCM.FD1P3BX(V); end for; - for all:FD1P3DX use entity SCM.FD1P3DX(V); end for; - for all:FD1S3BX use entity SCM.FD1S3BX(V); end for; - for all:FD1S3DX use entity SCM.FD1S3DX(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/optical_link/flexi_PCS_synch.vhd b/optical_link/flexi_PCS_synch.vhd deleted file mode 100644 index 39c2cc8..0000000 --- a/optical_link/flexi_PCS_synch.vhd +++ /dev/null @@ -1,112 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; -use work.trb_net_std.all; - -entity flexi_PCS_synch is - generic ( - HOW_MANY_CHANNELS : positive; - SYSTEM : positive - ); - port ( - RESET : in std_logic; - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - TXD : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MEDIA_STATUS : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MEDIA_CONTROL : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_STAT_OP : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_CTRL_OP : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - LINK_DEBUG : out std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0) - ); -end flexi_PCS_synch; - -architecture flexi_PCS_synch of flexi_PCS_synch is - - component flexi_PCS_channel_synch - generic ( - SYSTEM : positive - ); - port ( - RESET : in std_logic; - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic; - RX_CLK : in std_logic; - RXD : in std_logic_vector(15 downto 0); - RX_K : in std_logic_vector(1 downto 0); - RX_RST : out std_logic; - CV : in std_logic_vector(1 downto 0); - TXD : out std_logic_vector(15 downto 0); - TX_K : out std_logic_vector(1 downto 0); - MEDIA_STATUS : in std_logic_vector(15 downto 0); - MEDIA_CONTROL : out std_logic_vector(15 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector(15 downto 0); - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_STAT_OP : out std_logic_vector(15 downto 0); - MED_CTRL_OP : in std_logic_vector(15 downto 0); - LINK_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; - -begin - - CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate - begin - - CHANNEL_GENERATE: flexi_PCS_channel_synch - generic map ( - SYSTEM => SYSTEM - ) - port map ( - RESET => RESET, - SYSTEM_CLK => SYSTEM_CLK, - TX_CLK => TX_CLK(bit_index/4), --4 different channles clk, - RX_CLK => RX_CLK(bit_index), - RXD => RXD((bit_index*16+15) downto bit_index*16), - RX_K => RX_K(bit_index*2+1 downto bit_index*2), - RX_RST => RX_RST(bit_index), - CV => CV((bit_index*2+1) downto bit_index*2), - TXD => TXD((bit_index*16+15) downto bit_index*16), - TX_K => TX_K(bit_index*2+1 downto bit_index*2), - MEDIA_STATUS => MEDIA_STATUS((bit_index*16+15) downto bit_index*16), - MEDIA_CONTROL => MEDIA_CONTROL((bit_index*16+15) downto bit_index*16), - MED_DATAREADY_IN => MED_DATAREADY_IN(bit_index), - MED_DATA_IN => MED_DATA_IN((bit_index*16+15) downto bit_index*16), - MED_READ_OUT => MED_READ_OUT(bit_index), - MED_DATA_OUT => MED_DATA_OUT((bit_index*16+15) downto bit_index*16), - MED_DATAREADY_OUT => MED_DATAREADY_OUT(bit_index), - MED_READ_IN => MED_READ_IN(bit_index), - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH), - MED_STAT_OP => MED_STAT_OP((bit_index*16+15) downto bit_index*16), - MED_CTRL_OP => MED_CTRL_OP((bit_index*16+15) downto bit_index*16), - LINK_DEBUG => LINK_DEBUG((bit_index*32+31) downto bit_index*32) - ); - - end generate; - -end flexi_PCS_synch; diff --git a/optical_link/hub.lpf b/optical_link/hub.lpf deleted file mode 100644 index bbc963c..0000000 --- a/optical_link/hub.lpf +++ /dev/null @@ -1,541 +0,0 @@ -COMMERCIAL; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -#LOCATE COMP "ADDON_RESET" SITE "J21" ; -#LOCATE COMP "ADO_CLKOUTN" SITE "AE4" ; -#LOCATE COMP "ADO_CLKOUTP" SITE "AE3" ; -#LOCATE COMP "ADO_LV_0" SITE "D32" ; -#LOCATE COMP "ADO_LV_1" SITE "D31" ; -#LOCATE COMP "ADO_LV_2" SITE "F32" ; -#LOCATE COMP "ADO_LV_3" SITE "F31" ; -#LOCATE COMP "ADO_LV_4" SITE "J29" ; -#LOCATE COMP "ADO_LV_5" SITE "H29" ; -#LOCATE COMP "ADO_LV_6" SITE "L32" ; -#LOCATE COMP "ADO_LV_7" SITE "M32" ; -#LOCATE COMP "ADO_LV_8" SITE "P30" ; -#LOCATE COMP "ADO_LV_9" SITE "P29" ; -#LOCATE COMP "ADO_LV_10" SITE "R30" ; -#LOCATE COMP "ADO_LV_11" SITE "R29" ; -#LOCATE COMP "ADO_LV_12" SITE "T31" ; -#LOCATE COMP "ADO_LV_13" SITE "T32" ; -#LOCATE COMP "ADO_LV_14" SITE "V32" ; -#LOCATE COMP "ADO_LV_15" SITE "V31" ; -#LOCATE COMP "ADO_LV_16" SITE "W30" ; -#LOCATE COMP "ADO_LV_17" SITE "W29" ; -#LOCATE COMP "ADO_LV_18" SITE "W28" ; -#LOCATE COMP "ADO_LV_19" SITE "Y28" ; -#LOCATE COMP "ADO_LV_20" SITE "AB32" ; -#LOCATE COMP "ADO_LV_21" SITE "AA32" ; -#LOCATE COMP "ADO_LV_22" SITE "AD29" ; -#LOCATE COMP "ADO_LV_23" SITE "AD30" ; -#LOCATE COMP "ADO_LV_24" SITE "AC32" ; -#LOCATE COMP "ADO_LV_25" SITE "AD32" ; -#LOCATE COMP "ADO_LV_26" SITE "AE31" ; -#LOCATE COMP "ADO_LV_27" SITE "AE32" ; -#LOCATE COMP "ADO_LV_28" SITE "E32" ; -#LOCATE COMP "ADO_LV_29" SITE "E31" ; -#LOCATE COMP "ADO_LV_30" SITE "G31" ; -#LOCATE COMP "ADO_LV_31" SITE "G32" ; -#LOCATE COMP "ADO_LV_32" SITE "H31" ; -#LOCATE COMP "ADO_LV_33" SITE "H32" ; -#LOCATE COMP "ADO_LV_34" SITE "N31" ; -#LOCATE COMP "ADO_LV_35" SITE "N32" ; -#LOCATE COMP "ADO_LV_36" SITE "P32" ; -#LOCATE COMP "ADO_LV_37" SITE "P31" ; -#LOCATE COMP "ADO_LV_38" SITE "R31" ; -#LOCATE COMP "ADO_LV_39" SITE "R32" ; -#LOCATE COMP "ADO_LV_40" SITE "U32" ; -#LOCATE COMP "ADO_LV_41" SITE "U31" ; -#LOCATE COMP "ADO_LV_42" SITE "V29" ; -#LOCATE COMP "ADO_LV_43" SITE "V30" ; -#LOCATE COMP "ADO_LV_44" SITE "W31" ; -#LOCATE COMP "ADO_LV_45" SITE "Y31" ; -#LOCATE COMP "ADO_LV_46" SITE "W32" ; -#LOCATE COMP "ADO_LV_47" SITE "Y32" ; -#LOCATE COMP "ADO_LV_48" SITE "AD31" ; -#LOCATE COMP "ADO_LV_49" SITE "AC31" ; -#LOCATE COMP "ADO_LV_50" SITE "AC28" ; -#LOCATE COMP "ADO_LV_51" SITE "AD28" ; -#LOCATE COMP "ADO_LV_52" SITE "AE30" ; -#LOCATE COMP "ADO_LV_53" SITE "AE29" ; -#LOCATE COMP "ADO_LV_54" SITE "AF32" ; -#LOCATE COMP "ADO_LV_55" SITE "AF31" ; -#LOCATE COMP "ADO_LV_56" SITE "AG1" ; -#LOCATE COMP "ADO_LV_57" SITE "AG2" ; -#LOCATE COMP "ADO_LV_58" SITE "AE2" ; -#LOCATE COMP "ADO_LV_59" SITE "AE1" ; -#LOCATE COMP "ADO_LV_60" SITE "AF1" ; -#LOCATE COMP "ADO_LV_61" SITE "AF2" ; -LOCATE COMP "ADO_TTL_0" SITE "AJ32" ; -LOCATE COMP "ADO_TTL_1" SITE "AF27" ; -LOCATE COMP "ADO_TTL_2" SITE "AK31" ; -LOCATE COMP "ADO_TTL_3" SITE "AE25" ; -LOCATE COMP "ADO_TTL_4" SITE "AK30" ; -LOCATE COMP "ADO_TTL_5" SITE "AD23" ; -LOCATE COMP "ADO_TTL_6" SITE "AK29" ; -LOCATE COMP "ADO_TTL_7" SITE "AF26" ; -LOCATE COMP "ADO_TTL_8" SITE "AJ28" ; -LOCATE COMP "ADO_TTL_9" SITE "AJ31" ; -LOCATE COMP "ADO_TTL_10" SITE "AM30" ; -LOCATE COMP "ADO_TTL_11" SITE "AH29" ; -LOCATE COMP "ADO_TTL_12" SITE "AJ27" ; -LOCATE COMP "ADO_TTL_13" SITE "AE22" ; -LOCATE COMP "ADO_TTL_14" SITE "AL28" ; -LOCATE COMP "ADO_TTL_15" SITE "AC21" ; -LOCATE COMP "ADO_TTL_16" SITE "AM28" ; -LOCATE COMP "ADO_TTL_17" SITE "AG23" ; -LOCATE COMP "ADO_TTL_18" SITE "AG26" ; -LOCATE COMP "ADO_TTL_19" SITE "AL26" ; -LOCATE COMP "ADO_TTL_20" SITE "AK32" ; -LOCATE COMP "ADO_TTL_21" SITE "AG28" ; -LOCATE COMP "ADO_TTL_22" SITE "AL31" ; -LOCATE COMP "ADO_TTL_23" SITE "AE24" ; -LOCATE COMP "ADO_TTL_24" SITE "AL30" ; -LOCATE COMP "ADO_TTL_25" SITE "AE23" ; -LOCATE COMP "ADO_TTL_26" SITE "AL29" ; -LOCATE COMP "ADO_TTL_27" SITE "AF25" ; -LOCATE COMP "ADO_TTL_28" SITE "AK28" ; -LOCATE COMP "ADO_TTL_29" SITE "AH30" ; -LOCATE COMP "ADO_TTL_30" SITE "AM29" ; -LOCATE COMP "ADO_TTL_31" SITE "AH28" ; -LOCATE COMP "ADO_TTL_32" SITE "AK27" ; -LOCATE COMP "ADO_TTL_33" SITE "AF23" ; -LOCATE COMP "ADO_TTL_34" SITE "AL27" ; -LOCATE COMP "ADO_TTL_35" SITE "AD21" ; -LOCATE COMP "ADO_TTL_36" SITE "AM27" ; -LOCATE COMP "ADO_TTL_37" SITE "AF22" ; -LOCATE COMP "ADO_TTL_38" SITE "AG25" ; -LOCATE COMP "ADO_TTL_39" SITE "AM26" ; -LOCATE COMP "ADO_TTL_40" SITE "AK24" ; -LOCATE COMP "ADO_TTL_41" SITE "AE20" ; -LOCATE COMP "ADO_TTL_42" SITE "AJ24" ; -LOCATE COMP "ADO_TTL_43" SITE "AE21" ; -LOCATE COMP "ADO_TTL_44" SITE "AJ22" ; -LOCATE COMP "ADO_TTL_45" SITE "AK22" ; -LOCATE COMP "ADO_TTL_46" SITE "AG22" ; -IOBUF PORT "ADO_TTL_0" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_16" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_17" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_18" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_19" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_20" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_21" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_22" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_23" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_24" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_25" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_26" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_27" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_28" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_29" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_30" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_31" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_32" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_33" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_34" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_35" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_36" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_37" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_38" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_39" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_40" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_41" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_42" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_43" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_44" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_45" IO_TYPE=LVTTL33 ; -IOBUF PORT "ADO_TTL_46" IO_TYPE=LVTTL33 ; -LOCATE COMP "DBAD" SITE "AM20" ; -LOCATE COMP "DGOOD" SITE "AH20" ; -LOCATE COMP "DINT" SITE "AJ18" ; -LOCATE COMP "DWAIT" SITE "AH21" ; -IOBUF PORT "DBAD" IO_TYPE=LVTTL33 ; -IOBUF PORT "DGOOD" IO_TYPE=LVTTL33 ; -IOBUF PORT "DINT" IO_TYPE=LVTTL33 ; -IOBUF PORT "DWAIT" IO_TYPE=LVTTL33 ; -#LOCATE COMP "FROM_TRB_TO_ADDON_CLK" SITE "T10" ; -#LOCATE COMP "FROM_TRB_TO_ADDON_CLKB" SITE "T9" ; -#LOCATE COMP "FS_PE_0" SITE "J13" ; -#LOCATE COMP "FS_PE_1" SITE "K9" ; -#LOCATE COMP "FS_PE_2" SITE "J12" ; - -LOCATE COMP "FS_PE_5" SITE "AM16" ; -LOCATE COMP "FS_PE_6" SITE "AL16" ; -LOCATE COMP "FS_PE_7" SITE "AM15" ; -LOCATE COMP "FS_PE_8" SITE "AL15" ; -LOCATE COMP "FS_PE_9" SITE "AM14" ; -LOCATE COMP "FS_PE_10" SITE "AC16" ; -LOCATE COMP "FS_PE_12" SITE "AK15" ; -LOCATE COMP "FS_PE_13" SITE "AH14" ; -LOCATE COMP "FS_PE_14" SITE "AM13" ; -LOCATE COMP "FS_PE_15" SITE "AH12" ; -LOCATE COMP "FS_PE_16" SITE "AK14" ; -LOCATE COMP "FS_PE_17" SITE "AD15" ; - -IOBUF PORT "FS_PE_5" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_6" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_7" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_8" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_9" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_10" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_12" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_13" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_14" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_15" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_16" IO_TYPE=LVTTL33; -IOBUF PORT "FS_PE_17" IO_TYPE=LVTTL33; - -LOCATE COMP "FS_PE_11" SITE "AH16" ; -IOBUF PORT "FS_PE_11" IO_TYPE=LVTTL33 ; - - -LOCATE COMP "OPLL" SITE "AL11" ; -LOCATE COMP "IPLL" SITE "AL10" ; -LOCATE COMP "LOK_1" SITE "AJ1" ; -LOCATE COMP "LOK_2" SITE "AL2" ; -LOCATE COMP "LOK_3" SITE "AK3" ; -LOCATE COMP "LOK_4" SITE "AL4" ; -LOCATE COMP "LOK_5" SITE "AM4" ; -LOCATE COMP "LOK_6" SITE "AH5" ; -LOCATE COMP "LOK_7" SITE "AG5" ; -LOCATE COMP "LOK_8" SITE "AK5" ; -LOCATE COMP "LOK_9" SITE "AK6" ; -LOCATE COMP "LOK_10" SITE "AM5" ; -LOCATE COMP "LOK_11" SITE "AM6" ; -LOCATE COMP "LOK_12" SITE "AF8" ; -LOCATE COMP "LOK_13" SITE "AE9" ; -LOCATE COMP "LOK_14" SITE "AE10" ; -LOCATE COMP "LOK_15" SITE "AF11" ; -LOCATE COMP "LOK_16" SITE "AD12" ; -IOBUF PORT "IPLL" IO_TYPE=LVTTL33 ; -IOBUF PORT "OPLL" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "LOK_16" IO_TYPE=LVTTL33 ; -LOCATE COMP "LVDS_CLK_200P" SITE "P3" ; -#LOCATE COMP "LVDS_CLK_200N" SITE "P4" ; -IOBUF PORT "LVDS_CLK_200P" IO_TYPE=LVDS ; -#IOBUF PORT "LVDS_CLK_200N" IO_TYPE=LVDS ; -FREQUENCY PORT "LVDS_CLK_200P" 110.000000 MHz ; -#FREQUENCY PORT "LVDS_CLK_200N" 200.000000 MHz ; -IOBUF PORT "LVDS_CLK_200P" DIFFRESISTOR=120 ; - -#LOCATE COMP "RESET" SITE "AL23" ; -LOCATE COMP "RT_1" SITE "AK1" ; -LOCATE COMP "RT_2" SITE "AK2" ; -LOCATE COMP "RT_3" SITE "AJ3" ; -LOCATE COMP "RT_4" SITE "AL3" ; -LOCATE COMP "RT_5" SITE "AM3" ; -LOCATE COMP "RT_6" SITE "AH4" ; -LOCATE COMP "RT_7" SITE "AF6" ; -LOCATE COMP "RT_8" SITE "AJ5" ; -LOCATE COMP "RT_9" SITE "AJ6" ; -LOCATE COMP "RT_10" SITE "AL5" ; -LOCATE COMP "RT_11" SITE "AL6" ; -LOCATE COMP "RT_12" SITE "AF7" ; -LOCATE COMP "RT_13" SITE "AE8" ; -LOCATE COMP "RT_14" SITE "AD10" ; -LOCATE COMP "RT_15" SITE "AE11" ; -LOCATE COMP "RT_16" SITE "AE12" ; -IOBUF PORT "RT_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "RT_16" IO_TYPE=LVTTL33 ; - - - - -#LOCATE COMP "GBIT_INP_N" SITE "C2" ; -#LOCATE COMP "GBIT_INP_P" SITE "C1" ; -#LOCATE COMP "GBIT_OUT_N" SITE "B3" ; -#LOCATE COMP "GBIT_OUT_P" SITE "A3" ; - -#LOCATE COMP "GBIT_SFP_MOD_0" SITE "A19" ; -#LOCATE COMP "GBIT_SFP_MOD_1" SITE "H18" ; -#LOCATE COMP "GBIT_SFP_MOD_2" SITE "H17" ; - -#LOCATE COMP "GBIT_TX_FAULT" SITE "K15" ; -#LOCATE COMP "S1_GBIT_SFP_MOD_0" SITE "AG17" ; -#LOCATE COMP "S1_GBIT_TX_FAULT" SITE "AK21" ; -#LOCATE COMP "S2_GBIT_TX_DIS" SITE "AF19" ; - -#LOCATE COMP "S2_GBIT_SFP_MOD_0" SITE "AC17" ; - -#LOCATE COMP "S2_GBIT_TX_FAULT" SITE "AM23" ; -#LOCATE COMP "S3_GBIT_SFP_MOD_0" SITE "AM17" ; -#LOCATE COMP "S3_GBIT_TX_FAULT" SITE "AH26" ; -#LOCATE COMP "S3_GBIT_TX_DIS" SITE "AH25" ; - -#LOCATE COMP "S1_GBIT_TX_DIS" SITE "AJ21" ; -#LOCATE COMP "S1_GBIT_SFP_MOD_1" SITE "AL18" ; -#LOCATE COMP "S3_GBIT_SFP_MOD_1" SITE "AE17" ; -#LOCATE COMP "S2_GBIT_SFP_MOD_1" SITE "AD17" ; -#LOCATE COMP "S2_GBIT_SFP_MOD_2" SITE "AL17" ; -#LOCATE COMP "S3_GBIT_SFP_MOD_2" SITE "AF17" ; -#LOCATE COMP "S1_GBIT_SFP_MOD_2" SITE "AM18" ; -#LOCATE COMP "SERDES_125P" SITE "C5" ; -#LOCATE COMP "SERDES_200N" SITE "D28" ; -#LOCATE COMP "SERDES_200P" SITE "C28" ; -#LOCATE COMP "SERDES_200N" SITE "A_REFCLKN_L" ; -#LOCATE COMP "SERDES_200P" SITE "A_REFCLKP_L" ; - -#LOCATE COMP "SERDES_125N" SITE "D5" ; -#LOCATE COMP "SFP7_MOD_0" SITE "AE14" ; -#LOCATE COMP "SFP2_MOD_0" SITE "J18" ; -#LOCATE COMP "SFP1_MOD_0" SITE "F20" ; -#LOCATE COMP "SFP4_MOD_0" SITE "D20" ; -#LOCATE COMP "SFP3_MOD_0" SITE "G20" ; -#LOCATE COMP "SFP8_MOD_0" SITE "AK12" ; -#LOCATE COMP "SFP12_MOD_0" SITE "J17" ; -#LOCATE COMP "SFP9_MOD_0" SITE "AM10" ; -#LOCATE COMP "SFP5_MOD_0" SITE "C19" ; -#LOCATE COMP "SFP11_MOD_0" SITE "D18" ; -#LOCATE COMP "SFP6_MOD_0" SITE "E17" ; -#LOCATE COMP "SFP10_MOD_0" SITE "AG14" ; -#LOCATE COMP "SFP12_MOD_1" SITE "L20" ; -#LOCATE COMP "SFP11_MOD_1" SITE "C18" ; -#LOCATE COMP "SFP9_MOD_1" SITE "AM11" ; -#LOCATE COMP "SFP6_MOD_1" SITE "B20" ; -#LOCATE COMP "SFP8_MOD_1" SITE "AH10" ; -#LOCATE COMP "SFP4_MOD_1" SITE "G19" ; -#LOCATE COMP "SFP5_MOD_1" SITE "C20" ; -#LOCATE COMP "SFP3_MOD_1" SITE "H20" ; -#LOCATE COMP "SFP7_MOD_1" SITE "AF14" ; -#LOCATE COMP "SFP1_MOD_1" SITE "E20" ; -#LOCATE COMP "SFP2_MOD_1" SITE "F19" ; -#LOCATE COMP "SFP10_MOD_1" SITE "AL12" ; -#LOCATE COMP "SFP10_MOD_2" SITE "AL13" ; -#LOCATE COMP "SFP5_MOD_2" SITE "E18" ; -#LOCATE COMP "SFP4_MOD_2" SITE "H19" ; -#LOCATE COMP "SFP9_MOD_2" SITE "AG13" ; -#LOCATE COMP "SFP6_MOD_2" SITE "B19" ; -#LOCATE COMP "SFP2_MOD_2" SITE "E19" ; -#LOCATE COMP "SFP7_MOD_2" SITE "AJ12" ; -#LOCATE COMP "SFP3_MOD_2" SITE "D19" ; -#LOCATE COMP "SFP1_MOD_2" SITE "K18" ; -#LOCATE COMP "SFP8_MOD_2" SITE "AH11" ; -#LOCATE COMP "SFP12_MOD_2" SITE "A20" ; -#LOCATE COMP "SFP11_MOD_2" SITE "K17" ; -#IOBUF PORT "SFP7_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP2_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP1_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP4_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP3_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP8_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP12_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP9_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP5_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP11_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP6_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP10_MOD_0" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP12_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP11_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP9_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP6_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP8_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP4_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP5_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP3_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP7_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP1_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP2_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP10_MOD_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP10_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP5_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP4_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP9_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP6_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP2_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP7_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP3_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP1_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP8_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP12_MOD_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "SFP11_MOD_2" IO_TYPE=LVTTL33 ; - -#LOCATE COMP "GBIT_SFP_LOS" SITE "J15" ; -#LOCATE COMP "S2_GBIT_SFP_LOS" SITE "AM22" ; -#LOCATE COMP "S3_GBIT_SFP_LOS" SITE "AL21" ; -#LOCATE COMP "S1_GBIT_SFP_LOS" SITE "AE19" ; - - - -LOCATE COMP "SFP_LOS_1" SITE "A18" ; -LOCATE COMP "SFP_LOS_2" SITE "A15" ; -LOCATE COMP "SFP_LOS_3" SITE "B15" ; -LOCATE COMP "SFP_LOS_4" SITE "G16" ; -LOCATE COMP "SFP_LOS_5" SITE "H16" ; -LOCATE COMP "SFP_LOS_6" SITE "J16" ; -LOCATE COMP "SFP_LOS_7" SITE "L13" ; -LOCATE COMP "SFP_LOS_8" SITE "C14" ; -LOCATE COMP "SFP_LOS_9" SITE "E15" ; -LOCATE COMP "SFP_LOS_10" SITE "G14" ; -LOCATE COMP "SFP_LOS_11" SITE "E14" ; -LOCATE COMP "SFP_LOS_12" SITE "F13" ; -LOCATE COMP "SFP_LOS_13" SITE "J15" ; -LOCATE COMP "SFP_LOS_14" SITE "AE19" ; -LOCATE COMP "SFP_LOS_15" SITE "AM22" ; -LOCATE COMP "SFP_LOS_16" SITE "AL21" ; - -IOBUF PORT "SFP_LOS_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "SFP_LOS_16" IO_TYPE=LVTTL33 ; - - -#LOCATE COMP "quad_a/PCSA_INST" SITE "PCS36000" ; -LOCATE COMP "QUAD_GENERATE_0_QUAD/PCSA_INST" SITE "PCS36000" ; -LOCATE COMP "QUAD_GENERATE_1_QUAD/PCSA_INST" SITE "PCS36100" ; -LOCATE COMP "QUAD_GENERATE_2_QUAD/PCSA_INST" SITE "PCS3E100" ; -LOCATE COMP "QUAD_GENERATE_3_QUAD/PCSA_INST" SITE "PCS3E000" ; -#LOCATE COMP "TEST/PCSA_INST" SITE "PCS36000" ; -FREQUENCY NET "ref_pclk_0" 100.000000MHz; -FREQUENCY NET "rx_clk_i_0" 100.000000MHz; -FREQUENCY NET "rx_clk_i_1" 100.000000MHz; -FREQUENCY NET "rx_clk_i_2" 100.000000MHz; -FREQUENCY NET "rx_clk_i_3" 100.000000MHz; -FREQUENCY NET "ref_pclk_1" 100.000000MHz; -FREQUENCY NET "rx_clk_i_4" 100.000000MHz; -FREQUENCY NET "rx_clk_i_5" 100.000000MHz; -FREQUENCY NET "rx_clk_i_6" 100.000000MHz; -FREQUENCY NET "rx_clk_i_7" 100.000000MHz; -FREQUENCY NET "ref_pclk_2" 100.000000MHz; -FREQUENCY NET "rx_clk_i_8" 100.000000MHz; -FREQUENCY NET "rx_clk_i_9" 100.000000MHz; -FREQUENCY NET "rx_clk_i_10" 100.000000MHz; -FREQUENCY NET "rx_clk_i_11" 100.000000MHz; -FREQUENCY NET "ref_pclk_3" 100.000000MHz; -FREQUENCY NET "rx_clk_i_12" 100.000000MHz; -FREQUENCY NET "rx_clk_i_13" 100.000000MHz; -FREQUENCY NET "rx_clk_i_14" 100.000000MHz; -FREQUENCY NET "rx_clk_i_15" 100.000000MHz; - - -FREQUENCY PORT "ref_pclk_1/QUAD_GENERATE_1_QUAD" 100.000000MHz; -FREQUENCY PORT "ref_pclk_2/QUAD_GENERATE_2_QUAD" 100.000000MHz; -FREQUENCY PORT "ref_pclk_3/QUAD_GENERATE_3_QUAD" 100.000000MHz; -FREQUENCY PORT "ref_pclk_0/QUAD_GENERATE_0_QUAD" 100.000000MHz; - -#FREQUENCY PORT "rxa_pclk_a/quad_a" 100.000000MHz; -#FREQUENCY PORT "rx_1_sclk_a/quad_a" 100.000000MHz; -#FREQUENCY PORT "rx_2_sclk_a/quad_a" 100.000000MHz; -#FREQUENCY PORT "rx_3_sclk_a/quad_a" 100.000000MHz; -#LOCATE COMP "SUPPL_RESET" SITE "B18" ; - - - - - - -LOCATE COMP "TX_DIS_1" SITE "G17" ; -LOCATE COMP "TX_DIS_2" SITE "A17" ; -LOCATE COMP "TX_DIS_3" SITE "A16" ; -LOCATE COMP "TX_DIS_4" SITE "B16" ; -LOCATE COMP "TX_DIS_5" SITE "A13" ; -LOCATE COMP "TX_DIS_6" SITE "H15" ; -LOCATE COMP "TX_DIS_7" SITE "D15" ; -LOCATE COMP "TX_DIS_8" SITE "B13" ; -LOCATE COMP "TX_DIS_9" SITE "C13" ; -LOCATE COMP "TX_DIS_10" SITE "D14" ; -LOCATE COMP "TX_DIS_11" SITE "H14" ; -LOCATE COMP "TX_DIS_12" SITE "G13" ; -LOCATE COMP "TX_DIS_13" SITE "E13" ; -LOCATE COMP "TX_DIS_14" SITE "AJ21" ; -LOCATE COMP "TX_DIS_15" SITE "AF19" ; -LOCATE COMP "TX_DIS_16" SITE "AH25" ; - -IOBUF PORT "TX_DIS_1" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_2" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_3" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_4" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_5" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_6" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_7" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_8" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_9" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_10" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_11" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_12" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_13" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_14" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_15" IO_TYPE=LVTTL33 ; -IOBUF PORT "TX_DIS_16" IO_TYPE=LVTTL33 ; - -#LOCATE COMP "TX_FAULT_1" SITE "F17" ; -#LOCATE COMP "TX_FAULT_2" SITE "L17" ; -#LOCATE COMP "TX_FAULT_3" SITE "L16" ; -#LOCATE COMP "TX_FAULT_4" SITE "F16" ; -#LOCATE COMP "TX_FAULT_5" SITE "A14" ; -#LOCATE COMP "TX_FAULT_6" SITE "K16" ; -#LOCATE COMP "TX_FAULT_7" SITE "C15" ; -#LOCATE COMP "TX_FAULT_8" SITE "B14" ; -#LOCATE COMP "TX_FAULT_9" SITE "E16" ; -#LOCATE COMP "TX_FAULT_10" SITE "D13" ; -#LOCATE COMP "TX_FAULT_11" SITE "F14" ; -#LOCATE COMP "TX_FAULT_12" SITE "H13" ; -#IOBUF PORT "TX_FAULT_1" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_2" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_3" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_4" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_5" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_6" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_7" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_8" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_9" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_10" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_11" IO_TYPE=LVTTL33 ; -#IOBUF PORT "TX_FAULT_12" IO_TYPE=LVTTL33 ; - - diff --git a/optical_link/hub.vhd b/optical_link/hub.vhd deleted file mode 100644 index 1dd4586..0000000 --- a/optical_link/hub.vhd +++ /dev/null @@ -1,1027 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.all; -use work.version.all; -use work.trb_net_std.all; -use work.trb_net16_hub_func.all; -use ieee.std_logic_arith.all; --- library sc; --- use sc.components.all; -entity hub is - generic ( - HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 4 - ); - port ( - LVDS_CLK_200P : in std_logic; - --addon connector - ADO_TTL : inout std_logic_vector(46 downto 0); - --diodes - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - --sfp - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; - --data to/from optical tranceivers - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0); - --sfp - SFP_LOS : in std_logic_vector(16 downto 1); - --tempsens - FS_PE_11 : inout std_logic; - --etrax_interface - FS_PE : inout std_logic_vector(9 downto 8)--sim--; ---sim-- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); ---sim-- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); ---sim-- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); ---sim-- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0) - ); -end hub; ---add all sfp connections to measure opt. power temp. sens and if there is SFP - -architecture hub of hub is - - component serdes_fpga_ref_clk - port( - rxrefclk : in std_logic; - refclk : in std_logic; - hdinp_0 : in std_logic; - hdinn_0 : in std_logic; - tclk_0 : in std_logic; - rclk_0 : in std_logic; - tx_rst_0 : in std_logic; - rx_rst_0 : in std_logic; - txd_0 : in std_logic_vector(15 downto 0); - tx_k_0 : in std_logic_vector(1 downto 0); - tx_force_disp_0 : in std_logic_vector(1 downto 0); - tx_disp_sel_0 : in std_logic_vector(1 downto 0); - tx_crc_init_0 : in std_logic_vector(1 downto 0); - word_align_en_0 : in std_logic; - mca_align_en_0 : in std_logic; - felb_0 : in std_logic; - lsm_en_0 : in std_logic; - hdinp_1 : in std_logic; - hdinn_1 : in std_logic; - tclk_1 : in std_logic; - rclk_1 : in std_logic; - tx_rst_1 : in std_logic; - rx_rst_1 : in std_logic; - txd_1 : in std_logic_vector(15 downto 0); - tx_k_1 : in std_logic_vector(1 downto 0); - tx_force_disp_1 : in std_logic_vector(1 downto 0); - tx_disp_sel_1 : in std_logic_vector(1 downto 0); - tx_crc_init_1 : in std_logic_vector(1 downto 0); - word_align_en_1 : in std_logic; - mca_align_en_1 : in std_logic; - felb_1 : in std_logic; - lsm_en_1 : in std_logic; - hdinp_2 : in std_logic; - hdinn_2 : in std_logic; - tclk_2 : in std_logic; - rclk_2 : in std_logic; - tx_rst_2 : in std_logic; - rx_rst_2 : in std_logic; - txd_2 : in std_logic_vector(15 downto 0); - tx_k_2 : in std_logic_vector(1 downto 0); - tx_force_disp_2 : in std_logic_vector(1 downto 0); - tx_disp_sel_2 : in std_logic_vector(1 downto 0); - tx_crc_init_2 : in std_logic_vector(1 downto 0); - word_align_en_2 : in std_logic; - mca_align_en_2 : in std_logic; - felb_2 : in std_logic; - lsm_en_2 : in std_logic; - hdinp_3 : in std_logic; - hdinn_3 : in std_logic; - tclk_3 : in std_logic; - rclk_3 : in std_logic; - tx_rst_3 : in std_logic; - rx_rst_3 : in std_logic; - txd_3 : in std_logic_vector(15 downto 0); - tx_k_3 : in std_logic_vector(1 downto 0); - tx_force_disp_3 : in std_logic_vector(1 downto 0); - tx_disp_sel_3 : in std_logic_vector(1 downto 0); - tx_crc_init_3 : in std_logic_vector(1 downto 0); - word_align_en_3 : in std_logic; - mca_align_en_3 : in std_logic; - felb_3 : in std_logic; - lsm_en_3 : in std_logic; - mca_resync_01 : in std_logic; - mca_resync_23 : in std_logic; - quad_rst : in std_logic; - serdes_rst : in std_logic; - rxa_pclk : out std_logic; - rxb_pclk : out std_logic; - hdoutp_0 : out std_logic; - hdoutn_0 : out std_logic; - ref_0_sclk : out std_logic; - rx_0_sclk : out std_logic; - rxd_0 : out std_logic_vector(15 downto 0); - rx_k_0 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_0 : out std_logic_vector(1 downto 0); - rx_cv_detect_0 : out std_logic_vector(1 downto 0); - rx_crc_eop_0 : out std_logic_vector(1 downto 0); - lsm_status_0 : out std_logic; - hdoutp_1 : out std_logic; - hdoutn_1 : out std_logic; - ref_1_sclk : out std_logic; - rx_1_sclk : out std_logic; - rxd_1 : out std_logic_vector(15 downto 0); - rx_k_1 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_1 : out std_logic_vector(1 downto 0); - rx_cv_detect_1 : out std_logic_vector(1 downto 0); - rx_crc_eop_1 : out std_logic_vector(1 downto 0); - lsm_status_1 : out std_logic; - hdoutp_2 : out std_logic; - hdoutn_2 : out std_logic; - ref_2_sclk : out std_logic; - rx_2_sclk : out std_logic; - rxd_2 : out std_logic_vector(15 downto 0); - rx_k_2 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_2 : out std_logic_vector(1 downto 0); - rx_cv_detect_2 : out std_logic_vector(1 downto 0); - rx_crc_eop_2 : out std_logic_vector(1 downto 0); - lsm_status_2 : out std_logic; - hdoutp_3 : out std_logic; - hdoutn_3 : out std_logic; - ref_3_sclk : out std_logic; - rx_3_sclk : out std_logic; - rxd_3 : out std_logic_vector(15 downto 0); - rx_k_3 : out std_logic_vector(1 downto 0); - rx_disp_err_detect_3 : out std_logic_vector(1 downto 0); - rx_cv_detect_3 : out std_logic_vector(1 downto 0); - rx_crc_eop_3 : out std_logic_vector(1 downto 0); - lsm_status_3 : out std_logic; - mca_aligned_01 : out std_logic; - mca_inskew_01 : out std_logic; - mca_outskew_01 : out std_logic; - mca_aligned_23 : out std_logic; - mca_inskew_23 : out std_logic; - mca_outskew_23 : out std_logic; - ref_pclk : out std_logic - ); - end component; - - component up_down_counter - generic ( - NUMBER_OF_BITS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic; - DOWN_IN : in std_logic); - end component; - - component flexi_PCS_synch - generic ( - HOW_MANY_CHANNELS : positive; - SYSTEM : positive ); - port ( - RESET : in std_logic; - SYSTEM_CLK : in std_logic; - TX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - TXD : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - MEDIA_STATUS : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MEDIA_CONTROL : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - MED_STAT_OP : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - MED_CTRL_OP : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - LINK_DEBUG : out std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0) - ); - end component; - - component trb_net16_hub_base is - generic ( - --don't change - --hub control - HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL; - HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; - HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES); - USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES); - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - --media interfaces - MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 3; - MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; - -- settings for external api connections - INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; - INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); - INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6) - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - --Media interfacces - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0); - MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0); - --INT: interfaces to connect APIs - INT_INIT_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0); - INT_INIT_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0); - INT_INIT_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); - INT_INIT_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); - INT_INIT_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0'); - INT_INIT_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0'); - INT_INIT_READ_OUT : out std_logic_vector (INT_NUMBER downto 0); - INT_REPLY_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0); - INT_REPLY_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0); - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0); - INT_REPLY_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); - INT_REPLY_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); - INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0'); - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0'); - INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0); - ONEWIRE : inout std_logic; - --Fixed status and control ports - HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); - HUB_STAT_GEN : out std_logic_vector (31 downto 0); - MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); - MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); - STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs - STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs - STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs - STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs - --Additional access to registers - REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0); - REGIO_EXT_REG_DATA_OUT: out std_logic_vector(31 downto 0); - REGIO_EXT_REG_WRITE_IN: in std_logic; - REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0); - - --Debugging registers - STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging - CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging - ); - end component; - - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - - component etrax_interfacev2 - generic ( - RW_SYSTEM : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_BUS : in std_logic_vector(31 downto 0); - ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0); - ETRAX_DATA_BUS_B_17 : in std_logic; - ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0); - ETRAX_DATA_BUS_E : inout std_logic_vector(10 downto 9); - DATA_VALID : in std_logic; - ETRAX_BUS_BUSY : in std_logic; - ETRAX_IS_READY_TO_READ : out std_logic; - TDC_TCK : out std_logic; - TDC_TDI : out std_logic; - TDC_TMS : out std_logic; - TDC_TRST : out std_logic; - TDC_TDO : in std_logic; - TDC_RESET : out std_logic; - EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); - EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); - EXTERNAL_ACK : out std_logic; - EXTERNAL_VALID : in std_logic; - EXTERNAL_MODE : out std_logic_vector(15 downto 0); - FPGA_REGISTER_00 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); - FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0E : out std_logic_vector(31 downto 0); --- EXTERNAL_RESET : out std_logic; - LVL2_VALID : in std_logic); - end component; - - component simple_hub - generic ( - HOW_MANY_CHANNELS : positive); - port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - DATA_IN_VALID : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - SEND_DATA : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - ENABLE_CHANNELS : in std_logic_vector(15 downto 0); - READ_DATA : out std_logic_vector(HOW_MANY_CHANNELS -1 downto 0); - HUB_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; - - --- constant HOW_MANY_CHANNELS : integer := 16; - ----------------------------------------------------------------------------- - -- FLEXI_PCS - ----------------------------------------------------------------------------- - signal ref_pclk : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0); - signal rxd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal rxd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal rx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rx_rst_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal cv_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal txd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - signal tx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0); - signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal link_debug_i : std_logic_vector(HOW_MANY_CHANNELS*32-1 downto 0); - signal word_align_en : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - ----------------------------------------------------------------------------- - -- hub trb interface - ----------------------------------------------------------------------------- - signal hub_register_00_i : std_logic_vector(31 downto 0); - signal hub_register_01_i : std_logic_vector(31 downto 0); - signal hub_register_02_i : std_logic_vector(31 downto 0); - signal hub_register_03_i : std_logic_vector(31 downto 0); - signal hub_register_04_i : std_logic_vector(31 downto 0); - signal hub_register_05_i : std_logic_vector(31 downto 0); - signal hub_register_06_i : std_logic_vector(31 downto 0); - signal hub_register_07_i : std_logic_vector(31 downto 0); - signal hub_register_08_i : std_logic_vector(31 downto 0); - signal hub_register_09_i : std_logic_vector(31 downto 0); - signal hub_register_0a_i : std_logic_vector(31 downto 0); - signal hub_register_0b_i : std_logic_vector(31 downto 0); - signal hub_register_0c_i : std_logic_vector(31 downto 0); - signal hub_register_0d_i : std_logic_vector(31 downto 0); - signal hub_register_0e_i : std_logic_vector(31 downto 0); - signal hub_register_0f_i : std_logic_vector(31 downto 0); - signal hub_register_10_i : std_logic_vector(31 downto 0); - signal hub_register_11_i : std_logic_vector(31 downto 0); - signal hub_register_12_i : std_logic_vector(31 downto 0); - signal hub_register_13_i : std_logic_vector(31 downto 0); - signal hub_register_14_i : std_logic_vector(31 downto 0); - signal hub_register_15_i : std_logic_vector(31 downto 0); - signal hub_register_16_i : std_logic_vector(31 downto 0); - signal ADO_TTL_12 : std_logic; - ----------------------------------------------------------------------------- - -- flexi_PCS to hub interface - ----------------------------------------------------------------------------- - signal med_dataready_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_dataready_in_i_test : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - --test - signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_dataready_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_read_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_read_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal med_data_out_i_test : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - - signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0); - signal med_error_out_i : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0); - signal med_stat_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - signal hub_stat_channel_i : std_logic_vector(2**(c_MUX_WIDTH-1)*16-1 downto 0); - signal hub_stat_gen_i : std_logic_vector(31 downto 0); - - ----------------------------------------------------------------------------- - -- other - ----------------------------------------------------------------------------- - signal hub_register_0e_and_0d : std_logic_vector(15 downto 0) := x"0006"; - signal cv_counter : std_logic_vector(31 downto 0); - signal cv_countera : std_logic_vector(31 downto 0); - signal serdes_ref_clk : std_logic; - signal serdes_ref_lock : std_logic; - signal serdes_ref_clks : std_logic; - signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0); - signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0); - signal word_counter_for_api_00 : std_logic_vector(1 downto 0); - signal word_counter_for_api_01 : std_logic_vector(1 downto 0); - signal global_reset_i : std_logic; - signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0"; - signal registered_signals : std_logic_vector(7 downto 0); - signal hub_register_0a_i_synch : std_logic_vector(7 downto 0); - signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0); - signal test_signal : std_logic_vector(1 downto 0); - signal pulse_test : std_logic; - signal saved_lvl1_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0'); - signal saved_lvl2_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0'); - signal all_lvl1_ready : std_logic; - signal all_lvl2_ready : std_logic; - signal flexi_pcs_ref_clk : std_logic; - signal lok_i : std_logic_vector(16 downto 1); - signal not_used_lok : std_logic_vector(15 downto 0); - signal used_channels_locked : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal channels_locked : std_logic_vector(16 downto 1); - signal switch_rx_clk : std_logic; - signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - signal all_lvl1_ready_delay1 : std_logic; - signal all_lvl1_ready_delay2 : std_logic; - signal all_lvl2_ready_delay1 : std_logic; - signal all_lvl2_ready_delay2 : std_logic; - signal media_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); - -- etrax interface --- signal external_address_i : std_logic_vector(31 downto 0); --- signal external_data_out_i : std_logic_vector(31 downto 0); --- signal external_data_in_i : std_logic_vector(31 downto 0); --- signal external_ack_i : std_logic; --- signal external_valid_i : std_logic; --- signal external_mode_i : std_logic_vector(7 downto 0); --- signal data_valid_i : std_logic; - signal debug_register_00_i : std_logic_vector(7 downto 0); - signal test2 : std_logic_vector(1 downto 0); - signal med_read_counter : std_logic_vector(3 downto 0); - -- simulation - signal rx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal tx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - constant trb_net_enable : integer := 1; - --etrax interface - signal external_address_i : std_logic_vector(31 downto 0); - signal external_data_out_i : std_logic_vector(31 downto 0); - signal external_data_in_i : std_logic_vector(31 downto 0); - signal external_ack_i : std_logic; - signal external_valid_i : std_logic; - signal external_mode_i : std_logic_vector(15 downto 0); - signal fpga_register_00_i : std_logic_vector(31 downto 0); - signal fpga_register_01_i : std_logic_vector(31 downto 0); - signal fpga_register_02_i : std_logic_vector(31 downto 0); - signal fpga_register_03_i : std_logic_vector(31 downto 0); - signal fpga_register_04_i : std_logic_vector(31 downto 0); - signal fpga_register_05_i : std_logic_vector(31 downto 0); - signal fpga_register_06_i : std_logic_vector(31 downto 0):=x"00000003"; - signal fpga_register_07_i : std_logic_vector(31 downto 0); - signal fpga_register_08_i : std_logic_vector(31 downto 0); - signal fpga_register_09_i : std_logic_vector(31 downto 0); - signal fpga_register_0a_i : std_logic_vector(31 downto 0); - signal fpga_register_0b_i : std_logic_vector(31 downto 0); - signal fpga_register_0c_i : std_logic_vector(31 downto 0); - signal fpga_register_0d_i : std_logic_vector(31 downto 0); - signal fpga_register_0e_i : std_logic_vector(31 downto 0); - signal free_counter : std_logic_vector(16 downto 0); - --simple hub - signal hub_debug_i : std_logic_vector(31 downto 0); - - --test - constant OPT_TEST_MODE : integer := 0; - - --trbnet - signal hub_stat_debug_i : std_logic_vector(63 downto 0); - signal hub_ctrl_debug_i : std_logic_vector(63 downto 0); - signal sfp_los_synch : std_logic_vector(16 downto 1); - signal wait_counter : std_logic_vector(31 downto 0); - signal wait_counter_up : std_logic; -begin - - GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_cnt < x"e" then - global_reset_cnt <= global_reset_cnt + 1; - global_reset_i <= '1'; - elsif global_reset_cnt = x"e" then - global_reset_i <= '0'; - global_reset_cnt <= x"e"; - else - global_reset_i <= '0'; - global_reset_cnt <= global_reset_cnt; - end if; - end if; - end process GLOBAL_RESET; - - QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate - begin - QUAD : serdes_fpga_ref_clk - port map ( - rxrefclk => LVDS_CLK_200P,--flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, - refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, - hdinp_0 => SFP_INP_P(bit_index*4+0), - hdinn_0 => SFP_INP_N(bit_index*4+0), - tclk_0 => ref_pclk(bit_index), - rclk_0 => rx_clk_i(0+bit_index*4), - tx_rst_0 => '0', - rx_rst_0 => rx_rst_i(0+bit_index*4),--hub_register_0a_i(0), - txd_0 => txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,-- - tx_k_0 => tx_k_i(1+bit_index*8 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10", - tx_force_disp_0 => "00",--hub_register_0a_i(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8), - tx_disp_sel_0 => "00",--hub_register_0a_i(5 downto 4), --"00",--hub_register_0a_i_synch(5 downto 4),--"00", - tx_crc_init_0 => "00", - word_align_en_0 => '1',--word_align_en(0+bit_index*4),--'1', - mca_align_en_0 => '0', - felb_0 => '0', - lsm_en_0 => '0', - hdinp_1 => SFP_INP_P(bit_index*4+1), - hdinn_1 => SFP_INP_N(bit_index*4+1), - tclk_1 => ref_pclk(bit_index), - rclk_1 => rx_clk_i(1+bit_index*4), - tx_rst_1 => '0', - rx_rst_1 => rx_rst_i(1+bit_index*4), - txd_1 => txd_synch_i(31+bit_index*64 downto 16+bit_index*64), - tx_k_1 => tx_k_i(3+bit_index*8 downto 2+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10", - tx_force_disp_1 => "00",--tx_k_i(3+bit_index*8 downto 2+bit_index*8), - tx_disp_sel_1 => "00", - tx_crc_init_1 => "00", - word_align_en_1 => '1',--word_align_en(1+bit_index*4),--'1',-- - mca_align_en_1 => '0', - felb_1 => '0', - lsm_en_1 => '0', - hdinp_2 => SFP_INP_P(bit_index*4+2), - hdinn_2 => SFP_INP_N(bit_index*4+2), - tclk_2 => ref_pclk(bit_index), - rclk_2 => rx_clk_i(2+bit_index*4), - tx_rst_2 => '0', - rx_rst_2 => rx_rst_i(2+bit_index*4), - txd_2 => txd_synch_i(47+bit_index*64 downto 32+bit_index*64), - tx_k_2 => tx_k_i(5+bit_index*8 downto 4+bit_index*8),--"10", - tx_force_disp_2 => "00",-- - tx_disp_sel_2 => "00", - tx_crc_init_2 => "00", - word_align_en_2 => '1',--word_align_en(2+bit_index*4),--'1', - mca_align_en_2 => '0', - felb_2 => '0', - lsm_en_2 => '0', - hdinp_3 => SFP_INP_P(bit_index*4+3), - hdinn_3 => SFP_INP_N(bit_index*4+3), - tclk_3 => ref_pclk(bit_index), - rclk_3 => rx_clk_i(3+bit_index*4), - tx_rst_3 => '0', - rx_rst_3 => rx_rst_i(3+bit_index*4), - txd_3 => txd_synch_i(63+bit_index*64 downto 48+bit_index*64), - tx_k_3 => tx_k_i(7+bit_index*8 downto 6+bit_index*8),--"10", - tx_force_disp_3 => "00", - tx_disp_sel_3 => "00", - tx_crc_init_3 => "00", - word_align_en_3 => '1',--word_align_en(3+bit_index*4),--'1', - mca_align_en_3 => '0', - felb_3 => '0', - lsm_en_3 => '0', - mca_resync_01 => '0', - mca_resync_23 => '0', - quad_rst => '0', - serdes_rst => '0', - rxa_pclk => rx_clk_i(0+bit_index*4), - rxb_pclk => rxb_pclk_a(bit_index), - hdoutp_0 => SFP_OUT_P(bit_index*4+0), - hdoutn_0 => SFP_OUT_N(bit_index*4+0), - ref_0_sclk => open, - rx_0_sclk => open, - rxd_0 => rxd_i(15+bit_index*64 downto 0+bit_index*64), - rx_k_0 => rx_k_i(1+bit_index*8 downto 0+bit_index*8), - rx_disp_err_detect_0 => open, --rx_disp_err_detect_0_a, - rx_cv_detect_0 => cv_i(1+bit_index*8 downto 0+bit_index*8), - rx_crc_eop_0 => open, - lsm_status_0 => open, - hdoutp_1 => SFP_OUT_P(bit_index*4+1), - hdoutn_1 => SFP_OUT_N(bit_index*4+1), - ref_1_sclk => open, - rx_1_sclk => rx_clk_i(1+bit_index*4), - rxd_1 => rxd_i(31+bit_index*64 downto 16+bit_index*64), - rx_k_1 => rx_k_i(3+bit_index*8 downto 2+bit_index*8), - rx_disp_err_detect_1 => open, --rx_disp_err_detect_1_a, - rx_cv_detect_1 => cv_i(3+bit_index*8 downto 2+bit_index*8), - rx_crc_eop_1 => open, - lsm_status_1 => open, - hdoutp_2 => SFP_OUT_P(bit_index*4+2), - hdoutn_2 => SFP_OUT_N(bit_index*4+2), - ref_2_sclk => open, - rx_2_sclk => rx_clk_i(2+bit_index*4), - rxd_2 => rxd_i(47+bit_index*64 downto 32+bit_index*64), - rx_k_2 => rx_k_i(5+bit_index*8 downto 4+bit_index*8), - rx_disp_err_detect_2 => open, --rx_disp_err_detect_2_a, - rx_cv_detect_2 => cv_i(5+bit_index*8 downto 4+bit_index*8), - rx_crc_eop_2 => open, - lsm_status_2 => open, - hdoutp_3 => SFP_OUT_P(bit_index*4+3), - hdoutn_3 => SFP_OUT_N(bit_index*4+3), - ref_3_sclk => open, - rx_3_sclk => rx_clk_i(3+bit_index*4), - rxd_3 => rxd_i(63+bit_index*64 downto 48+bit_index*64), - rx_k_3 => rx_k_i(7+bit_index*8 downto 6+bit_index*8), - rx_disp_err_detect_3 => open, --rx_disp_err_detect_3_a, - rx_cv_detect_3 => cv_i(7+bit_index*8 downto 6+bit_index*8), - rx_crc_eop_3 => open, - lsm_status_3 => open, - mca_aligned_01 => open, --mca_aligned_01_i, - mca_inskew_01 => open, --mca_inskew_01_i, - mca_outskew_01 => open, --mca_outskew_01_i, - mca_aligned_23 => open, --mca_aligned_23_i, - mca_inskew_23 => open, --mca_inskew_23_i, - mca_outskew_23 => open, --mca_outskew_23_i, - ref_pclk => ref_pclk(bit_index) - ); - end generate QUAD_GENERATE; - -- word_align_en <= not rx_rst_i; ---sim-- SIMULATION_CONNECTION: for i in 0 to HOW_MANY_CHANNELS-1 generate ---sim-- rx_k_sim(i*2) <= not OPT_DATA_VALID_IN(i); ---sim-- rx_k_sim(i*2+1) <= '0'; ---sim-- OPT_DATA_VALID_OUT(i) <= not tx_k_sim(i*2); ---sim-- rx_clk_sim <= (others => LVDS_CLK_200P); ---sim-- ref_pclk_sim <= (others => LVDS_CLK_200P); ---sim-- cv_sim <= (others => '0'); ---sim-- end generate SIMULATION_CONNECTION; - FLEXI_PCS_INT : flexi_PCS_synch - generic map ( - HOW_MANY_CHANNELS => HOW_MANY_CHANNELS, - SYSTEM => 1) - port map ( - RESET => global_reset_i, - SYSTEM_CLK => LVDS_CLK_200P, - TX_CLK => ref_pclk, --no_sim-- ---sim-- TX_CLK => ref_pclk_sim, - RX_CLK => rx_clk_i, --no_sim-- ---sim-- RX_CLK => rx_clk_sim, - RXD => rxd_i, --no_sim-- ---sim-- RXD => OPT_DATA_IN, - RX_K => rx_k_i, --no_sim-- ---sim-- RX_K => rx_k_sim, - RX_RST => rx_rst_i, - CV => cv_i, --no_sim-- ---sim-- CV => cv_sim, - TXD => txd_synch_i, --no_sim-- ---sim-- TXD => OPT_DATA_OUT, - TX_K => tx_k_i, --no_sim-- ---sim-- TX_K => tx_k_sim, - MEDIA_STATUS => media_status_i, - MEDIA_CONTROL => open, - MED_DATAREADY_IN => med_dataready_in_i, - MED_DATA_IN => med_data_in_i, - MED_READ_OUT => med_read_out_i, - MED_DATA_OUT => med_data_out_i, - MED_DATAREADY_OUT => med_dataready_out_i, - MED_READ_IN => med_read_in_i, - MED_PACKET_NUM_IN => med_packet_num_in_i, - MED_PACKET_NUM_OUT => med_packet_num_out_i, - MED_STAT_OP => med_stat_op_i, - MED_CTRL_OP => med_ctrl_op_i, - LINK_DEBUG => link_debug_i - ); - - ADO_TTL(15 downto 0) <= link_debug_i(7 downto 4) & med_dataready_out_i(0) & med_packet_num_out_i(2 downto 0) & med_data_out_i(7 downto 0);--link_debug_i(15 downto 0); - ADO_TTL(34 downto 19) <= link_debug_i(23 downto 22) & LVDS_CLK_200P & med_read_out_i(0) & med_dataready_in_i(0) & med_packet_num_in_i(2 downto 0) & med_data_in_i(7 downto 0);--link_debug_i(31 downto 16); - - - SIMPLE_HUB_GEN : if trb_net_enable = 0 and OPT_TEST_MODE = 0 generate - - SIMPLE_HUB_INST : simple_hub - generic map ( - HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) - port map ( - CLK => LVDS_CLK_200P, - RESET => global_reset_i, - DATA_IN => med_data_out_i, --- DATA_IN => med_data_out_i_test, - DATA_OUT => med_data_in_i, - DATA_IN_VALID => med_dataready_out_i, - SEND_DATA => med_dataready_in_i, --- SEND_DATA => med_dataready_in_i_test, - ENABLE_CHANNELS => fpga_register_06_i(15 downto 0), - READ_DATA => med_read_in_i, - HUB_DEBUG => hub_debug_i - ); - - end generate SIMPLE_HUB_GEN; - - FREE_COUNTER_INST: up_down_counter - generic map ( - NUMBER_OF_BITS => 17) - port map ( - CLK => LVDS_CLK_200P, - RESET => '0', - COUNT_OUT => free_counter, - UP_IN => '1', - DOWN_IN => '0'); - - WAIT_COUNTER_INST: up_down_counter - generic map ( - NUMBER_OF_BITS => 32) - port map ( - CLK => LVDS_CLK_200P, - RESET => '0', - COUNT_OUT => wait_counter, - UP_IN => wait_counter_up, - DOWN_IN => '0'); - - wait_counter_up <= '1' when wait_counter(31) = '0' else '0'; - - ENABLE_OPT_TEST : if OPT_TEST_MODE = 1 generate - - SEND_COUNTER: process (LVDS_CLK_200P, global_reset_i) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - med_dataready_in_i <= (others => '0'); - med_data_in_i <= (others => '0'); --- elsif med_stat_op_i(9)='1' or med_stat_op_i(24)='1' or med_stat_op_i(40)='1' or med_stat_op_i(56)='1' then - -- elsif link_debug_i(3 downto 0) = x"a" and link_debug_i(35 downto 32) > 10 then - elsif wait_counter(31) = '1' then - - med_dataready_in_i <= free_counter(16) & free_counter(16) &free_counter(16) &free_counter(16); - med_data_in_i <= free_counter(15 downto 0) & free_counter(15 downto 0) & free_counter(15 downto 0) & free_counter(15 downto 0); - else - med_dataready_in_i <= (others => '0'); - med_data_in_i <= (others => '0'); - end if; - end if; - end process SEND_COUNTER; - med_read_in_i <= (others => '1'); --- med_data_in_i <= med_data_out_i; --- med_dataready_in_i <= med_dataready_out_i; - end generate ENABLE_OPT_TEST; - - ENABLE_TRB_NET: if trb_net_enable = 1 generate - - HUB_API: trb_net16_hub_base - generic map( - MII_NUMBER => HOW_MANY_CHANNELS - ) - port map ( - CLK => LVDS_CLK_200P, - RESET => global_reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_in_i, - MED_DATA_OUT => med_data_in_i, - MED_PACKET_NUM_OUT => med_packet_num_in_i, - MED_READ_IN => med_read_out_i, - MED_DATAREADY_IN => med_dataready_out_i, - MED_DATA_IN => med_data_out_i, - MED_PACKET_NUM_IN => med_packet_num_out_i, - MED_READ_OUT => med_read_in_i, - MED_STAT_OP => med_stat_op_i, - MED_CTRL_OP => med_ctrl_op_i, - INT_INIT_DATAREADY_OUT => open, - INT_INIT_DATA_OUT => open, - INT_INIT_PACKET_NUM_OUT => open, - INT_INIT_READ_IN => (others => '1'), - INT_INIT_DATAREADY_IN => (others => '0'), - INT_INIT_DATA_IN => (others => '0'), - INT_INIT_PACKET_NUM_IN => (others => '0'), - INT_INIT_READ_OUT => open, - INT_REPLY_DATAREADY_OUT => open, - INT_REPLY_DATA_OUT => open, - INT_REPLY_PACKET_NUM_OUT => open, - INT_REPLY_READ_IN => (others => '1'), - INT_REPLY_DATAREADY_IN => (others => '0'), - INT_REPLY_DATA_IN => (others => '0'), - INT_REPLY_PACKET_NUM_IN => (others => '0'), - INT_REPLY_READ_OUT => open, - ONEWIRE => FS_PE_11, - HUB_STAT_CHANNEL => hub_stat_channel_i, - HUB_STAT_GEN => hub_stat_gen_i, - MPLEX_CTRL => mplex_ctrl_i, - MPLEX_STAT => open, - REGIO_EXT_REG_DATA_IN => (others => '0'), - REGIO_EXT_REG_DATA_OUT => open, - REGIO_EXT_REG_WRITE_IN => '0', - REGIO_EXT_REG_ADDR_IN => (others => '0'), - STAT_DEBUG => open, - CTRL_DEBUG => (others => '0') - ); - - end generate ENABLE_TRB_NET; - - ETRAX_RW_DATA_INTERFACE : etrax_interfacev2 - generic map ( - RW_SYSTEM => 2) - port map ( - CLK => LVDS_CLK_200P, - RESET => global_reset_i, - DATA_BUS => (others => '0'), - ETRAX_DATA_BUS_B => open,--(others => '0'), - ETRAX_DATA_BUS_B_17 => '0', - ETRAX_DATA_BUS_C => open,--(others => '0'), - ETRAX_DATA_BUS_E => FS_PE(9 downto 8), - DATA_VALID => '0', - ETRAX_BUS_BUSY => '0', - ETRAX_IS_READY_TO_READ => open, - TDC_TCK => open, - TDC_TDI => open, - TDC_TMS => open, - TDC_TRST => open, - TDC_TDO => '0', - TDC_RESET => open, - EXTERNAL_ADDRESS => open, - EXTERNAL_DATA_OUT => open, - EXTERNAL_DATA_IN => x"ddbbccaa",--external_data_in_i, - EXTERNAL_ACK => external_ack_i, - EXTERNAL_VALID => '0',--external_valid_i, - EXTERNAL_MODE => external_mode_i, - FPGA_REGISTER_00 => fpga_register_00_i, - FPGA_REGISTER_01 => fpga_register_01_i, - FPGA_REGISTER_02 => fpga_register_02_i, - FPGA_REGISTER_03 => fpga_register_03_i, - FPGA_REGISTER_04 => fpga_register_04_i, - FPGA_REGISTER_05 => fpga_register_05_i, - FPGA_REGISTER_06 => fpga_register_06_i, - FPGA_REGISTER_07 => fpga_register_07_i, - FPGA_REGISTER_08 => fpga_register_08_i, - FPGA_REGISTER_09 => fpga_register_09_i, - FPGA_REGISTER_0A => fpga_register_0A_i, - FPGA_REGISTER_0B => fpga_register_0B_i, - FPGA_REGISTER_0C => fpga_register_0C_i, - FPGA_REGISTER_0D => fpga_register_0D_i, - FPGA_REGISTER_0E => fpga_register_0E_i, - -- EXTERNAL_RESET => open, - LVL2_VALID => '0'); - fpga_register_00_i <= x"0000"& lok_i; - fpga_register_01_i <= hub_debug_i; - fpga_register_02_i <= link_debug_i(31 downto 0); - fpga_register_03_i <= link_debug_i(63 downto 32); - fpga_register_04_i <= rxd_i(31 downto 0); - fpga_register_0A_i <= rxd_i(63 downto 32); --- fpga_register_02_i <= link_debug_i(95 downto 64); --- fpga_register_03_i <= link_debug_i(127 downto 96); --- fpga_register_04_i <= rxd_i(95 downto 64); --- fpga_register_0A_i <= rxd_i(127 downto 96); - fpga_register_0B_i <= conv_std_logic_vector(VERSION_NUMBER_TIME,32); - fpga_register_0C_i <= link_debug_i(95 downto 64); - fpga_register_0D_i <= link_debug_i(127 downto 96); --- -- fpga_register_08_i <= rxd_i(63 downto 32); --- fpga_register_0a_i(15 downto 0) <= cv_i(7 downto 0) & rx_k_i(3 downto 0) & "0000"; - - - - COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i ) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - fpga_register_05_i <= (others => '0'); - elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"1" then - fpga_register_05_i <= fpga_register_05_i + 1; - end if; - end if; - end process COUNT_LVL1_START; - --- COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i ) --- begin --- if rising_edge(LVDS_CLK_200P) then --- if global_reset_i = '1' then --- fpga_register_08_i <= (others => '0'); --- elsif med_data_ready_in_i(1) = '1' and med_data_in_i(31 downto 28) = x"1" then --- fpga_register_08_i <= fpga_register_08_i + 1; --- end if; --- end if; --- end process COUNT_LVL1_SEND; - - COUNT_LVL1_SEND_a: process (LVDS_CLK_200P, global_reset_i ) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - fpga_register_09_i <= (others => '0'); - elsif med_dataready_in_i(1) = '1' then - fpga_register_09_i <= fpga_register_08_i + 1; - end if; - end if; - end process COUNT_LVL1_SEND_a; - - COUNT_LVL1_END: process (LVDS_CLK_200P, global_reset_i ) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - fpga_register_07_i <= (others => '0'); - elsif med_dataready_out_i(1) = '1' and med_data_out_i(31 downto 28) = x"1" then - fpga_register_07_i <= fpga_register_07_i + 1; - end if; - end if; - end process COUNT_LVL1_END; - - TX_DIS_g : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate - begin - TX_DIS(synch_fsm_state+1) <= '0'; - end generate; - - TX_DIS_g1 : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate - begin - WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate - TX_DIS(16-not_connected) <= '1'; - end generate WHEN_NOT_ALL_EN; - end generate; - ---------------------------------------------------------------------------- --- setting LED ---------------------------------------------------------------------------- - - --correct this for channels 11-8 - mirrored due to schematics -- also - --adressing of sfps !!! - SYNCH_EXT_SIGNAL: process (LVDS_CLK_200P) - begin - if rising_edge(LVDS_CLK_200P) then - if global_reset_i = '1' then - sfp_los_synch <= (others => '0'); - else - sfp_los_synch <= SFP_LOS; - end if; - end if; - end process SYNCH_EXT_SIGNAL; - LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate - begin - -- lok_i(synch_fsm_state+1) <= not link_debug_i(2+synch_fsm_state*31); - lok_i(synch_fsm_state+1) <= med_stat_op_i(9 + synch_fsm_state*16); - media_status_i(synch_fsm_state*16) <= SFP_LOS(synch_fsm_state+1); - end generate LOK_STATUS_DIOD_EN; - --- LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate --- begin --- hub_register_00_i(synch_fsm_state) <= link_debug_i(2+synch_fsm_state*31); --- end generate LOK_STATUS_REGISTER_0; - --- LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate --- begin --- hub_register_01_i(synch_fsm_state) <= link_debug_i(2+synch_fsm_state*31+8*16); --- end generate LOK_STATUS_REGISTER_1; - - LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate - begin - WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate - lok_i(16-not_connected) <= '1'; - end generate WHEN_NOT_ALL_EN; - end generate LOK_STATUS_DIOD_DIS; - - LOK <= lok_i; - IPLL <= '0'; - OPLL <= '0'; - DBAD <= '1'; - DGOOD <= '1'; - DINT <= '0'; - DWAIT <= global_reset_i; - - CV_COUNTERaaa: process (LVDS_CLK_200P, global_reset_i) - begin - if rising_edge(LVDS_CLK_200P) then -- rising clock edge - if global_reset_i = '1' then -- asynchronous reset (active low) - cv_counter <= (others => '0'); - else - cv_counter <= cv_counter + 1; - end if; - end if; - end process CV_COUNTERaaa; - CV_COUNTERaab: process (ref_pclk(0), global_reset_i) - begin - if rising_edge(ref_pclk(0)) then -- rising clock edge - if global_reset_i = '1' then -- asynchronous reset (active low) - cv_countera <= (others => '0'); - else - cv_countera <= cv_countera + 1; - end if; - end if; - end process CV_COUNTERaab; --- RT(8) <= cv_counter(23); --- RT(9) <= med_read_in_i(0); --- RT(16 downto 10) <= link_debug_i(7 downto 1); --- RT(2) <= flexi_pcs_ref_clk;--cv_counter(0); --- RT(1) <= not switch_rx_clk;--ref_pclk(0); - --- RT(3) <= LVDS_CLK_200P; - --- RT(4) <= rx_k_i(0); - --- RT(5) <= med_dataready_out_i(0);--serdes_ref_clk; --- RT(6) <= med_data_out_i(0);--serdes_ref_clks; --- RT(7) <= med_data_out_i(1);--serdes_ref_lock; - RT <= (others => '1'); -end hub; - diff --git a/optical_link/hub_1.xcf b/optical_link/hub_1.xcf deleted file mode 100644 index 350e53a..0000000 --- a/optical_link/hub_1.xcf +++ /dev/null @@ -1,99 +0,0 @@ - - - - - - JTAG - - 1 - NA - Generic JTAG Device - JTAG-NOP - All - JTAG-NOP - - 10 - 1111111111 - 1 - 0 - - Bypass - - - - 2 - hub - Lattice - LatticeSCM - LFSCM3GA25E - 0x0a812157 - 1020-ball FFBGA - LFSCM3GA25EP1-XXFF1020 - - 8 - 11111111 - 1 - 0 - - /home/marek/trbnet/optical_link/workdir/hub.bit - /home/marek/.isplever_lin1/ispvmsystem/Database/xpga/sc/lfsc3ga25e.msk - 3/31/2009 22:28:11 - Fast Program - - - - 3 - power - NA - Generic JTAG Device - JTAG-NOP - All - JTAG-NOP - - 4 - 1111 - 1 - 0 - - Bypass - - - - - SEQUENTIAL - ENTIRED CHAIN - No Override - TLR - TLR - - - - TMS LOW; - TCK LOW; - TDI LOW; - TDO LOW; - CableEN HIGH; - - - diff --git a/optical_link/hub_syn.prj b/optical_link/hub_syn.prj deleted file mode 100644 index 10f1458..0000000 --- a/optical_link/hub_syn.prj +++ /dev/null @@ -1,112 +0,0 @@ -#-- Synopsys, Inc. -#-- Version 9.6L2 -#-- Project file /home/marek/trbnet/optical_link/hub_syn.prj -#-- Written on Thu Apr 2 10:51:38 2009 - - -#add_file options -add_file -vhdl -lib work "./version.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_addresses.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_hub_func.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x16.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x32.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/lattice_scm_fifo_18x64.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/lattice/scm/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_regIO.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_api_base.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_ibuf.vhd" -add_file -vhdl -lib work "./simple_hub.vhd" -add_file -vhdl -lib work "./cross_clk.vhd" -add_file -vhdl -lib work "/home/marek/trbv2/etrax_interfacev2.vhd" -add_file -vhdl -lib work "./simpleupcounter_32bit.vhd" -add_file -vhdl -lib work "./hub_etrax_interface.vhd" -add_file -vhdl -lib work "./hub.vhd" -add_file -vhdl -lib work "./f_divider.vhd" -add_file -vhdl -lib work "./simpleupcounter_16bit.vhd" -add_file -vhdl -lib work "./simpleupcounter_8bit.vhd" -add_file -vhdl -lib work "./flexi_PCS_synch.vhd" -add_file -vhdl -lib work "./flexi_PCS_channel_synch.vhd" -add_file -vhdl -lib work "./flexi_PCS_fifo_LUT.vhd" -add_file -vhdl -lib work "./flexi_PCS_fifo_EBR.vhd" -add_file -vhdl -lib work "./serdes_fpga_ref_clk.vhd" -add_file -vhdl -lib work "./pll_ref.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_dummy_fifo.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_pattern_gen.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_priority_encoder.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_hub_base.vhd" -add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_hub_logic.vhd" -add_file -vhdl -lib work "../basics/ram_16x8_dp.vhd" -add_file -vhdl -lib work "../basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../basics/ram_dp_rw.vhd" -add_file -vhdl -lib work "../basics/ram_dp.vhd" -add_file -vhdl -lib work "../basics/ram_true_dp.vhd" -add_file -vhdl -lib work "../basics/ram.vhd" -add_file -vhdl -lib work "../basics/rom_16x8.vhd" -add_file -vhdl -lib work "../basics/rom_16x16.vhd" -add_file -vhdl -lib work "../basics/rom_18x128.vhd" -add_file -vhdl -lib work "../basics/signal_sync.vhd" -add_file -vhdl -lib work "../basics/wide_adder_17x16.vhd" -add_file -vhdl -lib work "../basics/wide_adder.vhd" -add_file -vhdl -lib work "../trb_net16_term_buf.vhd" -add_file -vhdl -lib work "../../trbv2/up_down_counter.vhd" -add_file -vhdl -lib work "../trb_net16_hub_ipu_logic.vhd" - - -#implementation: "workdir" -impl -add workdir -type fpga - -#device options -set_option -technology LATTICE-SCM -set_option -part LFSCM3GA25EP1 -set_option -package FF1020C -set_option -speed_grade -5 -set_option -part_companion "" - -#compilation/mapping options -set_option -default_enum_encoding onehot -set_option -resource_sharing 1 -set_option -top_module "hub" - -#map options -set_option -frequency 110.000 -set_option -vendor_xcompatible_mode 0 -set_option -vendor_xcompatible_mode 0 -set_option -fanout_limit 100 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 0 -set_option -fixgatedclocks 0 -set_option -fixgeneratedclocks 3 -set_option -force_gsr no - - -#sequential_optimizations options -set_option -symbolic_fsm_compiler 1 - -#simulation options -set_option -write_verilog 0 -set_option -write_vhdl 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 0 - -#set result format/file last -project -result_file "./workdir/hub.edf" - -# -#implementation attributes - -set_option -vlog_std v2001 -set_option -synthesis_onoff_pragma 0 -set_option -project_relative_includes 1 -impl -active "workdir" diff --git a/optical_link/hub_tb.vhd b/optical_link/hub_tb.vhd deleted file mode 100644 index 3933fdd..0000000 --- a/optical_link/hub_tb.vhd +++ /dev/null @@ -1,122 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; - -entity hub_tb is - - port ( - LVDS_CLK_200P : in std_logic; - LVDS_CLK_200N : in std_logic; - SERDES_200N : in std_logic; - SERDES_200P : in std_logic; - ADO_TTL : inout std_logic_vector(46 downto 0); - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0); - AAAAAAAA : in std_logic); -end hub_tb; - -architecture hub_tb of hub_tb is - -signal LVDS_CLK_200P_i : std_logic; -signal LVDS_CLK_200N_i : std_logic; -signal SERDES_200N_i : std_logic; -signal SERDES_200P_i : std_logic; -signal ADO_TTL_i : std_logic_vector(46 downto 0); -signal DBAD_i : std_logic; -signal DGOOD_i : std_logic; -signal DINT_i : std_logic; -signal DWAIT_i : std_logic; -signal LOK_i : std_logic_vector(16 downto 1); -signal RT_i : std_logic_vector(16 downto 1); -signal TX_DIS_i : std_logic_vector(16 downto 1); -signal IPLL_i : std_logic; -signal OPLL_i : std_logic; -signal SFP_INP_N_i : std_logic_vector(15 downto 0); -signal SFP_INP_P_i : std_logic_vector(15 downto 0); -signal SFP_OUT_N_i : std_logic_vector(15 downto 0); -signal SFP_OUT_P_i : std_logic_vector(15 downto 0); - -component hub - port ( - LVDS_CLK_200P : in std_logic; --- LVDS_CLK_200N : in std_logic; --- SERDES_200N : in std_logic; --- SERDES_200P : in std_logic; - ADO_TTL : inout std_logic_vector(46 downto 0); - DBAD : out std_logic; - DGOOD : out std_logic; - DINT : out std_logic; - DWAIT : out std_logic; - LOK : out std_logic_vector(16 downto 1); - RT : out std_logic_vector(16 downto 1); - TX_DIS : out std_logic_vector(16 downto 1); - IPLL : out std_logic; - OPLL : out std_logic; - SFP_INP_N : in std_logic_vector(15 downto 0); - SFP_INP_P : in std_logic_vector(15 downto 0); - SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0); - FS_PE_11 : inout std_logic; - --------------------------------------------------------------------------- - -- sim - --------------------------------------------------------------------------- - OPT_DATA_IN : in std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0); - OPT_DATA_OUT : out std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0); - OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0) - - - ); -end component; - - -begin -- of hub_tb - HUB_SIM: hub - port map ( - LVDS_CLK_200P => LVDS_CLK_200P_i, - ADO_TTL => ADO_TTL_i, - DBAD => DBAD_i, - DGOOD => DGOOD_i, - DINT => DINT_i, - DWAIT => DWAIT_i, - LOK => LOK_i, - RT => RT_i, - TX_DIS => TX_DIS_i, - IPLL => IPLL_i, - OPLL => OPLL_i, - SFP_INP_N => SFP_INP_N_i, - SFP_INP_P => SFP_INP_P_i, - SFP_OUT_N => SFP_OUT_N_i, - SFP_OUT_P => SFP_OUT_P_i - FS_PE_11 => - OPT_DATA_IN => - OPT_DATA_OUT => - OPT_DATA_VALID_IN => - OPT_DATA_VALID_OUT => - - clock_gclk : process - begin - SERDES_200P_i <= '0'; - SERDES_200N_i <= '1'; - wait for 5 ns; - SERDES_200P_i <= '1'; - SERDES_200N_i <= '0'; - wait for 5 ns; - end process; -end hub_tb; diff --git a/optical_link/impact_batch_hub.txt b/optical_link/impact_batch_hub.txt deleted file mode 100644 index 84cf5a7..0000000 --- a/optical_link/impact_batch_hub.txt +++ /dev/null @@ -1,5 +0,0 @@ -setMode -bs -setCable -port stapl -file "hub_chain.stapl" -addDevice -p 1 -file "hub_1.svf" -Play -quit diff --git a/optical_link/pll_ref.vhd b/optical_link/pll_ref.vhd deleted file mode 100644 index 48256f8..0000000 --- a/optical_link/pll_ref.vhd +++ /dev/null @@ -1,167 +0,0 @@ --- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) --- Module Version: 3.6 ---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n pll_ref -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 200 -nfreq 100 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e - --- Thu Nov 29 18:28:19 2007 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library SCM; -use SCM.COMPONENTS.all; --- synopsys translate_on - -entity pll_ref is - generic ( - SMI_OFFSET : in String := "0x410" - ); - port ( - clk: in std_logic; - clkop: out std_logic; - clkos: out std_logic; - lock: out std_logic); - attribute dont_touch : string; - attribute dont_touch of pll_ref : entity is "true"; -end pll_ref; - -architecture Structure of pll_ref is - - -- internal signal declarations - signal scuba_vlo: std_logic; - signal scuba_vhi: std_logic; - signal clkos_t: std_logic; - signal clkop_t: std_logic; - signal clk_t: std_logic; - - attribute module_type : string; - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component EHXPLLA - generic (SMI_OFFSET : in String - -- synopsys translate_off - ; GSR : in String; CLKOS_DIV : in Integer; - CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; - CLKI_DIV : in Integer; CLKOS_FDEL : in Integer; - CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer; - CLKOS_MODE : in String; CLKOP_MODE : in String; - PHASEADJ : in Integer; CLKOS_VCODEL : in Integer - -- synopsys translate_on - ); - port (SMIADDR9: in std_logic; SMIADDR8: in std_logic; - SMIADDR7: in std_logic; SMIADDR6: in std_logic; - SMIADDR5: in std_logic; SMIADDR4: in std_logic; - SMIADDR3: in std_logic; SMIADDR2: in std_logic; - SMIADDR1: in std_logic; SMIADDR0: in std_logic; - SMIRD: in std_logic; SMIWR: in std_logic; - SMICLK: in std_logic; SMIWDATA: in std_logic; - SMIRSTN: in std_logic; CLKI: in std_logic; - CLKFB: in std_logic; RSTN: in std_logic; - CLKOS: out std_logic; CLKOP: out std_logic; - LOCK: out std_logic; CLKINTFB: out std_logic; - SMIRDATA: out std_logic); - end component; - attribute module_type of EHXPLLA : component is "EHXPLLA"; - attribute ip_type : string; - attribute FREQUENCY_PIN_CLKOS : string; - attribute FREQUENCY_PIN_CLKOP : string; - attribute FREQUENCY_PIN_CLKI : string; - attribute VCO_LOWERFREQ : string; - attribute GMCFREQSEL : string; - attribute GSR : string; - attribute SPREAD_DIV2 : string; - attribute SPREAD_DIV1 : string; - attribute SPREAD_DRIFT : string; - attribute SPREAD : string; - attribute CLKFB_FDEL : string; - attribute CLKI_FDEL : string; - attribute CLKFB_PDEL : string; - attribute CLKI_PDEL : string; - attribute LF_RESISTOR : string; - attribute LF_IX5UA : string; - attribute CLKOS_FDEL : string; - attribute CLKOS_VCODEL : string; - attribute PHASEADJ : string; - attribute CLKOS_MODE : string; - attribute CLKOP_MODE : string; - attribute CLKOS_DIV : string; - attribute CLKOP_DIV : string; - attribute CLKFB_DIV : string; - attribute CLKI_DIV : string; - attribute ip_type of pll_ref_0_0 : label is "EHXPLLA"; - attribute FREQUENCY_PIN_CLKOS of pll_ref_0_0 : label is "100.000000"; - attribute FREQUENCY_PIN_CLKOP of pll_ref_0_0 : label is "200.000000"; - attribute FREQUENCY_PIN_CLKI of pll_ref_0_0 : label is "100.000000"; - attribute VCO_LOWERFREQ of pll_ref_0_0 : label is "DISABLED"; - attribute GMCFREQSEL of pll_ref_0_0 : label is "HIGH"; - attribute GSR of pll_ref_0_0 : label is "DISABLED"; - attribute SPREAD_DIV2 of pll_ref_0_0 : label is "2"; - attribute SPREAD_DIV1 of pll_ref_0_0 : label is "2"; - attribute SPREAD_DRIFT of pll_ref_0_0 : label is "1"; - attribute SPREAD of pll_ref_0_0 : label is "DISABLED"; - attribute CLKFB_FDEL of pll_ref_0_0 : label is "0"; - attribute CLKI_FDEL of pll_ref_0_0 : label is "0"; - attribute CLKFB_PDEL of pll_ref_0_0 : label is "DEL0"; - attribute CLKI_PDEL of pll_ref_0_0 : label is "DEL0"; - attribute LF_RESISTOR of pll_ref_0_0 : label is "0b111010"; - attribute LF_IX5UA of pll_ref_0_0 : label is "31"; - attribute CLKOS_FDEL of pll_ref_0_0 : label is "0"; - attribute CLKOS_VCODEL of pll_ref_0_0 : label is "0"; - attribute PHASEADJ of pll_ref_0_0 : label is "0"; - attribute CLKOS_MODE of pll_ref_0_0 : label is "DIV"; - attribute CLKOP_MODE of pll_ref_0_0 : label is "DIV"; - attribute CLKOS_DIV of pll_ref_0_0 : label is "6"; - attribute CLKOP_DIV of pll_ref_0_0 : label is "3"; - attribute CLKFB_DIV of pll_ref_0_0 : label is "2"; - attribute CLKI_DIV of pll_ref_0_0 : label is "1"; - attribute syn_keep : boolean; - attribute syn_noprune : boolean; - attribute syn_noprune of Structure : architecture is true; - -begin - -- component instantiation statements - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - pll_ref_0_0: EHXPLLA - generic map (SMI_OFFSET=> SMI_OFFSET - -- synopsys translate_off - , GSR=> "DISABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0, - CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV", - CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 3, CLKFB_DIV=> 2, - CLKI_DIV=> 1 - -- synopsys translate_on - ) - port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, - SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, - SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, - SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, - SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, - SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, - SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t, - RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, - CLKINTFB=>open, SMIRDATA=>open); - - clkos <= clkos_t; - clkop <= clkop_t; - clk_t <= clk; -end Structure; - --- synopsys translate_off -library SCM; -configuration Structure_CON of pll_ref is - for Structure - for all:VHI use entity SCM.VHI(V); end for; - for all:VLO use entity SCM.VLO(V); end for; - for all:EHXPLLA use entity SCM.EHXPLLA(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/optical_link/readme b/optical_link/readme deleted file mode 100644 index 463360a..0000000 --- a/optical_link/readme +++ /dev/null @@ -1,14 +0,0 @@ -to run all: - -mkdir workdir; -cd workdir; -ln -s ../serdes_fpga_ref_clk.txt serdes_fpga_ref_clk.txt #configuration file for serdes in LATTICE -ln -s ../hub.lpf hub.lpf #user constraints -cd .. -. /your/xilinx/patch/settings.sh #set xilinx enviroment -. setup_env #check paths for LATTICE -#change in hub_1.xcf to correct path of out .bit file -# /your/project/path/workdir/hub.bit or produce it in isp - this for chain -#FPGA - LATTICE, in future there will be no FPGA on trbv2 for hub -./compile_hub.pl #run main script - diff --git a/optical_link/serdes_fpga_ref_clk.txt b/optical_link/serdes_fpga_ref_clk.txt deleted file mode 100644 index 05b6dec..0000000 --- a/optical_link/serdes_fpga_ref_clk.txt +++ /dev/null @@ -1,62 +0,0 @@ - - -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCS quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCS quad to the final design requirements. -# channel_0 is in "8b10b" mode -# channel_1 is in "8b10b" mode -# channel_2 is in "8b10b" mode -# channel_3 is in "8b10b" mode - -ch0 13 03 # Powerup Channel -ch0 00 00 -ch1 13 03 # Powerup Channel -ch1 00 00 -ch2 13 03 # Powerup Channel -ch2 00 00 -ch3 13 03 # Powerup Channel -ch3 00 00 -quad 00 00 -quad 01 E4 -quad 28 40 # Reference clock multiplier -quad 29 11 # FPGA sourced refclk -quad 02 00 # ref_pclk source is ch0 -quad 04 00 # MCA enable 4 channels - -quad 18 10 # 8b10b Mode -quad 14 FF # Word Alignment Mask -quad 15 7c # +ve K -quad 16 b6 # -ve K -#quad 16 83 # -ve K -quad 17 36 - -quad 19 8C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit - -#quad 1e 01 #SOP EOP only 1 word 24.04.2008 -#quad 1f ff -#quad 20 7c -#quad 21 7c -#quad 22 5 -#quad 23 7c -#quad 24 7c -#quad 25 5 - - -ch0 14 90 # 16% pre-emphasis -ch0 15 10 # +6dB equalization -ch1 14 90 # 16% pre-emphasis -ch1 15 10 # +6dB equalization -ch2 14 90 # 16% pre-emphasis -ch2 15 10 # +6dB equalization -ch3 14 90 # 16% pre-emphasis -ch3 15 10 # +6dB equalization - -# These lines must appear last in the autoconfig file. These lines apply the correct -# reset sequence to the PCS block upon bitstream configuration -quad 41 00 # de-assert serdes_rst -quad 40 ff # assert datapath reset for all channels -quad 40 00 # de-assert datapath reset for all channels - - - diff --git a/optical_link/serdes_fpga_ref_clk.vhd b/optical_link/serdes_fpga_ref_clk.vhd deleted file mode 100644 index 36d920f..0000000 --- a/optical_link/serdes_fpga_ref_clk.vhd +++ /dev/null @@ -1,2437 +0,0 @@ - - --- channel_0 is in "8b10b" mode --- channel_1 is in "8b10b" mode --- channel_2 is in "8b10b" mode --- channel_3 is in "8b10b" mode - ---synopsys translate_off - -library pcsa_mti_work; -use pcsa_mti_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSA is -GENERIC( - CONFIG_FILE : String := "serdes_fpga_ref_clk.txt" - ); -port ( - HDINP0 : in std_logic; - HDINN0 : in std_logic; - HDINP1 : in std_logic; - HDINN1 : in std_logic; - HDINP2 : in std_logic; - HDINN2 : in std_logic; - HDINP3 : in std_logic; - HDINN3 : in std_logic; - HDOUTP0 : out std_logic; - HDOUTN0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTP3 : out std_logic; - HDOUTN3 : out std_logic; - REFCLKP : in std_logic; - REFCLKN : in std_logic; - RXREFCLKP : in std_logic; - RXREFCLKN : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_MACRO_RST : in std_logic; - - FFC_LANE_TX_RST0 : in std_logic; - FFC_LANE_TX_RST1 : in std_logic; - FFC_LANE_TX_RST2 : in std_logic; - FFC_LANE_TX_RST3 : in std_logic; - - FFC_LANE_RX_RST0 : in std_logic; - FFC_LANE_RX_RST1 : in std_logic; - FFC_LANE_RX_RST2 : in std_logic; - FFC_LANE_RX_RST3 : in std_logic; - - FFC_PCIE_EI_EN_0 : in std_logic; - FFC_PCIE_EI_EN_1 : in std_logic; - FFC_PCIE_EI_EN_2 : in std_logic; - FFC_PCIE_EI_EN_3 : in std_logic; - - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - - FFC_PCIE_TX_0 : in std_logic; - FFC_PCIE_TX_1 : in std_logic; - FFC_PCIE_TX_2 : in std_logic; - FFC_PCIE_TX_3 : in std_logic; - - FFC_PCIE_RX_0 : in std_logic; - FFC_PCIE_RX_1 : in std_logic; - FFC_PCIE_RX_2 : in std_logic; - FFC_PCIE_RX_3 : in std_logic; - - FFC_SD_0 : in std_logic; - FFC_SD_1 : in std_logic; - FFC_SD_2 : in std_logic; - FFC_SD_3 : in std_logic; - - FFC_EN_CGA_0 : in std_logic; - FFC_EN_CGA_1 : in std_logic; - FFC_EN_CGA_2 : in std_logic; - FFC_EN_CGA_3 : in std_logic; - - FFC_ALIGN_EN_0 : in std_logic; - FFC_ALIGN_EN_1 : in std_logic; - FFC_ALIGN_EN_2 : in std_logic; - FFC_ALIGN_EN_3 : in std_logic; - - FFC_AB_RESET : in std_logic; - FFC_CD_RESET : in std_logic; - - FFS_LS_STATUS_0 : out std_logic; - FFS_LS_STATUS_1 : out std_logic; - FFS_LS_STATUS_2 : out std_logic; - FFS_LS_STATUS_3 : out std_logic; - - FFS_AB_STATUS : out std_logic; - FFS_CD_STATUS : out std_logic; - - FFS_AB_ALIGNED : out std_logic; - FFS_CD_ALIGNED : out std_logic; - - FFS_RLOS_LO0 : out std_logic; - FFS_RLOS_LO1 : out std_logic; - FFS_RLOS_LO2 : out std_logic; - FFS_RLOS_LO3 : out std_logic; - - FFS_AB_FAILED : out std_logic; - FFS_CD_FAILED : out std_logic; - - FFC_FB_LB_0 : in std_logic; - FFC_FB_LB_1 : in std_logic; - FFC_FB_LB_2 : in std_logic; - FFC_FB_LB_3 : in std_logic; - - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - - FFS_CC_ORUN_0 : out std_logic; - FFS_CC_ORUN_1 : out std_logic; - FFS_CC_ORUN_2 : out std_logic; - FFS_CC_ORUN_3 : out std_logic; - - FFS_CC_URUN_0 : out std_logic; - FFS_CC_URUN_1 : out std_logic; - FFS_CC_URUN_2 : out std_logic; - FFS_CC_URUN_3 : out std_logic; - - FFC_CK_CORE_TX : in std_logic; - FFC_CK_CORE_RX : in std_logic; - RDATAO_7 : out std_logic; - RDATAO_6 : out std_logic; - RDATAO_5 : out std_logic; - RDATAO_4 : out std_logic; - RDATAO_3 : out std_logic; - RDATAO_2 : out std_logic; - RDATAO_1 : out std_logic; - RDATAO_0 : out std_logic; - INTO : out std_logic; - - ADDRI_7 : in std_logic; - ADDRI_6 : in std_logic; - ADDRI_5 : in std_logic; - ADDRI_4 : in std_logic; - ADDRI_3 : in std_logic; - ADDRI_2 : in std_logic; - ADDRI_1 : in std_logic; - ADDRI_0 : in std_logic; - WDATAI_7 : in std_logic; - WDATAI_6 : in std_logic; - WDATAI_5 : in std_logic; - WDATAI_4 : in std_logic; - WDATAI_3 : in std_logic; - WDATAI_2 : in std_logic; - WDATAI_1 : in std_logic; - WDATAI_0 : in std_logic; - RDI : in std_logic; - WSTBI : in std_logic; - - CS_CHIF_0 : in std_logic; - CS_CHIF_1 : in std_logic; - CS_CHIF_2 : in std_logic; - CS_CHIF_3 : in std_logic; - CS_QIF : in std_logic; - - QUAD_ID_1 : in std_logic; - QUAD_ID_0 : in std_logic; - - FF_SYSCLK_P1 : out std_logic; - - FF_SYSCLK0 : out std_logic; - FF_SYSCLK1 : out std_logic; - FF_SYSCLK2 : out std_logic; - FF_SYSCLK3 : out std_logic; - - FF_RXCLK_P1 : out std_logic; - FF_RXCLK_P2 : out std_logic; - - FF_RXCLK0 : out std_logic; - FF_RXCLK1 : out std_logic; - FF_RXCLK2 : out std_logic; - FF_RXCLK3 : out std_logic; - - QUAD_CLK : out std_logic; - - GRP_CLK_P1_3 : in std_logic; - GRP_CLK_P1_2 : in std_logic; - GRP_CLK_P1_1 : in std_logic; - GRP_CLK_P1_0 : in std_logic; - - GRP_CLK_P2_3 : in std_logic; - GRP_CLK_P2_2 : in std_logic; - GRP_CLK_P2_1 : in std_logic; - GRP_CLK_P2_0 : in std_logic; - - GRP_START_3 : in std_logic; - GRP_START_2 : in std_logic; - GRP_START_1 : in std_logic; - GRP_START_0 : in std_logic; - - GRP_DONE_3 : in std_logic; - GRP_DONE_2 : in std_logic; - GRP_DONE_1 : in std_logic; - GRP_DONE_0 : in std_logic; - - GRP_DESKEW_ERROR_3 : in std_logic; - GRP_DESKEW_ERROR_2 : in std_logic; - GRP_DESKEW_ERROR_1 : in std_logic; - GRP_DESKEW_ERROR_0 : in std_logic; - - IQA_START_LS : out std_logic; - IQA_DONE_LS : out std_logic; - IQA_AND_FP1_LS : out std_logic; - IQA_AND_FP0_LS : out std_logic; - IQA_OR_FP1_LS : out std_logic; - IQA_OR_FP0_LS : out std_logic; - IQA_RST_N : out std_logic; - - FF_TCLK0 : in std_logic; - FF_TCLK1 : in std_logic; - FF_TCLK2 : in std_logic; - FF_TCLK3 : in std_logic; - - FF_RCLK0 : in std_logic; - FF_RCLK1 : in std_logic; - FF_RCLK2 : in std_logic; - FF_RCLK3 : in std_logic; - TCK_FMACP : in std_logic; - - FF_TXD_0_23 : in std_logic; - FF_TXD_0_22 : in std_logic; - FF_TXD_0_21 : in std_logic; - FF_TXD_0_20 : in std_logic; - FF_TXD_0_19 : in std_logic; - FF_TXD_0_18 : in std_logic; - FF_TXD_0_17 : in std_logic; - FF_TXD_0_16 : in std_logic; - FF_TXD_0_15 : in std_logic; - FF_TXD_0_14 : in std_logic; - FF_TXD_0_13 : in std_logic; - FF_TXD_0_12 : in std_logic; - FF_TXD_0_11 : in std_logic; - FF_TXD_0_10 : in std_logic; - FF_TXD_0_9 : in std_logic; - FF_TXD_0_8 : in std_logic; - FF_TXD_0_7 : in std_logic; - FF_TXD_0_6 : in std_logic; - FF_TXD_0_5 : in std_logic; - FF_TXD_0_4 : in std_logic; - FF_TXD_0_3 : in std_logic; - FF_TXD_0_2 : in std_logic; - FF_TXD_0_1 : in std_logic; - FF_TXD_0_0 : in std_logic; - FB_RXD_0_23 : out std_logic; - FB_RXD_0_22 : out std_logic; - FB_RXD_0_21 : out std_logic; - FB_RXD_0_20 : out std_logic; - FB_RXD_0_19 : out std_logic; - FB_RXD_0_18 : out std_logic; - FB_RXD_0_17 : out std_logic; - FB_RXD_0_16 : out std_logic; - FB_RXD_0_15 : out std_logic; - FB_RXD_0_14 : out std_logic; - FB_RXD_0_13 : out std_logic; - FB_RXD_0_12 : out std_logic; - FB_RXD_0_11 : out std_logic; - FB_RXD_0_10 : out std_logic; - FB_RXD_0_9 : out std_logic; - FB_RXD_0_8 : out std_logic; - FB_RXD_0_7 : out std_logic; - FB_RXD_0_6 : out std_logic; - FB_RXD_0_5 : out std_logic; - FB_RXD_0_4 : out std_logic; - FB_RXD_0_3 : out std_logic; - FB_RXD_0_2 : out std_logic; - FB_RXD_0_1 : out std_logic; - FB_RXD_0_0 : out std_logic; - FF_TXD_1_23 : in std_logic; - FF_TXD_1_22 : in std_logic; - FF_TXD_1_21 : in std_logic; - FF_TXD_1_20 : in std_logic; - FF_TXD_1_19 : in std_logic; - FF_TXD_1_18 : in std_logic; - FF_TXD_1_17 : in std_logic; - FF_TXD_1_16 : in std_logic; - FF_TXD_1_15 : in std_logic; - FF_TXD_1_14 : in std_logic; - FF_TXD_1_13 : in std_logic; - FF_TXD_1_12 : in std_logic; - FF_TXD_1_11 : in std_logic; - FF_TXD_1_10 : in std_logic; - FF_TXD_1_9 : in std_logic; - FF_TXD_1_8 : in std_logic; - FF_TXD_1_7 : in std_logic; - FF_TXD_1_6 : in std_logic; - FF_TXD_1_5 : in std_logic; - FF_TXD_1_4 : in std_logic; - FF_TXD_1_3 : in std_logic; - FF_TXD_1_2 : in std_logic; - FF_TXD_1_1 : in std_logic; - FF_TXD_1_0 : in std_logic; - FB_RXD_1_23 : out std_logic; - FB_RXD_1_22 : out std_logic; - FB_RXD_1_21 : out std_logic; - FB_RXD_1_20 : out std_logic; - FB_RXD_1_19 : out std_logic; - FB_RXD_1_18 : out std_logic; - FB_RXD_1_17 : out std_logic; - FB_RXD_1_16 : out std_logic; - FB_RXD_1_15 : out std_logic; - FB_RXD_1_14 : out std_logic; - FB_RXD_1_13 : out std_logic; - FB_RXD_1_12 : out std_logic; - FB_RXD_1_11 : out std_logic; - FB_RXD_1_10 : out std_logic; - FB_RXD_1_9 : out std_logic; - FB_RXD_1_8 : out std_logic; - FB_RXD_1_7 : out std_logic; - FB_RXD_1_6 : out std_logic; - FB_RXD_1_5 : out std_logic; - FB_RXD_1_4 : out std_logic; - FB_RXD_1_3 : out std_logic; - FB_RXD_1_2 : out std_logic; - FB_RXD_1_1 : out std_logic; - FB_RXD_1_0 : out std_logic; - FF_TXD_2_23 : in std_logic; - FF_TXD_2_22 : in std_logic; - FF_TXD_2_21 : in std_logic; - FF_TXD_2_20 : in std_logic; - FF_TXD_2_19 : in std_logic; - FF_TXD_2_18 : in std_logic; - FF_TXD_2_17 : in std_logic; - FF_TXD_2_16 : in std_logic; - FF_TXD_2_15 : in std_logic; - FF_TXD_2_14 : in std_logic; - FF_TXD_2_13 : in std_logic; - FF_TXD_2_12 : in std_logic; - FF_TXD_2_11 : in std_logic; - FF_TXD_2_10 : in std_logic; - FF_TXD_2_9 : in std_logic; - FF_TXD_2_8 : in std_logic; - FF_TXD_2_7 : in std_logic; - FF_TXD_2_6 : in std_logic; - FF_TXD_2_5 : in std_logic; - FF_TXD_2_4 : in std_logic; - FF_TXD_2_3 : in std_logic; - FF_TXD_2_2 : in std_logic; - FF_TXD_2_1 : in std_logic; - FF_TXD_2_0 : in std_logic; - FB_RXD_2_23 : out std_logic; - FB_RXD_2_22 : out std_logic; - FB_RXD_2_21 : out std_logic; - FB_RXD_2_20 : out std_logic; - FB_RXD_2_19 : out std_logic; - FB_RXD_2_18 : out std_logic; - FB_RXD_2_17 : out std_logic; - FB_RXD_2_16 : out std_logic; - FB_RXD_2_15 : out std_logic; - FB_RXD_2_14 : out std_logic; - FB_RXD_2_13 : out std_logic; - FB_RXD_2_12 : out std_logic; - FB_RXD_2_11 : out std_logic; - FB_RXD_2_10 : out std_logic; - FB_RXD_2_9 : out std_logic; - FB_RXD_2_8 : out std_logic; - FB_RXD_2_7 : out std_logic; - FB_RXD_2_6 : out std_logic; - FB_RXD_2_5 : out std_logic; - FB_RXD_2_4 : out std_logic; - FB_RXD_2_3 : out std_logic; - FB_RXD_2_2 : out std_logic; - FB_RXD_2_1 : out std_logic; - FB_RXD_2_0 : out std_logic; - FF_TXD_3_23 : in std_logic; - FF_TXD_3_22 : in std_logic; - FF_TXD_3_21 : in std_logic; - FF_TXD_3_20 : in std_logic; - FF_TXD_3_19 : in std_logic; - FF_TXD_3_18 : in std_logic; - FF_TXD_3_17 : in std_logic; - FF_TXD_3_16 : in std_logic; - FF_TXD_3_15 : in std_logic; - FF_TXD_3_14 : in std_logic; - FF_TXD_3_13 : in std_logic; - FF_TXD_3_12 : in std_logic; - FF_TXD_3_11 : in std_logic; - FF_TXD_3_10 : in std_logic; - FF_TXD_3_9 : in std_logic; - FF_TXD_3_8 : in std_logic; - FF_TXD_3_7 : in std_logic; - FF_TXD_3_6 : in std_logic; - FF_TXD_3_5 : in std_logic; - FF_TXD_3_4 : in std_logic; - FF_TXD_3_3 : in std_logic; - FF_TXD_3_2 : in std_logic; - FF_TXD_3_1 : in std_logic; - FF_TXD_3_0 : in std_logic; - FB_RXD_3_23 : out std_logic; - FB_RXD_3_22 : out std_logic; - FB_RXD_3_21 : out std_logic; - FB_RXD_3_20 : out std_logic; - FB_RXD_3_19 : out std_logic; - FB_RXD_3_18 : out std_logic; - FB_RXD_3_17 : out std_logic; - FB_RXD_3_16 : out std_logic; - FB_RXD_3_15 : out std_logic; - FB_RXD_3_14 : out std_logic; - FB_RXD_3_13 : out std_logic; - FB_RXD_3_12 : out std_logic; - FB_RXD_3_11 : out std_logic; - FB_RXD_3_10 : out std_logic; - FB_RXD_3_9 : out std_logic; - FB_RXD_3_8 : out std_logic; - FB_RXD_3_7 : out std_logic; - FB_RXD_3_6 : out std_logic; - FB_RXD_3_5 : out std_logic; - FB_RXD_3_4 : out std_logic; - FB_RXD_3_3 : out std_logic; - FB_RXD_3_2 : out std_logic; - FB_RXD_3_1 : out std_logic; - FB_RXD_3_0 : out std_logic; - TCK_FMAC : out std_logic; - BS4PAD_0 : out std_logic; - BS4PAD_1 : out std_logic; - BS4PAD_2 : out std_logic; - BS4PAD_3 : out std_logic; - COUT_21 : out std_logic; - COUT_20 : out std_logic; - COUT_19 : out std_logic; - COUT_18 : out std_logic; - COUT_17 : out std_logic; - COUT_16 : out std_logic; - COUT_15 : out std_logic; - COUT_14 : out std_logic; - COUT_13 : out std_logic; - COUT_12 : out std_logic; - COUT_11 : out std_logic; - COUT_10 : out std_logic; - COUT_9 : out std_logic; - COUT_8 : out std_logic; - COUT_7 : out std_logic; - COUT_6 : out std_logic; - COUT_5 : out std_logic; - COUT_4 : out std_logic; - COUT_3 : out std_logic; - COUT_2 : out std_logic; - COUT_1 : out std_logic; - COUT_0 : out std_logic; - CIN_12 : in std_logic; - CIN_11 : in std_logic; - CIN_10 : in std_logic; - CIN_9 : in std_logic; - CIN_8 : in std_logic; - CIN_7 : in std_logic; - CIN_6 : in std_logic; - CIN_5 : in std_logic; - CIN_4 : in std_logic; - CIN_3 : in std_logic; - CIN_2 : in std_logic; - CIN_1 : in std_logic; - CIN_0 : in std_logic; - TESTCLK_MACO : in std_logic -); - -end PCSA; - -architecture PCSA_arch of PCSA is - -component PCSA_sim -GENERIC( - CONFIG_FILE : String - ); -port ( - HDINP0 : in std_logic; - HDINN0 : in std_logic; - HDINP1 : in std_logic; - HDINN1 : in std_logic; - HDINP2 : in std_logic; - HDINN2 : in std_logic; - HDINP3 : in std_logic; - HDINN3 : in std_logic; - HDOUTP0 : out std_logic; - HDOUTN0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTP3 : out std_logic; - HDOUTN3 : out std_logic; - REFCLKP : in std_logic; - REFCLKN : in std_logic; - RXREFCLKP : in std_logic; - RXREFCLKN : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_MACRO_RST : in std_logic; - - FFC_LANE_TX_RST0 : in std_logic; - FFC_LANE_TX_RST1 : in std_logic; - FFC_LANE_TX_RST2 : in std_logic; - FFC_LANE_TX_RST3 : in std_logic; - - FFC_LANE_RX_RST0 : in std_logic; - FFC_LANE_RX_RST1 : in std_logic; - FFC_LANE_RX_RST2 : in std_logic; - FFC_LANE_RX_RST3 : in std_logic; - - FFC_PCIE_EI_EN_0 : in std_logic; - FFC_PCIE_EI_EN_1 : in std_logic; - FFC_PCIE_EI_EN_2 : in std_logic; - FFC_PCIE_EI_EN_3 : in std_logic; - - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - - FFC_PCIE_TX_0 : in std_logic; - FFC_PCIE_TX_1 : in std_logic; - FFC_PCIE_TX_2 : in std_logic; - FFC_PCIE_TX_3 : in std_logic; - - FFC_PCIE_RX_0 : in std_logic; - FFC_PCIE_RX_1 : in std_logic; - FFC_PCIE_RX_2 : in std_logic; - FFC_PCIE_RX_3 : in std_logic; - - FFC_SD_0 : in std_logic; - FFC_SD_1 : in std_logic; - FFC_SD_2 : in std_logic; - FFC_SD_3 : in std_logic; - - FFC_EN_CGA_0 : in std_logic; - FFC_EN_CGA_1 : in std_logic; - FFC_EN_CGA_2 : in std_logic; - FFC_EN_CGA_3 : in std_logic; - - FFC_ALIGN_EN_0 : in std_logic; - FFC_ALIGN_EN_1 : in std_logic; - FFC_ALIGN_EN_2 : in std_logic; - FFC_ALIGN_EN_3 : in std_logic; - - FFC_AB_RESET : in std_logic; - FFC_CD_RESET : in std_logic; - - FFS_LS_STATUS_0 : out std_logic; - FFS_LS_STATUS_1 : out std_logic; - FFS_LS_STATUS_2 : out std_logic; - FFS_LS_STATUS_3 : out std_logic; - - FFS_AB_STATUS : out std_logic; - FFS_CD_STATUS : out std_logic; - - FFS_AB_ALIGNED : out std_logic; - FFS_CD_ALIGNED : out std_logic; - - FFS_AB_FAILED : out std_logic; - FFS_CD_FAILED : out std_logic; - - FFS_RLOS_LO0 : out std_logic; - FFS_RLOS_LO1 : out std_logic; - FFS_RLOS_LO2 : out std_logic; - FFS_RLOS_LO3 : out std_logic; - - FFC_FB_LB_0 : in std_logic; - FFC_FB_LB_1 : in std_logic; - FFC_FB_LB_2 : in std_logic; - FFC_FB_LB_3 : in std_logic; - - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - - FFS_CC_ORUN_0 : out std_logic; - FFS_CC_ORUN_1 : out std_logic; - FFS_CC_ORUN_2 : out std_logic; - FFS_CC_ORUN_3 : out std_logic; - - FFS_CC_URUN_0 : out std_logic; - FFS_CC_URUN_1 : out std_logic; - FFS_CC_URUN_2 : out std_logic; - FFS_CC_URUN_3 : out std_logic; - - FFC_CK_CORE_TX : in std_logic; - FFC_CK_CORE_RX : in std_logic; - RDATAO_7 : out std_logic; - RDATAO_6 : out std_logic; - RDATAO_5 : out std_logic; - RDATAO_4 : out std_logic; - RDATAO_3 : out std_logic; - RDATAO_2 : out std_logic; - RDATAO_1 : out std_logic; - RDATAO_0 : out std_logic; - INTO : out std_logic; - - ADDRI_7 : in std_logic; - ADDRI_6 : in std_logic; - ADDRI_5 : in std_logic; - ADDRI_4 : in std_logic; - ADDRI_3 : in std_logic; - ADDRI_2 : in std_logic; - ADDRI_1 : in std_logic; - ADDRI_0 : in std_logic; - WDATAI_7 : in std_logic; - WDATAI_6 : in std_logic; - WDATAI_5 : in std_logic; - WDATAI_4 : in std_logic; - WDATAI_3 : in std_logic; - WDATAI_2 : in std_logic; - WDATAI_1 : in std_logic; - WDATAI_0 : in std_logic; - RDI : in std_logic; - WSTBI : in std_logic; - - CS_CHIF_0 : in std_logic; - CS_CHIF_1 : in std_logic; - CS_CHIF_2 : in std_logic; - CS_CHIF_3 : in std_logic; - CS_QIF : in std_logic; - - QUAD_ID_1 : in std_logic; - QUAD_ID_0 : in std_logic; - - FF_SYSCLK_P1 : out std_logic; - - FF_SYSCLK0 : out std_logic; - FF_SYSCLK1 : out std_logic; - FF_SYSCLK2 : out std_logic; - FF_SYSCLK3 : out std_logic; - - FF_RXCLK_P1 : out std_logic; - FF_RXCLK_P2 : out std_logic; - - FF_RXCLK0 : out std_logic; - FF_RXCLK1 : out std_logic; - FF_RXCLK2 : out std_logic; - FF_RXCLK3 : out std_logic; - - QUAD_CLK : out std_logic; - - GRP_CLK_P1_3 : in std_logic; - GRP_CLK_P1_2 : in std_logic; - GRP_CLK_P1_1 : in std_logic; - GRP_CLK_P1_0 : in std_logic; - - GRP_CLK_P2_3 : in std_logic; - GRP_CLK_P2_2 : in std_logic; - GRP_CLK_P2_1 : in std_logic; - GRP_CLK_P2_0 : in std_logic; - - GRP_START_3 : in std_logic; - GRP_START_2 : in std_logic; - GRP_START_1 : in std_logic; - GRP_START_0 : in std_logic; - - GRP_DONE_3 : in std_logic; - GRP_DONE_2 : in std_logic; - GRP_DONE_1 : in std_logic; - GRP_DONE_0 : in std_logic; - - GRP_DESKEW_ERROR_3 : in std_logic; - GRP_DESKEW_ERROR_2 : in std_logic; - GRP_DESKEW_ERROR_1 : in std_logic; - GRP_DESKEW_ERROR_0 : in std_logic; - - IQA_START_LS : out std_logic; - IQA_DONE_LS : out std_logic; - IQA_AND_FP1_LS : out std_logic; - IQA_AND_FP0_LS : out std_logic; - IQA_OR_FP1_LS : out std_logic; - IQA_OR_FP0_LS : out std_logic; - IQA_RST_N : out std_logic; - - FF_TCLK0 : in std_logic; - FF_TCLK1 : in std_logic; - FF_TCLK2 : in std_logic; - FF_TCLK3 : in std_logic; - - FF_RCLK0 : in std_logic; - FF_RCLK1 : in std_logic; - FF_RCLK2 : in std_logic; - FF_RCLK3 : in std_logic; - TCK_FMACP : in std_logic; - - FF_TXD_0_23 : in std_logic; - FF_TXD_0_22 : in std_logic; - FF_TXD_0_21 : in std_logic; - FF_TXD_0_20 : in std_logic; - FF_TXD_0_19 : in std_logic; - FF_TXD_0_18 : in std_logic; - FF_TXD_0_17 : in std_logic; - FF_TXD_0_16 : in std_logic; - FF_TXD_0_15 : in std_logic; - FF_TXD_0_14 : in std_logic; - FF_TXD_0_13 : in std_logic; - FF_TXD_0_12 : in std_logic; - FF_TXD_0_11 : in std_logic; - FF_TXD_0_10 : in std_logic; - FF_TXD_0_9 : in std_logic; - FF_TXD_0_8 : in std_logic; - FF_TXD_0_7 : in std_logic; - FF_TXD_0_6 : in std_logic; - FF_TXD_0_5 : in std_logic; - FF_TXD_0_4 : in std_logic; - FF_TXD_0_3 : in std_logic; - FF_TXD_0_2 : in std_logic; - FF_TXD_0_1 : in std_logic; - FF_TXD_0_0 : in std_logic; - FB_RXD_0_23 : out std_logic; - FB_RXD_0_22 : out std_logic; - FB_RXD_0_21 : out std_logic; - FB_RXD_0_20 : out std_logic; - FB_RXD_0_19 : out std_logic; - FB_RXD_0_18 : out std_logic; - FB_RXD_0_17 : out std_logic; - FB_RXD_0_16 : out std_logic; - FB_RXD_0_15 : out std_logic; - FB_RXD_0_14 : out std_logic; - FB_RXD_0_13 : out std_logic; - FB_RXD_0_12 : out std_logic; - FB_RXD_0_11 : out std_logic; - FB_RXD_0_10 : out std_logic; - FB_RXD_0_9 : out std_logic; - FB_RXD_0_8 : out std_logic; - FB_RXD_0_7 : out std_logic; - FB_RXD_0_6 : out std_logic; - FB_RXD_0_5 : out std_logic; - FB_RXD_0_4 : out std_logic; - FB_RXD_0_3 : out std_logic; - FB_RXD_0_2 : out std_logic; - FB_RXD_0_1 : out std_logic; - FB_RXD_0_0 : out std_logic; - FF_TXD_1_23 : in std_logic; - FF_TXD_1_22 : in std_logic; - FF_TXD_1_21 : in std_logic; - FF_TXD_1_20 : in std_logic; - FF_TXD_1_19 : in std_logic; - FF_TXD_1_18 : in std_logic; - FF_TXD_1_17 : in std_logic; - FF_TXD_1_16 : in std_logic; - FF_TXD_1_15 : in std_logic; - FF_TXD_1_14 : in std_logic; - FF_TXD_1_13 : in std_logic; - FF_TXD_1_12 : in std_logic; - FF_TXD_1_11 : in std_logic; - FF_TXD_1_10 : in std_logic; - FF_TXD_1_9 : in std_logic; - FF_TXD_1_8 : in std_logic; - FF_TXD_1_7 : in std_logic; - FF_TXD_1_6 : in std_logic; - FF_TXD_1_5 : in std_logic; - FF_TXD_1_4 : in std_logic; - FF_TXD_1_3 : in std_logic; - FF_TXD_1_2 : in std_logic; - FF_TXD_1_1 : in std_logic; - FF_TXD_1_0 : in std_logic; - FB_RXD_1_23 : out std_logic; - FB_RXD_1_22 : out std_logic; - FB_RXD_1_21 : out std_logic; - FB_RXD_1_20 : out std_logic; - FB_RXD_1_19 : out std_logic; - FB_RXD_1_18 : out std_logic; - FB_RXD_1_17 : out std_logic; - FB_RXD_1_16 : out std_logic; - FB_RXD_1_15 : out std_logic; - FB_RXD_1_14 : out std_logic; - FB_RXD_1_13 : out std_logic; - FB_RXD_1_12 : out std_logic; - FB_RXD_1_11 : out std_logic; - FB_RXD_1_10 : out std_logic; - FB_RXD_1_9 : out std_logic; - FB_RXD_1_8 : out std_logic; - FB_RXD_1_7 : out std_logic; - FB_RXD_1_6 : out std_logic; - FB_RXD_1_5 : out std_logic; - FB_RXD_1_4 : out std_logic; - FB_RXD_1_3 : out std_logic; - FB_RXD_1_2 : out std_logic; - FB_RXD_1_1 : out std_logic; - FB_RXD_1_0 : out std_logic; - FF_TXD_2_23 : in std_logic; - FF_TXD_2_22 : in std_logic; - FF_TXD_2_21 : in std_logic; - FF_TXD_2_20 : in std_logic; - FF_TXD_2_19 : in std_logic; - FF_TXD_2_18 : in std_logic; - FF_TXD_2_17 : in std_logic; - FF_TXD_2_16 : in std_logic; - FF_TXD_2_15 : in std_logic; - FF_TXD_2_14 : in std_logic; - FF_TXD_2_13 : in std_logic; - FF_TXD_2_12 : in std_logic; - FF_TXD_2_11 : in std_logic; - FF_TXD_2_10 : in std_logic; - FF_TXD_2_9 : in std_logic; - FF_TXD_2_8 : in std_logic; - FF_TXD_2_7 : in std_logic; - FF_TXD_2_6 : in std_logic; - FF_TXD_2_5 : in std_logic; - FF_TXD_2_4 : in std_logic; - FF_TXD_2_3 : in std_logic; - FF_TXD_2_2 : in std_logic; - FF_TXD_2_1 : in std_logic; - FF_TXD_2_0 : in std_logic; - FB_RXD_2_23 : out std_logic; - FB_RXD_2_22 : out std_logic; - FB_RXD_2_21 : out std_logic; - FB_RXD_2_20 : out std_logic; - FB_RXD_2_19 : out std_logic; - FB_RXD_2_18 : out std_logic; - FB_RXD_2_17 : out std_logic; - FB_RXD_2_16 : out std_logic; - FB_RXD_2_15 : out std_logic; - FB_RXD_2_14 : out std_logic; - FB_RXD_2_13 : out std_logic; - FB_RXD_2_12 : out std_logic; - FB_RXD_2_11 : out std_logic; - FB_RXD_2_10 : out std_logic; - FB_RXD_2_9 : out std_logic; - FB_RXD_2_8 : out std_logic; - FB_RXD_2_7 : out std_logic; - FB_RXD_2_6 : out std_logic; - FB_RXD_2_5 : out std_logic; - FB_RXD_2_4 : out std_logic; - FB_RXD_2_3 : out std_logic; - FB_RXD_2_2 : out std_logic; - FB_RXD_2_1 : out std_logic; - FB_RXD_2_0 : out std_logic; - FF_TXD_3_23 : in std_logic; - FF_TXD_3_22 : in std_logic; - FF_TXD_3_21 : in std_logic; - FF_TXD_3_20 : in std_logic; - FF_TXD_3_19 : in std_logic; - FF_TXD_3_18 : in std_logic; - FF_TXD_3_17 : in std_logic; - FF_TXD_3_16 : in std_logic; - FF_TXD_3_15 : in std_logic; - FF_TXD_3_14 : in std_logic; - FF_TXD_3_13 : in std_logic; - FF_TXD_3_12 : in std_logic; - FF_TXD_3_11 : in std_logic; - FF_TXD_3_10 : in std_logic; - FF_TXD_3_9 : in std_logic; - FF_TXD_3_8 : in std_logic; - FF_TXD_3_7 : in std_logic; - FF_TXD_3_6 : in std_logic; - FF_TXD_3_5 : in std_logic; - FF_TXD_3_4 : in std_logic; - FF_TXD_3_3 : in std_logic; - FF_TXD_3_2 : in std_logic; - FF_TXD_3_1 : in std_logic; - FF_TXD_3_0 : in std_logic; - FB_RXD_3_23 : out std_logic; - FB_RXD_3_22 : out std_logic; - FB_RXD_3_21 : out std_logic; - FB_RXD_3_20 : out std_logic; - FB_RXD_3_19 : out std_logic; - FB_RXD_3_18 : out std_logic; - FB_RXD_3_17 : out std_logic; - FB_RXD_3_16 : out std_logic; - FB_RXD_3_15 : out std_logic; - FB_RXD_3_14 : out std_logic; - FB_RXD_3_13 : out std_logic; - FB_RXD_3_12 : out std_logic; - FB_RXD_3_11 : out std_logic; - FB_RXD_3_10 : out std_logic; - FB_RXD_3_9 : out std_logic; - FB_RXD_3_8 : out std_logic; - FB_RXD_3_7 : out std_logic; - FB_RXD_3_6 : out std_logic; - FB_RXD_3_5 : out std_logic; - FB_RXD_3_4 : out std_logic; - FB_RXD_3_3 : out std_logic; - FB_RXD_3_2 : out std_logic; - FB_RXD_3_1 : out std_logic; - FB_RXD_3_0 : out std_logic; - TCK_FMAC : out std_logic; - BS4PAD_0 : out std_logic; - BS4PAD_1 : out std_logic; - BS4PAD_2 : out std_logic; - BS4PAD_3 : out std_logic; - COUT_21 : out std_logic; - COUT_20 : out std_logic; - COUT_19 : out std_logic; - COUT_18 : out std_logic; - COUT_17 : out std_logic; - COUT_16 : out std_logic; - COUT_15 : out std_logic; - COUT_14 : out std_logic; - COUT_13 : out std_logic; - COUT_12 : out std_logic; - COUT_11 : out std_logic; - COUT_10 : out std_logic; - COUT_9 : out std_logic; - COUT_8 : out std_logic; - COUT_7 : out std_logic; - COUT_6 : out std_logic; - COUT_5 : out std_logic; - COUT_4 : out std_logic; - COUT_3 : out std_logic; - COUT_2 : out std_logic; - COUT_1 : out std_logic; - COUT_0 : out std_logic; - CIN_12 : in std_logic; - CIN_11 : in std_logic; - CIN_10 : in std_logic; - CIN_9 : in std_logic; - CIN_8 : in std_logic; - CIN_7 : in std_logic; - CIN_6 : in std_logic; - CIN_5 : in std_logic; - CIN_4 : in std_logic; - CIN_3 : in std_logic; - CIN_2 : in std_logic; - CIN_1 : in std_logic; - CIN_0 : in std_logic; - TESTCLK_MACO : in std_logic -); -end component; - -begin - -PCSA_sim_inst : PCSA_sim -generic map ( - CONFIG_FILE => CONFIG_FILE) -port map ( - HDINP0 => HDINP0, - HDINN0 => HDINN0, - HDINP1 => HDINP1, - HDINN1 => HDINN1, - HDINP2 => HDINP2, - HDINN2 => HDINN2, - HDINP3 => HDINP3, - HDINN3 => HDINN3, - HDOUTP0 => HDOUTP0, - HDOUTN0 => HDOUTN0, - HDOUTP1 => HDOUTP1, - HDOUTN1 => HDOUTN1, - HDOUTP2 => HDOUTP2, - HDOUTN2 => HDOUTN2, - HDOUTP3 => HDOUTP3, - HDOUTN3 => HDOUTN3, - REFCLKP => REFCLKP, - REFCLKN => REFCLKN, - RXREFCLKP => RXREFCLKP, - RXREFCLKN => RXREFCLKN, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0, - FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1, - FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2, - FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3, - FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0, - FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1, - FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2, - FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3, - FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0, - FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1, - FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2, - FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFC_PCIE_TX_0 => FFC_PCIE_TX_0, - FFC_PCIE_TX_1 => FFC_PCIE_TX_1, - FFC_PCIE_TX_2 => FFC_PCIE_TX_2, - FFC_PCIE_TX_3 => FFC_PCIE_TX_3, - FFC_PCIE_RX_0 => FFC_PCIE_RX_0, - FFC_PCIE_RX_1 => FFC_PCIE_RX_1, - FFC_PCIE_RX_2 => FFC_PCIE_RX_2, - FFC_PCIE_RX_3 => FFC_PCIE_RX_3, - FFC_SD_0 => FFC_SD_0, - FFC_SD_1 => FFC_SD_1, - FFC_SD_2 => FFC_SD_2, - FFC_SD_3 => FFC_SD_3, - FFC_EN_CGA_0 => FFC_EN_CGA_0, - FFC_EN_CGA_1 => FFC_EN_CGA_1, - FFC_EN_CGA_2 => FFC_EN_CGA_2, - FFC_EN_CGA_3 => FFC_EN_CGA_3, - FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0, - FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1, - FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2, - FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3, - FFC_AB_RESET => FFC_AB_RESET, - FFC_CD_RESET => FFC_CD_RESET, - FFS_LS_STATUS_0 => FFS_LS_STATUS_0, - FFS_LS_STATUS_1 => FFS_LS_STATUS_1, - FFS_LS_STATUS_2 => FFS_LS_STATUS_2, - FFS_LS_STATUS_3 => FFS_LS_STATUS_3, - FFS_AB_STATUS => FFS_AB_STATUS, - FFS_CD_STATUS => FFS_CD_STATUS, - FFS_AB_ALIGNED => FFS_AB_ALIGNED, - FFS_CD_ALIGNED => FFS_CD_ALIGNED, - FFS_AB_FAILED => FFS_AB_FAILED, - FFS_CD_FAILED => FFS_CD_FAILED, - FFS_RLOS_LO0 => FFS_RLOS_LO0, - FFS_RLOS_LO1 => FFS_RLOS_LO1, - FFS_RLOS_LO2 => FFS_RLOS_LO2, - FFS_RLOS_LO3 => FFS_RLOS_LO3, - FFC_FB_LB_0 => FFC_FB_LB_0, - FFC_FB_LB_1 => FFC_FB_LB_1, - FFC_FB_LB_2 => FFC_FB_LB_2, - FFC_FB_LB_3 => FFC_FB_LB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFS_CC_ORUN_0 => FFS_CC_ORUN_0, - FFS_CC_ORUN_1 => FFS_CC_ORUN_1, - FFS_CC_ORUN_2 => FFS_CC_ORUN_2, - FFS_CC_ORUN_3 => FFS_CC_ORUN_3, - FFS_CC_URUN_0 => FFS_CC_URUN_0, - FFS_CC_URUN_1 => FFS_CC_URUN_1, - FFS_CC_URUN_2 => FFS_CC_URUN_2, - FFS_CC_URUN_3 => FFS_CC_URUN_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_CK_CORE_RX => FFC_CK_CORE_RX, - BS4PAD_0 => BS4PAD_0, - BS4PAD_1 => BS4PAD_1, - BS4PAD_2 => BS4PAD_2, - BS4PAD_3 => BS4PAD_3, - RDATAO_7 => RDATAO_7, - RDATAO_6 => RDATAO_6, - RDATAO_5 => RDATAO_5, - RDATAO_4 => RDATAO_4, - RDATAO_3 => RDATAO_3, - RDATAO_2 => RDATAO_2, - RDATAO_1 => RDATAO_1, - RDATAO_0 => RDATAO_0, - INTO => INTO, - ADDRI_7 => ADDRI_7, - ADDRI_6 => ADDRI_6, - ADDRI_5 => ADDRI_5, - ADDRI_4 => ADDRI_4, - ADDRI_3 => ADDRI_3, - ADDRI_2 => ADDRI_2, - ADDRI_1 => ADDRI_1, - ADDRI_0 => ADDRI_0, - WDATAI_7 => WDATAI_7, - WDATAI_6 => WDATAI_6, - WDATAI_5 => WDATAI_5, - WDATAI_4 => WDATAI_4, - WDATAI_3 => WDATAI_3, - WDATAI_2 => WDATAI_2, - WDATAI_1 => WDATAI_1, - WDATAI_0 => WDATAI_0, - RDI => RDI, - WSTBI => WSTBI, - CS_CHIF_0 => CS_CHIF_0, - CS_CHIF_1 => CS_CHIF_1, - CS_CHIF_2 => CS_CHIF_2, - CS_CHIF_3 => CS_CHIF_3, - CS_QIF => CS_QIF, - QUAD_ID_1 => QUAD_ID_1, - QUAD_ID_0 => QUAD_ID_0, - FF_SYSCLK_P1 => FF_SYSCLK_P1, - FF_SYSCLK0 => FF_SYSCLK0, - FF_SYSCLK1 => FF_SYSCLK1, - FF_SYSCLK2 => FF_SYSCLK2, - FF_SYSCLK3 => FF_SYSCLK3, - FF_RXCLK_P1 => FF_RXCLK_P1, - FF_RXCLK_P2 => FF_RXCLK_P2, - FF_RXCLK0 => FF_RXCLK0, - FF_RXCLK1 => FF_RXCLK1, - FF_RXCLK2 => FF_RXCLK2, - FF_RXCLK3 => FF_RXCLK3, - QUAD_CLK => QUAD_CLK, - GRP_CLK_P1_3 => GRP_CLK_P1_3, - GRP_CLK_P1_2 => GRP_CLK_P1_2, - GRP_CLK_P1_1 => GRP_CLK_P1_1, - GRP_CLK_P1_0 => GRP_CLK_P1_0, - GRP_CLK_P2_3 => GRP_CLK_P2_3, - GRP_CLK_P2_2 => GRP_CLK_P2_2, - GRP_CLK_P2_1 => GRP_CLK_P2_1, - GRP_CLK_P2_0 => GRP_CLK_P2_0, - GRP_START_3 => GRP_START_3, - GRP_START_2 => GRP_START_2, - GRP_START_1 => GRP_START_1, - GRP_START_0 => GRP_START_0, - GRP_DONE_3 => GRP_DONE_3, - GRP_DONE_2 => GRP_DONE_2, - GRP_DONE_1 => GRP_DONE_1, - GRP_DONE_0 => GRP_DONE_0, - GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3, - GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2, - GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1, - GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0, - IQA_START_LS => IQA_START_LS, - IQA_DONE_LS => IQA_DONE_LS, - IQA_AND_FP1_LS => IQA_AND_FP1_LS, - IQA_AND_FP0_LS => IQA_AND_FP0_LS, - IQA_OR_FP1_LS => IQA_OR_FP1_LS, - IQA_OR_FP0_LS => IQA_OR_FP0_LS, - IQA_RST_N => IQA_RST_N, - FF_TCLK0 => FF_TCLK0, - FF_TCLK1 => FF_TCLK1, - FF_TCLK2 => FF_TCLK2, - FF_TCLK3 => FF_TCLK3, - FF_RCLK0 => FF_RCLK0, - FF_RCLK1 => FF_RCLK1, - FF_RCLK2 => FF_RCLK2, - FF_RCLK3 => FF_RCLK3, - TCK_FMACP => TCK_FMACP, - FF_TXD_0_23 => FF_TXD_0_23, - FF_TXD_0_22 => FF_TXD_0_22, - FF_TXD_0_21 => FF_TXD_0_21, - FF_TXD_0_20 => FF_TXD_0_20, - FF_TXD_0_19 => FF_TXD_0_19, - FF_TXD_0_18 => FF_TXD_0_18, - FF_TXD_0_17 => FF_TXD_0_17, - FF_TXD_0_16 => FF_TXD_0_16, - FF_TXD_0_15 => FF_TXD_0_15, - FF_TXD_0_14 => FF_TXD_0_14, - FF_TXD_0_13 => FF_TXD_0_13, - FF_TXD_0_12 => FF_TXD_0_12, - FF_TXD_0_11 => FF_TXD_0_11, - FF_TXD_0_10 => FF_TXD_0_10, - FF_TXD_0_9 => FF_TXD_0_9, - FF_TXD_0_8 => FF_TXD_0_8, - FF_TXD_0_7 => FF_TXD_0_7, - FF_TXD_0_6 => FF_TXD_0_6, - FF_TXD_0_5 => FF_TXD_0_5, - FF_TXD_0_4 => FF_TXD_0_4, - FF_TXD_0_3 => FF_TXD_0_3, - FF_TXD_0_2 => FF_TXD_0_2, - FF_TXD_0_1 => FF_TXD_0_1, - FF_TXD_0_0 => FF_TXD_0_0, - FB_RXD_0_23 => FB_RXD_0_23, - FB_RXD_0_22 => FB_RXD_0_22, - FB_RXD_0_21 => FB_RXD_0_21, - FB_RXD_0_20 => FB_RXD_0_20, - FB_RXD_0_19 => FB_RXD_0_19, - FB_RXD_0_18 => FB_RXD_0_18, - FB_RXD_0_17 => FB_RXD_0_17, - FB_RXD_0_16 => FB_RXD_0_16, - FB_RXD_0_15 => FB_RXD_0_15, - FB_RXD_0_14 => FB_RXD_0_14, - FB_RXD_0_13 => FB_RXD_0_13, - FB_RXD_0_12 => FB_RXD_0_12, - FB_RXD_0_11 => FB_RXD_0_11, - FB_RXD_0_10 => FB_RXD_0_10, - FB_RXD_0_9 => FB_RXD_0_9, - FB_RXD_0_8 => FB_RXD_0_8, - FB_RXD_0_7 => FB_RXD_0_7, - FB_RXD_0_6 => FB_RXD_0_6, - FB_RXD_0_5 => FB_RXD_0_5, - FB_RXD_0_4 => FB_RXD_0_4, - FB_RXD_0_3 => FB_RXD_0_3, - FB_RXD_0_2 => FB_RXD_0_2, - FB_RXD_0_1 => FB_RXD_0_1, - FB_RXD_0_0 => FB_RXD_0_0, - FF_TXD_1_23 => FF_TXD_1_23, - FF_TXD_1_22 => FF_TXD_1_22, - FF_TXD_1_21 => FF_TXD_1_21, - FF_TXD_1_20 => FF_TXD_1_20, - FF_TXD_1_19 => FF_TXD_1_19, - FF_TXD_1_18 => FF_TXD_1_18, - FF_TXD_1_17 => FF_TXD_1_17, - FF_TXD_1_16 => FF_TXD_1_16, - FF_TXD_1_15 => FF_TXD_1_15, - FF_TXD_1_14 => FF_TXD_1_14, - FF_TXD_1_13 => FF_TXD_1_13, - FF_TXD_1_12 => FF_TXD_1_12, - FF_TXD_1_11 => FF_TXD_1_11, - FF_TXD_1_10 => FF_TXD_1_10, - FF_TXD_1_9 => FF_TXD_1_9, - FF_TXD_1_8 => FF_TXD_1_8, - FF_TXD_1_7 => FF_TXD_1_7, - FF_TXD_1_6 => FF_TXD_1_6, - FF_TXD_1_5 => FF_TXD_1_5, - FF_TXD_1_4 => FF_TXD_1_4, - FF_TXD_1_3 => FF_TXD_1_3, - FF_TXD_1_2 => FF_TXD_1_2, - FF_TXD_1_1 => FF_TXD_1_1, - FF_TXD_1_0 => FF_TXD_1_0, - FB_RXD_1_23 => FB_RXD_1_23, - FB_RXD_1_22 => FB_RXD_1_22, - FB_RXD_1_21 => FB_RXD_1_21, - FB_RXD_1_20 => FB_RXD_1_20, - FB_RXD_1_19 => FB_RXD_1_19, - FB_RXD_1_18 => FB_RXD_1_18, - FB_RXD_1_17 => FB_RXD_1_17, - FB_RXD_1_16 => FB_RXD_1_16, - FB_RXD_1_15 => FB_RXD_1_15, - FB_RXD_1_14 => FB_RXD_1_14, - FB_RXD_1_13 => FB_RXD_1_13, - FB_RXD_1_12 => FB_RXD_1_12, - FB_RXD_1_11 => FB_RXD_1_11, - FB_RXD_1_10 => FB_RXD_1_10, - FB_RXD_1_9 => FB_RXD_1_9, - FB_RXD_1_8 => FB_RXD_1_8, - FB_RXD_1_7 => FB_RXD_1_7, - FB_RXD_1_6 => FB_RXD_1_6, - FB_RXD_1_5 => FB_RXD_1_5, - FB_RXD_1_4 => FB_RXD_1_4, - FB_RXD_1_3 => FB_RXD_1_3, - FB_RXD_1_2 => FB_RXD_1_2, - FB_RXD_1_1 => FB_RXD_1_1, - FB_RXD_1_0 => FB_RXD_1_0, - FF_TXD_2_23 => FF_TXD_2_23, - FF_TXD_2_22 => FF_TXD_2_22, - FF_TXD_2_21 => FF_TXD_2_21, - FF_TXD_2_20 => FF_TXD_2_20, - FF_TXD_2_19 => FF_TXD_2_19, - FF_TXD_2_18 => FF_TXD_2_18, - FF_TXD_2_17 => FF_TXD_2_17, - FF_TXD_2_16 => FF_TXD_2_16, - FF_TXD_2_15 => FF_TXD_2_15, - FF_TXD_2_14 => FF_TXD_2_14, - FF_TXD_2_13 => FF_TXD_2_13, - FF_TXD_2_12 => FF_TXD_2_12, - FF_TXD_2_11 => FF_TXD_2_11, - FF_TXD_2_10 => FF_TXD_2_10, - FF_TXD_2_9 => FF_TXD_2_9, - FF_TXD_2_8 => FF_TXD_2_8, - FF_TXD_2_7 => FF_TXD_2_7, - FF_TXD_2_6 => FF_TXD_2_6, - FF_TXD_2_5 => FF_TXD_2_5, - FF_TXD_2_4 => FF_TXD_2_4, - FF_TXD_2_3 => FF_TXD_2_3, - FF_TXD_2_2 => FF_TXD_2_2, - FF_TXD_2_1 => FF_TXD_2_1, - FF_TXD_2_0 => FF_TXD_2_0, - FB_RXD_2_23 => FB_RXD_2_23, - FB_RXD_2_22 => FB_RXD_2_22, - FB_RXD_2_21 => FB_RXD_2_21, - FB_RXD_2_20 => FB_RXD_2_20, - FB_RXD_2_19 => FB_RXD_2_19, - FB_RXD_2_18 => FB_RXD_2_18, - FB_RXD_2_17 => FB_RXD_2_17, - FB_RXD_2_16 => FB_RXD_2_16, - FB_RXD_2_15 => FB_RXD_2_15, - FB_RXD_2_14 => FB_RXD_2_14, - FB_RXD_2_13 => FB_RXD_2_13, - FB_RXD_2_12 => FB_RXD_2_12, - FB_RXD_2_11 => FB_RXD_2_11, - FB_RXD_2_10 => FB_RXD_2_10, - FB_RXD_2_9 => FB_RXD_2_9, - FB_RXD_2_8 => FB_RXD_2_8, - FB_RXD_2_7 => FB_RXD_2_7, - FB_RXD_2_6 => FB_RXD_2_6, - FB_RXD_2_5 => FB_RXD_2_5, - FB_RXD_2_4 => FB_RXD_2_4, - FB_RXD_2_3 => FB_RXD_2_3, - FB_RXD_2_2 => FB_RXD_2_2, - FB_RXD_2_1 => FB_RXD_2_1, - FB_RXD_2_0 => FB_RXD_2_0, - FF_TXD_3_23 => FF_TXD_3_23, - FF_TXD_3_22 => FF_TXD_3_22, - FF_TXD_3_21 => FF_TXD_3_21, - FF_TXD_3_20 => FF_TXD_3_20, - FF_TXD_3_19 => FF_TXD_3_19, - FF_TXD_3_18 => FF_TXD_3_18, - FF_TXD_3_17 => FF_TXD_3_17, - FF_TXD_3_16 => FF_TXD_3_16, - FF_TXD_3_15 => FF_TXD_3_15, - FF_TXD_3_14 => FF_TXD_3_14, - FF_TXD_3_13 => FF_TXD_3_13, - FF_TXD_3_12 => FF_TXD_3_12, - FF_TXD_3_11 => FF_TXD_3_11, - FF_TXD_3_10 => FF_TXD_3_10, - FF_TXD_3_9 => FF_TXD_3_9, - FF_TXD_3_8 => FF_TXD_3_8, - FF_TXD_3_7 => FF_TXD_3_7, - FF_TXD_3_6 => FF_TXD_3_6, - FF_TXD_3_5 => FF_TXD_3_5, - FF_TXD_3_4 => FF_TXD_3_4, - FF_TXD_3_3 => FF_TXD_3_3, - FF_TXD_3_2 => FF_TXD_3_2, - FF_TXD_3_1 => FF_TXD_3_1, - FF_TXD_3_0 => FF_TXD_3_0, - FB_RXD_3_23 => FB_RXD_3_23, - FB_RXD_3_22 => FB_RXD_3_22, - FB_RXD_3_21 => FB_RXD_3_21, - FB_RXD_3_20 => FB_RXD_3_20, - FB_RXD_3_19 => FB_RXD_3_19, - FB_RXD_3_18 => FB_RXD_3_18, - FB_RXD_3_17 => FB_RXD_3_17, - FB_RXD_3_16 => FB_RXD_3_16, - FB_RXD_3_15 => FB_RXD_3_15, - FB_RXD_3_14 => FB_RXD_3_14, - FB_RXD_3_13 => FB_RXD_3_13, - FB_RXD_3_12 => FB_RXD_3_12, - FB_RXD_3_11 => FB_RXD_3_11, - FB_RXD_3_10 => FB_RXD_3_10, - FB_RXD_3_9 => FB_RXD_3_9, - FB_RXD_3_8 => FB_RXD_3_8, - FB_RXD_3_7 => FB_RXD_3_7, - FB_RXD_3_6 => FB_RXD_3_6, - FB_RXD_3_5 => FB_RXD_3_5, - FB_RXD_3_4 => FB_RXD_3_4, - FB_RXD_3_3 => FB_RXD_3_3, - FB_RXD_3_2 => FB_RXD_3_2, - FB_RXD_3_1 => FB_RXD_3_1, - FB_RXD_3_0 => FB_RXD_3_0, - TCK_FMAC => TCK_FMAC, - COUT_21 => COUT_21, - COUT_20 => COUT_20, - COUT_19 => COUT_19, - COUT_18 => COUT_18, - COUT_17 => COUT_17, - COUT_16 => COUT_16, - COUT_15 => COUT_15, - COUT_14 => COUT_14, - COUT_13 => COUT_13, - COUT_12 => COUT_12, - COUT_11 => COUT_11, - COUT_10 => COUT_10, - COUT_9 => COUT_9, - COUT_8 => COUT_8, - COUT_7 => COUT_7, - COUT_6 => COUT_6, - COUT_5 => COUT_5, - COUT_4 => COUT_4, - COUT_3 => COUT_3, - COUT_2 => COUT_2, - COUT_1 => COUT_1, - COUT_0 => COUT_0, - CIN_12 => CIN_12, - CIN_11 => CIN_11, - CIN_10 => CIN_10, - CIN_9 => CIN_9, - CIN_8 => CIN_8, - CIN_7 => CIN_7, - CIN_6 => CIN_6, - CIN_5 => CIN_5, - CIN_4 => CIN_4, - CIN_3 => CIN_3, - CIN_2 => CIN_2, - CIN_1 => CIN_1, - CIN_0 => CIN_0, - TESTCLK_MACO => TESTCLK_MACO -); - -end PCSA_arch; - ---synopsys translate_on - ---synopsys translate_off -library SC; -use SC.components.all; ---synopsys translate_on - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - - -entity serdes_fpga_ref_clk is - GENERIC (USER_CONFIG_FILE : String := "serdes_fpga_ref_clk.txt"); - port ( --- serdes clk pins -- - rxrefclk, refclk : in std_logic; - rxa_pclk, rxb_pclk : out std_logic; - hdinp_0, hdinn_0 : in std_logic; - hdoutp_0, hdoutn_0 : out std_logic; - tclk_0, rclk_0 : in std_logic; - tx_rst_0, rx_rst_0 : in std_logic; - ref_0_sclk, rx_0_sclk : out std_logic; - txd_0 : in std_logic_vector (15 downto 0); - tx_k_0, tx_force_disp_0, tx_disp_sel_0 : in std_logic_vector (1 downto 0); - rxd_0 : out std_logic_vector (15 downto 0); - rx_k_0, rx_disp_err_detect_0, rx_cv_detect_0 : out std_logic_vector (1 downto 0); - tx_crc_init_0 : in std_logic_vector (1 downto 0); - rx_crc_eop_0 : out std_logic_vector (1 downto 0); - word_align_en_0, mca_align_en_0, felb_0 : in std_logic; - lsm_en_0 : in std_logic; - lsm_status_0 : out std_logic; - - hdinp_1, hdinn_1 : in std_logic; - hdoutp_1, hdoutn_1 : out std_logic; - tclk_1, rclk_1 : in std_logic; - tx_rst_1, rx_rst_1 : in std_logic; - ref_1_sclk, rx_1_sclk : out std_logic; - txd_1 : in std_logic_vector (15 downto 0); - tx_k_1, tx_force_disp_1, tx_disp_sel_1 : in std_logic_vector (1 downto 0); - rxd_1 : out std_logic_vector (15 downto 0); - rx_k_1, rx_disp_err_detect_1, rx_cv_detect_1 : out std_logic_vector (1 downto 0); - tx_crc_init_1 : in std_logic_vector (1 downto 0); - rx_crc_eop_1 : out std_logic_vector (1 downto 0); - word_align_en_1, mca_align_en_1, felb_1 : in std_logic; - lsm_en_1 : in std_logic; - lsm_status_1 : out std_logic; - - hdinp_2, hdinn_2 : in std_logic; - hdoutp_2, hdoutn_2 : out std_logic; - tclk_2, rclk_2 : in std_logic; - tx_rst_2, rx_rst_2 : in std_logic; - ref_2_sclk, rx_2_sclk : out std_logic; - txd_2 : in std_logic_vector (15 downto 0); - tx_k_2, tx_force_disp_2, tx_disp_sel_2 : in std_logic_vector (1 downto 0); - rxd_2 : out std_logic_vector (15 downto 0); - rx_k_2, rx_disp_err_detect_2, rx_cv_detect_2 : out std_logic_vector (1 downto 0); - tx_crc_init_2 : in std_logic_vector (1 downto 0); - rx_crc_eop_2 : out std_logic_vector (1 downto 0); - word_align_en_2, mca_align_en_2, felb_2 : in std_logic; - lsm_en_2 : in std_logic; - lsm_status_2 : out std_logic; - - hdinp_3, hdinn_3 : in std_logic; - hdoutp_3, hdoutn_3 : out std_logic; - tclk_3, rclk_3 : in std_logic; - tx_rst_3, rx_rst_3 : in std_logic; - ref_3_sclk, rx_3_sclk : out std_logic; - txd_3 : in std_logic_vector (15 downto 0); - tx_k_3, tx_force_disp_3, tx_disp_sel_3 : in std_logic_vector (1 downto 0); - rxd_3 : out std_logic_vector (15 downto 0); - rx_k_3, rx_disp_err_detect_3, rx_cv_detect_3 : out std_logic_vector (1 downto 0); - tx_crc_init_3 : in std_logic_vector (1 downto 0); - rx_crc_eop_3 : out std_logic_vector (1 downto 0); - word_align_en_3, mca_align_en_3, felb_3 : in std_logic; - lsm_en_3 : in std_logic; - lsm_status_3 : out std_logic; - mca_resync_01 : in std_logic; - mca_aligned_01, mca_inskew_01, mca_outskew_01 : out std_logic; - mca_resync_23 : in std_logic; - mca_aligned_23, mca_inskew_23, mca_outskew_23 : out std_logic; - quad_rst, serdes_rst : in std_logic; - ref_pclk : out std_logic); - -end serdes_fpga_ref_clk; - -architecture serdes_fpga_ref_clk_arch of serdes_fpga_ref_clk is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - -component PCSA ---synopsys translate_off -GENERIC( - CONFIG_FILE : String - ); ---synopsys translate_on -port ( - HDINP0 : in std_logic; - HDINN0 : in std_logic; - HDINP1 : in std_logic; - HDINN1 : in std_logic; - HDINP2 : in std_logic; - HDINN2 : in std_logic; - HDINP3 : in std_logic; - HDINN3 : in std_logic; - HDOUTP0 : out std_logic; - HDOUTN0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTP3 : out std_logic; - HDOUTN3 : out std_logic; - REFCLKP : in std_logic; - REFCLKN : in std_logic; - RXREFCLKP : in std_logic; - RXREFCLKN : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_MACRO_RST : in std_logic; - - FFC_LANE_TX_RST0 : in std_logic; - FFC_LANE_TX_RST1 : in std_logic; - FFC_LANE_TX_RST2 : in std_logic; - FFC_LANE_TX_RST3 : in std_logic; - - FFC_LANE_RX_RST0 : in std_logic; - FFC_LANE_RX_RST1 : in std_logic; - FFC_LANE_RX_RST2 : in std_logic; - FFC_LANE_RX_RST3 : in std_logic; - - FFC_PCIE_EI_EN_0 : in std_logic; - FFC_PCIE_EI_EN_1 : in std_logic; - FFC_PCIE_EI_EN_2 : in std_logic; - FFC_PCIE_EI_EN_3 : in std_logic; - - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - - FFC_PCIE_TX_0 : in std_logic; - FFC_PCIE_TX_1 : in std_logic; - FFC_PCIE_TX_2 : in std_logic; - FFC_PCIE_TX_3 : in std_logic; - - FFC_PCIE_RX_0 : in std_logic; - FFC_PCIE_RX_1 : in std_logic; - FFC_PCIE_RX_2 : in std_logic; - FFC_PCIE_RX_3 : in std_logic; - - FFC_SD_0 : in std_logic; - FFC_SD_1 : in std_logic; - FFC_SD_2 : in std_logic; - FFC_SD_3 : in std_logic; - - FFC_EN_CGA_0 : in std_logic; - FFC_EN_CGA_1 : in std_logic; - FFC_EN_CGA_2 : in std_logic; - FFC_EN_CGA_3 : in std_logic; - - FFC_ALIGN_EN_0 : in std_logic; - FFC_ALIGN_EN_1 : in std_logic; - FFC_ALIGN_EN_2 : in std_logic; - FFC_ALIGN_EN_3 : in std_logic; - - FFC_AB_RESET : in std_logic; - FFC_CD_RESET : in std_logic; - - FFS_LS_STATUS_0 : out std_logic; - FFS_LS_STATUS_1 : out std_logic; - FFS_LS_STATUS_2 : out std_logic; - FFS_LS_STATUS_3 : out std_logic; - - FFS_AB_STATUS : out std_logic; - FFS_CD_STATUS : out std_logic; - - FFS_AB_ALIGNED : out std_logic; - FFS_CD_ALIGNED : out std_logic; - - FFS_AB_FAILED : out std_logic; - FFS_CD_FAILED : out std_logic; - - FFS_RLOS_LO0 : out std_logic; - FFS_RLOS_LO1 : out std_logic; - FFS_RLOS_LO2 : out std_logic; - FFS_RLOS_LO3 : out std_logic; - - FFC_FB_LB_0 : in std_logic; - FFC_FB_LB_1 : in std_logic; - FFC_FB_LB_2 : in std_logic; - FFC_FB_LB_3 : in std_logic; - - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - - FFS_CC_ORUN_0 : out std_logic; - FFS_CC_ORUN_1 : out std_logic; - FFS_CC_ORUN_2 : out std_logic; - FFS_CC_ORUN_3 : out std_logic; - - FFS_CC_URUN_0 : out std_logic; - FFS_CC_URUN_1 : out std_logic; - FFS_CC_URUN_2 : out std_logic; - FFS_CC_URUN_3 : out std_logic; - - FFC_CK_CORE_TX : in std_logic; - FFC_CK_CORE_RX : in std_logic; - RDATAO_7 : out std_logic; - RDATAO_6 : out std_logic; - RDATAO_5 : out std_logic; - RDATAO_4 : out std_logic; - RDATAO_3 : out std_logic; - RDATAO_2 : out std_logic; - RDATAO_1 : out std_logic; - RDATAO_0 : out std_logic; - INTO : out std_logic; - - ADDRI_7 : in std_logic; - ADDRI_6 : in std_logic; - ADDRI_5 : in std_logic; - ADDRI_4 : in std_logic; - ADDRI_3 : in std_logic; - ADDRI_2 : in std_logic; - ADDRI_1 : in std_logic; - ADDRI_0 : in std_logic; - WDATAI_7 : in std_logic; - WDATAI_6 : in std_logic; - WDATAI_5 : in std_logic; - WDATAI_4 : in std_logic; - WDATAI_3 : in std_logic; - WDATAI_2 : in std_logic; - WDATAI_1 : in std_logic; - WDATAI_0 : in std_logic; - RDI : in std_logic; - WSTBI : in std_logic; - - CS_CHIF_0 : in std_logic; - CS_CHIF_1 : in std_logic; - CS_CHIF_2 : in std_logic; - CS_CHIF_3 : in std_logic; - CS_QIF : in std_logic; - - QUAD_ID_1 : in std_logic; - QUAD_ID_0 : in std_logic; - - FF_SYSCLK_P1 : out std_logic; - - FF_SYSCLK0 : out std_logic; - FF_SYSCLK1 : out std_logic; - FF_SYSCLK2 : out std_logic; - FF_SYSCLK3 : out std_logic; - - FF_RXCLK_P1 : out std_logic; - FF_RXCLK_P2 : out std_logic; - - FF_RXCLK0 : out std_logic; - FF_RXCLK1 : out std_logic; - FF_RXCLK2 : out std_logic; - FF_RXCLK3 : out std_logic; - - QUAD_CLK : out std_logic; - - GRP_CLK_P1_3 : in std_logic; - GRP_CLK_P1_2 : in std_logic; - GRP_CLK_P1_1 : in std_logic; - GRP_CLK_P1_0 : in std_logic; - - GRP_CLK_P2_3 : in std_logic; - GRP_CLK_P2_2 : in std_logic; - GRP_CLK_P2_1 : in std_logic; - GRP_CLK_P2_0 : in std_logic; - - GRP_START_3 : in std_logic; - GRP_START_2 : in std_logic; - GRP_START_1 : in std_logic; - GRP_START_0 : in std_logic; - - GRP_DONE_3 : in std_logic; - GRP_DONE_2 : in std_logic; - GRP_DONE_1 : in std_logic; - GRP_DONE_0 : in std_logic; - - GRP_DESKEW_ERROR_3 : in std_logic; - GRP_DESKEW_ERROR_2 : in std_logic; - GRP_DESKEW_ERROR_1 : in std_logic; - GRP_DESKEW_ERROR_0 : in std_logic; - - IQA_START_LS : out std_logic; - IQA_DONE_LS : out std_logic; - IQA_AND_FP1_LS : out std_logic; - IQA_AND_FP0_LS : out std_logic; - IQA_OR_FP1_LS : out std_logic; - IQA_OR_FP0_LS : out std_logic; - IQA_RST_N : out std_logic; - - FF_TCLK0 : in std_logic; - FF_TCLK1 : in std_logic; - FF_TCLK2 : in std_logic; - FF_TCLK3 : in std_logic; - - FF_RCLK0 : in std_logic; - FF_RCLK1 : in std_logic; - FF_RCLK2 : in std_logic; - FF_RCLK3 : in std_logic; - TCK_FMACP : in std_logic; - - FF_TXD_0_23 : in std_logic; - FF_TXD_0_22 : in std_logic; - FF_TXD_0_21 : in std_logic; - FF_TXD_0_20 : in std_logic; - FF_TXD_0_19 : in std_logic; - FF_TXD_0_18 : in std_logic; - FF_TXD_0_17 : in std_logic; - FF_TXD_0_16 : in std_logic; - FF_TXD_0_15 : in std_logic; - FF_TXD_0_14 : in std_logic; - FF_TXD_0_13 : in std_logic; - FF_TXD_0_12 : in std_logic; - FF_TXD_0_11 : in std_logic; - FF_TXD_0_10 : in std_logic; - FF_TXD_0_9 : in std_logic; - FF_TXD_0_8 : in std_logic; - FF_TXD_0_7 : in std_logic; - FF_TXD_0_6 : in std_logic; - FF_TXD_0_5 : in std_logic; - FF_TXD_0_4 : in std_logic; - FF_TXD_0_3 : in std_logic; - FF_TXD_0_2 : in std_logic; - FF_TXD_0_1 : in std_logic; - FF_TXD_0_0 : in std_logic; - FB_RXD_0_23 : out std_logic; - FB_RXD_0_22 : out std_logic; - FB_RXD_0_21 : out std_logic; - FB_RXD_0_20 : out std_logic; - FB_RXD_0_19 : out std_logic; - FB_RXD_0_18 : out std_logic; - FB_RXD_0_17 : out std_logic; - FB_RXD_0_16 : out std_logic; - FB_RXD_0_15 : out std_logic; - FB_RXD_0_14 : out std_logic; - FB_RXD_0_13 : out std_logic; - FB_RXD_0_12 : out std_logic; - FB_RXD_0_11 : out std_logic; - FB_RXD_0_10 : out std_logic; - FB_RXD_0_9 : out std_logic; - FB_RXD_0_8 : out std_logic; - FB_RXD_0_7 : out std_logic; - FB_RXD_0_6 : out std_logic; - FB_RXD_0_5 : out std_logic; - FB_RXD_0_4 : out std_logic; - FB_RXD_0_3 : out std_logic; - FB_RXD_0_2 : out std_logic; - FB_RXD_0_1 : out std_logic; - FB_RXD_0_0 : out std_logic; - FF_TXD_1_23 : in std_logic; - FF_TXD_1_22 : in std_logic; - FF_TXD_1_21 : in std_logic; - FF_TXD_1_20 : in std_logic; - FF_TXD_1_19 : in std_logic; - FF_TXD_1_18 : in std_logic; - FF_TXD_1_17 : in std_logic; - FF_TXD_1_16 : in std_logic; - FF_TXD_1_15 : in std_logic; - FF_TXD_1_14 : in std_logic; - FF_TXD_1_13 : in std_logic; - FF_TXD_1_12 : in std_logic; - FF_TXD_1_11 : in std_logic; - FF_TXD_1_10 : in std_logic; - FF_TXD_1_9 : in std_logic; - FF_TXD_1_8 : in std_logic; - FF_TXD_1_7 : in std_logic; - FF_TXD_1_6 : in std_logic; - FF_TXD_1_5 : in std_logic; - FF_TXD_1_4 : in std_logic; - FF_TXD_1_3 : in std_logic; - FF_TXD_1_2 : in std_logic; - FF_TXD_1_1 : in std_logic; - FF_TXD_1_0 : in std_logic; - FB_RXD_1_23 : out std_logic; - FB_RXD_1_22 : out std_logic; - FB_RXD_1_21 : out std_logic; - FB_RXD_1_20 : out std_logic; - FB_RXD_1_19 : out std_logic; - FB_RXD_1_18 : out std_logic; - FB_RXD_1_17 : out std_logic; - FB_RXD_1_16 : out std_logic; - FB_RXD_1_15 : out std_logic; - FB_RXD_1_14 : out std_logic; - FB_RXD_1_13 : out std_logic; - FB_RXD_1_12 : out std_logic; - FB_RXD_1_11 : out std_logic; - FB_RXD_1_10 : out std_logic; - FB_RXD_1_9 : out std_logic; - FB_RXD_1_8 : out std_logic; - FB_RXD_1_7 : out std_logic; - FB_RXD_1_6 : out std_logic; - FB_RXD_1_5 : out std_logic; - FB_RXD_1_4 : out std_logic; - FB_RXD_1_3 : out std_logic; - FB_RXD_1_2 : out std_logic; - FB_RXD_1_1 : out std_logic; - FB_RXD_1_0 : out std_logic; - FF_TXD_2_23 : in std_logic; - FF_TXD_2_22 : in std_logic; - FF_TXD_2_21 : in std_logic; - FF_TXD_2_20 : in std_logic; - FF_TXD_2_19 : in std_logic; - FF_TXD_2_18 : in std_logic; - FF_TXD_2_17 : in std_logic; - FF_TXD_2_16 : in std_logic; - FF_TXD_2_15 : in std_logic; - FF_TXD_2_14 : in std_logic; - FF_TXD_2_13 : in std_logic; - FF_TXD_2_12 : in std_logic; - FF_TXD_2_11 : in std_logic; - FF_TXD_2_10 : in std_logic; - FF_TXD_2_9 : in std_logic; - FF_TXD_2_8 : in std_logic; - FF_TXD_2_7 : in std_logic; - FF_TXD_2_6 : in std_logic; - FF_TXD_2_5 : in std_logic; - FF_TXD_2_4 : in std_logic; - FF_TXD_2_3 : in std_logic; - FF_TXD_2_2 : in std_logic; - FF_TXD_2_1 : in std_logic; - FF_TXD_2_0 : in std_logic; - FB_RXD_2_23 : out std_logic; - FB_RXD_2_22 : out std_logic; - FB_RXD_2_21 : out std_logic; - FB_RXD_2_20 : out std_logic; - FB_RXD_2_19 : out std_logic; - FB_RXD_2_18 : out std_logic; - FB_RXD_2_17 : out std_logic; - FB_RXD_2_16 : out std_logic; - FB_RXD_2_15 : out std_logic; - FB_RXD_2_14 : out std_logic; - FB_RXD_2_13 : out std_logic; - FB_RXD_2_12 : out std_logic; - FB_RXD_2_11 : out std_logic; - FB_RXD_2_10 : out std_logic; - FB_RXD_2_9 : out std_logic; - FB_RXD_2_8 : out std_logic; - FB_RXD_2_7 : out std_logic; - FB_RXD_2_6 : out std_logic; - FB_RXD_2_5 : out std_logic; - FB_RXD_2_4 : out std_logic; - FB_RXD_2_3 : out std_logic; - FB_RXD_2_2 : out std_logic; - FB_RXD_2_1 : out std_logic; - FB_RXD_2_0 : out std_logic; - FF_TXD_3_23 : in std_logic; - FF_TXD_3_22 : in std_logic; - FF_TXD_3_21 : in std_logic; - FF_TXD_3_20 : in std_logic; - FF_TXD_3_19 : in std_logic; - FF_TXD_3_18 : in std_logic; - FF_TXD_3_17 : in std_logic; - FF_TXD_3_16 : in std_logic; - FF_TXD_3_15 : in std_logic; - FF_TXD_3_14 : in std_logic; - FF_TXD_3_13 : in std_logic; - FF_TXD_3_12 : in std_logic; - FF_TXD_3_11 : in std_logic; - FF_TXD_3_10 : in std_logic; - FF_TXD_3_9 : in std_logic; - FF_TXD_3_8 : in std_logic; - FF_TXD_3_7 : in std_logic; - FF_TXD_3_6 : in std_logic; - FF_TXD_3_5 : in std_logic; - FF_TXD_3_4 : in std_logic; - FF_TXD_3_3 : in std_logic; - FF_TXD_3_2 : in std_logic; - FF_TXD_3_1 : in std_logic; - FF_TXD_3_0 : in std_logic; - FB_RXD_3_23 : out std_logic; - FB_RXD_3_22 : out std_logic; - FB_RXD_3_21 : out std_logic; - FB_RXD_3_20 : out std_logic; - FB_RXD_3_19 : out std_logic; - FB_RXD_3_18 : out std_logic; - FB_RXD_3_17 : out std_logic; - FB_RXD_3_16 : out std_logic; - FB_RXD_3_15 : out std_logic; - FB_RXD_3_14 : out std_logic; - FB_RXD_3_13 : out std_logic; - FB_RXD_3_12 : out std_logic; - FB_RXD_3_11 : out std_logic; - FB_RXD_3_10 : out std_logic; - FB_RXD_3_9 : out std_logic; - FB_RXD_3_8 : out std_logic; - FB_RXD_3_7 : out std_logic; - FB_RXD_3_6 : out std_logic; - FB_RXD_3_5 : out std_logic; - FB_RXD_3_4 : out std_logic; - FB_RXD_3_3 : out std_logic; - FB_RXD_3_2 : out std_logic; - FB_RXD_3_1 : out std_logic; - FB_RXD_3_0 : out std_logic; - TCK_FMAC : out std_logic; - BS4PAD_0 : out std_logic; - BS4PAD_1 : out std_logic; - BS4PAD_2 : out std_logic; - BS4PAD_3 : out std_logic; - COUT_21 : out std_logic; - COUT_20 : out std_logic; - COUT_19 : out std_logic; - COUT_18 : out std_logic; - COUT_17 : out std_logic; - COUT_16 : out std_logic; - COUT_15 : out std_logic; - COUT_14 : out std_logic; - COUT_13 : out std_logic; - COUT_12 : out std_logic; - COUT_11 : out std_logic; - COUT_10 : out std_logic; - COUT_9 : out std_logic; - COUT_8 : out std_logic; - COUT_7 : out std_logic; - COUT_6 : out std_logic; - COUT_5 : out std_logic; - COUT_4 : out std_logic; - COUT_3 : out std_logic; - COUT_2 : out std_logic; - COUT_1 : out std_logic; - COUT_0 : out std_logic; - CIN_12 : in std_logic; - CIN_11 : in std_logic; - CIN_10 : in std_logic; - CIN_9 : in std_logic; - CIN_8 : in std_logic; - CIN_7 : in std_logic; - CIN_6 : in std_logic; - CIN_5 : in std_logic; - CIN_4 : in std_logic; - CIN_3 : in std_logic; - CIN_2 : in std_logic; - CIN_1 : in std_logic; - CIN_0 : in std_logic; - TESTCLK_MACO : in std_logic -); -end component; - attribute IS_ASB: string; - attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd"; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE; - attribute CH0_RX_MAXRATE: string; - attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH1_RX_MAXRATE: string; - attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH2_RX_MAXRATE: string; - attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH3_RX_MAXRATE: string; - attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3"; - attribute CH0_TX_MAXRATE: string; - attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute CH1_TX_MAXRATE: string; - attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute CH2_TX_MAXRATE: string; - attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute CH3_TX_MAXRATE: string; - attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2"; - attribute AMP_BOOST: string; - attribute AMP_BOOST of PCSA_INST : label is "DISABLED"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN"; - -signal fpsc_vlo : std_logic := '0'; - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); - --- pcs_quad instance -PCSA_INST : PCSA ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - RXREFCLKP => fpsc_vlo, - RXREFCLKN => fpsc_vlo, - FFC_CK_CORE_RX => rxrefclk, - FFC_CK_CORE_TX => refclk, - CS_CHIF_0 => fpsc_vlo, - CS_CHIF_1 => fpsc_vlo, - CS_CHIF_2 => fpsc_vlo, - CS_CHIF_3 => fpsc_vlo, - CS_QIF => fpsc_vlo, - QUAD_ID_0 => fpsc_vlo, - QUAD_ID_1 => fpsc_vlo, - ADDRI_0 => fpsc_vlo, - ADDRI_1 => fpsc_vlo, - ADDRI_2 => fpsc_vlo, - ADDRI_3 => fpsc_vlo, - ADDRI_4 => fpsc_vlo, - ADDRI_5 => fpsc_vlo, - ADDRI_6 => fpsc_vlo, - ADDRI_7 => fpsc_vlo, - WDATAI_0 => fpsc_vlo, - WDATAI_1 => fpsc_vlo, - WDATAI_2 => fpsc_vlo, - WDATAI_3 => fpsc_vlo, - WDATAI_4 => fpsc_vlo, - WDATAI_5 => fpsc_vlo, - WDATAI_6 => fpsc_vlo, - WDATAI_7 => fpsc_vlo, - RDI => fpsc_vlo, - WSTBI => fpsc_vlo, - GRP_CLK_P1_0 => fpsc_vlo, - GRP_CLK_P1_1 => fpsc_vlo, - GRP_CLK_P1_2 => fpsc_vlo, - GRP_CLK_P1_3 => fpsc_vlo, - GRP_CLK_P2_0 => fpsc_vlo, - GRP_CLK_P2_1 => fpsc_vlo, - GRP_CLK_P2_2 => fpsc_vlo, - GRP_CLK_P2_3 => fpsc_vlo, - GRP_START_0 => fpsc_vlo, - GRP_START_1 => fpsc_vlo, - GRP_START_2 => fpsc_vlo, - GRP_START_3 => fpsc_vlo, - GRP_DONE_0 => fpsc_vlo, - GRP_DONE_1 => fpsc_vlo, - GRP_DONE_2 => fpsc_vlo, - GRP_DONE_3 => fpsc_vlo, - GRP_DESKEW_ERROR_0 => fpsc_vlo, - GRP_DESKEW_ERROR_1 => fpsc_vlo, - GRP_DESKEW_ERROR_2 => fpsc_vlo, - GRP_DESKEW_ERROR_3 => fpsc_vlo, --- to sysbusa - RDATAO_0 => open, - RDATAO_1 => open, - RDATAO_2 => open, - RDATAO_3 => open, - RDATAO_4 => open, - RDATAO_5 => open, - RDATAO_6 => open, - RDATAO_7 => open, - INTO => open, - QUAD_CLK => open, - IQA_START_LS => open, - IQA_DONE_LS => open, - IQA_AND_FP1_LS => open, - IQA_AND_FP0_LS => open, - IQA_OR_FP1_LS => open, - IQA_OR_FP0_LS => open, - IQA_RST_N => open, - - FF_TXD_0_19 => txd_0(15), - FF_TXD_0_18 => txd_0(14), - FF_TXD_0_17 => txd_0(13), - FF_TXD_0_16 => txd_0(12), - FF_TXD_0_15 => txd_0(11), - FF_TXD_0_14 => txd_0(10), - FF_TXD_0_13 => txd_0(9), - FF_TXD_0_12 => txd_0(8), - FF_TXD_0_7 => txd_0(7), - FF_TXD_0_6 => txd_0(6), - FF_TXD_0_5 => txd_0(5), - FF_TXD_0_4 => txd_0(4), - FF_TXD_0_3 => txd_0(3), - FF_TXD_0_2 => txd_0(2), - FF_TXD_0_1 => txd_0(1), - FF_TXD_0_0 => txd_0(0), - FB_RXD_0_19 => rxd_0(15), - FB_RXD_0_18 => rxd_0(14), - FB_RXD_0_17 => rxd_0(13), - FB_RXD_0_16 => rxd_0(12), - FB_RXD_0_15 => rxd_0(11), - FB_RXD_0_14 => rxd_0(10), - FB_RXD_0_13 => rxd_0(9), - FB_RXD_0_12 => rxd_0(8), - FB_RXD_0_7 => rxd_0(7), - FB_RXD_0_6 => rxd_0(6), - FB_RXD_0_5 => rxd_0(5), - FB_RXD_0_4 => rxd_0(4), - FB_RXD_0_3 => rxd_0(3), - FB_RXD_0_2 => rxd_0(2), - FB_RXD_0_1 => rxd_0(1), - FB_RXD_0_0 => rxd_0(0), - - FF_TXD_0_20 => tx_k_0(1), - FF_TXD_0_8 => tx_k_0(0), - FB_RXD_0_20 => rx_k_0(1), - FB_RXD_0_8 => rx_k_0(0), - - FF_TXD_0_21 => tx_force_disp_0(1), - FF_TXD_0_9 => tx_force_disp_0(0), - - FF_TXD_0_22 => tx_disp_sel_0(1), - FF_TXD_0_10 => tx_disp_sel_0(0), - - FF_TXD_0_23 => tx_crc_init_0(1), - FF_TXD_0_11 => tx_crc_init_0(0), - - FB_RXD_0_21 => rx_disp_err_detect_0(1), - FB_RXD_0_9 => rx_disp_err_detect_0(0), - - FB_RXD_0_22 => rx_cv_detect_0(1), - FB_RXD_0_10 => rx_cv_detect_0(0), - - FB_RXD_0_23 => rx_crc_eop_0(1), - FB_RXD_0_11 => rx_crc_eop_0(0), - - FF_TXD_1_19 => txd_1(15), - FF_TXD_1_18 => txd_1(14), - FF_TXD_1_17 => txd_1(13), - FF_TXD_1_16 => txd_1(12), - FF_TXD_1_15 => txd_1(11), - FF_TXD_1_14 => txd_1(10), - FF_TXD_1_13 => txd_1(9), - FF_TXD_1_12 => txd_1(8), - FF_TXD_1_7 => txd_1(7), - FF_TXD_1_6 => txd_1(6), - FF_TXD_1_5 => txd_1(5), - FF_TXD_1_4 => txd_1(4), - FF_TXD_1_3 => txd_1(3), - FF_TXD_1_2 => txd_1(2), - FF_TXD_1_1 => txd_1(1), - FF_TXD_1_0 => txd_1(0), - FB_RXD_1_19 => rxd_1(15), - FB_RXD_1_18 => rxd_1(14), - FB_RXD_1_17 => rxd_1(13), - FB_RXD_1_16 => rxd_1(12), - FB_RXD_1_15 => rxd_1(11), - FB_RXD_1_14 => rxd_1(10), - FB_RXD_1_13 => rxd_1(9), - FB_RXD_1_12 => rxd_1(8), - FB_RXD_1_7 => rxd_1(7), - FB_RXD_1_6 => rxd_1(6), - FB_RXD_1_5 => rxd_1(5), - FB_RXD_1_4 => rxd_1(4), - FB_RXD_1_3 => rxd_1(3), - FB_RXD_1_2 => rxd_1(2), - FB_RXD_1_1 => rxd_1(1), - FB_RXD_1_0 => rxd_1(0), - - FF_TXD_1_20 => tx_k_1(1), - FF_TXD_1_8 => tx_k_1(0), - FB_RXD_1_20 => rx_k_1(1), - FB_RXD_1_8 => rx_k_1(0), - - FF_TXD_1_21 => tx_force_disp_1(1), - FF_TXD_1_9 => tx_force_disp_1(0), - - FF_TXD_1_22 => tx_disp_sel_1(1), - FF_TXD_1_10 => tx_disp_sel_1(0), - FF_TXD_1_23 => tx_crc_init_1(1), - FF_TXD_1_11 => tx_crc_init_1(0), - - FB_RXD_1_21 => rx_disp_err_detect_1(1), - FB_RXD_1_9 => rx_disp_err_detect_1(0), - - FB_RXD_1_22 => rx_cv_detect_1(1), - FB_RXD_1_10 => rx_cv_detect_1(0), - - FB_RXD_1_23 => rx_crc_eop_1(1), - FB_RXD_1_11 => rx_crc_eop_1(0), - - FF_TXD_2_19 => txd_2(15), - FF_TXD_2_18 => txd_2(14), - FF_TXD_2_17 => txd_2(13), - FF_TXD_2_16 => txd_2(12), - FF_TXD_2_15 => txd_2(11), - FF_TXD_2_14 => txd_2(10), - FF_TXD_2_13 => txd_2(9), - FF_TXD_2_12 => txd_2(8), - FF_TXD_2_7 => txd_2(7), - FF_TXD_2_6 => txd_2(6), - FF_TXD_2_5 => txd_2(5), - FF_TXD_2_4 => txd_2(4), - FF_TXD_2_3 => txd_2(3), - FF_TXD_2_2 => txd_2(2), - FF_TXD_2_1 => txd_2(1), - FF_TXD_2_0 => txd_2(0), - FB_RXD_2_19 => rxd_2(15), - FB_RXD_2_18 => rxd_2(14), - FB_RXD_2_17 => rxd_2(13), - FB_RXD_2_16 => rxd_2(12), - FB_RXD_2_15 => rxd_2(11), - FB_RXD_2_14 => rxd_2(10), - FB_RXD_2_13 => rxd_2(9), - FB_RXD_2_12 => rxd_2(8), - FB_RXD_2_7 => rxd_2(7), - FB_RXD_2_6 => rxd_2(6), - FB_RXD_2_5 => rxd_2(5), - FB_RXD_2_4 => rxd_2(4), - FB_RXD_2_3 => rxd_2(3), - FB_RXD_2_2 => rxd_2(2), - FB_RXD_2_1 => rxd_2(1), - FB_RXD_2_0 => rxd_2(0), - - FF_TXD_2_20 => tx_k_2(1), - FF_TXD_2_8 => tx_k_2(0), - FB_RXD_2_20 => rx_k_2(1), - FB_RXD_2_8 => rx_k_2(0), - - FF_TXD_2_21 => tx_force_disp_2(1), - FF_TXD_2_9 => tx_force_disp_2(0), - - FF_TXD_2_22 => tx_disp_sel_2(1), - FF_TXD_2_10 => tx_disp_sel_2(0), - FF_TXD_2_23 => tx_crc_init_2(1), - FF_TXD_2_11 => tx_crc_init_2(0), - - FB_RXD_2_21 => rx_disp_err_detect_2(1), - FB_RXD_2_9 => rx_disp_err_detect_2(0), - - FB_RXD_2_22 => rx_cv_detect_2(1), - FB_RXD_2_10 => rx_cv_detect_2(0), - - FB_RXD_2_23 => rx_crc_eop_2(1), - FB_RXD_2_11 => rx_crc_eop_2(0), - - FF_TXD_3_19 => txd_3(15), - FF_TXD_3_18 => txd_3(14), - FF_TXD_3_17 => txd_3(13), - FF_TXD_3_16 => txd_3(12), - FF_TXD_3_15 => txd_3(11), - FF_TXD_3_14 => txd_3(10), - FF_TXD_3_13 => txd_3(9), - FF_TXD_3_12 => txd_3(8), - FF_TXD_3_7 => txd_3(7), - FF_TXD_3_6 => txd_3(6), - FF_TXD_3_5 => txd_3(5), - FF_TXD_3_4 => txd_3(4), - FF_TXD_3_3 => txd_3(3), - FF_TXD_3_2 => txd_3(2), - FF_TXD_3_1 => txd_3(1), - FF_TXD_3_0 => txd_3(0), - FB_RXD_3_19 => rxd_3(15), - FB_RXD_3_18 => rxd_3(14), - FB_RXD_3_17 => rxd_3(13), - FB_RXD_3_16 => rxd_3(12), - FB_RXD_3_15 => rxd_3(11), - FB_RXD_3_14 => rxd_3(10), - FB_RXD_3_13 => rxd_3(9), - FB_RXD_3_12 => rxd_3(8), - FB_RXD_3_7 => rxd_3(7), - FB_RXD_3_6 => rxd_3(6), - FB_RXD_3_5 => rxd_3(5), - FB_RXD_3_4 => rxd_3(4), - FB_RXD_3_3 => rxd_3(3), - FB_RXD_3_2 => rxd_3(2), - FB_RXD_3_1 => rxd_3(1), - FB_RXD_3_0 => rxd_3(0), - - FF_TXD_3_20 => tx_k_3(1), - FF_TXD_3_8 => tx_k_3(0), - FB_RXD_3_20 => rx_k_3(1), - FB_RXD_3_8 => rx_k_3(0), - - FF_TXD_3_21 => tx_force_disp_3(1), - FF_TXD_3_9 => tx_force_disp_3(0), - - FF_TXD_3_22 => tx_disp_sel_3(1), - FF_TXD_3_10 => tx_disp_sel_3(0), - FF_TXD_3_23 => tx_crc_init_3(1), - FF_TXD_3_11 => tx_crc_init_3(0), - - FB_RXD_3_21 => rx_disp_err_detect_3(1), - FB_RXD_3_9 => rx_disp_err_detect_3(0), - - FB_RXD_3_22 => rx_cv_detect_3(1), - FB_RXD_3_10 => rx_cv_detect_3(0), - - FB_RXD_3_23 => rx_crc_eop_3(1), - FB_RXD_3_11 => rx_crc_eop_3(0), - - HDINP0 => hdinp_0, - HDINN0 => hdinn_0, - HDOUTP0 => hdoutp_0, - HDOUTN0 => hdoutn_0, - FF_SYSCLK0 => ref_0_sclk, - FF_RXCLK0 => rx_0_sclk, - FFC_LANE_TX_RST0 => tx_rst_0, - FFC_LANE_RX_RST0 => rx_rst_0, - FF_TCLK0 => tclk_0, - FF_RCLK0 => rclk_0, - HDINP1 => hdinp_1, - HDINN1 => hdinn_1, - HDOUTP1 => hdoutp_1, - HDOUTN1 => hdoutn_1, - FF_SYSCLK1 => ref_1_sclk, - FF_RXCLK1 => rx_1_sclk, - FFC_LANE_TX_RST1 => tx_rst_1, - FFC_LANE_RX_RST1 => rx_rst_1, - FF_TCLK1 => tclk_1, - FF_RCLK1 => rclk_1, - HDINP2 => hdinp_2, - HDINN2 => hdinn_2, - HDOUTP2 => hdoutp_2, - HDOUTN2 => hdoutn_2, - FF_SYSCLK2 => ref_2_sclk, - FF_RXCLK2 => rx_2_sclk, - FFC_LANE_TX_RST2 => tx_rst_2, - FFC_LANE_RX_RST2 => rx_rst_2, - FF_TCLK2 => tclk_2, - FF_RCLK2 => rclk_2, - HDINP3 => hdinp_3, - HDINN3 => hdinn_3, - HDOUTP3 => hdoutp_3, - HDOUTN3 => hdoutn_3, - FF_SYSCLK3 => ref_3_sclk, - FF_RXCLK3 => rx_3_sclk, - FFC_LANE_TX_RST3 => tx_rst_3, - FFC_LANE_RX_RST3 => rx_rst_3, - FF_TCLK3 => tclk_3, - FF_RCLK3 => rclk_3, - - FFC_PCIE_EI_EN_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCIE_TX_0 => fpsc_vlo, - FFC_PCIE_RX_0 => fpsc_vlo, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFC_PCIE_EI_EN_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCIE_TX_1 => fpsc_vlo, - FFC_PCIE_RX_1 => fpsc_vlo, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFC_PCIE_EI_EN_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCIE_TX_2 => fpsc_vlo, - FFC_PCIE_RX_2 => fpsc_vlo, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFC_PCIE_EI_EN_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCIE_TX_3 => fpsc_vlo, - FFC_PCIE_RX_3 => fpsc_vlo, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - - FFC_SD_0 => lsm_en_0, - FFC_SD_1 => lsm_en_1, - FFC_SD_2 => lsm_en_2, - FFC_SD_3 => lsm_en_3, - - FFC_EN_CGA_0 => word_align_en_0, - FFC_EN_CGA_1 => word_align_en_1, - FFC_EN_CGA_2 => word_align_en_2, - FFC_EN_CGA_3 => word_align_en_3, - - FFC_ALIGN_EN_0 => mca_align_en_0, - FFC_ALIGN_EN_1 => mca_align_en_1, - FFC_ALIGN_EN_2 => mca_align_en_2, - FFC_ALIGN_EN_3 => mca_align_en_3, - - FFC_FB_LB_0 => felb_0, - FFC_FB_LB_1 => felb_1, - FFC_FB_LB_2 => felb_2, - FFC_FB_LB_3 => felb_3, - - FFS_LS_STATUS_0 => lsm_status_0, - FFS_LS_STATUS_1 => lsm_status_1, - FFS_LS_STATUS_2 => lsm_status_2, - FFS_LS_STATUS_3 => lsm_status_3, - - FFS_CC_ORUN_0 => open, - FFS_CC_URUN_0 => open, - FFS_CC_ORUN_1 => open, - FFS_CC_URUN_1 => open, - FFS_CC_ORUN_2 => open, - FFS_CC_URUN_2 => open, - FFS_CC_ORUN_3 => open, - FFS_CC_URUN_3 => open, - - FFC_AB_RESET => mca_resync_01, - - FFS_AB_STATUS => mca_aligned_01, - FFS_AB_ALIGNED => mca_inskew_01, - FFS_AB_FAILED => mca_outskew_01, - - FFC_CD_RESET => mca_resync_23, - FFS_CD_STATUS => mca_aligned_23, - - FFS_CD_ALIGNED => mca_inskew_23, - FFS_CD_FAILED => mca_outskew_23, - BS4PAD_0 => open, - BS4PAD_1 => open, - BS4PAD_2 => open, - BS4PAD_3 => open, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - TCK_FMAC => open, - TCK_FMACP => fpsc_vlo, - FF_SYSCLK_P1 => ref_pclk, - FF_RXCLK_P1 => rxa_pclk, - FF_RXCLK_P2 => rxb_pclk, - FFC_QUAD_RST => quad_rst, - FFS_RLOS_LO0 => open, - FFS_RLOS_LO1 => open, - FFS_RLOS_LO2 => open, - FFS_RLOS_LO3 => open, - COUT_21 => open, - COUT_20 => open, - COUT_19 => open, - COUT_18 => open, - COUT_17 => open, - COUT_16 => open, - COUT_15 => open, - COUT_14 => open, - COUT_13 => open, - COUT_12 => open, - COUT_11 => open, - COUT_10 => open, - COUT_9 => open, - COUT_8 => open, - COUT_7 => open, - COUT_6 => open, - COUT_5 => open, - COUT_4 => open, - COUT_3 => open, - COUT_2 => open, - COUT_1 => open, - COUT_0 => open, - CIN_12 => fpsc_vlo, - CIN_11 => fpsc_vlo, - CIN_10 => fpsc_vlo, - CIN_9 => fpsc_vlo, - CIN_8 => fpsc_vlo, - CIN_7 => fpsc_vlo, - CIN_6 => fpsc_vlo, - CIN_5 => fpsc_vlo, - CIN_4 => fpsc_vlo, - CIN_3 => fpsc_vlo, - CIN_2 => fpsc_vlo, - CIN_1 => fpsc_vlo, - CIN_0 => fpsc_vlo, - TESTCLK_MACO => fpsc_vlo, - FFC_MACRO_RST => serdes_rst); - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on - -end serdes_fpga_ref_clk_arch ; diff --git a/optical_link/setup_env b/optical_link/setup_env deleted file mode 100755 index 8b7b31e..0000000 --- a/optical_link/setup_env +++ /dev/null @@ -1,28 +0,0 @@ -export ISPLEVER_PATH=/opt/lattice/isplever7.0/isptools - -export ISPCPLD=$ISPLEVER_PATH/ispcpld -export ISPJTOOLS=$ISPLEVER_PATH/ispjtools -export PDSPLUS=$ISPLEVER_PATH/ispcomp -export ISPFPGA=$ISPLEVER_PATH/ispfpga -export ISPVM_DIR=$ISPLEVER_PATH/ispvmsystem -export INI_FILE=lsc_7_0.ini -export MWHOME=$ISPCPLD/mw -export MWUSER_DIRECTORY=$HOME/isplever_lin_window -export MWREGISTRY=:$MWUSER_DIRECTORY/hklm_linux.bin -#unexport LD_LIBRARY_PATH -#source $MWHOME/setmwruntime.csh -export COMSPEC=/bin/csh -export PATH=$PATH:$ISPCPLD/bin:$PDSPLUS/bin:$ISPVM_DIR -export LD_LIBRARY_PATH=$ISPCPLD/bin:$PDSPLUS/bin:$ISPCPLD/../ispvmsystem/lib:$ISPFPGA/bin/lin:$ISPJTOOLS/vm15/lib/i386:$ISPJTOOLS/vm15/lib/i386/client:$ISPCPLD/tcltk/linux-ix86/lib:$LD_LIBRARY_PATH -export WINHELPDIR=$ISPCPLD/bin -export WINHELPPATH=$ISPCPLD/bin -export ABEL5DEV=$ISPCPLD/lib5 -#export LD_ASSUME_KERNEL 2.4.0 -export MWRT_MODE=professional - -export LM_LICENSE_FILE=$ISPCPLD/../license/license.dat:$LM_LICENSE_FILE - -sed -e "s?home_dir?$HOME/isplever_lin_window?" -e "s?bin_dir?$ISPLEVER_PATH/ispcpld/bin?" -e "s?isptool_dir?$ISPLEVER_PATH?" $ISPCPLD/config/$INI_FILE > $ISPLEVER_PATH/$INI_FILE -export LSC_INI_PATH=$ISPLEVER_PATH -export LSC_INI_FILE=$LSC_INI_PATH/$INI_FILE - diff --git a/optical_link/simpleupcounter_16bit.vhd b/optical_link/simpleupcounter_16bit.vhd deleted file mode 100644 index 16e14af..0000000 --- a/optical_link/simpleupcounter_16bit.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - - -entity simpleupcounter_16bit is - Port ( QOUT : out std_logic_vector(15 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); -end simpleupcounter_16bit; - -architecture simpleupcounter_16bit of simpleupcounter_16bit is - -signal counter: std_logic_vector (15 downto 0); - -begin - - process (CLR, UP, CLK) - - begin - if CLR = '1' then - counter <= "0000000000000000"; - elsif clk'event and clk = '1' then - if UP = '1' then - counter <= counter + 1; - else - counter <= counter; - end if; -end if; -end process; - -QOUT <= counter; - -end simpleupcounter_16bit; diff --git a/optical_link/simpleupcounter_32bit.vhd b/optical_link/simpleupcounter_32bit.vhd deleted file mode 100644 index 7bf16a9..0000000 --- a/optical_link/simpleupcounter_32bit.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - - -entity simpleupcounter_32bit is - Port ( QOUT : out std_logic_vector(31 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); -end simpleupcounter_32bit; - -architecture simpleupcounter_32bit of simpleupcounter_32bit is - -signal counter: std_logic_vector (31 downto 0); - -begin - - process (CLR, UP, CLK) - - begin - if CLR = '1' then - counter <= "00000000000000000000000000000000"; - elsif clk'event and clk = '1' then - if UP = '1' then - counter <= counter + 1; - else - counter <= counter; - end if; -end if; -end process; - -QOUT <= counter; - -end simpleupcounter_32bit; diff --git a/optical_link/simpleupcounter_8bit.vhd b/optical_link/simpleupcounter_8bit.vhd deleted file mode 100644 index e5fa035..0000000 --- a/optical_link/simpleupcounter_8bit.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - - -entity simpleupcounter_8bit is - Port ( QOUT : out std_logic_vector(7 downto 0); - UP : in std_logic; - CLK : in std_logic; - CLR : in std_logic); -end simpleupcounter_8bit; - -architecture Behavioral of simpleupcounter_8bit is - -signal counter: std_logic_vector (7 downto 0); - -begin - - process (CLR, UP, CLK) - - begin - if CLR = '1' then - counter <= ( others => '0'); - elsif clk'event and clk = '1' then - if UP = '1' then - counter <= counter + 1; - else - counter <= counter; - end if; -end if; -end process; - -QOUT <= counter; - -end Behavioral; diff --git a/optical_link/trb_hub_interface.vhd b/optical_link/trb_hub_interface.vhd deleted file mode 100644 index 6d7c59b..0000000 --- a/optical_link/trb_hub_interface.vhd +++ /dev/null @@ -1,197 +0,0 @@ -library IEEE; - -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.all; ---use work.support.all; - - -entity trb_hub_interface is - port ( - CLK : in std_logic; - RESET : in std_logic; - STROBE : in std_logic; - INTERNAL_DATA_IN : in std_logic_vector(7 downto 0); - INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0); - INTERNAL_ADDRESS : in std_logic_vector(15 downto 0); - INTERNAL_MODE : in std_logic; - VALID_DATA_SENT : out std_logic; - HUB_REGISTER_00 : in std_logic_vector(7 downto 0); - HUB_REGISTER_01 : in std_logic_vector(7 downto 0); - HUB_REGISTER_02 : in std_logic_vector(7 downto 0); - HUB_REGISTER_03 : in std_logic_vector(7 downto 0); - HUB_REGISTER_04 : in std_logic_vector(7 downto 0); - HUB_REGISTER_05 : in std_logic_vector(7 downto 0); - HUB_REGISTER_06 : in std_logic_vector(7 downto 0); - HUB_REGISTER_07 : in std_logic_vector(7 downto 0); - HUB_REGISTER_08 : in std_logic_vector(7 downto 0); - HUB_REGISTER_09 : in std_logic_vector(7 downto 0); - HUB_REGISTER_0a : out std_logic_vector(7 downto 0); - HUB_REGISTER_0b : out std_logic_vector(7 downto 0); - HUB_REGISTER_0c : out std_logic_vector(7 downto 0); - HUB_REGISTER_0d : out std_logic_vector(7 downto 0); - HUB_REGISTER_0e : out std_logic_vector(7 downto 0); - HUB_REGISTER_0f : out std_logic_vector(7 downto 0); - HUB_REGISTER_10 : in std_logic_vector(7 downto 0); - HUB_REGISTER_11 : in std_logic_vector(7 downto 0); - HUB_REGISTER_12 : in std_logic_vector(7 downto 0); - HUB_REGISTER_13 : in std_logic_vector(7 downto 0); - HUB_REGISTER_14 : in std_logic_vector(7 downto 0); - HUB_REGISTER_15 : in std_logic_vector(7 downto 0); - HUB_REGISTER_16 : in std_logic_vector(7 downto 0) - ); -end trb_hub_interface; -architecture trb_hub_interface of trb_hub_interface is - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - signal hub_register_08_i : std_logic_vector(7 downto 0); - signal hub_register_09_i : std_logic_vector(7 downto 0); - signal hub_register_0a_i : std_logic_vector(7 downto 0); - signal hub_register_0b_i : std_logic_vector(7 downto 0); - signal hub_register_0c_i : std_logic_vector(7 downto 0); - signal hub_register_0d_i : std_logic_vector(7 downto 0); - signal hub_register_0e_i : std_logic_vector(7 downto 0); - signal hub_register_0f_i : std_logic_vector(7 downto 0); - signal saved_address : std_logic_vector(15 downto 0); - signal saved_mod : std_logic; - signal saved_data_in : std_logic_vector(7 downto 0); - signal saved_data_out : std_logic_vector(7 downto 0); - signal strobe_pulse : std_logic; - signal data_ready : std_logic; - type SEND_VALID is - (IDLE ,VALID_1,VALID_2,VALID_3,VALID_4,VALID_5); - signal VALID_current, VALID_next: SEND_VALID; -begin - - STROBE_PULSER: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => STROBE, - pulse => strobe_pulse); - SAVE_MOD_ADD_DATA : process (CLK, RESET, strobe_pulse) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_address <= (others => '0'); - saved_mod <= '0'; - saved_data_in <= (others => '0'); - elsif strobe_pulse = '1' then - saved_address <= INTERNAL_ADDRESS; - saved_mod <= INTERNAL_MODE; - saved_data_in <= INTERNAL_DATA_IN; - end if; - end if; - end process SAVE_MOD_ADD_DATA; - - DATA_SOURCE_SELECT : process (CLK,RESET,saved_mod,saved_address) - begin - if rising_edge(CLK) then - if RESET = '1' then - hub_register_0a_i <= x"00"; - hub_register_0b_i <= x"00"; - hub_register_0c_i <= x"00"; - hub_register_0d_i <= x"00"; - else - if saved_mod = '1' then - case saved_address(15 downto 0) is - when x"0000" => saved_data_out <= HUB_REGISTER_00; - when x"0001" => saved_data_out <= HUB_REGISTER_01; - when x"0002" => saved_data_out <= HUB_REGISTER_02; - when x"0003" => saved_data_out <= HUB_REGISTER_03; - when x"0004" => saved_data_out <= HUB_REGISTER_04; - when x"0005" => saved_data_out <= HUB_REGISTER_05; - when x"0006" => saved_data_out <= HUB_REGISTER_06; - when x"0007" => saved_data_out <= HUB_REGISTER_07; - when x"0008" => saved_data_out <= HUB_REGISTER_08; - when x"0009" => saved_data_out <= HUB_REGISTER_09; - when x"000a" => saved_data_out <= hub_register_0a_i; - when x"000b" => saved_data_out <= hub_register_0b_i; - when x"000c" => saved_data_out <= hub_register_0c_i; - when x"000d" => saved_data_out <= hub_register_0d_i; - when x"000e" => saved_data_out <= hub_register_0e_i; - when x"000f" => saved_data_out <= hub_register_0f_i; - when x"0010" => saved_data_out <= HUB_REGISTER_10; - when x"0011" => saved_data_out <= HUB_REGISTER_11; - when x"0012" => saved_data_out <= HUB_REGISTER_12; - when x"0013" => saved_data_out <= HUB_REGISTER_13; - when x"0014" => saved_data_out <= HUB_REGISTER_14; - when x"0015" => saved_data_out <= HUB_REGISTER_15; - when x"0016" => saved_data_out <= HUB_REGISTER_16; - - when others => saved_data_out <= x"ff"; - end case; - elsif saved_mod = '0' then - case saved_address(15 downto 0) is - when x"000a" => hub_register_0a_i <= saved_data_in; - when x"000b" => hub_register_0b_i <= saved_data_in; - when x"000c" => hub_register_0c_i <= saved_data_in; - when x"000d" => hub_register_0d_i <= saved_data_in; - when x"000e" => hub_register_0e_i <= saved_data_in; - when x"000f" => hub_register_0f_i <= saved_data_in; - when others => null; - end case; - end if; - end if; - end if; - end process DATA_SOURCE_SELECT; - HUB_REGISTER_0a <= hub_register_0a_i; - HUB_REGISTER_0b <= hub_register_0b_i; - HUB_REGISTER_0c <= hub_register_0c_i; - HUB_REGISTER_0d <= hub_register_0d_i; - HUB_REGISTER_0e <= hub_register_0e_i; - HUB_REGISTER_0f <= hub_register_0f_i; - INTERNAL_DATA_OUT <= saved_data_out; - data_ready <= '1'; - VALID_CLOCKED : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - VALID_current <= IDLE; - else - VALID_current <= VALID_next; - end if; - end if; - end process VALID_CLOCKED; - SEND_VALID_FSM: process (VALID_current,data_ready,strobe_pulse) - begin - case (VALID_current) is - when IDLE => - VALID_DATA_SENT <= '0'; - if strobe_pulse = '1' then - VALID_next <= VALID_1; - else - VALID_next <= IDLE; - end if; - when VALID_1 => - VALID_DATA_SENT <= '0'; - -- if data_ready = '1' then - VALID_next <= VALID_2; - -- else - -- VALID_next <= VALID_1; - -- end if; - when VALID_2 => - VALID_DATA_SENT <= '1'; - VALID_next <= VALID_3; - when VALID_3 => - VALID_DATA_SENT <= '1'; - VALID_next <= VALID_4; - when VALID_4 => - VALID_DATA_SENT <= '1'; - VALID_next <= VALID_5; - when VALID_5 => - VALID_DATA_SENT <= '1'; - VALID_next <= IDLE; - when others => - VALID_DATA_SENT <= '0'; - VALID_next <= IDLE; - end case; - end process SEND_VALID_FSM; - -end trb_hub_interface; diff --git a/optical_link/trbv2_tlk_api.vhd b/optical_link/trbv2_tlk_api.vhd deleted file mode 100644 index 4bdce44..0000000 --- a/optical_link/trbv2_tlk_api.vhd +++ /dev/null @@ -1,142 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library ieee; -library work; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.all; - -entity trbv2_tlk_api is - - port ( - RESET : in std_logic; - CLK : in std_logic; - TLK_CLK : in std_logic; - TLK_ENABLE : out std_logic; - TLK_LCKREFN : out std_logic; - TLK_LOOPEN : out std_logic; - TLK_PRBSEN : out std_logic; - TLK_RXD : in std_logic_vector(15 downto 0); - TLK_RX_CLK : in std_logic; - TLK_RX_DV : in std_logic; - TLK_RX_ER : in std_logic; - TLK_TXD : out std_logic_vector(15 downto 0); - TLK_TX_EN : out std_logic; - TLK_TX_ER : out std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_IN : in std_logic_vector(15 downto 0); - DATA_VALID_IN : in std_logic; - DATA_VALID_OUT : out std_logic; - TLK_API_REGISTER_00 : out std_logic_vector(31 downto 0) - ); -end trbv2_tlk_api; -architecture trbv2_tlk_api of trbv2_tlk_api is - component trbv2_tlk_api_fifo - port ( - din : IN std_logic_VECTOR(17 downto 0); - rd_clk : IN std_logic; - rd_en : IN std_logic; - rst : IN std_logic; - wr_clk : IN std_logic; - wr_en : IN std_logic; - dout : OUT std_logic_VECTOR(17 downto 0); - empty : OUT std_logic; - full : OUT std_logic; - rd_data_count : OUT std_logic_VECTOR(9 downto 0); - wr_data_count : OUT std_logic_VECTOR(9 downto 0)); - end component; - signal fifo_din_a : std_logic_vector(17 downto 0); - signal fifo_dout_a : std_logic_vector(17 downto 0); - signal fifo_rst_a : std_logic; - signal fifo_rd_en_a : std_logic; - signal fifo_rd_data_count_a : std_logic_vector(9 downto 0); - signal fifo_wr_data_count_a : std_logic_vector(9 downto 0); - signal fifo_empty_a : std_logic; - signal fifo_full_a : std_logic; - signal fifo_din_m : std_logic_vector(17 downto 0); - signal fifo_dout_m : std_logic_vector(17 downto 0); - signal fifo_rst_m : std_logic; - signal fifo_rd_en_m : std_logic; - signal fifo_rd_data_count_m : std_logic_vector(9 downto 0); - signal fifo_wr_data_count_m : std_logic_vector(9 downto 0); - signal fifo_empty_m : std_logic; - signal fifo_full_m : std_logic; - signal reset_fifo_counter : std_logic_vector(7 downto 0); -begin - ----------------------------------------------------------------------------- - -- api to media - ----------------------------------------------------------------------------- - fifo_din_a <= TLK_RX_ER & TLK_RX_DV & TLK_RXD; - - OPTICAL_TO_FIFO_TO_API: trbv2_tlk_api_fifo - port map ( - din => fifo_din_a, - rd_clk => CLK, - rd_en => fifo_rd_en_a , - rst => fifo_rst_a , - wr_clk => TLK_RX_CLK, - wr_en => '1', - dout => fifo_dout_a, - empty => fifo_empty_a, - full => fifo_full_a, - rd_data_count => fifo_rd_data_count_a, - wr_data_count => fifo_wr_data_count_a); - SYNCH_DATA_OUT: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - DATA_VALID_OUT <= '0'; - DATA_OUT <= x"0000"; - else - DATA_VALID_OUT <= not(fifo_dout_a(17)) and fifo_dout_a(16); - DATA_OUT <= fifo_dout_a(15 downto 0); - end if; - end if; - end process SYNCH_DATA_OUT; - - ----------------------------------------------------------------------------- - -- media to api - ----------------------------------------------------------------------------- - fifo_din_m <= '0' & DATA_VALID_IN & DATA_IN; - - API_TO_FIFO_TO_OPTICAL: trbv2_tlk_api_fifo - port map ( - din => fifo_din_m, - rd_clk => TLK_CLK, - rd_en => fifo_rd_en_m , - rst => fifo_rst_m , - wr_clk => CLK, - wr_en => '1', - dout => fifo_dout_m, - empty => fifo_empty_m, - full => fifo_full_m, - rd_data_count => fifo_rd_data_count_m, - wr_data_count => fifo_wr_data_count_m); - - TLK_TXD <= fifo_dout_m (15 downto 0); - TLK_TX_EN <= fifo_dout_m(16); - TLK_TX_ER <= '0'; - TLK_LOOPEN <= '0'; - TLK_LCKREFN <= '1'; - TLK_ENABLE <= '1'; - TLK_PRBSEN <= '0'; - - ----------------------------------------------------------------------------- - -- all - ----------------------------------------------------------------------------- - RESET_FIFO_COUNTER_PROC: process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' or fifo_dout_a(17) = '1' then - reset_fifo_counter <= x"00"; - elsif reset_fifo_counter < x"f0" then - reset_fifo_counter <= reset_fifo_counter + 1; - end if; - end if; - end process RESET_FIFO_COUNTER_PROC; - fifo_rst_m <= '1' when reset_fifo_counter < x"40" else '0'; - fifo_rst_a <= '1' when reset_fifo_counter < x"40" else '0'; - fifo_rd_en_m <= '1' when reset_fifo_counter > x"46" else '0'; - fifo_rd_en_a <= '1' when reset_fifo_counter > x"46" else '0'; -end trbv2_tlk_api; diff --git a/optical_link/trbv2_tlk_api_fifo.ngc b/optical_link/trbv2_tlk_api_fifo.ngc deleted file mode 100644 index d0694d3..0000000 --- a/optical_link/trbv2_tlk_api_fifo.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e 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\ No newline at end of file diff --git a/optical_link/trbv2_tlk_api_fifo.vhd b/optical_link/trbv2_tlk_api_fifo.vhd deleted file mode 100644 index 5faa056..0000000 --- a/optical_link/trbv2_tlk_api_fifo.vhd +++ /dev/null @@ -1,150 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file trbv2_tlk_api_fifo.vhd when simulating --- the core, trbv2_tlk_api_fifo. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY trbv2_tlk_api_fifo IS - port ( - din: IN std_logic_VECTOR(17 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(9 downto 0); - wr_data_count: OUT std_logic_VECTOR(9 downto 0)); -END trbv2_tlk_api_fifo; - -ARCHITECTURE trbv2_tlk_api_fifo_a OF trbv2_tlk_api_fifo IS --- synthesis translate_off -component wrapped_trbv2_tlk_api_fifo - port ( - din: IN std_logic_VECTOR(17 downto 0); - rd_clk: IN std_logic; - rd_en: IN std_logic; - rst: IN std_logic; - wr_clk: IN std_logic; - wr_en: IN std_logic; - dout: OUT std_logic_VECTOR(17 downto 0); - empty: OUT std_logic; - full: OUT std_logic; - rd_data_count: OUT std_logic_VECTOR(9 downto 0); - wr_data_count: OUT std_logic_VECTOR(9 downto 0)); -end component; - --- Configuration specification - for all : wrapped_trbv2_tlk_api_fifo use entity XilinxCoreLib.fifo_generator_v3_3(behavioral) - generic map( - c_rd_freq => 100, - c_wr_response_latency => 1, - c_has_srst => 0, - c_has_rd_data_count => 1, - c_din_width => 18, - c_has_wr_data_count => 1, - c_implementation_type => 2, - c_family => "virtex4", - c_has_wr_rst => 0, - c_wr_freq => 100, - c_underflow_low => 0, - c_has_meminit_file => 0, - c_has_overflow => 0, - c_preload_latency => 1, - c_dout_width => 18, - c_rd_depth => 1024, - c_default_value => "BlankString", - c_mif_file_name => "BlankString", - c_has_underflow => 0, - c_has_rd_rst => 0, - c_has_almost_full => 0, - c_has_rst => 1, - c_data_count_width => 10, - c_has_wr_ack => 0, - c_use_ecc => 0, - c_wr_ack_low => 0, - c_common_clock => 0, - c_rd_pntr_width => 10, - c_has_almost_empty => 0, - c_rd_data_count_width => 10, - c_enable_rlocs => 0, - c_wr_pntr_width => 10, - c_overflow_low => 0, - c_prog_empty_type => 0, - c_optimization_mode => 0, - c_wr_data_count_width => 10, - c_preload_regs => 0, - c_dout_rst_val => "0", - c_has_data_count => 0, - c_prog_full_thresh_negate_val => 1021, - c_wr_depth => 1024, - c_prog_empty_thresh_negate_val => 3, - c_prog_empty_thresh_assert_val => 2, - c_has_valid => 0, - c_init_wr_pntr_val => 0, - c_prog_full_thresh_assert_val => 1022, - c_use_fifo16_flags => 0, - c_has_backup => 0, - c_valid_low => 0, - c_prim_fifo_type => "1kx18", - c_count_type => 0, - c_prog_full_type => 0, - c_memory_type => 1); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_trbv2_tlk_api_fifo - port map ( - din => din, - rd_clk => rd_clk, - rd_en => rd_en, - rst => rst, - wr_clk => wr_clk, - wr_en => wr_en, - dout => dout, - empty => empty, - full => full, - rd_data_count => rd_data_count, - wr_data_count => wr_data_count); --- synthesis translate_on - -END trbv2_tlk_api_fifo_a; - -- 2.43.0

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