From f493d8ffff572f310872d45437ac148966098918 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sat, 12 Nov 2022 22:48:55 +0100 Subject: [PATCH] double-swapped bytes in 16bit words fixed --- gbe_trb/base/gbe_frame_receiver.vhd | 22 +- gbe_trb/base/gbe_protocol_selector.vhd | 4 +- gbe_trb/ipcores/ecp3/ddr_out.lpc | 65 +++ gbe_trb/ipcores/ecp3/ddr_out.vhd | 93 +++++ gbe_trb/ipcores/ecp3/odr_dbg.lpc | 41 ++ gbe_trb/ipcores/ecp3/odr_dbg.vhd | 371 ++++++++++++++++++ .../gbe_response_constructor_Discovery.vhd | 185 +++++---- .../gbe_response_constructor_SCTRL.vhd | 23 +- 8 files changed, 698 insertions(+), 106 deletions(-) create mode 100644 gbe_trb/ipcores/ecp3/ddr_out.lpc create mode 100644 gbe_trb/ipcores/ecp3/ddr_out.vhd create mode 100644 gbe_trb/ipcores/ecp3/odr_dbg.lpc create mode 100644 gbe_trb/ipcores/ecp3/odr_dbg.vhd diff --git a/gbe_trb/base/gbe_frame_receiver.vhd b/gbe_trb/base/gbe_frame_receiver.vhd index 2f53082..36fc3dd 100644 --- a/gbe_trb/base/gbe_frame_receiver.vhd +++ b/gbe_trb/base/gbe_frame_receiver.vhd @@ -385,8 +385,8 @@ begin when x"08" => stored_src_mac(31 downto 24) <= MAC_RXD_IN; when x"09" => stored_src_mac(39 downto 32) <= MAC_RXD_IN; when x"0a" => stored_src_mac(47 downto 40) <= MAC_RXD_IN; - when x"0b" => stored_ethertype(15 downto 8) <= MAC_RXD_IN; - when x"0c" => stored_ethertype(7 downto 0) <= MAC_RXD_IN; + when x"0b" => stored_ethertype(7 downto 0) <= MAC_RXD_IN; + when x"0c" => stored_ethertype(15 downto 8) <= MAC_RXD_IN; when x"0d" => stored_version <= MAC_RXD_IN; when x"16" => stored_protocol <= MAC_RXD_IN; when x"19" => stored_src_ip(7 downto 0) <= MAC_RXD_IN; @@ -397,10 +397,10 @@ begin when x"1e" => stored_dst_ip(15 downto 8) <= MAC_RXD_IN; when x"1f" => stored_dst_ip(23 downto 16) <= MAC_RXD_IN; when x"20" => stored_dst_ip(31 downto 24) <= MAC_RXD_IN; - when x"21" => stored_src_port(15 downto 8) <= MAC_RXD_IN; - when x"22" => stored_src_port(7 downto 0) <= MAC_RXD_IN; - when x"23" => stored_dst_port(15 downto 8) <= MAC_RXD_IN; - when x"24" => stored_dst_port(7 downto 0) <= MAC_RXD_IN; + when x"21" => stored_src_port(7 downto 0) <= MAC_RXD_IN; + when x"22" => stored_src_port(15 downto 8) <= MAC_RXD_IN; + when x"23" => stored_dst_port(7 downto 0) <= MAC_RXD_IN; + when x"24" => stored_dst_port(15 downto 8) <= MAC_RXD_IN; when others => null; end case; end if; @@ -410,14 +410,14 @@ begin -- checks to filter frames, and distribute them to the correct handlers is_my_mac_x <= '1' when (stored_dst_mac = MY_MAC_IN) else '0'; is_broadcast_x <= '1' when (stored_dst_mac = x"ffffffffffff") else '0'; - is_arp_x <= '1' when (stored_ethertype = x"0806") else '0'; - is_ipv4_x <= '1' when (stored_ethertype = x"0800") else '0'; + is_arp_x <= '1' when (stored_ethertype = x"0608") else '0'; -- bytes mirrored + is_ipv4_x <= '1' when (stored_ethertype = x"0008") else '0'; -- bytes mirrored is_version_x <= '1' when (stored_version = x"45") else '0'; is_udp_x <= '1' when (stored_protocol = x"11") else '0'; is_icmp_x <= '1' when (stored_protocol = x"01") else '0'; - is_dhcp_x <= '1' when (stored_dst_port = x"0044") else '0'; - is_sctrl_x <= '1' when (stored_dst_port = x"6590") else '0'; - is_discovery_x <= '1' when (stored_dst_port = x"d903") else '0'; + is_dhcp_x <= '1' when (stored_dst_port = x"4400") else '0'; -- bytes mirrored + is_sctrl_x <= '1' when (stored_dst_port = x"9065") else '0'; -- bytes mirrored + is_discovery_x <= '1' when (stored_dst_port = x"03d9") else '0'; -- bytes mirrored is_my_ip_x <= '1' when (stored_dst_ip = MY_IP_IN) else '0'; is_broadcast_ip_x <= '1' when (stored_dst_ip = x"ffffffff") else '0'; is_empty_payload_x <= '1' when (rx_bytes_ctr = 0) else '0'; diff --git a/gbe_trb/base/gbe_protocol_selector.vhd b/gbe_trb/base/gbe_protocol_selector.vhd index 24ec501..1172bf2 100644 --- a/gbe_trb/base/gbe_protocol_selector.vhd +++ b/gbe_trb/base/gbe_protocol_selector.vhd @@ -510,7 +510,7 @@ begin if( rising_edge(CLK) ) then if ( select_current_state = IDLE ) then index <= 0; - elsif( select_current_state = LOOP_OVER and resp_ready(index) = '0' ) then + elsif( (select_current_state = LOOP_OVER) and (resp_ready(index) = '0') ) then index <= index + 1; end if; end if; @@ -519,7 +519,7 @@ begin PROC_SELECTOR: process( CLK ) begin if( rising_edge(CLK) ) then - if( select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST ) then + if( (select_current_state = SELECT_ONE) or (select_current_state = PROCESS_REQUEST) ) then TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9); TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16); TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16); diff --git a/gbe_trb/ipcores/ecp3/ddr_out.lpc b/gbe_trb/ipcores/ecp3/ddr_out.lpc new file mode 100644 index 0000000..196e184 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/ddr_out.lpc @@ -0,0 +1,65 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN672C +SpeedGrade=6 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=ddr_out +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/12/2022 +Time=17:51:26 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Transmit +trioddr=0 +io_type=LVCMOS25 +num_int=1 +width=1 +freq_in=125 +bandwidth=250 +aligned=Edge-to-Edge +pre-configuration=ENABLED +mode2=Transmit +trioddr2=0 +io_type2=LVCMOS25 +freq_in2=125 +gear=1x +aligned2=Edge-to-Edge +num_int2=1 +width2=1 +Interface=GDDRX1_TX.SCLK.Aligned +Delay= +Number= +dqs1= +dqs2= +dqs3= +dqs4= +dqs5= +dqs6= +dqs7= +dqs8= +val= +Phase=TRDLLB/DLLDELB +Divider=CLKDIVB +Multiplier=2 +PllFreq=62 + +[Command] +cmd_line= -w -n ddr_out -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 1 -freq_in 125 -gear 1 -clk sclk -aligned diff --git a/gbe_trb/ipcores/ecp3/ddr_out.vhd b/gbe_trb/ipcores/ecp3/ddr_out.vhd new file mode 100644 index 0000000..b1c9da6 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/ddr_out.vhd @@ -0,0 +1,93 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n ddr_out -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 1 -freq_in 125 -gear 1 -clk sclk -aligned + +-- Sat Nov 12 17:51:26 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity ddr_out is + port ( + clk: in std_logic; + clkout: out std_logic; + da: in std_logic_vector(0 downto 0); + db: in std_logic_vector(0 downto 0); + q: out std_logic_vector(0 downto 0)); +end ddr_out; + +architecture Structure of ddr_out is + + -- internal signal declarations + signal buf_clkout: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal clkos: std_logic; + signal clkop: std_logic; + signal buf_qo0: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component OB + port (I: in std_logic; O: out std_logic); + end component; + component ODDRXD1 + port (DA: in std_logic; DB: in std_logic; SCLK: in std_logic; + Q: out std_logic); + end component; + attribute ODDRAPPS : string; + attribute IO_TYPE : string; + attribute IO_TYPE of Inst3_OB : label is "LVCMOS25"; + attribute ODDRAPPS of Inst_ODDRXD1_0_0 : label is "SCLK_ALIGNED"; + attribute ODDRAPPS of Inst2_ODDRXD1 : label is "SCLK_ALIGNED"; + attribute IO_TYPE of Inst1_OB0 : label is "LVCMOS25"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + Inst3_OB: OB + port map (I=>buf_clkout, O=>clkout); + + Inst_ODDRXD1_0_0: ODDRXD1 + port map (DA=>da(0), DB=>db(0), SCLK=>clkop, Q=>buf_qo0); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst2_ODDRXD1: ODDRXD1 + port map (DA=>scuba_vhi, DB=>scuba_vlo, SCLK=>clkos, + Q=>buf_clkout); + + Inst1_OB0: OB + port map (I=>buf_qo0, O=>q(0)); + + clkos <= clk; + clkop <= clk; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of ddr_out is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:OB use entity ecp3.OB(V); end for; + for all:ODDRXD1 use entity ecp3.ODDRXD1(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/odr_dbg.lpc b/gbe_trb/ipcores/ecp3/odr_dbg.lpc new file mode 100644 index 0000000..2166be5 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/odr_dbg.lpc @@ -0,0 +1,41 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN672C +SpeedGrade=6 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=SDR +CoreRevision=6.0 +ModuleName=odr_dbg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/12/2022 +Time=18:59:59 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Transmit +io_type=LVCMOS25 +width=32 +freq_in=125 +bandwidth=4000 +interface=GOREG_TX.SCLK +negedge=DISABLED +del= +fdel= + +[Command] +cmd_line= -w -n odr_dbg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 32 -freq_in 125 -clk sclk -aligned -gear 0 diff --git a/gbe_trb/ipcores/ecp3/odr_dbg.vhd b/gbe_trb/ipcores/ecp3/odr_dbg.vhd new file mode 100644 index 0000000..060c58b --- /dev/null +++ b/gbe_trb/ipcores/ecp3/odr_dbg.vhd @@ -0,0 +1,371 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n odr_dbg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVCMOS25 -width 32 -freq_in 125 -clk sclk -aligned -gear 0 + +-- Sat Nov 12 18:59:59 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity odr_dbg is + port ( + clk: in std_logic; + clkout: out std_logic; + reset: in std_logic; + d: in std_logic_vector(31 downto 0); + dout: out std_logic_vector(31 downto 0)); +end odr_dbg; + +architecture Structure of odr_dbg is + + -- internal signal declarations + signal buf_clkout: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal buf_douto31: std_logic; + signal buf_douto30: std_logic; + signal buf_douto29: std_logic; + signal buf_douto28: std_logic; + signal buf_douto27: std_logic; + signal buf_douto26: std_logic; + signal buf_douto25: std_logic; + signal buf_douto24: std_logic; + signal buf_douto23: std_logic; + signal buf_douto22: std_logic; + signal buf_douto21: std_logic; + signal buf_douto20: std_logic; + signal buf_douto19: std_logic; + signal buf_douto18: std_logic; + signal buf_douto17: std_logic; + signal buf_douto16: std_logic; + signal buf_douto15: std_logic; + signal buf_douto14: std_logic; + signal buf_douto13: std_logic; + signal buf_douto12: std_logic; + signal buf_douto11: std_logic; + signal buf_douto10: std_logic; + signal buf_douto9: std_logic; + signal buf_douto8: std_logic; + signal buf_douto7: std_logic; + signal buf_douto6: std_logic; + signal buf_douto5: std_logic; + signal buf_douto4: std_logic; + signal buf_douto3: std_logic; + signal buf_douto2: std_logic; + signal buf_douto1: std_logic; + signal buf_douto0: std_logic; + + -- local component declarations + component OFS1P3DX + port (D: in std_logic; SP: in std_logic; SCLK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component OB + port (I: in std_logic; O: out std_logic); + end component; + component ODDRXD1 + port (DA: in std_logic; DB: in std_logic; SCLK: in std_logic; + Q: out std_logic); + end component; + attribute ODDRAPPS : string; + attribute IO_TYPE : string; + attribute IO_TYPE of Inst4_OB : label is "LVCMOS25"; + attribute ODDRAPPS of Inst3_ODDRXD1 : label is "SCLK_ALIGNED"; + attribute IO_TYPE of Inst1_OB31 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB30 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB29 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB28 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB27 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB26 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB25 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB24 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB23 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB22 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB21 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB20 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB19 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB18 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB17 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB16 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB15 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB14 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB13 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB12 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB11 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB10 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB9 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB8 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB7 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB6 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB5 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB4 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB3 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB2 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB1 : label is "LVCMOS25"; + attribute IO_TYPE of Inst1_OB0 : label is "LVCMOS25"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + Inst4_OB: OB + port map (I=>buf_clkout, O=>clkout); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Inst3_ODDRXD1: ODDRXD1 + port map (DA=>scuba_vhi, DB=>scuba_vlo, SCLK=>clk, Q=>buf_clkout); + + Inst2_OFS1P3DX31: OFS1P3DX + port map (D=>d(31), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto31); + + Inst2_OFS1P3DX30: OFS1P3DX + port map (D=>d(30), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto30); + + Inst2_OFS1P3DX29: OFS1P3DX + port map (D=>d(29), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto29); + + Inst2_OFS1P3DX28: OFS1P3DX + port map (D=>d(28), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto28); + + Inst2_OFS1P3DX27: OFS1P3DX + port map (D=>d(27), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto27); + + Inst2_OFS1P3DX26: OFS1P3DX + port map (D=>d(26), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto26); + + Inst2_OFS1P3DX25: OFS1P3DX + port map (D=>d(25), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto25); + + Inst2_OFS1P3DX24: OFS1P3DX + port map (D=>d(24), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto24); + + Inst2_OFS1P3DX23: OFS1P3DX + port map (D=>d(23), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto23); + + Inst2_OFS1P3DX22: OFS1P3DX + port map (D=>d(22), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto22); + + Inst2_OFS1P3DX21: OFS1P3DX + port map (D=>d(21), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto21); + + Inst2_OFS1P3DX20: OFS1P3DX + port map (D=>d(20), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto20); + + Inst2_OFS1P3DX19: OFS1P3DX + port map (D=>d(19), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto19); + + Inst2_OFS1P3DX18: OFS1P3DX + port map (D=>d(18), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto18); + + Inst2_OFS1P3DX17: OFS1P3DX + port map (D=>d(17), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto17); + + Inst2_OFS1P3DX16: OFS1P3DX + port map (D=>d(16), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto16); + + Inst2_OFS1P3DX15: OFS1P3DX + port map (D=>d(15), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto15); + + Inst2_OFS1P3DX14: OFS1P3DX + port map (D=>d(14), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto14); + + Inst2_OFS1P3DX13: OFS1P3DX + port map (D=>d(13), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto13); + + Inst2_OFS1P3DX12: OFS1P3DX + port map (D=>d(12), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto12); + + Inst2_OFS1P3DX11: OFS1P3DX + port map (D=>d(11), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto11); + + Inst2_OFS1P3DX10: OFS1P3DX + port map (D=>d(10), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto10); + + Inst2_OFS1P3DX9: OFS1P3DX + port map (D=>d(9), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto9); + + Inst2_OFS1P3DX8: OFS1P3DX + port map (D=>d(8), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto8); + + Inst2_OFS1P3DX7: OFS1P3DX + port map (D=>d(7), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto7); + + Inst2_OFS1P3DX6: OFS1P3DX + port map (D=>d(6), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto6); + + Inst2_OFS1P3DX5: OFS1P3DX + port map (D=>d(5), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto5); + + Inst2_OFS1P3DX4: OFS1P3DX + port map (D=>d(4), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto4); + + Inst2_OFS1P3DX3: OFS1P3DX + port map (D=>d(3), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto3); + + Inst2_OFS1P3DX2: OFS1P3DX + port map (D=>d(2), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto2); + + Inst2_OFS1P3DX1: OFS1P3DX + port map (D=>d(1), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto1); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst2_OFS1P3DX0: OFS1P3DX + port map (D=>d(0), SP=>scuba_vhi, SCLK=>clk, CD=>reset, + Q=>buf_douto0); + + Inst1_OB31: OB + port map (I=>buf_douto31, O=>dout(31)); + + Inst1_OB30: OB + port map (I=>buf_douto30, O=>dout(30)); + + Inst1_OB29: OB + port map (I=>buf_douto29, O=>dout(29)); + + Inst1_OB28: OB + port map (I=>buf_douto28, O=>dout(28)); + + Inst1_OB27: OB + port map (I=>buf_douto27, O=>dout(27)); + + Inst1_OB26: OB + port map (I=>buf_douto26, O=>dout(26)); + + Inst1_OB25: OB + port map (I=>buf_douto25, O=>dout(25)); + + Inst1_OB24: OB + port map (I=>buf_douto24, O=>dout(24)); + + Inst1_OB23: OB + port map (I=>buf_douto23, O=>dout(23)); + + Inst1_OB22: OB + port map (I=>buf_douto22, O=>dout(22)); + + Inst1_OB21: OB + port map (I=>buf_douto21, O=>dout(21)); + + Inst1_OB20: OB + port map (I=>buf_douto20, O=>dout(20)); + + Inst1_OB19: OB + port map (I=>buf_douto19, O=>dout(19)); + + Inst1_OB18: OB + port map (I=>buf_douto18, O=>dout(18)); + + Inst1_OB17: OB + port map (I=>buf_douto17, O=>dout(17)); + + Inst1_OB16: OB + port map (I=>buf_douto16, O=>dout(16)); + + Inst1_OB15: OB + port map (I=>buf_douto15, O=>dout(15)); + + Inst1_OB14: OB + port map (I=>buf_douto14, O=>dout(14)); + + Inst1_OB13: OB + port map (I=>buf_douto13, O=>dout(13)); + + Inst1_OB12: OB + port map (I=>buf_douto12, O=>dout(12)); + + Inst1_OB11: OB + port map (I=>buf_douto11, O=>dout(11)); + + Inst1_OB10: OB + port map (I=>buf_douto10, O=>dout(10)); + + Inst1_OB9: OB + port map (I=>buf_douto9, O=>dout(9)); + + Inst1_OB8: OB + port map (I=>buf_douto8, O=>dout(8)); + + Inst1_OB7: OB + port map (I=>buf_douto7, O=>dout(7)); + + Inst1_OB6: OB + port map (I=>buf_douto6, O=>dout(6)); + + Inst1_OB5: OB + port map (I=>buf_douto5, O=>dout(5)); + + Inst1_OB4: OB + port map (I=>buf_douto4, O=>dout(4)); + + Inst1_OB3: OB + port map (I=>buf_douto3, O=>dout(3)); + + Inst1_OB2: OB + port map (I=>buf_douto2, O=>dout(2)); + + Inst1_OB1: OB + port map (I=>buf_douto1, O=>dout(1)); + + Inst1_OB0: OB + port map (I=>buf_douto0, O=>dout(0)); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of odr_dbg is + for Structure + for all:OFS1P3DX use entity ecp3.OFS1P3DX(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:OB use entity ecp3.OB(V); end for; + for all:ODDRXD1 use entity ecp3.ODDRXD1(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd b/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd index 0371d02..89064ab 100644 --- a/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd @@ -59,31 +59,51 @@ architecture gbe_response_constructor_Discovery_arch of gbe_response_constructor signal state : std_logic_vector(3 downto 0); - signal test_ff : std_logic; +-- signal test_ff : std_logic; attribute syn_preserve : boolean; attribute syn_keep : boolean; attribute syn_keep of state : signal is true; attribute syn_preserve of state : signal is true; + signal stored_magic : std_logic_vector(31 downto 0); + signal stored_opcode : std_logic_vector(7 downto 0); + signal stored_random : std_logic_vector(7 downto 0); + signal stored_length : std_logic_vector(15 downto 0); + signal stored_address : std_logic_vector(31 downto 0); + signal stored_data : std_logic_vector(31 downto 0); + + signal ps_response_ready : std_logic; + signal ps_busy : std_logic; + signal tc_data_q : std_logic_vector(8 downto 0); + begin DEBUG_OUT(63 downto 32) <= (others => '0'); - DEBUG_OUT(31) <= test_ff; - DEBUG_OUT(30 downto 4) <= (others => '0'); - DEBUG_OUT(3 downto 0) <= state; + DEBUG_OUT(31 downto 28) <= state; + DEBUG_OUT(27 downto 24) <= std_logic_vector(dissect_ctr(3 downto 0)); + DEBUG_OUT(23) <= TC_RD_EN_IN; + DEBUG_OUT(22) <= ps_response_ready; + DEBUG_OUT(21) <= ps_busy; + DEBUG_OUT(20) <= PS_SELECTED_IN; + DEBUG_OUT(19) <= PS_WR_EN_IN; + DEBUG_OUT(18) <= PS_ACTIVATE_IN; + DEBUG_OUT(17 downto 9) <= tc_data_q; + DEBUG_OUT(8 downto 0) <= PS_DATA_IN; - PROC_TEST_FF: process( CLK, RESET ) - begin - if ( RESET = '1' ) then - test_ff <= '0'; - elsif( rising_edge(CLK) ) then - if( DISSECT_CS = DELAY ) then - test_ff <= not test_ff; - end if; - end if; - end process PROC_TEST_FF; +-- -- simple toggle FF for testing +-- PROC_TEST_FF: process( CLK, RESET ) +-- begin +-- if ( RESET = '1' ) then +-- test_ff <= '0'; +-- elsif( rising_edge(CLK) ) then +-- if( DISSECT_CS = DELAY ) then +-- test_ff <= not test_ff; +-- end if; +-- end if; +-- end process PROC_TEST_FF; + -- statemachine PROC_DISSECT_FSM: process( CLK, RESET ) begin if ( RESET = '1' ) then @@ -99,7 +119,7 @@ begin case DISSECT_CS is when IDLE => - state <= x"1"; + state <= x"0"; if( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then DISSECT_NS <= READ_FRAME; else @@ -107,7 +127,7 @@ begin end if; when READ_FRAME => - state <= x"2"; + state <= x"1"; -- BUG: fails on empty payload if( PS_DATA_IN(8) = '1' ) then DISSECT_NS <= DELAY; @@ -116,15 +136,16 @@ begin end if; when DELAY => + state <= x"2"; DISSECT_NS <= DECIDE; when DECIDE => state <= x"3"; -- if( saved_target_ip = MY_IP_IN ) then --- DISSECT_NS <= WAIT_FOR_LOAD; + DISSECT_NS <= WAIT_FOR_LOAD; -- -- in case the request is not for me, drop it -- else - DISSECT_NS <= IDLE; +-- DISSECT_NS <= IDLE; -- end if; when WAIT_FOR_LOAD => @@ -137,19 +158,20 @@ begin when LOAD_FRAME => state <= x"5"; - if( dissect_ctr = x"1c" ) then + if( dissect_ctr = x"14" ) then DISSECT_NS <= CLEANUP; else DISSECT_NS <= LOAD_FRAME; end if; when CLEANUP => - state <= x"e"; + state <= x"6"; DISSECT_NS <= IDLE; end case; end process PROC_DISSECT_TRANSITIONS; + -- counter for parsing received data and contructing frame PROC_DISSEC_CTR: process( CLK, RESET ) begin if ( RESET = '1' ) then @@ -172,34 +194,31 @@ begin PROC_SAVE_VALUES: process( CLK, RESET ) begin if ( RESET = '1' ) then - saved_opcode <= (others => '0'); - saved_sender_ip <= (others => '0'); - saved_target_ip <= (others => '0'); + stored_magic <= (others => '0'); + stored_opcode <= (others => '0'); + stored_random <= (others => '0'); + stored_length <= (others => '0'); + stored_address <= (others => '0'); + stored_data <= (others => '0'); elsif( rising_edge(CLK) ) then - if( DISSECT_CS = READ_FRAME ) then + if( ((DISSECT_CS = IDLE) or (DISSECT_CS = READ_FRAME)) and (PS_WR_EN_IN = '1') ) then case dissect_ctr is - - when x"06" => - saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0); - when x"07" => - saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0); - when x"0e" => - saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); - when x"0f" => - saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); - when x"10" => - saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); - when x"11" => - saved_sender_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); - when x"18" => - saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); - when x"19" => - saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0); - when x"1a" => - saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0); - when x"1b" => - saved_target_ip(31 downto 24) <= PS_DATA_IN(7 downto 0); - + when x"00" => stored_magic(7 downto 0) <= PS_DATA_IN(7 downto 0); + when x"01" => stored_magic(15 downto 8) <= PS_DATA_IN(7 downto 0); + when x"02" => stored_magic(23 downto 16) <= PS_DATA_IN(7 downto 0); + when x"03" => stored_magic(31 downto 24) <= PS_DATA_IN(7 downto 0); + when x"04" => stored_opcode <= PS_DATA_IN(7 downto 0); + when x"05" => stored_random <= PS_DATA_IN(7 downto 0); + when x"06" => stored_length(7 downto 0) <= PS_DATA_IN(7 downto 0); + when x"07" => stored_length(15 downto 8) <= PS_DATA_IN(7 downto 0); + when x"08" => stored_address(7 downto 0) <= PS_DATA_IN(7 downto 0); + when x"09" => stored_address(15 downto 8) <= PS_DATA_IN(7 downto 0); + when x"0a" => stored_address(23 downto 16) <= PS_DATA_IN(7 downto 0); + when x"0b" => stored_address(31 downto 24) <= PS_DATA_IN(7 downto 0); + when x"0c" => stored_data(7 downto 0) <= PS_DATA_IN(7 downto 0); + when x"0d" => stored_data(15 downto 8) <= PS_DATA_IN(7 downto 0); + when x"0e" => stored_data(23 downto 16) <= PS_DATA_IN(7 downto 0); + when x"0f" => stored_data(31 downto 24) <= PS_DATA_IN(7 downto 0); when others => null; end case; end if; @@ -211,69 +230,71 @@ begin if( rising_edge(CLK) ) then tc_data(8) <= '0'; tc_data(7 downto 0) <= x"00"; - if( DISSECT_CS = LOAD_FRAME ) then + if( (DISSECT_CS = LOAD_FRAME) ) then case dissect_ctr is - when x"00" => tc_data(7 downto 0) <= x"00"; -- HWTYPE - when x"01" => tc_data(7 downto 0) <= x"01"; - when x"02" => tc_data(7 downto 0) <= x"08"; -- PTYPE - when x"03" => tc_data(7 downto 0) <= x"00"; - when x"04" => tc_data(7 downto 0) <= x"06"; -- HLEN - when x"05" => tc_data(7 downto 0) <= x"04"; -- PLEN - when x"06" => tc_data(7 downto 0) <= x"00"; -- OPER - when x"07" => tc_data(7 downto 0) <= x"02"; - when x"08" => tc_data(7 downto 0) <= MY_MAC_IN(7 downto 0); -- SHA + when x"00" => tc_data(7 downto 0) <= stored_magic(7 downto 0); + when x"01" => tc_data(7 downto 0) <= stored_magic(15 downto 8); + when x"02" => tc_data(7 downto 0) <= stored_magic(23 downto 16); + when x"03" => tc_data(7 downto 0) <= stored_magic(31 downto 24); + when x"04" => tc_data(7 downto 0) <= x"1d"; -- ID + when x"05" => tc_data(7 downto 0) <= stored_random; + when x"06" => tc_data(7 downto 0) <= x"00"; + when x"07" => tc_data(7 downto 0) <= x"0c"; -- length + when x"08" => tc_data(7 downto 0) <= MY_MAC_IN(7 downto 0); when x"09" => tc_data(7 downto 0) <= MY_MAC_IN(15 downto 8); when x"0a" => tc_data(7 downto 0) <= MY_MAC_IN(23 downto 16); when x"0b" => tc_data(7 downto 0) <= MY_MAC_IN(31 downto 24); when x"0c" => tc_data(7 downto 0) <= MY_MAC_IN(39 downto 32); when x"0d" => tc_data(7 downto 0) <= MY_MAC_IN(47 downto 40); - when x"0e" => tc_data(7 downto 0) <= MY_IP_IN(7 downto 0); -- SPA - when x"0f" => tc_data(7 downto 0) <= MY_IP_IN(15 downto 8); - when x"10" => tc_data(7 downto 0) <= MY_IP_IN(23 downto 16); - when x"11" => tc_data(7 downto 0) <= MY_IP_IN(31 downto 24); - when x"12" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(7 downto 0); -- THA - when x"13" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(15 downto 8); - when x"14" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(23 downto 16); - when x"15" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(31 downto 24); - when x"16" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(39 downto 32); - when x"17" => tc_data(7 downto 0) <= PS_SRC_MAC_ADDRESS_IN(47 downto 40); - when x"18" => tc_data(7 downto 0) <= saved_sender_ip(7 downto 0); -- TPA - when x"19" => tc_data(7 downto 0) <= saved_sender_ip(15 downto 8); - when x"1a" => tc_data(7 downto 0) <= saved_sender_ip(23 downto 16); - when x"1b" => tc_data(7 downto 0) <= saved_sender_ip(31 downto 24); tc_data(8) <= '1'; + when x"0e" => tc_data(7 downto 0) <= x"00"; + when x"0f" => tc_data(7 downto 0) <= x"00"; + when x"10" => tc_data(7 downto 0) <= MY_IP_IN(7 downto 0); + when x"11" => tc_data(7 downto 0) <= MY_IP_IN(15 downto 8); + when x"12" => tc_data(7 downto 0) <= MY_IP_IN(23 downto 16); + when x"13" => tc_data(7 downto 0) <= MY_IP_IN(31 downto 24); tc_data(8) <= '1'; when others => tc_data(7 downto 0) <= x"00"; end case; - TC_DATA_OUT <= tc_data; -- delay once clock cycle +-- TC_DATA_OUT <= tc_data; -- delay once clock cycle + tc_data_q <= tc_data; -- delay once clock cycle end if; end if; end process PROC_TC_DATA; + TC_DATA_OUT <= tc_data_q; + PROC_PS_RESPONSE_SYNC: process( CLK ) begin if( rising_edge(CLK) ) then if( (DISSECT_CS = WAIT_FOR_LOAD) or (DISSECT_CS = LOAD_FRAME) or (DISSECT_CS = CLEANUP) ) then - PS_RESPONSE_READY_OUT <= '1'; +-- PS_RESPONSE_READY_OUT <= '1'; + ps_response_ready <= '1'; else - PS_RESPONSE_READY_OUT <= '0'; +-- PS_RESPONSE_READY_OUT <= '0'; + ps_response_ready <= '0'; end if; if( DISSECT_CS = IDLE ) then - PS_BUSY_OUT <= '0'; +-- PS_BUSY_OUT <= '0'; + ps_busy <= '0'; else - PS_BUSY_OUT <= '1'; +-- PS_BUSY_OUT <= '1'; + ps_busy <= '1'; end if; end if; end process PROC_PS_RESPONSE_SYNC; - TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size - TC_FRAME_TYPE_OUT <= x"0608"; + PS_RESPONSE_READY_OUT <= ps_response_ready; + PS_BUSY_OUT <= ps_busy; + + TC_FRAME_SIZE_OUT <= x"0014"; -- fixed frame size + TC_FRAME_TYPE_OUT <= x"0008"; -- byte swapped TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; - TC_DEST_IP_OUT <= x"00000000"; -- doesnt matter - TC_DEST_UDP_OUT <= x"0000"; -- doesnt matter + TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; + TC_DEST_UDP_OUT <= PS_SRC_UDP_PORT_IN; TC_SRC_MAC_OUT <= MY_MAC_IN; - TC_SRC_IP_OUT <= x"00000000"; -- doesnt matter - TC_SRC_UDP_OUT <= x"0000"; -- doesnt matter - TC_IP_PROTOCOL_OUT <= x"00"; -- doesnt matter + TC_SRC_IP_OUT <= MY_IP_IN; + TC_SRC_UDP_OUT <= x"03d9"; -- byte swapped + TC_IP_PROTOCOL_OUT <= x"11"; TC_IDENT_OUT <= (others => '0'); -- doesn't matter end gbe_response_constructor_Discovery_arch; diff --git a/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd b/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd index 39e80a0..50145c2 100644 --- a/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd @@ -405,17 +405,18 @@ begin end if; end process PS_RESPONSE_SYNC; - TC_FRAME_TYPE_OUT <= x"0008"; --- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; - TC_DEST_MAC_OUT <= saved_dst_mac; - TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; - TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8); - TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0); - TC_SRC_MAC_OUT <= MY_MAC_IN; - TC_SRC_IP_OUT <= MY_IP_IN; - TC_SRC_UDP_OUT <= x"9065"; --x"a861"; -- BUG?!? shouldn't we use the SRC UDP port? - TC_IP_PROTOCOL_OUT <= x"11"; - TC_IDENT_OUT <= x"3" & std_logic_vector(reply_ctr(11 downto 0)); + TC_FRAME_TYPE_OUT <= x"0008"; -- byte swapped +-- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; + TC_DEST_MAC_OUT <= saved_dst_mac; + TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; + TC_DEST_UDP_OUT <= PS_SRC_UDP_PORT_IN; +-- TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8); +-- TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0); + TC_SRC_MAC_OUT <= MY_MAC_IN; + TC_SRC_IP_OUT <= MY_IP_IN; + TC_SRC_UDP_OUT <= x"9065"; -- byte swapped + TC_IP_PROTOCOL_OUT <= x"11"; + TC_IDENT_OUT <= x"3" & std_logic_vector(reply_ctr(11 downto 0)); TC_FRAME_SIZE_OUT <= std_logic_vector(tx_data_ctr); -- 2.43.0